Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Feb-2026 13:50:19 5407
FPDL13_DWMZ_200600 20-Feb-2026 15:22:29 4946
SXDL31_DWAV_191800 19-Feb-2026 17:49:39 7976
SXDL31_DWAV_200800 20-Feb-2026 07:58:39 8639
SXDL31_DWAV_201800 20-Feb-2026 16:18:05 9647
SXDL31_DWAV_210800 21-Feb-2026 08:10:18 6502
SXDL31_DWAV_LATEST 21-Feb-2026 08:10:18 6502
SXDL33_DWAV_200000 20-Feb-2026 11:03:09 8185
SXDL33_DWAV_210000 21-Feb-2026 10:35:14 6594
SXDL33_DWAV_LATEST 21-Feb-2026 10:35:14 6594
ber01-FWDL39_DWMS_201230-2602201230-dsw--0-ia5 20-Feb-2026 13:26:07 1825
ber01-FWDL39_DWMS_201230_COR-2602201230-dsw--0-ia5 20-Feb-2026 14:10:21 1829
ber01-FWDL39_DWMS_211230-2602211230-dsw--0-ia5 21-Feb-2026 11:57:31 1491
ber01-VHDL13_DWEH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:17 3033
ber01-VHDL13_DWEH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:12 3647
ber01-VHDL13_DWEH_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:12 3911
ber01-VHDL13_DWEH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:16 3772
ber01-VHDL13_DWEH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:16 2995
ber01-VHDL13_DWEH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:12 2993
ber01-VHDL13_DWEH_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:13 2918
ber01-VHDL13_DWEH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:17 3436
ber01-VHDL13_DWHG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 3493
ber01-VHDL13_DWHG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:13 3567
ber01-VHDL13_DWHG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3578
ber01-VHDL13_DWHG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 3578
ber01-VHDL13_DWHG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 09:40:07 3918
ber01-VHDL13_DWHG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3095
ber01-VHDL13_DWHG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 3337
ber01-VHDL13_DWHG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3226
ber01-VHDL13_DWHG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:09 3050
ber01-VHDL13_DWHH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 3514
ber01-VHDL13_DWHH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:13 3662
ber01-VHDL13_DWHH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3696
ber01-VHDL13_DWHH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 3696
ber01-VHDL13_DWHH_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 09:42:07 3475
ber01-VHDL13_DWHH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2597
ber01-VHDL13_DWHH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2687
ber01-VHDL13_DWHH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 2665
ber01-VHDL13_DWHH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:09 2526
ber01-VHDL13_DWLG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2843
ber01-VHDL13_DWLG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3082
ber01-VHDL13_DWLG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3226
ber01-VHDL13_DWLG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3365
ber01-VHDL13_DWLG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3234
ber01-VHDL13_DWLG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2866
ber01-VHDL13_DWLG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2819
ber01-VHDL13_DWLG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2608
ber01-VHDL13_DWLH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2788
ber01-VHDL13_DWLH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2973
ber01-VHDL13_DWLH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 2912
ber01-VHDL13_DWLH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3136
ber01-VHDL13_DWLH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2978
ber01-VHDL13_DWLH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2720
ber01-VHDL13_DWLH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2585
ber01-VHDL13_DWLH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2605
ber01-VHDL13_DWLI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2727
ber01-VHDL13_DWLI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2725
ber01-VHDL13_DWLI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 2781
ber01-VHDL13_DWLI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 2998
ber01-VHDL13_DWLI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2986
ber01-VHDL13_DWLI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2499
ber01-VHDL13_DWLI_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2507
ber01-VHDL13_DWLI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2606
ber01-VHDL13_DWMG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:38:33 3863
ber01-VHDL13_DWMG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3930
ber01-VHDL13_DWMG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3208
ber01-VHDL13_DWMG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3463
ber01-VHDL13_DWMG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3752
ber01-VHDL13_DWMG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3695
ber01-VHDL13_DWMG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3952
ber01-VHDL13_DWMG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3794
ber01-VHDL13_DWMG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3489
ber01-VHDL13_DWMO_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3112
ber01-VHDL13_DWMO_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3247
ber01-VHDL13_DWMO_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3463
ber01-VHDL13_DWMO_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3850
ber01-VHDL13_DWMO_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3223
ber01-VHDL13_DWMO_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3479
ber01-VHDL13_DWMO_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3386
ber01-VHDL13_DWMO_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3013
ber01-VHDL13_DWMP_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:40:32 3038
ber01-VHDL13_DWMP_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3256
ber01-VHDL13_DWMP_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3269
ber01-VHDL13_DWMP_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:57 3524
ber01-VHDL13_DWMP_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3860
ber01-VHDL13_DWMP_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3309
ber01-VHDL13_DWMP_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3654
ber01-VHDL13_DWMP_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3483
ber01-VHDL13_DWMP_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3238
ber01-VHDL13_DWOG_190800-2602190800-dsw--0-ia5 19-Feb-2026 18:20:01 5122
ber01-VHDL13_DWOG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 15:36:06 5147
ber01-VHDL13_DWOG_191700-2602191700-dsw--0-ia5 19-Feb-2026 19:00:03 5122
ber01-VHDL13_DWOG_200300-2602200300-dsw--0-ia5 20-Feb-2026 04:00:06 5756
ber01-VHDL13_DWOG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 5163
ber01-VHDL13_DWOG_201700-2602201700-dsw--0-ia5 20-Feb-2026 19:00:06 5044
ber01-VHDL13_DWOG_210300-2602210300-dsw--0-ia5 21-Feb-2026 04:00:02 5387
ber01-VHDL13_DWOG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:39:06 4533
ber01-VHDL13_DWOH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:17 2911
ber01-VHDL13_DWOH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:12 3509
ber01-VHDL13_DWOH_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:16 3535
ber01-VHDL13_DWOH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:16 3676
ber01-VHDL13_DWOH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:16 3071
ber01-VHDL13_DWOH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:12 2927
ber01-VHDL13_DWOH_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:17 2851
ber01-VHDL13_DWOH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:17 3169
ber01-VHDL13_DWOI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:11 2704
ber01-VHDL13_DWOI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:17 3069
ber01-VHDL13_DWOI_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:16 3156
ber01-VHDL13_DWOI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:12 3419
ber01-VHDL13_DWOI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:12 2809
ber01-VHDL13_DWOI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:16 2658
ber01-VHDL13_DWOI_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:17 2582
ber01-VHDL13_DWOI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:11 2906
ber01-VHDL13_DWON_191527-2602191527-dsw--0-ia5 19-Feb-2026 15:27:22 3831
ber01-VHDL13_DWON_191819-2602191819-dsw--0-ia5 19-Feb-2026 18:19:37 3746
ber01-VHDL13_DWON_191936-2602191936-dsw--0-ia5 19-Feb-2026 19:36:33 3896
ber01-VHDL13_DWON_192238-2602192238-dsw--0-ia5 19-Feb-2026 22:38:12 3867
ber01-VHDL13_DWON_200004-2602200004-dsw--0-ia5 20-Feb-2026 00:04:26 4405
ber01-VHDL13_DWON_200144-2602200144-dsw--0-ia5 20-Feb-2026 01:44:32 4242
ber01-VHDL13_DWON_200342-2602200342-dsw--0-ia5 20-Feb-2026 03:42:47 4151
ber01-VHDL13_DWON_200628-2602200628-dsw--0-ia5 20-Feb-2026 06:28:36 4416
ber01-VHDL13_DWON_200728-2602200728-dsw--0-ia5 20-Feb-2026 07:28:47 4495
ber01-VHDL13_DWON_200808-2602200808-dsw--0-ia5 20-Feb-2026 08:08:10 4482
ber01-VHDL13_DWON_200924-2602200924-dsw--0-ia5 20-Feb-2026 09:24:32 4078
ber01-VHDL13_DWON_201256-2602201256-dsw--0-ia5 20-Feb-2026 12:56:51 3996
ber01-VHDL13_DWON_201553-2602201553-dsw--0-ia5 20-Feb-2026 15:54:02 3523
ber01-VHDL13_DWON_201752-2602201752-dsw--0-ia5 20-Feb-2026 17:52:17 3625
ber01-VHDL13_DWON_210222-2602210222-dsw--0-ia5 21-Feb-2026 02:22:37 4491
ber01-VHDL13_DWON_210334-2602210334-dsw--0-ia5 21-Feb-2026 03:34:54 4491
ber01-VHDL13_DWON_210630-2602210630-dsw--0-ia5 21-Feb-2026 06:30:27 4125
ber01-VHDL13_DWON_210710-2602210710-dsw--0-ia5 21-Feb-2026 07:11:01 3872
ber01-VHDL13_DWON_210938-2602210938-dsw--0-ia5 21-Feb-2026 09:38:38 3778
ber01-VHDL13_DWPG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2632
ber01-VHDL13_DWPG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2937
ber01-VHDL13_DWPG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3043
ber01-VHDL13_DWPG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3154
ber01-VHDL13_DWPG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2675
ber01-VHDL13_DWPG_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:08:30 2612
ber01-VHDL13_DWPG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2359
ber01-VHDL13_DWPG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2365
ber01-VHDL13_DWPG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2001
ber01-VHDL13_DWPH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2987
ber01-VHDL13_DWPH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3242
ber01-VHDL13_DWPH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3503
ber01-VHDL13_DWPH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3556
ber01-VHDL13_DWPH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3106
ber01-VHDL13_DWPH_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:08:51 3059
ber01-VHDL13_DWPH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2660
ber01-VHDL13_DWPH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2673
ber01-VHDL13_DWPH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2252
ber01-VHDL13_DWSG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 2301
ber01-VHDL13_DWSG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2792
ber01-VHDL13_DWSG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 2805
ber01-VHDL13_DWSG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 2558
ber01-VHDL13_DWSG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 12:05:37 3105
ber01-VHDL13_DWSG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3238
ber01-VHDL13_DWSG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3412
ber01-VHDL13_DWSG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3138
ber01-VHDL13_DWSG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3370
ber01-VHDL17_DWOG_201200-2602201200-dsw--0-ia5 20-Feb-2026 11:25:57 3456
ber01-VHDL17_DWOG_211200-2602211200-dsw--0-ia5 21-Feb-2026 12:35:46 3037
swis2-VHDL20_DWEG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3318
swis2-VHDL20_DWEG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3866
swis2-VHDL20_DWEG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4018
swis2-VHDL20_DWEG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4317
swis2-VHDL20_DWEG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3560
swis2-VHDL20_DWEG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3366
swis2-VHDL20_DWEG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 3174
swis2-VHDL20_DWEG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3649
swis2-VHDL20_DWEH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3482
swis2-VHDL20_DWEH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 4063
swis2-VHDL20_DWEH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4250
swis2-VHDL20_DWEH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4279
swis2-VHDL20_DWEH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3353
swis2-VHDL20_DWEH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3318
swis2-VHDL20_DWEH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 3256
swis2-VHDL20_DWEH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3941
swis2-VHDL20_DWEI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3152
swis2-VHDL20_DWEI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3458
swis2-VHDL20_DWEI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3511
swis2-VHDL20_DWEI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 3948
swis2-VHDL20_DWEI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3164
swis2-VHDL20_DWEI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2954
swis2-VHDL20_DWEI_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 2936
swis2-VHDL20_DWEI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3433
swis2-VHDL20_DWHG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3676
swis2-VHDL20_DWHG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3753
swis2-VHDL20_DWHG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3761
swis2-VHDL20_DWHG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4489
swis2-VHDL20_DWHG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3278
swis2-VHDL20_DWHG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3523
swis2-VHDL20_DWHG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3409
swis2-VHDL20_DWHG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3586
swis2-VHDL20_DWHH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3700
swis2-VHDL20_DWHH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3848
swis2-VHDL20_DWHH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3882
swis2-VHDL20_DWHH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4121
swis2-VHDL20_DWHH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 2783
swis2-VHDL20_DWHH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2873
swis2-VHDL20_DWHH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 2851
swis2-VHDL20_DWHH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3071
swis2-VHDL20_DWLG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3197
swis2-VHDL20_DWLG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3436
swis2-VHDL20_DWLG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3770
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swis2-VHDL20_DWLG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3317
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swis2-VHDL20_DWLH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3335
swis2-VHDL20_DWLH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3404
swis2-VHDL20_DWLH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3778
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swis2-VHDL20_DWLH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3139
swis2-VHDL20_DWLH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 2934
swis2-VHDL20_DWLH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3103
swis2-VHDL20_DWLI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3084
swis2-VHDL20_DWLI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3160
swis2-VHDL20_DWLI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3328
swis2-VHDL20_DWLI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3690
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swis2-VHDL20_DWLI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2939
swis2-VHDL20_DWLI_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 2851
swis2-VHDL20_DWLI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3094
swis2-VHDL20_DWMG_190400_COR-2602190400-dsw--0-ia5 20-Feb-2026 06:13:42 4844
swis2-VHDL20_DWMG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:38:33 4631
swis2-VHDL20_DWMG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 4421
swis2-VHDL20_DWMG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3678
swis2-VHDL20_DWMG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3979
swis2-VHDL20_DWMG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4523
swis2-VHDL20_DWMG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 4287
swis2-VHDL20_DWMG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:07 4557
swis2-VHDL20_DWMG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:07 4167
swis2-VHDL20_DWMG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 4021
swis2-VHDL20_DWMO_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3614
swis2-VHDL20_DWMO_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3715
swis2-VHDL20_DWMO_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4005
swis2-VHDL20_DWMO_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4566
swis2-VHDL20_DWMO_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3692
swis2-VHDL20_DWMO_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:07 4045
swis2-VHDL20_DWMO_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:07 3762
swis2-VHDL20_DWMO_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3555
swis2-VHDL20_DWMP_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:40:32 3870
swis2-VHDL20_DWMP_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3707
swis2-VHDL20_DWMP_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3742
swis2-VHDL20_DWMP_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4023
swis2-VHDL20_DWMP_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4696
swis2-VHDL20_DWMP_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3883
swis2-VHDL20_DWMP_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:07 4263
swis2-VHDL20_DWMP_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:07 3856
swis2-VHDL20_DWMP_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3776
swis2-VHDL20_DWPG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3391
swis2-VHDL20_DWPG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3280
swis2-VHDL20_DWPG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3733
swis2-VHDL20_DWPG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4207
swis2-VHDL20_DWPG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3405
swis2-VHDL20_DWPG_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:09:51 3409
swis2-VHDL20_DWPG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2865
swis2-VHDL20_DWPG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 2691
swis2-VHDL20_DWPG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 2459
swis2-VHDL20_DWPH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3739
swis2-VHDL20_DWPH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3584
swis2-VHDL20_DWPH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 4170
swis2-VHDL20_DWPH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4595
swis2-VHDL20_DWPH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3975
swis2-VHDL20_DWPH_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:10:03 3979
swis2-VHDL20_DWPH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3161
swis2-VHDL20_DWPH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 3002
swis2-VHDL20_DWPH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 2711
swis2-VHDL20_DWSG_191300-2602191300-dsw--0-ia5 19-Feb-2026 14:45:14 3073
swis2-VHDL20_DWSG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 2735
swis2-VHDL20_DWSG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3293
swis2-VHDL20_DWSG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3160
swis2-VHDL20_DWSG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3060
swis2-VHDL20_DWSG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 12:05:37 3607
swis2-VHDL20_DWSG_201300-2602201300-dsw--0-ia5 20-Feb-2026 14:45:02 3556
swis2-VHDL20_DWSG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3598
swis2-VHDL20_DWSG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3759
swis2-VHDL20_DWSG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 3493
swis2-VHDL20_DWSG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3871
wst04-VHDL20_DWEG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:11 236236
wst04-VHDL20_DWEG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 238778
wst04-VHDL20_DWEG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 238369
wst04-VHDL20_DWEG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:12 243817
wst04-VHDL20_DWEG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:11 242450
wst04-VHDL20_DWEG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:11 242118
wst04-VHDL20_DWEG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:16 240293
wst04-VHDL20_DWEG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:16 247820
wst04-VHDL20_DWEH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:11 232635
wst04-VHDL20_DWEH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 235303
wst04-VHDL20_DWEH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 234931
wst04-VHDL20_DWEH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:12 239022
wst04-VHDL20_DWEH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:11 237987
wst04-VHDL20_DWEH_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:11 238388
wst04-VHDL20_DWEH_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:22 237406
wst04-VHDL20_DWEH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:16 238338
wst04-VHDL20_DWEI_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 334421
wst04-VHDL20_DWEI_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 334812
wst04-VHDL20_DWEI_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 334671
wst04-VHDL20_DWEI_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 341769
wst04-VHDL20_DWEI_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 340687
wst04-VHDL20_DWEI_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:11 340199
wst04-VHDL20_DWEI_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:22 339643
wst04-VHDL20_DWEI_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:22 347884
wst04-VHDL20_DWHG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 323061
wst04-VHDL20_DWHG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:16 322597
wst04-VHDL20_DWHG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:11 322601
wst04-VHDL20_DWHG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 336712
wst04-VHDL20_DWHG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 335103
wst04-VHDL20_DWHG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:16 335078
wst04-VHDL20_DWHG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:12 334605
wst04-VHDL20_DWHG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:22 344945
wst04-VHDL20_DWHH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 317345
wst04-VHDL20_DWHH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:16 317649
wst04-VHDL20_DWHH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:11 317581
wst04-VHDL20_DWHH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 326594
wst04-VHDL20_DWHH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 324385
wst04-VHDL20_DWHH_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:16 323753
wst04-VHDL20_DWHH_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:12 323795
wst04-VHDL20_DWHH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:22 329073
wst04-VHDL20_DWLG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 313062
wst04-VHDL20_DWLG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 313290
wst04-VHDL20_DWLG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 314225
wst04-VHDL20_DWLG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 322350
wst04-VHDL20_DWLG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 322933
wst04-VHDL20_DWLG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:27 321997
wst04-VHDL20_DWLG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:41 321027
wst04-VHDL20_DWLG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 333608
wst04-VHDL20_DWLH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 316812
wst04-VHDL20_DWLH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 316415
wst04-VHDL20_DWLH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 316288
wst04-VHDL20_DWLH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 323994
wst04-VHDL20_DWLH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 325193
wst04-VHDL20_DWLH_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:27 324660
wst04-VHDL20_DWLH_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:41 323769
wst04-VHDL20_DWLH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 334708
wst04-VHDL20_DWLI_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 322300
wst04-VHDL20_DWLI_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 322326
wst04-VHDL20_DWLI_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 323142
wst04-VHDL20_DWLI_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 327157
wst04-VHDL20_DWLI_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 327924
wst04-VHDL20_DWLI_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:27 326627
wst04-VHDL20_DWLI_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:41 325459
wst04-VHDL20_DWLI_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 344246
wst04-VHDL20_DWMG_190800_COR-2602190800-omedes-..> 19-Feb-2026 13:38:43 547695
wst04-VHDL20_DWMG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 544105
wst04-VHDL20_DWMG_200200-2602200200-omedes--0.pdf 20-Feb-2026 06:03:07 544189
wst04-VHDL20_DWMG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:17 544886
wst04-VHDL20_DWMG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 553504
wst04-VHDL20_DWMG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 552533
wst04-VHDL20_DWMG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:22 552619
wst04-VHDL20_DWMG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:22 552165
wst04-VHDL20_DWMG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:26 567743
wst04-VHDL20_DWMO_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 431610
wst04-VHDL20_DWMO_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:12 432171
wst04-VHDL20_DWMO_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:11 433326
wst04-VHDL20_DWMO_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 443482
wst04-VHDL20_DWMO_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 442834
wst04-VHDL20_DWMO_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:16 443151
wst04-VHDL20_DWMO_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:16 443123
wst04-VHDL20_DWMO_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:26 459387
wst04-VHDL20_DWMP_190400_COR-2602190400-omedes-..> 20-Feb-2026 06:10:27 558986
wst04-VHDL20_DWMP_190800_COR-2602190800-omedes-..> 19-Feb-2026 13:40:36 561092
wst04-VHDL20_DWMP_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 558891
wst04-VHDL20_DWMP_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:12 558591
wst04-VHDL20_DWMP_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:17 560541
wst04-VHDL20_DWMP_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:26 565816
wst04-VHDL20_DWMP_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 564157
wst04-VHDL20_DWMP_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:22 563315
wst04-VHDL20_DWMP_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:26 563771
wst04-VHDL20_DWMP_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:26 573187
wst04-VHDL20_DWPG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 326161
wst04-VHDL20_DWPG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 325538
wst04-VHDL20_DWPG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:31 325833
wst04-VHDL20_DWPG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 378816
wst04-VHDL20_DWPG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 334134
wst04-VHDL20_DWPG_201800_COR-2602201800-omedes-..> 20-Feb-2026 20:09:11 334135
wst04-VHDL20_DWPG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:27 333000
wst04-VHDL20_DWPG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:31 332746
wst04-VHDL20_DWPG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:36 388286
wst04-VHDL20_DWPH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 277264
wst04-VHDL20_DWPH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 231562
wst04-VHDL20_DWPH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:31 233311
wst04-VHDL20_DWPH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 284456
wst04-VHDL20_DWPH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 284278
wst04-VHDL20_DWPH_201800_COR-2602201800-omedes-..> 20-Feb-2026 20:09:37 284671
wst04-VHDL20_DWPH_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:22 237811
wst04-VHDL20_DWPH_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:31 237020
wst04-VHDL20_DWPH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 287109
wst04-VHDL20_DWSG_191300-2602191300-omedes--0.pdf 19-Feb-2026 14:45:14 339665
wst04-VHDL20_DWSG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:11 339443
wst04-VHDL20_DWSG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:18 339995
wst04-VHDL20_DWSG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:17 339543
wst04-VHDL20_DWSG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:12 345740
wst04-VHDL20_DWSG_200800_COR-2602200800-omedes-..> 20-Feb-2026 12:05:47 346835
wst04-VHDL20_DWSG_201300-2602201300-omedes--0.pdf 20-Feb-2026 14:45:24 347811
wst04-VHDL20_DWSG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:11 347762
wst04-VHDL20_DWSG_210200-2602210200-omedes--0.pdf 21-Feb-2026 03:45:16 348182
wst04-VHDL20_DWSG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:11 347845
wst04-VHDL20_DWSG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:12 359970