Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Dec-2025 14:04:33 3968
FPDL13_DWMZ_190600 19-Dec-2025 14:43:11 7449
SXDL31_DWAV_171800 17-Dec-2025 16:15:20 6164
SXDL31_DWAV_180800 18-Dec-2025 08:12:39 8121
SXDL31_DWAV_181800 18-Dec-2025 16:45:25 9792
SXDL31_DWAV_190800 19-Dec-2025 07:41:43 7462
SXDL31_DWAV_LATEST 19-Dec-2025 07:41:43 7462
SXDL33_DWAV_180000 18-Dec-2025 12:23:53 12644
SXDL33_DWAV_190000 19-Dec-2025 11:21:29 12104
SXDL33_DWAV_LATEST 19-Dec-2025 11:21:29 12104
ber01-FWDL39_DWMS_181230-2512181230-dsw--0-ia5 18-Dec-2025 12:15:51 1419
ber01-FWDL39_DWMS_191230-2512191230-dsw--0-ia5 19-Dec-2025 11:58:36 1620
ber01-VHDL13_DWEH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:17 3210
ber01-VHDL13_DWEH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2813
ber01-VHDL13_DWEH_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:12 2720
ber01-VHDL13_DWEH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:17 2790
ber01-VHDL13_DWEH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2341
ber01-VHDL13_DWEH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:11 2182
ber01-VHDL13_DWEH_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:17 2304
ber01-VHDL13_DWEH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:17 2395
ber01-VHDL13_DWHG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 3542
ber01-VHDL13_DWHG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 3402
ber01-VHDL13_DWHG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3402
ber01-VHDL13_DWHG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:07 3430
ber01-VHDL13_DWHG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2871
ber01-VHDL13_DWHG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3257
ber01-VHDL13_DWHG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3481
ber01-VHDL13_DWHG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 2996
ber01-VHDL13_DWHH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 3077
ber01-VHDL13_DWHH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 3185
ber01-VHDL13_DWHH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3185
ber01-VHDL13_DWHH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:07 3215
ber01-VHDL13_DWHH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2645
ber01-VHDL13_DWHH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 2858
ber01-VHDL13_DWHH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 2888
ber01-VHDL13_DWHH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 2495
ber01-VHDL13_DWLG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2138
ber01-VHDL13_DWLG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2637
ber01-VHDL13_DWLG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2547
ber01-VHDL13_DWLG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2602
ber01-VHDL13_DWLG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2298
ber01-VHDL13_DWLG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2364
ber01-VHDL13_DWLG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2407
ber01-VHDL13_DWLG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2582
ber01-VHDL13_DWLH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2191
ber01-VHDL13_DWLH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2176
ber01-VHDL13_DWLH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2213
ber01-VHDL13_DWLH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2309
ber01-VHDL13_DWLH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2141
ber01-VHDL13_DWLH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2210
ber01-VHDL13_DWLH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2240
ber01-VHDL13_DWLH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2329
ber01-VHDL13_DWLI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2349
ber01-VHDL13_DWLI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2292
ber01-VHDL13_DWLI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2330
ber01-VHDL13_DWLI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2539
ber01-VHDL13_DWLI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2182
ber01-VHDL13_DWLI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2136
ber01-VHDL13_DWLI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2095
ber01-VHDL13_DWLI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2061
ber01-VHDL13_DWMG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2924
ber01-VHDL13_DWMG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3071
ber01-VHDL13_DWMG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 3258
ber01-VHDL13_DWMG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3627
ber01-VHDL13_DWMG_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:31:49 3782
ber01-VHDL13_DWMG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3130
ber01-VHDL13_DWMG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3523
ber01-VHDL13_DWMG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 3526
ber01-VHDL13_DWMG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3691
ber01-VHDL13_DWMO_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2985
ber01-VHDL13_DWMO_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3199
ber01-VHDL13_DWMO_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 3380
ber01-VHDL13_DWMO_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3711
ber01-VHDL13_DWMO_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:42:21 3937
ber01-VHDL13_DWMO_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3133
ber01-VHDL13_DWMO_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3571
ber01-VHDL13_DWMO_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 3564
ber01-VHDL13_DWMO_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3257
ber01-VHDL13_DWMP_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2600
ber01-VHDL13_DWMP_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 2817
ber01-VHDL13_DWMP_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2989
ber01-VHDL13_DWMP_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 2989
ber01-VHDL13_DWMP_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:57:17 2900
ber01-VHDL13_DWMP_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2451
ber01-VHDL13_DWMP_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3100
ber01-VHDL13_DWMP_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 2940
ber01-VHDL13_DWMP_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3065
ber01-VHDL13_DWOG_171700-2512171700-dsw--0-ia5 17-Dec-2025 19:00:03 3939
ber01-VHDL13_DWOG_180300-2512180300-dsw--0-ia5 18-Dec-2025 04:00:01 4002
ber01-VHDL13_DWOG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 4412
ber01-VHDL13_DWOG_181700-2512181700-dsw--0-ia5 18-Dec-2025 19:00:02 4110
ber01-VHDL13_DWOG_190300-2512190300-dsw--0-ia5 19-Dec-2025 04:00:06 4353
ber01-VHDL13_DWOG_190800-2512190800-dsw--0-ia5 19-Dec-2025 11:40:11 4010
ber01-VHDL13_DWOH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:17 2961
ber01-VHDL13_DWOH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2451
ber01-VHDL13_DWOH_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:16 2475
ber01-VHDL13_DWOH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:17 2674
ber01-VHDL13_DWOH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2383
ber01-VHDL13_DWOH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:11 2130
ber01-VHDL13_DWOH_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:11 2178
ber01-VHDL13_DWOH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:17 2376
ber01-VHDL13_DWOI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:11 3046
ber01-VHDL13_DWOI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2314
ber01-VHDL13_DWOI_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:16 2381
ber01-VHDL13_DWOI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:11 2589
ber01-VHDL13_DWOI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:12 2428
ber01-VHDL13_DWOI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:17 2203
ber01-VHDL13_DWOI_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:17 2137
ber01-VHDL13_DWOI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:13 2383
ber01-VHDL13_DWON_171733-2512171733-dsw--0-ia5 17-Dec-2025 17:33:32 3248
ber01-VHDL13_DWON_171741-2512171741-dsw--0-ia5 17-Dec-2025 17:42:01 3248
ber01-VHDL13_DWON_180119-2512180119-dsw--0-ia5 18-Dec-2025 01:19:22 3176
ber01-VHDL13_DWON_180624-2512180624-dsw--0-ia5 18-Dec-2025 06:24:36 3800
ber01-VHDL13_DWON_180715-2512180715-dsw--0-ia5 18-Dec-2025 07:15:43 3953
ber01-VHDL13_DWON_180903-2512180903-dsw--0-ia5 18-Dec-2025 09:03:35 3975
ber01-VHDL13_DWON_181551-2512181551-dsw--0-ia5 18-Dec-2025 15:51:41 3492
ber01-VHDL13_DWON_181731-2512181731-dsw--0-ia5 18-Dec-2025 17:31:45 3624
ber01-VHDL13_DWON_190152-2512190152-dsw--0-ia5 19-Dec-2025 01:52:31 4006
ber01-VHDL13_DWON_190333-2512190333-dsw--0-ia5 19-Dec-2025 03:33:55 4006
ber01-VHDL13_DWON_190627-2512190627-dsw--0-ia5 19-Dec-2025 06:27:27 4028
ber01-VHDL13_DWON_190709-2512190709-dsw--0-ia5 19-Dec-2025 07:09:26 4298
ber01-VHDL13_DWON_191125-2512191125-dsw--0-ia5 19-Dec-2025 11:25:46 4282
ber01-VHDL13_DWON_191139-2512191139-dsw--0-ia5 19-Dec-2025 11:39:43 4282
ber01-VHDL13_DWON_191504-2512191504-dsw--0-ia5 19-Dec-2025 15:04:42 3217
ber01-VHDL13_DWPG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 1859
ber01-VHDL13_DWPG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 1818
ber01-VHDL13_DWPG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 1913
ber01-VHDL13_DWPG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 1909
ber01-VHDL13_DWPG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1788
ber01-VHDL13_DWPG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 1803
ber01-VHDL13_DWPG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 1843
ber01-VHDL13_DWPG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 1865
ber01-VHDL13_DWPH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2086
ber01-VHDL13_DWPH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2106
ber01-VHDL13_DWPH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2082
ber01-VHDL13_DWPH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 1895
ber01-VHDL13_DWPH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1876
ber01-VHDL13_DWPH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 1910
ber01-VHDL13_DWPH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2032
ber01-VHDL13_DWPH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 1852
ber01-VHDL13_DWSG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 3064
ber01-VHDL13_DWSG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3509
ber01-VHDL13_DWSG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:06 3552
ber01-VHDL13_DWSG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3552
ber01-VHDL13_DWSG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 3203
ber01-VHDL13_DWSG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3511
ber01-VHDL13_DWSG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3523
ber01-VHDL13_DWSG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 3524
ber01-VHDL17_DWOG_181200-2512181200-dsw--0-ia5 18-Dec-2025 12:55:31 3733
ber01-VHDL17_DWOG_191200-2512191200-dsw--0-ia5 19-Dec-2025 12:58:06 3449
swis2-VHDL20_DWEG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 3290
swis2-VHDL20_DWEG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2730
swis2-VHDL20_DWEG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 2795
swis2-VHDL20_DWEG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3149
swis2-VHDL20_DWEG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2709
swis2-VHDL20_DWEG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2406
swis2-VHDL20_DWEG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2505
swis2-VHDL20_DWEG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2854
swis2-VHDL20_DWEH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3570
swis2-VHDL20_DWEH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 3137
swis2-VHDL20_DWEH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3052
swis2-VHDL20_DWEH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3290
swis2-VHDL20_DWEH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2695
swis2-VHDL20_DWEH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2503
swis2-VHDL20_DWEH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2636
swis2-VHDL20_DWEH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 2898
swis2-VHDL20_DWEI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3400
swis2-VHDL20_DWEI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2606
swis2-VHDL20_DWEI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 2733
swis2-VHDL20_DWEI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3112
swis2-VHDL20_DWEI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2780
swis2-VHDL20_DWEI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2496
swis2-VHDL20_DWEI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2494
swis2-VHDL20_DWEI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2908
swis2-VHDL20_DWHG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3725
swis2-VHDL20_DWHG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3588
swis2-VHDL20_DWHG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3585
swis2-VHDL20_DWHG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3964
swis2-VHDL20_DWHG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3054
swis2-VHDL20_DWHG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3443
swis2-VHDL20_DWHG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3664
swis2-VHDL20_DWHG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3527
swis2-VHDL20_DWHH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3263
swis2-VHDL20_DWHH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3371
swis2-VHDL20_DWHH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3371
swis2-VHDL20_DWHH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3758
swis2-VHDL20_DWHH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2831
swis2-VHDL20_DWHH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3044
swis2-VHDL20_DWHH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3074
swis2-VHDL20_DWHH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3038
swis2-VHDL20_DWLG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2480
swis2-VHDL20_DWLG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 3084
swis2-VHDL20_DWLG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2980
swis2-VHDL20_DWLG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 3149
swis2-VHDL20_DWLG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2756
swis2-VHDL20_DWLG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2825
swis2-VHDL20_DWLG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2745
swis2-VHDL20_DWLG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3062
swis2-VHDL20_DWLH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 2540
swis2-VHDL20_DWLH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2528
swis2-VHDL20_DWLH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2559
swis2-VHDL20_DWLH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2801
swis2-VHDL20_DWLH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2487
swis2-VHDL20_DWLH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2559
swis2-VHDL20_DWLH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2585
swis2-VHDL20_DWLH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2820
swis2-VHDL20_DWLI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2693
swis2-VHDL20_DWLI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2639
swis2-VHDL20_DWLI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2671
swis2-VHDL20_DWLI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 3096
swis2-VHDL20_DWLI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2598
swis2-VHDL20_DWLI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2555
swis2-VHDL20_DWLI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2435
swis2-VHDL20_DWLI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2542
swis2-VHDL20_DWMG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3353
swis2-VHDL20_DWMG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3500
swis2-VHDL20_DWMG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3684
swis2-VHDL20_DWMG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4264
swis2-VHDL20_DWMG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3556
swis2-VHDL20_DWMG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 3934
swis2-VHDL20_DWMG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3952
swis2-VHDL20_DWMG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 4573
swis2-VHDL20_DWMO_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3417
swis2-VHDL20_DWMO_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3642
swis2-VHDL20_DWMO_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3806
swis2-VHDL20_DWMO_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4344
swis2-VHDL20_DWMO_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:43:07 4570
swis2-VHDL20_DWMO_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3552
swis2-VHDL20_DWMO_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 4001
swis2-VHDL20_DWMO_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3983
swis2-VHDL20_DWMO_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 4145
swis2-VHDL20_DWMP_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3023
swis2-VHDL20_DWMP_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3251
swis2-VHDL20_DWMP_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3417
swis2-VHDL20_DWMP_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 3635
swis2-VHDL20_DWMP_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:58:07 3546
swis2-VHDL20_DWMP_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2872
swis2-VHDL20_DWMP_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 3528
swis2-VHDL20_DWMP_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3368
swis2-VHDL20_DWMP_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 3711
swis2-VHDL20_DWPG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2321
swis2-VHDL20_DWPG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2150
swis2-VHDL20_DWPG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2239
swis2-VHDL20_DWPG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2368
swis2-VHDL20_DWPG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2247
swis2-VHDL20_DWPG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2132
swis2-VHDL20_DWPG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2169
swis2-VHDL20_DWPG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2324
swis2-VHDL20_DWPH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 2548
swis2-VHDL20_DWPH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2437
swis2-VHDL20_DWPH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2410
swis2-VHDL20_DWPH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2354
swis2-VHDL20_DWPH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2335
swis2-VHDL20_DWPH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2238
swis2-VHDL20_DWPH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2360
swis2-VHDL20_DWPH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2311
swis2-VHDL20_DWSG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3506
swis2-VHDL20_DWSG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 3910
swis2-VHDL20_DWSG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:06 3917
swis2-VHDL20_DWSG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4109
swis2-VHDL20_DWSG_181300-2512181300-dsw--0-ia5 18-Dec-2025 14:45:04 3632
swis2-VHDL20_DWSG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3645
swis2-VHDL20_DWSG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3942
swis2-VHDL20_DWSG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3963
swis2-VHDL20_DWSG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 4194
swis2-VHDL20_DWSG_191300-2512191300-dsw--0-ia5 19-Dec-2025 14:45:09 3404
wst04-VHDL20_DWEG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 220367
wst04-VHDL20_DWEG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 221438
wst04-VHDL20_DWEG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:26 220953
wst04-VHDL20_DWEG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 222787
wst04-VHDL20_DWEG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 220825
wst04-VHDL20_DWEG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 220578
wst04-VHDL20_DWEG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:27 220112
wst04-VHDL20_DWEG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:23 222618
wst04-VHDL20_DWEH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 220785
wst04-VHDL20_DWEH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:16 221769
wst04-VHDL20_DWEH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 221164
wst04-VHDL20_DWEH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:21 221705
wst04-VHDL20_DWEH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 220219
wst04-VHDL20_DWEH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 220709
wst04-VHDL20_DWEH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:21 220462
wst04-VHDL20_DWEH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:23 221879
wst04-VHDL20_DWEI_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 302436
wst04-VHDL20_DWEI_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 302670
wst04-VHDL20_DWEI_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:26 303109
wst04-VHDL20_DWEI_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 301082
wst04-VHDL20_DWEI_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 300842
wst04-VHDL20_DWEI_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 300189
wst04-VHDL20_DWEI_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:27 300114
wst04-VHDL20_DWEI_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 305476
wst04-VHDL20_DWHG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 296562
wst04-VHDL20_DWHG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 296600
wst04-VHDL20_DWHG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:12 296584
wst04-VHDL20_DWHG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:21 297124
wst04-VHDL20_DWHG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 295720
wst04-VHDL20_DWHG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 295883
wst04-VHDL20_DWHG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:12 296270
wst04-VHDL20_DWHG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 300688
wst04-VHDL20_DWHH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 288157
wst04-VHDL20_DWHH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 288645
wst04-VHDL20_DWHH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:12 288655
wst04-VHDL20_DWHH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:17 288739
wst04-VHDL20_DWHH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 288719
wst04-VHDL20_DWHH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 288292
wst04-VHDL20_DWHH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:12 288050
wst04-VHDL20_DWHH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 305596
wst04-VHDL20_DWLG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 293092
wst04-VHDL20_DWLG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 293800
wst04-VHDL20_DWLG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 293801
wst04-VHDL20_DWLG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 287362
wst04-VHDL20_DWLG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 287061
wst04-VHDL20_DWLG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 287364
wst04-VHDL20_DWLG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 286426
wst04-VHDL20_DWLG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 291268
wst04-VHDL20_DWLH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 294406
wst04-VHDL20_DWLH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 294188
wst04-VHDL20_DWLH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 294165
wst04-VHDL20_DWLH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 287324
wst04-VHDL20_DWLH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 287587
wst04-VHDL20_DWLH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 287484
wst04-VHDL20_DWLH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 287114
wst04-VHDL20_DWLH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 293426
wst04-VHDL20_DWLI_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 295474
wst04-VHDL20_DWLI_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 295457
wst04-VHDL20_DWLI_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 295862
wst04-VHDL20_DWLI_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 289415
wst04-VHDL20_DWLI_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 289298
wst04-VHDL20_DWLI_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 289043
wst04-VHDL20_DWLI_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 287819
wst04-VHDL20_DWLI_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 295173
wst04-VHDL20_DWMG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 486420
wst04-VHDL20_DWMG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 486636
wst04-VHDL20_DWMG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 487044
wst04-VHDL20_DWMG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 482750
wst04-VHDL20_DWMG_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:33:12 482709
wst04-VHDL20_DWMG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 480834
wst04-VHDL20_DWMG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 481433
wst04-VHDL20_DWMG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:23 481629
wst04-VHDL20_DWMG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 476673
wst04-VHDL20_DWMO_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 395401
wst04-VHDL20_DWMO_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:18 395411
wst04-VHDL20_DWMO_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 396167
wst04-VHDL20_DWMO_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 392061
wst04-VHDL20_DWMO_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:42:53 391331
wst04-VHDL20_DWMO_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 390194
wst04-VHDL20_DWMO_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 391039
wst04-VHDL20_DWMO_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:17 391874
wst04-VHDL20_DWMO_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:11 395498
wst04-VHDL20_DWMP_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 509725
wst04-VHDL20_DWMP_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:18 508030
wst04-VHDL20_DWMP_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 510215
wst04-VHDL20_DWMP_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:17 505336
wst04-VHDL20_DWMP_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:57:47 504582
wst04-VHDL20_DWMP_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 503091
wst04-VHDL20_DWMP_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 503760
wst04-VHDL20_DWMP_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:23 504529
wst04-VHDL20_DWMP_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 491753
wst04-VHDL20_DWPG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 291984
wst04-VHDL20_DWPG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 291427
wst04-VHDL20_DWPG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:31 291497
wst04-VHDL20_DWPG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 336945
wst04-VHDL20_DWPG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 292042
wst04-VHDL20_DWPG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 291881
wst04-VHDL20_DWPG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:31 292460
wst04-VHDL20_DWPG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 347658
wst04-VHDL20_DWPH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 259833
wst04-VHDL20_DWPH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 214898
wst04-VHDL20_DWPH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:31 215224
wst04-VHDL20_DWPH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 259709
wst04-VHDL20_DWPH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 259580
wst04-VHDL20_DWPH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 214800
wst04-VHDL20_DWPH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:31 215275
wst04-VHDL20_DWPH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 266156
wst04-VHDL20_DWSG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 317688
wst04-VHDL20_DWSG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:16 318050
wst04-VHDL20_DWSG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:16 318054
wst04-VHDL20_DWSG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 313018
wst04-VHDL20_DWSG_181300-2512181300-omedes--0.pdf 18-Dec-2025 14:45:12 312687
wst04-VHDL20_DWSG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 313445
wst04-VHDL20_DWSG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 313201
wst04-VHDL20_DWSG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:17 313407
wst04-VHDL20_DWSG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:11 306268
wst04-VHDL20_DWSG_191300-2512191300-omedes--0.pdf 19-Dec-2025 14:45:12 305640