Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Nov-2025 14:43:33 4964
FPDL13_DWMZ_260600 26-Nov-2025 15:57:41 6574
SXDL31_DWAV_250800 25-Nov-2025 07:58:39 16584
SXDL31_DWAV_251800 25-Nov-2025 17:47:59 7265
SXDL31_DWAV_260800 26-Nov-2025 08:21:49 7855
SXDL31_DWAV_261800 26-Nov-2025 16:37:51 12505
SXDL31_DWAV_LATEST 26-Nov-2025 16:37:51 12505
SXDL33_DWAV_250000 25-Nov-2025 10:53:29 5525
SXDL33_DWAV_260000 26-Nov-2025 09:52:15 11968
SXDL33_DWAV_LATEST 26-Nov-2025 09:52:15 11968
ber01-FWDL39_DWMS_251230-2511251230-dsw--0-ia5 25-Nov-2025 12:06:17 1547
ber01-FWDL39_DWMS_261230-2511261230-dsw--0-ia5 26-Nov-2025 12:39:31 1494
ber01-VHDL13_DWEH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:28:16 2705
ber01-VHDL13_DWEH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:28:11 2962
ber01-VHDL13_DWEH_250400-2511250400-dsw--0-ia5 25-Nov-2025 05:58:15 2929
ber01-VHDL13_DWEH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:28:17 2954
ber01-VHDL13_DWEH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:28:17 2726
ber01-VHDL13_DWEH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:28:11 2868
ber01-VHDL13_DWEH_260400-2511260400-dsw--0-ia5 26-Nov-2025 05:58:17 2880
ber01-VHDL13_DWEH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:28:16 2815
ber01-VHDL13_DWHG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:06 2915
ber01-VHDL13_DWHG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:08 3335
ber01-VHDL13_DWHG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:11 3335
ber01-VHDL13_DWHG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:08 3232
ber01-VHDL13_DWHG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:06 2953
ber01-VHDL13_DWHG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 2870
ber01-VHDL13_DWHG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:07 3134
ber01-VHDL13_DWHG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:08 3496
ber01-VHDL13_DWHH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:06 2724
ber01-VHDL13_DWHH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:08 2965
ber01-VHDL13_DWHH_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:11 3079
ber01-VHDL13_DWHH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:08 2855
ber01-VHDL13_DWHH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:06 2722
ber01-VHDL13_DWHH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 2803
ber01-VHDL13_DWHH_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:07 3030
ber01-VHDL13_DWHH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:08 3337
ber01-VHDL13_DWLG_241800-2511241800-dsw--0-ia5 24-Nov-2025 20:08:36 2416
ber01-VHDL13_DWLG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 2561
ber01-VHDL13_DWLG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 2681
ber01-VHDL13_DWLG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2984
ber01-VHDL13_DWLG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 3010
ber01-VHDL13_DWLG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:01 3409
ber01-VHDL13_DWLG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:01 3492
ber01-VHDL13_DWLG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 3557
ber01-VHDL13_DWLH_241800-2511241800-dsw--0-ia5 24-Nov-2025 20:08:22 2489
ber01-VHDL13_DWLH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 2741
ber01-VHDL13_DWLH_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 2325
ber01-VHDL13_DWLH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2323
ber01-VHDL13_DWLH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2157
ber01-VHDL13_DWLH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:01 2480
ber01-VHDL13_DWLH_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:01 2759
ber01-VHDL13_DWLH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 2691
ber01-VHDL13_DWLI_241800-2511241800-dsw--0-ia5 24-Nov-2025 20:08:52 2473
ber01-VHDL13_DWLI_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 2793
ber01-VHDL13_DWLI_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 2365
ber01-VHDL13_DWLI_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2276
ber01-VHDL13_DWLI_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2244
ber01-VHDL13_DWLI_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:01 2633
ber01-VHDL13_DWLI_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:01 2936
ber01-VHDL13_DWLI_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 2855
ber01-VHDL13_DWMG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:02 2642
ber01-VHDL13_DWMG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 3915
ber01-VHDL13_DWMG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 3817
ber01-VHDL13_DWMG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 3554
ber01-VHDL13_DWMG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 3447
ber01-VHDL13_DWMG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 3440
ber01-VHDL13_DWMG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:03 3440
ber01-VHDL13_DWMG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 4038
ber01-VHDL13_DWMO_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:02 3513
ber01-VHDL13_DWMO_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 3491
ber01-VHDL13_DWMO_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 3207
ber01-VHDL13_DWMO_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2747
ber01-VHDL13_DWMO_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2820
ber01-VHDL13_DWMO_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 3108
ber01-VHDL13_DWMO_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:03 3108
ber01-VHDL13_DWMO_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 3693
ber01-VHDL13_DWMP_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:02 3906
ber01-VHDL13_DWMP_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 3781
ber01-VHDL13_DWMP_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 3752
ber01-VHDL13_DWMP_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 3636
ber01-VHDL13_DWMP_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 3422
ber01-VHDL13_DWMP_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 3535
ber01-VHDL13_DWMP_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:03 3535
ber01-VHDL13_DWMP_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 3605
ber01-VHDL13_DWOG_241700-2511241700-dsw--0-ia5 24-Nov-2025 19:00:05 4475
ber01-VHDL13_DWOG_250300-2511250300-dsw--0-ia5 25-Nov-2025 04:00:03 4851
ber01-VHDL13_DWOG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 4740
ber01-VHDL13_DWOG_250800_COR-2511250800-dsw--0-ia5 25-Nov-2025 15:47:21 4411
ber01-VHDL13_DWOG_251700-2511251700-dsw--0-ia5 25-Nov-2025 19:00:01 4254
ber01-VHDL13_DWOG_260300-2511260300-dsw--0-ia5 26-Nov-2025 04:00:02 4959
ber01-VHDL13_DWOG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 4849
ber01-VHDL13_DWOH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:28:16 2771
ber01-VHDL13_DWOH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:28:15 3035
ber01-VHDL13_DWOH_250400-2511250400-dsw--0-ia5 25-Nov-2025 05:58:15 2887
ber01-VHDL13_DWOH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:28:17 2858
ber01-VHDL13_DWOH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:28:17 2771
ber01-VHDL13_DWOH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:28:11 2710
ber01-VHDL13_DWOH_260400-2511260400-dsw--0-ia5 26-Nov-2025 05:58:11 2888
ber01-VHDL13_DWOH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:28:16 2998
ber01-VHDL13_DWOI_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:28:12 2603
ber01-VHDL13_DWOI_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:28:11 2756
ber01-VHDL13_DWOI_250400-2511250400-dsw--0-ia5 25-Nov-2025 05:58:15 2678
ber01-VHDL13_DWOI_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:28:11 2561
ber01-VHDL13_DWOI_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:28:17 2537
ber01-VHDL13_DWOI_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:28:16 2602
ber01-VHDL13_DWOI_260400-2511260400-dsw--0-ia5 26-Nov-2025 05:58:17 2688
ber01-VHDL13_DWOI_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:28:12 2690
ber01-VHDL13_DWON_242024-2511242024-dsw--0-ia5 24-Nov-2025 20:24:22 3497
ber01-VHDL13_DWON_250017-2511250017-dsw--0-ia5 25-Nov-2025 00:17:32 3727
ber01-VHDL13_DWON_250349-2511250349-dsw--0-ia5 25-Nov-2025 03:49:02 3727
ber01-VHDL13_DWON_250629-2511250629-dsw--0-ia5 25-Nov-2025 06:29:42 3909
ber01-VHDL13_DWON_250653-2511250653-dsw--0-ia5 25-Nov-2025 06:53:42 3893
ber01-VHDL13_DWON_250906-2511250906-dsw--0-ia5 25-Nov-2025 09:06:56 3934
ber01-VHDL13_DWON_251546-2511251546-dsw--0-ia5 25-Nov-2025 15:46:41 3218
ber01-VHDL13_DWON_251807-2511251807-dsw--0-ia5 25-Nov-2025 18:07:17 3336
ber01-VHDL13_DWON_260207-2511260207-dsw--0-ia5 26-Nov-2025 02:07:47 4059
ber01-VHDL13_DWON_260342-2511260342-dsw--0-ia5 26-Nov-2025 03:42:57 4059
ber01-VHDL13_DWON_260631-2511260631-dsw--0-ia5 26-Nov-2025 06:31:07 4059
ber01-VHDL13_DWON_260707-2511260707-dsw--0-ia5 26-Nov-2025 07:07:11 3915
ber01-VHDL13_DWON_260709-2511260709-dsw--0-ia5 26-Nov-2025 07:10:08 3798
ber01-VHDL13_DWON_260935-2511260935-dsw--0-ia5 26-Nov-2025 09:36:01 3798
ber01-VHDL13_DWON_261229-2511261229-dsw--0-ia5 26-Nov-2025 12:29:51 3798
ber01-VHDL13_DWON_261632-2511261632-dsw--0-ia5 26-Nov-2025 16:32:30 3801
ber01-VHDL13_DWON_261734-2511261734-dsw--0-ia5 26-Nov-2025 17:34:54 3862
ber01-VHDL13_DWPG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:06 2279
ber01-VHDL13_DWPG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:59:41 2932
ber01-VHDL13_DWPG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 2817
ber01-VHDL13_DWPG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2850
ber01-VHDL13_DWPG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2281
ber01-VHDL13_DWPG_251800_COR-2511251800-dsw--0-ia5 25-Nov-2025 21:57:07 2743
ber01-VHDL13_DWPG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:01 3105
ber01-VHDL13_DWPG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:01 2971
ber01-VHDL13_DWPG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 2995
ber01-VHDL13_DWPH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:06 2262
ber01-VHDL13_DWPH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 2765
ber01-VHDL13_DWPH_250200_COR-2511250200-dsw--0-ia5 25-Nov-2025 04:00:11 2774
ber01-VHDL13_DWPH_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:01 2563
ber01-VHDL13_DWPH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 2725
ber01-VHDL13_DWPH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2264
ber01-VHDL13_DWPH_251800_COR-2511251800-dsw--0-ia5 25-Nov-2025 21:57:27 2630
ber01-VHDL13_DWPH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:01 3043
ber01-VHDL13_DWPH_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:01 2907
ber01-VHDL13_DWPH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 2999
ber01-VHDL13_DWSG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:30:02 2676
ber01-VHDL13_DWSG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:30:01 3542
ber01-VHDL13_DWSG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:07 3786
ber01-VHDL13_DWSG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:30:01 3609
ber01-VHDL13_DWSG_250800_COR-2511250800-dsw--0-ia5 25-Nov-2025 10:15:53 3468
ber01-VHDL13_DWSG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:30:02 2890
ber01-VHDL13_DWSG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:30:07 3161
ber01-VHDL13_DWSG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:07 3082
ber01-VHDL13_DWSG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:30:04 3160
ber01-VHDL17_DWOG_251200-2511251200-dsw--0-ia5 25-Nov-2025 12:16:11 3659
ber01-VHDL17_DWOG_261200-2511261200-dsw--0-ia5 26-Nov-2025 11:54:07 3144
swis2-VHDL20_DWEG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:06 3451
swis2-VHDL20_DWEG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:07 3452
swis2-VHDL20_DWEG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:15:06 3348
swis2-VHDL20_DWEG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:01 3580
swis2-VHDL20_DWEG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 3237
swis2-VHDL20_DWEG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:06 3082
swis2-VHDL20_DWEG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:15:07 3289
swis2-VHDL20_DWEG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 3740
swis2-VHDL20_DWEH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:06 3201
swis2-VHDL20_DWEH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:07 3424
swis2-VHDL20_DWEH_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:15:06 3402
swis2-VHDL20_DWEH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:01 3701
swis2-VHDL20_DWEH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 3242
swis2-VHDL20_DWEH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:06 3281
swis2-VHDL20_DWEH_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:15:07 3293
swis2-VHDL20_DWEH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 3471
swis2-VHDL20_DWEI_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:06 3095
swis2-VHDL20_DWEI_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:07 3188
swis2-VHDL20_DWEI_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:15:06 3170
swis2-VHDL20_DWEI_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:01 3330
swis2-VHDL20_DWEI_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 3028
swis2-VHDL20_DWEI_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:06 2985
swis2-VHDL20_DWEI_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:15:07 3120
swis2-VHDL20_DWEI_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 3367
swis2-VHDL20_DWHG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:06 3098
swis2-VHDL20_DWHG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:01 3521
swis2-VHDL20_DWHG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:11 3518
swis2-VHDL20_DWHG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:06 3839
swis2-VHDL20_DWHG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 3136
swis2-VHDL20_DWHG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:02 3056
swis2-VHDL20_DWHG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:07 3317
swis2-VHDL20_DWHG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 4111
swis2-VHDL20_DWHH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:06 2910
swis2-VHDL20_DWHH_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:01 3151
swis2-VHDL20_DWHH_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:11 3265
swis2-VHDL20_DWHH_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:06 3445
swis2-VHDL20_DWHH_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 2908
swis2-VHDL20_DWHH_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:02 2989
swis2-VHDL20_DWHH_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:07 3216
swis2-VHDL20_DWHH_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 3958
swis2-VHDL20_DWLG_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:04 2846
swis2-VHDL20_DWLG_250200-2511250200-dsw--0-ia5 25-Nov-2025 03:45:01 3015
swis2-VHDL20_DWLG_250400-2511250400-dsw--0-ia5 25-Nov-2025 06:00:11 3086
swis2-VHDL20_DWLG_250800-2511250800-dsw--0-ia5 25-Nov-2025 09:45:01 3695
swis2-VHDL20_DWLG_251800-2511251800-dsw--0-ia5 25-Nov-2025 19:45:06 3498
swis2-VHDL20_DWLG_260200-2511260200-dsw--0-ia5 26-Nov-2025 03:45:06 3922
swis2-VHDL20_DWLG_260400-2511260400-dsw--0-ia5 26-Nov-2025 06:00:11 3895
swis2-VHDL20_DWLG_260800-2511260800-dsw--0-ia5 26-Nov-2025 09:45:02 4175
swis2-VHDL20_DWLH_241800-2511241800-dsw--0-ia5 24-Nov-2025 19:45:04 2926
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