Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Feb-2026 16:09:35 7699
FPDL13_DWMZ_150600 15-Feb-2026 13:43:43 4148
SXDL31_DWAV_131800 13-Feb-2026 17:10:35 7448
SXDL31_DWAV_140800 14-Feb-2026 09:32:22 10143
SXDL31_DWAV_141800 14-Feb-2026 17:10:19 8617
SXDL31_DWAV_150800 15-Feb-2026 09:05:14 11120
SXDL31_DWAV_LATEST 15-Feb-2026 09:05:14 11120
SXDL33_DWAV_140000 14-Feb-2026 10:12:10 10801
SXDL33_DWAV_150000 15-Feb-2026 11:19:04 6739
SXDL33_DWAV_LATEST 15-Feb-2026 11:19:04 6739
ber01-FWDL39_DWMS_141230-2602141230-dsw--0-ia5 14-Feb-2026 12:38:07 1904
ber01-FWDL39_DWMS_151230-2602151230-dsw--0-ia5 15-Feb-2026 13:05:07 1976
ber01-VHDL13_DWEH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:17 3512
ber01-VHDL13_DWEH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:12 3830
ber01-VHDL13_DWEH_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:12 3914
ber01-VHDL13_DWEH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:28:17 4139
ber01-VHDL13_DWEH_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 09:37:16 4143
ber01-VHDL13_DWEH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:28:16 3776
ber01-VHDL13_DWEH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:28:17 4093
ber01-VHDL13_DWEH_150400-2602150400-dsw--0-ia5 15-Feb-2026 05:58:15 4048
ber01-VHDL13_DWEH_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:11 4665
ber01-VHDL13_DWEH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:28:17 4673
ber01-VHDL13_DWHG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2881
ber01-VHDL13_DWHG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3662
ber01-VHDL13_DWHG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3662
ber01-VHDL13_DWHG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:08 3471
ber01-VHDL13_DWHG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3820
ber01-VHDL13_DWHG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 4224
ber01-VHDL13_DWHG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 4224
ber01-VHDL13_DWHG_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 07:08:46 4228
ber01-VHDL13_DWHG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:08 4111
ber01-VHDL13_DWHH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2830
ber01-VHDL13_DWHH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3251
ber01-VHDL13_DWHH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3250
ber01-VHDL13_DWHH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:07 3283
ber01-VHDL13_DWHH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3243
ber01-VHDL13_DWHH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 3760
ber01-VHDL13_DWHH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3760
ber01-VHDL13_DWHH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:08 3591
ber01-VHDL13_DWLG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 3113
ber01-VHDL13_DWLG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3331
ber01-VHDL13_DWLG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3269
ber01-VHDL13_DWLG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3482
ber01-VHDL13_DWLG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3219
ber01-VHDL13_DWLG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 3304
ber01-VHDL13_DWLG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3413
ber01-VHDL13_DWLG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 3767
ber01-VHDL13_DWLH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2936
ber01-VHDL13_DWLH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3098
ber01-VHDL13_DWLH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3123
ber01-VHDL13_DWLH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3306
ber01-VHDL13_DWLH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3110
ber01-VHDL13_DWLH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 3049
ber01-VHDL13_DWLH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3264
ber01-VHDL13_DWLH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 3597
ber01-VHDL13_DWLI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2996
ber01-VHDL13_DWLI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3136
ber01-VHDL13_DWLI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3079
ber01-VHDL13_DWLI_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3178
ber01-VHDL13_DWLI_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 2873
ber01-VHDL13_DWLI_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 2877
ber01-VHDL13_DWLI_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3095
ber01-VHDL13_DWLI_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 3105
ber01-VHDL13_DWMG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2880
ber01-VHDL13_DWMG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3154
ber01-VHDL13_DWMG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3274
ber01-VHDL13_DWMG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3548
ber01-VHDL13_DWMG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3344
ber01-VHDL13_DWMG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:01 3423
ber01-VHDL13_DWMG_150200_COR-2602150200-dsw--0-ia5 15-Feb-2026 03:48:17 4253
ber01-VHDL13_DWMG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3994
ber01-VHDL13_DWMG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 4329
ber01-VHDL13_DWMO_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2631
ber01-VHDL13_DWMO_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 2774
ber01-VHDL13_DWMO_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2822
ber01-VHDL13_DWMO_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3130
ber01-VHDL13_DWMO_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3078
ber01-VHDL13_DWMO_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:01 3391
ber01-VHDL13_DWMO_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3661
ber01-VHDL13_DWMO_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 3641
ber01-VHDL13_DWMO_150800_COR-2602150800-dsw--0-ia5 15-Feb-2026 09:42:28 4102
ber01-VHDL13_DWMP_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2893
ber01-VHDL13_DWMP_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3249
ber01-VHDL13_DWMP_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3256
ber01-VHDL13_DWMP_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3480
ber01-VHDL13_DWMP_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 3381
ber01-VHDL13_DWMP_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:01 3586
ber01-VHDL13_DWMP_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 4105
ber01-VHDL13_DWMP_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 4464
ber01-VHDL13_DWOG_131700-2602131700-dsw--0-ia5 13-Feb-2026 19:00:02 4517
ber01-VHDL13_DWOG_131700_COR-2602131700-dsw--0-ia5 13-Feb-2026 21:30:06 5155
ber01-VHDL13_DWOG_140300-2602140300-dsw--0-ia5 14-Feb-2026 04:00:02 5484
ber01-VHDL13_DWOG_140300_COR-2602140300-dsw--0-ia5 14-Feb-2026 07:08:11 5051
ber01-VHDL13_DWOG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:08 5538
ber01-VHDL13_DWOG_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 15:15:08 5112
ber01-VHDL13_DWOG_141700-2602141700-dsw--0-ia5 14-Feb-2026 19:00:02 5536
ber01-VHDL13_DWOG_141700_COR-2602141700-dsw--0-ia5 14-Feb-2026 21:55:37 6205
ber01-VHDL13_DWOG_150300-2602150300-dsw--0-ia5 15-Feb-2026 04:00:01 6302
ber01-VHDL13_DWOG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:08 6267
ber01-VHDL13_DWOH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:17 3429
ber01-VHDL13_DWOH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:12 3756
ber01-VHDL13_DWOH_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:16 3852
ber01-VHDL13_DWOH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:28:17 4008
ber01-VHDL13_DWOH_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 09:38:39 4083
ber01-VHDL13_DWOH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:28:16 3479
ber01-VHDL13_DWOH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:28:11 3937
ber01-VHDL13_DWOH_150400-2602150400-dsw--0-ia5 15-Feb-2026 05:58:15 3895
ber01-VHDL13_DWOH_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:11 4349
ber01-VHDL13_DWOH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:28:17 4239
ber01-VHDL13_DWOI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:11 3472
ber01-VHDL13_DWOI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:16 3771
ber01-VHDL13_DWOI_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:16 3873
ber01-VHDL13_DWOI_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:28:11 4054
ber01-VHDL13_DWOI_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 09:38:56 4058
ber01-VHDL13_DWOI_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:28:11 3557
ber01-VHDL13_DWOI_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:28:11 3801
ber01-VHDL13_DWOI_150400-2602150400-dsw--0-ia5 15-Feb-2026 05:58:15 3754
ber01-VHDL13_DWOI_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:11 4333
ber01-VHDL13_DWOI_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:28:11 4306
ber01-VHDL13_DWON_131731-2602131731-dsw--0-ia5 13-Feb-2026 17:32:03 3986
ber01-VHDL13_DWON_131734-2602131734-dsw--0-ia5 13-Feb-2026 17:34:29 3986
ber01-VHDL13_DWON_132129-2602132129-dsw--0-ia5 13-Feb-2026 21:29:41 4271
ber01-VHDL13_DWON_140356-2602140356-dsw--0-ia5 14-Feb-2026 03:56:29 4254
ber01-VHDL13_DWON_140707-2602140707-dsw--0-ia5 14-Feb-2026 07:07:52 5154
ber01-VHDL13_DWON_140708_COR-2602140708-dsw--0-ia5 14-Feb-2026 07:08:56 5158
ber01-VHDL13_DWON_140849-2602140849-dsw--0-ia5 14-Feb-2026 08:49:16 5154
ber01-VHDL13_DWON_141005-2602141005-dsw--0-ia5 14-Feb-2026 10:05:32 5154
ber01-VHDL13_DWON_141005_COR-2602141005-dsw--0-ia5 14-Feb-2026 10:05:52 5158
ber01-VHDL13_DWON_141514-2602141514-dsw--0-ia5 14-Feb-2026 15:14:53 4509
ber01-VHDL13_DWON_141515_COR-2602141515-dsw--0-ia5 14-Feb-2026 15:15:24 4513
ber01-VHDL13_DWON_141740-2602141740-dsw--0-ia5 14-Feb-2026 17:40:41 4324
ber01-VHDL13_DWON_142155-2602142155-dsw--0-ia5 14-Feb-2026 21:55:23 4336
ber01-VHDL13_DWON_150352-2602150352-dsw--0-ia5 15-Feb-2026 03:52:52 4306
ber01-VHDL13_DWON_150629-2602150629-dsw--0-ia5 15-Feb-2026 06:29:26 4461
ber01-VHDL13_DWON_150805-2602150805-dsw--0-ia5 15-Feb-2026 08:05:40 5207
ber01-VHDL13_DWON_151358-2602151358-dsw--0-ia5 15-Feb-2026 13:58:16 4212
ber01-VHDL13_DWPG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2700
ber01-VHDL13_DWPG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 2995
ber01-VHDL13_DWPG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2999
ber01-VHDL13_DWPG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 2792
ber01-VHDL13_DWPG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 2466
ber01-VHDL13_DWPG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 2680
ber01-VHDL13_DWPG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 2915
ber01-VHDL13_DWPG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 2819
ber01-VHDL13_DWPH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2650
ber01-VHDL13_DWPH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 2853
ber01-VHDL13_DWPH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2826
ber01-VHDL13_DWPH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 2619
ber01-VHDL13_DWPH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 2184
ber01-VHDL13_DWPH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:06 2509
ber01-VHDL13_DWPH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 2627
ber01-VHDL13_DWPH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 3016
ber01-VHDL13_DWSG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 3223
ber01-VHDL13_DWSG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3562
ber01-VHDL13_DWSG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3914
ber01-VHDL13_DWSG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:30:02 3915
ber01-VHDL13_DWSG_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 13:57:11 4324
ber01-VHDL13_DWSG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:30:10 4037
ber01-VHDL13_DWSG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:30:01 4383
ber01-VHDL13_DWSG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 4455
ber01-VHDL13_DWSG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:30:04 4944
ber01-VHDL17_DWOG_141200-2602141200-dsw--0-ia5 14-Feb-2026 12:11:27 3415
ber01-VHDL17_DWOG_151200-2602151200-dsw--0-ia5 15-Feb-2026 12:05:37 4024
swis2-VHDL20_DWEG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4032
swis2-VHDL20_DWEG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4304
swis2-VHDL20_DWEG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4397
swis2-VHDL20_DWEG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 5069
swis2-VHDL20_DWEG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 4035
swis2-VHDL20_DWEG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4443
swis2-VHDL20_DWEG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 4950
swis2-VHDL20_DWEG_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:01 4954
swis2-VHDL20_DWEG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 5078
swis2-VHDL20_DWEH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4122
swis2-VHDL20_DWEH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4402
swis2-VHDL20_DWEH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4373
swis2-VHDL20_DWEH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 5041
swis2-VHDL20_DWEH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 4244
swis2-VHDL20_DWEH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4528
swis2-VHDL20_DWEH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 5284
swis2-VHDL20_DWEH_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:01 5288
swis2-VHDL20_DWEH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 5550
swis2-VHDL20_DWEI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4030
swis2-VHDL20_DWEI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4270
swis2-VHDL20_DWEI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4449
swis2-VHDL20_DWEI_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 5050
swis2-VHDL20_DWEI_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 4138
swis2-VHDL20_DWEI_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4323
swis2-VHDL20_DWEI_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 4924
swis2-VHDL20_DWEI_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 06:01:01 4928
swis2-VHDL20_DWEI_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 5154
swis2-VHDL20_DWHG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3064
swis2-VHDL20_DWHG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3848
swis2-VHDL20_DWHG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3845
swis2-VHDL20_DWHG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 4198
swis2-VHDL20_DWHG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:06 4003
swis2-VHDL20_DWHG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:02 4410
swis2-VHDL20_DWHG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 4407
swis2-VHDL20_DWHG_150400_COR-2602150400-dsw--0-ia5 15-Feb-2026 07:09:11 4411
swis2-VHDL20_DWHG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 4847
swis2-VHDL20_DWHH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3016
swis2-VHDL20_DWHH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3437
swis2-VHDL20_DWHH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3436
swis2-VHDL20_DWHH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:06 3917
swis2-VHDL20_DWHH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:06 3429
swis2-VHDL20_DWHH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:02 3946
swis2-VHDL20_DWHH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:07 3946
swis2-VHDL20_DWHH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 4233
swis2-VHDL20_DWLG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3648
swis2-VHDL20_DWLG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3862
swis2-VHDL20_DWLG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3648
swis2-VHDL20_DWLG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 4043
swis2-VHDL20_DWLG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 3598
swis2-VHDL20_DWLG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 3683
swis2-VHDL20_DWLG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:11 3791
swis2-VHDL20_DWLG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 4328
swis2-VHDL20_DWLH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3318
swis2-VHDL20_DWLH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3616
swis2-VHDL20_DWLH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3505
swis2-VHDL20_DWLH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 3852
swis2-VHDL20_DWLH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 3492
swis2-VHDL20_DWLH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 3431
swis2-VHDL20_DWLH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:11 3627
swis2-VHDL20_DWLH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 4147
swis2-VHDL20_DWLI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3535
swis2-VHDL20_DWLI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3675
swis2-VHDL20_DWLI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3460
swis2-VHDL20_DWLI_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 3718
swis2-VHDL20_DWLI_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 3254
swis2-VHDL20_DWLI_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 3258
swis2-VHDL20_DWLI_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:11 3453
swis2-VHDL20_DWLI_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 3639
swis2-VHDL20_DWMG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3334
swis2-VHDL20_DWMG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3637
swis2-VHDL20_DWMG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3708
swis2-VHDL20_DWMG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:06 4294
swis2-VHDL20_DWMG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:06 3844
swis2-VHDL20_DWMG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4670
swis2-VHDL20_DWMG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 4455
swis2-VHDL20_DWMG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 5016
swis2-VHDL20_DWMO_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3092
swis2-VHDL20_DWMO_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3236
swis2-VHDL20_DWMO_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3262
swis2-VHDL20_DWMO_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:06 3866
swis2-VHDL20_DWMO_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:06 3519
swis2-VHDL20_DWMO_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 3397
swis2-VHDL20_DWMO_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 4106
swis2-VHDL20_DWMO_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 4818
swis2-VHDL20_DWMP_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3272
swis2-VHDL20_DWMP_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3670
swis2-VHDL20_DWMP_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3688
swis2-VHDL20_DWMP_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:06 4164
swis2-VHDL20_DWMP_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:06 3840
swis2-VHDL20_DWMP_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4007
swis2-VHDL20_DWMP_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:06 4562
swis2-VHDL20_DWMP_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:01 5208
swis2-VHDL20_DWPG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3333
swis2-VHDL20_DWPG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3538
swis2-VHDL20_DWPG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3442
swis2-VHDL20_DWPG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 3404
swis2-VHDL20_DWPG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 3045
swis2-VHDL20_DWPG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 3057
swis2-VHDL20_DWPG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:11 3306
swis2-VHDL20_DWPG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 3397
swis2-VHDL20_DWPH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3214
swis2-VHDL20_DWPH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3395
swis2-VHDL20_DWPH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3202
swis2-VHDL20_DWPH_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 3163
swis2-VHDL20_DWPH_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 2738
swis2-VHDL20_DWPH_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 2885
swis2-VHDL20_DWPH_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:00:11 2995
swis2-VHDL20_DWPH_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 3585
swis2-VHDL20_DWSG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3582
swis2-VHDL20_DWSG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3968
swis2-VHDL20_DWSG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4408
swis2-VHDL20_DWSG_140800-2602140800-dsw--0-ia5 14-Feb-2026 09:45:02 4757
swis2-VHDL20_DWSG_140800_COR-2602140800-dsw--0-ia5 14-Feb-2026 13:57:11 4952
swis2-VHDL20_DWSG_141300-2602141300-dsw--0-ia5 14-Feb-2026 14:45:12 4763
swis2-VHDL20_DWSG_141800-2602141800-dsw--0-ia5 14-Feb-2026 19:45:02 4454
swis2-VHDL20_DWSG_150200-2602150200-dsw--0-ia5 15-Feb-2026 03:45:06 4789
swis2-VHDL20_DWSG_150400-2602150400-dsw--0-ia5 15-Feb-2026 06:15:02 4869
swis2-VHDL20_DWSG_150800-2602150800-dsw--0-ia5 15-Feb-2026 09:45:06 5548
swis2-VHDL20_DWSG_151300-2602151300-dsw--0-ia5 15-Feb-2026 14:45:11 5336
wst04-VHDL20_DWEG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 237135
wst04-VHDL20_DWEG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 238684
wst04-VHDL20_DWEG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:26 238308
wst04-VHDL20_DWEG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:12 237125
wst04-VHDL20_DWEG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:12 235292
wst04-VHDL20_DWEG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:17 235990
wst04-VHDL20_DWEG_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:17 236467
wst04-VHDL20_DWEG_150400_COR-2602150400-omedes-..> 15-Feb-2026 06:01:17 236467
wst04-VHDL20_DWEG_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:12 233693
wst04-VHDL20_DWEH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 231950
wst04-VHDL20_DWEH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 232571
wst04-VHDL20_DWEH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 232069
wst04-VHDL20_DWEH_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:17 234766
wst04-VHDL20_DWEH_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:12 233935
wst04-VHDL20_DWEH_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:23 234581
wst04-VHDL20_DWEH_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:17 235272
wst04-VHDL20_DWEH_150400_COR-2602150400-omedes-..> 15-Feb-2026 06:01:17 235272
wst04-VHDL20_DWEH_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:12 237091
wst04-VHDL20_DWEI_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 332050
wst04-VHDL20_DWEI_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 332715
wst04-VHDL20_DWEI_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:26 332809
wst04-VHDL20_DWEI_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:17 328840
wst04-VHDL20_DWEI_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:12 326788
wst04-VHDL20_DWEI_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:23 326986
wst04-VHDL20_DWEI_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:21 328633
wst04-VHDL20_DWEI_150400_COR-2602150400-omedes-..> 15-Feb-2026 06:01:17 328633
wst04-VHDL20_DWEI_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:16 325256
wst04-VHDL20_DWHG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:23 318774
wst04-VHDL20_DWHG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 319012
wst04-VHDL20_DWHG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:12 319050
wst04-VHDL20_DWHG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:21 318647
wst04-VHDL20_DWHG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:22 316583
wst04-VHDL20_DWHG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:17 317218
wst04-VHDL20_DWHG_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:13 317152
wst04-VHDL20_DWHG_150400_COR-2602150400-omedes-..> 15-Feb-2026 07:08:17 317152
wst04-VHDL20_DWHG_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:26 322001
wst04-VHDL20_DWHH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:23 306644
wst04-VHDL20_DWHH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 307104
wst04-VHDL20_DWHH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:12 307254
wst04-VHDL20_DWHH_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:21 305898
wst04-VHDL20_DWHH_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:22 304991
wst04-VHDL20_DWHH_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:17 305379
wst04-VHDL20_DWHH_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:13 305303
wst04-VHDL20_DWHH_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:26 321736
wst04-VHDL20_DWLG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:21 304876
wst04-VHDL20_DWLG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 304802
wst04-VHDL20_DWLG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 304195
wst04-VHDL20_DWLG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:31 305840
wst04-VHDL20_DWLG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:22 305902
wst04-VHDL20_DWLG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:27 306468
wst04-VHDL20_DWLG_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:41 306179
wst04-VHDL20_DWLG_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:36 314854
wst04-VHDL20_DWLH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 304953
wst04-VHDL20_DWLH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 305828
wst04-VHDL20_DWLH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 305037
wst04-VHDL20_DWLH_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:31 309446
wst04-VHDL20_DWLH_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:22 308721
wst04-VHDL20_DWLH_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:27 309763
wst04-VHDL20_DWLH_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:41 308975
wst04-VHDL20_DWLH_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:32 312566
wst04-VHDL20_DWLI_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 306464
wst04-VHDL20_DWLI_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 306841
wst04-VHDL20_DWLI_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 306024
wst04-VHDL20_DWLI_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:31 307010
wst04-VHDL20_DWLI_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:26 306456
wst04-VHDL20_DWLI_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:27 306927
wst04-VHDL20_DWLI_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:41 306147
wst04-VHDL20_DWLI_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:32 309626
wst04-VHDL20_DWMG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 516754
wst04-VHDL20_DWMG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 517290
wst04-VHDL20_DWMG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 517247
wst04-VHDL20_DWMG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:27 514373
wst04-VHDL20_DWMG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:16 513354
wst04-VHDL20_DWMG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:13 515276
wst04-VHDL20_DWMG_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:27 514133
wst04-VHDL20_DWMG_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:22 503620
wst04-VHDL20_DWMO_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 413741
wst04-VHDL20_DWMO_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 414577
wst04-VHDL20_DWMO_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 415090
wst04-VHDL20_DWMO_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:27 414188
wst04-VHDL20_DWMO_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:16 413404
wst04-VHDL20_DWMO_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:13 412557
wst04-VHDL20_DWMO_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:21 414054
wst04-VHDL20_DWMO_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:16 413658
wst04-VHDL20_DWMP_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 542382
wst04-VHDL20_DWMP_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 541722
wst04-VHDL20_DWMP_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 542826
wst04-VHDL20_DWMP_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:27 538743
wst04-VHDL20_DWMP_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:16 537033
wst04-VHDL20_DWMP_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:17 536011
wst04-VHDL20_DWMP_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:15:27 538329
wst04-VHDL20_DWMP_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:22 528584
wst04-VHDL20_DWPG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 312885
wst04-VHDL20_DWPG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 313505
wst04-VHDL20_DWPG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:32 312844
wst04-VHDL20_DWPG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:31 358562
wst04-VHDL20_DWPG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:26 313286
wst04-VHDL20_DWPG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:27 313381
wst04-VHDL20_DWPG_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:31 313606
wst04-VHDL20_DWPG_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:32 363134
wst04-VHDL20_DWPH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:21 272322
wst04-VHDL20_DWPH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 227538
wst04-VHDL20_DWPH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:32 227274
wst04-VHDL20_DWPH_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:27 269527
wst04-VHDL20_DWPH_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:22 268741
wst04-VHDL20_DWPH_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:21 224145
wst04-VHDL20_DWPH_150400-2602150400-omedes--0.pdf 15-Feb-2026 06:00:31 224217
wst04-VHDL20_DWPH_150800-2602150800-omedes--0.pdf 15-Feb-2026 09:45:26 273572
wst04-VHDL20_DWSG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 323187
wst04-VHDL20_DWSG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 324203
wst04-VHDL20_DWSG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:16 324755
wst04-VHDL20_DWSG_140800-2602140800-omedes--0.pdf 14-Feb-2026 09:45:12 325583
wst04-VHDL20_DWSG_140800_COR-2602140800-omedes-..> 14-Feb-2026 13:57:17 325886
wst04-VHDL20_DWSG_141300-2602141300-omedes--0.pdf 14-Feb-2026 14:45:12 325836
wst04-VHDL20_DWSG_141800-2602141800-omedes--0.pdf 14-Feb-2026 19:45:12 325564
wst04-VHDL20_DWSG_150200-2602150200-omedes--0.pdf 15-Feb-2026 03:45:17 325890
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