Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Dec-2025 15:02:09 6047
FPDL13_DWMZ_160600 16-Dec-2025 12:35:47 3386
SXDL31_DWAV_150800 15-Dec-2025 08:09:19 6816
SXDL31_DWAV_151800 15-Dec-2025 17:01:25 5894
SXDL31_DWAV_160800 16-Dec-2025 08:49:14 10894
SXDL31_DWAV_161800 16-Dec-2025 17:34:28 4476
SXDL31_DWAV_LATEST 16-Dec-2025 17:34:28 4476
SXDL33_DWAV_150000 15-Dec-2025 10:47:35 7322
SXDL33_DWAV_160000 16-Dec-2025 10:59:59 8208
SXDL33_DWAV_LATEST 16-Dec-2025 10:59:59 8208
ber01-FWDL39_DWMS_151230-2512151230-dsw--0-ia5 15-Dec-2025 12:19:11 1270
ber01-FWDL39_DWMS_161230-2512161230-dsw--0-ia5 16-Dec-2025 12:08:47 1158
ber01-VHDL13_DWEH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:28:12 2976
ber01-VHDL13_DWEH_150400-2512150400-dsw--0-ia5 15-Dec-2025 05:58:17 3373
ber01-VHDL13_DWEH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:28:18 3430
ber01-VHDL13_DWEH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:28:19 2621
ber01-VHDL13_DWEH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:28:11 2777
ber01-VHDL13_DWEH_160400-2512160400-dsw--0-ia5 16-Dec-2025 05:58:11 3037
ber01-VHDL13_DWEH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:28:17 3056
ber01-VHDL13_DWEH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:28:17 2760
ber01-VHDL13_DWHG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 3206
ber01-VHDL13_DWHG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:06 3245
ber01-VHDL13_DWHG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:06 3623
ber01-VHDL13_DWHG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 3079
ber01-VHDL13_DWHG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:09 3297
ber01-VHDL13_DWHG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 3297
ber01-VHDL13_DWHG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:09 3403
ber01-VHDL13_DWHG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:08 3194
ber01-VHDL13_DWHH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 2607
ber01-VHDL13_DWHH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:06 2619
ber01-VHDL13_DWHH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:06 2902
ber01-VHDL13_DWHH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 2557
ber01-VHDL13_DWHH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:09 3095
ber01-VHDL13_DWHH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 3095
ber01-VHDL13_DWHH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:09 3178
ber01-VHDL13_DWHH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:08 3084
ber01-VHDL13_DWLG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 2256
ber01-VHDL13_DWLG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 2632
ber01-VHDL13_DWLG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 2613
ber01-VHDL13_DWLG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 2295
ber01-VHDL13_DWLG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 2408
ber01-VHDL13_DWLG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 2349
ber01-VHDL13_DWLG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 2378
ber01-VHDL13_DWLG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 2174
ber01-VHDL13_DWLH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 2003
ber01-VHDL13_DWLH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 2189
ber01-VHDL13_DWLH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 2135
ber01-VHDL13_DWLH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 1919
ber01-VHDL13_DWLH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 2160
ber01-VHDL13_DWLH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 1975
ber01-VHDL13_DWLH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 1975
ber01-VHDL13_DWLH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 1842
ber01-VHDL13_DWLI_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 2119
ber01-VHDL13_DWLI_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 2283
ber01-VHDL13_DWLI_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 2255
ber01-VHDL13_DWLI_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 1984
ber01-VHDL13_DWLI_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 2095
ber01-VHDL13_DWLI_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 1947
ber01-VHDL13_DWLI_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 1947
ber01-VHDL13_DWLI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 1868
ber01-VHDL13_DWMG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:02 3124
ber01-VHDL13_DWMG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 3135
ber01-VHDL13_DWMG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:06 2906
ber01-VHDL13_DWMG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:02 2824
ber01-VHDL13_DWMG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 3381
ber01-VHDL13_DWMG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:02 3377
ber01-VHDL13_DWMG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 3251
ber01-VHDL13_DWMG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 3118
ber01-VHDL13_DWMO_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:02 2843
ber01-VHDL13_DWMO_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 2854
ber01-VHDL13_DWMO_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:06 2692
ber01-VHDL13_DWMO_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:02 2476
ber01-VHDL13_DWMO_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 3042
ber01-VHDL13_DWMO_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:02 3034
ber01-VHDL13_DWMO_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 2880
ber01-VHDL13_DWMO_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 2620
ber01-VHDL13_DWMP_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:02 2979
ber01-VHDL13_DWMP_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 2990
ber01-VHDL13_DWMP_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:06 3029
ber01-VHDL13_DWMP_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:02 2664
ber01-VHDL13_DWMP_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 3295
ber01-VHDL13_DWMP_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:02 3291
ber01-VHDL13_DWMP_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 3157
ber01-VHDL13_DWMP_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 2923
ber01-VHDL13_DWOG_150300-2512150300-dsw--0-ia5 15-Dec-2025 04:00:01 3761
ber01-VHDL13_DWOG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 4048
ber01-VHDL13_DWOG_150800_COR-2512150800-dsw--0-ia5 15-Dec-2025 15:52:37 3722
ber01-VHDL13_DWOG_151700-2512151700-dsw--0-ia5 15-Dec-2025 19:00:02 3713
ber01-VHDL13_DWOG_160300-2512160300-dsw--0-ia5 16-Dec-2025 04:00:03 4168
ber01-VHDL13_DWOG_160800-2512160800-dsw--0-ia5 16-Dec-2025 11:33:47 4014
ber01-VHDL13_DWOG_161700-2512161700-dsw--0-ia5 16-Dec-2025 19:00:03 3824
ber01-VHDL13_DWOH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:28:12 2444
ber01-VHDL13_DWOH_150400-2512150400-dsw--0-ia5 15-Dec-2025 05:58:11 2514
ber01-VHDL13_DWOH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:28:18 2479
ber01-VHDL13_DWOH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:28:13 2028
ber01-VHDL13_DWOH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:28:11 2474
ber01-VHDL13_DWOH_160400-2512160400-dsw--0-ia5 16-Dec-2025 05:58:16 2675
ber01-VHDL13_DWOH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:28:17 2496
ber01-VHDL13_DWOH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:28:17 2216
ber01-VHDL13_DWOI_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:28:16 2518
ber01-VHDL13_DWOI_150400-2512150400-dsw--0-ia5 15-Dec-2025 05:58:17 2846
ber01-VHDL13_DWOI_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:28:12 2965
ber01-VHDL13_DWOI_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:28:13 2314
ber01-VHDL13_DWOI_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:28:17 2730
ber01-VHDL13_DWOI_160400-2512160400-dsw--0-ia5 16-Dec-2025 05:58:16 2894
ber01-VHDL13_DWOI_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:28:11 2676
ber01-VHDL13_DWOI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:28:13 2362
ber01-VHDL13_DWON_150628-2512150628-dsw--0-ia5 15-Dec-2025 06:28:57 3542
ber01-VHDL13_DWON_150649-2512150649-dsw--0-ia5 15-Dec-2025 06:49:06 3579
ber01-VHDL13_DWON_150854-2512150854-dsw--0-ia5 15-Dec-2025 08:54:41 3579
ber01-VHDL13_DWON_151551-2512151551-dsw--0-ia5 15-Dec-2025 15:52:00 3219
ber01-VHDL13_DWON_151742-2512151742-dsw--0-ia5 15-Dec-2025 17:42:46 3284
ber01-VHDL13_DWON_160244-2512160244-dsw--0-ia5 16-Dec-2025 02:44:22 3374
ber01-VHDL13_DWON_160259-2512160259-dsw--0-ia5 16-Dec-2025 02:59:19 3528
ber01-VHDL13_DWON_160447-2512160447-dsw--0-ia5 16-Dec-2025 04:47:46 3528
ber01-VHDL13_DWON_160606-2512160606-dsw--0-ia5 16-Dec-2025 06:06:33 3887
ber01-VHDL13_DWON_160707-2512160707-dsw--0-ia5 16-Dec-2025 07:07:57 3887
ber01-VHDL13_DWON_160718-2512160718-dsw--0-ia5 16-Dec-2025 07:18:12 3887
ber01-VHDL13_DWON_160852-2512160852-dsw--0-ia5 16-Dec-2025 08:52:11 3887
ber01-VHDL13_DWON_160918-2512160918-dsw--0-ia5 16-Dec-2025 09:18:17 3887
ber01-VHDL13_DWON_161133-2512161133-dsw--0-ia5 16-Dec-2025 11:33:26 3889
ber01-VHDL13_DWON_161553-2512161553-dsw--0-ia5 16-Dec-2025 15:53:22 3220
ber01-VHDL13_DWON_161737-2512161737-dsw--0-ia5 16-Dec-2025 17:37:22 3220
ber01-VHDL13_DWPG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 1777
ber01-VHDL13_DWPG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 1832
ber01-VHDL13_DWPG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 1784
ber01-VHDL13_DWPG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 1591
ber01-VHDL13_DWPG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 1654
ber01-VHDL13_DWPG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 1808
ber01-VHDL13_DWPG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 1692
ber01-VHDL13_DWPG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 1532
ber01-VHDL13_DWPH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:06 1718
ber01-VHDL13_DWPH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:01 1829
ber01-VHDL13_DWPH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 1839
ber01-VHDL13_DWPH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 1641
ber01-VHDL13_DWPH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 1872
ber01-VHDL13_DWPH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 2151
ber01-VHDL13_DWPH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 2182
ber01-VHDL13_DWPH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:30:03 2003
ber01-VHDL13_DWSG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:30:02 2913
ber01-VHDL13_DWSG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:07 2913
ber01-VHDL13_DWSG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:30:01 2692
ber01-VHDL13_DWSG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:30:09 2638
ber01-VHDL13_DWSG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:30:04 2984
ber01-VHDL13_DWSG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 3382
ber01-VHDL13_DWSG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:30:01 3340
ber01-VHDL13_DWSG_161800-2512161800-dsw--0-ia5 16-Dec-2025 20:58:17 2842
ber01-VHDL17_DWOG_151200-2512151200-dsw--0-ia5 15-Dec-2025 12:39:09 3439
ber01-VHDL17_DWOG_161200-2512161200-dsw--0-ia5 16-Dec-2025 12:31:07 3560
swis2-VHDL20_DWEG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:06 2836
swis2-VHDL20_DWEG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:06 2858
swis2-VHDL20_DWEG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 2986
swis2-VHDL20_DWEG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 2378
swis2-VHDL20_DWEG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2774
swis2-VHDL20_DWEG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:07 3026
swis2-VHDL20_DWEG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3009
swis2-VHDL20_DWEG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 2560
swis2-VHDL20_DWEH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:06 3393
swis2-VHDL20_DWEH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:06 3794
swis2-VHDL20_DWEH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 4028
swis2-VHDL20_DWEH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 3075
swis2-VHDL20_DWEH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 3197
swis2-VHDL20_DWEH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:07 3410
swis2-VHDL20_DWEH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3604
swis2-VHDL20_DWEH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3153
swis2-VHDL20_DWEI_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:06 2926
swis2-VHDL20_DWEI_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:06 3218
swis2-VHDL20_DWEI_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3516
swis2-VHDL20_DWEI_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 2686
swis2-VHDL20_DWEI_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 3042
swis2-VHDL20_DWEI_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:07 3288
swis2-VHDL20_DWEI_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3248
swis2-VHDL20_DWEI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 2734
swis2-VHDL20_DWHG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 3392
swis2-VHDL20_DWHG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:06 3428
swis2-VHDL20_DWHG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:07 4328
swis2-VHDL20_DWHG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 3262
swis2-VHDL20_DWHG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:02 3483
swis2-VHDL20_DWHG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 3480
swis2-VHDL20_DWHG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:06 4034
swis2-VHDL20_DWHG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3377
swis2-VHDL20_DWHH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 2793
swis2-VHDL20_DWHH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:07 2805
swis2-VHDL20_DWHH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:07 3445
swis2-VHDL20_DWHH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 2743
swis2-VHDL20_DWHH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:02 3281
swis2-VHDL20_DWHH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:06 3281
swis2-VHDL20_DWHH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:06 3720
swis2-VHDL20_DWHH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3270
swis2-VHDL20_DWLG_150200-2512150200-dsw--0-ia5 15-Dec-2025 04:41:37 2638
swis2-VHDL20_DWLG_150345-2512150345-dsw--0-ia5 15-Dec-2025 03:45:04 2597
swis2-VHDL20_DWLG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:11 3012
swis2-VHDL20_DWLG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3170
swis2-VHDL20_DWLG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:05 2675
swis2-VHDL20_DWLG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2738
swis2-VHDL20_DWLG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:12 2710
swis2-VHDL20_DWLG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 2885
swis2-VHDL20_DWLG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2680
swis2-VHDL20_DWLH_150200-2512150200-dsw--0-ia5 15-Dec-2025 04:30:33 2392
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swis2-VHDL20_DWLH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 2704
swis2-VHDL20_DWLH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:05 2307
swis2-VHDL20_DWLH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2497
swis2-VHDL20_DWLH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:12 2343
swis2-VHDL20_DWLH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 2493
swis2-VHDL20_DWLH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2210
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swis2-VHDL20_DWLI_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:11 2665
swis2-VHDL20_DWLI_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 2813
swis2-VHDL20_DWLI_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:05 2366
swis2-VHDL20_DWLI_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2427
swis2-VHDL20_DWLI_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:12 2310
swis2-VHDL20_DWLI_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 2455
swis2-VHDL20_DWLI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2231
swis2-VHDL20_DWMG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 3608
swis2-VHDL20_DWMG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:01 3622
swis2-VHDL20_DWMG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3540
swis2-VHDL20_DWMG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 3242
swis2-VHDL20_DWMG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 3859
swis2-VHDL20_DWMG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:02 3796
swis2-VHDL20_DWMG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3894
swis2-VHDL20_DWMG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3545
swis2-VHDL20_DWMO_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 3277
swis2-VHDL20_DWMO_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:01 3297
swis2-VHDL20_DWMO_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3337
swis2-VHDL20_DWMO_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 2903
swis2-VHDL20_DWMO_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 3470
swis2-VHDL20_DWMO_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:02 3461
swis2-VHDL20_DWMO_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3575
swis2-VHDL20_DWMO_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3047
swis2-VHDL20_DWMP_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 3456
swis2-VHDL20_DWMP_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:01 3475
swis2-VHDL20_DWMP_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3669
swis2-VHDL20_DWMP_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:07 3109
swis2-VHDL20_DWMP_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 3769
swis2-VHDL20_DWMP_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:07 3710
swis2-VHDL20_DWMP_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:02 3809
swis2-VHDL20_DWMP_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3341
swis2-VHDL20_DWPG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 2102
swis2-VHDL20_DWPG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:11 2176
swis2-VHDL20_DWPG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 2262
swis2-VHDL20_DWPG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:05 2069
swis2-VHDL20_DWPG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2001
swis2-VHDL20_DWPG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:12 2135
swis2-VHDL20_DWPG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 2155
swis2-VHDL20_DWPG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 1995
swis2-VHDL20_DWPH_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:04 2042
swis2-VHDL20_DWPH_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:00:11 2155
swis2-VHDL20_DWPH_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 2297
swis2-VHDL20_DWPH_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:05 2099
swis2-VHDL20_DWPH_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:07 2198
swis2-VHDL20_DWPH_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:00:12 2480
swis2-VHDL20_DWPH_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 2645
swis2-VHDL20_DWPH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2466
swis2-VHDL20_DWSG_150200-2512150200-dsw--0-ia5 15-Dec-2025 03:45:06 3322
swis2-VHDL20_DWSG_150400-2512150400-dsw--0-ia5 15-Dec-2025 06:15:01 3330
swis2-VHDL20_DWSG_150800-2512150800-dsw--0-ia5 15-Dec-2025 09:45:04 3354
swis2-VHDL20_DWSG_151300-2512151300-dsw--0-ia5 15-Dec-2025 14:45:06 3202
swis2-VHDL20_DWSG_151800-2512151800-dsw--0-ia5 15-Dec-2025 19:45:03 3043
swis2-VHDL20_DWSG_160200-2512160200-dsw--0-ia5 16-Dec-2025 03:45:02 3398
swis2-VHDL20_DWSG_160400-2512160400-dsw--0-ia5 16-Dec-2025 06:15:02 3836
swis2-VHDL20_DWSG_160800-2512160800-dsw--0-ia5 16-Dec-2025 09:45:00 4038
swis2-VHDL20_DWSG_161300-2512161300-dsw--0-ia5 16-Dec-2025 14:45:06 3673
swis2-VHDL20_DWSG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3005
wst04-VHDL20_DWEG_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:16 228778
wst04-VHDL20_DWEG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:26 228282
wst04-VHDL20_DWEG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:13 229761
wst04-VHDL20_DWEG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:19 227322
wst04-VHDL20_DWEG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:17 228599
wst04-VHDL20_DWEG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:27 228151
wst04-VHDL20_DWEG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:22 225613
wst04-VHDL20_DWEG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 224446
wst04-VHDL20_DWEH_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:12 229307
wst04-VHDL20_DWEH_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:22 229156
wst04-VHDL20_DWEH_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:17 231173
wst04-VHDL20_DWEH_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:19 228735
wst04-VHDL20_DWEH_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:17 230195
wst04-VHDL20_DWEH_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:21 229845
wst04-VHDL20_DWEH_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:22 228342
wst04-VHDL20_DWEH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 227000
wst04-VHDL20_DWEI_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:16 322941
wst04-VHDL20_DWEI_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:26 323285
wst04-VHDL20_DWEI_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:17 321034
wst04-VHDL20_DWEI_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:19 319232
wst04-VHDL20_DWEI_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:17 319682
wst04-VHDL20_DWEI_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:27 320281
wst04-VHDL20_DWEI_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:26 310161
wst04-VHDL20_DWEI_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 309185
wst04-VHDL20_DWHG_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:12 312706
wst04-VHDL20_DWHG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:11 312619
wst04-VHDL20_DWHG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:27 311380
wst04-VHDL20_DWHG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:21 308931
wst04-VHDL20_DWHG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:13 309146
wst04-VHDL20_DWHG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:12 309209
wst04-VHDL20_DWHG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:22 301075
wst04-VHDL20_DWHG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:22 299797
wst04-VHDL20_DWHH_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:12 296051
wst04-VHDL20_DWHH_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:11 296198
wst04-VHDL20_DWHH_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:27 295487
wst04-VHDL20_DWHH_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:21 294362
wst04-VHDL20_DWHH_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:13 295228
wst04-VHDL20_DWHH_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:12 295277
wst04-VHDL20_DWHH_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:16 287936
wst04-VHDL20_DWHH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:22 287269
wst04-VHDL20_DWLG_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:26 311126
wst04-VHDL20_DWLG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:42 311856
wst04-VHDL20_DWLG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:31 309885
wst04-VHDL20_DWLG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:27 308364
wst04-VHDL20_DWLG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:21 308731
wst04-VHDL20_DWLG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:42 308610
wst04-VHDL20_DWLG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:32 295139
wst04-VHDL20_DWLG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 294697
wst04-VHDL20_DWLH_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:22 311154
wst04-VHDL20_DWLH_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:42 311471
wst04-VHDL20_DWLH_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:31 308838
wst04-VHDL20_DWLH_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:21 308113
wst04-VHDL20_DWLH_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:27 308544
wst04-VHDL20_DWLH_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:42 308398
wst04-VHDL20_DWLH_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:32 297608
wst04-VHDL20_DWLH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:20 297209
wst04-VHDL20_DWLI_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:26 317935
wst04-VHDL20_DWLI_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:42 318145
wst04-VHDL20_DWLI_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:37 317870
wst04-VHDL20_DWLI_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:27 317137
wst04-VHDL20_DWLI_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:27 317377
wst04-VHDL20_DWLI_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:42 317226
wst04-VHDL20_DWLI_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:32 300774
wst04-VHDL20_DWLI_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 300263
wst04-VHDL20_DWMG_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:18 528877
wst04-VHDL20_DWMG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:22 529246
wst04-VHDL20_DWMG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:21 526805
wst04-VHDL20_DWMG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:19 526523
wst04-VHDL20_DWMG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:21 527021
wst04-VHDL20_DWMG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:21 526967
wst04-VHDL20_DWMG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:16 508085
wst04-VHDL20_DWMG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:18 507238
wst04-VHDL20_DWMO_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:18 422961
wst04-VHDL20_DWMO_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:16 423495
wst04-VHDL20_DWMO_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:11 424396
wst04-VHDL20_DWMO_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:11 423808
wst04-VHDL20_DWMO_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:17 424258
wst04-VHDL20_DWMO_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:21 424754
wst04-VHDL20_DWMO_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:12 409126
wst04-VHDL20_DWMO_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 408097
wst04-VHDL20_DWMP_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:22 544412
wst04-VHDL20_DWMP_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:22 545509
wst04-VHDL20_DWMP_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:21 538992
wst04-VHDL20_DWMP_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:11 538062
wst04-VHDL20_DWMP_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:21 537519
wst04-VHDL20_DWMP_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:21 538592
wst04-VHDL20_DWMP_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:16 535421
wst04-VHDL20_DWMP_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 534397
wst04-VHDL20_DWPG_150200-2512150200-omedes--0.pdf 15-Dec-2025 04:27:32 312909
wst04-VHDL20_DWPG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:31 312503
wst04-VHDL20_DWPG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:31 353114
wst04-VHDL20_DWPG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:27 308655
wst04-VHDL20_DWPG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:27 308068
wst04-VHDL20_DWPG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:31 307958
wst04-VHDL20_DWPG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:32 340100
wst04-VHDL20_DWPG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 295601
wst04-VHDL20_DWPH_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:22 222623
wst04-VHDL20_DWPH_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:00:31 222903
wst04-VHDL20_DWPH_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:25 265643
wst04-VHDL20_DWPH_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:21 265362
wst04-VHDL20_DWPH_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:21 220563
wst04-VHDL20_DWPH_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:00:31 220828
wst04-VHDL20_DWPH_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:26 261798
wst04-VHDL20_DWPH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:20 261873
wst04-VHDL20_DWSG_150200-2512150200-omedes--0.pdf 15-Dec-2025 03:45:16 337065
wst04-VHDL20_DWSG_150400-2512150400-omedes--0.pdf 15-Dec-2025 06:15:16 337254
wst04-VHDL20_DWSG_150800-2512150800-omedes--0.pdf 15-Dec-2025 09:45:11 339309
wst04-VHDL20_DWSG_151300-2512151300-omedes--0.pdf 15-Dec-2025 14:45:12 339318
wst04-VHDL20_DWSG_151800-2512151800-omedes--0.pdf 15-Dec-2025 19:45:11 339086
wst04-VHDL20_DWSG_160200-2512160200-omedes--0.pdf 16-Dec-2025 03:45:13 339330
wst04-VHDL20_DWSG_160400-2512160400-omedes--0.pdf 16-Dec-2025 06:15:17 340261
wst04-VHDL20_DWSG_160800-2512160800-omedes--0.pdf 16-Dec-2025 09:45:12 327961
wst04-VHDL20_DWSG_161300-2512161300-omedes--0.pdf 16-Dec-2025 14:45:12 327512
wst04-VHDL20_DWSG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 326604