Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Feb-2026 15:07:20 5497
FPDL13_DWMZ_060600 06-Feb-2026 14:16:05 4410
SXDL31_DWAV_050800 05-Feb-2026 09:17:58 8187
SXDL31_DWAV_051800 05-Feb-2026 17:41:15 10716
SXDL31_DWAV_060800 06-Feb-2026 08:36:29 11512
SXDL31_DWAV_061800 06-Feb-2026 17:23:58 10211
SXDL31_DWAV_LATEST 06-Feb-2026 17:23:58 10211
SXDL33_DWAV_050000 05-Feb-2026 11:25:34 7692
SXDL33_DWAV_060000 06-Feb-2026 10:48:18 10060
SXDL33_DWAV_LATEST 06-Feb-2026 10:48:18 10060
ber01-FWDL39_DWMS_051230-2602051230-dsw--0-ia5 05-Feb-2026 12:01:31 1752
ber01-FWDL39_DWMS_061230-2602061230-dsw--0-ia5 06-Feb-2026 11:50:21 1908
ber01-VHDL13_DWEH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:17 3731
ber01-VHDL13_DWEH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:28:17 3376
ber01-VHDL13_DWEH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 3561
ber01-VHDL13_DWEH_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:12 3708
ber01-VHDL13_DWEH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:22 3267
ber01-VHDL13_DWEH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:16 2967
ber01-VHDL13_DWEH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:12 3264
ber01-VHDL13_DWEH_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:16 2934
ber01-VHDL13_DWHG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3498
ber01-VHDL13_DWHG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 3419
ber01-VHDL13_DWHG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 3315
ber01-VHDL13_DWHG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 3159
ber01-VHDL13_DWHG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3064
ber01-VHDL13_DWHG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:07 3922
ber01-VHDL13_DWHG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:08 4408
ber01-VHDL13_DWHG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 4378
ber01-VHDL13_DWHH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3073
ber01-VHDL13_DWHH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2901
ber01-VHDL13_DWHH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 2700
ber01-VHDL13_DWHH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2551
ber01-VHDL13_DWHH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 2599
ber01-VHDL13_DWHH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:07 3035
ber01-VHDL13_DWHH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:08 3377
ber01-VHDL13_DWHH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3557
ber01-VHDL13_DWLG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2520
ber01-VHDL13_DWLG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2238
ber01-VHDL13_DWLG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2096
ber01-VHDL13_DWLG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2285
ber01-VHDL13_DWLG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2180
ber01-VHDL13_DWLG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2080
ber01-VHDL13_DWLG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2517
ber01-VHDL13_DWLG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2274
ber01-VHDL13_DWLH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2574
ber01-VHDL13_DWLH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2387
ber01-VHDL13_DWLH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2186
ber01-VHDL13_DWLH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2174
ber01-VHDL13_DWLH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2210
ber01-VHDL13_DWLH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2454
ber01-VHDL13_DWLH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2617
ber01-VHDL13_DWLH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2235
ber01-VHDL13_DWLI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2572
ber01-VHDL13_DWLI_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2305
ber01-VHDL13_DWLI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2161
ber01-VHDL13_DWLI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2211
ber01-VHDL13_DWLI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2218
ber01-VHDL13_DWLI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2113
ber01-VHDL13_DWLI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2219
ber01-VHDL13_DWLI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 1897
ber01-VHDL13_DWMG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3247
ber01-VHDL13_DWMG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2751
ber01-VHDL13_DWMG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 3036
ber01-VHDL13_DWMG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 3130
ber01-VHDL13_DWMG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3149
ber01-VHDL13_DWMG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 3272
ber01-VHDL13_DWMG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3417
ber01-VHDL13_DWMG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3110
ber01-VHDL13_DWMO_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3122
ber01-VHDL13_DWMO_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2536
ber01-VHDL13_DWMO_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2842
ber01-VHDL13_DWMO_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2823
ber01-VHDL13_DWMO_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 2828
ber01-VHDL13_DWMO_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2939
ber01-VHDL13_DWMO_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3106
ber01-VHDL13_DWMO_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 2876
ber01-VHDL13_DWMP_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 3198
ber01-VHDL13_DWMP_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:07 2746
ber01-VHDL13_DWMP_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 3068
ber01-VHDL13_DWMP_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 3142
ber01-VHDL13_DWMP_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3017
ber01-VHDL13_DWMP_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 3066
ber01-VHDL13_DWMP_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3441
ber01-VHDL13_DWMP_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3110
ber01-VHDL13_DWOG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:51:11 6258
ber01-VHDL13_DWOG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 16:12:51 5936
ber01-VHDL13_DWOG_051700-2602051700-dsw--0-ia5 05-Feb-2026 19:00:01 5641
ber01-VHDL13_DWOG_060300-2602060300-dsw--0-ia5 06-Feb-2026 04:00:02 6001
ber01-VHDL13_DWOG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 5404
ber01-VHDL13_DWOG_061700-2602061700-dsw--0-ia5 06-Feb-2026 19:00:03 5314
ber01-VHDL13_DWOG_070300-2602070300-dsw--0-ia5 07-Feb-2026 04:00:01 5231
ber01-VHDL13_DWOH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:11 3183
ber01-VHDL13_DWOH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:28:11 3075
ber01-VHDL13_DWOH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 3023
ber01-VHDL13_DWOH_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:16 3153
ber01-VHDL13_DWOH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:12 2976
ber01-VHDL13_DWOH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:16 2691
ber01-VHDL13_DWOH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:16 2919
ber01-VHDL13_DWOH_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:12 2683
ber01-VHDL13_DWOI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:28:11 2785
ber01-VHDL13_DWOI_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:28:11 2803
ber01-VHDL13_DWOI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 2852
ber01-VHDL13_DWOI_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:16 2735
ber01-VHDL13_DWOI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:12 2419
ber01-VHDL13_DWOI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:12 2375
ber01-VHDL13_DWOI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:12 2730
ber01-VHDL13_DWOI_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:16 2421
ber01-VHDL13_DWON_050925-2602050925-dsw--0-ia5 05-Feb-2026 09:25:26 4296
ber01-VHDL13_DWON_050949-2602050949-dsw--0-ia5 05-Feb-2026 09:49:29 4296
ber01-VHDL13_DWON_051612-2602051612-dsw--0-ia5 05-Feb-2026 16:12:27 3939
ber01-VHDL13_DWON_051725-2602051725-dsw--0-ia5 05-Feb-2026 17:25:46 4335
ber01-VHDL13_DWON_051743-2602051743-dsw--0-ia5 05-Feb-2026 17:43:37 4335
ber01-VHDL13_DWON_052154-2602052154-dsw--0-ia5 05-Feb-2026 21:55:03 4522
ber01-VHDL13_DWON_060147-2602060147-dsw--0-ia5 06-Feb-2026 01:47:51 4491
ber01-VHDL13_DWON_060154-2602060154-dsw--0-ia5 06-Feb-2026 01:54:57 4491
ber01-VHDL13_DWON_060623-2602060623-dsw--0-ia5 06-Feb-2026 06:23:11 4970
ber01-VHDL13_DWON_060716-2602060716-dsw--0-ia5 06-Feb-2026 07:16:47 4964
ber01-VHDL13_DWON_060918-2602060918-dsw--0-ia5 06-Feb-2026 09:18:41 4868
ber01-VHDL13_DWON_061544-2602061544-dsw--0-ia5 06-Feb-2026 15:45:01 4012
ber01-VHDL13_DWON_061829-2602061829-dsw--0-ia5 06-Feb-2026 18:29:59 4037
ber01-VHDL13_DWON_062000-2602062000-dsw--0-ia5 06-Feb-2026 20:00:11 3972
ber01-VHDL13_DWON_070021-2602070021-dsw--0-ia5 07-Feb-2026 00:21:17 3938
ber01-VHDL13_DWON_070354-2602070354-dsw--0-ia5 07-Feb-2026 03:54:42 3938
ber01-VHDL13_DWON_070630-2602070630-dsw--0-ia5 07-Feb-2026 06:30:16 3846
ber01-VHDL13_DWON_070657-2602070657-dsw--0-ia5 07-Feb-2026 06:57:17 3841
ber01-VHDL13_DWPG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 2798
ber01-VHDL13_DWPG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2643
ber01-VHDL13_DWPG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2275
ber01-VHDL13_DWPG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2328
ber01-VHDL13_DWPG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2087
ber01-VHDL13_DWPG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2571
ber01-VHDL13_DWPG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2509
ber01-VHDL13_DWPG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2514
ber01-VHDL13_DWPH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:06 3324
ber01-VHDL13_DWPH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:05 2970
ber01-VHDL13_DWPH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2716
ber01-VHDL13_DWPH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2562
ber01-VHDL13_DWPH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2617
ber01-VHDL13_DWPH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2610
ber01-VHDL13_DWPH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2538
ber01-VHDL13_DWPH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2491
ber01-VHDL13_DWSG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:30:04 2789
ber01-VHDL13_DWSG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 11:11:01 2761
ber01-VHDL13_DWSG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:30:07 2767
ber01-VHDL13_DWSG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 2663
ber01-VHDL13_DWSG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2653
ber01-VHDL13_DWSG_060400_COR-2602060400-dsw--0-ia5 06-Feb-2026 06:36:24 2854
ber01-VHDL13_DWSG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2817
ber01-VHDL13_DWSG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2398
ber01-VHDL13_DWSG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 2566
ber01-VHDL13_DWSG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 2417
ber01-VHDL17_DWOG_051200-2602051200-dsw--0-ia5 05-Feb-2026 12:46:53 4228
ber01-VHDL17_DWOG_061200-2602061200-dsw--0-ia5 06-Feb-2026 12:37:03 3420
swis2-VHDL20_DWEG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3889
swis2-VHDL20_DWEG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3462
swis2-VHDL20_DWEG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3359
swis2-VHDL20_DWEG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3634
swis2-VHDL20_DWEG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3683
swis2-VHDL20_DWEG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 3160
swis2-VHDL20_DWEG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3313
swis2-VHDL20_DWEG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3075
swis2-VHDL20_DWEH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4637
swis2-VHDL20_DWEH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 4020
swis2-VHDL20_DWEH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 4219
swis2-VHDL20_DWEH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 4202
swis2-VHDL20_DWEH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 4028
swis2-VHDL20_DWEH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 3501
swis2-VHDL20_DWEH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3742
swis2-VHDL20_DWEH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3372
swis2-VHDL20_DWEI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3453
swis2-VHDL20_DWEI_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3334
swis2-VHDL20_DWEI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3309
swis2-VHDL20_DWEI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3090
swis2-VHDL20_DWEI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3013
swis2-VHDL20_DWEI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 2730
swis2-VHDL20_DWEI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3026
swis2-VHDL20_DWEI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 2830
swis2-VHDL20_DWHG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4354
swis2-VHDL20_DWHG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:06 3602
swis2-VHDL20_DWHG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3501
swis2-VHDL20_DWHG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 3342
swis2-VHDL20_DWHG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3866
swis2-VHDL20_DWHG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 4105
swis2-VHDL20_DWHG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 4594
swis2-VHDL20_DWHG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 4561
swis2-VHDL20_DWHH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 4002
swis2-VHDL20_DWHH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:06 3087
swis2-VHDL20_DWHH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2886
swis2-VHDL20_DWHH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2737
swis2-VHDL20_DWHH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3432
swis2-VHDL20_DWHH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3221
swis2-VHDL20_DWHH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3563
swis2-VHDL20_DWHH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3743
swis2-VHDL20_DWLG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3118
swis2-VHDL20_DWLG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 2654
swis2-VHDL20_DWLG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2514
swis2-VHDL20_DWLG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2685
swis2-VHDL20_DWLG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2793
swis2-VHDL20_DWLG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2480
swis2-VHDL20_DWLG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2917
swis2-VHDL20_DWLG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2695
swis2-VHDL20_DWLH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3184
swis2-VHDL20_DWLH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 2812
swis2-VHDL20_DWLH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2611
swis2-VHDL20_DWLH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2581
swis2-VHDL20_DWLH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2835
swis2-VHDL20_DWLH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2866
swis2-VHDL20_DWLH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3029
swis2-VHDL20_DWLH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2664
swis2-VHDL20_DWLI_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3171
swis2-VHDL20_DWLI_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 2724
swis2-VHDL20_DWLI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2582
swis2-VHDL20_DWLI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2613
swis2-VHDL20_DWLI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2832
swis2-VHDL20_DWLI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2514
swis2-VHDL20_DWLI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2620
swis2-VHDL20_DWLI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2308
swis2-VHDL20_DWMG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 4040
swis2-VHDL20_DWMG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3167
swis2-VHDL20_DWMG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3456
swis2-VHDL20_DWMG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3722
swis2-VHDL20_DWMG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3965
swis2-VHDL20_DWMG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3812
swis2-VHDL20_DWMG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 4023
swis2-VHDL20_DWMG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3533
swis2-VHDL20_DWMO_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3926
swis2-VHDL20_DWMO_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 2957
swis2-VHDL20_DWMO_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3264
swis2-VHDL20_DWMO_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3419
swis2-VHDL20_DWMO_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3634
swis2-VHDL20_DWMO_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3483
swis2-VHDL20_DWMO_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 3652
swis2-VHDL20_DWMO_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3296
swis2-VHDL20_DWMP_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 4006
swis2-VHDL20_DWMP_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3158
swis2-VHDL20_DWMP_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3489
swis2-VHDL20_DWMP_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3692
swis2-VHDL20_DWMP_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3584
swis2-VHDL20_DWMP_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 3972
swis2-VHDL20_DWMP_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3500
swis2-VHDL20_DWPG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3383
swis2-VHDL20_DWPG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 15:08:07 3522
swis2-VHDL20_DWPG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3342
swis2-VHDL20_DWPG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2669
swis2-VHDL20_DWPG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2699
swis2-VHDL20_DWPG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2658
swis2-VHDL20_DWPG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3142
swis2-VHDL20_DWPG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2883
swis2-VHDL20_DWPG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2907
swis2-VHDL20_DWPH_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:06 3860
swis2-VHDL20_DWPH_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 15:08:47 3679
swis2-VHDL20_DWPH_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:04 3628
swis2-VHDL20_DWPH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3087
swis2-VHDL20_DWPH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2936
swis2-VHDL20_DWPH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 3190
swis2-VHDL20_DWPH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3183
swis2-VHDL20_DWPH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2912
swis2-VHDL20_DWPH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2886
swis2-VHDL20_DWSG_050800-2602050800-dsw--0-ia5 05-Feb-2026 09:45:02 3375
swis2-VHDL20_DWSG_050800_COR-2602050800-dsw--0-ia5 05-Feb-2026 11:11:01 3292
swis2-VHDL20_DWSG_051300-2602051300-dsw--0-ia5 05-Feb-2026 14:45:01 3359
swis2-VHDL20_DWSG_051800-2602051800-dsw--0-ia5 05-Feb-2026 19:45:06 3153
swis2-VHDL20_DWSG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:06 3126
swis2-VHDL20_DWSG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3130
swis2-VHDL20_DWSG_060400_COR-2602060400-dsw--0-ia5 06-Feb-2026 06:36:24 3259
swis2-VHDL20_DWSG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3388
swis2-VHDL20_DWSG_061300-2602061300-dsw--0-ia5 06-Feb-2026 14:45:04 3247
swis2-VHDL20_DWSG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2805
swis2-VHDL20_DWSG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 2963
swis2-VHDL20_DWSG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:02 2829
wst04-VHDL20_DWEG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 227461
wst04-VHDL20_DWEG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:12 226280
wst04-VHDL20_DWEG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 226759
wst04-VHDL20_DWEG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:20 226560
wst04-VHDL20_DWEG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 227127
wst04-VHDL20_DWEG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 224436
wst04-VHDL20_DWEG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 225413
wst04-VHDL20_DWEG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 224064
wst04-VHDL20_DWEH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 229213
wst04-VHDL20_DWEH_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:12 228532
wst04-VHDL20_DWEH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 229077
wst04-VHDL20_DWEH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:18 228513
wst04-VHDL20_DWEH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 228733
wst04-VHDL20_DWEH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 225291
wst04-VHDL20_DWEH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 225737
wst04-VHDL20_DWEH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:26 224884
wst04-VHDL20_DWEI_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:16 319010
wst04-VHDL20_DWEI_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:12 318430
wst04-VHDL20_DWEI_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 318477
wst04-VHDL20_DWEI_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:20 318362
wst04-VHDL20_DWEI_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 318447
wst04-VHDL20_DWEI_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 316284
wst04-VHDL20_DWEI_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 316919
wst04-VHDL20_DWEI_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 316299
wst04-VHDL20_DWHG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:23 301317
wst04-VHDL20_DWHG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:22 299228
wst04-VHDL20_DWHG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 299327
wst04-VHDL20_DWHG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:11 298945
wst04-VHDL20_DWHG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 299715
wst04-VHDL20_DWHG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 302047
wst04-VHDL20_DWHG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 303410
wst04-VHDL20_DWHG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:11 303394
wst04-VHDL20_DWHH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:23 291444
wst04-VHDL20_DWHH_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:22 289992
wst04-VHDL20_DWHH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 290088
wst04-VHDL20_DWHH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:11 289702
wst04-VHDL20_DWHH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 290061
wst04-VHDL20_DWHH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 287636
wst04-VHDL20_DWHH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 288094
wst04-VHDL20_DWHH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:11 288344
wst04-VHDL20_DWLG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 302732
wst04-VHDL20_DWLG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:22 302336
wst04-VHDL20_DWLG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 301896
wst04-VHDL20_DWLG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 301820
wst04-VHDL20_DWLG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 302056
wst04-VHDL20_DWLG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:26 295617
wst04-VHDL20_DWLG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 296111
wst04-VHDL20_DWLG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 295814
wst04-VHDL20_DWLH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 297751
wst04-VHDL20_DWLH_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:22 297518
wst04-VHDL20_DWLH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 297097
wst04-VHDL20_DWLH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 296826
wst04-VHDL20_DWLH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:32 296967
wst04-VHDL20_DWLH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 295245
wst04-VHDL20_DWLH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:26 295539
wst04-VHDL20_DWLH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 295353
wst04-VHDL20_DWLI_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 289297
wst04-VHDL20_DWLI_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:26 288864
wst04-VHDL20_DWLI_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:26 288550
wst04-VHDL20_DWLI_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 288709
wst04-VHDL20_DWLI_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 288875
wst04-VHDL20_DWLI_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 290005
wst04-VHDL20_DWLI_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 290046
wst04-VHDL20_DWLI_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 289553
wst04-VHDL20_DWMG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 502337
wst04-VHDL20_DWMG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:16 500525
wst04-VHDL20_DWMG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 500585
wst04-VHDL20_DWMG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:16 500552
wst04-VHDL20_DWMG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:21 501515
wst04-VHDL20_DWMG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 499695
wst04-VHDL20_DWMG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 500460
wst04-VHDL20_DWMG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:16 499313
wst04-VHDL20_DWMO_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 400823
wst04-VHDL20_DWMO_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:16 399473
wst04-VHDL20_DWMO_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 400036
wst04-VHDL20_DWMO_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:16 400432
wst04-VHDL20_DWMO_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 400266
wst04-VHDL20_DWMO_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 402236
wst04-VHDL20_DWMO_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 402499
wst04-VHDL20_DWMO_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:16 402414
wst04-VHDL20_DWMP_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 537755
wst04-VHDL20_DWMP_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:16 535352
wst04-VHDL20_DWMP_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 534608
wst04-VHDL20_DWMP_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:22 535556
wst04-VHDL20_DWMP_060400_COR-2602060400-omedes-..> 06-Feb-2026 11:48:52 523189
wst04-VHDL20_DWMP_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 536571
wst04-VHDL20_DWMP_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 524042
wst04-VHDL20_DWMP_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 523596
wst04-VHDL20_DWMP_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 523948
wst04-VHDL20_DWPG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:33 351205
wst04-VHDL20_DWPG_050800_COR-2602050800-omedes-..> 05-Feb-2026 15:05:46 350716
wst04-VHDL20_DWPG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:26 305598
wst04-VHDL20_DWPG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:26 304457
wst04-VHDL20_DWPG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:31 304420
wst04-VHDL20_DWPG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:32 348915
wst04-VHDL20_DWPG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:26 306531
wst04-VHDL20_DWPG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:26 306270
wst04-VHDL20_DWPG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:31 306069
wst04-VHDL20_DWPH_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:27 268838
wst04-VHDL20_DWPH_050800_COR-2602050800-omedes-..> 05-Feb-2026 15:06:26 268327
wst04-VHDL20_DWPH_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:22 267347
wst04-VHDL20_DWPH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 221090
wst04-VHDL20_DWPH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:31 220775
wst04-VHDL20_DWPH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 265879
wst04-VHDL20_DWPH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 266076
wst04-VHDL20_DWPH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 220611
wst04-VHDL20_DWPH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:31 220830
wst04-VHDL20_DWSG_050800-2602050800-omedes--0.pdf 05-Feb-2026 09:45:12 326201
wst04-VHDL20_DWSG_050800_COR-2602050800-omedes-..> 05-Feb-2026 11:11:07 326198
wst04-VHDL20_DWSG_051300-2602051300-omedes--0.pdf 05-Feb-2026 14:45:12 326801
wst04-VHDL20_DWSG_051800-2602051800-omedes--0.pdf 05-Feb-2026 19:45:12 326063
wst04-VHDL20_DWSG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 325642
wst04-VHDL20_DWSG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:12 326162
wst04-VHDL20_DWSG_060400_COR-2602060400-omedes-..> 06-Feb-2026 06:36:24 326177
wst04-VHDL20_DWSG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 326295
wst04-VHDL20_DWSG_061300-2602061300-omedes--0.pdf 06-Feb-2026 14:45:12 329394
wst04-VHDL20_DWSG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:12 328994
wst04-VHDL20_DWSG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 328849
wst04-VHDL20_DWSG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:12 328690