Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Jan-2026 13:37:18 4127
FPDL13_DWMZ_280600 28-Jan-2026 13:52:19 3702
SXDL31_DWAV_270800 27-Jan-2026 09:21:30 13555
SXDL31_DWAV_271800 27-Jan-2026 18:10:25 8766
SXDL31_DWAV_280800 28-Jan-2026 08:15:58 9482
SXDL31_DWAV_281800 28-Jan-2026 17:44:01 6513
SXDL31_DWAV_LATEST 28-Jan-2026 17:44:01 6513
SXDL33_DWAV_270000 27-Jan-2026 10:36:06 8552
SXDL33_DWAV_280000 28-Jan-2026 10:56:59 11613
SXDL33_DWAV_LATEST 28-Jan-2026 10:56:59 11613
ber01-FWDL39_DWMS_271230-2601271230-dsw--0-ia5 27-Jan-2026 12:52:07 1795
ber01-FWDL39_DWMS_281230-2601281230-dsw--0-ia5 28-Jan-2026 12:38:37 2120
ber01-VHDL13_DWEH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3835
ber01-VHDL13_DWEH_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:17 3884
ber01-VHDL13_DWEH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:28:23 3949
ber01-VHDL13_DWEH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:17 3949
ber01-VHDL13_DWEH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 3961
ber01-VHDL13_DWEH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:11 3771
ber01-VHDL13_DWEH_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:12 3912
ber01-VHDL13_DWEH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:16 4068
ber01-VHDL13_DWEH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:17 3640
ber01-VHDL13_DWHG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3779
ber01-VHDL13_DWHG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3789
ber01-VHDL13_DWHG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 3229
ber01-VHDL13_DWHG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3966
ber01-VHDL13_DWHG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3500
ber01-VHDL13_DWHG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3500
ber01-VHDL13_DWHG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:10 3850
ber01-VHDL13_DWHG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:08 3183
ber01-VHDL13_DWHH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3429
ber01-VHDL13_DWHH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 3429
ber01-VHDL13_DWHH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 2907
ber01-VHDL13_DWHH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3136
ber01-VHDL13_DWHH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 2969
ber01-VHDL13_DWHH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 2969
ber01-VHDL13_DWHH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:10 3128
ber01-VHDL13_DWHH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:08 2922
ber01-VHDL13_DWLG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2973
ber01-VHDL13_DWLG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2840
ber01-VHDL13_DWLG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 2888
ber01-VHDL13_DWLG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2539
ber01-VHDL13_DWLG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2434
ber01-VHDL13_DWLG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2434
ber01-VHDL13_DWLG_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:34:51 2985
ber01-VHDL13_DWLG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2920
ber01-VHDL13_DWLG_280800_COR-2601280800-dsw--0-ia5 28-Jan-2026 11:00:26 3062
ber01-VHDL13_DWLG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2635
ber01-VHDL13_DWLH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2906
ber01-VHDL13_DWLH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2589
ber01-VHDL13_DWLH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:08 2644
ber01-VHDL13_DWLH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2412
ber01-VHDL13_DWLH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2355
ber01-VHDL13_DWLH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2355
ber01-VHDL13_DWLH_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:34:41 2808
ber01-VHDL13_DWLH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2815
ber01-VHDL13_DWLH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2433
ber01-VHDL13_DWLI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2592
ber01-VHDL13_DWLI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2644
ber01-VHDL13_DWLI_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 2551
ber01-VHDL13_DWLI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2062
ber01-VHDL13_DWLI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 1962
ber01-VHDL13_DWLI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 1962
ber01-VHDL13_DWLI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:35:04 2411
ber01-VHDL13_DWLI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2750
ber01-VHDL13_DWLI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2226
ber01-VHDL13_DWMG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:08 4013
ber01-VHDL13_DWMG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3642
ber01-VHDL13_DWMG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:08 3934
ber01-VHDL13_DWMG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3381
ber01-VHDL13_DWMG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3528
ber01-VHDL13_DWMG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 3248
ber01-VHDL13_DWMG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3722
ber01-VHDL13_DWMG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3072
ber01-VHDL13_DWMO_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3666
ber01-VHDL13_DWMO_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 3312
ber01-VHDL13_DWMO_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:08 3453
ber01-VHDL13_DWMO_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2969
ber01-VHDL13_DWMO_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3299
ber01-VHDL13_DWMO_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 3229
ber01-VHDL13_DWMO_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3604
ber01-VHDL13_DWMO_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3615
ber01-VHDL13_DWMO_281800_COR-2601281800-dsw--0-ia5 28-Jan-2026 19:34:59 2963
ber01-VHDL13_DWMP_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3670
ber01-VHDL13_DWMP_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3670
ber01-VHDL13_DWMP_270400_COR-2601270400-dsw--0-ia5 27-Jan-2026 07:11:52 3507
ber01-VHDL13_DWMP_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:08 3503
ber01-VHDL13_DWMP_270800_COR-2601270800-dsw--0-ia5 27-Jan-2026 09:33:37 3311
ber01-VHDL13_DWMP_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3074
ber01-VHDL13_DWMP_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3240
ber01-VHDL13_DWMP_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 2908
ber01-VHDL13_DWMP_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3189
ber01-VHDL13_DWMP_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2845
ber01-VHDL13_DWOG_270300-2601270300-dsw--0-ia5 27-Jan-2026 04:00:01 4783
ber01-VHDL13_DWOG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:52:12 5270
ber01-VHDL13_DWOG_270800_COR-2601270800-dsw--0-ia5 27-Jan-2026 15:05:29 6007
ber01-VHDL13_DWOG_271700-2601271700-dsw--0-ia5 27-Jan-2026 19:00:02 6162
ber01-VHDL13_DWOG_280300-2601280300-dsw--0-ia5 28-Jan-2026 04:00:02 5464
ber01-VHDL13_DWOG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 5688
ber01-VHDL13_DWOG_281700-2601281700-dsw--0-ia5 28-Jan-2026 19:00:06 4933
ber01-VHDL13_DWOH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3671
ber01-VHDL13_DWOH_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:22 3535
ber01-VHDL13_DWOH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:28:23 3726
ber01-VHDL13_DWOH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:11 3720
ber01-VHDL13_DWOH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 3481
ber01-VHDL13_DWOH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:11 3503
ber01-VHDL13_DWOH_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:16 3510
ber01-VHDL13_DWOH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:16 3455
ber01-VHDL13_DWOH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:11 3308
ber01-VHDL13_DWOI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3068
ber01-VHDL13_DWOI_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:22 3029
ber01-VHDL13_DWOI_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:28:17 2958
ber01-VHDL13_DWOI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:11 2952
ber01-VHDL13_DWOI_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 2899
ber01-VHDL13_DWOI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:17 2634
ber01-VHDL13_DWOI_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:16 2584
ber01-VHDL13_DWOI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:07:31 2592
ber01-VHDL13_DWOI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:12 2669
ber01-VHDL13_DWOI_280800_COR-2601280800-dsw--0-ia5 28-Jan-2026 06:06:17 2598
ber01-VHDL13_DWOI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:11 3132
ber01-VHDL13_DWON_270244-2601270244-dsw--0-ia5 27-Jan-2026 02:44:37 3971
ber01-VHDL13_DWON_270629-2601270629-dsw--0-ia5 27-Jan-2026 06:29:21 4233
ber01-VHDL13_DWON_270715-2601270715-dsw--0-ia5 27-Jan-2026 07:15:57 4159
ber01-VHDL13_DWON_270853-2601270853-dsw--0-ia5 27-Jan-2026 08:53:47 4159
ber01-VHDL13_DWON_270951-2601270951-dsw--0-ia5 27-Jan-2026 09:51:56 4159
ber01-VHDL13_DWON_271242-2601271242-dsw--0-ia5 27-Jan-2026 12:42:11 3897
ber01-VHDL13_DWON_271505-2601271505-dsw--0-ia5 27-Jan-2026 15:05:29 3897
ber01-VHDL13_DWON_271531-2601271531-dsw--0-ia5 27-Jan-2026 15:31:52 4260
ber01-VHDL13_DWON_271836-2601271836-dsw--0-ia5 27-Jan-2026 18:36:51 4851
ber01-VHDL13_DWON_272001-2601272001-dsw--0-ia5 27-Jan-2026 20:01:46 4290
ber01-VHDL13_DWON_280016-2601280016-dsw--0-ia5 28-Jan-2026 00:16:27 3869
ber01-VHDL13_DWON_280354-2601280354-dsw--0-ia5 28-Jan-2026 03:54:17 3869
ber01-VHDL13_DWON_280629-2601280629-dsw--0-ia5 28-Jan-2026 06:29:16 4252
ber01-VHDL13_DWON_280725-2601280725-dsw--0-ia5 28-Jan-2026 07:25:23 4440
ber01-VHDL13_DWON_280726-2601280726-dsw--0-ia5 28-Jan-2026 07:26:47 4440
ber01-VHDL13_DWON_280919-2601280919-dsw--0-ia5 28-Jan-2026 09:19:57 4493
ber01-VHDL13_DWON_281559-2601281559-dsw--0-ia5 28-Jan-2026 16:00:02 3735
ber01-VHDL13_DWON_281800-2601281800-dsw--0-ia5 28-Jan-2026 18:00:36 3735
ber01-VHDL13_DWON_281818-2601281818-dsw--0-ia5 28-Jan-2026 18:18:47 3729
ber01-VHDL13_DWON_282122-2601282122-dsw--0-ia5 28-Jan-2026 21:22:17 3732
ber01-VHDL13_DWPG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2300
ber01-VHDL13_DWPG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2210
ber01-VHDL13_DWPG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 2037
ber01-VHDL13_DWPG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2037
ber01-VHDL13_DWPG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 1785
ber01-VHDL13_DWPG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2006
ber01-VHDL13_DWPG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2104
ber01-VHDL13_DWPG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2037
ber01-VHDL13_DWPH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2986
ber01-VHDL13_DWPH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2450
ber01-VHDL13_DWPH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:06 2367
ber01-VHDL13_DWPH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2367
ber01-VHDL13_DWPH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2085
ber01-VHDL13_DWPH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2325
ber01-VHDL13_DWPH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2451
ber01-VHDL13_DWPH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2283
ber01-VHDL13_DWSG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2931
ber01-VHDL13_DWSG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2931
ber01-VHDL13_DWSG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:30:04 2715
ber01-VHDL13_DWSG_270800_COR-2601270800-dsw--0-ia5 27-Jan-2026 14:35:01 3975
ber01-VHDL13_DWSG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:01 4099
ber01-VHDL13_DWSG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 3441
ber01-VHDL13_DWSG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3441
ber01-VHDL13_DWSG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3169
ber01-VHDL13_DWSG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3954
ber01-VHDL17_DWOG_271200-2601271200-dsw--0-ia5 27-Jan-2026 12:46:01 2942
ber01-VHDL17_DWOG_281200-2601281200-dsw--0-ia5 28-Jan-2026 12:13:27 3401
swis2-VHDL20_DWEG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4034
swis2-VHDL20_DWEG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 4115
swis2-VHDL20_DWEG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:08 4552
swis2-VHDL20_DWEG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 4063
swis2-VHDL20_DWEG_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 4067
swis2-VHDL20_DWEG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 3989
swis2-VHDL20_DWEG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3918
swis2-VHDL20_DWEG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 4081
swis2-VHDL20_DWEG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3812
swis2-VHDL20_DWEH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4229
swis2-VHDL20_DWEH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 4339
swis2-VHDL20_DWEH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:08 4660
swis2-VHDL20_DWEH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 4435
swis2-VHDL20_DWEH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 4439
swis2-VHDL20_DWEH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 4215
swis2-VHDL20_DWEH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 4307
swis2-VHDL20_DWEH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4694
swis2-VHDL20_DWEH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 4075
swis2-VHDL20_DWEI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 3431
swis2-VHDL20_DWEI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 3569
swis2-VHDL20_DWEI_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:08 3760
swis2-VHDL20_DWEI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 3435
swis2-VHDL20_DWEI_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 3439
swis2-VHDL20_DWEI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 2995
swis2-VHDL20_DWEI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3004
swis2-VHDL20_DWEI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3306
swis2-VHDL20_DWEI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3550
swis2-VHDL20_DWHG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3965
swis2-VHDL20_DWHG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3972
swis2-VHDL20_DWHG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:02 4142
swis2-VHDL20_DWHG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 4149
swis2-VHDL20_DWHG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3686
swis2-VHDL20_DWHG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3683
swis2-VHDL20_DWHG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4713
swis2-VHDL20_DWHG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3366
swis2-VHDL20_DWHH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3615
swis2-VHDL20_DWHH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3615
swis2-VHDL20_DWHH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:02 3723
swis2-VHDL20_DWHH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 3322
swis2-VHDL20_DWHH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3155
swis2-VHDL20_DWHH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3155
swis2-VHDL20_DWHH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3802
swis2-VHDL20_DWHH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3108
swis2-VHDL20_DWLG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3418
swis2-VHDL20_DWLG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3334
swis2-VHDL20_DWLG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 3567
swis2-VHDL20_DWLG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3033
swis2-VHDL20_DWLG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2928
swis2-VHDL20_DWLG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2844
swis2-VHDL20_DWLG_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:49:02 3415
swis2-VHDL20_DWLG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3575
swis2-VHDL20_DWLG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3064
swis2-VHDL20_DWLH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3395
swis2-VHDL20_DWLH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3106
swis2-VHDL20_DWLH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 3359
swis2-VHDL20_DWLH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2929
swis2-VHDL20_DWLH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2888
swis2-VHDL20_DWLH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2781
swis2-VHDL20_DWLH_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:48:32 3249
swis2-VHDL20_DWLH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3455
swis2-VHDL20_DWLH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2874
swis2-VHDL20_DWLI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3040
swis2-VHDL20_DWLI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3197
swis2-VHDL20_DWLI_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 3288
swis2-VHDL20_DWLI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2615
swis2-VHDL20_DWLI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2515
swis2-VHDL20_DWLI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2345
swis2-VHDL20_DWLI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:49:26 2819
swis2-VHDL20_DWLI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3351
swis2-VHDL20_DWLI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2632
swis2-VHDL20_DWMG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4501
swis2-VHDL20_DWMG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 4152
swis2-VHDL20_DWMG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 4636
swis2-VHDL20_DWMG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3990
swis2-VHDL20_DWMG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 4041
swis2-VHDL20_DWMG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3641
swis2-VHDL20_DWMG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4387
swis2-VHDL20_DWMG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3528
swis2-VHDL20_DWMO_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4136
swis2-VHDL20_DWMO_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 3782
swis2-VHDL20_DWMO_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 4141
swis2-VHDL20_DWMO_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3582
swis2-VHDL20_DWMO_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3846
swis2-VHDL20_DWMO_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3629
swis2-VHDL20_DWMO_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4280
swis2-VHDL20_DWMO_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3422
swis2-VHDL20_DWMP_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4110
swis2-VHDL20_DWMP_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 4151
swis2-VHDL20_DWMP_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:08 4039
swis2-VHDL20_DWMP_271300_COR-2601271300-dsw--0-ia5 27-Jan-2026 07:14:36 3991
swis2-VHDL20_DWMP_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3638
swis2-VHDL20_DWMP_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3733
swis2-VHDL20_DWMP_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3304
swis2-VHDL20_DWMP_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3911
swis2-VHDL20_DWMP_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3233
swis2-VHDL20_DWPG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 2849
swis2-VHDL20_DWPG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 2596
swis2-VHDL20_DWPG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 2681
swis2-VHDL20_DWPG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2681
swis2-VHDL20_DWPG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2176
swis2-VHDL20_DWPG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2518
swis2-VHDL20_DWPG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 2922
swis2-VHDL20_DWPG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2855
swis2-VHDL20_DWPH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3492
swis2-VHDL20_DWPH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3010
swis2-VHDL20_DWPH_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 3183
swis2-VHDL20_DWPH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3183
swis2-VHDL20_DWPH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2647
swis2-VHDL20_DWPH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2837
swis2-VHDL20_DWPH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3267
swis2-VHDL20_DWPH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3099
swis2-VHDL20_DWSG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:02 3442
swis2-VHDL20_DWSG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:06 3394
swis2-VHDL20_DWSG_270800-2601270800-dsw--0-ia5 27-Jan-2026 09:45:06 3343
swis2-VHDL20_DWSG_270800_COR-2601270800-dsw--0-ia5 27-Jan-2026 14:35:01 4205
swis2-VHDL20_DWSG_271300-2601271300-dsw--0-ia5 27-Jan-2026 14:45:04 4441
swis2-VHDL20_DWSG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 4631
swis2-VHDL20_DWSG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3925
swis2-VHDL20_DWSG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3855
swis2-VHDL20_DWSG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3744
swis2-VHDL20_DWSG_281300-2601281300-dsw--0-ia5 28-Jan-2026 14:45:01 4269
swis2-VHDL20_DWSG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 4519
wst04-VHDL20_DWEG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:18 224684
wst04-VHDL20_DWEG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:22 223736
wst04-VHDL20_DWEG_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:18 226437
wst04-VHDL20_DWEG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 226416
wst04-VHDL20_DWEG_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 226416
wst04-VHDL20_DWEG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 226015
wst04-VHDL20_DWEG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 225438
wst04-VHDL20_DWEG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 225828
wst04-VHDL20_DWEG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 224830
wst04-VHDL20_DWEH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:18 224975
wst04-VHDL20_DWEH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:22 224138
wst04-VHDL20_DWEH_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:12 229164
wst04-VHDL20_DWEH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 229785
wst04-VHDL20_DWEH_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 229785
wst04-VHDL20_DWEH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 229540
wst04-VHDL20_DWEH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:22 228993
wst04-VHDL20_DWEH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:22 229600
wst04-VHDL20_DWEH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 229123
wst04-VHDL20_DWEI_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:22 307631
wst04-VHDL20_DWEI_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:32 307228
wst04-VHDL20_DWEI_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:22 313200
wst04-VHDL20_DWEI_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 313481
wst04-VHDL20_DWEI_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 313481
wst04-VHDL20_DWEI_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 312949
wst04-VHDL20_DWEI_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 312789
wst04-VHDL20_DWEI_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 313615
wst04-VHDL20_DWEI_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 312909
wst04-VHDL20_DWHG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 298503
wst04-VHDL20_DWHG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:11 298650
wst04-VHDL20_DWHG_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:12 301766
wst04-VHDL20_DWHG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 300903
wst04-VHDL20_DWHG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 300593
wst04-VHDL20_DWHG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:13 300501
wst04-VHDL20_DWHG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 301308
wst04-VHDL20_DWHG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 299016
wst04-VHDL20_DWHH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 293855
wst04-VHDL20_DWHH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:11 293886
wst04-VHDL20_DWHH_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:12 293900
wst04-VHDL20_DWHH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 293185
wst04-VHDL20_DWHH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 292472
wst04-VHDL20_DWHH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:13 292415
wst04-VHDL20_DWHH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 297165
wst04-VHDL20_DWHH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 296412
wst04-VHDL20_DWLG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:36 301181
wst04-VHDL20_DWLG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:43 300811
wst04-VHDL20_DWLG_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:37 294086
wst04-VHDL20_DWLG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 293972
wst04-VHDL20_DWLG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:26 293902
wst04-VHDL20_DWLG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 293797
wst04-VHDL20_DWLG_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:46:51 294898
wst04-VHDL20_DWLG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 293053
wst04-VHDL20_DWLG_280800_COR-2601280800-omedes-..> 28-Jan-2026 11:02:21 293049
wst04-VHDL20_DWLG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 292294
wst04-VHDL20_DWLH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 295289
wst04-VHDL20_DWLH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:41 294620
wst04-VHDL20_DWLH_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:37 290244
wst04-VHDL20_DWLH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 290210
wst04-VHDL20_DWLH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 289881
wst04-VHDL20_DWLH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 289772
wst04-VHDL20_DWLH_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:46:11 290716
wst04-VHDL20_DWLH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 295848
wst04-VHDL20_DWLH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 295125
wst04-VHDL20_DWLI_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 296144
wst04-VHDL20_DWLI_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:47 296358
wst04-VHDL20_DWLI_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:41 290198
wst04-VHDL20_DWLI_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 289932
wst04-VHDL20_DWLI_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 289569
wst04-VHDL20_DWLI_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 289379
wst04-VHDL20_DWLI_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:48:12 290435
wst04-VHDL20_DWLI_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 301937
wst04-VHDL20_DWLI_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 300565
wst04-VHDL20_DWMG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:28 496985
wst04-VHDL20_DWMG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:28 496439
wst04-VHDL20_DWMG_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:33 510061
wst04-VHDL20_DWMG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 508206
wst04-VHDL20_DWMG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 507679
wst04-VHDL20_DWMG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 507542
wst04-VHDL20_DWMG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 513334
wst04-VHDL20_DWMG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 512415
wst04-VHDL20_DWMO_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:16 398876
wst04-VHDL20_DWMO_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:16 399188
wst04-VHDL20_DWMO_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:26 401632
wst04-VHDL20_DWMO_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:06 400163
wst04-VHDL20_DWMO_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 400475
wst04-VHDL20_DWMO_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:12 401113
wst04-VHDL20_DWMO_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 409774
wst04-VHDL20_DWMO_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 408815
wst04-VHDL20_DWMP_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:22 517600
wst04-VHDL20_DWMP_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:28 518831
wst04-VHDL20_DWMP_270400_COR-2601270400-omedes-..> 27-Jan-2026 07:14:01 519052
wst04-VHDL20_DWMP_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:31 545062
wst04-VHDL20_DWMP_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 543014
wst04-VHDL20_DWMP_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 541533
wst04-VHDL20_DWMP_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 542578
wst04-VHDL20_DWMP_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 550148
wst04-VHDL20_DWMP_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 549288
wst04-VHDL20_DWPG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 299619
wst04-VHDL20_DWPG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:31 299458
wst04-VHDL20_DWPG_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:41 339391
wst04-VHDL20_DWPG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 294805
wst04-VHDL20_DWPG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 294920
wst04-VHDL20_DWPG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:31 295120
wst04-VHDL20_DWPG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 348567
wst04-VHDL20_DWPG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:26 304442
wst04-VHDL20_DWPH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:26 217286
wst04-VHDL20_DWPH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:31 216521
wst04-VHDL20_DWPH_270800-2601270800-omedes--0.pdf 27-Jan-2026 09:45:37 264852
wst04-VHDL20_DWPH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 264863
wst04-VHDL20_DWPH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 220166
wst04-VHDL20_DWPH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:31 220286
wst04-VHDL20_DWPH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:20 267437
wst04-VHDL20_DWPH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 267292
wst04-VHDL20_DWSG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 314817
wst04-VHDL20_DWSG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:12 314958
wst04-VHDL20_DWSG_270800-2601270800-omedes--0.pdf 27-Jan-2026 14:35:15 321438
wst04-VHDL20_DWSG_270800_COR-2601270800-omedes-..> 27-Jan-2026 10:36:33 321207
wst04-VHDL20_DWSG_271300-2601271300-omedes--0.pdf 27-Jan-2026 14:45:11 322038
wst04-VHDL20_DWSG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:10 322030
wst04-VHDL20_DWSG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 322544
wst04-VHDL20_DWSG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:12 322403
wst04-VHDL20_DWSG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 328875
wst04-VHDL20_DWSG_281300-2601281300-omedes--0.pdf 28-Jan-2026 14:45:13 329982
wst04-VHDL20_DWSG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 329980