Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_160600 16-Nov-2025 14:30:32 13799
FPDL13_DWMZ_170600 17-Nov-2025 14:29:55 3387
SXDL31_DWAV_151800 15-Nov-2025 17:47:19 9497
SXDL31_DWAV_160800 16-Nov-2025 08:21:09 16814
SXDL31_DWAV_161800 16-Nov-2025 18:21:43 7704
SXDL31_DWAV_170800 17-Nov-2025 08:46:47 9673
SXDL31_DWAV_LATEST 17-Nov-2025 08:46:47 9673
SXDL33_DWAV_160000 16-Nov-2025 11:41:35 11335
SXDL33_DWAV_170000 17-Nov-2025 11:03:39 9165
SXDL33_DWAV_LATEST 17-Nov-2025 11:03:39 9165
ber01-FWDL39_DWMS_161230-2511161230-dsw--0-ia5 16-Nov-2025 12:33:52 1830
ber01-FWDL39_DWMS_171230-2511171230-dsw--0-ia5 17-Nov-2025 12:26:57 1839
ber01-VHDL13_DWEH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:12 2483
ber01-VHDL13_DWEH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:28:12 2448
ber01-VHDL13_DWEH_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:58:17 2648
ber01-VHDL13_DWEH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:28:16 3269
ber01-VHDL13_DWEH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:12 3546
ber01-VHDL13_DWEH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:11 3548
ber01-VHDL13_DWEH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3486
ber01-VHDL13_DWEH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:17 3380
ber01-VHDL13_DWEH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:57:02 3589
ber01-VHDL13_DWHG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2689
ber01-VHDL13_DWHG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:06 3738
ber01-VHDL13_DWHG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:07 3912
ber01-VHDL13_DWHG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:10 4254
ber01-VHDL13_DWHG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:11 4165
ber01-VHDL13_DWHG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:09 4319
ber01-VHDL13_DWHG_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:07:47 4307
ber01-VHDL13_DWHG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4303
ber01-VHDL13_DWHG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3940
ber01-VHDL13_DWHH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 3010
ber01-VHDL13_DWHH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:06 3782
ber01-VHDL13_DWHH_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:07 3785
ber01-VHDL13_DWHH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:10 4203
ber01-VHDL13_DWHH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:11 3815
ber01-VHDL13_DWHH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:09 3860
ber01-VHDL13_DWHH_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:07:11 3842
ber01-VHDL13_DWHH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 3841
ber01-VHDL13_DWHH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3793
ber01-VHDL13_DWLG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2470
ber01-VHDL13_DWLG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 2887
ber01-VHDL13_DWLG_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:59:57 2898
ber01-VHDL13_DWLG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2984
ber01-VHDL13_DWLG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2755
ber01-VHDL13_DWLG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3488
ber01-VHDL13_DWLG_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 3262
ber01-VHDL13_DWLG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3386
ber01-VHDL13_DWLH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2234
ber01-VHDL13_DWLH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 2869
ber01-VHDL13_DWLH_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:59:57 2866
ber01-VHDL13_DWLH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2885
ber01-VHDL13_DWLH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2825
ber01-VHDL13_DWLH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3223
ber01-VHDL13_DWLH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 3017
ber01-VHDL13_DWLH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3034
ber01-VHDL13_DWLI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2175
ber01-VHDL13_DWLI_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 2795
ber01-VHDL13_DWLI_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:59:57 2782
ber01-VHDL13_DWLI_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2789
ber01-VHDL13_DWLI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2638
ber01-VHDL13_DWLI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 2964
ber01-VHDL13_DWLI_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 2754
ber01-VHDL13_DWLI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 2753
ber01-VHDL13_DWMG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2866
ber01-VHDL13_DWMG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 3438
ber01-VHDL13_DWMG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:01 3377
ber01-VHDL13_DWMG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 3717
ber01-VHDL13_DWMG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3471
ber01-VHDL13_DWMG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3463
ber01-VHDL13_DWMG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3563
ber01-VHDL13_DWMG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:56:57 4201
ber01-VHDL13_DWMO_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2505
ber01-VHDL13_DWMO_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 2866
ber01-VHDL13_DWMO_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:01 3238
ber01-VHDL13_DWMO_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2935
ber01-VHDL13_DWMO_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3180
ber01-VHDL13_DWMO_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3289
ber01-VHDL13_DWMO_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:30:42 3368
ber01-VHDL13_DWMO_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3364
ber01-VHDL13_DWMO_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3279
ber01-VHDL13_DWMP_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 3137
ber01-VHDL13_DWMP_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 3421
ber01-VHDL13_DWMP_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:01 3376
ber01-VHDL13_DWMP_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 3204
ber01-VHDL13_DWMP_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3290
ber01-VHDL13_DWMP_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3290
ber01-VHDL13_DWMP_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:26:07 3106
ber01-VHDL13_DWMP_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3354
ber01-VHDL13_DWMP_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3587
ber01-VHDL13_DWOG_151700-2511151700-dsw--0-ia5 15-Nov-2025 19:00:02 3638
ber01-VHDL13_DWOG_160300-2511160300-dsw--0-ia5 16-Nov-2025 04:00:02 4996
ber01-VHDL13_DWOG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 4823
ber01-VHDL13_DWOG_161700-2511161700-dsw--0-ia5 16-Nov-2025 19:00:02 4877
ber01-VHDL13_DWOG_170300-2511170300-dsw--0-ia5 17-Nov-2025 04:00:01 5990
ber01-VHDL13_DWOG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 5345
ber01-VHDL13_DWOH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:12 2469
ber01-VHDL13_DWOH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:28:12 2716
ber01-VHDL13_DWOH_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:58:11 2714
ber01-VHDL13_DWOH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:28:16 3128
ber01-VHDL13_DWOH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:16 3404
ber01-VHDL13_DWOH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:11 3529
ber01-VHDL13_DWOH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3384
ber01-VHDL13_DWOH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:11 3030
ber01-VHDL13_DWOH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:57:02 3248
ber01-VHDL13_DWOI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:16 2483
ber01-VHDL13_DWOI_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:28:16 2569
ber01-VHDL13_DWOI_160400-2511160400-dsw--0-ia5 16-Nov-2025 05:58:17 2639
ber01-VHDL13_DWOI_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:28:12 2883
ber01-VHDL13_DWOI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:12 2822
ber01-VHDL13_DWOI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:17 3049
ber01-VHDL13_DWOI_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3014
ber01-VHDL13_DWOI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:11 2682
ber01-VHDL13_DWOI_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:56 2686
ber01-VHDL13_DWON_151531-2511151531-dsw--0-ia5 15-Nov-2025 15:31:35 4420
ber01-VHDL13_DWON_151840-2511151840-dsw--0-ia5 15-Nov-2025 18:40:27 3615
ber01-VHDL13_DWON_160339-2511160339-dsw--0-ia5 16-Nov-2025 03:39:42 4874
ber01-VHDL13_DWON_160623-2511160623-dsw--0-ia5 16-Nov-2025 06:23:51 5090
ber01-VHDL13_DWON_160807-2511160807-dsw--0-ia5 16-Nov-2025 08:07:41 5090
ber01-VHDL13_DWON_161347-2511161347-dsw--0-ia5 16-Nov-2025 13:47:21 5090
ber01-VHDL13_DWON_161519-2511161519-dsw--0-ia5 16-Nov-2025 15:19:07 4703
ber01-VHDL13_DWON_161829-2511161829-dsw--0-ia5 16-Nov-2025 18:29:17 3916
ber01-VHDL13_DWON_170339-2511170339-dsw--0-ia5 17-Nov-2025 03:39:27 4706
ber01-VHDL13_DWON_170629-2511170629-dsw--0-ia5 17-Nov-2025 06:29:52 4231
ber01-VHDL13_DWON_170727-2511170727-dsw--0-ia5 17-Nov-2025 07:27:56 4244
ber01-VHDL13_DWON_170753-2511170753-dsw--0-ia5 17-Nov-2025 07:53:15 4308
ber01-VHDL13_DWON_170919-2511170919-dsw--0-ia5 17-Nov-2025 09:19:30 4256
ber01-VHDL13_DWPG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2076
ber01-VHDL13_DWPG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:06 2594
ber01-VHDL13_DWPG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:03 2564
ber01-VHDL13_DWPG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2615
ber01-VHDL13_DWPG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2340
ber01-VHDL13_DWPG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 2450
ber01-VHDL13_DWPG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 2432
ber01-VHDL13_DWPG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 2433
ber01-VHDL13_DWPH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2261
ber01-VHDL13_DWPH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:06 2605
ber01-VHDL13_DWPH_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:03 2610
ber01-VHDL13_DWPH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 2701
ber01-VHDL13_DWPH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2723
ber01-VHDL13_DWPH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3138
ber01-VHDL13_DWPH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3119
ber01-VHDL13_DWPH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3121
ber01-VHDL13_DWSG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2625
ber01-VHDL13_DWSG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:30:02 2870
ber01-VHDL13_DWSG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:07 3180
ber01-VHDL13_DWSG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:30:03 3181
ber01-VHDL13_DWSG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2728
ber01-VHDL13_DWSG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3000
ber01-VHDL13_DWSG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 3075
ber01-VHDL13_DWSG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3367
ber01-VHDL17_DWOG_161200-2511161200-dsw--0-ia5 16-Nov-2025 12:04:31 3437
ber01-VHDL17_DWOG_171200-2511171200-dsw--0-ia5 17-Nov-2025 12:47:07 3126
swis2-VHDL20_DWEG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:02 2795
swis2-VHDL20_DWEG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:45:02 2992
swis2-VHDL20_DWEG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:15:01 3255
swis2-VHDL20_DWEG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:45:06 4064
swis2-VHDL20_DWEG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 3969
swis2-VHDL20_DWEG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4044
swis2-VHDL20_DWEG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3952
swis2-VHDL20_DWEG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3999
swis2-VHDL20_DWEG_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 3427
swis2-VHDL20_DWEH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:03 2837
swis2-VHDL20_DWEH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:45:02 2769
swis2-VHDL20_DWEH_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:15:07 3168
swis2-VHDL20_DWEH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:45:06 4165
swis2-VHDL20_DWEH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 4103
swis2-VHDL20_DWEH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4073
swis2-VHDL20_DWEH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3994
swis2-VHDL20_DWEH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4302
swis2-VHDL20_DWEH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 3767
swis2-VHDL20_DWEI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:02 2834
swis2-VHDL20_DWEI_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:45:02 2861
swis2-VHDL20_DWEI_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:15:07 3128
swis2-VHDL20_DWEI_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:45:06 3767
swis2-VHDL20_DWEI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 3311
swis2-VHDL20_DWEI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 3480
swis2-VHDL20_DWEI_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3551
swis2-VHDL20_DWEI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3636
swis2-VHDL20_DWEI_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 2865
swis2-VHDL20_DWHG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:07 2872
swis2-VHDL20_DWHG_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:45:02 3924
swis2-VHDL20_DWHG_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:07 4095
swis2-VHDL20_DWHG_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:45:02 4902
swis2-VHDL20_DWHG_160800_COR-2511160800-dsw--0-ia5 16-Nov-2025 10:56:21 4903
swis2-VHDL20_DWHG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 4348
swis2-VHDL20_DWHG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4505
swis2-VHDL20_DWHG_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:09:32 4493
swis2-VHDL20_DWHG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4486
swis2-VHDL20_DWHG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4516
swis2-VHDL20_DWHH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:07 3196
swis2-VHDL20_DWHH_160200-2511160200-dsw--0-ia5 16-Nov-2025 03:45:02 3968
swis2-VHDL20_DWHH_160400-2511160400-dsw--0-ia5 16-Nov-2025 06:00:07 3971
swis2-VHDL20_DWHH_160800-2511160800-dsw--0-ia5 16-Nov-2025 09:45:02 4745
swis2-VHDL20_DWHH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 4001
swis2-VHDL20_DWHH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4046
swis2-VHDL20_DWHH_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:08:48 4028
swis2-VHDL20_DWHH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4027
swis2-VHDL20_DWHH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4336
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wst04-VHDL20_DWEG_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:45:17 232643
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wst04-VHDL20_DWEG_170800_COR-2511170800-omedes-..> 17-Nov-2025 10:57:02 229244
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wst04-VHDL20_DWEH_170800_COR-2511170800-omedes-..> 17-Nov-2025 10:57:06 234716
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wst04-VHDL20_DWMO_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:22 423022
wst04-VHDL20_DWMO_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 423204
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wst04-VHDL20_DWMP_160400-2511160400-omedes--0.pdf 16-Nov-2025 06:15:21 545441
wst04-VHDL20_DWMP_160800-2511160800-omedes--0.pdf 16-Nov-2025 09:45:32 546420
wst04-VHDL20_DWMP_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:22 545950
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wst04-VHDL20_DWMP_170400_COR-2511170400-omedes-..> 17-Nov-2025 05:53:42 545983
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wst04-VHDL20_DWPG_160400-2511160400-omedes--0.pdf 16-Nov-2025 06:00:13 318576
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wst04-VHDL20_DWPH_160800-2511160800-omedes--0.pdf 16-Nov-2025 09:45:12 277023
wst04-VHDL20_DWPH_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:12 277819
wst04-VHDL20_DWPH_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:11 231956
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wst04-VHDL20_DWSG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 322839
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wst04-VHDL20_DWSG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:12 331312
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