Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Jan-2026 09:55:09 2436
FPDL13_DWMZ_040600 04-Jan-2026 13:51:10 2322
SXDL31_DWAV_030800 03-Jan-2026 07:56:01 11197
SXDL31_DWAV_031800 03-Jan-2026 18:02:29 11053
SXDL31_DWAV_040800 04-Jan-2026 08:11:33 14354
SXDL31_DWAV_041800 04-Jan-2026 17:22:59 6340
SXDL31_DWAV_LATEST 04-Jan-2026 17:22:59 6340
SXDL33_DWAV_030000 03-Jan-2026 10:43:43 8521
SXDL33_DWAV_040000 04-Jan-2026 11:24:39 7347
SXDL33_DWAV_LATEST 04-Jan-2026 11:24:39 7347
ber01-FWDL39_DWMS_031230-2601031230-dsw--0-ia5 03-Jan-2026 12:39:52 1850
ber01-FWDL39_DWMS_041230-2601041230-dsw--0-ia5 04-Jan-2026 12:34:51 890
ber01-VHDL13_DWEH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 4146
ber01-VHDL13_DWEH_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:17 4234
ber01-VHDL13_DWEH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:17 4022
ber01-VHDL13_DWEH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:17 3682
ber01-VHDL13_DWEH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:42 3682
ber01-VHDL13_DWEH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:28:12 3533
ber01-VHDL13_DWEH_040400-2601040400-dsw--0-ia5 04-Jan-2026 05:58:16 3491
ber01-VHDL13_DWEH_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:21 3720
ber01-VHDL13_DWEH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:28:16 3438
ber01-VHDL13_DWEH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:28:16 3286
ber01-VHDL13_DWHG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 4462
ber01-VHDL13_DWHG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4146
ber01-VHDL13_DWHG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 4812
ber01-VHDL13_DWHG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:10 3851
ber01-VHDL13_DWHG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 3882
ber01-VHDL13_DWHG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:07 3909
ber01-VHDL13_DWHG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 3881
ber01-VHDL13_DWHG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 3296
ber01-VHDL13_DWHH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 4137
ber01-VHDL13_DWHH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4137
ber01-VHDL13_DWHH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 4392
ber01-VHDL13_DWHH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:10 3783
ber01-VHDL13_DWHH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 4191
ber01-VHDL13_DWHH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:07 4235
ber01-VHDL13_DWHH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 4202
ber01-VHDL13_DWHH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 3647
ber01-VHDL13_DWLG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 2984
ber01-VHDL13_DWLG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 2905
ber01-VHDL13_DWLG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3191
ber01-VHDL13_DWLG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2921
ber01-VHDL13_DWLG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 3046
ber01-VHDL13_DWLG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2629
ber01-VHDL13_DWLG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 2337
ber01-VHDL13_DWLG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2309
ber01-VHDL13_DWLH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3285
ber01-VHDL13_DWLH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3381
ber01-VHDL13_DWLH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3653
ber01-VHDL13_DWLH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3309
ber01-VHDL13_DWLH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:54:46 3476
ber01-VHDL13_DWLH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 3320
ber01-VHDL13_DWLH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2893
ber01-VHDL13_DWLH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 2503
ber01-VHDL13_DWLH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2633
ber01-VHDL13_DWLI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 2768
ber01-VHDL13_DWLI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 2728
ber01-VHDL13_DWLI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 2982
ber01-VHDL13_DWLI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2900
ber01-VHDL13_DWLI_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2952
ber01-VHDL13_DWLI_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2932
ber01-VHDL13_DWLI_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 2443
ber01-VHDL13_DWLI_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2267
ber01-VHDL13_DWMG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3654
ber01-VHDL13_DWMG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3634
ber01-VHDL13_DWMG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 4056
ber01-VHDL13_DWMG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3543
ber01-VHDL13_DWMG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 3137
ber01-VHDL13_DWMG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 3193
ber01-VHDL13_DWMG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:00 2937
ber01-VHDL13_DWMG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2636
ber01-VHDL13_DWMO_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3152
ber01-VHDL13_DWMO_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3154
ber01-VHDL13_DWMO_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 3217
ber01-VHDL13_DWMO_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2983
ber01-VHDL13_DWMO_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2799
ber01-VHDL13_DWMO_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2876
ber01-VHDL13_DWMO_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:00 2734
ber01-VHDL13_DWMO_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2334
ber01-VHDL13_DWMP_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3209
ber01-VHDL13_DWMP_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3193
ber01-VHDL13_DWMP_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 3193
ber01-VHDL13_DWMP_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 09:43:21 3449
ber01-VHDL13_DWMP_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2802
ber01-VHDL13_DWMP_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2515
ber01-VHDL13_DWMP_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2709
ber01-VHDL13_DWMP_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:00 2380
ber01-VHDL13_DWMP_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2273
ber01-VHDL13_DWOG_030300-2601030300-dsw--0-ia5 03-Jan-2026 04:00:07 5716
ber01-VHDL13_DWOG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 5518
ber01-VHDL13_DWOG_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 13:23:01 5668
ber01-VHDL13_DWOG_031700-2601031700-dsw--0-ia5 03-Jan-2026 19:00:07 5362
ber01-VHDL13_DWOG_031700_COR-2601031700-dsw--0-ia5 03-Jan-2026 15:54:22 6330
ber01-VHDL13_DWOG_040300-2601040300-dsw--0-ia5 04-Jan-2026 04:00:01 4810
ber01-VHDL13_DWOG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:02 4843
ber01-VHDL13_DWOG_041700-2601041700-dsw--0-ia5 04-Jan-2026 19:00:00 5941
ber01-VHDL13_DWOG_041700_COR-2601041700-dsw--0-ia5 04-Jan-2026 18:26:46 5945
ber01-VHDL13_DWOH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 3567
ber01-VHDL13_DWOH_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:11 3824
ber01-VHDL13_DWOH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:17 3559
ber01-VHDL13_DWOH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:17 3623
ber01-VHDL13_DWOH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:42 3631
ber01-VHDL13_DWOH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:28:12 2887
ber01-VHDL13_DWOH_040400-2601040400-dsw--0-ia5 04-Jan-2026 05:58:12 2845
ber01-VHDL13_DWOH_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:21 3218
ber01-VHDL13_DWOH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:28:12 3231
ber01-VHDL13_DWOH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:28:12 3110
ber01-VHDL13_DWOI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 3235
ber01-VHDL13_DWOI_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:11 3299
ber01-VHDL13_DWOI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:11 3450
ber01-VHDL13_DWOI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:11 2800
ber01-VHDL13_DWOI_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:38 2774
ber01-VHDL13_DWOI_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:28:16 2910
ber01-VHDL13_DWOI_040400-2601040400-dsw--0-ia5 04-Jan-2026 05:58:16 2863
ber01-VHDL13_DWOI_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:28 3116
ber01-VHDL13_DWOI_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:28:18 3158
ber01-VHDL13_DWOI_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:28:12 3144
ber01-VHDL13_DWON_030421-2601030421-dsw--0-ia5 03-Jan-2026 04:21:52 3861
ber01-VHDL13_DWON_030629-2601030629-dsw--0-ia5 03-Jan-2026 06:29:57 3732
ber01-VHDL13_DWON_030708-2601030708-dsw--0-ia5 03-Jan-2026 07:08:17 3973
ber01-VHDL13_DWON_030732-2601030732-dsw--0-ia5 03-Jan-2026 07:32:06 3983
ber01-VHDL13_DWON_031322-2601031322-dsw--0-ia5 03-Jan-2026 13:22:31 3987
ber01-VHDL13_DWON_031547-2601031547-dsw--0-ia5 03-Jan-2026 15:47:37 3985
ber01-VHDL13_DWON_031554-2601031554-dsw--0-ia5 03-Jan-2026 15:54:12 4021
ber01-VHDL13_DWON_031811-2601031811-dsw--0-ia5 03-Jan-2026 18:11:27 3561
ber01-VHDL13_DWON_032120-2601032120-dsw--0-ia5 03-Jan-2026 21:20:07 3408
ber01-VHDL13_DWON_040225-2601040225-dsw--0-ia5 04-Jan-2026 02:25:53 3637
ber01-VHDL13_DWON_040619-2601040619-dsw--0-ia5 04-Jan-2026 06:19:52 3899
ber01-VHDL13_DWON_040724-2601040724-dsw--0-ia5 04-Jan-2026 07:24:52 3868
ber01-VHDL13_DWON_040902-2601040902-dsw--0-ia5 04-Jan-2026 09:02:27 3909
ber01-VHDL13_DWON_040959-2601040959-dsw--0-ia5 04-Jan-2026 09:59:36 3909
ber01-VHDL13_DWON_041535-2601041535-dsw--0-ia5 04-Jan-2026 15:35:18 3358
ber01-VHDL13_DWON_041826-2601041826-dsw--0-ia5 04-Jan-2026 18:26:16 4584
ber01-VHDL13_DWON_042032-2601042032-dsw--0-ia5 04-Jan-2026 20:32:31 4398
ber01-VHDL13_DWON_050019-2601050019-dsw--0-ia5 05-Jan-2026 00:19:56 4090
ber01-VHDL13_DWPG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3353
ber01-VHDL13_DWPG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3070
ber01-VHDL13_DWPG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3244
ber01-VHDL13_DWPG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2848
ber01-VHDL13_DWPG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2755
ber01-VHDL13_DWPG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2692
ber01-VHDL13_DWPG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 3014
ber01-VHDL13_DWPG_040800_COR-2601040800-dsw--0-ia5 04-Jan-2026 09:46:57 3116
ber01-VHDL13_DWPG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2208
ber01-VHDL13_DWPH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3179
ber01-VHDL13_DWPH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3137
ber01-VHDL13_DWPH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 2940
ber01-VHDL13_DWPH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3019
ber01-VHDL13_DWPH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2539
ber01-VHDL13_DWPH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:01 2559
ber01-VHDL13_DWPH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 3038
ber01-VHDL13_DWPH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2082
ber01-VHDL13_DWSG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3336
ber01-VHDL13_DWSG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:07 3174
ber01-VHDL13_DWSG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3182
ber01-VHDL13_DWSG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2913
ber01-VHDL13_DWSG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:30:05 2828
ber01-VHDL13_DWSG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:07 2908
ber01-VHDL13_DWSG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:30:08 2871
ber01-VHDL13_DWSG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:30:11 2755
ber01-VHDL17_DWOG_031200-2601031200-dsw--0-ia5 03-Jan-2026 12:28:20 2622
ber01-VHDL17_DWOG_041200-2601041200-dsw--0-ia5 04-Jan-2026 12:59:38 2755
swis2-VHDL20_DWEG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 4308
swis2-VHDL20_DWEG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 4433
swis2-VHDL20_DWEG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4473
swis2-VHDL20_DWEG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4358
swis2-VHDL20_DWEG_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:00:18 4368
swis2-VHDL20_DWEG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 3400
swis2-VHDL20_DWEG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:07 3684
swis2-VHDL20_DWEG_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:11 3688
swis2-VHDL20_DWEG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 4150
swis2-VHDL20_DWEG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3662
swis2-VHDL20_DWEH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 4853
swis2-VHDL20_DWEH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 4809
swis2-VHDL20_DWEH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4995
swis2-VHDL20_DWEH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4344
swis2-VHDL20_DWEH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:35:07 4736
swis2-VHDL20_DWEH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 4278
swis2-VHDL20_DWEH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:07 4278
swis2-VHDL20_DWEH_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:11 4282
swis2-VHDL20_DWEH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 4386
swis2-VHDL20_DWEH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3869
swis2-VHDL20_DWEI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3843
swis2-VHDL20_DWEI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 3874
swis2-VHDL20_DWEI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4117
swis2-VHDL20_DWEI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3372
swis2-VHDL20_DWEI_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:27 3376
swis2-VHDL20_DWEI_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 3453
swis2-VHDL20_DWEI_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:07 3613
swis2-VHDL20_DWEI_040400_COR-2601040400-dsw--0-ia5 04-Jan-2026 06:03:11 3617
swis2-VHDL20_DWEI_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 4124
swis2-VHDL20_DWEI_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3721
swis2-VHDL20_DWHG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4648
swis2-VHDL20_DWHG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4329
swis2-VHDL20_DWHG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 5521
swis2-VHDL20_DWHG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4034
swis2-VHDL20_DWHG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 4068
swis2-VHDL20_DWHG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:07 4092
swis2-VHDL20_DWHG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 4772
swis2-VHDL20_DWHG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3479
swis2-VHDL20_DWHH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4323
swis2-VHDL20_DWHH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:07 4323
swis2-VHDL20_DWHH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 5122
swis2-VHDL20_DWHH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3969
swis2-VHDL20_DWHH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 4377
swis2-VHDL20_DWHH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:07 4421
swis2-VHDL20_DWHH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 5319
swis2-VHDL20_DWHH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3833
swis2-VHDL20_DWLG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3429
swis2-VHDL20_DWLG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3332
swis2-VHDL20_DWLG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3795
swis2-VHDL20_DWLG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3324
swis2-VHDL20_DWLG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3452
swis2-VHDL20_DWLG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:11 3026
swis2-VHDL20_DWLG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 2906
swis2-VHDL20_DWLG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2700
swis2-VHDL20_DWLH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3734
swis2-VHDL20_DWLH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3843
swis2-VHDL20_DWLH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4247
swis2-VHDL20_DWLH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3719
swis2-VHDL20_DWLH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:55:41 3886
swis2-VHDL20_DWLH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3733
swis2-VHDL20_DWLH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:11 3299
swis2-VHDL20_DWLH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 3085
swis2-VHDL20_DWLH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3033
swis2-VHDL20_DWLI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3216
swis2-VHDL20_DWLI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3157
swis2-VHDL20_DWLI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3587
swis2-VHDL20_DWLI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3305
swis2-VHDL20_DWLI_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3360
swis2-VHDL20_DWLI_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:11 3331
swis2-VHDL20_DWLI_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 3013
swis2-VHDL20_DWLI_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2660
swis2-VHDL20_DWMG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4064
swis2-VHDL20_DWMG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 4065
swis2-VHDL20_DWMG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 4706
swis2-VHDL20_DWMG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 4043
swis2-VHDL20_DWMG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 3547
swis2-VHDL20_DWMG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:02 3622
swis2-VHDL20_DWMG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 3631
swis2-VHDL20_DWMG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3094
swis2-VHDL20_DWMO_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 3588
swis2-VHDL20_DWMO_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3591
swis2-VHDL20_DWMO_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 3876
swis2-VHDL20_DWMO_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 3468
swis2-VHDL20_DWMO_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 3245
swis2-VHDL20_DWMO_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:02 3309
swis2-VHDL20_DWMO_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 3438
swis2-VHDL20_DWMO_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2796
swis2-VHDL20_DWMP_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 3606
swis2-VHDL20_DWMP_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3584
swis2-VHDL20_DWMP_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 4124
swis2-VHDL20_DWMP_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 09:43:21 4128
swis2-VHDL20_DWMP_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 3334
swis2-VHDL20_DWMP_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:06 2951
swis2-VHDL20_DWMP_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:02 3138
swis2-VHDL20_DWMP_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:08 3036
swis2-VHDL20_DWMP_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2697
swis2-VHDL20_DWPG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3793
swis2-VHDL20_DWPG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3601
swis2-VHDL20_DWPG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3846
swis2-VHDL20_DWPG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3528
swis2-VHDL20_DWPG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3246
swis2-VHDL20_DWPG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:11 3080
swis2-VHDL20_DWPG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 3854
swis2-VHDL20_DWPG_040800_COR-2601040800-dsw--0-ia5 04-Jan-2026 09:48:15 3858
swis2-VHDL20_DWPG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2796
swis2-VHDL20_DWPH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3618
swis2-VHDL20_DWPH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3641
swis2-VHDL20_DWPH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3542
swis2-VHDL20_DWPH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3679
swis2-VHDL20_DWPH_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3009
swis2-VHDL20_DWPH_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:00:11 2949
swis2-VHDL20_DWPH_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 3722
swis2-VHDL20_DWPH_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 2659
swis2-VHDL20_DWSG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3816
swis2-VHDL20_DWSG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3589
swis2-VHDL20_DWSG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:04 3798
swis2-VHDL20_DWSG_031300-2601031300-dsw--0-ia5 03-Jan-2026 14:45:15 3580
swis2-VHDL20_DWSG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3330
swis2-VHDL20_DWSG_040200-2601040200-dsw--0-ia5 04-Jan-2026 03:45:01 3242
swis2-VHDL20_DWSG_040400-2601040400-dsw--0-ia5 04-Jan-2026 06:15:02 3322
swis2-VHDL20_DWSG_040800-2601040800-dsw--0-ia5 04-Jan-2026 09:45:05 3441
swis2-VHDL20_DWSG_041300-2601041300-dsw--0-ia5 04-Jan-2026 14:45:05 3357
swis2-VHDL20_DWSG_041800-2601041800-dsw--0-ia5 04-Jan-2026 19:45:04 3166
wst04-VHDL20_DWEG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 229920
wst04-VHDL20_DWEG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 229594
wst04-VHDL20_DWEG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:22 224604
wst04-VHDL20_DWEG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 223645
wst04-VHDL20_DWEG_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 223646
wst04-VHDL20_DWEG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:12 223549
wst04-VHDL20_DWEG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:27 223317
wst04-VHDL20_DWEG_040400_COR-2601040400-omedes-..> 04-Jan-2026 06:03:28 223317
wst04-VHDL20_DWEG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:17 226837
wst04-VHDL20_DWEG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:12 225390
wst04-VHDL20_DWEH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 224913
wst04-VHDL20_DWEH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:22 224398
wst04-VHDL20_DWEH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:22 225631
wst04-VHDL20_DWEH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 224498
wst04-VHDL20_DWEH_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 224557
wst04-VHDL20_DWEH_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:16 224780
wst04-VHDL20_DWEH_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:21 224736
wst04-VHDL20_DWEH_040400_COR-2601040400-omedes-..> 04-Jan-2026 06:03:21 224736
wst04-VHDL20_DWEH_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:21 227166
wst04-VHDL20_DWEH_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:16 226366
wst04-VHDL20_DWEI_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 314790
wst04-VHDL20_DWEI_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:22 314756
wst04-VHDL20_DWEI_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 307701
wst04-VHDL20_DWEI_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 306191
wst04-VHDL20_DWEI_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 306191
wst04-VHDL20_DWEI_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:16 306650
wst04-VHDL20_DWEI_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:27 307135
wst04-VHDL20_DWEI_040400_COR-2601040400-omedes-..> 04-Jan-2026 06:03:28 307135
wst04-VHDL20_DWEI_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:21 310801
wst04-VHDL20_DWEI_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:16 309969
wst04-VHDL20_DWHG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 307605
wst04-VHDL20_DWHG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:11 306521
wst04-VHDL20_DWHG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:16 307415
wst04-VHDL20_DWHG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 305691
wst04-VHDL20_DWHG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:12 305555
wst04-VHDL20_DWHG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:11 305250
wst04-VHDL20_DWHG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:27 309646
wst04-VHDL20_DWHG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:12 308055
wst04-VHDL20_DWHH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 309988
wst04-VHDL20_DWHH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:11 309988
wst04-VHDL20_DWHH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:12 299655
wst04-VHDL20_DWHH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 298725
wst04-VHDL20_DWHH_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:12 298596
wst04-VHDL20_DWHH_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:11 299164
wst04-VHDL20_DWHH_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:17 302991
wst04-VHDL20_DWHH_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:12 301379
wst04-VHDL20_DWLG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 304896
wst04-VHDL20_DWLG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 304818
wst04-VHDL20_DWLG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 298030
wst04-VHDL20_DWLG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 298083
wst04-VHDL20_DWLG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:26 298390
wst04-VHDL20_DWLG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:41 297171
wst04-VHDL20_DWLG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:31 304804
wst04-VHDL20_DWLG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:26 304151
wst04-VHDL20_DWLH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 304818
wst04-VHDL20_DWLH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 304742
wst04-VHDL20_DWLH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 301938
wst04-VHDL20_DWLH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 301076
wst04-VHDL20_DWLH_031800_COR-2601031800-omedes-..> 03-Jan-2026 20:55:17 301276
wst04-VHDL20_DWLH_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:26 301032
wst04-VHDL20_DWLH_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:41 300740
wst04-VHDL20_DWLH_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:31 297506
wst04-VHDL20_DWLH_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:22 296364
wst04-VHDL20_DWLI_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 297087
wst04-VHDL20_DWLI_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 297065
wst04-VHDL20_DWLI_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 298378
wst04-VHDL20_DWLI_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 298310
wst04-VHDL20_DWLI_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:20 298422
wst04-VHDL20_DWLI_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:41 298445
wst04-VHDL20_DWLI_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:31 296254
wst04-VHDL20_DWLI_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:26 295503
wst04-VHDL20_DWMG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 507376
wst04-VHDL20_DWMG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 507339
wst04-VHDL20_DWMG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 505750
wst04-VHDL20_DWMG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 502900
wst04-VHDL20_DWMG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:22 503099
wst04-VHDL20_DWMG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:17 503123
wst04-VHDL20_DWMG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:17 501474
wst04-VHDL20_DWMG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:18 500396
wst04-VHDL20_DWMO_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 404070
wst04-VHDL20_DWMO_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 404648
wst04-VHDL20_DWMO_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 403199
wst04-VHDL20_DWMO_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 402323
wst04-VHDL20_DWMO_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:18 401911
wst04-VHDL20_DWMO_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:17 402490
wst04-VHDL20_DWMO_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:12 405293
wst04-VHDL20_DWMO_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:22 403183
wst04-VHDL20_DWMP_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 529005
wst04-VHDL20_DWMP_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 530100
wst04-VHDL20_DWMP_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 526594
wst04-VHDL20_DWMP_030800_COR-2601030800-omedes-..> 03-Jan-2026 09:43:27 526594
wst04-VHDL20_DWMP_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 524525
wst04-VHDL20_DWMP_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:22 523183
wst04-VHDL20_DWMP_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:17 524276
wst04-VHDL20_DWMP_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:27 517176
wst04-VHDL20_DWMP_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:18 516112
wst04-VHDL20_DWPG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 316233
wst04-VHDL20_DWPG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:32 315759
wst04-VHDL20_DWPG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 351989
wst04-VHDL20_DWPG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:26 306898
wst04-VHDL20_DWPG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:26 306716
wst04-VHDL20_DWPG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:30 306202
wst04-VHDL20_DWPG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:31 345762
wst04-VHDL20_DWPG_040800_COR-2601040800-omedes-..> 04-Jan-2026 09:47:57 345762
wst04-VHDL20_DWPG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:22 299846
wst04-VHDL20_DWPH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 224935
wst04-VHDL20_DWPH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:32 224677
wst04-VHDL20_DWPH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 267875
wst04-VHDL20_DWPH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 268126
wst04-VHDL20_DWPH_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:20 222310
wst04-VHDL20_DWPH_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:00:30 221282
wst04-VHDL20_DWPH_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:27 266555
wst04-VHDL20_DWPH_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:22 264898
wst04-VHDL20_DWSG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 327683
wst04-VHDL20_DWSG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:11 327266
wst04-VHDL20_DWSG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:12 317335
wst04-VHDL20_DWSG_031300-2601031300-omedes--0.pdf 03-Jan-2026 14:45:15 317258
wst04-VHDL20_DWSG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 317239
wst04-VHDL20_DWSG_040200-2601040200-omedes--0.pdf 04-Jan-2026 03:45:18 317135
wst04-VHDL20_DWSG_040400-2601040400-omedes--0.pdf 04-Jan-2026 06:15:11 316802
wst04-VHDL20_DWSG_040800-2601040800-omedes--0.pdf 04-Jan-2026 09:45:12 315723
wst04-VHDL20_DWSG_041300-2601041300-omedes--0.pdf 04-Jan-2026 14:45:14 316072
wst04-VHDL20_DWSG_041800-2601041800-omedes--0.pdf 04-Jan-2026 19:45:12 315886