Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Jan-2026 14:30:01 7020
FPDL13_DWMZ_260600 26-Jan-2026 14:47:31 3451
SXDL31_DWAV_250800 25-Jan-2026 10:03:35 14981
SXDL31_DWAV_251800 25-Jan-2026 17:49:45 17844
SXDL31_DWAV_260800 26-Jan-2026 09:02:14 10593
SXDL31_DWAV_261800 26-Jan-2026 17:50:55 10175
SXDL31_DWAV_LATEST 26-Jan-2026 17:50:55 10175
SXDL33_DWAV_250000 25-Jan-2026 14:03:50 10600
SXDL33_DWAV_260000 26-Jan-2026 11:08:33 7334
SXDL33_DWAV_LATEST 26-Jan-2026 11:08:33 7334
ber01-FWDL39_DWMS_251230-2601251230-dsw--0-ia5 25-Jan-2026 12:19:42 1226
ber01-FWDL39_DWMS_261230-2601261230-dsw--0-ia5 26-Jan-2026 12:13:26 1555
ber01-VHDL13_DWEH_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3657
ber01-VHDL13_DWEH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 14:40:21 3635
ber01-VHDL13_DWEH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:28:22 3644
ber01-VHDL13_DWEH_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:32 3645
ber01-VHDL13_DWEH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:28:17 3858
ber01-VHDL13_DWEH_260400-2601260400-dsw--0-ia5 26-Jan-2026 05:58:18 3861
ber01-VHDL13_DWEH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:28:23 4274
ber01-VHDL13_DWEH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:28:22 4320
ber01-VHDL13_DWEH_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:22 3788
ber01-VHDL13_DWEH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3835
ber01-VHDL13_DWEH_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:17 3884
ber01-VHDL13_DWHG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4131
ber01-VHDL13_DWHG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 4211
ber01-VHDL13_DWHG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3490
ber01-VHDL13_DWHG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3490
ber01-VHDL13_DWHG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 4212
ber01-VHDL13_DWHG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 3369
ber01-VHDL13_DWHG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3779
ber01-VHDL13_DWHG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3789
ber01-VHDL13_DWHH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4280
ber01-VHDL13_DWHH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 3835
ber01-VHDL13_DWHH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3380
ber01-VHDL13_DWHH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3380
ber01-VHDL13_DWHH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 4371
ber01-VHDL13_DWHH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 3399
ber01-VHDL13_DWHH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3429
ber01-VHDL13_DWHH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 3429
ber01-VHDL13_DWLG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4033
ber01-VHDL13_DWLG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:01 3485
ber01-VHDL13_DWLG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3245
ber01-VHDL13_DWLG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3122
ber01-VHDL13_DWLG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 2863
ber01-VHDL13_DWLG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:01 2149
ber01-VHDL13_DWLG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2973
ber01-VHDL13_DWLG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2840
ber01-VHDL13_DWLH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3436
ber01-VHDL13_DWLH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:01 3029
ber01-VHDL13_DWLH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 2861
ber01-VHDL13_DWLH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 2782
ber01-VHDL13_DWLH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 2547
ber01-VHDL13_DWLH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:01 2090
ber01-VHDL13_DWLH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2906
ber01-VHDL13_DWLH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2589
ber01-VHDL13_DWLI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3516
ber01-VHDL13_DWLI_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:01 3013
ber01-VHDL13_DWLI_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 2952
ber01-VHDL13_DWLI_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 2854
ber01-VHDL13_DWLI_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 2556
ber01-VHDL13_DWLI_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:01 2052
ber01-VHDL13_DWLI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2592
ber01-VHDL13_DWLI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 2644
ber01-VHDL13_DWMG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3982
ber01-VHDL13_DWMG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 15:40:27 3923
ber01-VHDL13_DWMG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 3558
ber01-VHDL13_DWMG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3894
ber01-VHDL13_DWMG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3973
ber01-VHDL13_DWMG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:09 3759
ber01-VHDL13_DWMG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 3573
ber01-VHDL13_DWMG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:08 4013
ber01-VHDL13_DWMG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3642
ber01-VHDL13_DWMO_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3284
ber01-VHDL13_DWMO_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 3185
ber01-VHDL13_DWMO_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3191
ber01-VHDL13_DWMO_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3283
ber01-VHDL13_DWMO_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 3141
ber01-VHDL13_DWMO_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 3397
ber01-VHDL13_DWMO_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3666
ber01-VHDL13_DWMO_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 3312
ber01-VHDL13_DWMP_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4125
ber01-VHDL13_DWMP_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 3834
ber01-VHDL13_DWMP_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 4062
ber01-VHDL13_DWMP_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 4114
ber01-VHDL13_DWMP_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 3804
ber01-VHDL13_DWMP_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 3468
ber01-VHDL13_DWMP_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 3670
ber01-VHDL13_DWMP_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3670
ber01-VHDL13_DWOG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 6138
ber01-VHDL13_DWOG_251700-2601251700-dsw--0-ia5 25-Jan-2026 19:00:01 6237
ber01-VHDL13_DWOG_260300-2601260300-dsw--0-ia5 26-Jan-2026 04:00:01 6136
ber01-VHDL13_DWOG_260800-2601260800-dsw--0-ia5 26-Jan-2026 11:06:17 5694
ber01-VHDL13_DWOG_261700-2601261700-dsw--0-ia5 26-Jan-2026 19:00:02 4939
ber01-VHDL13_DWOG_270300-2601270300-dsw--0-ia5 27-Jan-2026 04:00:01 4783
ber01-VHDL13_DWOH_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3391
ber01-VHDL13_DWOH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 14:40:21 3267
ber01-VHDL13_DWOH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:28:22 2864
ber01-VHDL13_DWOH_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:32 2847
ber01-VHDL13_DWOH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:28:17 3325
ber01-VHDL13_DWOH_260400-2601260400-dsw--0-ia5 26-Jan-2026 05:58:22 3354
ber01-VHDL13_DWOH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:28:23 3393
ber01-VHDL13_DWOH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:28:22 3585
ber01-VHDL13_DWOH_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:22 3499
ber01-VHDL13_DWOH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3671
ber01-VHDL13_DWOH_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:22 3535
ber01-VHDL13_DWOI_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3776
ber01-VHDL13_DWOI_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 14:40:21 3506
ber01-VHDL13_DWOI_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:28:16 2786
ber01-VHDL13_DWOI_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:26 2790
ber01-VHDL13_DWOI_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:28:22 3210
ber01-VHDL13_DWOI_260400-2601260400-dsw--0-ia5 26-Jan-2026 05:58:18 3150
ber01-VHDL13_DWOI_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:28:17 3284
ber01-VHDL13_DWOI_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:28:16 3295
ber01-VHDL13_DWOI_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:18 3081
ber01-VHDL13_DWOI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:28:18 3068
ber01-VHDL13_DWOI_270400-2601270400-dsw--0-ia5 27-Jan-2026 05:58:22 3029
ber01-VHDL13_DWON_250628-2601250628-dsw--0-ia5 25-Jan-2026 06:28:21 3560
ber01-VHDL13_DWON_250724-2601250724-dsw--0-ia5 25-Jan-2026 07:24:56 4785
ber01-VHDL13_DWON_251601-2601251601-dsw--0-ia5 25-Jan-2026 16:01:12 3992
ber01-VHDL13_DWON_251806-2601251806-dsw--0-ia5 25-Jan-2026 18:06:07 4010
ber01-VHDL13_DWON_260006-2601260006-dsw--0-ia5 26-Jan-2026 00:06:32 4542
ber01-VHDL13_DWON_260345-2601260345-dsw--0-ia5 26-Jan-2026 03:45:27 3921
ber01-VHDL13_DWON_260622-2601260622-dsw--0-ia5 26-Jan-2026 06:23:03 3921
ber01-VHDL13_DWON_260757-2601260757-dsw--0-ia5 26-Jan-2026 07:57:31 4740
ber01-VHDL13_DWON_260831-2601260831-dsw--0-ia5 26-Jan-2026 08:31:18 4625
ber01-VHDL13_DWON_261105-2601261105-dsw--0-ia5 26-Jan-2026 11:06:00 4493
ber01-VHDL13_DWON_261520-2601261520-dsw--0-ia5 26-Jan-2026 15:20:32 3912
ber01-VHDL13_DWON_261812-2601261812-dsw--0-ia5 26-Jan-2026 18:12:37 3894
ber01-VHDL13_DWON_262023-2601262023-dsw--0-ia5 26-Jan-2026 20:23:51 3981
ber01-VHDL13_DWON_270244-2601270244-dsw--0-ia5 27-Jan-2026 02:44:37 3971
ber01-VHDL13_DWPG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3198
ber01-VHDL13_DWPG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:01 3288
ber01-VHDL13_DWPG_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 20:29:12 3135
ber01-VHDL13_DWPG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 2932
ber01-VHDL13_DWPG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 2836
ber01-VHDL13_DWPG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 2066
ber01-VHDL13_DWPG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:01 2217
ber01-VHDL13_DWPG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2300
ber01-VHDL13_DWPG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2210
ber01-VHDL13_DWPH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3866
ber01-VHDL13_DWPH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:01 3756
ber01-VHDL13_DWPH_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 20:29:37 3827
ber01-VHDL13_DWPH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3572
ber01-VHDL13_DWPH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3492
ber01-VHDL13_DWPH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 2771
ber01-VHDL13_DWPH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:01 3080
ber01-VHDL13_DWPH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2986
ber01-VHDL13_DWPH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2450
ber01-VHDL13_DWSG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3551
ber01-VHDL13_DWSG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 14:44:10 4355
ber01-VHDL13_DWSG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:30:06 4349
ber01-VHDL13_DWSG_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 20:15:02 4098
ber01-VHDL13_DWSG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:30:09 3333
ber01-VHDL13_DWSG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:09 3335
ber01-VHDL13_DWSG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:30:08 3168
ber01-VHDL13_DWSG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:30:10 2520
ber01-VHDL13_DWSG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:30:06 2931
ber01-VHDL13_DWSG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:07 2931
ber01-VHDL17_DWOG_251200-2601251200-dsw--0-ia5 25-Jan-2026 12:56:13 3011
ber01-VHDL17_DWOG_261200-2601261200-dsw--0-ia5 26-Jan-2026 12:46:42 2556
swis2-VHDL20_DWEG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4431
swis2-VHDL20_DWEG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 15:18:38 4221
swis2-VHDL20_DWEG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:02 3364
swis2-VHDL20_DWEG_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:12 3347
swis2-VHDL20_DWEG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:08 3770
swis2-VHDL20_DWEG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 4062
swis2-VHDL20_DWEG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:08 4522
swis2-VHDL20_DWEG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:08 4205
swis2-VHDL20_DWEG_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:13 4209
swis2-VHDL20_DWEG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4034
swis2-VHDL20_DWEG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 4115
swis2-VHDL20_DWEH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4840
swis2-VHDL20_DWEH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 16:06:37 4717
swis2-VHDL20_DWEH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:02 4235
swis2-VHDL20_DWEH_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:12 4236
swis2-VHDL20_DWEH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:08 4410
swis2-VHDL20_DWEH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 4569
swis2-VHDL20_DWEH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 5310
swis2-VHDL20_DWEH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:08 4513
swis2-VHDL20_DWEH_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:13 4517
swis2-VHDL20_DWEH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4229
swis2-VHDL20_DWEH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 4339
swis2-VHDL20_DWEI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4894
swis2-VHDL20_DWEI_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 15:18:56 4526
swis2-VHDL20_DWEI_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:02 3370
swis2-VHDL20_DWEI_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 19:55:12 3374
swis2-VHDL20_DWEI_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3715
swis2-VHDL20_DWEI_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 3801
swis2-VHDL20_DWEI_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:08 4362
swis2-VHDL20_DWEI_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:08 3728
swis2-VHDL20_DWEI_261800_COR-2601261800-dsw--0-ia5 26-Jan-2026 19:35:13 3732
swis2-VHDL20_DWEI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 3431
swis2-VHDL20_DWEI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:08 3569
swis2-VHDL20_DWHG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4969
swis2-VHDL20_DWHG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:02 4394
swis2-VHDL20_DWHG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3676
swis2-VHDL20_DWHG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3673
swis2-VHDL20_DWHG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:02 5316
swis2-VHDL20_DWHG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:01 3552
swis2-VHDL20_DWHG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3965
swis2-VHDL20_DWHG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3972
swis2-VHDL20_DWHH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 5175
swis2-VHDL20_DWHH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:02 4021
swis2-VHDL20_DWHH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3566
swis2-VHDL20_DWHH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:07 3566
swis2-VHDL20_DWHH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:02 5379
swis2-VHDL20_DWHH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:01 3585
swis2-VHDL20_DWHH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3615
swis2-VHDL20_DWHH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:06 3615
swis2-VHDL20_DWLG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4749
swis2-VHDL20_DWLG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 3992
swis2-VHDL20_DWLG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3752
swis2-VHDL20_DWLG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:11 3527
swis2-VHDL20_DWLG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 3455
swis2-VHDL20_DWLG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 2554
swis2-VHDL20_DWLG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3418
swis2-VHDL20_DWLG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3334
swis2-VHDL20_DWLH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4093
swis2-VHDL20_DWLH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 3473
swis2-VHDL20_DWLH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3305
swis2-VHDL20_DWLH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:11 3194
swis2-VHDL20_DWLH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:08 3166
swis2-VHDL20_DWLH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 2502
swis2-VHDL20_DWLH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3395
swis2-VHDL20_DWLH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3106
swis2-VHDL20_DWLI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4162
swis2-VHDL20_DWLI_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 3451
swis2-VHDL20_DWLI_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3315
swis2-VHDL20_DWLI_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:11 3261
swis2-VHDL20_DWLI_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 3146
swis2-VHDL20_DWLI_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 2459
swis2-VHDL20_DWLI_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3040
swis2-VHDL20_DWLI_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3197
swis2-VHDL20_DWMG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4783
swis2-VHDL20_DWMG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 4164
swis2-VHDL20_DWMG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 4404
swis2-VHDL20_DWMG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 4458
swis2-VHDL20_DWMG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 4476
swis2-VHDL20_DWMG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 4127
swis2-VHDL20_DWMG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4501
swis2-VHDL20_DWMG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 4152
swis2-VHDL20_DWMO_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 3930
swis2-VHDL20_DWMO_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 3049
swis2-VHDL20_DWMO_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3601
swis2-VHDL20_DWMO_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 3775
swis2-VHDL20_DWMO_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:08 3854
swis2-VHDL20_DWMO_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 3921
swis2-VHDL20_DWMO_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4136
swis2-VHDL20_DWMO_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 3782
swis2-VHDL20_DWMP_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4886
swis2-VHDL20_DWMP_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 4173
swis2-VHDL20_DWMP_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 4566
swis2-VHDL20_DWMP_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 4582
swis2-VHDL20_DWMP_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 4415
swis2-VHDL20_DWMP_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 4014
swis2-VHDL20_DWMP_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:08 4110
swis2-VHDL20_DWMP_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:02 4151
swis2-VHDL20_DWPG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4029
swis2-VHDL20_DWPG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 4119
swis2-VHDL20_DWPG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3509
swis2-VHDL20_DWPG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:11 3302
swis2-VHDL20_DWPG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 2722
swis2-VHDL20_DWPG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:06 2948
swis2-VHDL20_DWPG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 2849
swis2-VHDL20_DWPG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 2596
swis2-VHDL20_DWPH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4768
swis2-VHDL20_DWPH_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 4636
swis2-VHDL20_DWPH_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 4076
swis2-VHDL20_DWPH_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:00:11 3968
swis2-VHDL20_DWPH_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:08 3435
swis2-VHDL20_DWPH_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:08 3960
swis2-VHDL20_DWPH_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:06 3492
swis2-VHDL20_DWPH_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:00:17 3010
swis2-VHDL20_DWSG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:02 4578
swis2-VHDL20_DWSG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 14:44:10 5006
swis2-VHDL20_DWSG_251300-2601251300-dsw--0-ia5 25-Jan-2026 14:45:24 4775
swis2-VHDL20_DWSG_251800-2601251800-dsw--0-ia5 25-Jan-2026 19:45:06 4747
swis2-VHDL20_DWSG_251800_COR-2601251800-dsw--0-ia5 25-Jan-2026 20:15:02 4473
swis2-VHDL20_DWSG_260200-2601260200-dsw--0-ia5 26-Jan-2026 03:45:06 3780
swis2-VHDL20_DWSG_260400-2601260400-dsw--0-ia5 26-Jan-2026 06:15:06 3739
swis2-VHDL20_DWSG_260800-2601260800-dsw--0-ia5 26-Jan-2026 09:45:06 3830
swis2-VHDL20_DWSG_261300-2601261300-dsw--0-ia5 26-Jan-2026 14:45:13 3600
swis2-VHDL20_DWSG_261800-2601261800-dsw--0-ia5 26-Jan-2026 19:45:01 3035
swis2-VHDL20_DWSG_270200-2601270200-dsw--0-ia5 27-Jan-2026 03:45:02 3442
swis2-VHDL20_DWSG_270400-2601270400-dsw--0-ia5 27-Jan-2026 06:15:06 3394
wst04-VHDL20_DWEG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:18 228134
wst04-VHDL20_DWEG_250800_COR-2601250800-omedes-..> 25-Jan-2026 14:40:21 227897
wst04-VHDL20_DWEG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:22 225678
wst04-VHDL20_DWEG_251800_COR-2601251800-omedes-..> 25-Jan-2026 19:55:38 225664
wst04-VHDL20_DWEG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:17 227180
wst04-VHDL20_DWEG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:28 227559
wst04-VHDL20_DWEG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:17 225515
wst04-VHDL20_DWEG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:18 223620
wst04-VHDL20_DWEG_261800_COR-2601261800-omedes-..> 26-Jan-2026 19:35:26 223620
wst04-VHDL20_DWEG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:18 224684
wst04-VHDL20_DWEG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:22 223736
wst04-VHDL20_DWEH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 224982
wst04-VHDL20_DWEH_250800_COR-2601250800-omedes-..> 25-Jan-2026 14:40:21 224222
wst04-VHDL20_DWEH_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:16 223839
wst04-VHDL20_DWEH_251800_COR-2601251800-omedes-..> 25-Jan-2026 19:55:38 223839
wst04-VHDL20_DWEH_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:17 224318
wst04-VHDL20_DWEH_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:28 224183
wst04-VHDL20_DWEH_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:11 225873
wst04-VHDL20_DWEH_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:12 224133
wst04-VHDL20_DWEH_261800_COR-2601261800-omedes-..> 26-Jan-2026 19:35:26 224133
wst04-VHDL20_DWEH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:18 224975
wst04-VHDL20_DWEH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:22 224138
wst04-VHDL20_DWEI_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:16 314149
wst04-VHDL20_DWEI_250800_COR-2601250800-omedes-..> 25-Jan-2026 14:40:22 312546
wst04-VHDL20_DWEI_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:22 311262
wst04-VHDL20_DWEI_251800_COR-2601251800-omedes-..> 25-Jan-2026 19:55:42 311262
wst04-VHDL20_DWEI_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:17 311741
wst04-VHDL20_DWEI_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:28 312412
wst04-VHDL20_DWEI_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:23 309410
wst04-VHDL20_DWEI_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:16 307636
wst04-VHDL20_DWEI_261800_COR-2601261800-omedes-..> 26-Jan-2026 19:35:34 307636
wst04-VHDL20_DWEI_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:22 307631
wst04-VHDL20_DWEI_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:32 307228
wst04-VHDL20_DWHG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 300322
wst04-VHDL20_DWHG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:12 298428
wst04-VHDL20_DWHG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:13 298322
wst04-VHDL20_DWHG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:11 298475
wst04-VHDL20_DWHG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:11 300716
wst04-VHDL20_DWHG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:12 298100
wst04-VHDL20_DWHG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 298503
wst04-VHDL20_DWHG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:11 298650
wst04-VHDL20_DWHH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 291602
wst04-VHDL20_DWHH_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:12 290680
wst04-VHDL20_DWHH_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:13 290282
wst04-VHDL20_DWHH_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:11 290262
wst04-VHDL20_DWHH_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:11 295823
wst04-VHDL20_DWHH_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:12 293712
wst04-VHDL20_DWHH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 293855
wst04-VHDL20_DWHH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:11 293886
wst04-VHDL20_DWLG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 300482
wst04-VHDL20_DWLG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:40 299290
wst04-VHDL20_DWLG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:33 299598
wst04-VHDL20_DWLG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:43 299630
wst04-VHDL20_DWLG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:37 301232
wst04-VHDL20_DWLG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:27 299786
wst04-VHDL20_DWLG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:36 301181
wst04-VHDL20_DWLG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:43 300811
wst04-VHDL20_DWLH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 295602
wst04-VHDL20_DWLH_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:36 294810
wst04-VHDL20_DWLH_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:37 295026
wst04-VHDL20_DWLH_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:43 295156
wst04-VHDL20_DWLH_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:43 295123
wst04-VHDL20_DWLH_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:32 293858
wst04-VHDL20_DWLH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 295289
wst04-VHDL20_DWLH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:41 294620
wst04-VHDL20_DWLI_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:32 297246
wst04-VHDL20_DWLI_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:40 296418
wst04-VHDL20_DWLI_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:37 296931
wst04-VHDL20_DWLI_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:47 297132
wst04-VHDL20_DWLI_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:43 296207
wst04-VHDL20_DWLI_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:32 294995
wst04-VHDL20_DWLI_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 296144
wst04-VHDL20_DWLI_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:47 296358
wst04-VHDL20_DWMG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 535723
wst04-VHDL20_DWMG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:32 534246
wst04-VHDL20_DWMG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:27 536110
wst04-VHDL20_DWMG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:16 535242
wst04-VHDL20_DWMG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:27 497557
wst04-VHDL20_DWMG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:27 496245
wst04-VHDL20_DWMG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:28 496985
wst04-VHDL20_DWMG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:28 496439
wst04-VHDL20_DWMO_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 419678
wst04-VHDL20_DWMO_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:26 418530
wst04-VHDL20_DWMO_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:21 419133
wst04-VHDL20_DWMO_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:16 419923
wst04-VHDL20_DWMO_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:27 399182
wst04-VHDL20_DWMO_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:22 398821
wst04-VHDL20_DWMO_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:16 398876
wst04-VHDL20_DWMO_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:16 399188
wst04-VHDL20_DWMP_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 560045
wst04-VHDL20_DWMP_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:26 559203
wst04-VHDL20_DWMP_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:21 558637
wst04-VHDL20_DWMP_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:22 560659
wst04-VHDL20_DWMP_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:31 520998
wst04-VHDL20_DWMP_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:22 519366
wst04-VHDL20_DWMP_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:22 517600
wst04-VHDL20_DWMP_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:28 518831
wst04-VHDL20_DWPG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 346209
wst04-VHDL20_DWPG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:36 302590
wst04-VHDL20_DWPG_251800_COR-2601251800-omedes-..> 25-Jan-2026 20:31:39 302487
wst04-VHDL20_DWPG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:33 301476
wst04-VHDL20_DWPG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:31 301110
wst04-VHDL20_DWPG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:37 343993
wst04-VHDL20_DWPG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:38 299271
wst04-VHDL20_DWPG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:32 299619
wst04-VHDL20_DWPG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:31 299458
wst04-VHDL20_DWPH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:32 263045
wst04-VHDL20_DWPH_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:32 262829
wst04-VHDL20_DWPH_251800_COR-2601251800-omedes-..> 25-Jan-2026 20:32:03 263317
wst04-VHDL20_DWPH_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:27 218070
wst04-VHDL20_DWPH_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:00:33 218311
wst04-VHDL20_DWPH_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:31 263132
wst04-VHDL20_DWPH_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:32 263209
wst04-VHDL20_DWPH_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:26 217286
wst04-VHDL20_DWPH_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:00:31 216521
wst04-VHDL20_DWSG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 328663
wst04-VHDL20_DWSG_250800_COR-2601250800-omedes-..> 25-Jan-2026 14:44:10 329888
wst04-VHDL20_DWSG_251300-2601251300-omedes--0.pdf 25-Jan-2026 14:45:24 329842
wst04-VHDL20_DWSG_251800-2601251800-omedes--0.pdf 25-Jan-2026 19:45:16 329835
wst04-VHDL20_DWSG_251800_COR-2601251800-omedes-..> 25-Jan-2026 20:15:16 329669
wst04-VHDL20_DWSG_260200-2601260200-omedes--0.pdf 26-Jan-2026 03:45:13 327750
wst04-VHDL20_DWSG_260400-2601260400-omedes--0.pdf 26-Jan-2026 06:15:12 328244
wst04-VHDL20_DWSG_260800-2601260800-omedes--0.pdf 26-Jan-2026 09:45:11 315782
wst04-VHDL20_DWSG_261300-2601261300-omedes--0.pdf 26-Jan-2026 14:45:13 315738
wst04-VHDL20_DWSG_261800-2601261800-omedes--0.pdf 26-Jan-2026 19:45:12 313762
wst04-VHDL20_DWSG_270200-2601270200-omedes--0.pdf 27-Jan-2026 03:45:12 314817
wst04-VHDL20_DWSG_270400-2601270400-omedes--0.pdf 27-Jan-2026 06:15:12 314958