Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Dec-2025 14:43:54 6437
FPDL13_DWMZ_180600 18-Dec-2025 14:04:33 3968
SXDL31_DWAV_170800 17-Dec-2025 07:46:29 14514
SXDL31_DWAV_171800 17-Dec-2025 16:15:20 6164
SXDL31_DWAV_180800 18-Dec-2025 08:12:39 8121
SXDL31_DWAV_181800 18-Dec-2025 16:45:25 9792
SXDL31_DWAV_LATEST 18-Dec-2025 16:45:25 9792
SXDL33_DWAV_170000 17-Dec-2025 10:28:45 7600
SXDL33_DWAV_180000 18-Dec-2025 12:23:53 12644
SXDL33_DWAV_LATEST 18-Dec-2025 12:23:53 12644
ber01-FWDL39_DWMS_171230-2512171230-dsw--0-ia5 17-Dec-2025 11:24:03 1108
ber01-FWDL39_DWMS_181230-2512181230-dsw--0-ia5 18-Dec-2025 12:15:51 1419
ber01-VHDL13_DWEH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:28:12 2564
ber01-VHDL13_DWEH_170400-2512170400-dsw--0-ia5 17-Dec-2025 05:58:17 2851
ber01-VHDL13_DWEH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:28:16 2655
ber01-VHDL13_DWEH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:17 3210
ber01-VHDL13_DWEH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2813
ber01-VHDL13_DWEH_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:12 2720
ber01-VHDL13_DWEH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:17 2790
ber01-VHDL13_DWEH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2341
ber01-VHDL13_DWHG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:12 3188
ber01-VHDL13_DWHG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3317
ber01-VHDL13_DWHG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:06 3226
ber01-VHDL13_DWHG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 3542
ber01-VHDL13_DWHG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 3402
ber01-VHDL13_DWHG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3402
ber01-VHDL13_DWHG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:07 3430
ber01-VHDL13_DWHG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2871
ber01-VHDL13_DWHH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:12 3143
ber01-VHDL13_DWHH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3143
ber01-VHDL13_DWHH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:06 3213
ber01-VHDL13_DWHH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 3077
ber01-VHDL13_DWHH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 3185
ber01-VHDL13_DWHH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3185
ber01-VHDL13_DWHH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:07 3215
ber01-VHDL13_DWHH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2645
ber01-VHDL13_DWLG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:01 2563
ber01-VHDL13_DWLG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 2270
ber01-VHDL13_DWLG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2273
ber01-VHDL13_DWLG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2138
ber01-VHDL13_DWLG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2637
ber01-VHDL13_DWLG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2547
ber01-VHDL13_DWLG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2602
ber01-VHDL13_DWLG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2298
ber01-VHDL13_DWLH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:01 2446
ber01-VHDL13_DWLH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 2259
ber01-VHDL13_DWLH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2121
ber01-VHDL13_DWLH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2191
ber01-VHDL13_DWLH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2176
ber01-VHDL13_DWLH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2213
ber01-VHDL13_DWLH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2309
ber01-VHDL13_DWLH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2141
ber01-VHDL13_DWLI_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:01 2305
ber01-VHDL13_DWLI_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 2231
ber01-VHDL13_DWLI_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2328
ber01-VHDL13_DWLI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2349
ber01-VHDL13_DWLI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2292
ber01-VHDL13_DWLI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2330
ber01-VHDL13_DWLI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 2539
ber01-VHDL13_DWLI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2182
ber01-VHDL13_DWMG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:12 3347
ber01-VHDL13_DWMG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3206
ber01-VHDL13_DWMG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 3001
ber01-VHDL13_DWMG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2924
ber01-VHDL13_DWMG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3071
ber01-VHDL13_DWMG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 3258
ber01-VHDL13_DWMG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3627
ber01-VHDL13_DWMG_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:31:49 3782
ber01-VHDL13_DWMG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3130
ber01-VHDL13_DWMO_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:12 3143
ber01-VHDL13_DWMO_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3143
ber01-VHDL13_DWMO_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2902
ber01-VHDL13_DWMO_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2985
ber01-VHDL13_DWMO_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3199
ber01-VHDL13_DWMO_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 3380
ber01-VHDL13_DWMO_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3711
ber01-VHDL13_DWMO_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:42:21 3937
ber01-VHDL13_DWMO_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3133
ber01-VHDL13_DWMP_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:12 3065
ber01-VHDL13_DWMP_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3065
ber01-VHDL13_DWMP_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2734
ber01-VHDL13_DWMP_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 2600
ber01-VHDL13_DWMP_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 2817
ber01-VHDL13_DWMP_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2989
ber01-VHDL13_DWMP_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 2989
ber01-VHDL13_DWMP_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:57:17 2900
ber01-VHDL13_DWMP_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2451
ber01-VHDL13_DWOG_170300-2512170300-dsw--0-ia5 17-Dec-2025 04:00:01 4416
ber01-VHDL13_DWOG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:06 4212
ber01-VHDL13_DWOG_171700-2512171700-dsw--0-ia5 17-Dec-2025 19:00:03 3939
ber01-VHDL13_DWOG_180300-2512180300-dsw--0-ia5 18-Dec-2025 04:00:01 4002
ber01-VHDL13_DWOG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 4412
ber01-VHDL13_DWOG_181700-2512181700-dsw--0-ia5 18-Dec-2025 19:00:02 4110
ber01-VHDL13_DWOH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:28:12 2198
ber01-VHDL13_DWOH_170400-2512170400-dsw--0-ia5 17-Dec-2025 05:58:17 2516
ber01-VHDL13_DWOH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:28:16 2520
ber01-VHDL13_DWOH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:17 2961
ber01-VHDL13_DWOH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2451
ber01-VHDL13_DWOH_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:16 2475
ber01-VHDL13_DWOH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:17 2674
ber01-VHDL13_DWOH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2383
ber01-VHDL13_DWOI_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:28:16 2167
ber01-VHDL13_DWOI_170400-2512170400-dsw--0-ia5 17-Dec-2025 05:58:11 2530
ber01-VHDL13_DWOI_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:28:16 2465
ber01-VHDL13_DWOI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:28:11 3046
ber01-VHDL13_DWOI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:28:12 2314
ber01-VHDL13_DWOI_180400-2512180400-dsw--0-ia5 18-Dec-2025 05:58:16 2381
ber01-VHDL13_DWOI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:28:11 2589
ber01-VHDL13_DWOI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:12 2428
ber01-VHDL13_DWON_170232-2512170232-dsw--0-ia5 17-Dec-2025 02:32:34 3639
ber01-VHDL13_DWON_170243-2512170243-dsw--0-ia5 17-Dec-2025 02:43:07 3639
ber01-VHDL13_DWON_170334-2512170334-dsw--0-ia5 17-Dec-2025 03:35:04 3639
ber01-VHDL13_DWON_170443-2512170443-dsw--0-ia5 17-Dec-2025 04:43:36 3656
ber01-VHDL13_DWON_170628-2512170628-dsw--0-ia5 17-Dec-2025 06:28:57 3653
ber01-VHDL13_DWON_170723-2512170723-dsw--0-ia5 17-Dec-2025 07:23:16 3703
ber01-VHDL13_DWON_171128-2512171128-dsw--0-ia5 17-Dec-2025 11:28:37 3688
ber01-VHDL13_DWON_171548-2512171548-dsw--0-ia5 17-Dec-2025 15:48:12 3248
ber01-VHDL13_DWON_171733-2512171733-dsw--0-ia5 17-Dec-2025 17:33:32 3248
ber01-VHDL13_DWON_171741-2512171741-dsw--0-ia5 17-Dec-2025 17:42:01 3248
ber01-VHDL13_DWON_180119-2512180119-dsw--0-ia5 18-Dec-2025 01:19:22 3176
ber01-VHDL13_DWON_180624-2512180624-dsw--0-ia5 18-Dec-2025 06:24:36 3800
ber01-VHDL13_DWON_180715-2512180715-dsw--0-ia5 18-Dec-2025 07:15:43 3953
ber01-VHDL13_DWON_180903-2512180903-dsw--0-ia5 18-Dec-2025 09:03:35 3975
ber01-VHDL13_DWON_181551-2512181551-dsw--0-ia5 18-Dec-2025 15:51:41 3492
ber01-VHDL13_DWON_181731-2512181731-dsw--0-ia5 18-Dec-2025 17:31:45 3624
ber01-VHDL13_DWPG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:01 1868
ber01-VHDL13_DWPG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 1881
ber01-VHDL13_DWPG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 1849
ber01-VHDL13_DWPG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 1859
ber01-VHDL13_DWPG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 1818
ber01-VHDL13_DWPG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 1913
ber01-VHDL13_DWPG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 1909
ber01-VHDL13_DWPG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1788
ber01-VHDL13_DWPH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:01 2300
ber01-VHDL13_DWPH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 2195
ber01-VHDL13_DWPH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:02 2072
ber01-VHDL13_DWPH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:08 2086
ber01-VHDL13_DWPH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:07 2106
ber01-VHDL13_DWPH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:02 2082
ber01-VHDL13_DWPH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:05 1895
ber01-VHDL13_DWPH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1876
ber01-VHDL13_DWSG_161800-2512161800-dsw--0-ia5 16-Dec-2025 20:58:17 2842
ber01-VHDL13_DWSG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:30:04 3123
ber01-VHDL13_DWSG_170200_COR-2512170200-dsw--0-ia5 17-Dec-2025 03:41:52 3345
ber01-VHDL13_DWSG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3490
ber01-VHDL13_DWSG_170400_COR-2512170400-dsw--0-ia5 17-Dec-2025 03:37:38 3345
ber01-VHDL13_DWSG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:30:06 3440
ber01-VHDL13_DWSG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:30:02 3064
ber01-VHDL13_DWSG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:30:01 3509
ber01-VHDL13_DWSG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:06 3552
ber01-VHDL13_DWSG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:30:03 3552
ber01-VHDL13_DWSG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 3203
ber01-VHDL17_DWOG_171200-2512171200-dsw--0-ia5 17-Dec-2025 12:45:32 2825
ber01-VHDL17_DWOG_181200-2512181200-dsw--0-ia5 18-Dec-2025 12:55:31 3733
swis2-VHDL20_DWEG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 2560
swis2-VHDL20_DWEG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 2492
swis2-VHDL20_DWEG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:02 2839
swis2-VHDL20_DWEG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 3106
swis2-VHDL20_DWEG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 3290
swis2-VHDL20_DWEG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2730
swis2-VHDL20_DWEG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 2795
swis2-VHDL20_DWEG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3149
swis2-VHDL20_DWEH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3153
swis2-VHDL20_DWEH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 2923
swis2-VHDL20_DWEH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:02 3186
swis2-VHDL20_DWEH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 3194
swis2-VHDL20_DWEH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3570
swis2-VHDL20_DWEH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 3137
swis2-VHDL20_DWEH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3052
swis2-VHDL20_DWEH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3290
swis2-VHDL20_DWEI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 2734
swis2-VHDL20_DWEI_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 2479
swis2-VHDL20_DWEI_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:02 2884
swis2-VHDL20_DWEI_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 3101
swis2-VHDL20_DWEI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3400
swis2-VHDL20_DWEI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2606
swis2-VHDL20_DWEI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 2733
swis2-VHDL20_DWEI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3112
swis2-VHDL20_DWHG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3377
swis2-VHDL20_DWHG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:02 3374
swis2-VHDL20_DWHG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3500
swis2-VHDL20_DWHG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 3763
swis2-VHDL20_DWHG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3725
swis2-VHDL20_DWHG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3588
swis2-VHDL20_DWHG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3585
swis2-VHDL20_DWHG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3964
swis2-VHDL20_DWHH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:06 3270
swis2-VHDL20_DWHH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:02 3329
swis2-VHDL20_DWHH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:07 3329
swis2-VHDL20_DWHH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 3759
swis2-VHDL20_DWHH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3263
swis2-VHDL20_DWHH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3371
swis2-VHDL20_DWHH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:12 3371
swis2-VHDL20_DWHH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:07 3758
swis2-VHDL20_DWLG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2680
swis2-VHDL20_DWLG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:00 3072
swis2-VHDL20_DWLG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:11 2612
swis2-VHDL20_DWLG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 2758
swis2-VHDL20_DWLG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2480
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swis2-VHDL20_DWLG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2980
swis2-VHDL20_DWLG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 3149
swis2-VHDL20_DWLH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2210
swis2-VHDL20_DWLH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:00 2817
swis2-VHDL20_DWLH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:11 2608
swis2-VHDL20_DWLH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 2617
swis2-VHDL20_DWLH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 2540
swis2-VHDL20_DWLH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2528
swis2-VHDL20_DWLH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2559
swis2-VHDL20_DWLH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2801
swis2-VHDL20_DWLI_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2231
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swis2-VHDL20_DWLI_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:11 2575
swis2-VHDL20_DWLI_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 2814
swis2-VHDL20_DWLI_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2693
swis2-VHDL20_DWLI_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2639
swis2-VHDL20_DWLI_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2671
swis2-VHDL20_DWLI_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 3096
swis2-VHDL20_DWMG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3545
swis2-VHDL20_DWMG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 3897
swis2-VHDL20_DWMG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:06 3633
swis2-VHDL20_DWMG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 3695
swis2-VHDL20_DWMG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3353
swis2-VHDL20_DWMG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3500
swis2-VHDL20_DWMG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3684
swis2-VHDL20_DWMG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4264
swis2-VHDL20_DWMO_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3047
swis2-VHDL20_DWMO_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 3579
swis2-VHDL20_DWMO_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:06 3575
swis2-VHDL20_DWMO_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 3596
swis2-VHDL20_DWMO_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3417
swis2-VHDL20_DWMO_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3642
swis2-VHDL20_DWMO_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3806
swis2-VHDL20_DWMO_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4344
swis2-VHDL20_DWMO_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:43:07 4570
swis2-VHDL20_DWMP_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3341
swis2-VHDL20_DWMP_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:07 3605
swis2-VHDL20_DWMP_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:06 3495
swis2-VHDL20_DWMP_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 3434
swis2-VHDL20_DWMP_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:06 3023
swis2-VHDL20_DWMP_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:01 3251
swis2-VHDL20_DWMP_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:02 3417
swis2-VHDL20_DWMP_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 3635
swis2-VHDL20_DWMP_180800_COR-2512180800-dsw--0-ia5 18-Dec-2025 10:58:07 3546
swis2-VHDL20_DWPG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 1995
swis2-VHDL20_DWPG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:00 2198
swis2-VHDL20_DWPG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:11 2210
swis2-VHDL20_DWPG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 2311
swis2-VHDL20_DWPG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 2321
swis2-VHDL20_DWPG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2150
swis2-VHDL20_DWPG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2239
swis2-VHDL20_DWPG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2368
swis2-VHDL20_DWPH_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 2466
swis2-VHDL20_DWPH_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:00 2629
swis2-VHDL20_DWPH_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:00:11 2526
swis2-VHDL20_DWPH_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:01 2534
swis2-VHDL20_DWPH_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:01 2548
swis2-VHDL20_DWPH_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 2437
swis2-VHDL20_DWPH_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:00:17 2410
swis2-VHDL20_DWPH_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:05 2354
swis2-VHDL20_DWSG_161800-2512161800-dsw--0-ia5 16-Dec-2025 19:45:04 3005
swis2-VHDL20_DWSG_170200-2512170200-dsw--0-ia5 17-Dec-2025 03:45:02 3924
swis2-VHDL20_DWSG_170200_COR-2512170200-dsw--0-ia5 17-Dec-2025 03:41:52 3928
swis2-VHDL20_DWSG_170400-2512170400-dsw--0-ia5 17-Dec-2025 06:15:02 3929
swis2-VHDL20_DWSG_170400_COR-2512170400-dsw--0-ia5 17-Dec-2025 03:37:38 3911
swis2-VHDL20_DWSG_170800-2512170800-dsw--0-ia5 17-Dec-2025 09:45:06 4108
swis2-VHDL20_DWSG_171300-2512171300-dsw--0-ia5 17-Dec-2025 14:45:10 3780
swis2-VHDL20_DWSG_171800-2512171800-dsw--0-ia5 17-Dec-2025 19:45:02 3506
swis2-VHDL20_DWSG_180200-2512180200-dsw--0-ia5 18-Dec-2025 03:45:06 3910
swis2-VHDL20_DWSG_180400-2512180400-dsw--0-ia5 18-Dec-2025 06:15:06 3917
swis2-VHDL20_DWSG_180800-2512180800-dsw--0-ia5 18-Dec-2025 09:45:01 4109
swis2-VHDL20_DWSG_181300-2512181300-dsw--0-ia5 18-Dec-2025 14:45:04 3632
wst04-VHDL20_DWEG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 224446
wst04-VHDL20_DWEG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:21 225278
wst04-VHDL20_DWEG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:26 224075
wst04-VHDL20_DWEG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:22 221300
wst04-VHDL20_DWEG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 220367
wst04-VHDL20_DWEG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 221438
wst04-VHDL20_DWEG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:26 220953
wst04-VHDL20_DWEG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 222787
wst04-VHDL20_DWEH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 227000
wst04-VHDL20_DWEH_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:17 228316
wst04-VHDL20_DWEH_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:20 227446
wst04-VHDL20_DWEH_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:22 220691
wst04-VHDL20_DWEH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 220785
wst04-VHDL20_DWEH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:16 221769
wst04-VHDL20_DWEH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 221164
wst04-VHDL20_DWEH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:21 221705
wst04-VHDL20_DWEI_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:16 309185
wst04-VHDL20_DWEI_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:21 309241
wst04-VHDL20_DWEI_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:26 308787
wst04-VHDL20_DWEI_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:26 302832
wst04-VHDL20_DWEI_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 302436
wst04-VHDL20_DWEI_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 302670
wst04-VHDL20_DWEI_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:26 303109
wst04-VHDL20_DWEI_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 301082
wst04-VHDL20_DWHG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:22 299797
wst04-VHDL20_DWHG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:11 299831
wst04-VHDL20_DWHG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:11 300070
wst04-VHDL20_DWHG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:22 297066
wst04-VHDL20_DWHG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 296562
wst04-VHDL20_DWHG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 296600
wst04-VHDL20_DWHG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:12 296584
wst04-VHDL20_DWHG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:21 297124
wst04-VHDL20_DWHH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:22 287269
wst04-VHDL20_DWHH_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:11 286969
wst04-VHDL20_DWHH_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:11 287069
wst04-VHDL20_DWHH_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:16 288824
wst04-VHDL20_DWHH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 288157
wst04-VHDL20_DWHH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 288645
wst04-VHDL20_DWHH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:12 288655
wst04-VHDL20_DWHH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:17 288739
wst04-VHDL20_DWLG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 294697
wst04-VHDL20_DWLG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:28 295784
wst04-VHDL20_DWLG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:41 294270
wst04-VHDL20_DWLG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:32 293649
wst04-VHDL20_DWLG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 293092
wst04-VHDL20_DWLG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 293800
wst04-VHDL20_DWLG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 293801
wst04-VHDL20_DWLG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 287362
wst04-VHDL20_DWLH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:20 297209
wst04-VHDL20_DWLH_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:21 298537
wst04-VHDL20_DWLH_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:41 296810
wst04-VHDL20_DWLH_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:32 294492
wst04-VHDL20_DWLH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 294406
wst04-VHDL20_DWLH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 294188
wst04-VHDL20_DWLH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 294165
wst04-VHDL20_DWLH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 287324
wst04-VHDL20_DWLI_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 300263
wst04-VHDL20_DWLI_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:28 301462
wst04-VHDL20_DWLI_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:41 300184
wst04-VHDL20_DWLI_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:32 295206
wst04-VHDL20_DWLI_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 295474
wst04-VHDL20_DWLI_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 295457
wst04-VHDL20_DWLI_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:42 295862
wst04-VHDL20_DWLI_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 289415
wst04-VHDL20_DWMG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:18 507238
wst04-VHDL20_DWMG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:17 507270
wst04-VHDL20_DWMG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:22 506989
wst04-VHDL20_DWMG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:16 486658
wst04-VHDL20_DWMG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:16 486420
wst04-VHDL20_DWMG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:12 486636
wst04-VHDL20_DWMG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 487044
wst04-VHDL20_DWMG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 482750
wst04-VHDL20_DWMG_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:33:12 482709
wst04-VHDL20_DWMO_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 408097
wst04-VHDL20_DWMO_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:17 408763
wst04-VHDL20_DWMO_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:16 409262
wst04-VHDL20_DWMO_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:12 395663
wst04-VHDL20_DWMO_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 395401
wst04-VHDL20_DWMO_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:18 395411
wst04-VHDL20_DWMO_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 396167
wst04-VHDL20_DWMO_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 392061
wst04-VHDL20_DWMO_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:42:53 391331
wst04-VHDL20_DWMP_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 534397
wst04-VHDL20_DWMP_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:17 533405
wst04-VHDL20_DWMP_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:22 534483
wst04-VHDL20_DWMP_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:16 510600
wst04-VHDL20_DWMP_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 509725
wst04-VHDL20_DWMP_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:18 508030
wst04-VHDL20_DWMP_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:22 510215
wst04-VHDL20_DWMP_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:17 505336
wst04-VHDL20_DWMP_180800_COR-2512180800-omedes-..> 18-Dec-2025 10:57:47 504582
wst04-VHDL20_DWPG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:26 295601
wst04-VHDL20_DWPG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:28 296493
wst04-VHDL20_DWPG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:31 295939
wst04-VHDL20_DWPG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:32 336723
wst04-VHDL20_DWPG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:26 291984
wst04-VHDL20_DWPG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:22 291427
wst04-VHDL20_DWPG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:31 291497
wst04-VHDL20_DWPG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:31 336945
wst04-VHDL20_DWPH_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:20 261873
wst04-VHDL20_DWPH_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:21 217679
wst04-VHDL20_DWPH_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:00:31 217399
wst04-VHDL20_DWPH_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:26 260389
wst04-VHDL20_DWPH_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:22 259833
wst04-VHDL20_DWPH_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:26 214898
wst04-VHDL20_DWPH_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:00:31 215224
wst04-VHDL20_DWPH_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:27 259709
wst04-VHDL20_DWSG_161800-2512161800-omedes--0.pdf 16-Dec-2025 19:45:12 326604
wst04-VHDL20_DWSG_170200-2512170200-omedes--0.pdf 17-Dec-2025 03:45:13 327331
wst04-VHDL20_DWSG_170200_COR-2512170200-omedes-..> 17-Dec-2025 03:41:56 327331
wst04-VHDL20_DWSG_170400-2512170400-omedes--0.pdf 17-Dec-2025 06:15:16 327436
wst04-VHDL20_DWSG_170400_COR-2512170400-omedes-..> 17-Dec-2025 03:37:50 327425
wst04-VHDL20_DWSG_170800-2512170800-omedes--0.pdf 17-Dec-2025 09:45:12 317032
wst04-VHDL20_DWSG_171300-2512171300-omedes--0.pdf 17-Dec-2025 14:45:22 317119
wst04-VHDL20_DWSG_171800-2512171800-omedes--0.pdf 17-Dec-2025 19:45:12 317688
wst04-VHDL20_DWSG_180200-2512180200-omedes--0.pdf 18-Dec-2025 03:45:16 318050
wst04-VHDL20_DWSG_180400-2512180400-omedes--0.pdf 18-Dec-2025 06:15:16 318054
wst04-VHDL20_DWSG_180800-2512180800-omedes--0.pdf 18-Dec-2025 09:45:11 313018
wst04-VHDL20_DWSG_181300-2512181300-omedes--0.pdf 18-Dec-2025 14:45:12 312687