Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Feb-2026 13:05:13 5282
FPDL13_DWMZ_130600 13-Feb-2026 14:39:55 4878
SXDL31_DWAV_120800 12-Feb-2026 08:06:19 16013
SXDL31_DWAV_121800 12-Feb-2026 18:05:33 10072
SXDL31_DWAV_130800 13-Feb-2026 07:54:30 9087
SXDL31_DWAV_131800 13-Feb-2026 17:10:35 7448
SXDL31_DWAV_LATEST 13-Feb-2026 17:10:35 7448
SXDL33_DWAV_120000 12-Feb-2026 10:50:48 9946
SXDL33_DWAV_130000 13-Feb-2026 11:06:29 9201
SXDL33_DWAV_LATEST 13-Feb-2026 11:06:29 9201
ber01-FWDL39_DWMS_121230-2602121230-dsw--0-ia5 12-Feb-2026 11:52:47 1735
ber01-FWDL39_DWMS_131230-2602131230-dsw--0-ia5 13-Feb-2026 12:18:02 1629
ber01-VHDL13_DWEH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:28:17 3669
ber01-VHDL13_DWEH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:28:16 3469
ber01-VHDL13_DWEH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:28:12 3792
ber01-VHDL13_DWEH_130400-2602130400-dsw--0-ia5 13-Feb-2026 05:58:17 3798
ber01-VHDL13_DWEH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:28:17 4137
ber01-VHDL13_DWEH_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:27 4089
ber01-VHDL13_DWEH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:17 3512
ber01-VHDL13_DWEH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:12 3830
ber01-VHDL13_DWEH_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:12 3914
ber01-VHDL13_DWHG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 3215
ber01-VHDL13_DWHG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:08 3034
ber01-VHDL13_DWHG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:07 2477
ber01-VHDL13_DWHG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:07 2477
ber01-VHDL13_DWHG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:07 2580
ber01-VHDL13_DWHG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2881
ber01-VHDL13_DWHG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3662
ber01-VHDL13_DWHG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3662
ber01-VHDL13_DWHH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 3401
ber01-VHDL13_DWHH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:08 3216
ber01-VHDL13_DWHH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:07 2789
ber01-VHDL13_DWHH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:07 2609
ber01-VHDL13_DWHH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:07 2609
ber01-VHDL13_DWHH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2830
ber01-VHDL13_DWHH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3251
ber01-VHDL13_DWHH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3250
ber01-VHDL13_DWLG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 2619
ber01-VHDL13_DWLG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 2590
ber01-VHDL13_DWLG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 2751
ber01-VHDL13_DWLG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 2754
ber01-VHDL13_DWLG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 2872
ber01-VHDL13_DWLG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 3113
ber01-VHDL13_DWLG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3331
ber01-VHDL13_DWLG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3269
ber01-VHDL13_DWLH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 2600
ber01-VHDL13_DWLH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 3011
ber01-VHDL13_DWLH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 3084
ber01-VHDL13_DWLH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 2892
ber01-VHDL13_DWLH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 3008
ber01-VHDL13_DWLH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2936
ber01-VHDL13_DWLH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3098
ber01-VHDL13_DWLH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3123
ber01-VHDL13_DWLI_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 2691
ber01-VHDL13_DWLI_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 2632
ber01-VHDL13_DWLI_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 2782
ber01-VHDL13_DWLI_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 2516
ber01-VHDL13_DWLI_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 2662
ber01-VHDL13_DWLI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2996
ber01-VHDL13_DWLI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3136
ber01-VHDL13_DWLI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3079
ber01-VHDL13_DWMG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:02 3552
ber01-VHDL13_DWMG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 3547
ber01-VHDL13_DWMG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:07 4097
ber01-VHDL13_DWMG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 3773
ber01-VHDL13_DWMG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 3837
ber01-VHDL13_DWMG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2880
ber01-VHDL13_DWMG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3154
ber01-VHDL13_DWMG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3274
ber01-VHDL13_DWMO_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:02 3468
ber01-VHDL13_DWMO_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 3256
ber01-VHDL13_DWMO_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:07 3622
ber01-VHDL13_DWMO_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 3563
ber01-VHDL13_DWMO_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 3644
ber01-VHDL13_DWMO_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2631
ber01-VHDL13_DWMO_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 2774
ber01-VHDL13_DWMO_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2822
ber01-VHDL13_DWMP_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:02 3631
ber01-VHDL13_DWMP_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 3426
ber01-VHDL13_DWMP_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:07 4042
ber01-VHDL13_DWMP_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:02 3756
ber01-VHDL13_DWMP_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 3697
ber01-VHDL13_DWMP_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2893
ber01-VHDL13_DWMP_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:10 3249
ber01-VHDL13_DWMP_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3256
ber01-VHDL13_DWOG_120800-2602120800-dsw--0-ia5 12-Feb-2026 11:58:57 6431
ber01-VHDL13_DWOG_121700-2602121700-dsw--0-ia5 12-Feb-2026 19:00:07 6065
ber01-VHDL13_DWOG_130300-2602130300-dsw--0-ia5 13-Feb-2026 04:00:06 6030
ber01-VHDL13_DWOG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 5111
ber01-VHDL13_DWOG_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 15:45:41 4605
ber01-VHDL13_DWOG_131700-2602131700-dsw--0-ia5 13-Feb-2026 19:00:02 4517
ber01-VHDL13_DWOG_131700_COR-2602131700-dsw--0-ia5 13-Feb-2026 21:30:06 5155
ber01-VHDL13_DWOG_140300-2602140300-dsw--0-ia5 14-Feb-2026 04:00:02 5484
ber01-VHDL13_DWOH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:28:17 3103
ber01-VHDL13_DWOH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:28:16 2693
ber01-VHDL13_DWOH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:28:12 3422
ber01-VHDL13_DWOH_130400-2602130400-dsw--0-ia5 13-Feb-2026 05:58:11 3646
ber01-VHDL13_DWOH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:28:17 3631
ber01-VHDL13_DWOH_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:31 3577
ber01-VHDL13_DWOH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:17 3429
ber01-VHDL13_DWOH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:12 3756
ber01-VHDL13_DWOH_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:16 3852
ber01-VHDL13_DWOI_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:28:11 3324
ber01-VHDL13_DWOI_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:28:12 2976
ber01-VHDL13_DWOI_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:28:12 3517
ber01-VHDL13_DWOI_130400-2602130400-dsw--0-ia5 13-Feb-2026 05:58:17 3952
ber01-VHDL13_DWOI_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:28:17 3704
ber01-VHDL13_DWOI_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:27 3682
ber01-VHDL13_DWOI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:28:11 3472
ber01-VHDL13_DWOI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:28:16 3771
ber01-VHDL13_DWOI_140400-2602140400-dsw--0-ia5 14-Feb-2026 05:58:16 3873
ber01-VHDL13_DWON_120705-2602120705-dsw--0-ia5 12-Feb-2026 07:05:08 4636
ber01-VHDL13_DWON_120832-2602120832-dsw--0-ia5 12-Feb-2026 08:32:47 4636
ber01-VHDL13_DWON_121158-2602121158-dsw--0-ia5 12-Feb-2026 11:58:11 4636
ber01-VHDL13_DWON_121553-2602121553-dsw--0-ia5 12-Feb-2026 15:53:36 4625
ber01-VHDL13_DWON_121828-2602121828-dsw--0-ia5 12-Feb-2026 18:28:12 3856
ber01-VHDL13_DWON_122125-2602122125-dsw--0-ia5 12-Feb-2026 21:25:21 4047
ber01-VHDL13_DWON_130120-2602130120-dsw--0-ia5 13-Feb-2026 01:20:52 4282
ber01-VHDL13_DWON_130409-2602130409-dsw--0-ia5 13-Feb-2026 04:09:37 4282
ber01-VHDL13_DWON_130628-2602130628-dsw--0-ia5 13-Feb-2026 06:28:17 4335
ber01-VHDL13_DWON_130647-2602130647-dsw--0-ia5 13-Feb-2026 06:47:37 4363
ber01-VHDL13_DWON_130855-2602130855-dsw--0-ia5 13-Feb-2026 08:55:13 4363
ber01-VHDL13_DWON_130928-2602130928-dsw--0-ia5 13-Feb-2026 09:28:37 4363
ber01-VHDL13_DWON_131148-2602131148-dsw--0-ia5 13-Feb-2026 11:48:07 4363
ber01-VHDL13_DWON_131544-2602131544-dsw--0-ia5 13-Feb-2026 15:45:01 3937
ber01-VHDL13_DWON_131731-2602131731-dsw--0-ia5 13-Feb-2026 17:32:03 3986
ber01-VHDL13_DWON_131734-2602131734-dsw--0-ia5 13-Feb-2026 17:34:29 3986
ber01-VHDL13_DWON_132129-2602132129-dsw--0-ia5 13-Feb-2026 21:29:41 4271
ber01-VHDL13_DWON_140356-2602140356-dsw--0-ia5 14-Feb-2026 03:56:29 4254
ber01-VHDL13_DWPG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 2519
ber01-VHDL13_DWPG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 2755
ber01-VHDL13_DWPG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 2785
ber01-VHDL13_DWPG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:12:47 2784
ber01-VHDL13_DWPG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 2380
ber01-VHDL13_DWPG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:04 2700
ber01-VHDL13_DWPG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 2995
ber01-VHDL13_DWPG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2999
ber01-VHDL13_DWPH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:06 2888
ber01-VHDL13_DWPH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 2991
ber01-VHDL13_DWPH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 3118
ber01-VHDL13_DWPH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:13:13 3081
ber01-VHDL13_DWPH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 2590
ber01-VHDL13_DWPH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 2650
ber01-VHDL13_DWPH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 2853
ber01-VHDL13_DWPH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 2826
ber01-VHDL13_DWSG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:30:02 3926
ber01-VHDL13_DWSG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:30:02 3457
ber01-VHDL13_DWSG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:30:02 3818
ber01-VHDL13_DWSG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:07 3853
ber01-VHDL13_DWSG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:30:01 3710
ber01-VHDL13_DWSG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:30:10 3223
ber01-VHDL13_DWSG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:30:05 3562
ber01-VHDL13_DWSG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3914
ber01-VHDL17_DWOG_121200-2602121200-dsw--0-ia5 12-Feb-2026 12:44:51 3334
ber01-VHDL17_DWOG_131200-2602131200-dsw--0-ia5 13-Feb-2026 12:36:02 3093
swis2-VHDL20_DWEG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:01 3652
swis2-VHDL20_DWEG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3019
swis2-VHDL20_DWEG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 3698
swis2-VHDL20_DWEG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4249
swis2-VHDL20_DWEG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 4491
swis2-VHDL20_DWEG_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:17 4477
swis2-VHDL20_DWEG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4032
swis2-VHDL20_DWEG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4304
swis2-VHDL20_DWEG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4397
swis2-VHDL20_DWEH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:01 4361
swis2-VHDL20_DWEH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3872
swis2-VHDL20_DWEH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 4279
swis2-VHDL20_DWEH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4375
swis2-VHDL20_DWEH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 5022
swis2-VHDL20_DWEH_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:17 4972
swis2-VHDL20_DWEH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4122
swis2-VHDL20_DWEH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4402
swis2-VHDL20_DWEH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4373
swis2-VHDL20_DWEI_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:01 3931
swis2-VHDL20_DWEI_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3330
swis2-VHDL20_DWEI_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 3812
swis2-VHDL20_DWEI_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4533
swis2-VHDL20_DWEI_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 4544
swis2-VHDL20_DWEI_130800_COR-2602130800-dsw--0-ia5 13-Feb-2026 09:49:17 4559
swis2-VHDL20_DWEI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 4030
swis2-VHDL20_DWEI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 4270
swis2-VHDL20_DWEI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4449
swis2-VHDL20_DWHG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 4042
swis2-VHDL20_DWHG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3217
swis2-VHDL20_DWHG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 2663
swis2-VHDL20_DWHG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:07 2660
swis2-VHDL20_DWHG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3219
swis2-VHDL20_DWHG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3064
swis2-VHDL20_DWHG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3848
swis2-VHDL20_DWHG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3845
swis2-VHDL20_DWHH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 4141
swis2-VHDL20_DWHH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3402
swis2-VHDL20_DWHH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 2975
swis2-VHDL20_DWHH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:07 2795
swis2-VHDL20_DWHH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3236
swis2-VHDL20_DWHH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3016
swis2-VHDL20_DWHH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3437
swis2-VHDL20_DWHH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:06 3436
swis2-VHDL20_DWLG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 3252
swis2-VHDL20_DWLG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:00 3023
swis2-VHDL20_DWLG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 3091
swis2-VHDL20_DWLG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:11 3177
swis2-VHDL20_DWLG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3453
swis2-VHDL20_DWLG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3648
swis2-VHDL20_DWLG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3862
swis2-VHDL20_DWLG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3648
swis2-VHDL20_DWLH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 3202
swis2-VHDL20_DWLH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:00 3412
swis2-VHDL20_DWLH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 3485
swis2-VHDL20_DWLH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:11 3291
swis2-VHDL20_DWLH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3598
swis2-VHDL20_DWLH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3318
swis2-VHDL20_DWLH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3616
swis2-VHDL20_DWLH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3505
swis2-VHDL20_DWLI_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 3322
swis2-VHDL20_DWLI_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:00 3067
swis2-VHDL20_DWLI_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 3124
swis2-VHDL20_DWLI_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:11 2938
swis2-VHDL20_DWLI_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3274
swis2-VHDL20_DWLI_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3535
swis2-VHDL20_DWLI_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3675
swis2-VHDL20_DWLI_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3460
swis2-VHDL20_DWMG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:01 4268
swis2-VHDL20_DWMG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 4451
swis2-VHDL20_DWMG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 4538
swis2-VHDL20_DWMG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4246
swis2-VHDL20_DWMG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 4509
swis2-VHDL20_DWMG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3334
swis2-VHDL20_DWMG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3637
swis2-VHDL20_DWMG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3708
swis2-VHDL20_DWMO_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 4144
swis2-VHDL20_DWMO_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3669
swis2-VHDL20_DWMO_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 4038
swis2-VHDL20_DWMO_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4041
swis2-VHDL20_DWMO_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 4328
swis2-VHDL20_DWMO_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3092
swis2-VHDL20_DWMO_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3236
swis2-VHDL20_DWMO_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3262
swis2-VHDL20_DWMP_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 4300
swis2-VHDL20_DWMP_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3867
swis2-VHDL20_DWMP_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:03 4501
swis2-VHDL20_DWMP_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:02 4175
swis2-VHDL20_DWMP_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:10 4294
swis2-VHDL20_DWMP_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:02 3272
swis2-VHDL20_DWMP_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:02 3670
swis2-VHDL20_DWMP_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:02 3688
swis2-VHDL20_DWPG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 3179
swis2-VHDL20_DWPG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:00 3579
swis2-VHDL20_DWPG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 3348
swis2-VHDL20_DWPG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:11 3169
swis2-VHDL20_DWPG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3013
swis2-VHDL20_DWPG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3333
swis2-VHDL20_DWPG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3538
swis2-VHDL20_DWPG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3442
swis2-VHDL20_DWPH_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:06 3555
swis2-VHDL20_DWPH_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:00 3656
swis2-VHDL20_DWPH_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:07 3600
swis2-VHDL20_DWPH_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:00:11 3503
swis2-VHDL20_DWPH_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 3154
swis2-VHDL20_DWPH_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3214
swis2-VHDL20_DWPH_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3395
swis2-VHDL20_DWPH_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:00:12 3202
swis2-VHDL20_DWSG_120800-2602120800-dsw--0-ia5 12-Feb-2026 09:45:01 4499
swis2-VHDL20_DWSG_121300-2602121300-dsw--0-ia5 12-Feb-2026 14:45:07 4327
swis2-VHDL20_DWSG_121800-2602121800-dsw--0-ia5 12-Feb-2026 19:45:04 3871
swis2-VHDL20_DWSG_130200-2602130200-dsw--0-ia5 13-Feb-2026 03:45:01 4224
swis2-VHDL20_DWSG_130400-2602130400-dsw--0-ia5 13-Feb-2026 06:15:06 4266
swis2-VHDL20_DWSG_130800-2602130800-dsw--0-ia5 13-Feb-2026 09:45:04 4411
swis2-VHDL20_DWSG_131300-2602131300-dsw--0-ia5 13-Feb-2026 14:45:04 3986
swis2-VHDL20_DWSG_131800-2602131800-dsw--0-ia5 13-Feb-2026 19:45:06 3582
swis2-VHDL20_DWSG_140200-2602140200-dsw--0-ia5 14-Feb-2026 03:45:07 3968
swis2-VHDL20_DWSG_140400-2602140400-dsw--0-ia5 14-Feb-2026 06:15:06 4408
wst04-VHDL20_DWEG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:10 237595
wst04-VHDL20_DWEG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:12 235176
wst04-VHDL20_DWEG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 236511
wst04-VHDL20_DWEG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:12 236612
wst04-VHDL20_DWEG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:13 238022
wst04-VHDL20_DWEG_130800_COR-2602130800-omedes-..> 13-Feb-2026 09:49:31 237832
wst04-VHDL20_DWEG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 237135
wst04-VHDL20_DWEG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 238684
wst04-VHDL20_DWEG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:26 238308
wst04-VHDL20_DWEH_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:10 233936
wst04-VHDL20_DWEH_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:12 232909
wst04-VHDL20_DWEH_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:11 232916
wst04-VHDL20_DWEH_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:18 232366
wst04-VHDL20_DWEH_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:17 232348
wst04-VHDL20_DWEH_130800_COR-2602130800-omedes-..> 13-Feb-2026 09:49:37 232200
wst04-VHDL20_DWEH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 231950
wst04-VHDL20_DWEH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 232571
wst04-VHDL20_DWEH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 232069
wst04-VHDL20_DWEI_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:17 330256
wst04-VHDL20_DWEI_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:12 329093
wst04-VHDL20_DWEI_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 329024
wst04-VHDL20_DWEI_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:18 328939
wst04-VHDL20_DWEI_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:23 332279
wst04-VHDL20_DWEI_130800_COR-2602130800-omedes-..> 13-Feb-2026 09:49:37 332185
wst04-VHDL20_DWEI_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 332050
wst04-VHDL20_DWEI_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 332715
wst04-VHDL20_DWEI_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:26 332809
wst04-VHDL20_DWHG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:26 321630
wst04-VHDL20_DWHG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:22 320277
wst04-VHDL20_DWHG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:21 319995
wst04-VHDL20_DWHG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:11 320124
wst04-VHDL20_DWHG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:29 319204
wst04-VHDL20_DWHG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:23 318774
wst04-VHDL20_DWHG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 319012
wst04-VHDL20_DWHG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:12 319050
wst04-VHDL20_DWHH_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:26 309554
wst04-VHDL20_DWHH_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:18 308546
wst04-VHDL20_DWHH_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:21 309193
wst04-VHDL20_DWHH_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:11 308405
wst04-VHDL20_DWHH_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:29 307131
wst04-VHDL20_DWHH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:23 306644
wst04-VHDL20_DWHH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 307104
wst04-VHDL20_DWHH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:12 307254
wst04-VHDL20_DWLG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:32 313593
wst04-VHDL20_DWLG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:26 313345
wst04-VHDL20_DWLG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:27 313679
wst04-VHDL20_DWLG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:42 314008
wst04-VHDL20_DWLG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:36 305646
wst04-VHDL20_DWLG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:21 304876
wst04-VHDL20_DWLG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 304802
wst04-VHDL20_DWLG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 304195
wst04-VHDL20_DWLH_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:32 315561
wst04-VHDL20_DWLH_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:22 316226
wst04-VHDL20_DWLH_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:21 316033
wst04-VHDL20_DWLH_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:42 316119
wst04-VHDL20_DWLH_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:33 305716
wst04-VHDL20_DWLH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 304953
wst04-VHDL20_DWLH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 305828
wst04-VHDL20_DWLH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 305037
wst04-VHDL20_DWLI_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:32 307677
wst04-VHDL20_DWLI_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:22 306825
wst04-VHDL20_DWLI_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:21 306986
wst04-VHDL20_DWLI_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:42 306820
wst04-VHDL20_DWLI_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:33 306590
wst04-VHDL20_DWLI_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 306464
wst04-VHDL20_DWLI_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 306841
wst04-VHDL20_DWLI_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:42 306024
wst04-VHDL20_DWMG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:22 530729
wst04-VHDL20_DWMG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:16 531208
wst04-VHDL20_DWMG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 531611
wst04-VHDL20_DWMG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:22 530579
wst04-VHDL20_DWMG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:23 519648
wst04-VHDL20_DWMG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 516754
wst04-VHDL20_DWMG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 517290
wst04-VHDL20_DWMG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 517247
wst04-VHDL20_DWMO_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:22 422030
wst04-VHDL20_DWMO_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:16 420617
wst04-VHDL20_DWMO_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 421721
wst04-VHDL20_DWMO_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:18 422151
wst04-VHDL20_DWMO_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:23 415983
wst04-VHDL20_DWMO_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 413741
wst04-VHDL20_DWMO_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 414577
wst04-VHDL20_DWMO_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 415090
wst04-VHDL20_DWMP_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:22 555735
wst04-VHDL20_DWMP_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:16 554338
wst04-VHDL20_DWMP_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 553847
wst04-VHDL20_DWMP_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:26 554619
wst04-VHDL20_DWMP_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:26 545191
wst04-VHDL20_DWMP_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:17 542382
wst04-VHDL20_DWMP_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:17 541722
wst04-VHDL20_DWMP_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:22 542826
wst04-VHDL20_DWPG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:32 355050
wst04-VHDL20_DWPG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:26 311158
wst04-VHDL20_DWPG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:27 310995
wst04-VHDL20_DWPG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:32 310861
wst04-VHDL20_DWPG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:33 357997
wst04-VHDL20_DWPG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:27 312885
wst04-VHDL20_DWPG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:27 313505
wst04-VHDL20_DWPG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:32 312844
wst04-VHDL20_DWPH_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:26 272682
wst04-VHDL20_DWPH_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:22 272589
wst04-VHDL20_DWPH_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:21 227926
wst04-VHDL20_DWPH_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:00:32 227924
wst04-VHDL20_DWPH_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:33 271922
wst04-VHDL20_DWPH_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:21 272322
wst04-VHDL20_DWPH_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:21 227538
wst04-VHDL20_DWPH_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:00:32 227274
wst04-VHDL20_DWSG_120800-2602120800-omedes--0.pdf 12-Feb-2026 09:45:10 333425
wst04-VHDL20_DWSG_121300-2602121300-omedes--0.pdf 12-Feb-2026 14:45:39 333352
wst04-VHDL20_DWSG_121800-2602121800-omedes--0.pdf 12-Feb-2026 19:45:12 332021
wst04-VHDL20_DWSG_130200-2602130200-omedes--0.pdf 13-Feb-2026 03:45:17 332813
wst04-VHDL20_DWSG_130400-2602130400-omedes--0.pdf 13-Feb-2026 06:15:12 331135
wst04-VHDL20_DWSG_130800-2602130800-omedes--0.pdf 13-Feb-2026 09:45:13 323168
wst04-VHDL20_DWSG_131300-2602131300-omedes--0.pdf 13-Feb-2026 14:45:11 323234
wst04-VHDL20_DWSG_131800-2602131800-omedes--0.pdf 13-Feb-2026 19:45:11 323187
wst04-VHDL20_DWSG_140200-2602140200-omedes--0.pdf 14-Feb-2026 03:45:11 324203
wst04-VHDL20_DWSG_140400-2602140400-omedes--0.pdf 14-Feb-2026 06:15:16 324755