Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Feb-2026 15:35:52 4915
FPDL13_DWMZ_240600 24-Feb-2026 12:42:45 4833
FPDL13_DWMZ_250600 25-Feb-2026 11:42:23 2827
SXDL31_DWAV_231800 23-Feb-2026 17:51:39 7166
SXDL31_DWAV_240800 24-Feb-2026 08:11:38 7012
SXDL31_DWAV_241800 24-Feb-2026 17:01:40 6555
SXDL31_DWAV_250800 25-Feb-2026 09:06:23 12053
SXDL31_DWAV_LATEST 25-Feb-2026 09:06:23 12053
SXDL33_DWAV_240000 24-Feb-2026 11:20:19 8167
SXDL33_DWAV_250000 25-Feb-2026 11:06:49 9515
SXDL33_DWAV_LATEST 25-Feb-2026 11:06:49 9515
ber01-FWDL39_DWMS_231230-2602231230-dsw--0-ia5 23-Feb-2026 13:28:26 2092
ber01-FWDL39_DWMS_241230-2602241230-dsw--0-ia5 24-Feb-2026 12:39:16 1533
ber01-FWDL39_DWMS_251230-2602251230-dsw--0-ia5 25-Feb-2026 12:12:22 1478
ber01-VHDL13_DWEH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:17 2219
ber01-VHDL13_DWEH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:28:12 2172
ber01-VHDL13_DWEH_240400-2602240400-dsw--0-ia5 24-Feb-2026 05:58:16 2257
ber01-VHDL13_DWEH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:28:17 2361
ber01-VHDL13_DWEH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:17 2096
ber01-VHDL13_DWEH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:11 2416
ber01-VHDL13_DWEH_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:17 2424
ber01-VHDL13_DWEH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2416
ber01-VHDL13_DWHG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:09 2439
ber01-VHDL13_DWHG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:09 2628
ber01-VHDL13_DWHG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:08 2715
ber01-VHDL13_DWHG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2978
ber01-VHDL13_DWHG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2854
ber01-VHDL13_DWHG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:11 2719
ber01-VHDL13_DWHG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2620
ber01-VHDL13_DWHG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2622
ber01-VHDL13_DWHH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:09 2557
ber01-VHDL13_DWHH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:09 2697
ber01-VHDL13_DWHH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:08 2697
ber01-VHDL13_DWHH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2772
ber01-VHDL13_DWHH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2712
ber01-VHDL13_DWHH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:11 2566
ber01-VHDL13_DWHH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2498
ber01-VHDL13_DWHH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2668
ber01-VHDL13_DWLG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2499
ber01-VHDL13_DWLG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:03 2822
ber01-VHDL13_DWLG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:02 2379
ber01-VHDL13_DWLG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2530
ber01-VHDL13_DWLG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2255
ber01-VHDL13_DWLG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2349
ber01-VHDL13_DWLG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 1962
ber01-VHDL13_DWLG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 1964
ber01-VHDL13_DWLH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2392
ber01-VHDL13_DWLH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:04 2698
ber01-VHDL13_DWLH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:02 2402
ber01-VHDL13_DWLH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2402
ber01-VHDL13_DWLH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2164
ber01-VHDL13_DWLH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2327
ber01-VHDL13_DWLH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2133
ber01-VHDL13_DWLH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2138
ber01-VHDL13_DWLI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2317
ber01-VHDL13_DWLI_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:03 2708
ber01-VHDL13_DWLI_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:02 2354
ber01-VHDL13_DWLI_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2353
ber01-VHDL13_DWLI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2129
ber01-VHDL13_DWLI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2280
ber01-VHDL13_DWLI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2143
ber01-VHDL13_DWLI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2148
ber01-VHDL13_DWMG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 3184
ber01-VHDL13_DWMG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:09 3812
ber01-VHDL13_DWMG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:06 3840
ber01-VHDL13_DWMG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:04 3786
ber01-VHDL13_DWMG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2647
ber01-VHDL13_DWMG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3240
ber01-VHDL13_DWMG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3280
ber01-VHDL13_DWMG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3088
ber01-VHDL13_DWMO_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2347
ber01-VHDL13_DWMO_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:09 2710
ber01-VHDL13_DWMO_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:06 2706
ber01-VHDL13_DWMO_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:04 3027
ber01-VHDL13_DWMO_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2555
ber01-VHDL13_DWMO_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3118
ber01-VHDL13_DWMO_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3157
ber01-VHDL13_DWMO_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2960
ber01-VHDL13_DWMP_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2945
ber01-VHDL13_DWMP_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:09 3481
ber01-VHDL13_DWMP_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:06 3530
ber01-VHDL13_DWMP_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:04 3620
ber01-VHDL13_DWMP_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2489
ber01-VHDL13_DWMP_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3260
ber01-VHDL13_DWMP_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3302
ber01-VHDL13_DWMP_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3011
ber01-VHDL13_DWOG_231700-2602231700-dsw--0-ia5 23-Feb-2026 19:00:04 4490
ber01-VHDL13_DWOG_240300-2602240300-dsw--0-ia5 24-Feb-2026 04:00:01 4390
ber01-VHDL13_DWOG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:04 4293
ber01-VHDL13_DWOG_241700-2602241700-dsw--0-ia5 24-Feb-2026 19:00:02 4031
ber01-VHDL13_DWOG_250300-2602250300-dsw--0-ia5 25-Feb-2026 04:00:02 4420
ber01-VHDL13_DWOG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 4035
ber01-VHDL13_DWOH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:17 2146
ber01-VHDL13_DWOH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:28:12 2178
ber01-VHDL13_DWOH_240400-2602240400-dsw--0-ia5 24-Feb-2026 05:58:12 2244
ber01-VHDL13_DWOH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:28:17 2331
ber01-VHDL13_DWOH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:17 2080
ber01-VHDL13_DWOH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:11 2264
ber01-VHDL13_DWOH_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:17 2289
ber01-VHDL13_DWOH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2220
ber01-VHDL13_DWOI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:11 1945
ber01-VHDL13_DWOI_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:28:16 2266
ber01-VHDL13_DWOI_240400-2602240400-dsw--0-ia5 24-Feb-2026 05:58:16 2321
ber01-VHDL13_DWOI_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:28:13 2336
ber01-VHDL13_DWOI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:11 2093
ber01-VHDL13_DWOI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:16 2340
ber01-VHDL13_DWOI_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:11 2371
ber01-VHDL13_DWOI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2308
ber01-VHDL13_DWON_231542-2602231542-dsw--0-ia5 23-Feb-2026 15:42:41 3819
ber01-VHDL13_DWON_231558-2602231558-dsw--0-ia5 23-Feb-2026 15:58:42 3819
ber01-VHDL13_DWON_231801-2602231801-dsw--0-ia5 23-Feb-2026 18:01:41 3396
ber01-VHDL13_DWON_232028-2602232028-dsw--0-ia5 23-Feb-2026 20:28:11 3396
ber01-VHDL13_DWON_240149-2602240149-dsw--0-ia5 24-Feb-2026 01:49:20 3434
ber01-VHDL13_DWON_240317-2602240317-dsw--0-ia5 24-Feb-2026 03:17:31 3457
ber01-VHDL13_DWON_240350-2602240350-dsw--0-ia5 24-Feb-2026 03:50:51 3457
ber01-VHDL13_DWON_240409-2602240409-dsw--0-ia5 24-Feb-2026 04:09:31 3457
ber01-VHDL13_DWON_240617-2602240617-dsw--0-ia5 24-Feb-2026 06:17:07 3673
ber01-VHDL13_DWON_240653-2602240653-dsw--0-ia5 24-Feb-2026 06:53:07 3743
ber01-VHDL13_DWON_240912-2602240912-dsw--0-ia5 24-Feb-2026 09:12:31 3743
ber01-VHDL13_DWON_241545-2602241545-dsw--0-ia5 24-Feb-2026 15:45:51 3119
ber01-VHDL13_DWON_241659-2602241659-dsw--0-ia5 24-Feb-2026 16:59:21 3284
ber01-VHDL13_DWON_241817-2602241817-dsw--0-ia5 24-Feb-2026 18:17:16 3197
ber01-VHDL13_DWON_250355-2602250355-dsw--0-ia5 25-Feb-2026 03:55:07 4085
ber01-VHDL13_DWON_250554-2602250554-dsw--0-ia5 25-Feb-2026 05:54:57 3761
ber01-VHDL13_DWON_250708-2602250708-dsw--0-ia5 25-Feb-2026 07:08:16 3761
ber01-VHDL13_DWON_250953-2602250953-dsw--0-ia5 25-Feb-2026 09:53:36 3869
ber01-VHDL13_DWON_251229-2602251229-dsw--0-ia5 25-Feb-2026 12:29:07 3700
ber01-VHDL13_DWPG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2080
ber01-VHDL13_DWPG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:03 2213
ber01-VHDL13_DWPG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:02 2400
ber01-VHDL13_DWPG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2364
ber01-VHDL13_DWPG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 1910
ber01-VHDL13_DWPG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2245
ber01-VHDL13_DWPG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2008
ber01-VHDL13_DWPG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 1973
ber01-VHDL13_DWPH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 1899
ber01-VHDL13_DWPH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:04 2226
ber01-VHDL13_DWPH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:02 2197
ber01-VHDL13_DWPH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:15 2073
ber01-VHDL13_DWPH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2033
ber01-VHDL13_DWPH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2288
ber01-VHDL13_DWPH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2000
ber01-VHDL13_DWPH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2004
ber01-VHDL13_DWSG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2657
ber01-VHDL13_DWSG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:30:03 3092
ber01-VHDL13_DWSG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:06 3289
ber01-VHDL13_DWSG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:30:04 3097
ber01-VHDL13_DWSG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2558
ber01-VHDL13_DWSG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3075
ber01-VHDL13_DWSG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 3179
ber01-VHDL13_DWSG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3060
ber01-VHDL17_DWOG_241200-2602241200-dsw--0-ia5 24-Feb-2026 11:55:17 3899
ber01-VHDL17_DWOG_251200-2602251200-dsw--0-ia5 25-Feb-2026 11:41:26 3133
swis2-VHDL20_DWEG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2476
swis2-VHDL20_DWEG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2458
swis2-VHDL20_DWEG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:03 2565
swis2-VHDL20_DWEG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:06 2810
swis2-VHDL20_DWEG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2407
swis2-VHDL20_DWEG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2541
swis2-VHDL20_DWEG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2612
swis2-VHDL20_DWEG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2698
swis2-VHDL20_DWEH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2578
swis2-VHDL20_DWEH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2497
swis2-VHDL20_DWEH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:03 2593
swis2-VHDL20_DWEH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:06 2865
swis2-VHDL20_DWEH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2452
swis2-VHDL20_DWEH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2738
swis2-VHDL20_DWEH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2762
swis2-VHDL20_DWEH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2919
swis2-VHDL20_DWEI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2300
swis2-VHDL20_DWEI_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2561
swis2-VHDL20_DWEI_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:03 2673
swis2-VHDL20_DWEI_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:06 2862
swis2-VHDL20_DWEI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2445
swis2-VHDL20_DWEI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2632
swis2-VHDL20_DWEI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2725
swis2-VHDL20_DWEI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2833
swis2-VHDL20_DWHG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:06 2622
swis2-VHDL20_DWHG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2814
swis2-VHDL20_DWHG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:08 2898
swis2-VHDL20_DWHG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:06 3516
swis2-VHDL20_DWHG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 3037
swis2-VHDL20_DWHG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2905
swis2-VHDL20_DWHG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2803
swis2-VHDL20_DWHG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3159
swis2-VHDL20_DWHH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:06 2743
swis2-VHDL20_DWHH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2883
swis2-VHDL20_DWHH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:08 2883
swis2-VHDL20_DWHH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 3318
swis2-VHDL20_DWHH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2898
swis2-VHDL20_DWHH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2752
swis2-VHDL20_DWHH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2684
swis2-VHDL20_DWHH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3211
swis2-VHDL20_DWLG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2960
swis2-VHDL20_DWLG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 3283
swis2-VHDL20_DWLG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:12 2794
swis2-VHDL20_DWLG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 3094
swis2-VHDL20_DWLG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2663
swis2-VHDL20_DWLG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2757
swis2-VHDL20_DWLG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2307
swis2-VHDL20_DWLG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2457
swis2-VHDL20_DWLH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2741
swis2-VHDL20_DWLH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 3047
swis2-VHDL20_DWLH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:12 2751
swis2-VHDL20_DWLH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 2904
swis2-VHDL20_DWLH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2513
swis2-VHDL20_DWLH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2676
swis2-VHDL20_DWLH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2485
swis2-VHDL20_DWLH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2640
swis2-VHDL20_DWLI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2661
swis2-VHDL20_DWLI_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 3052
swis2-VHDL20_DWLI_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:12 2697
swis2-VHDL20_DWLI_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 2844
swis2-VHDL20_DWLI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2472
swis2-VHDL20_DWLI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2623
swis2-VHDL20_DWLI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2490
swis2-VHDL20_DWLI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2642
swis2-VHDL20_DWMG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 3716
swis2-VHDL20_DWMG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:07 4331
swis2-VHDL20_DWMG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:07 4324
swis2-VHDL20_DWMG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 4520
swis2-VHDL20_DWMG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 3136
swis2-VHDL20_DWMG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3715
swis2-VHDL20_DWMG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3740
swis2-VHDL20_DWMG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3791
swis2-VHDL20_DWMO_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2724
swis2-VHDL20_DWMO_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:07 3085
swis2-VHDL20_DWMO_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:07 3174
swis2-VHDL20_DWMO_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 3737
swis2-VHDL20_DWMO_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 3028
swis2-VHDL20_DWMO_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3579
swis2-VHDL20_DWMO_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3607
swis2-VHDL20_DWMO_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3642
swis2-VHDL20_DWMP_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 3434
swis2-VHDL20_DWMP_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:07 4034
swis2-VHDL20_DWMP_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:07 3999
swis2-VHDL20_DWMP_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 4348
swis2-VHDL20_DWMP_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2963
swis2-VHDL20_DWMP_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3725
swis2-VHDL20_DWMP_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3765
swis2-VHDL20_DWMP_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3723
swis2-VHDL20_DWPG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2581
swis2-VHDL20_DWPG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2543
swis2-VHDL20_DWPG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:12 2767
swis2-VHDL20_DWPG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 2867
swis2-VHDL20_DWPG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2373
swis2-VHDL20_DWPG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2575
swis2-VHDL20_DWPG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2337
swis2-VHDL20_DWPG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2435
swis2-VHDL20_DWPH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2360
swis2-VHDL20_DWPH_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:01 2555
swis2-VHDL20_DWPH_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:00:12 2526
swis2-VHDL20_DWPH_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 2536
swis2-VHDL20_DWPH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2570
swis2-VHDL20_DWPH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2691
swis2-VHDL20_DWPH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2331
swis2-VHDL20_DWPH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2466
swis2-VHDL20_DWSG_231300-2602231300-dsw--0-ia5 23-Feb-2026 14:45:07 3450
swis2-VHDL20_DWSG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 3015
swis2-VHDL20_DWSG_240200-2602240200-dsw--0-ia5 24-Feb-2026 03:45:07 3438
swis2-VHDL20_DWSG_240400-2602240400-dsw--0-ia5 24-Feb-2026 06:15:07 3745
swis2-VHDL20_DWSG_240800-2602240800-dsw--0-ia5 24-Feb-2026 09:45:01 3601
swis2-VHDL20_DWSG_241300-2602241300-dsw--0-ia5 24-Feb-2026 14:45:17 3423
swis2-VHDL20_DWSG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2914
swis2-VHDL20_DWSG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3481
swis2-VHDL20_DWSG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3535
swis2-VHDL20_DWSG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3563
wst04-VHDL20_DWEG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 247279
wst04-VHDL20_DWEG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:17 247679
wst04-VHDL20_DWEG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:17 247076
wst04-VHDL20_DWEG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:12 226724
wst04-VHDL20_DWEG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 247344
wst04-VHDL20_DWEG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 248271
wst04-VHDL20_DWEG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:18 247312
wst04-VHDL20_DWEG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:12 223359
wst04-VHDL20_DWEH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 240254
wst04-VHDL20_DWEH_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:13 240955
wst04-VHDL20_DWEH_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:23 240002
wst04-VHDL20_DWEH_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:16 239053
wst04-VHDL20_DWEH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 238396
wst04-VHDL20_DWEH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 239617
wst04-VHDL20_DWEH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:18 238739
wst04-VHDL20_DWEH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 240360
wst04-VHDL20_DWEI_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 353459
wst04-VHDL20_DWEI_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:17 354161
wst04-VHDL20_DWEI_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:27 353624
wst04-VHDL20_DWEI_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:26 334466
wst04-VHDL20_DWEI_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 355062
wst04-VHDL20_DWEI_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 355707
wst04-VHDL20_DWEI_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 355240
wst04-VHDL20_DWEI_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 353881
wst04-VHDL20_DWHG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 342878
wst04-VHDL20_DWHG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:21 342255
wst04-VHDL20_DWHG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:12 342503
wst04-VHDL20_DWHG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:26 314552
wst04-VHDL20_DWHG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 340079
wst04-VHDL20_DWHG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 340599
wst04-VHDL20_DWHG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:11 340420
wst04-VHDL20_DWHG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 346329
wst04-VHDL20_DWHH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 327023
wst04-VHDL20_DWHH_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:17 327024
wst04-VHDL20_DWHH_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:12 327057
wst04-VHDL20_DWHH_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:16 312638
wst04-VHDL20_DWHH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 327816
wst04-VHDL20_DWHH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 328241
wst04-VHDL20_DWHH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:11 328158
wst04-VHDL20_DWHH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:26 311544
wst04-VHDL20_DWLG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 350582
wst04-VHDL20_DWLG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:25 351020
wst04-VHDL20_DWLG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:41 350335
wst04-VHDL20_DWLG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:30 342451
wst04-VHDL20_DWLG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 341591
wst04-VHDL20_DWLG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 342556
wst04-VHDL20_DWLG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 341728
wst04-VHDL20_DWLG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:36 322865
wst04-VHDL20_DWLH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 344069
wst04-VHDL20_DWLH_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:21 344239
wst04-VHDL20_DWLH_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:41 343939
wst04-VHDL20_DWLH_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:30 317739
wst04-VHDL20_DWLH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 334034
wst04-VHDL20_DWLH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 335459
wst04-VHDL20_DWLH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 334935
wst04-VHDL20_DWLH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 316872
wst04-VHDL20_DWLI_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 344033
wst04-VHDL20_DWLI_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:25 344161
wst04-VHDL20_DWLI_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:41 343589
wst04-VHDL20_DWLI_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:30 325643
wst04-VHDL20_DWLI_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 342180
wst04-VHDL20_DWLI_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 343426
wst04-VHDL20_DWLI_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 343097
wst04-VHDL20_DWLI_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 322286
wst04-VHDL20_DWMG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 589176
wst04-VHDL20_DWMG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:15 592063
wst04-VHDL20_DWMG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:21 591676
wst04-VHDL20_DWMG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:22 543886
wst04-VHDL20_DWMG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 580687
wst04-VHDL20_DWMG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 580771
wst04-VHDL20_DWMG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:26 580663
wst04-VHDL20_DWMG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 432359
wst04-VHDL20_DWMO_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 472439
wst04-VHDL20_DWMO_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:11 475124
wst04-VHDL20_DWMO_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:21 475643
wst04-VHDL20_DWMO_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:16 457892
wst04-VHDL20_DWMO_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 474108
wst04-VHDL20_DWMO_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:11 474238
wst04-VHDL20_DWMO_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 474761
wst04-VHDL20_DWMO_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 432230
wst04-VHDL20_DWMP_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 591824
wst04-VHDL20_DWMP_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:15 593297
wst04-VHDL20_DWMP_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:27 594338
wst04-VHDL20_DWMP_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:16 518515
wst04-VHDL20_DWMP_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 581018
wst04-VHDL20_DWMP_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:11 580416
wst04-VHDL20_DWMP_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:26 581540
wst04-VHDL20_DWMP_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:22 511786
wst04-VHDL20_DWPG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 356368
wst04-VHDL20_DWPG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:25 356288
wst04-VHDL20_DWPG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:33 356374
wst04-VHDL20_DWPG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:36 376660
wst04-VHDL20_DWPG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 350293
wst04-VHDL20_DWPG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 350580
wst04-VHDL20_DWPG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:31 349995
wst04-VHDL20_DWPG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 351206
wst04-VHDL20_DWPH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 285202
wst04-VHDL20_DWPH_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:21 240899
wst04-VHDL20_DWPH_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:00:31 241171
wst04-VHDL20_DWPH_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:30 286050
wst04-VHDL20_DWPH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 286027
wst04-VHDL20_DWPH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 241500
wst04-VHDL20_DWPH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:31 241286
wst04-VHDL20_DWPH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 268253
wst04-VHDL20_DWSG_231300-2602231300-omedes--0.pdf 23-Feb-2026 14:45:11 361794
wst04-VHDL20_DWSG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 361158
wst04-VHDL20_DWSG_240200-2602240200-omedes--0.pdf 24-Feb-2026 03:45:21 361142
wst04-VHDL20_DWSG_240400-2602240400-omedes--0.pdf 24-Feb-2026 06:15:17 360941
wst04-VHDL20_DWSG_240800-2602240800-omedes--0.pdf 24-Feb-2026 09:45:12 342264
wst04-VHDL20_DWSG_241300-2602241300-omedes--0.pdf 24-Feb-2026 14:45:17 342466
wst04-VHDL20_DWSG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 360413
wst04-VHDL20_DWSG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 360993
wst04-VHDL20_DWSG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 361305
wst04-VHDL20_DWSG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:12 337662