Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Mar-2026 14:45:58 5080
FPDL13_DWMZ_130600 13-Mar-2026 14:45:27 5333
SXDL31_DWAV_121800 12-Mar-2026 17:27:11 6722
SXDL31_DWAV_130800 13-Mar-2026 08:41:05 9569
SXDL31_DWAV_131800 13-Mar-2026 17:46:01 7016
SXDL31_DWAV_LATEST 13-Mar-2026 17:46:01 7016
SXDL33_DWAV_120000 12-Mar-2026 10:43:49 8919
SXDL33_DWAV_130000 13-Mar-2026 10:59:19 9076
SXDL33_DWAV_LATEST 13-Mar-2026 10:59:19 9076
ber01-FWDL39_DWMS_121230-2603121230-dsw--0-ia5 12-Mar-2026 12:25:22 1138
ber01-FWDL39_DWMS_131230-2603131230-dsw--0-ia5 13-Mar-2026 13:00:47 2650
ber01-VHDL13_DWEH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:28:17 2969
ber01-VHDL13_DWEH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:28:17 2698
ber01-VHDL13_DWEH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:28:11 2895
ber01-VHDL13_DWEH_130400-2603130400-dsw--0-ia5 13-Mar-2026 05:58:15 2901
ber01-VHDL13_DWEH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:16 2904
ber01-VHDL13_DWEH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 3142
ber01-VHDL13_DWEH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:17 3397
ber01-VHDL13_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 3160
ber01-VHDL13_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:16 3115
ber01-VHDL13_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 3274
ber01-VHDL13_DWHG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:06 4451
ber01-VHDL13_DWHG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 3516
ber01-VHDL13_DWHG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:10 3347
ber01-VHDL13_DWHG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:07 3341
ber01-VHDL13_DWHG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 4173
ber01-VHDL13_DWHG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:46:07 4125
ber01-VHDL13_DWHG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:07 3509
ber01-VHDL13_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2869
ber01-VHDL13_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 2940
ber01-VHDL13_DWHH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:06 3335
ber01-VHDL13_DWHH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 2813
ber01-VHDL13_DWHH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:10 2781
ber01-VHDL13_DWHH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 2763
ber01-VHDL13_DWHH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 2946
ber01-VHDL13_DWHH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:46:27 2903
ber01-VHDL13_DWHH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:07 2406
ber01-VHDL13_DWHH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2202
ber01-VHDL13_DWHH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:06 2236
ber01-VHDL13_DWLG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2656
ber01-VHDL13_DWLG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 2556
ber01-VHDL13_DWLG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 2359
ber01-VHDL13_DWLG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:01 2567
ber01-VHDL13_DWLG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2762
ber01-VHDL13_DWLG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2244
ber01-VHDL13_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2420
ber01-VHDL13_DWLG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2287
ber01-VHDL13_DWLH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2883
ber01-VHDL13_DWLH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 2695
ber01-VHDL13_DWLH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 2757
ber01-VHDL13_DWLH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:01 3263
ber01-VHDL13_DWLH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 3618
ber01-VHDL13_DWLH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2503
ber01-VHDL13_DWLH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2577
ber01-VHDL13_DWLH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2474
ber01-VHDL13_DWLI_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2789
ber01-VHDL13_DWLI_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 2747
ber01-VHDL13_DWLI_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 2658
ber01-VHDL13_DWLI_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:01 2708
ber01-VHDL13_DWLI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 3322
ber01-VHDL13_DWLI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2378
ber01-VHDL13_DWLI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2493
ber01-VHDL13_DWLI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2319
ber01-VHDL13_DWMG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2970
ber01-VHDL13_DWMG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:02 2908
ber01-VHDL13_DWMG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 3248
ber01-VHDL13_DWMG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:07 3236
ber01-VHDL13_DWMG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3609
ber01-VHDL13_DWMG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:36:28 3615
ber01-VHDL13_DWMG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3536
ber01-VHDL13_DWMG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3524
ber01-VHDL13_DWMG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3370
ber01-VHDL13_DWMO_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2936
ber01-VHDL13_DWMO_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:02 2947
ber01-VHDL13_DWMO_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 3203
ber01-VHDL13_DWMO_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:07 3191
ber01-VHDL13_DWMO_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 2876
ber01-VHDL13_DWMO_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2672
ber01-VHDL13_DWMO_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2937
ber01-VHDL13_DWMO_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2937
ber01-VHDL13_DWMP_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2827
ber01-VHDL13_DWMP_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:02 2508
ber01-VHDL13_DWMP_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 3045
ber01-VHDL13_DWMP_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:07 3059
ber01-VHDL13_DWMP_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3184
ber01-VHDL13_DWMP_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3606
ber01-VHDL13_DWMP_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3613
ber01-VHDL13_DWMP_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3593
ber01-VHDL13_DWOG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:06 5089
ber01-VHDL13_DWOG_121700-2603121700-dsw--0-ia5 12-Mar-2026 19:00:02 4607
ber01-VHDL13_DWOG_130300-2603130300-dsw--0-ia5 13-Mar-2026 04:00:06 4697
ber01-VHDL13_DWOG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 4453
ber01-VHDL13_DWOG_131700-2603131700-dsw--0-ia5 13-Mar-2026 19:00:03 5200
ber01-VHDL13_DWOG_140300-2603140300-dsw--0-ia5 14-Mar-2026 04:00:05 4603
ber01-VHDL13_DWOH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:28:17 2720
ber01-VHDL13_DWOH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:28:17 2533
ber01-VHDL13_DWOH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:28:11 2803
ber01-VHDL13_DWOH_130400-2603130400-dsw--0-ia5 13-Mar-2026 05:58:15 2816
ber01-VHDL13_DWOH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:16 2816
ber01-VHDL13_DWOH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 2879
ber01-VHDL13_DWOH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:11 3017
ber01-VHDL13_DWOH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2819
ber01-VHDL13_DWOH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:21 2676
ber01-VHDL13_DWOI_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:28:11 2675
ber01-VHDL13_DWOI_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:28:17 2425
ber01-VHDL13_DWOI_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:28:11 2652
ber01-VHDL13_DWOI_130400-2603130400-dsw--0-ia5 13-Mar-2026 05:58:15 2662
ber01-VHDL13_DWOI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:12 2668
ber01-VHDL13_DWOI_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 2721
ber01-VHDL13_DWOI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:11 3243
ber01-VHDL13_DWOI_131800_COR-2603131800-dsw--0-ia5 13-Mar-2026 19:31:15 2973
ber01-VHDL13_DWOI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2824
ber01-VHDL13_DWOI_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 2723
ber01-VHDL13_DWON_120910-2603120910-dsw--0-ia5 12-Mar-2026 09:10:23 4601
ber01-VHDL13_DWON_121159-2603121159-dsw--0-ia5 12-Mar-2026 11:59:26 4601
ber01-VHDL13_DWON_121519-2603121519-dsw--0-ia5 12-Mar-2026 15:19:56 4669
ber01-VHDL13_DWON_121753-2603121753-dsw--0-ia5 12-Mar-2026 17:53:37 4111
ber01-VHDL13_DWON_130306-2603130306-dsw--0-ia5 13-Mar-2026 03:06:55 4065
ber01-VHDL13_DWON_130309-2603130309-dsw--0-ia5 13-Mar-2026 03:09:11 4067
ber01-VHDL13_DWON_130358-2603130358-dsw--0-ia5 13-Mar-2026 03:58:17 4067
ber01-VHDL13_DWON_130617-2603130617-dsw--0-ia5 13-Mar-2026 06:17:46 4747
ber01-VHDL13_DWON_130652-2603130652-dsw--0-ia5 13-Mar-2026 06:52:21 4725
ber01-VHDL13_DWON_130845-2603130845-dsw--0-ia5 13-Mar-2026 08:45:53 4725
ber01-VHDL13_DWON_130918-2603130918-dsw--0-ia5 13-Mar-2026 09:18:23 4725
ber01-VHDL13_DWON_131015-2603131015-dsw--0-ia5 13-Mar-2026 10:16:00 4725
ber01-VHDL13_DWON_131558-2603131558-dsw--0-ia5 13-Mar-2026 15:59:02 4223
ber01-VHDL13_DWON_131756-2603131756-dsw--0-ia5 13-Mar-2026 17:56:46 4223
ber01-VHDL13_DWON_140240-2603140240-dsw--0-ia5 14-Mar-2026 02:40:14 3438
ber01-VHDL13_DWON_140613-2603140613-dsw--0-ia5 14-Mar-2026 06:13:53 4314
ber01-VHDL13_DWON_140655-2603140655-dsw--0-ia5 14-Mar-2026 06:55:27 4314
ber01-VHDL13_DWPG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2145
ber01-VHDL13_DWPG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 1874
ber01-VHDL13_DWPG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 1980
ber01-VHDL13_DWPG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:01 2434
ber01-VHDL13_DWPG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2663
ber01-VHDL13_DWPG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 1980
ber01-VHDL13_DWPG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:15 2173
ber01-VHDL13_DWPG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2129
ber01-VHDL13_DWPH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 2428
ber01-VHDL13_DWPH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:07 2144
ber01-VHDL13_DWPH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 2088
ber01-VHDL13_DWPH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:01 2392
ber01-VHDL13_DWPH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2587
ber01-VHDL13_DWPH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 1885
ber01-VHDL13_DWPH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2130
ber01-VHDL13_DWPH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2125
ber01-VHDL13_DWSG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:30:01 3195
ber01-VHDL13_DWSG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:30:02 3321
ber01-VHDL13_DWSG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:30:04 3496
ber01-VHDL13_DWSG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:07 3403
ber01-VHDL13_DWSG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3432
ber01-VHDL13_DWSG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3356
ber01-VHDL13_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3628
ber01-VHDL13_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3780
ber01-VHDL17_DWOG_121200-2603121200-dsw--0-ia5 12-Mar-2026 12:20:41 3458
ber01-VHDL17_DWOG_131200-2603131200-dsw--0-ia5 13-Mar-2026 12:31:33 3012
swis2-VHDL20_DWEG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3310
swis2-VHDL20_DWEG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2863
swis2-VHDL20_DWEG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3083
swis2-VHDL20_DWEG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3241
swis2-VHDL20_DWEG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3572
swis2-VHDL20_DWEG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3576
swis2-VHDL20_DWEG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3448
swis2-VHDL20_DWEG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3184
swis2-VHDL20_DWEG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3109
swis2-VHDL20_DWEG_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3113
swis2-VHDL20_DWEH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3581
swis2-VHDL20_DWEH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3056
swis2-VHDL20_DWEH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3220
swis2-VHDL20_DWEH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3339
swis2-VHDL20_DWEH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3837
swis2-VHDL20_DWEH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3841
swis2-VHDL20_DWEH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3854
swis2-VHDL20_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3568
swis2-VHDL20_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3701
swis2-VHDL20_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3705
swis2-VHDL20_DWEI_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3296
swis2-VHDL20_DWEI_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2780
swis2-VHDL20_DWEI_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 2948
swis2-VHDL20_DWEI_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3102
swis2-VHDL20_DWEI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3424
swis2-VHDL20_DWEI_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3428
swis2-VHDL20_DWEI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3409
swis2-VHDL20_DWEI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3205
swis2-VHDL20_DWEI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3166
swis2-VHDL20_DWEI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3170
swis2-VHDL20_DWHG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:07 5419
swis2-VHDL20_DWHG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3699
swis2-VHDL20_DWHG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:01 3533
swis2-VHDL20_DWHG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 3524
swis2-VHDL20_DWHG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:06 4951
swis2-VHDL20_DWHG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3692
swis2-VHDL20_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:07 3055
swis2-VHDL20_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3123
swis2-VHDL20_DWHH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:07 3985
swis2-VHDL20_DWHH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2999
swis2-VHDL20_DWHH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:01 2967
swis2-VHDL20_DWHH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 2949
swis2-VHDL20_DWHH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:06 3548
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swis2-VHDL20_DWLG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 2909
swis2-VHDL20_DWLG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3352
swis2-VHDL20_DWLG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2586
swis2-VHDL20_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2762
swis2-VHDL20_DWLG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2676
swis2-VHDL20_DWLH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3383
swis2-VHDL20_DWLH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3045
swis2-VHDL20_DWLH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3107
swis2-VHDL20_DWLH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 3718
swis2-VHDL20_DWLH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4297
swis2-VHDL20_DWLH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2899
swis2-VHDL20_DWLH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2926
swis2-VHDL20_DWLH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2884
swis2-VHDL20_DWLI_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3282
swis2-VHDL20_DWLI_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3095
swis2-VHDL20_DWLI_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3006
swis2-VHDL20_DWLI_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 3052
swis2-VHDL20_DWLI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3959
swis2-VHDL20_DWLI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2722
swis2-VHDL20_DWLI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2837
swis2-VHDL20_DWLI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2728
swis2-VHDL20_DWMG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3544
swis2-VHDL20_DWMG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3361
swis2-VHDL20_DWMG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3702
swis2-VHDL20_DWMG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3606
swis2-VHDL20_DWMG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4249
swis2-VHDL20_DWMG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:36:28 4253
swis2-VHDL20_DWMG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3906
swis2-VHDL20_DWMG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3895
swis2-VHDL20_DWMG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3843
swis2-VHDL20_DWMO_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3518
swis2-VHDL20_DWMO_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 3390
swis2-VHDL20_DWMO_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3649
swis2-VHDL20_DWMO_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3565
swis2-VHDL20_DWMO_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3480
swis2-VHDL20_DWMO_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3046
swis2-VHDL20_DWMO_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3314
swis2-VHDL20_DWMO_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3418
swis2-VHDL20_DWMP_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3407
swis2-VHDL20_DWMP_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2972
swis2-VHDL20_DWMP_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 3466
swis2-VHDL20_DWMP_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3429
swis2-VHDL20_DWMP_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3809
swis2-VHDL20_DWMP_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3965
swis2-VHDL20_DWMP_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3986
swis2-VHDL20_DWMP_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3814
swis2-VHDL20_DWPG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 2606
swis2-VHDL20_DWPG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2335
swis2-VHDL20_DWPG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 2311
swis2-VHDL20_DWPG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 2760
swis2-VHDL20_DWPG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3122
swis2-VHDL20_DWPG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2439
swis2-VHDL20_DWPG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2502
swis2-VHDL20_DWPG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2455
swis2-VHDL20_DWPH_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 2889
swis2-VHDL20_DWPH_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:06 2605
swis2-VHDL20_DWPH_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:07 2418
swis2-VHDL20_DWPH_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:00:11 2720
swis2-VHDL20_DWPH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3046
swis2-VHDL20_DWPH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2344
swis2-VHDL20_DWPH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2458
swis2-VHDL20_DWPH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2453
swis2-VHDL20_DWSG_120800-2603120800-dsw--0-ia5 12-Mar-2026 09:45:02 3772
swis2-VHDL20_DWSG_121300-2603121300-dsw--0-ia5 12-Mar-2026 14:45:08 3687
swis2-VHDL20_DWSG_121800-2603121800-dsw--0-ia5 12-Mar-2026 19:45:02 3697
swis2-VHDL20_DWSG_130200-2603130200-dsw--0-ia5 13-Mar-2026 03:45:01 3862
swis2-VHDL20_DWSG_130400-2603130400-dsw--0-ia5 13-Mar-2026 06:15:06 3812
swis2-VHDL20_DWSG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4043
swis2-VHDL20_DWSG_131300-2603131300-dsw--0-ia5 13-Mar-2026 14:45:15 3875
swis2-VHDL20_DWSG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3771
swis2-VHDL20_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 4036
swis2-VHDL20_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 4215
wst04-VHDL20_DWEG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:13 248625
wst04-VHDL20_DWEG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:12 246828
wst04-VHDL20_DWEG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:22 248790
wst04-VHDL20_DWEG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:16 247823
wst04-VHDL20_DWEG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 251854
wst04-VHDL20_DWEG_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 249769
wst04-VHDL20_DWEG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 251996
wst04-VHDL20_DWEG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:15 251482
wst04-VHDL20_DWEG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:11 250097
wst04-VHDL20_DWEG_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250097
wst04-VHDL20_DWEH_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:13 244403
wst04-VHDL20_DWEH_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:12 243085
wst04-VHDL20_DWEH_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:17 246085
wst04-VHDL20_DWEH_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:16 245137
wst04-VHDL20_DWEH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 251054
wst04-VHDL20_DWEH_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 246217
wst04-VHDL20_DWEH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 251362
wst04-VHDL20_DWEH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 251353
wst04-VHDL20_DWEH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:17 250927
wst04-VHDL20_DWEH_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250927
wst04-VHDL20_DWEI_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:16 353018
wst04-VHDL20_DWEI_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:12 352113
wst04-VHDL20_DWEI_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:22 353293
wst04-VHDL20_DWEI_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:22 352808
wst04-VHDL20_DWEI_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:16 358015
wst04-VHDL20_DWEI_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 353808
wst04-VHDL20_DWEI_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 358758
wst04-VHDL20_DWEI_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:15 358136
wst04-VHDL20_DWEI_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:23 357689
wst04-VHDL20_DWEI_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 357689
wst04-VHDL20_DWHG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:27 356730
wst04-VHDL20_DWHG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:22 354049
wst04-VHDL20_DWHG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:17 354062
wst04-VHDL20_DWHG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:11 354118
wst04-VHDL20_DWHG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:22 362723
wst04-VHDL20_DWHG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 360336
wst04-VHDL20_DWHG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 359687
wst04-VHDL20_DWHG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 359933
wst04-VHDL20_DWHH_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:21 337017
wst04-VHDL20_DWHH_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:22 335586
wst04-VHDL20_DWHH_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:13 335197
wst04-VHDL20_DWHH_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:11 335290
wst04-VHDL20_DWHH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:26 342789
wst04-VHDL20_DWHH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 342313
wst04-VHDL20_DWHH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:17 341715
wst04-VHDL20_DWHH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 341468
wst04-VHDL20_DWLG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:31 346050
wst04-VHDL20_DWLG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:22 344818
wst04-VHDL20_DWLG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:22 345331
wst04-VHDL20_DWLG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:41 345312
wst04-VHDL20_DWLG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 343454
wst04-VHDL20_DWLG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 343725
wst04-VHDL20_DWLG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 343715
wst04-VHDL20_DWLG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 343606
wst04-VHDL20_DWLH_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:31 344066
wst04-VHDL20_DWLH_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:26 342542
wst04-VHDL20_DWLH_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:26 343166
wst04-VHDL20_DWLH_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:41 344180
wst04-VHDL20_DWLH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 346845
wst04-VHDL20_DWLH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:25 345679
wst04-VHDL20_DWLH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 345560
wst04-VHDL20_DWLH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 345973
wst04-VHDL20_DWLI_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:31 348368
wst04-VHDL20_DWLI_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:22 347383
wst04-VHDL20_DWLI_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:26 347530
wst04-VHDL20_DWLI_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:41 347062
wst04-VHDL20_DWLI_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 350246
wst04-VHDL20_DWLI_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 348956
wst04-VHDL20_DWLI_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 348976
wst04-VHDL20_DWLI_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 349147
wst04-VHDL20_DWMG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:21 572375
wst04-VHDL20_DWMG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:16 570916
wst04-VHDL20_DWMG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:11 571381
wst04-VHDL20_DWMG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:26 571166
wst04-VHDL20_DWMG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:28 567123
wst04-VHDL20_DWMG_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:36:32 567123
wst04-VHDL20_DWMG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 565205
wst04-VHDL20_DWMG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:17 566325
wst04-VHDL20_DWMG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 566048
wst04-VHDL20_DWMO_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:21 467818
wst04-VHDL20_DWMO_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:16 466745
wst04-VHDL20_DWMO_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:11 467142
wst04-VHDL20_DWMO_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:22 467452
wst04-VHDL20_DWMO_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:22 463482
wst04-VHDL20_DWMO_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 462449
wst04-VHDL20_DWMO_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 463827
wst04-VHDL20_DWMO_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:11 464361
wst04-VHDL20_DWMP_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:27 574408
wst04-VHDL20_DWMP_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:16 573329
wst04-VHDL20_DWMP_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:17 572865
wst04-VHDL20_DWMP_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:26 573897
wst04-VHDL20_DWMP_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:28 565667
wst04-VHDL20_DWMP_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 564506
wst04-VHDL20_DWMP_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 564188
wst04-VHDL20_DWMP_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 565258
wst04-VHDL20_DWPG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:31 400796
wst04-VHDL20_DWPG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:26 355274
wst04-VHDL20_DWPG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:26 355054
wst04-VHDL20_DWPG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:31 354799
wst04-VHDL20_DWPG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 398505
wst04-VHDL20_DWPG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:25 353541
wst04-VHDL20_DWPG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 353093
wst04-VHDL20_DWPG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 353564
wst04-VHDL20_DWPH_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:27 290126
wst04-VHDL20_DWPH_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:22 289661
wst04-VHDL20_DWPH_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:22 244835
wst04-VHDL20_DWPH_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:00:31 245419
wst04-VHDL20_DWPH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:26 296035
wst04-VHDL20_DWPH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 295384
wst04-VHDL20_DWPH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 250352
wst04-VHDL20_DWPH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 250897
wst04-VHDL20_DWSG_120800-2603120800-omedes--0.pdf 12-Mar-2026 09:45:13 353240
wst04-VHDL20_DWSG_121300-2603121300-omedes--0.pdf 12-Mar-2026 14:45:11 353583
wst04-VHDL20_DWSG_121800-2603121800-omedes--0.pdf 12-Mar-2026 19:45:12 353105
wst04-VHDL20_DWSG_130200-2603130200-omedes--0.pdf 13-Mar-2026 03:45:17 353220
wst04-VHDL20_DWSG_130400-2603130400-omedes--0.pdf 13-Mar-2026 06:15:16 353538
wst04-VHDL20_DWSG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 361042
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