Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_070600 07-Apr-2026 12:48:09 3712
FPDL13_DWMZ_080600 08-Apr-2026 11:33:02 2521
SXDL31_DWAV_070800 07-Apr-2026 07:18:29 9040
SXDL31_DWAV_071800 07-Apr-2026 16:54:49 3889
SXDL31_DWAV_080800 08-Apr-2026 08:07:29 12964
SXDL31_DWAV_081800 08-Apr-2026 16:36:17 6402
SXDL31_DWAV_LATEST 08-Apr-2026 16:36:17 6402
SXDL33_DWAV_070000 07-Apr-2026 10:06:26 6440
SXDL33_DWAV_080000 08-Apr-2026 09:23:29 9141
SXDL33_DWAV_LATEST 08-Apr-2026 09:23:29 9141
ber01-FWDL39_DWMS_071230-2604071230-dsw--0-ia5 07-Apr-2026 12:08:07 1768
ber01-FWDL39_DWMS_081230-2604081230-dsw--0-ia5 08-Apr-2026 11:39:02 1545
ber01-VHDL13_DWEH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:17 2275
ber01-VHDL13_DWEH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:28:17 2135
ber01-VHDL13_DWEH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:28:11 2288
ber01-VHDL13_DWEH_080400-2604080400-dsw--0-ia5 08-Apr-2026 04:58:16 2233
ber01-VHDL13_DWEH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:28:11 2595
ber01-VHDL13_DWEH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:28:13 2745
ber01-VHDL13_DWEH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:28:11 3000
ber01-VHDL13_DWEH_090400-2604090400-dsw--0-ia5 09-Apr-2026 04:58:17 3049
ber01-VHDL13_DWHG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2358
ber01-VHDL13_DWHG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 2173
ber01-VHDL13_DWHG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:09 2385
ber01-VHDL13_DWHG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2385
ber01-VHDL13_DWHG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:08 3488
ber01-VHDL13_DWHG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:08 3531
ber01-VHDL13_DWHG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 4069
ber01-VHDL13_DWHG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:17 4069
ber01-VHDL13_DWHH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2445
ber01-VHDL13_DWHH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 2235
ber01-VHDL13_DWHH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:09 2529
ber01-VHDL13_DWHH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2529
ber01-VHDL13_DWHH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:08 3403
ber01-VHDL13_DWHH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:08 3140
ber01-VHDL13_DWHH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 3717
ber01-VHDL13_DWHH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:17 3717
ber01-VHDL13_DWLG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2182
ber01-VHDL13_DWLG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 2151
ber01-VHDL13_DWLG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2575
ber01-VHDL13_DWLG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2628
ber01-VHDL13_DWLG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2512
ber01-VHDL13_DWLG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2249
ber01-VHDL13_DWLG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 2418
ber01-VHDL13_DWLG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2522
ber01-VHDL13_DWLH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2017
ber01-VHDL13_DWLH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 1936
ber01-VHDL13_DWLH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2365
ber01-VHDL13_DWLH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2392
ber01-VHDL13_DWLH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2481
ber01-VHDL13_DWLH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2249
ber01-VHDL13_DWLH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 2441
ber01-VHDL13_DWLH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2442
ber01-VHDL13_DWLI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 1902
ber01-VHDL13_DWLI_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 1883
ber01-VHDL13_DWLI_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2197
ber01-VHDL13_DWLI_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2285
ber01-VHDL13_DWLI_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2279
ber01-VHDL13_DWLI_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2076
ber01-VHDL13_DWLI_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 2189
ber01-VHDL13_DWLI_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2256
ber01-VHDL13_DWMG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2159
ber01-VHDL13_DWMG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:01 1938
ber01-VHDL13_DWMG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:05 2298
ber01-VHDL13_DWMG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2247
ber01-VHDL13_DWMG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:08 2390
ber01-VHDL13_DWMG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2150
ber01-VHDL13_DWMG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:03 2628
ber01-VHDL13_DWMG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2640
ber01-VHDL13_DWMO_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2381
ber01-VHDL13_DWMO_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:01 2058
ber01-VHDL13_DWMO_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:05 2363
ber01-VHDL13_DWMO_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2288
ber01-VHDL13_DWMO_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:08 2459
ber01-VHDL13_DWMO_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2160
ber01-VHDL13_DWMO_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:03 2504
ber01-VHDL13_DWMO_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2491
ber01-VHDL13_DWMP_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2329
ber01-VHDL13_DWMP_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:01 2065
ber01-VHDL13_DWMP_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:05 2490
ber01-VHDL13_DWMP_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2474
ber01-VHDL13_DWMP_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:08 2650
ber01-VHDL13_DWMP_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2308
ber01-VHDL13_DWMP_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:03 2700
ber01-VHDL13_DWMP_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2676
ber01-VHDL13_DWOG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 3308
ber01-VHDL13_DWOG_071700-2604071700-dsw--0-ia5 07-Apr-2026 18:00:03 3117
ber01-VHDL13_DWOG_080300-2604080300-dsw--0-ia5 08-Apr-2026 03:00:07 3586
ber01-VHDL13_DWOG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 3616
ber01-VHDL13_DWOG_081700-2604081700-dsw--0-ia5 08-Apr-2026 18:00:03 4487
ber01-VHDL13_DWOG_090300-2604090300-dsw--0-ia5 09-Apr-2026 03:00:07 5156
ber01-VHDL13_DWOH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:17 2254
ber01-VHDL13_DWOH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:28:11 2104
ber01-VHDL13_DWOH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:28:11 2300
ber01-VHDL13_DWOH_080400-2604080400-dsw--0-ia5 08-Apr-2026 04:58:11 2349
ber01-VHDL13_DWOH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:28:17 2732
ber01-VHDL13_DWOH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:28:13 2550
ber01-VHDL13_DWOH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:28:17 2660
ber01-VHDL13_DWOH_090400-2604090400-dsw--0-ia5 09-Apr-2026 04:58:11 2984
ber01-VHDL13_DWOI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:11 2196
ber01-VHDL13_DWOI_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:28:17 2079
ber01-VHDL13_DWOI_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:28:11 2161
ber01-VHDL13_DWOI_080400-2604080400-dsw--0-ia5 08-Apr-2026 04:58:16 2101
ber01-VHDL13_DWOI_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:28:17 2552
ber01-VHDL13_DWOI_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:28:17 2459
ber01-VHDL13_DWOI_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:28:11 2615
ber01-VHDL13_DWOI_090400-2604090400-dsw--0-ia5 09-Apr-2026 04:58:17 2962
ber01-VHDL13_DWON_070605-2604070605-dsw--0-ia5 07-Apr-2026 06:05:52 3672
ber01-VHDL13_DWON_070821-2604070821-dsw--0-ia5 07-Apr-2026 08:21:22 3672
ber01-VHDL13_DWON_071440-2604071440-dsw--0-ia5 07-Apr-2026 14:40:06 3504
ber01-VHDL13_DWON_071459-2604071459-dsw--0-ia5 07-Apr-2026 14:59:11 3200
ber01-VHDL13_DWON_071757-2604071757-dsw--0-ia5 07-Apr-2026 17:57:12 3223
ber01-VHDL13_DWON_071813-2604071813-dsw--0-ia5 07-Apr-2026 18:13:12 3203
ber01-VHDL13_DWON_071940-2604071940-dsw--0-ia5 07-Apr-2026 19:40:22 3200
ber01-VHDL13_DWON_072130-2604072130-dsw--0-ia5 07-Apr-2026 21:30:10 3253
ber01-VHDL13_DWON_080006-2604080006-dsw--0-ia5 08-Apr-2026 00:06:37 3804
ber01-VHDL13_DWON_080134-2604080134-dsw--0-ia5 08-Apr-2026 01:35:04 3734
ber01-VHDL13_DWON_080246-2604080246-dsw--0-ia5 08-Apr-2026 02:46:17 3734
ber01-VHDL13_DWON_080510-2604080510-dsw--0-ia5 08-Apr-2026 05:10:36 4239
ber01-VHDL13_DWON_080612-2604080612-dsw--0-ia5 08-Apr-2026 06:12:22 4206
ber01-VHDL13_DWON_080810-2604080810-dsw--0-ia5 08-Apr-2026 08:10:36 4206
ber01-VHDL13_DWON_080934-2604080934-dsw--0-ia5 08-Apr-2026 09:34:32 4206
ber01-VHDL13_DWON_081411-2604081411-dsw--0-ia5 08-Apr-2026 14:11:47 4103
ber01-VHDL13_DWON_081450-2604081450-dsw--0-ia5 08-Apr-2026 14:50:49 4103
ber01-VHDL13_DWON_081638-2604081638-dsw--0-ia5 08-Apr-2026 16:38:56 4103
ber01-VHDL13_DWON_081838-2604081838-dsw--0-ia5 08-Apr-2026 18:38:27 4168
ber01-VHDL13_DWON_081855-2604081855-dsw--0-ia5 08-Apr-2026 18:55:16 4118
ber01-VHDL13_DWON_082131-2604082131-dsw--0-ia5 08-Apr-2026 21:31:31 4112
ber01-VHDL13_DWON_090002-2604090002-dsw--0-ia5 09-Apr-2026 00:02:58 4758
ber01-VHDL13_DWON_090135-2604090135-dsw--0-ia5 09-Apr-2026 01:35:41 4693
ber01-VHDL13_DWON_090247-2604090247-dsw--0-ia5 09-Apr-2026 02:48:02 4703
ber01-VHDL13_DWON_090350-2604090350-dsw--0-ia5 09-Apr-2026 03:50:28 4703
ber01-VHDL13_DWON_090508-2604090508-dsw--0-ia5 09-Apr-2026 05:08:27 4071
ber01-VHDL13_DWON_090526-2604090526-dsw--0-ia5 09-Apr-2026 05:27:15 4088
ber01-VHDL13_DWPG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 1971
ber01-VHDL13_DWPG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 2064
ber01-VHDL13_DWPG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2575
ber01-VHDL13_DWPG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2533
ber01-VHDL13_DWPG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2468
ber01-VHDL13_DWPG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2175
ber01-VHDL13_DWPG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 2690
ber01-VHDL13_DWPG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2459
ber01-VHDL13_DWPH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2153
ber01-VHDL13_DWPH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:05 2376
ber01-VHDL13_DWPH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2804
ber01-VHDL13_DWPH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:06 2912
ber01-VHDL13_DWPH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2863
ber01-VHDL13_DWPH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2525
ber01-VHDL13_DWPH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:08 3037
ber01-VHDL13_DWPH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:01 2940
ber01-VHDL13_DWSG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2025
ber01-VHDL13_DWSG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:30:01 2077
ber01-VHDL13_DWSG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:30:01 2448
ber01-VHDL13_DWSG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:16 2443
ber01-VHDL13_DWSG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:30:03 2420
ber01-VHDL13_DWSG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:30:03 2249
ber01-VHDL13_DWSG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:30:03 2698
ber01-VHDL13_DWSG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:17 2698
ber01-VHDL13_DWSG_090400_COR-2604090400-dsw--0-ia5 09-Apr-2026 05:27:15 2649
ber01-VHDL17_DWOG_071200-2604071200-dsw--0-ia5 07-Apr-2026 11:30:07 2876
ber01-VHDL17_DWOG_081200-2604081200-dsw--0-ia5 08-Apr-2026 10:49:08 3599
swis2-VHDL20_DWEG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2733
swis2-VHDL20_DWEG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2428
swis2-VHDL20_DWEG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:01 2577
swis2-VHDL20_DWEG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:06 2672
swis2-VHDL20_DWEG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3213
swis2-VHDL20_DWEG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:06 2879
swis2-VHDL20_DWEG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:06 2942
swis2-VHDL20_DWEG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:06 3304
swis2-VHDL20_DWEH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2779
swis2-VHDL20_DWEH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2488
swis2-VHDL20_DWEH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:01 2610
swis2-VHDL20_DWEH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:06 2568
swis2-VHDL20_DWEH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3101
swis2-VHDL20_DWEH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:06 3105
swis2-VHDL20_DWEH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:06 3327
swis2-VHDL20_DWEH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:06 3381
swis2-VHDL20_DWEI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2722
swis2-VHDL20_DWEI_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2428
swis2-VHDL20_DWEI_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:01 2453
swis2-VHDL20_DWEI_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:06 2455
swis2-VHDL20_DWEI_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3080
swis2-VHDL20_DWEI_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:06 2813
swis2-VHDL20_DWEI_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:06 2910
swis2-VHDL20_DWEI_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:06 3313
swis2-VHDL20_DWHG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:06 2890
swis2-VHDL20_DWHG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2356
swis2-VHDL20_DWHG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:01 2571
swis2-VHDL20_DWHG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2568
swis2-VHDL20_DWHG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:10 4102
swis2-VHDL20_DWHG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 3714
swis2-VHDL20_DWHG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 4255
swis2-VHDL20_DWHG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:17 4252
swis2-VHDL20_DWHH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:06 2986
swis2-VHDL20_DWHH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2421
swis2-VHDL20_DWHH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:01 2715
swis2-VHDL20_DWHH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:16 2715
swis2-VHDL20_DWHH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:10 4043
swis2-VHDL20_DWHH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 3326
swis2-VHDL20_DWHH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3903
swis2-VHDL20_DWHH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:17 3903
swis2-VHDL20_DWLG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2674
swis2-VHDL20_DWLG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2494
swis2-VHDL20_DWLG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2918
swis2-VHDL20_DWLG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2973
swis2-VHDL20_DWLG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3002
swis2-VHDL20_DWLG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2594
swis2-VHDL20_DWLG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 2763
swis2-VHDL20_DWLG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:11 2863
swis2-VHDL20_DWLH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2519
swis2-VHDL20_DWLH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2285
swis2-VHDL20_DWLH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2714
swis2-VHDL20_DWLH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2744
swis2-VHDL20_DWLH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3148
swis2-VHDL20_DWLH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2601
swis2-VHDL20_DWLH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 2793
swis2-VHDL20_DWLH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:11 2929
swis2-VHDL20_DWLI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2395
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swis2-VHDL20_DWLI_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2542
swis2-VHDL20_DWLI_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2632
swis2-VHDL20_DWLI_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 2770
swis2-VHDL20_DWLI_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2423
swis2-VHDL20_DWLI_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 2536
swis2-VHDL20_DWLI_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:11 2599
swis2-VHDL20_DWMG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2688
swis2-VHDL20_DWMG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2308
swis2-VHDL20_DWMG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2666
swis2-VHDL20_DWMG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:02 2619
swis2-VHDL20_DWMG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:10 2918
swis2-VHDL20_DWMG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2522
swis2-VHDL20_DWMG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3001
swis2-VHDL20_DWMG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:02 3009
swis2-VHDL20_DWMO_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2921
swis2-VHDL20_DWMO_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2432
swis2-VHDL20_DWMO_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2737
swis2-VHDL20_DWMO_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:02 2667
swis2-VHDL20_DWMO_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:10 2998
swis2-VHDL20_DWMO_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2539
swis2-VHDL20_DWMO_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 2883
swis2-VHDL20_DWMO_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:02 2864
swis2-VHDL20_DWMP_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2867
swis2-VHDL20_DWMP_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2433
swis2-VHDL20_DWMP_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:21 2863
swis2-VHDL20_DWMP_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:02 2849
swis2-VHDL20_DWMP_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:10 3187
swis2-VHDL20_DWMP_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2671
swis2-VHDL20_DWMP_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3078
swis2-VHDL20_DWMP_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:02 3045
swis2-VHDL20_DWPG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2434
swis2-VHDL20_DWPG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2527
swis2-VHDL20_DWPG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 2908
swis2-VHDL20_DWPG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 2862
swis2-VHDL20_DWPG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3013
swis2-VHDL20_DWPG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2720
swis2-VHDL20_DWPG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3022
swis2-VHDL20_DWPG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:11 2786
swis2-VHDL20_DWPH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2616
swis2-VHDL20_DWPH_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2839
swis2-VHDL20_DWPH_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:20 3136
swis2-VHDL20_DWPH_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:00:12 3243
swis2-VHDL20_DWPH_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 3368
swis2-VHDL20_DWPH_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 3030
swis2-VHDL20_DWPH_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3369
swis2-VHDL20_DWPH_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:00:11 3316
swis2-VHDL20_DWSG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:06 2527
swis2-VHDL20_DWSG_071300-2604071300-dsw--0-ia5 07-Apr-2026 13:45:04 2696
swis2-VHDL20_DWSG_071800-2604071800-dsw--0-ia5 07-Apr-2026 18:45:02 2433
swis2-VHDL20_DWSG_080200-2604080200-dsw--0-ia5 08-Apr-2026 02:45:21 2794
swis2-VHDL20_DWSG_080400-2604080400-dsw--0-ia5 08-Apr-2026 05:15:02 2774
swis2-VHDL20_DWSG_080800-2604080800-dsw--0-ia5 08-Apr-2026 08:45:02 2921
swis2-VHDL20_DWSG_081300-2604081300-dsw--0-ia5 08-Apr-2026 13:45:01 2804
swis2-VHDL20_DWSG_081800-2604081800-dsw--0-ia5 08-Apr-2026 18:45:02 2607
swis2-VHDL20_DWSG_090200-2604090200-dsw--0-ia5 09-Apr-2026 02:45:02 3044
swis2-VHDL20_DWSG_090400-2604090400-dsw--0-ia5 09-Apr-2026 05:15:02 3051
swis2-VHDL20_DWSG_090400_COR-2604090400-dsw--0-ia5 09-Apr-2026 05:27:19 3002
wst04-VHDL20_DWEG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:16 246122
wst04-VHDL20_DWEG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:12 244728
wst04-VHDL20_DWEG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 245370
wst04-VHDL20_DWEG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:12 245007
wst04-VHDL20_DWEG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 246988
wst04-VHDL20_DWEG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:12 243559
wst04-VHDL20_DWEG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:16 244779
wst04-VHDL20_DWEG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:16 245341
wst04-VHDL20_DWEH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 242680
wst04-VHDL20_DWEH_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:12 241905
wst04-VHDL20_DWEH_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:21 242862
wst04-VHDL20_DWEH_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:12 242373
wst04-VHDL20_DWEH_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 244162
wst04-VHDL20_DWEH_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:12 244779
wst04-VHDL20_DWEH_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:16 246737
wst04-VHDL20_DWEH_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:16 246278
wst04-VHDL20_DWEI_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 349089
wst04-VHDL20_DWEI_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:12 350648
wst04-VHDL20_DWEI_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:21 350762
wst04-VHDL20_DWEI_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:16 351096
wst04-VHDL20_DWEI_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 352566
wst04-VHDL20_DWEI_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:12 350393
wst04-VHDL20_DWEI_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:16 351197
wst04-VHDL20_DWEI_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:22 351493
wst04-VHDL20_DWHG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 356730
wst04-VHDL20_DWHG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:22 351283
wst04-VHDL20_DWHG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 351068
wst04-VHDL20_DWHG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:12 351147
wst04-VHDL20_DWHG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 354472
wst04-VHDL20_DWHG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:22 348056
wst04-VHDL20_DWHG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:23 348536
wst04-VHDL20_DWHG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:11 348559
wst04-VHDL20_DWHH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:16 322812
wst04-VHDL20_DWHH_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:22 325845
wst04-VHDL20_DWHH_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:21 325746
wst04-VHDL20_DWHH_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:12 325832
wst04-VHDL20_DWHH_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 327358
wst04-VHDL20_DWHH_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:22 325787
wst04-VHDL20_DWHH_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:23 326684
wst04-VHDL20_DWHH_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:11 326761
wst04-VHDL20_DWLG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 329178
wst04-VHDL20_DWLG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:22 333831
wst04-VHDL20_DWLG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:31 334716
wst04-VHDL20_DWLG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:42 334154
wst04-VHDL20_DWLG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:26 334684
wst04-VHDL20_DWLG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:26 332323
wst04-VHDL20_DWLG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:27 333038
wst04-VHDL20_DWLG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:41 332850
wst04-VHDL20_DWLH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 332302
wst04-VHDL20_DWLH_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:26 338935
wst04-VHDL20_DWLH_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:31 340080
wst04-VHDL20_DWLH_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:42 339404
wst04-VHDL20_DWLH_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:26 339780
wst04-VHDL20_DWLH_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:22 339959
wst04-VHDL20_DWLH_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:27 341069
wst04-VHDL20_DWLH_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:41 340898
wst04-VHDL20_DWLI_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:36 334428
wst04-VHDL20_DWLI_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:22 338912
wst04-VHDL20_DWLI_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:21 339963
wst04-VHDL20_DWLI_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:42 339342
wst04-VHDL20_DWLI_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:26 339588
wst04-VHDL20_DWLI_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:26 341969
wst04-VHDL20_DWLI_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:23 342991
wst04-VHDL20_DWLI_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:41 342497
wst04-VHDL20_DWMG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:16 559955
wst04-VHDL20_DWMG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:16 553957
wst04-VHDL20_DWMG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 555077
wst04-VHDL20_DWMG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:16 554729
wst04-VHDL20_DWMG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:24 555135
wst04-VHDL20_DWMG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:16 564324
wst04-VHDL20_DWMG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:12 565401
wst04-VHDL20_DWMG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:18 565511
wst04-VHDL20_DWMO_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 451037
wst04-VHDL20_DWMO_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:16 452364
wst04-VHDL20_DWMO_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 452869
wst04-VHDL20_DWMO_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:16 454045
wst04-VHDL20_DWMO_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:24 454240
wst04-VHDL20_DWMO_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:16 455125
wst04-VHDL20_DWMO_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:12 456311
wst04-VHDL20_DWMO_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:12 456888
wst04-VHDL20_DWMP_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 572410
wst04-VHDL20_DWMP_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:16 556404
wst04-VHDL20_DWMP_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 556623
wst04-VHDL20_DWMP_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:16 556772
wst04-VHDL20_DWMP_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:24 557994
wst04-VHDL20_DWMP_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:16 572218
wst04-VHDL20_DWMP_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:12 572273
wst04-VHDL20_DWMP_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:18 573017
wst04-VHDL20_DWPG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:36 385616
wst04-VHDL20_DWPG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:26 342385
wst04-VHDL20_DWPG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:31 342410
wst04-VHDL20_DWPG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:32 342164
wst04-VHDL20_DWPG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:32 387139
wst04-VHDL20_DWPG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:22 337628
wst04-VHDL20_DWPG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:27 338094
wst04-VHDL20_DWPG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:31 338168
wst04-VHDL20_DWPH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 283826
wst04-VHDL20_DWPH_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:22 286789
wst04-VHDL20_DWPH_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 242466
wst04-VHDL20_DWPH_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:00:32 242415
wst04-VHDL20_DWPH_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:26 287526
wst04-VHDL20_DWPH_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:22 285744
wst04-VHDL20_DWPH_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:23 241564
wst04-VHDL20_DWPH_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:00:31 241578
wst04-VHDL20_DWSG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 353530
wst04-VHDL20_DWSG_071300-2604071300-omedes--0.pdf 07-Apr-2026 13:45:12 347176
wst04-VHDL20_DWSG_071800-2604071800-omedes--0.pdf 07-Apr-2026 18:45:12 346485
wst04-VHDL20_DWSG_080200-2604080200-omedes--0.pdf 08-Apr-2026 02:45:20 346642
wst04-VHDL20_DWSG_080400-2604080400-omedes--0.pdf 08-Apr-2026 05:15:12 346402
wst04-VHDL20_DWSG_080800-2604080800-omedes--0.pdf 08-Apr-2026 08:45:19 346330
wst04-VHDL20_DWSG_081300-2604081300-omedes--0.pdf 08-Apr-2026 13:45:11 352198
wst04-VHDL20_DWSG_081800-2604081800-omedes--0.pdf 08-Apr-2026 18:45:12 351550
wst04-VHDL20_DWSG_090200-2604090200-omedes--0.pdf 09-Apr-2026 02:45:16 352388
wst04-VHDL20_DWSG_090400-2604090400-omedes--0.pdf 09-Apr-2026 05:15:12 352517
wst04-VHDL20_DWSG_090400_COR-2604090400-omedes-..> 09-Apr-2026 05:27:19 352316