Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_080600 08-Mar-2026 12:32:14 4082
FPDL13_DWMZ_090600 09-Mar-2026 13:35:39 4665
SXDL31_DWAV_080800 08-Mar-2026 08:52:18 7051
SXDL31_DWAV_081800 08-Mar-2026 17:20:40 8678
SXDL31_DWAV_090800 09-Mar-2026 08:51:43 11967
SXDL31_DWAV_091800 09-Mar-2026 17:08:04 11295
SXDL31_DWAV_LATEST 09-Mar-2026 17:08:04 11295
SXDL33_DWAV_080000 08-Mar-2026 10:43:59 14373
SXDL33_DWAV_090000 09-Mar-2026 10:38:49 6193
SXDL33_DWAV_LATEST 09-Mar-2026 10:38:49 6193
ber01-FWDL39_DWMS_081230-2603081230-dsw--0-ia5 08-Mar-2026 12:04:27 891
ber01-FWDL39_DWMS_081230_COR-2603081230-dsw--0-ia5 08-Mar-2026 12:49:57 891
ber01-FWDL39_DWMS_091230-2603091230-dsw--0-ia5 09-Mar-2026 13:15:01 1959
ber01-VHDL13_DWEH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:12 2845
ber01-VHDL13_DWEH_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2765
ber01-VHDL13_DWEH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:17 2667
ber01-VHDL13_DWEH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:28:15 2648
ber01-VHDL13_DWEH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:28:16 2987
ber01-VHDL13_DWEH_090400-2603090400-dsw--0-ia5 09-Mar-2026 05:58:11 2970
ber01-VHDL13_DWEH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:28:16 3061
ber01-VHDL13_DWEH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:28:16 2726
ber01-VHDL13_DWHG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:14 2814
ber01-VHDL13_DWHG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2794
ber01-VHDL13_DWHG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3446
ber01-VHDL13_DWHG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:08 2883
ber01-VHDL13_DWHG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2709
ber01-VHDL13_DWHG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2682
ber01-VHDL13_DWHG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:07 2939
ber01-VHDL13_DWHG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2713
ber01-VHDL13_DWHH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:14 2415
ber01-VHDL13_DWHH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2403
ber01-VHDL13_DWHH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3459
ber01-VHDL13_DWHH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:08 2616
ber01-VHDL13_DWHH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2425
ber01-VHDL13_DWHH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2424
ber01-VHDL13_DWHH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:07 2739
ber01-VHDL13_DWHH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2654
ber01-VHDL13_DWLG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2435
ber01-VHDL13_DWLG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 2382
ber01-VHDL13_DWLG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2528
ber01-VHDL13_DWLG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 2386
ber01-VHDL13_DWLG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2689
ber01-VHDL13_DWLG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:02 2630
ber01-VHDL13_DWLG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2541
ber01-VHDL13_DWLG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2093
ber01-VHDL13_DWLH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2216
ber01-VHDL13_DWLH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2150
ber01-VHDL13_DWLH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2026
ber01-VHDL13_DWLH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 1866
ber01-VHDL13_DWLH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2350
ber01-VHDL13_DWLH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:02 2466
ber01-VHDL13_DWLH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 3110
ber01-VHDL13_DWLH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2916
ber01-VHDL13_DWLI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:02 2223
ber01-VHDL13_DWLI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2236
ber01-VHDL13_DWLI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2132
ber01-VHDL13_DWLI_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 1947
ber01-VHDL13_DWLI_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2307
ber01-VHDL13_DWLI_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:02 2343
ber01-VHDL13_DWLI_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2910
ber01-VHDL13_DWLI_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2630
ber01-VHDL13_DWMG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 1864
ber01-VHDL13_DWMG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 1869
ber01-VHDL13_DWMG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1706
ber01-VHDL13_DWMG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:08 1710
ber01-VHDL13_DWMG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2132
ber01-VHDL13_DWMG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2140
ber01-VHDL13_DWMG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2803
ber01-VHDL13_DWMG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:02 2488
ber01-VHDL13_DWMO_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2088
ber01-VHDL13_DWMO_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 2096
ber01-VHDL13_DWMO_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1925
ber01-VHDL13_DWMO_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:08 1800
ber01-VHDL13_DWMO_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2182
ber01-VHDL13_DWMO_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2200
ber01-VHDL13_DWMO_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2827
ber01-VHDL13_DWMO_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:02 2553
ber01-VHDL13_DWMP_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:02 2032
ber01-VHDL13_DWMP_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 2046
ber01-VHDL13_DWMP_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1921
ber01-VHDL13_DWMP_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:08 1855
ber01-VHDL13_DWMP_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2265
ber01-VHDL13_DWMP_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2314
ber01-VHDL13_DWMP_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2669
ber01-VHDL13_DWMP_090800_COR-2603090800-dsw--0-ia5 09-Mar-2026 13:51:07 2673
ber01-VHDL13_DWMP_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:02 2356
ber01-VHDL13_DWOG_080300-2603080300-dsw--0-ia5 08-Mar-2026 04:00:07 3100
ber01-VHDL13_DWOG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3375
ber01-VHDL13_DWOG_081700-2603081700-dsw--0-ia5 08-Mar-2026 19:00:07 3247
ber01-VHDL13_DWOG_090300-2603090300-dsw--0-ia5 09-Mar-2026 04:15:36 4059
ber01-VHDL13_DWOG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:07 4450
ber01-VHDL13_DWOG_091700-2603091700-dsw--0-ia5 09-Mar-2026 19:00:02 4118
ber01-VHDL13_DWOH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:12 2682
ber01-VHDL13_DWOH_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2671
ber01-VHDL13_DWOH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:17 2646
ber01-VHDL13_DWOH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:28:15 2609
ber01-VHDL13_DWOH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:28:12 2792
ber01-VHDL13_DWOH_090400-2603090400-dsw--0-ia5 09-Mar-2026 05:58:17 3026
ber01-VHDL13_DWOH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:28:16 3263
ber01-VHDL13_DWOH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:28:16 2855
ber01-VHDL13_DWOI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:16 2591
ber01-VHDL13_DWOI_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2503
ber01-VHDL13_DWOI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:13 2483
ber01-VHDL13_DWOI_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:28:11 2531
ber01-VHDL13_DWOI_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:28:16 2774
ber01-VHDL13_DWOI_090400-2603090400-dsw--0-ia5 09-Mar-2026 05:58:17 2924
ber01-VHDL13_DWOI_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:28:12 3065
ber01-VHDL13_DWOI_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:28:16 2657
ber01-VHDL13_DWON_080119-2603080119-dsw--0-ia5 08-Mar-2026 01:19:52 3342
ber01-VHDL13_DWON_080343-2603080343-dsw--0-ia5 08-Mar-2026 03:43:07 3342
ber01-VHDL13_DWON_080614-2603080614-dsw--0-ia5 08-Mar-2026 06:14:36 3491
ber01-VHDL13_DWON_080927-2603080927-dsw--0-ia5 08-Mar-2026 09:27:22 3390
ber01-VHDL13_DWON_080946-2603080946-dsw--0-ia5 08-Mar-2026 09:46:21 3599
ber01-VHDL13_DWON_081353-2603081353-dsw--0-ia5 08-Mar-2026 13:53:27 2905
ber01-VHDL13_DWON_081734-2603081734-dsw--0-ia5 08-Mar-2026 17:34:40 3035
ber01-VHDL13_DWON_081829-2603081829-dsw--0-ia5 08-Mar-2026 18:29:45 3035
ber01-VHDL13_DWON_090205-2603090205-dsw--0-ia5 09-Mar-2026 02:05:36 3366
ber01-VHDL13_DWON_090334-2603090334-dsw--0-ia5 09-Mar-2026 03:34:36 3366
ber01-VHDL13_DWON_090414-2603090414-dsw--0-ia5 09-Mar-2026 04:14:16 3366
ber01-VHDL13_DWON_090625-2603090625-dsw--0-ia5 09-Mar-2026 06:25:17 3927
ber01-VHDL13_DWON_090710-2603090710-dsw--0-ia5 09-Mar-2026 07:10:12 4068
ber01-VHDL13_DWON_090857-2603090857-dsw--0-ia5 09-Mar-2026 08:57:26 4055
ber01-VHDL13_DWON_091556-2603091556-dsw--0-ia5 09-Mar-2026 15:56:07 3587
ber01-VHDL13_DWON_091733-2603091733-dsw--0-ia5 09-Mar-2026 17:33:31 3728
ber01-VHDL13_DWPG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2018
ber01-VHDL13_DWPG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 1942
ber01-VHDL13_DWPG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1937
ber01-VHDL13_DWPG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 1909
ber01-VHDL13_DWPG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2098
ber01-VHDL13_DWPG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:02 2113
ber01-VHDL13_DWPG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2142
ber01-VHDL13_DWPG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 1985
ber01-VHDL13_DWPH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2154
ber01-VHDL13_DWPH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 2196
ber01-VHDL13_DWPH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2205
ber01-VHDL13_DWPH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 2117
ber01-VHDL13_DWPH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 2293
ber01-VHDL13_DWPH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:02 2315
ber01-VHDL13_DWPH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2601
ber01-VHDL13_DWPH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:06 2768
ber01-VHDL13_DWSG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2389
ber01-VHDL13_DWSG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2577
ber01-VHDL13_DWSG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2784
ber01-VHDL13_DWSG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:30:05 2518
ber01-VHDL13_DWSG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:30:09 3068
ber01-VHDL13_DWSG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 3019
ber01-VHDL13_DWSG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:30:01 2688
ber01-VHDL13_DWSG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:30:02 2731
ber01-VHDL17_DWOG_081200-2603081200-dsw--0-ia5 08-Mar-2026 12:11:23 3597
ber01-VHDL17_DWOG_091200-2603091200-dsw--0-ia5 09-Mar-2026 12:28:22 3014
swis2-VHDL20_DWEG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2958
swis2-VHDL20_DWEG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 2990
swis2-VHDL20_DWEG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3124
swis2-VHDL20_DWEG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 2934
swis2-VHDL20_DWEG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 3067
swis2-VHDL20_DWEG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:01 3350
swis2-VHDL20_DWEG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:07 3744
swis2-VHDL20_DWEG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 3183
swis2-VHDL20_DWEH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 3166
swis2-VHDL20_DWEH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 3099
swis2-VHDL20_DWEH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3170
swis2-VHDL20_DWEH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 3000
swis2-VHDL20_DWEH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 3307
swis2-VHDL20_DWEH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:01 3309
swis2-VHDL20_DWEH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:07 3567
swis2-VHDL20_DWEH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 3083
swis2-VHDL20_DWEI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2883
swis2-VHDL20_DWEI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 2853
swis2-VHDL20_DWEI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3008
swis2-VHDL20_DWEI_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 2881
swis2-VHDL20_DWEI_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 3066
swis2-VHDL20_DWEI_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:01 3279
swis2-VHDL20_DWEI_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:07 3593
swis2-VHDL20_DWEI_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 3010
swis2-VHDL20_DWHG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 3000
swis2-VHDL20_DWHG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2977
swis2-VHDL20_DWHG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 4132
swis2-VHDL20_DWHG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 3066
swis2-VHDL20_DWHG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 2895
swis2-VHDL20_DWHG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2865
swis2-VHDL20_DWHG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:07 3641
swis2-VHDL20_DWHG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 2896
swis2-VHDL20_DWHH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2601
swis2-VHDL20_DWHH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2589
swis2-VHDL20_DWHH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 3998
swis2-VHDL20_DWHH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2802
swis2-VHDL20_DWHH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 2611
swis2-VHDL20_DWHH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:06 2610
swis2-VHDL20_DWHH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:07 3345
swis2-VHDL20_DWHH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 2840
swis2-VHDL20_DWLG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2777
swis2-VHDL20_DWLG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2722
swis2-VHDL20_DWLG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 3015
swis2-VHDL20_DWLG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2726
swis2-VHDL20_DWLG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 3029
swis2-VHDL20_DWLG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:12 2973
swis2-VHDL20_DWLG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3030
swis2-VHDL20_DWLG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:06 2436
swis2-VHDL20_DWLH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2565
swis2-VHDL20_DWLH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2497
swis2-VHDL20_DWLH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2523
swis2-VHDL20_DWLH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2213
swis2-VHDL20_DWLH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 2697
swis2-VHDL20_DWLH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:12 2815
swis2-VHDL20_DWLH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3609
swis2-VHDL20_DWLH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:06 3265
swis2-VHDL20_DWLI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2567
swis2-VHDL20_DWLI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2578
swis2-VHDL20_DWLI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2620
swis2-VHDL20_DWLI_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2289
swis2-VHDL20_DWLI_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 2649
swis2-VHDL20_DWLI_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:12 2688
swis2-VHDL20_DWLI_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3400
swis2-VHDL20_DWLI_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:06 2975
swis2-VHDL20_DWMG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2296
swis2-VHDL20_DWMG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2309
swis2-VHDL20_DWMG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2364
swis2-VHDL20_DWMG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 2102
swis2-VHDL20_DWMG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 2550
swis2-VHDL20_DWMG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:06 2514
swis2-VHDL20_DWMG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3337
swis2-VHDL20_DWMG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 2862
swis2-VHDL20_DWMO_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2524
swis2-VHDL20_DWMO_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2531
swis2-VHDL20_DWMO_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2583
swis2-VHDL20_DWMO_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 2196
swis2-VHDL20_DWMO_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 2617
swis2-VHDL20_DWMO_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:06 2578
swis2-VHDL20_DWMO_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3369
swis2-VHDL20_DWMO_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 2931
swis2-VHDL20_DWMP_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2467
swis2-VHDL20_DWMP_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2416
swis2-VHDL20_DWMP_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2515
swis2-VHDL20_DWMP_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:06 2236
swis2-VHDL20_DWMP_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:06 2699
swis2-VHDL20_DWMP_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:06 2688
swis2-VHDL20_DWMP_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3209
swis2-VHDL20_DWMP_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 2744
swis2-VHDL20_DWPG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2347
swis2-VHDL20_DWPG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2267
swis2-VHDL20_DWPG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2394
swis2-VHDL20_DWPG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2368
swis2-VHDL20_DWPG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 2426
swis2-VHDL20_DWPG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:12 2440
swis2-VHDL20_DWPG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 2603
swis2-VHDL20_DWPG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:06 2446
swis2-VHDL20_DWPH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2482
swis2-VHDL20_DWPH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2523
swis2-VHDL20_DWPH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2663
swis2-VHDL20_DWPH_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2576
swis2-VHDL20_DWPH_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 2620
swis2-VHDL20_DWPH_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:00:12 2644
swis2-VHDL20_DWPH_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3062
swis2-VHDL20_DWPH_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:06 3229
swis2-VHDL20_DWSG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2797
swis2-VHDL20_DWSG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2998
swis2-VHDL20_DWSG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3351
swis2-VHDL20_DWSG_081300-2603081300-dsw--0-ia5 08-Mar-2026 14:45:21 3224
swis2-VHDL20_DWSG_081800-2603081800-dsw--0-ia5 08-Mar-2026 19:45:04 2941
swis2-VHDL20_DWSG_090200-2603090200-dsw--0-ia5 09-Mar-2026 03:45:01 3414
swis2-VHDL20_DWSG_090400-2603090400-dsw--0-ia5 09-Mar-2026 06:15:01 3373
swis2-VHDL20_DWSG_090800-2603090800-dsw--0-ia5 09-Mar-2026 09:45:04 3188
swis2-VHDL20_DWSG_091300-2603091300-dsw--0-ia5 09-Mar-2026 14:45:13 3517
swis2-VHDL20_DWSG_091800-2603091800-dsw--0-ia5 09-Mar-2026 19:45:02 3087
wst04-VHDL20_DWEG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 247328
wst04-VHDL20_DWEG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 246376
wst04-VHDL20_DWEG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:22 245762
wst04-VHDL20_DWEG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:12 244710
wst04-VHDL20_DWEG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:22 245956
wst04-VHDL20_DWEG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:16 246662
wst04-VHDL20_DWEG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:11 248357
wst04-VHDL20_DWEG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:12 246013
wst04-VHDL20_DWEH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 246465
wst04-VHDL20_DWEH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 245834
wst04-VHDL20_DWEH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:22 249051
wst04-VHDL20_DWEH_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:12 248338
wst04-VHDL20_DWEH_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:22 250234
wst04-VHDL20_DWEH_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:16 249819
wst04-VHDL20_DWEH_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:11 243562
wst04-VHDL20_DWEH_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:12 241816
wst04-VHDL20_DWEI_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:23 356498
wst04-VHDL20_DWEI_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:22 355993
wst04-VHDL20_DWEI_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:26 350174
wst04-VHDL20_DWEI_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:16 350050
wst04-VHDL20_DWEI_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:22 350652
wst04-VHDL20_DWEI_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:22 351240
wst04-VHDL20_DWEI_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:18 352232
wst04-VHDL20_DWEI_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:16 350990
wst04-VHDL20_DWHG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 354867
wst04-VHDL20_DWHG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:11 354938
wst04-VHDL20_DWHG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 358934
wst04-VHDL20_DWHG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:22 356589
wst04-VHDL20_DWHG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:16 356203
wst04-VHDL20_DWHG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:12 357020
wst04-VHDL20_DWHG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:26 356076
wst04-VHDL20_DWHG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:22 353834
wst04-VHDL20_DWHH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 334853
wst04-VHDL20_DWHH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:11 334923
wst04-VHDL20_DWHH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:22 337233
wst04-VHDL20_DWHH_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:22 335197
wst04-VHDL20_DWHH_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:12 335587
wst04-VHDL20_DWHH_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:12 335760
wst04-VHDL20_DWHH_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:26 336596
wst04-VHDL20_DWHH_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:22 336550
wst04-VHDL20_DWLG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 353741
wst04-VHDL20_DWLG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 353726
wst04-VHDL20_DWLG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:36 342835
wst04-VHDL20_DWLG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:26 342420
wst04-VHDL20_DWLG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:26 343646
wst04-VHDL20_DWLG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:40 343487
wst04-VHDL20_DWLG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:36 332627
wst04-VHDL20_DWLG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:22 332507
wst04-VHDL20_DWLH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 347108
wst04-VHDL20_DWLH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 346988
wst04-VHDL20_DWLH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 339768
wst04-VHDL20_DWLH_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:22 339570
wst04-VHDL20_DWLH_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:26 341019
wst04-VHDL20_DWLH_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:40 341592
wst04-VHDL20_DWLH_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:36 343856
wst04-VHDL20_DWLH_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:26 342713
wst04-VHDL20_DWLI_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 342869
wst04-VHDL20_DWLI_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 342971
wst04-VHDL20_DWLI_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 337596
wst04-VHDL20_DWLI_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:26 337410
wst04-VHDL20_DWLI_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:26 338792
wst04-VHDL20_DWLI_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:40 339328
wst04-VHDL20_DWLI_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:31 339748
wst04-VHDL20_DWLI_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:26 338687
wst04-VHDL20_DWMG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 586556
wst04-VHDL20_DWMG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:26 586445
wst04-VHDL20_DWMG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 557058
wst04-VHDL20_DWMG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:16 556810
wst04-VHDL20_DWMG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:12 557937
wst04-VHDL20_DWMG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:26 557038
wst04-VHDL20_DWMG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:18 554704
wst04-VHDL20_DWMG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:16 553408
wst04-VHDL20_DWMO_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 476048
wst04-VHDL20_DWMO_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 476552
wst04-VHDL20_DWMO_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:12 460122
wst04-VHDL20_DWMO_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:16 458959
wst04-VHDL20_DWMO_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:12 460313
wst04-VHDL20_DWMO_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:26 460804
wst04-VHDL20_DWMO_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:18 456356
wst04-VHDL20_DWMO_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:16 455471
wst04-VHDL20_DWMP_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 571192
wst04-VHDL20_DWMP_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:22 572322
wst04-VHDL20_DWMP_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 555278
wst04-VHDL20_DWMP_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:22 554972
wst04-VHDL20_DWMP_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:16 554304
wst04-VHDL20_DWMP_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:26 555221
wst04-VHDL20_DWMP_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:23 551021
wst04-VHDL20_DWMP_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:16 549692
wst04-VHDL20_DWPG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 358267
wst04-VHDL20_DWPG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:31 358173
wst04-VHDL20_DWPG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 394533
wst04-VHDL20_DWPG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:26 349473
wst04-VHDL20_DWPG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:26 350198
wst04-VHDL20_DWPG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:32 350688
wst04-VHDL20_DWPG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:36 393147
wst04-VHDL20_DWPG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:26 348442
wst04-VHDL20_DWPH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 250145
wst04-VHDL20_DWPH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:31 249877
wst04-VHDL20_DWPH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 294479
wst04-VHDL20_DWPH_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:22 294992
wst04-VHDL20_DWPH_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:20 250734
wst04-VHDL20_DWPH_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:00:32 250608
wst04-VHDL20_DWPH_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:31 291181
wst04-VHDL20_DWPH_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:22 291335
wst04-VHDL20_DWSG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 360370
wst04-VHDL20_DWSG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:12 360855
wst04-VHDL20_DWSG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:12 358109
wst04-VHDL20_DWSG_081300-2603081300-omedes--0.pdf 08-Mar-2026 14:45:21 358063
wst04-VHDL20_DWSG_081800-2603081800-omedes--0.pdf 08-Mar-2026 19:45:12 357826
wst04-VHDL20_DWSG_090200-2603090200-omedes--0.pdf 09-Mar-2026 03:45:16 358350
wst04-VHDL20_DWSG_090400-2603090400-omedes--0.pdf 09-Mar-2026 06:15:16 358524
wst04-VHDL20_DWSG_090800-2603090800-omedes--0.pdf 09-Mar-2026 09:45:11 354845
wst04-VHDL20_DWSG_091300-2603091300-omedes--0.pdf 09-Mar-2026 14:45:13 354661
wst04-VHDL20_DWSG_091800-2603091800-omedes--0.pdf 09-Mar-2026 19:45:12 353700