Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Mar-2026 12:14:09 2545
FPDL13_DWMZ_040600 04-Mar-2026 11:54:24 3254
SXDL31_DWAV_030800 03-Mar-2026 08:30:34 9619
SXDL31_DWAV_031800 03-Mar-2026 17:40:18 3910
SXDL31_DWAV_040800 04-Mar-2026 08:15:23 8954
SXDL31_DWAV_041800 04-Mar-2026 17:35:28 3230
SXDL31_DWAV_LATEST 04-Mar-2026 17:35:28 3230
SXDL33_DWAV_030000 03-Mar-2026 11:18:09 8130
SXDL33_DWAV_040000 04-Mar-2026 10:16:33 7232
SXDL33_DWAV_LATEST 04-Mar-2026 10:16:33 7232
ber01-FWDL39_DWMS_031230-2603031230-dsw--0-ia5 03-Mar-2026 12:39:37 1476
ber01-FWDL39_DWMS_041230-2603041230-dsw--0-ia5 04-Mar-2026 12:03:21 1569
ber01-VHDL13_DWEH_030400-2603030400-dsw--0-ia5 03-Mar-2026 05:58:16 2473
ber01-VHDL13_DWEH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:28:17 2476
ber01-VHDL13_DWEH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:28:17 2416
ber01-VHDL13_DWEH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:28:11 2513
ber01-VHDL13_DWEH_040400-2603040400-dsw--0-ia5 04-Mar-2026 05:58:16 2302
ber01-VHDL13_DWEH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:28:17 2283
ber01-VHDL13_DWEH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:28:17 2137
ber01-VHDL13_DWEH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:28:12 2249
ber01-VHDL13_DWHG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2866
ber01-VHDL13_DWHG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2629
ber01-VHDL13_DWHG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:06 2622
ber01-VHDL13_DWHG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:07 2510
ber01-VHDL13_DWHG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:08 2501
ber01-VHDL13_DWHG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:09 2528
ber01-VHDL13_DWHG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2159
ber01-VHDL13_DWHG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2821
ber01-VHDL13_DWHH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2497
ber01-VHDL13_DWHH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2310
ber01-VHDL13_DWHH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:06 2144
ber01-VHDL13_DWHH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:07 2113
ber01-VHDL13_DWHH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:08 2196
ber01-VHDL13_DWHH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:09 2074
ber01-VHDL13_DWHH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 1907
ber01-VHDL13_DWHH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2482
ber01-VHDL13_DWLG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2065
ber01-VHDL13_DWLG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2140
ber01-VHDL13_DWLG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2195
ber01-VHDL13_DWLG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2298
ber01-VHDL13_DWLG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:00 2264
ber01-VHDL13_DWLG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2142
ber01-VHDL13_DWLG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2087
ber01-VHDL13_DWLG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2194
ber01-VHDL13_DWLH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2163
ber01-VHDL13_DWLH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2307
ber01-VHDL13_DWLH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2356
ber01-VHDL13_DWLH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2311
ber01-VHDL13_DWLH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:00 2131
ber01-VHDL13_DWLH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2174
ber01-VHDL13_DWLH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2062
ber01-VHDL13_DWLH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2027
ber01-VHDL13_DWLI_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 1969
ber01-VHDL13_DWLI_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 1996
ber01-VHDL13_DWLI_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2084
ber01-VHDL13_DWLI_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2202
ber01-VHDL13_DWLI_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:00 2186
ber01-VHDL13_DWLI_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2057
ber01-VHDL13_DWLI_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2242
ber01-VHDL13_DWLI_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2201
ber01-VHDL13_DWMG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:02 2426
ber01-VHDL13_DWMG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2241
ber01-VHDL13_DWMG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 1821
ber01-VHDL13_DWMG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 1887
ber01-VHDL13_DWMG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:02 1913
ber01-VHDL13_DWMG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2036
ber01-VHDL13_DWMG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:02 1928
ber01-VHDL13_DWMG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:05 2001
ber01-VHDL13_DWMO_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:02 2412
ber01-VHDL13_DWMO_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2268
ber01-VHDL13_DWMO_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:06 2017
ber01-VHDL13_DWMO_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2140
ber01-VHDL13_DWMO_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:02 2145
ber01-VHDL13_DWMO_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2266
ber01-VHDL13_DWMO_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:02 2085
ber01-VHDL13_DWMO_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:05 2242
ber01-VHDL13_DWMP_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:02 2704
ber01-VHDL13_DWMP_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2502
ber01-VHDL13_DWMP_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2074
ber01-VHDL13_DWMP_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2222
ber01-VHDL13_DWMP_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:02 2226
ber01-VHDL13_DWMP_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2307
ber01-VHDL13_DWMP_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:02 2040
ber01-VHDL13_DWMP_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:05 2196
ber01-VHDL13_DWOG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 3645
ber01-VHDL13_DWOG_031700-2603031700-dsw--0-ia5 03-Mar-2026 19:00:02 3216
ber01-VHDL13_DWOG_040300-2603040300-dsw--0-ia5 04-Mar-2026 04:00:02 3367
ber01-VHDL13_DWOG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 3255
ber01-VHDL13_DWOG_041700-2603041700-dsw--0-ia5 04-Mar-2026 19:00:07 2798
ber01-VHDL13_DWOG_050300-2603050300-dsw--0-ia5 05-Mar-2026 04:00:02 3386
ber01-VHDL13_DWOH_030400-2603030400-dsw--0-ia5 03-Mar-2026 05:58:16 2442
ber01-VHDL13_DWOH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:28:17 2442
ber01-VHDL13_DWOH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:28:17 2436
ber01-VHDL13_DWOH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:28:11 2469
ber01-VHDL13_DWOH_040400-2603040400-dsw--0-ia5 04-Mar-2026 05:58:12 2222
ber01-VHDL13_DWOH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:28:17 2194
ber01-VHDL13_DWOH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:28:17 2128
ber01-VHDL13_DWOH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:28:17 2220
ber01-VHDL13_DWOI_030400-2603030400-dsw--0-ia5 03-Mar-2026 05:58:16 2302
ber01-VHDL13_DWOI_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:28:11 2308
ber01-VHDL13_DWOI_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:28:11 2300
ber01-VHDL13_DWOI_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:28:17 2423
ber01-VHDL13_DWOI_040400-2603040400-dsw--0-ia5 04-Mar-2026 05:58:16 2190
ber01-VHDL13_DWOI_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:28:11 2170
ber01-VHDL13_DWOI_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:28:12 2139
ber01-VHDL13_DWOI_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:28:12 2251
ber01-VHDL13_DWON_030624-2603030624-dsw--0-ia5 03-Mar-2026 06:24:36 3155
ber01-VHDL13_DWON_030712-2603030712-dsw--0-ia5 03-Mar-2026 07:12:36 3341
ber01-VHDL13_DWON_030859-2603030859-dsw--0-ia5 03-Mar-2026 08:59:51 3341
ber01-VHDL13_DWON_030957-2603030957-dsw--0-ia5 03-Mar-2026 09:57:11 3341
ber01-VHDL13_DWON_031506-2603031506-dsw--0-ia5 03-Mar-2026 15:06:11 2850
ber01-VHDL13_DWON_031747-2603031747-dsw--0-ia5 03-Mar-2026 17:47:37 2722
ber01-VHDL13_DWON_032133-2603032133-dsw--0-ia5 03-Mar-2026 21:33:23 2722
ber01-VHDL13_DWON_032347-2603032347-dsw--0-ia5 03-Mar-2026 23:47:51 2985
ber01-VHDL13_DWON_040116-2603040116-dsw--0-ia5 04-Mar-2026 01:16:11 2985
ber01-VHDL13_DWON_040608-2603040608-dsw--0-ia5 04-Mar-2026 06:08:42 3352
ber01-VHDL13_DWON_040706-2603040706-dsw--0-ia5 04-Mar-2026 07:06:41 3352
ber01-VHDL13_DWON_041401-2603041401-dsw--0-ia5 04-Mar-2026 14:01:22 2695
ber01-VHDL13_DWON_041517-2603041517-dsw--0-ia5 04-Mar-2026 15:17:42 2695
ber01-VHDL13_DWON_041519-2603041519-dsw--0-ia5 04-Mar-2026 15:19:52 2695
ber01-VHDL13_DWON_041742-2603041742-dsw--0-ia5 04-Mar-2026 17:42:37 2573
ber01-VHDL13_DWON_042245-2603042245-dsw--0-ia5 04-Mar-2026 22:45:31 2538
ber01-VHDL13_DWON_050331-2603050331-dsw--0-ia5 05-Mar-2026 03:31:07 2624
ber01-VHDL13_DWPG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2254
ber01-VHDL13_DWPG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2376
ber01-VHDL13_DWPG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2273
ber01-VHDL13_DWPG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2061
ber01-VHDL13_DWPG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:00 2320
ber01-VHDL13_DWPG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2296
ber01-VHDL13_DWPG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2484
ber01-VHDL13_DWPG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2249
ber01-VHDL13_DWPH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2342
ber01-VHDL13_DWPH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:07 2254
ber01-VHDL13_DWPH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 2222
ber01-VHDL13_DWPH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2117
ber01-VHDL13_DWPH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:00 2224
ber01-VHDL13_DWPH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2225
ber01-VHDL13_DWPH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:06 2203
ber01-VHDL13_DWPH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:09 2265
ber01-VHDL13_DWSG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2349
ber01-VHDL13_DWSG_030400_COR-2603030400-dsw--0-ia5 03-Mar-2026 06:04:37 2451
ber01-VHDL13_DWSG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:30:03 2295
ber01-VHDL13_DWSG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:30:02 1966
ber01-VHDL13_DWSG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:30:02 2128
ber01-VHDL13_DWSG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:06 2180
ber01-VHDL13_DWSG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:30:04 2221
ber01-VHDL13_DWSG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:30:02 2078
ber01-VHDL13_DWSG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:30:05 2244
ber01-VHDL17_DWOG_031200-2603031200-dsw--0-ia5 03-Mar-2026 12:09:02 2194
ber01-VHDL17_DWOG_041200-2603041200-dsw--0-ia5 04-Mar-2026 12:55:11 3059
swis2-VHDL20_DWEG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:06 2763
swis2-VHDL20_DWEG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2924
swis2-VHDL20_DWEG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2763
swis2-VHDL20_DWEG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2746
swis2-VHDL20_DWEG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2548
swis2-VHDL20_DWEG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2675
swis2-VHDL20_DWEG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:00 2460
swis2-VHDL20_DWEG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2502
swis2-VHDL20_DWEH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:06 2809
swis2-VHDL20_DWEH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2983
swis2-VHDL20_DWEH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2772
swis2-VHDL20_DWEH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2835
swis2-VHDL20_DWEH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2643
swis2-VHDL20_DWEH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2789
swis2-VHDL20_DWEH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:00 2500
swis2-VHDL20_DWEH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2576
swis2-VHDL20_DWEI_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:06 2654
swis2-VHDL20_DWEI_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2837
swis2-VHDL20_DWEI_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2652
swis2-VHDL20_DWEI_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2715
swis2-VHDL20_DWEI_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2547
swis2-VHDL20_DWEI_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2698
swis2-VHDL20_DWEI_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:00 2496
swis2-VHDL20_DWEI_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2546
swis2-VHDL20_DWHG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 3049
swis2-VHDL20_DWHG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 3314
swis2-VHDL20_DWHG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:08 2805
swis2-VHDL20_DWHG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:06 2696
swis2-VHDL20_DWHG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2684
swis2-VHDL20_DWHG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:06 3063
swis2-VHDL20_DWHG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:07 2342
swis2-VHDL20_DWHG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:06 3007
swis2-VHDL20_DWHH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:07 2683
swis2-VHDL20_DWHH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 3026
swis2-VHDL20_DWHH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:08 2330
swis2-VHDL20_DWHH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:06 2299
swis2-VHDL20_DWHH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2382
swis2-VHDL20_DWHH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:06 2640
swis2-VHDL20_DWHH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:07 2093
swis2-VHDL20_DWHH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:06 2668
swis2-VHDL20_DWLG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:11 2408
swis2-VHDL20_DWLG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2631
swis2-VHDL20_DWLG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2538
swis2-VHDL20_DWLG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2641
swis2-VHDL20_DWLG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2608
swis2-VHDL20_DWLG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2632
swis2-VHDL20_DWLG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2434
swis2-VHDL20_DWLG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2541
swis2-VHDL20_DWLH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:11 2514
swis2-VHDL20_DWLH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2810
swis2-VHDL20_DWLH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2707
swis2-VHDL20_DWLH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2662
swis2-VHDL20_DWLH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2482
swis2-VHDL20_DWLH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2675
swis2-VHDL20_DWLH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2416
swis2-VHDL20_DWLH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2381
swis2-VHDL20_DWLI_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:11 2315
swis2-VHDL20_DWLI_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2489
swis2-VHDL20_DWLI_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2430
swis2-VHDL20_DWLI_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2548
swis2-VHDL20_DWLI_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2532
swis2-VHDL20_DWLI_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2548
swis2-VHDL20_DWLI_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2591
swis2-VHDL20_DWLI_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2550
swis2-VHDL20_DWMG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:01 2856
swis2-VHDL20_DWMG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 3034
swis2-VHDL20_DWMG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:08 2324
swis2-VHDL20_DWMG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2419
swis2-VHDL20_DWMG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2415
swis2-VHDL20_DWMG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2804
swis2-VHDL20_DWMG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:07 2423
swis2-VHDL20_DWMG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2498
swis2-VHDL20_DWMO_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:01 2848
swis2-VHDL20_DWMO_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 3047
swis2-VHDL20_DWMO_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:08 2511
swis2-VHDL20_DWMO_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:06 2630
swis2-VHDL20_DWMO_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2641
swis2-VHDL20_DWMO_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 3018
swis2-VHDL20_DWMO_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:07 2571
swis2-VHDL20_DWMO_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2734
swis2-VHDL20_DWMP_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:01 3136
swis2-VHDL20_DWMP_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 3262
swis2-VHDL20_DWMP_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:08 2542
swis2-VHDL20_DWMP_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2701
swis2-VHDL20_DWMP_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2710
swis2-VHDL20_DWMP_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 3041
swis2-VHDL20_DWMP_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:07 2512
swis2-VHDL20_DWMP_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2674
swis2-VHDL20_DWPG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:11 2582
swis2-VHDL20_DWPG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2840
swis2-VHDL20_DWPG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2736
swis2-VHDL20_DWPG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2391
swis2-VHDL20_DWPG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2649
swis2-VHDL20_DWPG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2758
swis2-VHDL20_DWPG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2946
swis2-VHDL20_DWPG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2581
swis2-VHDL20_DWPH_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:00:11 2672
swis2-VHDL20_DWPH_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2718
swis2-VHDL20_DWPH_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2685
swis2-VHDL20_DWPH_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2446
swis2-VHDL20_DWPH_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:00:12 2555
swis2-VHDL20_DWPH_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2687
swis2-VHDL20_DWPH_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2665
swis2-VHDL20_DWPH_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2596
swis2-VHDL20_DWSG_030400-2603030400-dsw--0-ia5 03-Mar-2026 06:15:06 2831
swis2-VHDL20_DWSG_030400_COR-2603030400-dsw--0-ia5 03-Mar-2026 06:04:37 2835
swis2-VHDL20_DWSG_030800-2603030800-dsw--0-ia5 03-Mar-2026 09:45:04 2857
swis2-VHDL20_DWSG_031300-2603031300-dsw--0-ia5 03-Mar-2026 14:45:05 2631
swis2-VHDL20_DWSG_031800-2603031800-dsw--0-ia5 03-Mar-2026 19:45:04 2352
swis2-VHDL20_DWSG_040200-2603040200-dsw--0-ia5 04-Mar-2026 03:45:02 2503
swis2-VHDL20_DWSG_040400-2603040400-dsw--0-ia5 04-Mar-2026 06:15:04 2566
swis2-VHDL20_DWSG_040800-2603040800-dsw--0-ia5 04-Mar-2026 09:45:01 2782
swis2-VHDL20_DWSG_041300-2603041300-dsw--0-ia5 04-Mar-2026 14:45:10 2684
swis2-VHDL20_DWSG_041800-2603041800-dsw--0-ia5 04-Mar-2026 19:45:02 2466
swis2-VHDL20_DWSG_050200-2603050200-dsw--0-ia5 05-Mar-2026 03:45:01 2661
wst04-VHDL20_DWEG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:16 241556
wst04-VHDL20_DWEG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:12 243040
wst04-VHDL20_DWEG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:12 246894
wst04-VHDL20_DWEG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:12 247576
wst04-VHDL20_DWEG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:22 247678
wst04-VHDL20_DWEG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:16 247494
wst04-VHDL20_DWEG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:11 245811
wst04-VHDL20_DWEG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:18 246510
wst04-VHDL20_DWEH_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:16 241237
wst04-VHDL20_DWEH_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:16 242365
wst04-VHDL20_DWEH_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:12 245054
wst04-VHDL20_DWEH_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:12 246369
wst04-VHDL20_DWEH_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:16 245861
wst04-VHDL20_DWEH_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:16 248572
wst04-VHDL20_DWEH_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:11 246930
wst04-VHDL20_DWEH_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:18 247922
wst04-VHDL20_DWEI_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:22 347030
wst04-VHDL20_DWEI_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:16 347647
wst04-VHDL20_DWEI_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:18 359838
wst04-VHDL20_DWEI_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:18 359907
wst04-VHDL20_DWEI_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:22 360603
wst04-VHDL20_DWEI_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:26 358853
wst04-VHDL20_DWEI_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:17 357519
wst04-VHDL20_DWEI_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:22 357680
wst04-VHDL20_DWHG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:11 355074
wst04-VHDL20_DWHG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:26 355960
wst04-VHDL20_DWHG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:22 361782
wst04-VHDL20_DWHG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:16 361300
wst04-VHDL20_DWHG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:12 361347
wst04-VHDL20_DWHG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:26 359487
wst04-VHDL20_DWHG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:17 358001
wst04-VHDL20_DWHG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:18 358837
wst04-VHDL20_DWHH_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:11 329430
wst04-VHDL20_DWHH_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:26 329782
wst04-VHDL20_DWHH_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:22 331301
wst04-VHDL20_DWHH_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:16 331307
wst04-VHDL20_DWHH_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:12 331500
wst04-VHDL20_DWHH_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:26 328176
wst04-VHDL20_DWHH_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:17 327641
wst04-VHDL20_DWHH_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:12 328303
wst04-VHDL20_DWLG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:41 334513
wst04-VHDL20_DWLG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:32 334898
wst04-VHDL20_DWLG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:26 347433
wst04-VHDL20_DWLG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:22 347960
wst04-VHDL20_DWLG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:42 347102
wst04-VHDL20_DWLG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:32 344322
wst04-VHDL20_DWLG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:25 344372
wst04-VHDL20_DWLG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:22 344734
wst04-VHDL20_DWLH_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:41 334174
wst04-VHDL20_DWLH_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:32 334497
wst04-VHDL20_DWLH_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:22 350859
wst04-VHDL20_DWLH_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:26 351093
wst04-VHDL20_DWLH_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:42 350479
wst04-VHDL20_DWLH_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:36 356287
wst04-VHDL20_DWLH_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:25 355882
wst04-VHDL20_DWLH_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:26 356165
wst04-VHDL20_DWLI_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:41 340263
wst04-VHDL20_DWLI_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:32 340683
wst04-VHDL20_DWLI_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:26 350346
wst04-VHDL20_DWLI_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:26 350696
wst04-VHDL20_DWLI_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:42 350392
wst04-VHDL20_DWLI_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:32 356748
wst04-VHDL20_DWLI_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:21 356672
wst04-VHDL20_DWLI_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:26 356940
wst04-VHDL20_DWMG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:26 569993
wst04-VHDL20_DWMG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:26 569371
wst04-VHDL20_DWMG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:16 585686
wst04-VHDL20_DWMG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:22 585874
wst04-VHDL20_DWMG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:26 585767
wst04-VHDL20_DWMG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:22 578773
wst04-VHDL20_DWMG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:21 578001
wst04-VHDL20_DWMG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:16 578370
wst04-VHDL20_DWMO_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:22 462910
wst04-VHDL20_DWMO_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:20 462541
wst04-VHDL20_DWMO_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:16 481450
wst04-VHDL20_DWMO_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:16 481469
wst04-VHDL20_DWMO_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:22 481952
wst04-VHDL20_DWMO_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:16 475901
wst04-VHDL20_DWMO_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:17 474131
wst04-VHDL20_DWMP_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:26 564791
wst04-VHDL20_DWMP_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:26 565192
wst04-VHDL20_DWMP_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:16 575280
wst04-VHDL20_DWMP_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:22 574495
wst04-VHDL20_DWMP_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:26 575453
wst04-VHDL20_DWMP_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:22 569770
wst04-VHDL20_DWMP_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:21 568720
wst04-VHDL20_DWMP_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:12 568028
wst04-VHDL20_DWPG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:31 344748
wst04-VHDL20_DWPG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:36 389542
wst04-VHDL20_DWPG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:26 357375
wst04-VHDL20_DWPG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:26 357289
wst04-VHDL20_DWPG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:32 357151
wst04-VHDL20_DWPG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:32 399447
wst04-VHDL20_DWPG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:25 355577
wst04-VHDL20_DWPG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:26 354282
wst04-VHDL20_DWPH_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:00:31 247399
wst04-VHDL20_DWPH_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:32 291914
wst04-VHDL20_DWPH_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:22 291963
wst04-VHDL20_DWPH_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:22 247179
wst04-VHDL20_DWPH_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:00:32 247127
wst04-VHDL20_DWPH_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:26 290089
wst04-VHDL20_DWPH_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:21 289845
wst04-VHDL20_DWPH_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:22 244986
wst04-VHDL20_DWSG_030400-2603030400-omedes--0.pdf 03-Mar-2026 06:15:10 352978
wst04-VHDL20_DWSG_030400_COR-2603030400-omedes-..> 03-Mar-2026 06:04:41 352978
wst04-VHDL20_DWSG_030800-2603030800-omedes--0.pdf 03-Mar-2026 09:45:12 352709
wst04-VHDL20_DWSG_031300-2603031300-omedes--0.pdf 03-Mar-2026 14:45:23 360376
wst04-VHDL20_DWSG_031800-2603031800-omedes--0.pdf 03-Mar-2026 19:45:12 359201
wst04-VHDL20_DWSG_040200-2603040200-omedes--0.pdf 04-Mar-2026 03:45:12 360325
wst04-VHDL20_DWSG_040400-2603040400-omedes--0.pdf 04-Mar-2026 06:15:16 360071
wst04-VHDL20_DWSG_040800-2603040800-omedes--0.pdf 04-Mar-2026 09:45:12 359258
wst04-VHDL20_DWSG_041300-2603041300-omedes--0.pdf 04-Mar-2026 14:45:10 359261
wst04-VHDL20_DWSG_041800-2603041800-omedes--0.pdf 04-Mar-2026 19:45:11 359128
wst04-VHDL20_DWSG_050200-2603050200-omedes--0.pdf 05-Mar-2026 03:45:12 359398