Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Jan-2026 13:03:30 4946
FPDL13_DWMZ_240600 24-Jan-2026 14:44:49 4448
SXDL31_DWAV_230800 23-Jan-2026 08:26:25 8596
SXDL31_DWAV_231800 23-Jan-2026 18:04:55 8199
SXDL31_DWAV_240800 24-Jan-2026 08:01:53 10662
SXDL31_DWAV_241800 24-Jan-2026 18:25:44 7812
SXDL31_DWAV_LATEST 24-Jan-2026 18:25:44 7812
SXDL33_DWAV_230000 23-Jan-2026 10:31:59 8506
SXDL33_DWAV_240000 24-Jan-2026 10:01:49 6715
SXDL33_DWAV_LATEST 24-Jan-2026 10:01:49 6715
ber01-FWDL39_DWMS_231230-2601231230-dsw--0-ia5 23-Jan-2026 11:59:31 1712
ber01-FWDL39_DWMS_241230-2601241230-dsw--0-ia5 24-Jan-2026 12:47:42 1914
ber01-VHDL13_DWEH_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:16 2991
ber01-VHDL13_DWEH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:21 3467
ber01-VHDL13_DWEH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:22 3284
ber01-VHDL13_DWEH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3745
ber01-VHDL13_DWEH_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3699
ber01-VHDL13_DWEH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:22 3989
ber01-VHDL13_DWEH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:22 2468
ber01-VHDL13_DWEH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3258
ber01-VHDL13_DWHG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:01:51 4278
ber01-VHDL13_DWHG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 5154
ber01-VHDL13_DWHG_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:35:16 5101
ber01-VHDL13_DWHG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 4496
ber01-VHDL13_DWHG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 4510
ber01-VHDL13_DWHG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 4635
ber01-VHDL13_DWHG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 4635
ber01-VHDL13_DWHG_240800_COR-2601240800-dsw--0-ia5 24-Jan-2026 09:43:01 4765
ber01-VHDL13_DWHG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 3581
ber01-VHDL13_DWHG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3848
ber01-VHDL13_DWHH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3293
ber01-VHDL13_DWHH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3595
ber01-VHDL13_DWHH_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:37:59 3608
ber01-VHDL13_DWHH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 3263
ber01-VHDL13_DWHH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 3214
ber01-VHDL13_DWHH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3240
ber01-VHDL13_DWHH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3240
ber01-VHDL13_DWHH_240800_COR-2601240800-dsw--0-ia5 24-Jan-2026 09:43:21 3470
ber01-VHDL13_DWHH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3006
ber01-VHDL13_DWHH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3894
ber01-VHDL13_DWLG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2193
ber01-VHDL13_DWLG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2614
ber01-VHDL13_DWLG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 2253
ber01-VHDL13_DWLG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2546
ber01-VHDL13_DWLG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2693
ber01-VHDL13_DWLG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3431
ber01-VHDL13_DWLG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3559
ber01-VHDL13_DWLG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3609
ber01-VHDL13_DWLH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 1922
ber01-VHDL13_DWLH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2354
ber01-VHDL13_DWLH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 1954
ber01-VHDL13_DWLH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2262
ber01-VHDL13_DWLH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2388
ber01-VHDL13_DWLH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2779
ber01-VHDL13_DWLH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 3008
ber01-VHDL13_DWLH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3242
ber01-VHDL13_DWLI_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2299
ber01-VHDL13_DWLI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2611
ber01-VHDL13_DWLI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 2014
ber01-VHDL13_DWLI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2195
ber01-VHDL13_DWLI_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2281
ber01-VHDL13_DWLI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2504
ber01-VHDL13_DWLI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 2788
ber01-VHDL13_DWLI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 2997
ber01-VHDL13_DWMG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:01 2862
ber01-VHDL13_DWMG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3210
ber01-VHDL13_DWMG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2919
ber01-VHDL13_DWMG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:01 3004
ber01-VHDL13_DWMG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3123
ber01-VHDL13_DWMG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3965
ber01-VHDL13_DWMG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3148
ber01-VHDL13_DWMG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4332
ber01-VHDL13_DWMO_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3114
ber01-VHDL13_DWMO_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3109
ber01-VHDL13_DWMO_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2820
ber01-VHDL13_DWMO_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 3200
ber01-VHDL13_DWMO_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3200
ber01-VHDL13_DWMO_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3589
ber01-VHDL13_DWMO_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 2796
ber01-VHDL13_DWMO_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3424
ber01-VHDL13_DWMP_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:01 2909
ber01-VHDL13_DWMP_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2994
ber01-VHDL13_DWMP_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2863
ber01-VHDL13_DWMP_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 3137
ber01-VHDL13_DWMP_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3198
ber01-VHDL13_DWMP_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 4105
ber01-VHDL13_DWMP_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3167
ber01-VHDL13_DWMP_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4407
ber01-VHDL13_DWOG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:01 5181
ber01-VHDL13_DWOG_231700-2601231700-dsw--0-ia5 23-Jan-2026 19:00:02 4108
ber01-VHDL13_DWOG_240300-2601240300-dsw--0-ia5 24-Jan-2026 04:00:03 4695
ber01-VHDL13_DWOG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 5077
ber01-VHDL13_DWOG_241700-2601241700-dsw--0-ia5 24-Jan-2026 19:00:06 4604
ber01-VHDL13_DWOG_250300-2601250300-dsw--0-ia5 25-Jan-2026 04:00:01 5679
ber01-VHDL13_DWOH_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:16 2722
ber01-VHDL13_DWOH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:17 2856
ber01-VHDL13_DWOH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:16 2787
ber01-VHDL13_DWOH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3394
ber01-VHDL13_DWOH_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3343
ber01-VHDL13_DWOH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:16 3750
ber01-VHDL13_DWOH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:16 2670
ber01-VHDL13_DWOH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3050
ber01-VHDL13_DWOI_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:22 2659
ber01-VHDL13_DWOI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:17 2777
ber01-VHDL13_DWOI_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 12:02:51 2844
ber01-VHDL13_DWOI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:16 2695
ber01-VHDL13_DWOI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3392
ber01-VHDL13_DWOI_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3334
ber01-VHDL13_DWOI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:16 3269
ber01-VHDL13_DWOI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:16 3007
ber01-VHDL13_DWOI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3550
ber01-VHDL13_DWON_230602-2601230602-dsw--0-ia5 23-Jan-2026 06:02:32 3958
ber01-VHDL13_DWON_230709-2601230709-dsw--0-ia5 23-Jan-2026 07:10:08 3958
ber01-VHDL13_DWON_231229-2601231229-dsw--0-ia5 23-Jan-2026 12:30:02 4133
ber01-VHDL13_DWON_231421-2601231421-dsw--0-ia5 23-Jan-2026 14:21:47 3581
ber01-VHDL13_DWON_231823-2601231823-dsw--0-ia5 23-Jan-2026 18:23:41 3242
ber01-VHDL13_DWON_232351-2601232351-dsw--0-ia5 23-Jan-2026 23:51:41 3910
ber01-VHDL13_DWON_240147-2601240147-dsw--0-ia5 24-Jan-2026 01:47:06 3309
ber01-VHDL13_DWON_240303-2601240303-dsw--0-ia5 24-Jan-2026 03:03:27 3309
ber01-VHDL13_DWON_240314-2601240314-dsw--0-ia5 24-Jan-2026 03:14:17 3696
ber01-VHDL13_DWON_240447-2601240447-dsw--0-ia5 24-Jan-2026 04:47:32 3684
ber01-VHDL13_DWON_240451-2601240451-dsw--0-ia5 24-Jan-2026 04:51:54 3684
ber01-VHDL13_DWON_240630-2601240630-dsw--0-ia5 24-Jan-2026 06:30:32 4083
ber01-VHDL13_DWON_240710-2601240710-dsw--0-ia5 24-Jan-2026 07:10:07 4239
ber01-VHDL13_DWON_240718-2601240718-dsw--0-ia5 24-Jan-2026 07:19:02 4232
ber01-VHDL13_DWON_240913-2601240913-dsw--0-ia5 24-Jan-2026 09:13:22 4194
ber01-VHDL13_DWON_241539-2601241539-dsw--0-ia5 24-Jan-2026 15:41:09 3299
ber01-VHDL13_DWON_241849-2601241849-dsw--0-ia5 24-Jan-2026 18:49:52 3472
ber01-VHDL13_DWON_242341-2601242341-dsw--0-ia5 24-Jan-2026 23:41:15 3315
ber01-VHDL13_DWON_250119-2601250119-dsw--0-ia5 25-Jan-2026 01:19:51 3315
ber01-VHDL13_DWON_250151-2601250151-dsw--0-ia5 25-Jan-2026 01:51:17 3560
ber01-VHDL13_DWON_250316-2601250316-dsw--0-ia5 25-Jan-2026 03:16:52 3560
ber01-VHDL13_DWON_250439-2601250439-dsw--0-ia5 25-Jan-2026 04:39:26 3560
ber01-VHDL13_DWPG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 1929
ber01-VHDL13_DWPG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2637
ber01-VHDL13_DWPG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2413
ber01-VHDL13_DWPG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2661
ber01-VHDL13_DWPG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2719
ber01-VHDL13_DWPG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3002
ber01-VHDL13_DWPG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3370
ber01-VHDL13_DWPG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3527
ber01-VHDL13_DWPH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2444
ber01-VHDL13_DWPH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2902
ber01-VHDL13_DWPH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2500
ber01-VHDL13_DWPH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2689
ber01-VHDL13_DWPH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2500
ber01-VHDL13_DWPH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2801
ber01-VHDL13_DWPH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3409
ber01-VHDL13_DWPH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3693
ber01-VHDL13_DWSG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2972
ber01-VHDL13_DWSG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:01 2721
ber01-VHDL13_DWSG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2755
ber01-VHDL13_DWSG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 3016
ber01-VHDL13_DWSG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:08 2972
ber01-VHDL13_DWSG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3243
ber01-VHDL13_DWSG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3261
ber01-VHDL13_DWSG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4137
ber01-VHDL17_DWOG_231200-2601231200-dsw--0-ia5 23-Jan-2026 12:17:47 2715
ber01-VHDL17_DWOG_241200-2601241200-dsw--0-ia5 24-Jan-2026 11:47:02 2682
swis2-VHDL20_DWEG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3128
swis2-VHDL20_DWEG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3550
swis2-VHDL20_DWEG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3285
swis2-VHDL20_DWEG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3910
swis2-VHDL20_DWEG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3722
swis2-VHDL20_DWEG_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:26:37 4133
swis2-VHDL20_DWEG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4627
swis2-VHDL20_DWEG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3183
swis2-VHDL20_DWEG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3496
swis2-VHDL20_DWEH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3455
swis2-VHDL20_DWEH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 4160
swis2-VHDL20_DWEH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3760
swis2-VHDL20_DWEH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 4188
swis2-VHDL20_DWEH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 4102
swis2-VHDL20_DWEH_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:27:21 4396
swis2-VHDL20_DWEH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4935
swis2-VHDL20_DWEH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 2947
swis2-VHDL20_DWEH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3704
swis2-VHDL20_DWEI_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3113
swis2-VHDL20_DWEI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3552
swis2-VHDL20_DWEI_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 12:04:12 3619
swis2-VHDL20_DWEI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3225
swis2-VHDL20_DWEI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3913
swis2-VHDL20_DWEI_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3759
swis2-VHDL20_DWEI_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:28:11 3692
swis2-VHDL20_DWEI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4144
swis2-VHDL20_DWEI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3532
swis2-VHDL20_DWEI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4016
swis2-VHDL20_DWHG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 4532
swis2-VHDL20_DWHG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 6208
swis2-VHDL20_DWHG_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:38:38 6152
swis2-VHDL20_DWHG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:04 4679
swis2-VHDL20_DWHG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 4696
swis2-VHDL20_DWHG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 4818
swis2-VHDL20_DWHG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:01 5723
swis2-VHDL20_DWHG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3764
swis2-VHDL20_DWHG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4034
swis2-VHDL20_DWHH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3479
swis2-VHDL20_DWHH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 4286
swis2-VHDL20_DWHH_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:39:12 4296
swis2-VHDL20_DWHH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:04 3449
swis2-VHDL20_DWHH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3400
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swis2-VHDL20_DWMO_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3630
swis2-VHDL20_DWMO_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:01 3714
swis2-VHDL20_DWMO_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4191
swis2-VHDL20_DWMO_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3224
swis2-VHDL20_DWMO_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3900
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swis2-VHDL20_DWMP_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3333
swis2-VHDL20_DWMP_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3569
swis2-VHDL20_DWMP_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:01 3621
swis2-VHDL20_DWMP_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4718
swis2-VHDL20_DWMP_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3618
swis2-VHDL20_DWMP_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4834
swis2-VHDL20_DWPG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2255
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swis2-VHDL20_DWPG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3255
swis2-VHDL20_DWPG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3256
swis2-VHDL20_DWPG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:12 3162
swis2-VHDL20_DWPG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 3884
swis2-VHDL20_DWPG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 4249
swis2-VHDL20_DWPG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3938
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swis2-VHDL20_DWPH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3342
swis2-VHDL20_DWPH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3283
swis2-VHDL20_DWPH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:12 2945
swis2-VHDL20_DWPH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 3619
swis2-VHDL20_DWPH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:08 4127
swis2-VHDL20_DWPH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4103
swis2-VHDL20_DWSG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:01 3498
swis2-VHDL20_DWSG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 3448
swis2-VHDL20_DWSG_231300-2601231300-dsw--0-ia5 23-Jan-2026 14:45:38 3250
swis2-VHDL20_DWSG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3278
swis2-VHDL20_DWSG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3530
swis2-VHDL20_DWSG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3381
swis2-VHDL20_DWSG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:01 3840
swis2-VHDL20_DWSG_241300-2601241300-dsw--0-ia5 24-Jan-2026 14:45:06 3628
swis2-VHDL20_DWSG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3672
swis2-VHDL20_DWSG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4539
wst04-VHDL20_DWEG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:27 230266
wst04-VHDL20_DWEG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 233760
wst04-VHDL20_DWEG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:16 232196
wst04-VHDL20_DWEG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:17 233477
wst04-VHDL20_DWEG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:17 232899
wst04-VHDL20_DWEG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 229533
wst04-VHDL20_DWEG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:18 227002
wst04-VHDL20_DWEG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 228928
wst04-VHDL20_DWEH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:23 233488
wst04-VHDL20_DWEH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 232809
wst04-VHDL20_DWEH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 231836
wst04-VHDL20_DWEH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 232353
wst04-VHDL20_DWEH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:21 231857
wst04-VHDL20_DWEH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:16 226427
wst04-VHDL20_DWEH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 224061
wst04-VHDL20_DWEH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 226785
wst04-VHDL20_DWEI_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:27 328645
wst04-VHDL20_DWEI_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 331122
wst04-VHDL20_DWEI_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:16 330237
wst04-VHDL20_DWEI_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:17 330775
wst04-VHDL20_DWEI_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:25 330629
wst04-VHDL20_DWEI_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:16 323134
wst04-VHDL20_DWEI_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:18 322031
wst04-VHDL20_DWEI_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 323352
wst04-VHDL20_DWHG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:11 307385
wst04-VHDL20_DWHG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:13 312001
wst04-VHDL20_DWHG_230800_COR-2601230800-omedes-..> 23-Jan-2026 11:32:32 311944
wst04-VHDL20_DWHG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 310498
wst04-VHDL20_DWHG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 310741
wst04-VHDL20_DWHG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:12 310889
wst04-VHDL20_DWHG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 302713
wst04-VHDL20_DWHG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 299543
wst04-VHDL20_DWHG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 299699
wst04-VHDL20_DWHH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:11 292511
wst04-VHDL20_DWHH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:13 292687
wst04-VHDL20_DWHH_230800_COR-2601230800-omedes-..> 23-Jan-2026 11:34:43 292658
wst04-VHDL20_DWHH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 291366
wst04-VHDL20_DWHH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 291418
wst04-VHDL20_DWHH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:12 291502
wst04-VHDL20_DWHH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 292451
wst04-VHDL20_DWHH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 289969
wst04-VHDL20_DWHH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 290516
wst04-VHDL20_DWLG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:43 300930
wst04-VHDL20_DWLG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:41 309382
wst04-VHDL20_DWLG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:32 308686
wst04-VHDL20_DWLG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:27 308878
wst04-VHDL20_DWLG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:43 308642
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wst04-VHDL20_DWLG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:27 304023
wst04-VHDL20_DWLG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:33 303974
wst04-VHDL20_DWLH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:41 302445
wst04-VHDL20_DWLH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:37 298390
wst04-VHDL20_DWLH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:26 297656
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wst04-VHDL20_DWLH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:38 297934
wst04-VHDL20_DWLH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:30 297445
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wst04-VHDL20_DWLI_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:47 314062
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wst04-VHDL20_DWMP_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:22 563553
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wst04-VHDL20_DWPG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:31 305601
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wst04-VHDL20_DWPG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:33 302012
wst04-VHDL20_DWPG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:38 342621
wst04-VHDL20_DWPG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:30 298105
wst04-VHDL20_DWPG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:31 298473
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wst04-VHDL20_DWPH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:31 265287
wst04-VHDL20_DWPH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:26 264378
wst04-VHDL20_DWPH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:27 219311
wst04-VHDL20_DWPH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:33 218981
wst04-VHDL20_DWPH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:32 259886
wst04-VHDL20_DWPH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:27 261564
wst04-VHDL20_DWPH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:29 216522
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wst04-VHDL20_DWSG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 338335
wst04-VHDL20_DWSG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 338341
wst04-VHDL20_DWSG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:11 338331
wst04-VHDL20_DWSG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:10 341099
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wst04-VHDL20_DWSG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:10 340154
wst04-VHDL20_DWSG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 340541