Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Feb-2026 13:52:56 2848
FPDL13_DWMZ_280600 28-Feb-2026 13:30:40 8518
SXDL31_DWAV_261800 26-Feb-2026 17:38:53 5416
SXDL31_DWAV_270800 27-Feb-2026 08:59:35 12242
SXDL31_DWAV_271800 27-Feb-2026 17:28:14 5334
SXDL31_DWAV_280800 28-Feb-2026 08:53:09 7922
SXDL31_DWAV_LATEST 28-Feb-2026 08:53:09 7922
SXDL33_DWAV_270000 27-Feb-2026 09:00:15 7561
SXDL33_DWAV_280000 28-Feb-2026 10:27:19 6914
SXDL33_DWAV_LATEST 28-Feb-2026 10:27:19 6914
ber01-FWDL39_DWMS_271230-2602271230-dsw--0-ia5 27-Feb-2026 12:57:42 1335
ber01-FWDL39_DWMS_281230-2602281230-dsw--0-ia5 28-Feb-2026 12:52:31 2061
ber01-VHDL13_DWEH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:16 2570
ber01-VHDL13_DWEH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:11 2781
ber01-VHDL13_DWEH_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:16 2796
ber01-VHDL13_DWEH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:17 2925
ber01-VHDL13_DWEH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:16 2792
ber01-VHDL13_DWEH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:11 3182
ber01-VHDL13_DWEH_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:17 3051
ber01-VHDL13_DWEH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:17 3042
ber01-VHDL13_DWHG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:10 2332
ber01-VHDL13_DWHG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2324
ber01-VHDL13_DWHG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2369
ber01-VHDL13_DWHG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2633
ber01-VHDL13_DWHG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2848
ber01-VHDL13_DWHG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2945
ber01-VHDL13_DWHG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2949
ber01-VHDL13_DWHG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 3033
ber01-VHDL13_DWHH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:10 2500
ber01-VHDL13_DWHH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2477
ber01-VHDL13_DWHH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:07 2490
ber01-VHDL13_DWHH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 2381
ber01-VHDL13_DWHH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2475
ber01-VHDL13_DWHH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2718
ber01-VHDL13_DWHH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2732
ber01-VHDL13_DWHH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2492
ber01-VHDL13_DWLG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1895
ber01-VHDL13_DWLG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2258
ber01-VHDL13_DWLG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 1934
ber01-VHDL13_DWLG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 1920
ber01-VHDL13_DWLG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1817
ber01-VHDL13_DWLG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2036
ber01-VHDL13_DWLG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 1994
ber01-VHDL13_DWLG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2051
ber01-VHDL13_DWLH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2328
ber01-VHDL13_DWLH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2513
ber01-VHDL13_DWLH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2399
ber01-VHDL13_DWLH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2399
ber01-VHDL13_DWLH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2245
ber01-VHDL13_DWLH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2296
ber01-VHDL13_DWLH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 2335
ber01-VHDL13_DWLH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2337
ber01-VHDL13_DWLI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2241
ber01-VHDL13_DWLI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2447
ber01-VHDL13_DWLI_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2130
ber01-VHDL13_DWLI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 2142
ber01-VHDL13_DWLI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1855
ber01-VHDL13_DWLI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 1999
ber01-VHDL13_DWLI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 2049
ber01-VHDL13_DWLI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2051
ber01-VHDL13_DWMG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2499
ber01-VHDL13_DWMG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2765
ber01-VHDL13_DWMG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2775
ber01-VHDL13_DWMG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2540
ber01-VHDL13_DWMG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2209
ber01-VHDL13_DWMG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2418
ber01-VHDL13_DWMG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2405
ber01-VHDL13_DWMG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2563
ber01-VHDL13_DWMO_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2389
ber01-VHDL13_DWMO_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2770
ber01-VHDL13_DWMO_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2762
ber01-VHDL13_DWMO_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2774
ber01-VHDL13_DWMO_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2360
ber01-VHDL13_DWMO_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2520
ber01-VHDL13_DWMO_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2515
ber01-VHDL13_DWMO_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2709
ber01-VHDL13_DWMP_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2385
ber01-VHDL13_DWMP_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2699
ber01-VHDL13_DWMP_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2690
ber01-VHDL13_DWMP_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2465
ber01-VHDL13_DWMP_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2210
ber01-VHDL13_DWMP_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2047
ber01-VHDL13_DWMP_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2035
ber01-VHDL13_DWMP_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2258
ber01-VHDL13_DWOG_261700-2602261700-dsw--0-ia5 26-Feb-2026 19:00:01 3326
ber01-VHDL13_DWOG_270300-2602270300-dsw--0-ia5 27-Feb-2026 04:00:06 3986
ber01-VHDL13_DWOG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 3774
ber01-VHDL13_DWOG_271700-2602271700-dsw--0-ia5 27-Feb-2026 19:00:07 3360
ber01-VHDL13_DWOG_280300-2602280300-dsw--0-ia5 28-Feb-2026 04:00:06 3612
ber01-VHDL13_DWOG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 3335
ber01-VHDL13_DWOH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:16 2243
ber01-VHDL13_DWOH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:11 2554
ber01-VHDL13_DWOH_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:11 2548
ber01-VHDL13_DWOH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:17 2678
ber01-VHDL13_DWOH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:16 2505
ber01-VHDL13_DWOH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:11 2788
ber01-VHDL13_DWOH_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:11 2735
ber01-VHDL13_DWOH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:17 2788
ber01-VHDL13_DWOI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:12 2336
ber01-VHDL13_DWOI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:16 2565
ber01-VHDL13_DWOI_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:16 2615
ber01-VHDL13_DWOI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:12 2651
ber01-VHDL13_DWOI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:12 2542
ber01-VHDL13_DWOI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:17 2905
ber01-VHDL13_DWOI_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:17 2849
ber01-VHDL13_DWOI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:13 3000
ber01-VHDL13_DWON_261742-2602261742-dsw--0-ia5 26-Feb-2026 17:43:01 2947
ber01-VHDL13_DWON_262240-2602262240-dsw--0-ia5 26-Feb-2026 22:40:17 3080
ber01-VHDL13_DWON_270232-2602270232-dsw--0-ia5 27-Feb-2026 02:32:47 3486
ber01-VHDL13_DWON_270635-2602270635-dsw--0-ia5 27-Feb-2026 06:35:21 3769
ber01-VHDL13_DWON_270710-2602270710-dsw--0-ia5 27-Feb-2026 07:10:43 3769
ber01-VHDL13_DWON_270919-2602270919-dsw--0-ia5 27-Feb-2026 09:19:57 3689
ber01-VHDL13_DWON_270958-2602270958-dsw--0-ia5 27-Feb-2026 09:58:26 3689
ber01-VHDL13_DWON_271555-2602271555-dsw--0-ia5 27-Feb-2026 15:55:22 2818
ber01-VHDL13_DWON_271729-2602271729-dsw--0-ia5 27-Feb-2026 17:29:22 2818
ber01-VHDL13_DWON_272338-2602272338-dsw--0-ia5 27-Feb-2026 23:39:01 3398
ber01-VHDL13_DWON_280153-2602280153-dsw--0-ia5 28-Feb-2026 01:53:06 3398
ber01-VHDL13_DWON_280353-2602280353-dsw--0-ia5 28-Feb-2026 03:53:22 3398
ber01-VHDL13_DWON_280629-2602280629-dsw--0-ia5 28-Feb-2026 06:29:17 3162
ber01-VHDL13_DWON_280725-2602280725-dsw--0-ia5 28-Feb-2026 07:25:26 2888
ber01-VHDL13_DWON_280942-2602280942-dsw--0-ia5 28-Feb-2026 09:42:31 2888
ber01-VHDL13_DWON_281539-2602281539-dsw--0-ia5 28-Feb-2026 15:40:06 2652
ber01-VHDL13_DWON_281541-2602281541-dsw--0-ia5 28-Feb-2026 15:41:47 2652
ber01-VHDL13_DWPG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1896
ber01-VHDL13_DWPG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2039
ber01-VHDL13_DWPG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2051
ber01-VHDL13_DWPG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 1945
ber01-VHDL13_DWPG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1819
ber01-VHDL13_DWPG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 1885
ber01-VHDL13_DWPG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 1901
ber01-VHDL13_DWPG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 1888
ber01-VHDL13_DWPH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1903
ber01-VHDL13_DWPH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2194
ber01-VHDL13_DWPH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2205
ber01-VHDL13_DWPH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2068
ber01-VHDL13_DWPH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1860
ber01-VHDL13_DWPH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2090
ber01-VHDL13_DWPH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2115
ber01-VHDL13_DWPH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2085
ber01-VHDL13_DWSG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2408
ber01-VHDL13_DWSG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2513
ber01-VHDL13_DWSG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2474
ber01-VHDL13_DWSG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2402
ber01-VHDL13_DWSG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2179
ber01-VHDL13_DWSG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2165
ber01-VHDL13_DWSG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2345
ber01-VHDL13_DWSG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2323
ber01-VHDL17_DWOG_271200-2602271200-dsw--0-ia5 27-Feb-2026 11:52:51 2512
ber01-VHDL17_DWOG_281200-2602281200-dsw--0-ia5 28-Feb-2026 12:20:27 1713
swis2-VHDL20_DWEG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2569
swis2-VHDL20_DWEG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2830
swis2-VHDL20_DWEG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 2871
swis2-VHDL20_DWEG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3159
swis2-VHDL20_DWEG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2832
swis2-VHDL20_DWEG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3065
swis2-VHDL20_DWEG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3162
swis2-VHDL20_DWEG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3371
swis2-VHDL20_DWEH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2924
swis2-VHDL20_DWEH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 3102
swis2-VHDL20_DWEH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 3134
swis2-VHDL20_DWEH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3431
swis2-VHDL20_DWEH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 3147
swis2-VHDL20_DWEH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3504
swis2-VHDL20_DWEH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3387
swis2-VHDL20_DWEH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3543
swis2-VHDL20_DWEI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2687
swis2-VHDL20_DWEI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2857
swis2-VHDL20_DWEI_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 2969
swis2-VHDL20_DWEI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3179
swis2-VHDL20_DWEI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2894
swis2-VHDL20_DWEI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3198
swis2-VHDL20_DWEI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3310
swis2-VHDL20_DWEI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3633
swis2-VHDL20_DWHG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:06 2515
swis2-VHDL20_DWHG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:06 2510
swis2-VHDL20_DWHG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2552
swis2-VHDL20_DWHG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3167
swis2-VHDL20_DWHG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 3031
swis2-VHDL20_DWHG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 3131
swis2-VHDL20_DWHG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 3132
swis2-VHDL20_DWHG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3572
swis2-VHDL20_DWHH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:06 2686
swis2-VHDL20_DWHH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:06 2663
swis2-VHDL20_DWHH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:07 2676
swis2-VHDL20_DWHH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:08 2924
swis2-VHDL20_DWHH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2661
swis2-VHDL20_DWHH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2904
swis2-VHDL20_DWHH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2918
swis2-VHDL20_DWHH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3040
swis2-VHDL20_DWLG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2239
swis2-VHDL20_DWLG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2602
swis2-VHDL20_DWLG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2276
swis2-VHDL20_DWLG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2408
swis2-VHDL20_DWLG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2159
swis2-VHDL20_DWLG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2378
swis2-VHDL20_DWLG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2336
swis2-VHDL20_DWLG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2542
swis2-VHDL20_DWLH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2677
swis2-VHDL20_DWLH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2862
swis2-VHDL20_DWLH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2748
swis2-VHDL20_DWLH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2898
swis2-VHDL20_DWLH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2594
swis2-VHDL20_DWLH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2645
swis2-VHDL20_DWLH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2684
swis2-VHDL20_DWLH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2838
swis2-VHDL20_DWLI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2587
swis2-VHDL20_DWLI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2793
swis2-VHDL20_DWLI_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2474
swis2-VHDL20_DWLI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2631
swis2-VHDL20_DWLI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2199
swis2-VHDL20_DWLI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2343
swis2-VHDL20_DWLI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2393
swis2-VHDL20_DWLI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2543
swis2-VHDL20_DWMG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2953
swis2-VHDL20_DWMG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 3225
swis2-VHDL20_DWMG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:02 3229
swis2-VHDL20_DWMG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:06 3150
swis2-VHDL20_DWMG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2663
swis2-VHDL20_DWMG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2814
swis2-VHDL20_DWMG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2776
swis2-VHDL20_DWMG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3153
swis2-VHDL20_DWMO_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2856
swis2-VHDL20_DWMO_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 3232
swis2-VHDL20_DWMO_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:02 3225
swis2-VHDL20_DWMO_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:06 3407
swis2-VHDL20_DWMO_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2829
swis2-VHDL20_DWMO_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2895
swis2-VHDL20_DWMO_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2889
swis2-VHDL20_DWMO_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3307
swis2-VHDL20_DWMP_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2861
swis2-VHDL20_DWMP_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 3135
swis2-VHDL20_DWMP_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:02 3123
swis2-VHDL20_DWMP_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:06 3094
swis2-VHDL20_DWMP_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2641
swis2-VHDL20_DWMP_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2470
swis2-VHDL20_DWMP_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2405
swis2-VHDL20_DWMP_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 2853
swis2-VHDL20_DWPG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2355
swis2-VHDL20_DWPG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2368
swis2-VHDL20_DWPG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2377
swis2-VHDL20_DWPG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2404
swis2-VHDL20_DWPG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2278
swis2-VHDL20_DWPG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2214
swis2-VHDL20_DWPG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2227
swis2-VHDL20_DWPG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2347
swis2-VHDL20_DWPH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2362
swis2-VHDL20_DWPH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2522
swis2-VHDL20_DWPH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2533
swis2-VHDL20_DWPH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2527
swis2-VHDL20_DWPH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2319
swis2-VHDL20_DWPH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2418
swis2-VHDL20_DWPH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2443
swis2-VHDL20_DWPH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2544
swis2-VHDL20_DWSG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2763
swis2-VHDL20_DWSG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2859
swis2-VHDL20_DWSG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:02 2827
swis2-VHDL20_DWSG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2902
swis2-VHDL20_DWSG_271300-2602271300-dsw--0-ia5 27-Feb-2026 14:45:11 2783
swis2-VHDL20_DWSG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2534
swis2-VHDL20_DWSG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2510
swis2-VHDL20_DWSG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:05 2698
swis2-VHDL20_DWSG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2882
swis2-VHDL20_DWSG_281300-2602281300-dsw--0-ia5 28-Feb-2026 14:45:06 2748
wst04-VHDL20_DWEG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:12 246477
wst04-VHDL20_DWEG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:12 246935
wst04-VHDL20_DWEG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:17 246479
wst04-VHDL20_DWEG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:12 248463
wst04-VHDL20_DWEG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:12 246599
wst04-VHDL20_DWEG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 247335
wst04-VHDL20_DWEG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 246682
wst04-VHDL20_DWEG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 243329
wst04-VHDL20_DWEH_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:12 245394
wst04-VHDL20_DWEH_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:12 246428
wst04-VHDL20_DWEH_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:17 246050
wst04-VHDL20_DWEH_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:19 251050
wst04-VHDL20_DWEH_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:12 248570
wst04-VHDL20_DWEH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 250729
wst04-VHDL20_DWEH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:27 250354
wst04-VHDL20_DWEH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 246687
wst04-VHDL20_DWEI_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:16 350547
wst04-VHDL20_DWEI_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:18 350911
wst04-VHDL20_DWEI_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:21 350891
wst04-VHDL20_DWEI_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:22 354566
wst04-VHDL20_DWEI_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:12 354088
wst04-VHDL20_DWEI_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 354501
wst04-VHDL20_DWEI_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 354308
wst04-VHDL20_DWEI_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:16 349394
wst04-VHDL20_DWHG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:22 344168
wst04-VHDL20_DWHG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:16 344276
wst04-VHDL20_DWHG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:11 344323
wst04-VHDL20_DWHG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:26 354120
wst04-VHDL20_DWHG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:22 353425
wst04-VHDL20_DWHG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 354339
wst04-VHDL20_DWHG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:11 354409
wst04-VHDL20_DWHG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 351205
wst04-VHDL20_DWHH_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:22 326852
wst04-VHDL20_DWHH_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:20 326806
wst04-VHDL20_DWHH_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:11 326824
wst04-VHDL20_DWHH_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:26 332550
wst04-VHDL20_DWHH_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:22 331786
wst04-VHDL20_DWHH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 331822
wst04-VHDL20_DWHH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:11 331944
wst04-VHDL20_DWHH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 330716
wst04-VHDL20_DWLG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:26 351120
wst04-VHDL20_DWLG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:26 351491
wst04-VHDL20_DWLG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:41 351410
wst04-VHDL20_DWLG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:35 341647
wst04-VHDL20_DWLG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:26 340898
wst04-VHDL20_DWLG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 340425
wst04-VHDL20_DWLG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 341375
wst04-VHDL20_DWLG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 334346
wst04-VHDL20_DWLH_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:22 343625
wst04-VHDL20_DWLH_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:26 343724
wst04-VHDL20_DWLH_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:41 343927
wst04-VHDL20_DWLH_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:35 347215
wst04-VHDL20_DWLH_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:22 346985
wst04-VHDL20_DWLH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 346306
wst04-VHDL20_DWLH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 347355
wst04-VHDL20_DWLH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 339165
wst04-VHDL20_DWLI_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:26 345828
wst04-VHDL20_DWLI_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:26 345953
wst04-VHDL20_DWLI_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:41 345844
wst04-VHDL20_DWLI_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:39 340898
wst04-VHDL20_DWLI_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:26 340079
wst04-VHDL20_DWLI_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 339530
wst04-VHDL20_DWLI_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 340631
wst04-VHDL20_DWLI_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 342134
wst04-VHDL20_DWMG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:16 577789
wst04-VHDL20_DWMG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:20 577276
wst04-VHDL20_DWMG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:21 577958
wst04-VHDL20_DWMG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:22 575987
wst04-VHDL20_DWMG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:16 574183
wst04-VHDL20_DWMG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:17 575655
wst04-VHDL20_DWMG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 575574
wst04-VHDL20_DWMG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 559988
wst04-VHDL20_DWMO_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:16 471111
wst04-VHDL20_DWMO_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:16 472081
wst04-VHDL20_DWMO_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:17 472560
wst04-VHDL20_DWMO_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:19 476533
wst04-VHDL20_DWMO_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:16 475049
wst04-VHDL20_DWMO_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:17 475695
wst04-VHDL20_DWMO_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:17 476242
wst04-VHDL20_DWMO_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:22 461726
wst04-VHDL20_DWMP_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:16 571961
wst04-VHDL20_DWMP_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:20 571200
wst04-VHDL20_DWMP_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:21 572150
wst04-VHDL20_DWMP_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:22 562482
wst04-VHDL20_DWMP_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:16 560617
wst04-VHDL20_DWMP_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 560839
wst04-VHDL20_DWMP_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 561656
wst04-VHDL20_DWMP_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:22 556874
wst04-VHDL20_DWPG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:26 357374
wst04-VHDL20_DWPG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:20 356861
wst04-VHDL20_DWPG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:31 357094
wst04-VHDL20_DWPG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:39 398034
wst04-VHDL20_DWPG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:26 353460
wst04-VHDL20_DWPG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 352156
wst04-VHDL20_DWPG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:31 353065
wst04-VHDL20_DWPG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:36 392219
wst04-VHDL20_DWPH_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:22 287842
wst04-VHDL20_DWPH_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:20 243155
wst04-VHDL20_DWPH_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:00:31 243409
wst04-VHDL20_DWPH_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:35 290618
wst04-VHDL20_DWPH_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:22 290154
wst04-VHDL20_DWPH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 245841
wst04-VHDL20_DWPH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:31 246399
wst04-VHDL20_DWPH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 292242
wst04-VHDL20_DWSG_261800-2602261800-omedes--0.pdf 26-Feb-2026 19:45:12 358386
wst04-VHDL20_DWSG_270200-2602270200-omedes--0.pdf 27-Feb-2026 03:45:12 358449
wst04-VHDL20_DWSG_270400-2602270400-omedes--0.pdf 27-Feb-2026 06:15:17 359224
wst04-VHDL20_DWSG_270800-2602270800-omedes--0.pdf 27-Feb-2026 09:45:12 353882
wst04-VHDL20_DWSG_271300-2602271300-omedes--0.pdf 27-Feb-2026 14:45:11 353571
wst04-VHDL20_DWSG_271800-2602271800-omedes--0.pdf 27-Feb-2026 19:45:12 353356
wst04-VHDL20_DWSG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:11 355227
wst04-VHDL20_DWSG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:17 356284
wst04-VHDL20_DWSG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 358120
wst04-VHDL20_DWSG_281300-2602281300-omedes--0.pdf 28-Feb-2026 14:45:12 357205