Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Nov-2025 12:25:09 4050
SXDL31_DWAV_201800 20-Nov-2025 16:04:35 6278
SXDL31_DWAV_210800 21-Nov-2025 08:34:21 14147
SXDL31_DWAV_211800 21-Nov-2025 18:01:35 6762
SXDL31_DWAV_220800 22-Nov-2025 09:32:30 9625
SXDL31_DWAV_LATEST 22-Nov-2025 09:32:30 9625
SXDL33_DWAV_210000 21-Nov-2025 11:01:39 11854
SXDL33_DWAV_220000 22-Nov-2025 11:12:19 7532
SXDL33_DWAV_LATEST 22-Nov-2025 11:12:19 7532
ber01-FWDL39_DWMS_211230-2511211230-dsw--0-ia5 21-Nov-2025 12:39:53 1555
ber01-FWDL39_DWMS_221230-2511221230-dsw--0-ia5 22-Nov-2025 12:58:33 985
ber01-VHDL13_DWEH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:28:16 3096
ber01-VHDL13_DWEH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:28:12 3177
ber01-VHDL13_DWEH_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:58:18 3240
ber01-VHDL13_DWEH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:28:17 3160
ber01-VHDL13_DWEH_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:31:09 3508
ber01-VHDL13_DWEH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:28:18 3163
ber01-VHDL13_DWEH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:28:12 3961
ber01-VHDL13_DWEH_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:58:17 3914
ber01-VHDL13_DWEH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:28:17 3914
ber01-VHDL13_DWEH_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 09:52:48 4791
ber01-VHDL13_DWHG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:10 3671
ber01-VHDL13_DWHG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 4145
ber01-VHDL13_DWHG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 4331
ber01-VHDL13_DWHG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:06 4475
ber01-VHDL13_DWHG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:07 3658
ber01-VHDL13_DWHG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3843
ber01-VHDL13_DWHG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:06 3846
ber01-VHDL13_DWHG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:10 4109
ber01-VHDL13_DWHH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:10 2996
ber01-VHDL13_DWHH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 3701
ber01-VHDL13_DWHH_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 3902
ber01-VHDL13_DWHH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:06 4020
ber01-VHDL13_DWHH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:07 3576
ber01-VHDL13_DWHH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3562
ber01-VHDL13_DWHH_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:06 3565
ber01-VHDL13_DWHH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:10 3652
ber01-VHDL13_DWLG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:02 2333
ber01-VHDL13_DWLG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:01 2435
ber01-VHDL13_DWLG_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:59:57 2610
ber01-VHDL13_DWLG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 3063
ber01-VHDL13_DWLG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 2785
ber01-VHDL13_DWLG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:02 3092
ber01-VHDL13_DWLG_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:59:56 3168
ber01-VHDL13_DWLG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 2956
ber01-VHDL13_DWLH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:02 2086
ber01-VHDL13_DWLH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:01 2221
ber01-VHDL13_DWLH_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:59:57 2338
ber01-VHDL13_DWLH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 2729
ber01-VHDL13_DWLH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 2539
ber01-VHDL13_DWLH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:02 2799
ber01-VHDL13_DWLH_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:59:56 2925
ber01-VHDL13_DWLH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 3019
ber01-VHDL13_DWLI_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:02 2174
ber01-VHDL13_DWLI_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:01 2284
ber01-VHDL13_DWLI_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:59:57 2403
ber01-VHDL13_DWLI_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 2859
ber01-VHDL13_DWLI_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 2693
ber01-VHDL13_DWLI_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:02 2999
ber01-VHDL13_DWLI_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:59:56 3100
ber01-VHDL13_DWLI_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:01 3040
ber01-VHDL13_DWMG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:05 3105
ber01-VHDL13_DWMG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 3342
ber01-VHDL13_DWMG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 3311
ber01-VHDL13_DWMG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 3530
ber01-VHDL13_DWMG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:07 2713
ber01-VHDL13_DWMG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3028
ber01-VHDL13_DWMG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:02 3039
ber01-VHDL13_DWMG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 2973
ber01-VHDL13_DWMO_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:05 2387
ber01-VHDL13_DWMO_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 2819
ber01-VHDL13_DWMO_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 2766
ber01-VHDL13_DWMO_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:40:37 2821
ber01-VHDL13_DWMO_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:07 2539
ber01-VHDL13_DWMO_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3024
ber01-VHDL13_DWMO_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:02 3024
ber01-VHDL13_DWMO_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 3151
ber01-VHDL13_DWMP_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:05 2877
ber01-VHDL13_DWMP_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 3222
ber01-VHDL13_DWMP_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 3151
ber01-VHDL13_DWMP_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:54:32 3575
ber01-VHDL13_DWMP_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:07 2822
ber01-VHDL13_DWMP_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3186
ber01-VHDL13_DWMP_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:02 3186
ber01-VHDL13_DWMP_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 3215
ber01-VHDL13_DWOG_201700-2511201700-dsw--0-ia5 20-Nov-2025 19:00:02 5226
ber01-VHDL13_DWOG_210300-2511210300-dsw--0-ia5 21-Nov-2025 04:00:03 5197
ber01-VHDL13_DWOG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:06 5442
ber01-VHDL13_DWOG_211700-2511211700-dsw--0-ia5 21-Nov-2025 19:00:02 4848
ber01-VHDL13_DWOG_211700_COR-2511211700-dsw--0-ia5 21-Nov-2025 01:16:07 5182
ber01-VHDL13_DWOG_220300-2511220300-dsw--0-ia5 22-Nov-2025 04:00:01 4631
ber01-VHDL13_DWOG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:10 4624
ber01-VHDL13_DWOH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:28:16 2757
ber01-VHDL13_DWOH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:28:12 2809
ber01-VHDL13_DWOH_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:58:12 2891
ber01-VHDL13_DWOH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:28:17 2790
ber01-VHDL13_DWOH_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:31:09 3226
ber01-VHDL13_DWOH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:28:18 2934
ber01-VHDL13_DWOH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:28:12 3075
ber01-VHDL13_DWOH_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:58:11 3094
ber01-VHDL13_DWOH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:28:17 3094
ber01-VHDL13_DWOH_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 11:04:51 4041
ber01-VHDL13_DWOI_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:28:12 3033
ber01-VHDL13_DWOI_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:28:12 2832
ber01-VHDL13_DWOI_210400-2511210400-dsw--0-ia5 21-Nov-2025 05:58:12 2872
ber01-VHDL13_DWOI_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:28:11 2827
ber01-VHDL13_DWOI_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:31:01 3111
ber01-VHDL13_DWOI_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:28:12 2833
ber01-VHDL13_DWOI_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:28:17 3335
ber01-VHDL13_DWOI_220400-2511220400-dsw--0-ia5 22-Nov-2025 05:58:17 3364
ber01-VHDL13_DWOI_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:28:12 3370
ber01-VHDL13_DWOI_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 09:52:48 4237
ber01-VHDL13_DWON_201530-2511201530-dsw--0-ia5 20-Nov-2025 15:30:18 4215
ber01-VHDL13_DWON_201754-2511201754-dsw--0-ia5 20-Nov-2025 17:54:32 4183
ber01-VHDL13_DWON_201806-2511201806-dsw--0-ia5 20-Nov-2025 18:06:22 4183
ber01-VHDL13_DWON_202036-2511202036-dsw--0-ia5 20-Nov-2025 20:36:52 4008
ber01-VHDL13_DWON_202334-2511202334-dsw--0-ia5 20-Nov-2025 23:34:50 3791
ber01-VHDL13_DWON_210115-2511210115-dsw--0-ia5 21-Nov-2025 01:15:47 3791
ber01-VHDL13_DWON_210341-2511210341-dsw--0-ia5 21-Nov-2025 03:41:06 3791
ber01-VHDL13_DWON_210620-2511210620-dsw--0-ia5 21-Nov-2025 06:20:52 4453
ber01-VHDL13_DWON_210710-2511210710-dsw--0-ia5 21-Nov-2025 07:10:27 4453
ber01-VHDL13_DWON_210858-2511210858-dsw--0-ia5 21-Nov-2025 08:58:52 4453
ber01-VHDL13_DWON_211029-2511211029-dsw--0-ia5 21-Nov-2025 10:29:47 4453
ber01-VHDL13_DWON_211537-2511211537-dsw--0-ia5 21-Nov-2025 15:37:50 3788
ber01-VHDL13_DWON_211833-2511211833-dsw--0-ia5 21-Nov-2025 18:33:16 3792
ber01-VHDL13_DWON_212353-2511212353-dsw--0-ia5 21-Nov-2025 23:53:41 3609
ber01-VHDL13_DWON_220146-2511220146-dsw--0-ia5 22-Nov-2025 01:46:27 3723
ber01-VHDL13_DWON_220431-2511220431-dsw--0-ia5 22-Nov-2025 04:31:51 3723
ber01-VHDL13_DWON_220620-2511220620-dsw--0-ia5 22-Nov-2025 06:20:22 4464
ber01-VHDL13_DWON_220710-2511220710-dsw--0-ia5 22-Nov-2025 07:10:27 4444
ber01-VHDL13_DWPG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:02 1876
ber01-VHDL13_DWPG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:01 2030
ber01-VHDL13_DWPG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:01 2211
ber01-VHDL13_DWPG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 2118
ber01-VHDL13_DWPG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 1924
ber01-VHDL13_DWPG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:02 2035
ber01-VHDL13_DWPG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:02 2227
ber01-VHDL13_DWPG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 2324
ber01-VHDL13_DWPH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:02 2728
ber01-VHDL13_DWPH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:01 2611
ber01-VHDL13_DWPH_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:01 2663
ber01-VHDL13_DWPH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 2490
ber01-VHDL13_DWPH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 2270
ber01-VHDL13_DWPH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:02 2423
ber01-VHDL13_DWPH_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:02 2549
ber01-VHDL13_DWPH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 2625
ber01-VHDL13_DWSG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:30:05 3313
ber01-VHDL13_DWSG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:30:11 3685
ber01-VHDL13_DWSG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 3686
ber01-VHDL13_DWSG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:30:02 3542
ber01-VHDL13_DWSG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:30:02 3599
ber01-VHDL13_DWSG_211800_COR-2511211800-dsw--0-ia5 21-Nov-2025 19:31:33 3186
ber01-VHDL13_DWSG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:30:10 3226
ber01-VHDL13_DWSG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:06 3385
ber01-VHDL13_DWSG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:30:02 3732
ber01-VHDL17_DWOG_211200-2511211200-dsw--0-ia5 21-Nov-2025 12:55:47 3701
ber01-VHDL17_DWOG_221200-2511221200-dsw--0-ia5 22-Nov-2025 12:40:17 3471
swis2-VHDL20_DWEG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:45:01 3210
swis2-VHDL20_DWEG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:45:02 3106
swis2-VHDL20_DWEG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:15:02 3232
swis2-VHDL20_DWEG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:45:06 3334
swis2-VHDL20_DWEG_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:30:56 3405
swis2-VHDL20_DWEG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:45:04 3302
swis2-VHDL20_DWEG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:45:06 3445
swis2-VHDL20_DWEG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:15:06 3438
swis2-VHDL20_DWEG_220400_COR-2511220400-dsw--0-ia5 22-Nov-2025 10:02:13 4387
swis2-VHDL20_DWEG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:45:04 3514
swis2-VHDL20_DWEG_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 11:06:20 5318
swis2-VHDL20_DWEH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:45:01 3605
swis2-VHDL20_DWEH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:45:02 3551
swis2-VHDL20_DWEH_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:15:02 3591
swis2-VHDL20_DWEH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:45:06 4071
swis2-VHDL20_DWEH_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:30:56 3686
swis2-VHDL20_DWEH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:45:04 3536
swis2-VHDL20_DWEH_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:45:06 4487
swis2-VHDL20_DWEH_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:15:06 4633
swis2-VHDL20_DWEH_220400_COR-2511220400-dsw--0-ia5 22-Nov-2025 10:03:31 5510
swis2-VHDL20_DWEH_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:45:10 4722
swis2-VHDL20_DWEH_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 10:06:36 6462
swis2-VHDL20_DWEI_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:45:01 3511
swis2-VHDL20_DWEI_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:45:02 3156
swis2-VHDL20_DWEI_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:15:02 3244
swis2-VHDL20_DWEI_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:45:06 3576
swis2-VHDL20_DWEI_210800_COR-2511210800-dsw--0-ia5 21-Nov-2025 10:30:56 3290
swis2-VHDL20_DWEI_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:45:04 3205
swis2-VHDL20_DWEI_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:45:06 3651
swis2-VHDL20_DWEI_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:15:06 4041
swis2-VHDL20_DWEI_220400_COR-2511220400-dsw--0-ia5 22-Nov-2025 10:04:02 4908
swis2-VHDL20_DWEI_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:45:10 4139
swis2-VHDL20_DWEI_220800_COR-2511220800-dsw--0-ia5 22-Nov-2025 10:06:22 5863
swis2-VHDL20_DWHG_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:45:01 3854
swis2-VHDL20_DWHG_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:45:07 4331
swis2-VHDL20_DWHG_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 4514
swis2-VHDL20_DWHG_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:45:01 5207
swis2-VHDL20_DWHG_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:45:04 3841
swis2-VHDL20_DWHG_220200-2511220200-dsw--0-ia5 22-Nov-2025 03:45:03 4029
swis2-VHDL20_DWHG_220400-2511220400-dsw--0-ia5 22-Nov-2025 06:00:06 4029
swis2-VHDL20_DWHG_220800-2511220800-dsw--0-ia5 22-Nov-2025 09:45:10 4799
swis2-VHDL20_DWHH_201800-2511201800-dsw--0-ia5 20-Nov-2025 19:45:06 3182
swis2-VHDL20_DWHH_210200-2511210200-dsw--0-ia5 21-Nov-2025 03:45:07 3887
swis2-VHDL20_DWHH_210400-2511210400-dsw--0-ia5 21-Nov-2025 06:00:06 4088
swis2-VHDL20_DWHH_210800-2511210800-dsw--0-ia5 21-Nov-2025 09:45:01 4724
swis2-VHDL20_DWHH_211800-2511211800-dsw--0-ia5 21-Nov-2025 19:45:04 3762
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wst04-VHDL20_DWEG_210800_COR-2511210800-omedes-..> 21-Nov-2025 10:31:09 230042
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wst04-VHDL20_DWEG_220800_COR-2511220800-omedes-..> 22-Nov-2025 11:05:48 229786
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wst04-VHDL20_DWEH_210800_COR-2511210800-omedes-..> 21-Nov-2025 10:31:09 229258
wst04-VHDL20_DWEH_211800-2511211800-omedes--0.pdf 21-Nov-2025 19:45:16 230077
wst04-VHDL20_DWEH_220200-2511220200-omedes--0.pdf 22-Nov-2025 03:45:12 231594
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wst04-VHDL20_DWEH_220800_COR-2511220800-omedes-..> 22-Nov-2025 10:14:12 233250
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wst04-VHDL20_DWEI_210200-2511210200-omedes--0.pdf 21-Nov-2025 03:45:21 320506
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wst04-VHDL20_DWEI_210800_COR-2511210800-omedes-..> 21-Nov-2025 10:31:11 319334
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wst04-VHDL20_DWEI_220200-2511220200-omedes--0.pdf 22-Nov-2025 03:45:16 321169
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wst04-VHDL20_DWSG_220200-2511220200-omedes--0.pdf 22-Nov-2025 03:45:16 324191
wst04-VHDL20_DWSG_220400-2511220400-omedes--0.pdf 22-Nov-2025 06:15:16 324385
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