Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Dec-2025 14:04:33 3968
FPDL13_DWMZ_190600 19-Dec-2025 14:43:11 7449
SXDL31_DWAV_181800 18-Dec-2025 16:45:25 9792
SXDL31_DWAV_190800 19-Dec-2025 07:41:43 7462
SXDL31_DWAV_191800 19-Dec-2025 16:48:43 7624
SXDL31_DWAV_200800 20-Dec-2025 09:06:33 12820
SXDL31_DWAV_LATEST 20-Dec-2025 09:06:33 12820
SXDL33_DWAV_180000 18-Dec-2025 12:23:53 12644
SXDL33_DWAV_190000 19-Dec-2025 11:21:29 12104
SXDL33_DWAV_200000 20-Dec-2025 10:11:53 9222
SXDL33_DWAV_LATEST 20-Dec-2025 10:11:53 9222
ber01-FWDL39_DWMS_181230-2512181230-dsw--0-ia5 18-Dec-2025 12:15:51 1419
ber01-FWDL39_DWMS_191230-2512191230-dsw--0-ia5 19-Dec-2025 11:58:36 1620
ber01-VHDL13_DWEH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2341
ber01-VHDL13_DWEH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:11 2182
ber01-VHDL13_DWEH_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:17 2304
ber01-VHDL13_DWEH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:17 2395
ber01-VHDL13_DWEH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:28:17 2102
ber01-VHDL13_DWEH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:28:12 2310
ber01-VHDL13_DWEH_200400-2512200400-dsw--0-ia5 20-Dec-2025 05:58:11 2592
ber01-VHDL13_DWEH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:16 2592
ber01-VHDL13_DWHG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2871
ber01-VHDL13_DWHG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3257
ber01-VHDL13_DWHG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3481
ber01-VHDL13_DWHG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 2996
ber01-VHDL13_DWHG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:09 2717
ber01-VHDL13_DWHG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 2944
ber01-VHDL13_DWHG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:07 2964
ber01-VHDL13_DWHG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 2957
ber01-VHDL13_DWHH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 2645
ber01-VHDL13_DWHH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 2858
ber01-VHDL13_DWHH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 2888
ber01-VHDL13_DWHH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 2495
ber01-VHDL13_DWHH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:09 2209
ber01-VHDL13_DWHH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 2594
ber01-VHDL13_DWHH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 2607
ber01-VHDL13_DWHH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 2675
ber01-VHDL13_DWLG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2298
ber01-VHDL13_DWLG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2364
ber01-VHDL13_DWLG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2407
ber01-VHDL13_DWLG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2582
ber01-VHDL13_DWLG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2219
ber01-VHDL13_DWLG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 2361
ber01-VHDL13_DWLG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:07 2695
ber01-VHDL13_DWLG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2680
ber01-VHDL13_DWLH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2141
ber01-VHDL13_DWLH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2210
ber01-VHDL13_DWLH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2240
ber01-VHDL13_DWLH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2329
ber01-VHDL13_DWLH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2019
ber01-VHDL13_DWLH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 2231
ber01-VHDL13_DWLH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:07 2205
ber01-VHDL13_DWLH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2190
ber01-VHDL13_DWLI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2182
ber01-VHDL13_DWLI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 2136
ber01-VHDL13_DWLI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2095
ber01-VHDL13_DWLI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 2061
ber01-VHDL13_DWLI_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2090
ber01-VHDL13_DWLI_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 2322
ber01-VHDL13_DWLI_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 2407
ber01-VHDL13_DWLI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2435
ber01-VHDL13_DWMG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3130
ber01-VHDL13_DWMG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3523
ber01-VHDL13_DWMG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 3526
ber01-VHDL13_DWMG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3691
ber01-VHDL13_DWMG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 3181
ber01-VHDL13_DWMG_191800_COR-2512191800-dsw--0-ia5 20-Dec-2025 01:09:47 3376
ber01-VHDL13_DWMG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:02 3624
ber01-VHDL13_DWMG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:03 3626
ber01-VHDL13_DWMG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3395
ber01-VHDL13_DWMO_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 3133
ber01-VHDL13_DWMO_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3571
ber01-VHDL13_DWMO_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 3564
ber01-VHDL13_DWMO_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3257
ber01-VHDL13_DWMO_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2798
ber01-VHDL13_DWMO_191800_COR-2512191800-dsw--0-ia5 20-Dec-2025 00:53:32 2995
ber01-VHDL13_DWMO_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:02 3709
ber01-VHDL13_DWMO_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:03 3708
ber01-VHDL13_DWMO_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3442
ber01-VHDL13_DWMP_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 2451
ber01-VHDL13_DWMP_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3100
ber01-VHDL13_DWMP_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:02 2940
ber01-VHDL13_DWMP_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:13 3065
ber01-VHDL13_DWMP_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2756
ber01-VHDL13_DWMP_191800_COR-2512191800-dsw--0-ia5 20-Dec-2025 00:53:46 2972
ber01-VHDL13_DWMP_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:02 3554
ber01-VHDL13_DWMP_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:03 3552
ber01-VHDL13_DWMP_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3186
ber01-VHDL13_DWOG_181700-2512181700-dsw--0-ia5 18-Dec-2025 19:00:02 4110
ber01-VHDL13_DWOG_190300-2512190300-dsw--0-ia5 19-Dec-2025 04:00:06 4353
ber01-VHDL13_DWOG_190800-2512190800-dsw--0-ia5 19-Dec-2025 11:40:11 4010
ber01-VHDL13_DWOG_191700-2512191700-dsw--0-ia5 19-Dec-2025 19:00:02 3518
ber01-VHDL13_DWOG_200300-2512200300-dsw--0-ia5 20-Dec-2025 04:00:01 4035
ber01-VHDL13_DWOG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3915
ber01-VHDL13_DWOH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:16 2383
ber01-VHDL13_DWOH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:11 2130
ber01-VHDL13_DWOH_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:11 2178
ber01-VHDL13_DWOH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:17 2376
ber01-VHDL13_DWOH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:28:11 2109
ber01-VHDL13_DWOH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:28:12 2272
ber01-VHDL13_DWOH_200400-2512200400-dsw--0-ia5 20-Dec-2025 05:58:17 2393
ber01-VHDL13_DWOH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:16 2393
ber01-VHDL13_DWOI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:28:12 2428
ber01-VHDL13_DWOI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:28:17 2203
ber01-VHDL13_DWOI_190400-2512190400-dsw--0-ia5 19-Dec-2025 05:58:17 2137
ber01-VHDL13_DWOI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:28:13 2383
ber01-VHDL13_DWOI_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:28:11 1990
ber01-VHDL13_DWOI_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:28:16 2121
ber01-VHDL13_DWOI_200400-2512200400-dsw--0-ia5 20-Dec-2025 05:58:17 2329
ber01-VHDL13_DWOI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:12 2335
ber01-VHDL13_DWON_181551-2512181551-dsw--0-ia5 18-Dec-2025 15:51:41 3492
ber01-VHDL13_DWON_181731-2512181731-dsw--0-ia5 18-Dec-2025 17:31:45 3624
ber01-VHDL13_DWON_190152-2512190152-dsw--0-ia5 19-Dec-2025 01:52:31 4006
ber01-VHDL13_DWON_190333-2512190333-dsw--0-ia5 19-Dec-2025 03:33:55 4006
ber01-VHDL13_DWON_190627-2512190627-dsw--0-ia5 19-Dec-2025 06:27:27 4028
ber01-VHDL13_DWON_190709-2512190709-dsw--0-ia5 19-Dec-2025 07:09:26 4298
ber01-VHDL13_DWON_191125-2512191125-dsw--0-ia5 19-Dec-2025 11:25:46 4282
ber01-VHDL13_DWON_191139-2512191139-dsw--0-ia5 19-Dec-2025 11:39:43 4282
ber01-VHDL13_DWON_191504-2512191504-dsw--0-ia5 19-Dec-2025 15:04:42 3217
ber01-VHDL13_DWON_191745-2512191745-dsw--0-ia5 19-Dec-2025 17:46:01 3187
ber01-VHDL13_DWON_192032-2512192032-dsw--0-ia5 19-Dec-2025 20:32:06 3172
ber01-VHDL13_DWON_192329-2512192329-dsw--0-ia5 19-Dec-2025 23:29:47 3744
ber01-VHDL13_DWON_200406-2512200406-dsw--0-ia5 20-Dec-2025 04:06:43 3744
ber01-VHDL13_DWON_200629-2512200629-dsw--0-ia5 20-Dec-2025 06:29:26 3812
ber01-VHDL13_DWON_200725-2512200725-dsw--0-ia5 20-Dec-2025 07:25:23 3767
ber01-VHDL13_DWPG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1788
ber01-VHDL13_DWPG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 1803
ber01-VHDL13_DWPG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 1843
ber01-VHDL13_DWPG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 1865
ber01-VHDL13_DWPG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 1481
ber01-VHDL13_DWPG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 1757
ber01-VHDL13_DWPG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 1767
ber01-VHDL13_DWPG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 1868
ber01-VHDL13_DWPH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:02 1876
ber01-VHDL13_DWPH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:02 1910
ber01-VHDL13_DWPH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:00 2032
ber01-VHDL13_DWPH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 1852
ber01-VHDL13_DWPH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 1609
ber01-VHDL13_DWPH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:06 1957
ber01-VHDL13_DWPH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:07 1890
ber01-VHDL13_DWPH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2051
ber01-VHDL13_DWSG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:30:08 3203
ber01-VHDL13_DWSG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:30:06 3511
ber01-VHDL13_DWSG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3523
ber01-VHDL13_DWSG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:30:02 3524
ber01-VHDL13_DWSG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:30:02 2631
ber01-VHDL13_DWSG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:30:02 3522
ber01-VHDL13_DWSG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 3442
ber01-VHDL13_DWSG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 3345
ber01-VHDL17_DWOG_181200-2512181200-dsw--0-ia5 18-Dec-2025 12:55:31 3733
ber01-VHDL17_DWOG_191200-2512191200-dsw--0-ia5 19-Dec-2025 12:58:06 3449
ber01-VHDL17_DWOG_201200-2512201200-dsw--0-ia5 20-Dec-2025 11:44:31 3168
swis2-VHDL20_DWEG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2709
swis2-VHDL20_DWEG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2406
swis2-VHDL20_DWEG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2505
swis2-VHDL20_DWEG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2854
swis2-VHDL20_DWEG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2435
swis2-VHDL20_DWEG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2548
swis2-VHDL20_DWEG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:02 2716
swis2-VHDL20_DWEG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3356
swis2-VHDL20_DWEH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2695
swis2-VHDL20_DWEH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2503
swis2-VHDL20_DWEH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2636
swis2-VHDL20_DWEH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 2898
swis2-VHDL20_DWEH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2456
swis2-VHDL20_DWEH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2631
swis2-VHDL20_DWEH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:07 2927
swis2-VHDL20_DWEH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3563
swis2-VHDL20_DWEI_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:06 2780
swis2-VHDL20_DWEI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2496
swis2-VHDL20_DWEI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:07 2494
swis2-VHDL20_DWEI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2908
swis2-VHDL20_DWEI_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2341
swis2-VHDL20_DWEI_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2413
swis2-VHDL20_DWEI_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:07 2683
swis2-VHDL20_DWEI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3201
swis2-VHDL20_DWHG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3054
swis2-VHDL20_DWHG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3443
swis2-VHDL20_DWHG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3664
swis2-VHDL20_DWHG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3527
swis2-VHDL20_DWHG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2900
swis2-VHDL20_DWHG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 3130
swis2-VHDL20_DWHG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 3147
swis2-VHDL20_DWHG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3484
swis2-VHDL20_DWHH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2831
swis2-VHDL20_DWHH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3044
swis2-VHDL20_DWHH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:06 3074
swis2-VHDL20_DWHH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3038
swis2-VHDL20_DWHH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2395
swis2-VHDL20_DWHH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2780
swis2-VHDL20_DWHH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:08 2793
swis2-VHDL20_DWHH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3214
swis2-VHDL20_DWLG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2756
swis2-VHDL20_DWLG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2825
swis2-VHDL20_DWLG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2745
swis2-VHDL20_DWLG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 3062
swis2-VHDL20_DWLG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:04 2557
swis2-VHDL20_DWLG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2702
swis2-VHDL20_DWLG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:16 3033
swis2-VHDL20_DWLG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 3160
swis2-VHDL20_DWLH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2487
swis2-VHDL20_DWLH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2559
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swis2-VHDL20_DWLH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2364
swis2-VHDL20_DWLH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2579
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swis2-VHDL20_DWLI_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2555
swis2-VHDL20_DWLI_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2435
swis2-VHDL20_DWLI_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2542
swis2-VHDL20_DWLI_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2430
swis2-VHDL20_DWLI_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2665
swis2-VHDL20_DWLI_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:16 2747
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swis2-VHDL20_DWMG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 3934
swis2-VHDL20_DWMG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3952
swis2-VHDL20_DWMG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 4573
swis2-VHDL20_DWMG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:04 3777
swis2-VHDL20_DWMG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 4169
swis2-VHDL20_DWMG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:02 4234
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swis2-VHDL20_DWMO_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3552
swis2-VHDL20_DWMO_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 4001
swis2-VHDL20_DWMO_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3983
swis2-VHDL20_DWMO_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 4145
swis2-VHDL20_DWMO_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 3399
swis2-VHDL20_DWMO_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 4255
swis2-VHDL20_DWMO_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:02 4322
swis2-VHDL20_DWMO_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 4090
swis2-VHDL20_DWMP_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2872
swis2-VHDL20_DWMP_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:03 3528
swis2-VHDL20_DWMP_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3368
swis2-VHDL20_DWMP_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:06 3711
swis2-VHDL20_DWMP_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 3261
swis2-VHDL20_DWMP_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 4098
swis2-VHDL20_DWMP_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:02 4097
swis2-VHDL20_DWMP_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3838
swis2-VHDL20_DWPG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2247
swis2-VHDL20_DWPG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2132
swis2-VHDL20_DWPG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2169
swis2-VHDL20_DWPG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2324
swis2-VHDL20_DWPG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 1940
swis2-VHDL20_DWPG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2086
swis2-VHDL20_DWPG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:16 2093
swis2-VHDL20_DWPG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2326
swis2-VHDL20_DWPH_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 2335
swis2-VHDL20_DWPH_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 2238
swis2-VHDL20_DWPH_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:00:12 2360
swis2-VHDL20_DWPH_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 2311
swis2-VHDL20_DWPH_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 2068
swis2-VHDL20_DWPH_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 2285
swis2-VHDL20_DWPH_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:00:16 2218
swis2-VHDL20_DWPH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2509
swis2-VHDL20_DWSG_181300-2512181300-dsw--0-ia5 18-Dec-2025 14:45:04 3632
swis2-VHDL20_DWSG_181800-2512181800-dsw--0-ia5 18-Dec-2025 19:45:04 3645
swis2-VHDL20_DWSG_190200-2512190200-dsw--0-ia5 19-Dec-2025 03:45:08 3942
swis2-VHDL20_DWSG_190400-2512190400-dsw--0-ia5 19-Dec-2025 06:15:02 3963
swis2-VHDL20_DWSG_190800-2512190800-dsw--0-ia5 19-Dec-2025 09:45:02 4194
swis2-VHDL20_DWSG_191300-2512191300-dsw--0-ia5 19-Dec-2025 14:45:09 3404
swis2-VHDL20_DWSG_191800-2512191800-dsw--0-ia5 19-Dec-2025 19:45:03 3071
swis2-VHDL20_DWSG_200200-2512200200-dsw--0-ia5 20-Dec-2025 03:45:05 3951
swis2-VHDL20_DWSG_200400-2512200400-dsw--0-ia5 20-Dec-2025 06:15:02 3882
swis2-VHDL20_DWSG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 4071
wst04-VHDL20_DWEG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 220825
wst04-VHDL20_DWEG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 220578
wst04-VHDL20_DWEG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:27 220112
wst04-VHDL20_DWEG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:23 222618
wst04-VHDL20_DWEG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:10 221118
wst04-VHDL20_DWEG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:13 221431
wst04-VHDL20_DWEG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:23 221064
wst04-VHDL20_DWEG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 226964
wst04-VHDL20_DWEH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 220219
wst04-VHDL20_DWEH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 220709
wst04-VHDL20_DWEH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:21 220462
wst04-VHDL20_DWEH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:23 221879
wst04-VHDL20_DWEH_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:10 220522
wst04-VHDL20_DWEH_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:13 221249
wst04-VHDL20_DWEH_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:27 220967
wst04-VHDL20_DWEH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 224778
wst04-VHDL20_DWEI_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 300842
wst04-VHDL20_DWEI_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 300189
wst04-VHDL20_DWEI_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:27 300114
wst04-VHDL20_DWEI_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 305476
wst04-VHDL20_DWEI_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:16 304007
wst04-VHDL20_DWEI_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:17 304090
wst04-VHDL20_DWEI_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:27 304192
wst04-VHDL20_DWEI_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 312603
wst04-VHDL20_DWHG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 295720
wst04-VHDL20_DWHG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 295883
wst04-VHDL20_DWHG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:12 296270
wst04-VHDL20_DWHG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 300688
wst04-VHDL20_DWHG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:22 298770
wst04-VHDL20_DWHG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:13 299158
wst04-VHDL20_DWHG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:12 299209
wst04-VHDL20_DWHG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 302096
wst04-VHDL20_DWHH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 288719
wst04-VHDL20_DWHH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:12 288292
wst04-VHDL20_DWHH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:12 288050
wst04-VHDL20_DWHH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 305596
wst04-VHDL20_DWHH_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:22 304910
wst04-VHDL20_DWHH_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:13 304842
wst04-VHDL20_DWHH_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:12 223885
wst04-VHDL20_DWHH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 286983
wst04-VHDL20_DWLG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 287061
wst04-VHDL20_DWLG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 287364
wst04-VHDL20_DWLG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 286426
wst04-VHDL20_DWLG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 291268
wst04-VHDL20_DWLG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:26 290891
wst04-VHDL20_DWLG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:25 291253
wst04-VHDL20_DWLG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:41 291353
wst04-VHDL20_DWLG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 299110
wst04-VHDL20_DWLH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 287587
wst04-VHDL20_DWLH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 287484
wst04-VHDL20_DWLH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 287114
wst04-VHDL20_DWLH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 293426
wst04-VHDL20_DWLH_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:26 292872
wst04-VHDL20_DWLH_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:25 292998
wst04-VHDL20_DWLH_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:41 293064
wst04-VHDL20_DWLH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 295194
wst04-VHDL20_DWLI_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:26 289298
wst04-VHDL20_DWLI_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 289043
wst04-VHDL20_DWLI_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:41 287819
wst04-VHDL20_DWLI_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:31 295173
wst04-VHDL20_DWLI_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:22 294838
wst04-VHDL20_DWLI_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:25 295395
wst04-VHDL20_DWLI_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:41 295177
wst04-VHDL20_DWLI_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 299737
wst04-VHDL20_DWMG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 480834
wst04-VHDL20_DWMG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 481433
wst04-VHDL20_DWMG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:23 481629
wst04-VHDL20_DWMG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 476673
wst04-VHDL20_DWMG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:16 393483
wst04-VHDL20_DWMG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:17 393766
wst04-VHDL20_DWMG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:21 474973
wst04-VHDL20_DWMG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 496853
wst04-VHDL20_DWMO_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 390194
wst04-VHDL20_DWMO_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 391039
wst04-VHDL20_DWMO_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:17 391874
wst04-VHDL20_DWMO_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:11 395498
wst04-VHDL20_DWMO_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:16 394261
wst04-VHDL20_DWMO_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:21 394983
wst04-VHDL20_DWMO_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:21 395659
wst04-VHDL20_DWMO_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:11 404089
wst04-VHDL20_DWMP_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:16 503091
wst04-VHDL20_DWMP_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 503760
wst04-VHDL20_DWMP_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:23 504529
wst04-VHDL20_DWMP_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:17 491753
wst04-VHDL20_DWMP_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:16 490848
wst04-VHDL20_DWMP_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:21 489344
wst04-VHDL20_DWMP_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:21 490687
wst04-VHDL20_DWMP_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 514439
wst04-VHDL20_DWPG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 292042
wst04-VHDL20_DWPG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:26 291881
wst04-VHDL20_DWPG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:31 292460
wst04-VHDL20_DWPG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 347658
wst04-VHDL20_DWPG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:26 302789
wst04-VHDL20_DWPG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:21 302633
wst04-VHDL20_DWPG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:32 302655
wst04-VHDL20_DWPG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 344333
wst04-VHDL20_DWPH_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:22 259580
wst04-VHDL20_DWPH_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:22 214800
wst04-VHDL20_DWPH_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:00:31 215275
wst04-VHDL20_DWPH_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:27 266156
wst04-VHDL20_DWPH_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:22 266001
wst04-VHDL20_DWPH_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:21 222081
wst04-VHDL20_DWPH_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:00:32 221814
wst04-VHDL20_DWPH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 264053
wst04-VHDL20_DWSG_181300-2512181300-omedes--0.pdf 18-Dec-2025 14:45:12 312687
wst04-VHDL20_DWSG_181800-2512181800-omedes--0.pdf 18-Dec-2025 19:45:12 313445
wst04-VHDL20_DWSG_190200-2512190200-omedes--0.pdf 19-Dec-2025 03:45:16 313201
wst04-VHDL20_DWSG_190400-2512190400-omedes--0.pdf 19-Dec-2025 06:15:17 313407
wst04-VHDL20_DWSG_190800-2512190800-omedes--0.pdf 19-Dec-2025 09:45:11 306268
wst04-VHDL20_DWSG_191300-2512191300-omedes--0.pdf 19-Dec-2025 14:45:12 305640
wst04-VHDL20_DWSG_191800-2512191800-omedes--0.pdf 19-Dec-2025 19:45:12 304898
wst04-VHDL20_DWSG_200200-2512200200-omedes--0.pdf 20-Dec-2025 03:45:17 306249
wst04-VHDL20_DWSG_200400-2512200400-omedes--0.pdf 20-Dec-2025 06:15:17 306840
wst04-VHDL20_DWSG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:11 315201