Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_080600 08-Feb-2026 14:23:04 3142
FPDL13_DWMZ_090600 09-Feb-2026 15:03:08 3581
SXDL31_DWAV_081800 08-Feb-2026 18:16:19 8172
SXDL31_DWAV_090800 09-Feb-2026 08:37:07 9981
SXDL31_DWAV_091800 09-Feb-2026 17:39:49 7288
SXDL31_DWAV_100800 10-Feb-2026 08:32:20 15242
SXDL31_DWAV_LATEST 10-Feb-2026 08:32:20 15242
SXDL33_DWAV_080000 08-Feb-2026 11:07:39 9434
SXDL33_DWAV_090000 09-Feb-2026 09:28:44 10288
SXDL33_DWAV_LATEST 09-Feb-2026 09:28:44 10288
ber01-FWDL39_DWMS_081230-2602081230-dsw--0-ia5 08-Feb-2026 12:32:26 1438
ber01-FWDL39_DWMS_091230-2602091230-dsw--0-ia5 09-Feb-2026 13:23:31 2341
ber01-VHDL13_DWEH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:28:16 2520
ber01-VHDL13_DWEH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:28:12 2644
ber01-VHDL13_DWEH_090400-2602090400-dsw--0-ia5 09-Feb-2026 05:58:17 2647
ber01-VHDL13_DWEH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:28:16 2687
ber01-VHDL13_DWEH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:28:17 2479
ber01-VHDL13_DWEH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:28:11 2477
ber01-VHDL13_DWEH_100400-2602100400-dsw--0-ia5 10-Feb-2026 05:58:11 2432
ber01-VHDL13_DWEH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:28:16 2435
ber01-VHDL13_DWEH_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:51 2447
ber01-VHDL13_DWHG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:05 3121
ber01-VHDL13_DWHG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:10 3556
ber01-VHDL13_DWHG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 3698
ber01-VHDL13_DWHG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:08 3819
ber01-VHDL13_DWHG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 3416
ber01-VHDL13_DWHG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:07 3921
ber01-VHDL13_DWHG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:08 3964
ber01-VHDL13_DWHG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:08 3678
ber01-VHDL13_DWHH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:05 2345
ber01-VHDL13_DWHH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:10 2751
ber01-VHDL13_DWHH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2711
ber01-VHDL13_DWHH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:08 2814
ber01-VHDL13_DWHH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2521
ber01-VHDL13_DWHH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:07 3700
ber01-VHDL13_DWHH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:08 3713
ber01-VHDL13_DWHH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:08 3572
ber01-VHDL13_DWLG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 3056
ber01-VHDL13_DWLG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 3153
ber01-VHDL13_DWLG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 3231
ber01-VHDL13_DWLG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3157
ber01-VHDL13_DWLG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 3087
ber01-VHDL13_DWLG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3325
ber01-VHDL13_DWLG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:02 3283
ber01-VHDL13_DWLG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:08 3287
ber01-VHDL13_DWLH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2648
ber01-VHDL13_DWLH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 2757
ber01-VHDL13_DWLH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2836
ber01-VHDL13_DWLH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 2841
ber01-VHDL13_DWLH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2578
ber01-VHDL13_DWLH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 2777
ber01-VHDL13_DWLH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:02 2774
ber01-VHDL13_DWLH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 2781
ber01-VHDL13_DWLI_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2535
ber01-VHDL13_DWLI_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 2713
ber01-VHDL13_DWLI_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2731
ber01-VHDL13_DWLI_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 2600
ber01-VHDL13_DWLI_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2510
ber01-VHDL13_DWLI_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 2960
ber01-VHDL13_DWLI_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:02 2932
ber01-VHDL13_DWLI_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 2847
ber01-VHDL13_DWMG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2703
ber01-VHDL13_DWMG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 3205
ber01-VHDL13_DWMG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:02 3222
ber01-VHDL13_DWMG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3445
ber01-VHDL13_DWMG_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:16 3693
ber01-VHDL13_DWMG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 3152
ber01-VHDL13_DWMG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3551
ber01-VHDL13_DWMG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:06 3694
ber01-VHDL13_DWMG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 4458
ber01-VHDL13_DWMO_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 3071
ber01-VHDL13_DWMO_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 3165
ber01-VHDL13_DWMO_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:02 3154
ber01-VHDL13_DWMO_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3247
ber01-VHDL13_DWMO_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:26 3347
ber01-VHDL13_DWMO_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2950
ber01-VHDL13_DWMO_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3321
ber01-VHDL13_DWMO_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:06 3310
ber01-VHDL13_DWMO_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 3666
ber01-VHDL13_DWMP_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 3434
ber01-VHDL13_DWMP_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 3541
ber01-VHDL13_DWMP_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:02 3532
ber01-VHDL13_DWMP_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3532
ber01-VHDL13_DWMP_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:36 3771
ber01-VHDL13_DWMP_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 3355
ber01-VHDL13_DWMP_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3757
ber01-VHDL13_DWMP_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:06 3897
ber01-VHDL13_DWMP_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 4792
ber01-VHDL13_DWOG_081700-2602081700-dsw--0-ia5 08-Feb-2026 19:00:07 4196
ber01-VHDL13_DWOG_090300-2602090300-dsw--0-ia5 09-Feb-2026 04:00:01 4936
ber01-VHDL13_DWOG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 4986
ber01-VHDL13_DWOG_091700-2602091700-dsw--0-ia5 09-Feb-2026 19:00:02 4352
ber01-VHDL13_DWOG_100300-2602100300-dsw--0-ia5 10-Feb-2026 04:00:01 5412
ber01-VHDL13_DWOG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 5965
ber01-VHDL13_DWOH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:28:16 2350
ber01-VHDL13_DWOH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:28:12 2559
ber01-VHDL13_DWOH_090400-2602090400-dsw--0-ia5 09-Feb-2026 05:58:17 2588
ber01-VHDL13_DWOH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:28:12 2514
ber01-VHDL13_DWOH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:28:11 2270
ber01-VHDL13_DWOH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:28:11 2447
ber01-VHDL13_DWOH_100400-2602100400-dsw--0-ia5 10-Feb-2026 05:58:11 2403
ber01-VHDL13_DWOH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:28:16 2403
ber01-VHDL13_DWOH_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:51 2567
ber01-VHDL13_DWOI_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:28:12 2153
ber01-VHDL13_DWOI_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:28:16 2484
ber01-VHDL13_DWOI_090400-2602090400-dsw--0-ia5 09-Feb-2026 05:58:11 2481
ber01-VHDL13_DWOI_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:28:16 2812
ber01-VHDL13_DWOI_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:28:11 2645
ber01-VHDL13_DWOI_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:28:17 2404
ber01-VHDL13_DWOI_100400-2602100400-dsw--0-ia5 10-Feb-2026 05:58:18 2462
ber01-VHDL13_DWOI_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:28:11 2468
ber01-VHDL13_DWOI_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:51 2361
ber01-VHDL13_DWON_081558-2602081558-dsw--0-ia5 08-Feb-2026 15:58:51 3863
ber01-VHDL13_DWON_081559-2602081559-dsw--0-ia5 08-Feb-2026 16:00:01 3863
ber01-VHDL13_DWON_081824-2602081824-dsw--0-ia5 08-Feb-2026 18:24:36 3863
ber01-VHDL13_DWON_081826-2602081826-dsw--0-ia5 08-Feb-2026 18:26:51 3863
ber01-VHDL13_DWON_082255-2602082255-dsw--0-ia5 08-Feb-2026 22:55:06 3635
ber01-VHDL13_DWON_090335-2602090335-dsw--0-ia5 09-Feb-2026 03:36:01 4053
ber01-VHDL13_DWON_090628-2602090628-dsw--0-ia5 09-Feb-2026 06:28:23 4163
ber01-VHDL13_DWON_090855-2602090855-dsw--0-ia5 09-Feb-2026 08:56:01 4854
ber01-VHDL13_DWON_091253-2602091253-dsw--0-ia5 09-Feb-2026 12:53:17 4854
ber01-VHDL13_DWON_091437-2602091437-dsw--0-ia5 09-Feb-2026 14:37:48 4171
ber01-VHDL13_DWON_091440-2602091440-dsw--0-ia5 09-Feb-2026 14:41:01 4171
ber01-VHDL13_DWON_091752-2602091752-dsw--0-ia5 09-Feb-2026 17:52:07 4470
ber01-VHDL13_DWON_100325-2602100325-dsw--0-ia5 10-Feb-2026 03:25:11 4218
ber01-VHDL13_DWON_100627-2602100627-dsw--0-ia5 10-Feb-2026 06:27:53 4276
ber01-VHDL13_DWON_101041-2602101041-dsw--0-ia5 10-Feb-2026 10:42:02 5081
ber01-VHDL13_DWPG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2531
ber01-VHDL13_DWPG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 2797
ber01-VHDL13_DWPG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2851
ber01-VHDL13_DWPG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3202
ber01-VHDL13_DWPG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2488
ber01-VHDL13_DWPG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3261
ber01-VHDL13_DWPG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:02 3248
ber01-VHDL13_DWPG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:08 3261
ber01-VHDL13_DWPH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2335
ber01-VHDL13_DWPH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 2711
ber01-VHDL13_DWPH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2730
ber01-VHDL13_DWPH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:04 3329
ber01-VHDL13_DWPH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 2594
ber01-VHDL13_DWPH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 3778
ber01-VHDL13_DWPH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:02 3899
ber01-VHDL13_DWPH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 3762
ber01-VHDL13_DWSG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:30:03 2607
ber01-VHDL13_DWSG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:30:01 3232
ber01-VHDL13_DWSG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 3447
ber01-VHDL13_DWSG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:30:08 3788
ber01-VHDL13_DWSG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:30:06 3441
ber01-VHDL13_DWSG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:30:03 4030
ber01-VHDL13_DWSG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:06 4234
ber01-VHDL13_DWSG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:30:01 3814
ber01-VHDL17_DWOG_081200-2602081200-dsw--0-ia5 08-Feb-2026 12:20:21 3470
ber01-VHDL17_DWOG_091200-2602091200-dsw--0-ia5 09-Feb-2026 11:53:37 3551
swis2-VHDL20_DWEG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 2752
swis2-VHDL20_DWEG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:11 2911
swis2-VHDL20_DWEG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 2956
swis2-VHDL20_DWEG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3108
swis2-VHDL20_DWEG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 2644
swis2-VHDL20_DWEG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:06 2771
swis2-VHDL20_DWEG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 2794
swis2-VHDL20_DWEG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:09 3091
swis2-VHDL20_DWEG_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:41 3095
swis2-VHDL20_DWEH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 2949
swis2-VHDL20_DWEH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:11 3041
swis2-VHDL20_DWEH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 3028
swis2-VHDL20_DWEH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3282
swis2-VHDL20_DWEH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 2880
swis2-VHDL20_DWEH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:06 2844
swis2-VHDL20_DWEH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 2816
swis2-VHDL20_DWEH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:09 2995
swis2-VHDL20_DWEH_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:41 2999
swis2-VHDL20_DWEI_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 2562
swis2-VHDL20_DWEI_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:11 2835
swis2-VHDL20_DWEI_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 2875
swis2-VHDL20_DWEI_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3403
swis2-VHDL20_DWEI_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3060
swis2-VHDL20_DWEI_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:06 2759
swis2-VHDL20_DWEI_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 2818
swis2-VHDL20_DWEI_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:09 2887
swis2-VHDL20_DWEI_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 09:37:41 2891
swis2-VHDL20_DWHG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3304
swis2-VHDL20_DWHG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3742
swis2-VHDL20_DWHG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 3881
swis2-VHDL20_DWHG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 4536
swis2-VHDL20_DWHG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:06 3599
swis2-VHDL20_DWHG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 4107
swis2-VHDL20_DWHG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:08 4147
swis2-VHDL20_DWHG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:09 4497
swis2-VHDL20_DWHH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 2531
swis2-VHDL20_DWHH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 2937
swis2-VHDL20_DWHH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:06 2897
swis2-VHDL20_DWHH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3562
swis2-VHDL20_DWHH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:06 2707
swis2-VHDL20_DWHH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3886
swis2-VHDL20_DWHH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:08 3899
swis2-VHDL20_DWHH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:09 4756
swis2-VHDL20_DWLG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3487
swis2-VHDL20_DWLG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3609
swis2-VHDL20_DWLG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:12 3605
swis2-VHDL20_DWLG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3756
swis2-VHDL20_DWLG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3463
swis2-VHDL20_DWLG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3696
swis2-VHDL20_DWLG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:12 3752
swis2-VHDL20_DWLG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:05 3905
swis2-VHDL20_DWLH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3144
swis2-VHDL20_DWLH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3279
swis2-VHDL20_DWLH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:12 3216
swis2-VHDL20_DWLH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3423
swis2-VHDL20_DWLH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 2960
swis2-VHDL20_DWLH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3154
swis2-VHDL20_DWLH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:12 3234
swis2-VHDL20_DWLH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:05 3394
swis2-VHDL20_DWLI_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3074
swis2-VHDL20_DWLI_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3249
swis2-VHDL20_DWLI_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:12 3107
swis2-VHDL20_DWLI_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3174
swis2-VHDL20_DWLI_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 2888
swis2-VHDL20_DWLI_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3333
swis2-VHDL20_DWLI_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:12 3403
swis2-VHDL20_DWLI_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:05 3466
swis2-VHDL20_DWMG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3150
swis2-VHDL20_DWMG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3651
swis2-VHDL20_DWMG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 3632
swis2-VHDL20_DWMG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 4167
swis2-VHDL20_DWMG_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:16 4610
swis2-VHDL20_DWMG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3578
swis2-VHDL20_DWMG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3975
swis2-VHDL20_DWMG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 4230
swis2-VHDL20_DWMG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:02 5199
swis2-VHDL20_DWMO_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3118
swis2-VHDL20_DWMO_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3613
swis2-VHDL20_DWMO_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 3570
swis2-VHDL20_DWMO_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3888
swis2-VHDL20_DWMO_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:26 4242
swis2-VHDL20_DWMO_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3383
swis2-VHDL20_DWMO_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3751
swis2-VHDL20_DWMO_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 3842
swis2-VHDL20_DWMO_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:02 4453
swis2-VHDL20_DWMP_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3405
swis2-VHDL20_DWMP_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 4013
swis2-VHDL20_DWMP_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:06 3942
swis2-VHDL20_DWMP_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 4343
swis2-VHDL20_DWMP_090800_COR-2602090800-dsw--0-ia5 09-Feb-2026 10:28:36 4514
swis2-VHDL20_DWMP_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3773
swis2-VHDL20_DWMP_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 4189
swis2-VHDL20_DWMP_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 4406
swis2-VHDL20_DWMP_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:02 5382
swis2-VHDL20_DWPG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3314
swis2-VHDL20_DWPG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3305
swis2-VHDL20_DWPG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:12 3209
swis2-VHDL20_DWPG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 3935
swis2-VHDL20_DWPG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3073
swis2-VHDL20_DWPG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 3642
swis2-VHDL20_DWPG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:12 3776
swis2-VHDL20_DWPG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:05 3925
swis2-VHDL20_DWPH_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3117
swis2-VHDL20_DWPH_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3218
swis2-VHDL20_DWPH_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:00:12 3089
swis2-VHDL20_DWPH_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 4176
swis2-VHDL20_DWPH_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3362
swis2-VHDL20_DWPH_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 4158
swis2-VHDL20_DWPH_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:00:12 4606
swis2-VHDL20_DWPH_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:05 4755
swis2-VHDL20_DWPH_100800_COR-2602100800-dsw--0-ia5 10-Feb-2026 10:12:31 4577
swis2-VHDL20_DWSG_081300-2602081300-dsw--0-ia5 08-Feb-2026 14:45:17 3423
swis2-VHDL20_DWSG_081800-2602081800-dsw--0-ia5 08-Feb-2026 19:45:04 3017
swis2-VHDL20_DWSG_090200-2602090200-dsw--0-ia5 09-Feb-2026 03:45:05 3635
swis2-VHDL20_DWSG_090400-2602090400-dsw--0-ia5 09-Feb-2026 06:15:01 3857
swis2-VHDL20_DWSG_090800-2602090800-dsw--0-ia5 09-Feb-2026 09:45:02 4415
swis2-VHDL20_DWSG_091300-2602091300-dsw--0-ia5 09-Feb-2026 14:45:03 4297
swis2-VHDL20_DWSG_091800-2602091800-dsw--0-ia5 09-Feb-2026 19:45:02 3975
swis2-VHDL20_DWSG_100200-2602100200-dsw--0-ia5 10-Feb-2026 03:45:02 4552
swis2-VHDL20_DWSG_100400-2602100400-dsw--0-ia5 10-Feb-2026 06:15:07 4644
swis2-VHDL20_DWSG_100800-2602100800-dsw--0-ia5 10-Feb-2026 09:45:02 4320
wst04-VHDL20_DWEG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:12 232258
wst04-VHDL20_DWEG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 233100
wst04-VHDL20_DWEG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:16 232606
wst04-VHDL20_DWEG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:16 235940
wst04-VHDL20_DWEG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:12 233572
wst04-VHDL20_DWEG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:17 234039
wst04-VHDL20_DWEG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:17 233206
wst04-VHDL20_DWEG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:16 237349
wst04-VHDL20_DWEG_100800_COR-2602100800-omedes-..> 10-Feb-2026 09:37:57 237349
wst04-VHDL20_DWEH_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:12 227246
wst04-VHDL20_DWEH_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 228468
wst04-VHDL20_DWEH_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:12 227954
wst04-VHDL20_DWEH_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:12 229461
wst04-VHDL20_DWEH_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:12 227706
wst04-VHDL20_DWEH_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:10 228910
wst04-VHDL20_DWEH_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:17 228077
wst04-VHDL20_DWEH_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:16 235724
wst04-VHDL20_DWEH_100800_COR-2602100800-omedes-..> 10-Feb-2026 09:37:51 235724
wst04-VHDL20_DWEI_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:16 324803
wst04-VHDL20_DWEI_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 325155
wst04-VHDL20_DWEI_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:16 325117
wst04-VHDL20_DWEI_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:16 329944
wst04-VHDL20_DWEI_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:12 328635
wst04-VHDL20_DWEI_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:17 329098
wst04-VHDL20_DWEI_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:17 328687
wst04-VHDL20_DWEI_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:16 332595
wst04-VHDL20_DWEI_100800_COR-2602100800-omedes-..> 10-Feb-2026 09:37:57 332595
wst04-VHDL20_DWHG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:22 310973
wst04-VHDL20_DWHG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 311604
wst04-VHDL20_DWHG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:12 311621
wst04-VHDL20_DWHG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:26 320785
wst04-VHDL20_DWHG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:22 318788
wst04-VHDL20_DWHG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:21 319721
wst04-VHDL20_DWHG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:12 319658
wst04-VHDL20_DWHG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:26 321773
wst04-VHDL20_DWHH_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:22 299316
wst04-VHDL20_DWHH_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 300435
wst04-VHDL20_DWHH_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:12 300367
wst04-VHDL20_DWHH_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:26 306535
wst04-VHDL20_DWHH_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:22 305720
wst04-VHDL20_DWHH_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:13 307002
wst04-VHDL20_DWHH_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:12 307530
wst04-VHDL20_DWHH_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:26 310286
wst04-VHDL20_DWLG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:22 307775
wst04-VHDL20_DWLG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 308300
wst04-VHDL20_DWLG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:42 308280
wst04-VHDL20_DWLG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:32 306453
wst04-VHDL20_DWLG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:22 305748
wst04-VHDL20_DWLG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:26 305973
wst04-VHDL20_DWLG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:42 305974
wst04-VHDL20_DWLG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:32 313726
wst04-VHDL20_DWLH_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:26 304756
wst04-VHDL20_DWLH_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:26 305572
wst04-VHDL20_DWLH_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:42 305395
wst04-VHDL20_DWLH_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:36 313396
wst04-VHDL20_DWLH_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:22 312269
wst04-VHDL20_DWLH_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:21 312831
wst04-VHDL20_DWLH_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:42 312856
wst04-VHDL20_DWLH_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:32 312131
wst04-VHDL20_DWLI_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:22 304058
wst04-VHDL20_DWLI_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 304021
wst04-VHDL20_DWLI_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:42 303934
wst04-VHDL20_DWLI_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:32 308144
wst04-VHDL20_DWLI_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:26 307295
wst04-VHDL20_DWLI_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:26 307694
wst04-VHDL20_DWLI_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:42 307585
wst04-VHDL20_DWLI_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:32 314156
wst04-VHDL20_DWMG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:18 516289
wst04-VHDL20_DWMG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 517860
wst04-VHDL20_DWMG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:22 517760
wst04-VHDL20_DWMG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:22 518209
wst04-VHDL20_DWMG_090800_COR-2602090800-omedes-..> 09-Feb-2026 10:28:26 519275
wst04-VHDL20_DWMG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:16 516143
wst04-VHDL20_DWMG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:17 516586
wst04-VHDL20_DWMG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:17 518067
wst04-VHDL20_DWMG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:22 538831
wst04-VHDL20_DWMO_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:18 420177
wst04-VHDL20_DWMO_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:11 421027
wst04-VHDL20_DWMO_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:16 421302
wst04-VHDL20_DWMO_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:22 417457
wst04-VHDL20_DWMO_090800_COR-2602090800-omedes-..> 09-Feb-2026 10:28:36 417696
wst04-VHDL20_DWMO_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:16 416257
wst04-VHDL20_DWMO_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:13 416011
wst04-VHDL20_DWMO_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:11 416986
wst04-VHDL20_DWMO_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:22 427543
wst04-VHDL20_DWMP_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:18 528525
wst04-VHDL20_DWMP_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:11 528656
wst04-VHDL20_DWMP_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:22 529731
wst04-VHDL20_DWMP_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:22 538066
wst04-VHDL20_DWMP_090800_COR-2602090800-omedes-..> 09-Feb-2026 10:28:42 537996
wst04-VHDL20_DWMP_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:16 535086
wst04-VHDL20_DWMP_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:23 534265
wst04-VHDL20_DWMP_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:21 536921
wst04-VHDL20_DWMP_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:22 563880
wst04-VHDL20_DWPG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:26 315642
wst04-VHDL20_DWPG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:26 316507
wst04-VHDL20_DWPG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:32 316356
wst04-VHDL20_DWPG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:32 360421
wst04-VHDL20_DWPG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:26 314313
wst04-VHDL20_DWPG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:26 314800
wst04-VHDL20_DWPG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:32 314831
wst04-VHDL20_DWPG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:32 364078
wst04-VHDL20_DWPH_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:22 271835
wst04-VHDL20_DWPH_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:21 227913
wst04-VHDL20_DWPH_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:00:32 227803
wst04-VHDL20_DWPH_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:26 275288
wst04-VHDL20_DWPH_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:22 273966
wst04-VHDL20_DWPH_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:21 230298
wst04-VHDL20_DWPH_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:00:32 230665
wst04-VHDL20_DWPH_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:26 275586
wst04-VHDL20_DWPH_100800_COR-2602100800-omedes-..> 10-Feb-2026 10:00:35 275725
wst04-VHDL20_DWSG_081300-2602081300-omedes--0.pdf 08-Feb-2026 14:45:17 326752
wst04-VHDL20_DWSG_081800-2602081800-omedes--0.pdf 08-Feb-2026 19:45:12 326016
wst04-VHDL20_DWSG_090200-2602090200-omedes--0.pdf 09-Feb-2026 03:45:11 327179
wst04-VHDL20_DWSG_090400-2602090400-omedes--0.pdf 09-Feb-2026 06:15:12 327416
wst04-VHDL20_DWSG_090800-2602090800-omedes--0.pdf 09-Feb-2026 09:45:12 331415
wst04-VHDL20_DWSG_091300-2602091300-omedes--0.pdf 09-Feb-2026 14:45:12 331362
wst04-VHDL20_DWSG_091800-2602091800-omedes--0.pdf 09-Feb-2026 19:45:12 330676
wst04-VHDL20_DWSG_100200-2602100200-omedes--0.pdf 10-Feb-2026 03:45:10 331669
wst04-VHDL20_DWSG_100400-2602100400-omedes--0.pdf 10-Feb-2026 06:15:11 332754
wst04-VHDL20_DWSG_100800-2602100800-omedes--0.pdf 10-Feb-2026 09:45:16 338220