Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_070600 07-Dec-2025 13:39:14 5015
FPDL13_DWMZ_080600 08-Dec-2025 13:59:20 3337
SXDL31_DWAV_071800 07-Dec-2025 17:55:14 6475
SXDL31_DWAV_080800 08-Dec-2025 08:26:59 7647
SXDL31_DWAV_081800 08-Dec-2025 17:39:00 4904
SXDL31_DWAV_090800 09-Dec-2025 08:36:59 6416
SXDL31_DWAV_LATEST 09-Dec-2025 08:36:59 6416
SXDL33_DWAV_080000 08-Dec-2025 09:09:33 6686
SXDL33_DWAV_090000 09-Dec-2025 10:39:32 10301
SXDL33_DWAV_LATEST 09-Dec-2025 10:39:32 10301
ber01-FWDL39_DWMS_081230-2512081230-dsw--0-ia5 08-Dec-2025 12:55:52 1522
ber01-VHDL13_DWEH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:28:17 2458
ber01-VHDL13_DWEH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:28:11 2309
ber01-VHDL13_DWEH_080400-2512080400-dsw--0-ia5 08-Dec-2025 05:58:17 2407
ber01-VHDL13_DWEH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:28:17 2521
ber01-VHDL13_DWEH_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:29:07 2625
ber01-VHDL13_DWEH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:28:16 2140
ber01-VHDL13_DWEH_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:46 2369
ber01-VHDL13_DWEH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:28:11 2395
ber01-VHDL13_DWEH_090400-2512090400-dsw--0-ia5 09-Dec-2025 05:58:17 2837
ber01-VHDL13_DWEH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:28:16 2806
ber01-VHDL13_DWHG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:09 2537
ber01-VHDL13_DWHG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:09 2531
ber01-VHDL13_DWHG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:06 2532
ber01-VHDL13_DWHG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2554
ber01-VHDL13_DWHG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:09 2143
ber01-VHDL13_DWHG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:08 2279
ber01-VHDL13_DWHG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:07 2279
ber01-VHDL13_DWHG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:07 2585
ber01-VHDL13_DWHH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:09 2408
ber01-VHDL13_DWHH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:09 2427
ber01-VHDL13_DWHH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:06 2356
ber01-VHDL13_DWHH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2503
ber01-VHDL13_DWHH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:09 2154
ber01-VHDL13_DWHH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:08 2254
ber01-VHDL13_DWHH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:06 2254
ber01-VHDL13_DWHH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:07 2507
ber01-VHDL13_DWLG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 2395
ber01-VHDL13_DWLG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:01 2307
ber01-VHDL13_DWLG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 2226
ber01-VHDL13_DWLG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2233
ber01-VHDL13_DWLG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 2125
ber01-VHDL13_DWLG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 2161
ber01-VHDL13_DWLG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 2237
ber01-VHDL13_DWLG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2519
ber01-VHDL13_DWLH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 2471
ber01-VHDL13_DWLH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:01 2458
ber01-VHDL13_DWLH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 2286
ber01-VHDL13_DWLH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2178
ber01-VHDL13_DWLH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 2065
ber01-VHDL13_DWLH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 1977
ber01-VHDL13_DWLH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 1947
ber01-VHDL13_DWLH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2091
ber01-VHDL13_DWLI_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 2183
ber01-VHDL13_DWLI_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:01 2167
ber01-VHDL13_DWLI_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 2203
ber01-VHDL13_DWLI_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2263
ber01-VHDL13_DWLI_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 1996
ber01-VHDL13_DWLI_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 1993
ber01-VHDL13_DWLI_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 2083
ber01-VHDL13_DWLI_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2347
ber01-VHDL13_DWMG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 3315
ber01-VHDL13_DWMG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:04 3525
ber01-VHDL13_DWMG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 3305
ber01-VHDL13_DWMG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 3140
ber01-VHDL13_DWMG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 2909
ber01-VHDL13_DWMG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 3209
ber01-VHDL13_DWMG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 3220
ber01-VHDL13_DWMG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2961
ber01-VHDL13_DWMO_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 2700
ber01-VHDL13_DWMO_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:04 2794
ber01-VHDL13_DWMO_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 2794
ber01-VHDL13_DWMO_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2805
ber01-VHDL13_DWMO_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 2612
ber01-VHDL13_DWMO_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 2770
ber01-VHDL13_DWMO_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 2769
ber01-VHDL13_DWMO_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2589
ber01-VHDL13_DWMP_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 3324
ber01-VHDL13_DWMP_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:04 3716
ber01-VHDL13_DWMP_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 3716
ber01-VHDL13_DWMP_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 3155
ber01-VHDL13_DWMP_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 2840
ber01-VHDL13_DWMP_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 3067
ber01-VHDL13_DWMP_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 3067
ber01-VHDL13_DWMP_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2815
ber01-VHDL13_DWOG_071700-2512071700-dsw--0-ia5 07-Dec-2025 19:00:06 4246
ber01-VHDL13_DWOG_080300-2512080300-dsw--0-ia5 08-Dec-2025 04:00:04 4059
ber01-VHDL13_DWOG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 4204
ber01-VHDL13_DWOG_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:18:36 4173
ber01-VHDL13_DWOG_081700-2512081700-dsw--0-ia5 08-Dec-2025 19:00:03 3850
ber01-VHDL13_DWOG_090300-2512090300-dsw--0-ia5 09-Dec-2025 04:00:02 4010
ber01-VHDL13_DWOG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:07 4246
ber01-VHDL13_DWOH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:28:17 2294
ber01-VHDL13_DWOH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:28:11 2423
ber01-VHDL13_DWOH_080400-2512080400-dsw--0-ia5 08-Dec-2025 05:58:11 2574
ber01-VHDL13_DWOH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:28:17 2748
ber01-VHDL13_DWOH_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:29:11 2948
ber01-VHDL13_DWOH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:28:16 2621
ber01-VHDL13_DWOH_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:46 2626
ber01-VHDL13_DWOH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:28:17 2869
ber01-VHDL13_DWOH_090400-2512090400-dsw--0-ia5 09-Dec-2025 05:58:17 3076
ber01-VHDL13_DWOH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:28:16 2791
ber01-VHDL13_DWOI_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:28:11 2218
ber01-VHDL13_DWOI_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:28:17 2364
ber01-VHDL13_DWOI_080400-2512080400-dsw--0-ia5 08-Dec-2025 05:58:11 2155
ber01-VHDL13_DWOI_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:28:11 2324
ber01-VHDL13_DWOI_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:29:07 2560
ber01-VHDL13_DWOI_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:28:12 2495
ber01-VHDL13_DWOI_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:52 2400
ber01-VHDL13_DWOI_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:28:11 2391
ber01-VHDL13_DWOI_090400-2512090400-dsw--0-ia5 09-Dec-2025 05:58:12 2856
ber01-VHDL13_DWOI_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:28:12 2663
ber01-VHDL13_DWON_071532-2512071532-dsw--0-ia5 07-Dec-2025 15:32:36 3877
ber01-VHDL13_DWON_071818-2512071818-dsw--0-ia5 07-Dec-2025 18:18:37 3867
ber01-VHDL13_DWON_072354-2512072354-dsw--0-ia5 07-Dec-2025 23:54:42 3776
ber01-VHDL13_DWON_080324-2512080324-dsw--0-ia5 08-Dec-2025 03:24:27 3776
ber01-VHDL13_DWON_080334-2512080334-dsw--0-ia5 08-Dec-2025 03:34:30 3776
ber01-VHDL13_DWON_080629-2512080629-dsw--0-ia5 08-Dec-2025 06:29:41 3608
ber01-VHDL13_DWON_080649-2512080649-dsw--0-ia5 08-Dec-2025 06:49:41 3887
ber01-VHDL13_DWON_080903-2512080903-dsw--0-ia5 08-Dec-2025 09:03:21 3887
ber01-VHDL13_DWON_080914-2512080914-dsw--0-ia5 08-Dec-2025 09:14:37 3824
ber01-VHDL13_DWON_080915-2512080915-dsw--0-ia5 08-Dec-2025 09:15:21 3824
ber01-VHDL13_DWON_081318-2512081318-dsw--0-ia5 08-Dec-2025 13:18:22 3768
ber01-VHDL13_DWON_081550-2512081550-dsw--0-ia5 08-Dec-2025 15:50:46 3215
ber01-VHDL13_DWON_081552-2512081552-dsw--0-ia5 08-Dec-2025 15:52:06 3215
ber01-VHDL13_DWON_090146-2512090146-dsw--0-ia5 09-Dec-2025 01:46:51 3528
ber01-VHDL13_DWON_090347-2512090347-dsw--0-ia5 09-Dec-2025 03:48:01 3730
ber01-VHDL13_DWON_090622-2512090622-dsw--0-ia5 09-Dec-2025 06:22:42 4084
ber01-VHDL13_DWON_090703-2512090703-dsw--0-ia5 09-Dec-2025 07:03:42 4098
ber01-VHDL13_DWON_090907-2512090907-dsw--0-ia5 09-Dec-2025 09:08:03 4097
ber01-VHDL13_DWON_090910-2512090910-dsw--0-ia5 09-Dec-2025 09:10:27 4097
ber01-VHDL13_DWPG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 1833
ber01-VHDL13_DWPG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:01 1846
ber01-VHDL13_DWPG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 1742
ber01-VHDL13_DWPG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 1740
ber01-VHDL13_DWPG_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 14:11:17 1818
ber01-VHDL13_DWPG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 1699
ber01-VHDL13_DWPG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 1803
ber01-VHDL13_DWPG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 2172
ber01-VHDL13_DWPG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2374
ber01-VHDL13_DWPH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 2107
ber01-VHDL13_DWPH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:01 2171
ber01-VHDL13_DWPH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:02 2037
ber01-VHDL13_DWPH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 2040
ber01-VHDL13_DWPH_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 14:12:20 1992
ber01-VHDL13_DWPH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 1818
ber01-VHDL13_DWPH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 1875
ber01-VHDL13_DWPH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:01 2029
ber01-VHDL13_DWPH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:02 2157
ber01-VHDL13_DWSG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:30:05 3660
ber01-VHDL13_DWSG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:30:04 3883
ber01-VHDL13_DWSG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:08 3455
ber01-VHDL13_DWSG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:30:07 3251
ber01-VHDL13_DWSG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:30:02 3493
ber01-VHDL13_DWSG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:30:04 3766
ber01-VHDL13_DWSG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:06 3622
ber01-VHDL13_DWSG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:30:07 3548
ber01-VHDL17_DWOG_081200-2512081200-dsw--0-ia5 08-Dec-2025 11:55:41 2578
ber01-VHDL17_DWOG_091200-2512091200-dsw--0-ia5 09-Dec-2025 12:39:26 3498
swis2-VHDL20_DWEG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2622
swis2-VHDL20_DWEG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:07 2701
swis2-VHDL20_DWEG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 2898
swis2-VHDL20_DWEG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 3231
swis2-VHDL20_DWEG_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:28:57 3127
swis2-VHDL20_DWEG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:06 2917
swis2-VHDL20_DWEG_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:36 2811
swis2-VHDL20_DWEG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:07 3149
swis2-VHDL20_DWEG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:06 3400
swis2-VHDL20_DWEG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3199
swis2-VHDL20_DWEH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2813
swis2-VHDL20_DWEH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:07 2632
swis2-VHDL20_DWEH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 2743
swis2-VHDL20_DWEH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 3029
swis2-VHDL20_DWEH_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:28:57 2803
swis2-VHDL20_DWEH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:06 2563
swis2-VHDL20_DWEH_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:36 2570
swis2-VHDL20_DWEH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:07 2720
swis2-VHDL20_DWEH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:06 3173
swis2-VHDL20_DWEH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:06 3239
swis2-VHDL20_DWEI_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2571
swis2-VHDL20_DWEI_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:07 2659
swis2-VHDL20_DWEI_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 2510
swis2-VHDL20_DWEI_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2854
swis2-VHDL20_DWEI_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 13:28:57 2739
swis2-VHDL20_DWEI_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:06 2791
swis2-VHDL20_DWEI_081800_COR-2512081800-dsw--0-ia5 08-Dec-2025 20:17:36 2585
swis2-VHDL20_DWEI_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:07 2686
swis2-VHDL20_DWEI_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:06 3211
swis2-VHDL20_DWEI_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3118
swis2-VHDL20_DWHG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2720
swis2-VHDL20_DWHG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2717
swis2-VHDL20_DWHG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:06 2715
swis2-VHDL20_DWHG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:02 3084
swis2-VHDL20_DWHG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2326
swis2-VHDL20_DWHG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:07 2465
swis2-VHDL20_DWHG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:07 2462
swis2-VHDL20_DWHG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3198
swis2-VHDL20_DWHH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2594
swis2-VHDL20_DWHH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2613
swis2-VHDL20_DWHH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:06 2542
swis2-VHDL20_DWHH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:02 3041
swis2-VHDL20_DWHH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2340
swis2-VHDL20_DWHH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:07 2440
swis2-VHDL20_DWHH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:07 2440
swis2-VHDL20_DWHH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3053
swis2-VHDL20_DWLG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2738
swis2-VHDL20_DWLG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2653
swis2-VHDL20_DWLG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:12 2571
swis2-VHDL20_DWLG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2728
swis2-VHDL20_DWLG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2470
swis2-VHDL20_DWLG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 2509
swis2-VHDL20_DWLG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:11 2583
swis2-VHDL20_DWLG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3017
swis2-VHDL20_DWLH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2821
swis2-VHDL20_DWLH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2811
swis2-VHDL20_DWLH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:12 2638
swis2-VHDL20_DWLH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2684
swis2-VHDL20_DWLH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2417
swis2-VHDL20_DWLH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 2332
swis2-VHDL20_DWLH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:11 2300
swis2-VHDL20_DWLH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 2599
swis2-VHDL20_DWLI_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2528
swis2-VHDL20_DWLI_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2515
swis2-VHDL20_DWLI_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:12 2550
swis2-VHDL20_DWLI_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2759
swis2-VHDL20_DWLI_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2343
swis2-VHDL20_DWLI_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:04 2343
swis2-VHDL20_DWLI_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:11 2431
swis2-VHDL20_DWLI_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 2845
swis2-VHDL20_DWMG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 3684
swis2-VHDL20_DWMG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 3894
swis2-VHDL20_DWMG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 3736
swis2-VHDL20_DWMG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 3797
swis2-VHDL20_DWMG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 3339
swis2-VHDL20_DWMG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 3616
swis2-VHDL20_DWMG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:02 3650
swis2-VHDL20_DWMG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3623
swis2-VHDL20_DWMO_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 3073
swis2-VHDL20_DWMO_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 3167
swis2-VHDL20_DWMO_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 2990
swis2-VHDL20_DWMO_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 3341
swis2-VHDL20_DWMO_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2987
swis2-VHDL20_DWMO_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 3145
swis2-VHDL20_DWMO_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:02 3144
swis2-VHDL20_DWMO_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3130
swis2-VHDL20_DWMP_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 3695
swis2-VHDL20_DWMP_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 4088
swis2-VHDL20_DWMP_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 3923
swis2-VHDL20_DWMP_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 3811
swis2-VHDL20_DWMP_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 3281
swis2-VHDL20_DWMP_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 3501
swis2-VHDL20_DWMP_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:02 3492
swis2-VHDL20_DWMP_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 3482
swis2-VHDL20_DWPG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2292
swis2-VHDL20_DWPG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2174
swis2-VHDL20_DWPG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:12 2069
swis2-VHDL20_DWPG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2201
swis2-VHDL20_DWPG_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 14:18:51 2279
swis2-VHDL20_DWPG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2160
swis2-VHDL20_DWPG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 2133
swis2-VHDL20_DWPG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:11 2499
swis2-VHDL20_DWPG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 2837
swis2-VHDL20_DWPH_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 2566
swis2-VHDL20_DWPH_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 2498
swis2-VHDL20_DWPH_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:00:12 2366
swis2-VHDL20_DWPH_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:06 2501
swis2-VHDL20_DWPH_080800_COR-2512080800-dsw--0-ia5 08-Dec-2025 14:19:27 2453
swis2-VHDL20_DWPH_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 2279
swis2-VHDL20_DWPH_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 2204
swis2-VHDL20_DWPH_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:00:11 2358
swis2-VHDL20_DWPH_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 2620
swis2-VHDL20_DWSG_071300-2512071300-dsw--0-ia5 07-Dec-2025 14:45:06 4039
swis2-VHDL20_DWSG_071800-2512071800-dsw--0-ia5 07-Dec-2025 19:45:05 4015
swis2-VHDL20_DWSG_080200-2512080200-dsw--0-ia5 08-Dec-2025 03:45:01 4230
swis2-VHDL20_DWSG_080400-2512080400-dsw--0-ia5 08-Dec-2025 06:15:01 3868
swis2-VHDL20_DWSG_080800-2512080800-dsw--0-ia5 08-Dec-2025 09:45:02 3815
swis2-VHDL20_DWSG_081300-2512081300-dsw--0-ia5 08-Dec-2025 14:45:10 3751
swis2-VHDL20_DWSG_081800-2512081800-dsw--0-ia5 08-Dec-2025 19:45:02 3908
swis2-VHDL20_DWSG_090200-2512090200-dsw--0-ia5 09-Dec-2025 03:45:05 4171
swis2-VHDL20_DWSG_090400-2512090400-dsw--0-ia5 09-Dec-2025 06:15:02 4039
swis2-VHDL20_DWSG_090800-2512090800-dsw--0-ia5 09-Dec-2025 09:45:04 4177
wst04-VHDL20_DWEG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:17 233779
wst04-VHDL20_DWEG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:11 235507
wst04-VHDL20_DWEG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:21 234575
wst04-VHDL20_DWEG_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:22 229899
wst04-VHDL20_DWEG_080800_COR-2512080800-omedes-..> 08-Dec-2025 13:29:11 227972
wst04-VHDL20_DWEG_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:16 227673
wst04-VHDL20_DWEG_081800_COR-2512081800-omedes-..> 08-Dec-2025 20:17:46 227234
wst04-VHDL20_DWEG_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:16 229863
wst04-VHDL20_DWEG_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:21 229333
wst04-VHDL20_DWEG_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:22 227468
wst04-VHDL20_DWEH_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:13 234675
wst04-VHDL20_DWEH_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:16 235579
wst04-VHDL20_DWEH_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:27 235618
wst04-VHDL20_DWEH_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:22 230075
wst04-VHDL20_DWEH_080800_COR-2512080800-omedes-..> 08-Dec-2025 13:29:07 229098
wst04-VHDL20_DWEH_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:16 229261
wst04-VHDL20_DWEH_081800_COR-2512081800-omedes-..> 08-Dec-2025 20:17:52 228787
wst04-VHDL20_DWEH_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:16 229352
wst04-VHDL20_DWEH_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:27 230138
wst04-VHDL20_DWEH_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:22 227121
wst04-VHDL20_DWEI_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:17 329229
wst04-VHDL20_DWEI_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:16 329658
wst04-VHDL20_DWEI_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:27 329694
wst04-VHDL20_DWEI_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:26 319443
wst04-VHDL20_DWEI_080800_COR-2512080800-omedes-..> 08-Dec-2025 13:29:11 319189
wst04-VHDL20_DWEI_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:16 319519
wst04-VHDL20_DWEI_081800_COR-2512081800-omedes-..> 08-Dec-2025 20:17:52 319044
wst04-VHDL20_DWEI_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:16 319943
wst04-VHDL20_DWEI_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:27 319926
wst04-VHDL20_DWEI_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:22 315476
wst04-VHDL20_DWHG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:11 318937
wst04-VHDL20_DWHG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:11 319369
wst04-VHDL20_DWHG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:12 319333
wst04-VHDL20_DWHG_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:22 309904
wst04-VHDL20_DWHG_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:22 308527
wst04-VHDL20_DWHG_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:12 308720
wst04-VHDL20_DWHG_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:11 308741
wst04-VHDL20_DWHG_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:16 307154
wst04-VHDL20_DWHH_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:11 315325
wst04-VHDL20_DWHH_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:11 315744
wst04-VHDL20_DWHH_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:12 315714
wst04-VHDL20_DWHH_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:16 301543
wst04-VHDL20_DWHH_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:16 300956
wst04-VHDL20_DWHH_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:12 300762
wst04-VHDL20_DWHH_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:11 300877
wst04-VHDL20_DWHH_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:16 294685
wst04-VHDL20_DWLG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:21 322795
wst04-VHDL20_DWLG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:22 322543
wst04-VHDL20_DWLG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:41 322261
wst04-VHDL20_DWLG_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:32 312250
wst04-VHDL20_DWLG_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:26 312106
wst04-VHDL20_DWLG_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:27 313622
wst04-VHDL20_DWLG_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:41 312954
wst04-VHDL20_DWLG_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:36 305911
wst04-VHDL20_DWLH_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:27 318219
wst04-VHDL20_DWLH_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:26 318051
wst04-VHDL20_DWLH_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:41 317677
wst04-VHDL20_DWLH_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:32 313574
wst04-VHDL20_DWLH_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:22 313050
wst04-VHDL20_DWLH_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:27 314217
wst04-VHDL20_DWLH_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:41 313235
wst04-VHDL20_DWLH_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:30 305208
wst04-VHDL20_DWLI_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:21 318505
wst04-VHDL20_DWLI_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:26 318568
wst04-VHDL20_DWLI_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:41 318088
wst04-VHDL20_DWLI_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:32 307286
wst04-VHDL20_DWLI_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:22 306397
wst04-VHDL20_DWLI_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:27 308248
wst04-VHDL20_DWLI_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:41 307639
wst04-VHDL20_DWLI_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:30 298541
wst04-VHDL20_DWMG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:17 551667
wst04-VHDL20_DWMG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:22 551849
wst04-VHDL20_DWMG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:21 551021
wst04-VHDL20_DWMG_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:16 532966
wst04-VHDL20_DWMG_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:12 532251
wst04-VHDL20_DWMG_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:22 532920
wst04-VHDL20_DWMG_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:21 532859
wst04-VHDL20_DWMG_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:16 504180
wst04-VHDL20_DWMO_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:17 433968
wst04-VHDL20_DWMO_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:16 434096
wst04-VHDL20_DWMO_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:21 433904
wst04-VHDL20_DWMO_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:12 416385
wst04-VHDL20_DWMO_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:12 415675
wst04-VHDL20_DWMO_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:16 416421
wst04-VHDL20_DWMO_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:21 416869
wst04-VHDL20_DWMO_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:12 403101
wst04-VHDL20_DWMP_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:23 572652
wst04-VHDL20_DWMP_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:22 571981
wst04-VHDL20_DWMP_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:17 572317
wst04-VHDL20_DWMP_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:16 553143
wst04-VHDL20_DWMP_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:16 552312
wst04-VHDL20_DWMP_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:22 551645
wst04-VHDL20_DWMP_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:15:21 552787
wst04-VHDL20_DWMP_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:16 519073
wst04-VHDL20_DWPG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:27 323774
wst04-VHDL20_DWPG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:22 323162
wst04-VHDL20_DWPG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:32 322590
wst04-VHDL20_DWPG_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:36 358836
wst04-VHDL20_DWPG_080800_COR-2512080800-omedes-..> 08-Dec-2025 14:17:11 359164
wst04-VHDL20_DWPG_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:26 314398
wst04-VHDL20_DWPG_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:22 314899
wst04-VHDL20_DWPG_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:31 314980
wst04-VHDL20_DWPG_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:30 347305
wst04-VHDL20_DWPH_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:21 274951
wst04-VHDL20_DWPH_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:26 230007
wst04-VHDL20_DWPH_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:00:32 229719
wst04-VHDL20_DWPH_080800-2512080800-omedes--0.pdf 08-Dec-2025 09:45:26 266594
wst04-VHDL20_DWPH_080800_COR-2512080800-omedes-..> 08-Dec-2025 14:17:57 266030
wst04-VHDL20_DWPH_081800-2512081800-omedes--0.pdf 08-Dec-2025 19:45:22 265915
wst04-VHDL20_DWPH_090200-2512090200-omedes--0.pdf 09-Dec-2025 03:45:22 221991
wst04-VHDL20_DWPH_090400-2512090400-omedes--0.pdf 09-Dec-2025 06:00:31 221268
wst04-VHDL20_DWPH_090800-2512090800-omedes--0.pdf 09-Dec-2025 09:45:30 264731
wst04-VHDL20_DWSG_071300-2512071300-omedes--0.pdf 07-Dec-2025 14:45:13 347160
wst04-VHDL20_DWSG_071800-2512071800-omedes--0.pdf 07-Dec-2025 19:45:11 347097
wst04-VHDL20_DWSG_080200-2512080200-omedes--0.pdf 08-Dec-2025 03:45:16 347317
wst04-VHDL20_DWSG_080400-2512080400-omedes--0.pdf 08-Dec-2025 06:15:17 346811
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