Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Apr-2026 12:19:50 4239
FPDL13_DWMZ_150600 15-Apr-2026 12:12:35 3592
SXDL31_DWAV_131800 13-Apr-2026 16:45:44 6012
SXDL31_DWAV_140800 14-Apr-2026 06:41:15 6000
SXDL31_DWAV_141800 14-Apr-2026 15:30:20 5375
SXDL31_DWAV_150800 15-Apr-2026 07:08:49 6390
SXDL31_DWAV_LATEST 15-Apr-2026 07:08:49 6390
SXDL33_DWAV_140000 14-Apr-2026 11:44:43 11363
SXDL33_DWAV_150000 15-Apr-2026 09:52:59 13461
SXDL33_DWAV_LATEST 15-Apr-2026 09:52:59 13461
ber01-FWDL39_DWMS_141230-2604141230-dsw--0-ia5 14-Apr-2026 11:04:51 1801
ber01-FWDL39_DWMS_151230-2604151230-dsw--0-ia5 15-Apr-2026 11:33:52 1431
ber01-VHDL13_DWEH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:28:13 2353
ber01-VHDL13_DWEH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:28:13 2353
ber01-VHDL13_DWEH_140400-2604140400-dsw--0-ia5 14-Apr-2026 04:58:11 2341
ber01-VHDL13_DWEH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:28:17 2146
ber01-VHDL13_DWEH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:28:16 2311
ber01-VHDL13_DWEH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:28:11 2310
ber01-VHDL13_DWEH_150400-2604150400-dsw--0-ia5 15-Apr-2026 04:58:17 2307
ber01-VHDL13_DWEH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:28:11 2189
ber01-VHDL13_DWHG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2684
ber01-VHDL13_DWHG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 3367
ber01-VHDL13_DWHG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3369
ber01-VHDL13_DWHG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 3130
ber01-VHDL13_DWHG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2544
ber01-VHDL13_DWHG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2484
ber01-VHDL13_DWHG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2487
ber01-VHDL13_DWHG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2487
ber01-VHDL13_DWHH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2667
ber01-VHDL13_DWHH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 3235
ber01-VHDL13_DWHH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3237
ber01-VHDL13_DWHH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 3131
ber01-VHDL13_DWHH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2451
ber01-VHDL13_DWHH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2483
ber01-VHDL13_DWHH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2486
ber01-VHDL13_DWHH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2486
ber01-VHDL13_DWLG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2446
ber01-VHDL13_DWLG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 2267
ber01-VHDL13_DWLG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:02 2359
ber01-VHDL13_DWLG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2422
ber01-VHDL13_DWLG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2408
ber01-VHDL13_DWLG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2415
ber01-VHDL13_DWLG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:01 2387
ber01-VHDL13_DWLG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2046
ber01-VHDL13_DWLH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2191
ber01-VHDL13_DWLH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 2107
ber01-VHDL13_DWLH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:02 2441
ber01-VHDL13_DWLH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2417
ber01-VHDL13_DWLH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2349
ber01-VHDL13_DWLH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2398
ber01-VHDL13_DWLH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:01 2449
ber01-VHDL13_DWLH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2375
ber01-VHDL13_DWLI_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2242
ber01-VHDL13_DWLI_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 2102
ber01-VHDL13_DWLI_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:02 2466
ber01-VHDL13_DWLI_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2470
ber01-VHDL13_DWLI_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2482
ber01-VHDL13_DWLI_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2527
ber01-VHDL13_DWLI_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:01 2520
ber01-VHDL13_DWLI_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2443
ber01-VHDL13_DWMG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2229
ber01-VHDL13_DWMG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:04 2571
ber01-VHDL13_DWMG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:06 2524
ber01-VHDL13_DWMG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2492
ber01-VHDL13_DWMG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2108
ber01-VHDL13_DWMG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2359
ber01-VHDL13_DWMG_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:31:54 2421
ber01-VHDL13_DWMG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:06 2417
ber01-VHDL13_DWMG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2608
ber01-VHDL13_DWMO_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2349
ber01-VHDL13_DWMO_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:04 2667
ber01-VHDL13_DWMO_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:06 2628
ber01-VHDL13_DWMO_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2660
ber01-VHDL13_DWMO_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2159
ber01-VHDL13_DWMO_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2476
ber01-VHDL13_DWMO_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:37:33 2520
ber01-VHDL13_DWMO_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:06 2516
ber01-VHDL13_DWMO_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2816
ber01-VHDL13_DWMP_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 1993
ber01-VHDL13_DWMP_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:04 2280
ber01-VHDL13_DWMP_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:06 2289
ber01-VHDL13_DWMP_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2246
ber01-VHDL13_DWMP_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 1920
ber01-VHDL13_DWMP_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2448
ber01-VHDL13_DWMP_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:37:50 2507
ber01-VHDL13_DWMP_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:06 2503
ber01-VHDL13_DWMP_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2561
ber01-VHDL13_DWOG_131700-2604131700-dsw--0-ia5 13-Apr-2026 18:00:12 2969
ber01-VHDL13_DWOG_140300-2604140300-dsw--0-ia5 14-Apr-2026 03:00:16 3057
ber01-VHDL13_DWOG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2712
ber01-VHDL13_DWOG_141700-2604141700-dsw--0-ia5 14-Apr-2026 18:00:09 2321
ber01-VHDL13_DWOG_150300-2604150300-dsw--0-ia5 15-Apr-2026 03:00:15 3039
ber01-VHDL13_DWOG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2781
ber01-VHDL13_DWOH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:28:16 2212
ber01-VHDL13_DWOH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:28:13 2320
ber01-VHDL13_DWOH_140400-2604140400-dsw--0-ia5 14-Apr-2026 04:58:11 2423
ber01-VHDL13_DWOH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:28:13 2211
ber01-VHDL13_DWOH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:28:12 2141
ber01-VHDL13_DWOH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:28:11 2235
ber01-VHDL13_DWOH_150400-2604150400-dsw--0-ia5 15-Apr-2026 04:58:11 2259
ber01-VHDL13_DWOH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:28:17 2105
ber01-VHDL13_DWOI_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:28:16 2263
ber01-VHDL13_DWOI_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:28:13 2257
ber01-VHDL13_DWOI_140400-2604140400-dsw--0-ia5 14-Apr-2026 04:58:17 2343
ber01-VHDL13_DWOI_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:28:13 2125
ber01-VHDL13_DWOI_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:28:16 2335
ber01-VHDL13_DWOI_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:28:17 2414
ber01-VHDL13_DWOI_150400-2604150400-dsw--0-ia5 15-Apr-2026 04:58:17 2438
ber01-VHDL13_DWOI_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:28:17 2331
ber01-VHDL13_DWON_131430-2604131430-dsw--0-ia5 13-Apr-2026 14:30:57 2763
ber01-VHDL13_DWON_131525-2604131525-dsw--0-ia5 13-Apr-2026 15:25:22 2818
ber01-VHDL13_DWON_131645-2604131645-dsw--0-ia5 13-Apr-2026 16:45:56 2818
ber01-VHDL13_DWON_131655-2604131655-dsw--0-ia5 13-Apr-2026 16:55:13 2961
ber01-VHDL13_DWON_131839-2604131839-dsw--0-ia5 13-Apr-2026 18:39:11 2972
ber01-VHDL13_DWON_132011-2604132011-dsw--0-ia5 13-Apr-2026 20:11:42 2941
ber01-VHDL13_DWON_132123-2604132123-dsw--0-ia5 13-Apr-2026 21:23:11 2935
ber01-VHDL13_DWON_140004-2604140004-dsw--0-ia5 14-Apr-2026 00:04:42 3277
ber01-VHDL13_DWON_140131-2604140131-dsw--0-ia5 14-Apr-2026 01:31:38 3254
ber01-VHDL13_DWON_140249-2604140249-dsw--0-ia5 14-Apr-2026 02:49:22 3254
ber01-VHDL13_DWON_140516-2604140516-dsw--0-ia5 14-Apr-2026 05:16:41 2951
ber01-VHDL13_DWON_140559-2604140559-dsw--0-ia5 14-Apr-2026 05:59:26 2951
ber01-VHDL13_DWON_140600-2604140600-dsw--0-ia5 14-Apr-2026 06:00:07 2949
ber01-VHDL13_DWON_140734-2604140734-dsw--0-ia5 14-Apr-2026 07:34:21 2949
ber01-VHDL13_DWON_140849-2604140849-dsw--0-ia5 14-Apr-2026 08:49:47 2949
ber01-VHDL13_DWON_141455-2604141455-dsw--0-ia5 14-Apr-2026 14:55:52 2354
ber01-VHDL13_DWON_141644-2604141644-dsw--0-ia5 14-Apr-2026 16:44:06 2354
ber01-VHDL13_DWON_141812-2604141812-dsw--0-ia5 14-Apr-2026 18:12:27 2611
ber01-VHDL13_DWON_142147-2604142147-dsw--0-ia5 14-Apr-2026 21:47:16 2581
ber01-VHDL13_DWON_150004-2604150004-dsw--0-ia5 15-Apr-2026 00:04:31 3257
ber01-VHDL13_DWON_150142-2604150142-dsw--0-ia5 15-Apr-2026 01:42:27 3239
ber01-VHDL13_DWON_150246-2604150246-dsw--0-ia5 15-Apr-2026 02:46:28 3239
ber01-VHDL13_DWON_150457-2604150457-dsw--0-ia5 15-Apr-2026 04:57:41 3068
ber01-VHDL13_DWON_150544-2604150544-dsw--0-ia5 15-Apr-2026 05:44:07 3068
ber01-VHDL13_DWON_150742-2604150742-dsw--0-ia5 15-Apr-2026 07:42:37 3068
ber01-VHDL13_DWON_151119-2604151119-dsw--0-ia5 15-Apr-2026 11:19:27 3181
ber01-VHDL13_DWON_151222-2604151222-dsw--0-ia5 15-Apr-2026 12:22:37 3174
ber01-VHDL13_DWON_151318-2604151318-dsw--0-ia5 15-Apr-2026 13:18:36 3174
ber01-VHDL13_DWON_151333-2604151333-dsw--0-ia5 15-Apr-2026 13:33:49 2710
ber01-VHDL13_DWON_151407-2604151407-dsw--0-ia5 15-Apr-2026 14:07:21 2710
ber01-VHDL13_DWPG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2351
ber01-VHDL13_DWPG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 2529
ber01-VHDL13_DWPG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:02 2722
ber01-VHDL13_DWPG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2605
ber01-VHDL13_DWPG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2311
ber01-VHDL13_DWPG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2147
ber01-VHDL13_DWPG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:01 2266
ber01-VHDL13_DWPG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2417
ber01-VHDL13_DWPH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 2325
ber01-VHDL13_DWPH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:10 2450
ber01-VHDL13_DWPH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:02 2857
ber01-VHDL13_DWPH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2762
ber01-VHDL13_DWPH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2384
ber01-VHDL13_DWPH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:09 2316
ber01-VHDL13_DWPH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:01 2444
ber01-VHDL13_DWPH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2793
ber01-VHDL13_DWSG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:30:12 1935
ber01-VHDL13_DWSG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:30:04 2183
ber01-VHDL13_DWSG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:18 2055
ber01-VHDL13_DWSG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:30:13 2109
ber01-VHDL13_DWSG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:30:13 2078
ber01-VHDL13_DWSG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:30:04 2268
ber01-VHDL13_DWSG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2198
ber01-VHDL13_DWSG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:30:09 2199
ber01-VHDL17_DWOG_141200-2604141200-dsw--0-ia5 14-Apr-2026 12:03:46 2887
ber01-VHDL17_DWOG_151200-2604151200-dsw--0-ia5 15-Apr-2026 11:59:17 2954
swis2-VHDL20_DWEG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2539
swis2-VHDL20_DWEG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2600
swis2-VHDL20_DWEG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:02 2742
swis2-VHDL20_DWEG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2735
swis2-VHDL20_DWEG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2518
swis2-VHDL20_DWEG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2565
swis2-VHDL20_DWEG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:07 2580
swis2-VHDL20_DWEG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:01 2582
swis2-VHDL20_DWEH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2709
swis2-VHDL20_DWEH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2678
swis2-VHDL20_DWEH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:02 2672
swis2-VHDL20_DWEH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2695
swis2-VHDL20_DWEH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2717
swis2-VHDL20_DWEH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2685
swis2-VHDL20_DWEH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:07 2640
swis2-VHDL20_DWEH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:01 2691
swis2-VHDL20_DWEI_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2615
swis2-VHDL20_DWEI_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2552
swis2-VHDL20_DWEI_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:02 2693
swis2-VHDL20_DWEI_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2696
swis2-VHDL20_DWEI_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2737
swis2-VHDL20_DWEI_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2759
swis2-VHDL20_DWEI_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:07 2790
swis2-VHDL20_DWEI_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:01 2855
swis2-VHDL20_DWHG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2867
swis2-VHDL20_DWHG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 3553
swis2-VHDL20_DWHG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3552
swis2-VHDL20_DWHG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3890
swis2-VHDL20_DWHG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2727
swis2-VHDL20_DWHG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:07 2670
swis2-VHDL20_DWHG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2670
swis2-VHDL20_DWHG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3155
swis2-VHDL20_DWHH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2853
swis2-VHDL20_DWHH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 3421
swis2-VHDL20_DWHH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3423
swis2-VHDL20_DWHH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3875
swis2-VHDL20_DWHH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2637
swis2-VHDL20_DWHH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2669
swis2-VHDL20_DWHH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2672
swis2-VHDL20_DWHH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3117
swis2-VHDL20_DWLG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2789
swis2-VHDL20_DWLG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2610
swis2-VHDL20_DWLG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 2701
swis2-VHDL20_DWLG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2912
swis2-VHDL20_DWLG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2750
swis2-VHDL20_DWLG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2757
swis2-VHDL20_DWLG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:17 2731
swis2-VHDL20_DWLG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 2536
swis2-VHDL20_DWLH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:10 2541
swis2-VHDL20_DWLH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2457
swis2-VHDL20_DWLH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 2790
swis2-VHDL20_DWLH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2919
swis2-VHDL20_DWLH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2698
swis2-VHDL20_DWLH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2747
swis2-VHDL20_DWLH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:15 2801
swis2-VHDL20_DWLH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 2876
swis2-VHDL20_DWLI_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2587
swis2-VHDL20_DWLI_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2447
swis2-VHDL20_DWLI_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 2810
swis2-VHDL20_DWLI_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2961
swis2-VHDL20_DWLI_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2826
swis2-VHDL20_DWLI_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2871
swis2-VHDL20_DWLI_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:15 2866
swis2-VHDL20_DWLI_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 2934
swis2-VHDL20_DWMG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2599
swis2-VHDL20_DWMG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2939
swis2-VHDL20_DWMG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:06 2894
swis2-VHDL20_DWMG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3022
swis2-VHDL20_DWMG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:05 2478
swis2-VHDL20_DWMG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2725
swis2-VHDL20_DWMG_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:31:54 2773
swis2-VHDL20_DWMG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:03 3145
swis2-VHDL20_DWMG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3136
swis2-VHDL20_DWMO_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2723
swis2-VHDL20_DWMO_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 3041
swis2-VHDL20_DWMO_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:06 3002
swis2-VHDL20_DWMO_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3201
swis2-VHDL20_DWMO_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:05 2533
swis2-VHDL20_DWMO_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2850
swis2-VHDL20_DWMO_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:37:33 2894
swis2-VHDL20_DWMO_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:03 2895
swis2-VHDL20_DWMO_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3355
swis2-VHDL20_DWMP_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2354
swis2-VHDL20_DWMP_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2653
swis2-VHDL20_DWMP_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:06 2659
swis2-VHDL20_DWMP_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2784
swis2-VHDL20_DWMP_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:05 2288
swis2-VHDL20_DWMP_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2821
swis2-VHDL20_DWMP_150200_COR-2604150200-dsw--0-ia5 15-Apr-2026 03:37:50 2724
swis2-VHDL20_DWMP_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:03 2878
swis2-VHDL20_DWMP_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3098
swis2-VHDL20_DWPG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2812
swis2-VHDL20_DWPG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2859
swis2-VHDL20_DWPG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3049
swis2-VHDL20_DWPG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3068
swis2-VHDL20_DWPG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2774
swis2-VHDL20_DWPG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2477
swis2-VHDL20_DWPG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:15 2595
swis2-VHDL20_DWPG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 2879
swis2-VHDL20_DWPH_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2787
swis2-VHDL20_DWPH_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2780
swis2-VHDL20_DWPH_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:00:16 3186
swis2-VHDL20_DWPH_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 3225
swis2-VHDL20_DWPH_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:12 2847
swis2-VHDL20_DWPH_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:07 2645
swis2-VHDL20_DWPH_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:00:15 2775
swis2-VHDL20_DWPH_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:06 3255
swis2-VHDL20_DWSG_131800-2604131800-dsw--0-ia5 13-Apr-2026 18:45:09 2291
swis2-VHDL20_DWSG_140200-2604140200-dsw--0-ia5 14-Apr-2026 02:45:09 2529
swis2-VHDL20_DWSG_140400-2604140400-dsw--0-ia5 14-Apr-2026 05:15:02 2409
swis2-VHDL20_DWSG_140800-2604140800-dsw--0-ia5 14-Apr-2026 08:45:13 2611
swis2-VHDL20_DWSG_141800-2604141800-dsw--0-ia5 14-Apr-2026 18:45:05 2434
swis2-VHDL20_DWSG_150200-2604150200-dsw--0-ia5 15-Apr-2026 02:45:06 2614
swis2-VHDL20_DWSG_150400-2604150400-dsw--0-ia5 15-Apr-2026 05:15:07 2554
swis2-VHDL20_DWSG_150800-2604150800-dsw--0-ia5 15-Apr-2026 08:45:01 2700
wst04-VHDL20_DWEG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:17 239577
wst04-VHDL20_DWEG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 240144
wst04-VHDL20_DWEG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:12 239609
wst04-VHDL20_DWEG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:18 240589
wst04-VHDL20_DWEG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:12 238948
wst04-VHDL20_DWEG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 239978
wst04-VHDL20_DWEG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:11 238823
wst04-VHDL20_DWEG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:12 239362
wst04-VHDL20_DWEH_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:12 239340
wst04-VHDL20_DWEH_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 239679
wst04-VHDL20_DWEH_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:12 239567
wst04-VHDL20_DWEH_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:18 239260
wst04-VHDL20_DWEH_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:12 242546
wst04-VHDL20_DWEH_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 243130
wst04-VHDL20_DWEH_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:11 242355
wst04-VHDL20_DWEH_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:16 242353
wst04-VHDL20_DWEI_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:17 339622
wst04-VHDL20_DWEI_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 340251
wst04-VHDL20_DWEI_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:18 340140
wst04-VHDL20_DWEI_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:18 340274
wst04-VHDL20_DWEI_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:12 341364
wst04-VHDL20_DWEI_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 341739
wst04-VHDL20_DWEI_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:18 341486
wst04-VHDL20_DWEI_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:12 341761
wst04-VHDL20_DWHG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:21 347097
wst04-VHDL20_DWHG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 348358
wst04-VHDL20_DWHG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:12 349024
wst04-VHDL20_DWHG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:13 349149
wst04-VHDL20_DWHG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:17 352561
wst04-VHDL20_DWHG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 352269
wst04-VHDL20_DWHG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:13 352129
wst04-VHDL20_DWHG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 352325
wst04-VHDL20_DWHH_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:17 326665
wst04-VHDL20_DWHH_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 327616
wst04-VHDL20_DWHH_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:12 328442
wst04-VHDL20_DWHH_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:13 328414
wst04-VHDL20_DWHH_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:17 336607
wst04-VHDL20_DWHH_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 336412
wst04-VHDL20_DWHH_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:13 336297
wst04-VHDL20_DWHH_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 335963
wst04-VHDL20_DWLG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:25 333812
wst04-VHDL20_DWLG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:27 333762
wst04-VHDL20_DWLG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:42 333299
wst04-VHDL20_DWLG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:32 333954
wst04-VHDL20_DWLG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:21 330976
wst04-VHDL20_DWLG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 331510
wst04-VHDL20_DWLG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:41 331169
wst04-VHDL20_DWLG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 331464
wst04-VHDL20_DWLH_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:21 332345
wst04-VHDL20_DWLH_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 332303
wst04-VHDL20_DWLH_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:42 331836
wst04-VHDL20_DWLH_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:26 333282
wst04-VHDL20_DWLH_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:27 341157
wst04-VHDL20_DWLH_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 341256
wst04-VHDL20_DWLH_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:41 340230
wst04-VHDL20_DWLH_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:42 340427
wst04-VHDL20_DWLI_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:21 330906
wst04-VHDL20_DWLI_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:27 330803
wst04-VHDL20_DWLI_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:42 330672
wst04-VHDL20_DWLI_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:32 331832
wst04-VHDL20_DWLI_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:21 331387
wst04-VHDL20_DWLI_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 331417
wst04-VHDL20_DWLI_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:41 331268
wst04-VHDL20_DWLI_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:42 331460
wst04-VHDL20_DWMG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:12 552854
wst04-VHDL20_DWMG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 553719
wst04-VHDL20_DWMG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:16 553921
wst04-VHDL20_DWMG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:22 554863
wst04-VHDL20_DWMG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:21 547728
wst04-VHDL20_DWMG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 548017
wst04-VHDL20_DWMG_150200_COR-2604150200-omedes-..> 15-Apr-2026 03:32:04 548125
wst04-VHDL20_DWMG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:18 549381
wst04-VHDL20_DWMG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 549736
wst04-VHDL20_DWMO_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:12 450485
wst04-VHDL20_DWMO_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 451294
wst04-VHDL20_DWMO_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:16 451962
wst04-VHDL20_DWMO_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:22 452853
wst04-VHDL20_DWMO_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:17 451680
wst04-VHDL20_DWMO_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 451363
wst04-VHDL20_DWMO_150200_COR-2604150200-omedes-..> 15-Apr-2026 03:37:41 451420
wst04-VHDL20_DWMO_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:18 452655
wst04-VHDL20_DWMO_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:24 453846
wst04-VHDL20_DWMP_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:17 551216
wst04-VHDL20_DWMP_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 551372
wst04-VHDL20_DWMP_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:22 552713
wst04-VHDL20_DWMP_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:22 553160
wst04-VHDL20_DWMP_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:17 536261
wst04-VHDL20_DWMP_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 535738
wst04-VHDL20_DWMP_150200_COR-2604150200-omedes-..> 15-Apr-2026 03:38:00 535804
wst04-VHDL20_DWMP_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:22 536722
wst04-VHDL20_DWMP_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 538661
wst04-VHDL20_DWPG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:25 339822
wst04-VHDL20_DWPG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:27 339604
wst04-VHDL20_DWPG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:32 339502
wst04-VHDL20_DWPG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:26 383608
wst04-VHDL20_DWPG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:27 346836
wst04-VHDL20_DWPG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 346794
wst04-VHDL20_DWPG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:31 346194
wst04-VHDL20_DWPG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 390921
wst04-VHDL20_DWPH_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:21 285377
wst04-VHDL20_DWPH_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 240554
wst04-VHDL20_DWPH_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:00:32 240578
wst04-VHDL20_DWPH_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:26 285316
wst04-VHDL20_DWPH_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:21 289086
wst04-VHDL20_DWPH_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 244549
wst04-VHDL20_DWPH_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:00:31 244124
wst04-VHDL20_DWPH_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 289659
wst04-VHDL20_DWSG_131800-2604131800-omedes--0.pdf 13-Apr-2026 18:45:12 340398
wst04-VHDL20_DWSG_140200-2604140200-omedes--0.pdf 14-Apr-2026 02:45:23 340736
wst04-VHDL20_DWSG_140400-2604140400-omedes--0.pdf 14-Apr-2026 05:15:12 341118
wst04-VHDL20_DWSG_140800-2604140800-omedes--0.pdf 14-Apr-2026 08:45:13 341468
wst04-VHDL20_DWSG_141800-2604141800-omedes--0.pdf 14-Apr-2026 18:45:12 340448
wst04-VHDL20_DWSG_150200-2604150200-omedes--0.pdf 15-Apr-2026 02:45:26 341117
wst04-VHDL20_DWSG_150400-2604150400-omedes--0.pdf 15-Apr-2026 05:15:18 341173
wst04-VHDL20_DWSG_150800-2604150800-omedes--0.pdf 15-Apr-2026 08:45:36 341083