Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Mar-2026 14:39:20 3825
FPDL13_DWMZ_230600 23-Mar-2026 14:06:14 4163
SXDL31_DWAV_220800 22-Mar-2026 08:33:47 10590
SXDL31_DWAV_221800 22-Mar-2026 17:23:09 6497
SXDL31_DWAV_230800 23-Mar-2026 08:59:30 11247
SXDL31_DWAV_231800 23-Mar-2026 16:38:29 8102
SXDL31_DWAV_LATEST 23-Mar-2026 16:38:29 8102
SXDL33_DWAV_220000 22-Mar-2026 11:28:43 13778
SXDL33_DWAV_230000 23-Mar-2026 11:19:19 8609
SXDL33_DWAV_LATEST 23-Mar-2026 11:19:19 8609
ber01-FWDL39_DWMS_221230-2603221230-dsw--0-ia5 22-Mar-2026 11:48:01 1093
ber01-FWDL39_DWMS_231230-2603231230-dsw--0-ia5 23-Mar-2026 12:48:21 1162
ber01-VHDL13_DWEH_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:13 2438
ber01-VHDL13_DWEH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:16 2360
ber01-VHDL13_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2449
ber01-VHDL13_DWEH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:17 2777
ber01-VHDL13_DWEH_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:17 2684
ber01-VHDL13_DWEH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:16 3113
ber01-VHDL13_DWEH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:12 3324
ber01-VHDL13_DWEH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:12 3570
ber01-VHDL13_DWHG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 3057
ber01-VHDL13_DWHG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 3440
ber01-VHDL13_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 3231
ber01-VHDL13_DWHG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3595
ber01-VHDL13_DWHG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3595
ber01-VHDL13_DWHG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 3587
ber01-VHDL13_DWHG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:10 3494
ber01-VHDL13_DWHG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 3761
ber01-VHDL13_DWHH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2770
ber01-VHDL13_DWHH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2735
ber01-VHDL13_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 2620
ber01-VHDL13_DWHH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3138
ber01-VHDL13_DWHH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3138
ber01-VHDL13_DWHH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 3100
ber01-VHDL13_DWHH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:10 2849
ber01-VHDL13_DWHH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 3363
ber01-VHDL13_DWLG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1948
ber01-VHDL13_DWLG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1842
ber01-VHDL13_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1821
ber01-VHDL13_DWLG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2062
ber01-VHDL13_DWLG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2226
ber01-VHDL13_DWLG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2543
ber01-VHDL13_DWLG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2313
ber01-VHDL13_DWLG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3028
ber01-VHDL13_DWLH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 2000
ber01-VHDL13_DWLH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1984
ber01-VHDL13_DWLH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1961
ber01-VHDL13_DWLH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2196
ber01-VHDL13_DWLH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2359
ber01-VHDL13_DWLH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2713
ber01-VHDL13_DWLH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2558
ber01-VHDL13_DWLH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3180
ber01-VHDL13_DWLI_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1909
ber01-VHDL13_DWLI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1851
ber01-VHDL13_DWLI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1835
ber01-VHDL13_DWLI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2076
ber01-VHDL13_DWLI_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2306
ber01-VHDL13_DWLI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2722
ber01-VHDL13_DWLI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2541
ber01-VHDL13_DWLI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3032
ber01-VHDL13_DWMG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 2899
ber01-VHDL13_DWMG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2680
ber01-VHDL13_DWMG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2383
ber01-VHDL13_DWMG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2907
ber01-VHDL13_DWMG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 2798
ber01-VHDL13_DWMG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2649
ber01-VHDL13_DWMG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2214
ber01-VHDL13_DWMG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2888
ber01-VHDL13_DWMO_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 2669
ber01-VHDL13_DWMO_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2508
ber01-VHDL13_DWMO_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL13_DWMO_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2755
ber01-VHDL13_DWMO_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 2683
ber01-VHDL13_DWMO_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2458
ber01-VHDL13_DWMO_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2458
ber01-VHDL13_DWMO_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2663
ber01-VHDL13_DWMP_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 3086
ber01-VHDL13_DWMP_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2897
ber01-VHDL13_DWMP_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2516
ber01-VHDL13_DWMP_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3109
ber01-VHDL13_DWMP_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 3001
ber01-VHDL13_DWMP_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2611
ber01-VHDL13_DWMP_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2191
ber01-VHDL13_DWMP_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2857
ber01-VHDL13_DWOG_220300-2603220300-dsw--0-ia5 22-Mar-2026 04:00:01 3379
ber01-VHDL13_DWOG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 3340
ber01-VHDL13_DWOG_221700-2603221700-dsw--0-ia5 22-Mar-2026 19:00:01 3180
ber01-VHDL13_DWOG_230300-2603230300-dsw--0-ia5 23-Mar-2026 04:00:02 3882
ber01-VHDL13_DWOG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 3827
ber01-VHDL13_DWOG_231700-2603231700-dsw--0-ia5 23-Mar-2026 19:00:06 4444
ber01-VHDL13_DWOH_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:13 2658
ber01-VHDL13_DWOH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:16 2528
ber01-VHDL13_DWOH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2598
ber01-VHDL13_DWOH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:11 2998
ber01-VHDL13_DWOH_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:11 2689
ber01-VHDL13_DWOH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:16 2882
ber01-VHDL13_DWOH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:16 3100
ber01-VHDL13_DWOH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:12 3308
ber01-VHDL13_DWOI_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:17 2429
ber01-VHDL13_DWOI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:12 2397
ber01-VHDL13_DWOI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:12 2297
ber01-VHDL13_DWOI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:11 2785
ber01-VHDL13_DWOI_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:17 2707
ber01-VHDL13_DWOI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:12 2877
ber01-VHDL13_DWOI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:12 3091
ber01-VHDL13_DWOI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:16 3312
ber01-VHDL13_DWON_220341-2603220341-dsw--0-ia5 22-Mar-2026 03:41:31 3129
ber01-VHDL13_DWON_220627-2603220627-dsw--0-ia5 22-Mar-2026 06:27:27 3302
ber01-VHDL13_DWON_220704-2603220704-dsw--0-ia5 22-Mar-2026 07:04:37 3278
ber01-VHDL13_DWON_220921-2603220921-dsw--0-ia5 22-Mar-2026 09:21:29 3284
ber01-VHDL13_DWON_221533-2603221533-dsw--0-ia5 22-Mar-2026 15:33:24 2745
ber01-VHDL13_DWON_221731-2603221731-dsw--0-ia5 22-Mar-2026 17:32:03 2745
ber01-VHDL13_DWON_221752-2603221752-dsw--0-ia5 22-Mar-2026 17:52:23 3119
ber01-VHDL13_DWON_221937-2603221937-dsw--0-ia5 22-Mar-2026 19:37:28 3120
ber01-VHDL13_DWON_222228-2603222228-dsw--0-ia5 22-Mar-2026 22:28:57 3118
ber01-VHDL13_DWON_230000-2603230000-dsw--0-ia5 23-Mar-2026 00:00:22 3800
ber01-VHDL13_DWON_230137-2603230137-dsw--0-ia5 23-Mar-2026 01:37:26 3771
ber01-VHDL13_DWON_230340-2603230340-dsw--0-ia5 23-Mar-2026 03:41:03 3790
ber01-VHDL13_DWON_230628-2603230628-dsw--0-ia5 23-Mar-2026 06:28:47 3388
ber01-VHDL13_DWON_230658-2603230658-dsw--0-ia5 23-Mar-2026 06:58:27 3572
ber01-VHDL13_DWON_230733-2603230733-dsw--0-ia5 23-Mar-2026 07:33:27 3584
ber01-VHDL13_DWON_230842-2603230842-dsw--0-ia5 23-Mar-2026 08:42:47 3584
ber01-VHDL13_DWON_231045-2603231045-dsw--0-ia5 23-Mar-2026 10:45:57 3762
ber01-VHDL13_DWON_231516-2603231516-dsw--0-ia5 23-Mar-2026 15:16:51 3870
ber01-VHDL13_DWON_231522-2603231522-dsw--0-ia5 23-Mar-2026 15:23:01 3870
ber01-VHDL13_DWON_231525-2603231525-dsw--0-ia5 23-Mar-2026 15:25:42 3870
ber01-VHDL13_DWON_231753-2603231753-dsw--0-ia5 23-Mar-2026 17:53:21 3465
ber01-VHDL13_DWON_231846-2603231846-dsw--0-ia5 23-Mar-2026 18:46:08 3465
ber01-VHDL13_DWON_231942-2603231942-dsw--0-ia5 23-Mar-2026 19:42:46 3791
ber01-VHDL13_DWON_232230-2603232230-dsw--0-ia5 23-Mar-2026 22:30:21 3785
ber01-VHDL13_DWON_240003-2603240003-dsw--0-ia5 24-Mar-2026 00:03:07 4493
ber01-VHDL13_DWON_240124-2603240124-dsw--0-ia5 24-Mar-2026 01:24:17 4459
ber01-VHDL13_DWPG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1771
ber01-VHDL13_DWPG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1751
ber01-VHDL13_DWPG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1745
ber01-VHDL13_DWPG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 1947
ber01-VHDL13_DWPG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 1911
ber01-VHDL13_DWPG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 1914
ber01-VHDL13_DWPG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 1933
ber01-VHDL13_DWPG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 2259
ber01-VHDL13_DWPH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1984
ber01-VHDL13_DWPH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1903
ber01-VHDL13_DWPH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1868
ber01-VHDL13_DWPH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2142
ber01-VHDL13_DWPH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2002
ber01-VHDL13_DWPH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2009
ber01-VHDL13_DWPH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2171
ber01-VHDL13_DWPH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 2869
ber01-VHDL13_DWSG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2665
ber01-VHDL13_DWSG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 2658
ber01-VHDL13_DWSG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL13_DWSG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2865
ber01-VHDL13_DWSG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2871
ber01-VHDL13_DWSG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2920
ber01-VHDL13_DWSG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2589
ber01-VHDL13_DWSG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3061
ber01-VHDL17_DWOG_221200-2603221200-dsw--0-ia5 22-Mar-2026 12:50:40 4087
ber01-VHDL17_DWOG_231200-2603231200-dsw--0-ia5 23-Mar-2026 12:43:57 3399
swis2-VHDL20_DWEG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 3111
swis2-VHDL20_DWEG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2975
swis2-VHDL20_DWEG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 3002
swis2-VHDL20_DWEG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3022
swis2-VHDL20_DWEG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3375
swis2-VHDL20_DWEG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3008
swis2-VHDL20_DWEG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3458
swis2-VHDL20_DWEG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3526
swis2-VHDL20_DWEH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 2811
swis2-VHDL20_DWEH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2767
swis2-VHDL20_DWEH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 2859
swis2-VHDL20_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2900
swis2-VHDL20_DWEH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3199
swis2-VHDL20_DWEH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3015
swis2-VHDL20_DWEH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3714
swis2-VHDL20_DWEH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3779
swis2-VHDL20_DWEI_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 2776
swis2-VHDL20_DWEI_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2777
swis2-VHDL20_DWEI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 2918
swis2-VHDL20_DWEI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2746
swis2-VHDL20_DWEI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3179
swis2-VHDL20_DWEI_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3057
swis2-VHDL20_DWEI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3503
swis2-VHDL20_DWEI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3542
swis2-VHDL20_DWHG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 3223
swis2-VHDL20_DWHG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 3240
swis2-VHDL20_DWHG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 4124
swis2-VHDL20_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3414
swis2-VHDL20_DWHG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3781
swis2-VHDL20_DWHG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3778
swis2-VHDL20_DWHG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 4123
swis2-VHDL20_DWHG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 3677
swis2-VHDL20_DWHH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2953
swis2-VHDL20_DWHH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2956
swis2-VHDL20_DWHH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 3428
swis2-VHDL20_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2806
swis2-VHDL20_DWHH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3324
swis2-VHDL20_DWHH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3324
swis2-VHDL20_DWHH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3643
swis2-VHDL20_DWHH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 3035
swis2-VHDL20_DWLG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2484
swis2-VHDL20_DWLG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2289
swis2-VHDL20_DWLG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2330
swis2-VHDL20_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2162
swis2-VHDL20_DWLG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2403
swis2-VHDL20_DWLG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2569
swis2-VHDL20_DWLG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 3033
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