Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Dec-2025 17:18:58 5037
FPDL13_DWMZ_020600 02-Dec-2025 11:12:05 2396
SXDL31_DWAV_011800 01-Dec-2025 16:58:44 7934
SXDL31_DWAV_020800 02-Dec-2025 08:32:04 9553
SXDL31_DWAV_021800 02-Dec-2025 16:32:39 7155
SXDL31_DWAV_030800 03-Dec-2025 08:04:09 9585
SXDL31_DWAV_LATEST 03-Dec-2025 08:04:09 9585
SXDL33_DWAV_010000 01-Dec-2025 11:12:19 8361
SXDL33_DWAV_020000 02-Dec-2025 10:54:09 15934
SXDL33_DWAV_LATEST 02-Dec-2025 10:54:09 15934
ber01-FWDL39_DWMS_011230-2512011230-dsw--0-ia5 01-Dec-2025 13:36:15 1166
ber01-FWDL39_DWMS_011230_COR-2512011230-dsw--0-ia5 01-Dec-2025 13:51:41 1240
ber01-FWDL39_DWMS_021230-2512021230-dsw--0-ia5 02-Dec-2025 12:34:18 1230
ber01-VHDL13_DWEH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:17 3102
ber01-VHDL13_DWEH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:17 2485
ber01-VHDL13_DWEH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:28:12 2599
ber01-VHDL13_DWEH_020400-2512020400-dsw--0-ia5 02-Dec-2025 05:58:16 2504
ber01-VHDL13_DWEH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:28:17 2289
ber01-VHDL13_DWEH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:28:17 2502
ber01-VHDL13_DWEH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:29:34 2880
ber01-VHDL13_DWEH_030400-2512030400-dsw--0-ia5 03-Dec-2025 05:58:12 2711
ber01-VHDL13_DWHG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2908
ber01-VHDL13_DWHG_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:55:26 3161
ber01-VHDL13_DWHG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:09 2964
ber01-VHDL13_DWHG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:06 2797
ber01-VHDL13_DWHG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2797
ber01-VHDL13_DWHG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2475
ber01-VHDL13_DWHG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:06 2288
ber01-VHDL13_DWHG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:09 2677
ber01-VHDL13_DWHG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:07 2677
ber01-VHDL13_DWHH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2683
ber01-VHDL13_DWHH_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:54:41 2743
ber01-VHDL13_DWHH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:09 2551
ber01-VHDL13_DWHH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:06 2434
ber01-VHDL13_DWHH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2467
ber01-VHDL13_DWHH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2342
ber01-VHDL13_DWHH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:06 2040
ber01-VHDL13_DWHH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:09 2145
ber01-VHDL13_DWHH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:07 2145
ber01-VHDL13_DWLG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2799
ber01-VHDL13_DWLG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2510
ber01-VHDL13_DWLG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2525
ber01-VHDL13_DWLG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:02 2489
ber01-VHDL13_DWLG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2496
ber01-VHDL13_DWLG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 2604
ber01-VHDL13_DWLG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 3025
ber01-VHDL13_DWLG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 3047
ber01-VHDL13_DWLH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2259
ber01-VHDL13_DWLH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2174
ber01-VHDL13_DWLH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2220
ber01-VHDL13_DWLH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:02 2199
ber01-VHDL13_DWLH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2235
ber01-VHDL13_DWLH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 1907
ber01-VHDL13_DWLH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2246
ber01-VHDL13_DWLH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2203
ber01-VHDL13_DWLI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2699
ber01-VHDL13_DWLI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2671
ber01-VHDL13_DWLI_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2565
ber01-VHDL13_DWLI_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:02 2520
ber01-VHDL13_DWLI_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2428
ber01-VHDL13_DWLI_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 2386
ber01-VHDL13_DWLI_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2783
ber01-VHDL13_DWLI_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2803
ber01-VHDL13_DWMG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2531
ber01-VHDL13_DWMG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2199
ber01-VHDL13_DWMG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2419
ber01-VHDL13_DWMG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:06 2427
ber01-VHDL13_DWMG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:01 2441
ber01-VHDL13_DWMG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 2237
ber01-VHDL13_DWMG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2366
ber01-VHDL13_DWMG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2374
ber01-VHDL13_DWMO_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2403
ber01-VHDL13_DWMO_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2063
ber01-VHDL13_DWMO_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2416
ber01-VHDL13_DWMO_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:06 2424
ber01-VHDL13_DWMO_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:01 2386
ber01-VHDL13_DWMO_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 2153
ber01-VHDL13_DWMO_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2316
ber01-VHDL13_DWMO_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2316
ber01-VHDL13_DWMP_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2482
ber01-VHDL13_DWMP_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2282
ber01-VHDL13_DWMP_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2605
ber01-VHDL13_DWMP_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:06 2606
ber01-VHDL13_DWMP_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:01 2605
ber01-VHDL13_DWMP_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 2329
ber01-VHDL13_DWMP_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2431
ber01-VHDL13_DWMP_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2431
ber01-VHDL13_DWOG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 5327
ber01-VHDL13_DWOG_011700-2512011700-dsw--0-ia5 01-Dec-2025 19:00:01 4923
ber01-VHDL13_DWOG_020300-2512020300-dsw--0-ia5 02-Dec-2025 04:00:01 5626
ber01-VHDL13_DWOG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:01 4925
ber01-VHDL13_DWOG_021700-2512021700-dsw--0-ia5 02-Dec-2025 19:00:02 4114
ber01-VHDL13_DWOG_030300-2512030300-dsw--0-ia5 03-Dec-2025 04:00:02 4895
ber01-VHDL13_DWOH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:17 2783
ber01-VHDL13_DWOH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:17 2569
ber01-VHDL13_DWOH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:28:12 2695
ber01-VHDL13_DWOH_020400-2512020400-dsw--0-ia5 02-Dec-2025 05:58:13 2919
ber01-VHDL13_DWOH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:28:17 2537
ber01-VHDL13_DWOH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:28:17 2705
ber01-VHDL13_DWOH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:29:34 2996
ber01-VHDL13_DWOH_030400-2512030400-dsw--0-ia5 03-Dec-2025 05:58:18 2752
ber01-VHDL13_DWOI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:11 2948
ber01-VHDL13_DWOI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:11 2950
ber01-VHDL13_DWOI_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:28:12 2817
ber01-VHDL13_DWOI_020400-2512020400-dsw--0-ia5 02-Dec-2025 05:58:13 2738
ber01-VHDL13_DWOI_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:28:11 2521
ber01-VHDL13_DWOI_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:28:11 2708
ber01-VHDL13_DWOI_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:29:34 2999
ber01-VHDL13_DWOI_030400-2512030400-dsw--0-ia5 03-Dec-2025 05:58:18 2562
ber01-VHDL13_DWON_010927-2512010927-dsw--0-ia5 01-Dec-2025 09:27:57 4569
ber01-VHDL13_DWON_011244-2512011244-dsw--0-ia5 01-Dec-2025 12:44:47 4514
ber01-VHDL13_DWON_011519-2512011519-dsw--0-ia5 01-Dec-2025 15:19:52 3831
ber01-VHDL13_DWON_011737-2512011737-dsw--0-ia5 01-Dec-2025 17:37:48 4061
ber01-VHDL13_DWON_011930-2512011930-dsw--0-ia5 01-Dec-2025 19:30:29 4032
ber01-VHDL13_DWON_020001-2512020001-dsw--0-ia5 02-Dec-2025 00:01:23 4691
ber01-VHDL13_DWON_020140-2512020140-dsw--0-ia5 02-Dec-2025 01:41:01 4657
ber01-VHDL13_DWON_020347-2512020347-dsw--0-ia5 02-Dec-2025 03:47:47 4711
ber01-VHDL13_DWON_020620-2512020620-dsw--0-ia5 02-Dec-2025 06:20:41 3969
ber01-VHDL13_DWON_020702-2512020702-dsw--0-ia5 02-Dec-2025 07:02:16 4323
ber01-VHDL13_DWON_020846-2512020846-dsw--0-ia5 02-Dec-2025 08:46:26 4491
ber01-VHDL13_DWON_021030-2512021030-dsw--0-ia5 02-Dec-2025 10:31:03 4491
ber01-VHDL13_DWON_021529-2512021529-dsw--0-ia5 02-Dec-2025 15:29:20 3821
ber01-VHDL13_DWON_021632-2512021632-dsw--0-ia5 02-Dec-2025 16:33:01 3821
ber01-VHDL13_DWON_021908-2512021908-dsw--0-ia5 02-Dec-2025 19:08:42 3848
ber01-VHDL13_DWON_022217-2512022217-dsw--0-ia5 02-Dec-2025 22:17:51 3844
ber01-VHDL13_DWON_030000-2512030000-dsw--0-ia5 03-Dec-2025 00:00:11 4655
ber01-VHDL13_DWON_030133-2512030133-dsw--0-ia5 03-Dec-2025 01:34:02 4695
ber01-VHDL13_DWON_030341-2512030341-dsw--0-ia5 03-Dec-2025 03:41:21 4695
ber01-VHDL13_DWON_030426-2512030426-dsw--0-ia5 03-Dec-2025 04:27:39 4656
ber01-VHDL13_DWON_030435-2512030435-dsw--0-ia5 03-Dec-2025 04:35:20 4656
ber01-VHDL13_DWON_030630-2512030630-dsw--0-ia5 03-Dec-2025 06:30:53 4174
ber01-VHDL13_DWON_030729-2512030729-dsw--0-ia5 03-Dec-2025 07:29:08 4782
ber01-VHDL13_DWPG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2122
ber01-VHDL13_DWPG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 1790
ber01-VHDL13_DWPG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 1890
ber01-VHDL13_DWPG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:02 1806
ber01-VHDL13_DWPG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 1968
ber01-VHDL13_DWPG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 1951
ber01-VHDL13_DWPG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2292
ber01-VHDL13_DWPG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2425
ber01-VHDL13_DWPG_030400_COR-2512030400-dsw--0-ia5 03-Dec-2025 07:01:36 2631
ber01-VHDL13_DWPH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2196
ber01-VHDL13_DWPH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 1961
ber01-VHDL13_DWPH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2109
ber01-VHDL13_DWPH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:02 1984
ber01-VHDL13_DWPH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 2001
ber01-VHDL13_DWPH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 1837
ber01-VHDL13_DWPH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2122
ber01-VHDL13_DWPH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:00 2419
ber01-VHDL13_DWSG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2965
ber01-VHDL13_DWSG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2626
ber01-VHDL13_DWSG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:30:01 2884
ber01-VHDL13_DWSG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:08 3041
ber01-VHDL13_DWSG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:30:11 3027
ber01-VHDL13_DWSG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:30:02 3025
ber01-VHDL13_DWSG_021800_COR-2512021800-dsw--0-ia5 02-Dec-2025 19:40:07 2753
ber01-VHDL13_DWSG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:30:04 2887
ber01-VHDL13_DWSG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:07 2911
ber01-VHDL17_DWOG_011200-2512011200-dsw--0-ia5 01-Dec-2025 12:03:58 3996
ber01-VHDL17_DWOG_021200-2512021200-dsw--0-ia5 02-Dec-2025 12:00:17 2892
swis2-VHDL20_DWEG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3550
swis2-VHDL20_DWEG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3094
swis2-VHDL20_DWEG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:04 3048
swis2-VHDL20_DWEG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 3347
swis2-VHDL20_DWEG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 3308
swis2-VHDL20_DWEG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 3139
swis2-VHDL20_DWEG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 3258
swis2-VHDL20_DWEG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 3260
swis2-VHDL20_DWEH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3838
swis2-VHDL20_DWEH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3025
swis2-VHDL20_DWEH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:04 3066
swis2-VHDL20_DWEH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 2840
swis2-VHDL20_DWEH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 2933
swis2-VHDL20_DWEH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2926
swis2-VHDL20_DWEH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 3022
swis2-VHDL20_DWEH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 3118
swis2-VHDL20_DWEI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3772
swis2-VHDL20_DWEI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3499
swis2-VHDL20_DWEI_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:04 3218
swis2-VHDL20_DWEI_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 3134
swis2-VHDL20_DWEI_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 3161
swis2-VHDL20_DWEI_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 3104
swis2-VHDL20_DWEI_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2846
swis2-VHDL20_DWEI_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 2986
swis2-VHDL20_DWHG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3550
swis2-VHDL20_DWHG_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:57:51 3803
swis2-VHDL20_DWHG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3147
swis2-VHDL20_DWHG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2983
swis2-VHDL20_DWHG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2980
swis2-VHDL20_DWHG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 3138
swis2-VHDL20_DWHG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2471
swis2-VHDL20_DWHG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2863
swis2-VHDL20_DWHG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:07 2860
swis2-VHDL20_DWHH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3225
swis2-VHDL20_DWHH_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:56:57 3285
swis2-VHDL20_DWHH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2737
swis2-VHDL20_DWHH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2620
swis2-VHDL20_DWHH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2653
swis2-VHDL20_DWHH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 2887
swis2-VHDL20_DWHH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2226
swis2-VHDL20_DWHH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2331
swis2-VHDL20_DWHH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:07 2331
swis2-VHDL20_DWLG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3341
swis2-VHDL20_DWLG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2910
swis2-VHDL20_DWLG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2928
swis2-VHDL20_DWLG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2875
swis2-VHDL20_DWLG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 3080
swis2-VHDL20_DWLG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 3042
swis2-VHDL20_DWLG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 3466
swis2-VHDL20_DWLG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:11 3415
swis2-VHDL20_DWLH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2812
swis2-VHDL20_DWLH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2581
swis2-VHDL20_DWLH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2630
swis2-VHDL20_DWLH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2592
swis2-VHDL20_DWLH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 2825
swis2-VHDL20_DWLH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2300
swis2-VHDL20_DWLH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 2642
swis2-VHDL20_DWLH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:11 2599
swis2-VHDL20_DWLI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3242
swis2-VHDL20_DWLI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3073
swis2-VHDL20_DWLI_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2970
swis2-VHDL20_DWLI_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2908
swis2-VHDL20_DWLI_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 2967
swis2-VHDL20_DWLI_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2774
swis2-VHDL20_DWLI_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 3174
swis2-VHDL20_DWLI_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:11 3200
swis2-VHDL20_DWMG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3087
swis2-VHDL20_DWMG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2587
swis2-VHDL20_DWMG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:06 2839
swis2-VHDL20_DWMG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 2853
swis2-VHDL20_DWMG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 3050
swis2-VHDL20_DWMG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2631
swis2-VHDL20_DWMG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2793
swis2-VHDL20_DWMG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 2770
swis2-VHDL20_DWMO_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 2969
swis2-VHDL20_DWMO_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2455
swis2-VHDL20_DWMO_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:06 2845
swis2-VHDL20_DWMO_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 2854
swis2-VHDL20_DWMO_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 3006
swis2-VHDL20_DWMO_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2551
swis2-VHDL20_DWMO_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2752
swis2-VHDL20_DWMO_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 2719
swis2-VHDL20_DWMP_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 2985
swis2-VHDL20_DWMP_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2674
swis2-VHDL20_DWMP_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:06 3034
swis2-VHDL20_DWMP_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 3032
swis2-VHDL20_DWMP_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 3222
swis2-VHDL20_DWMP_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2665
swis2-VHDL20_DWMP_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:08 2867
swis2-VHDL20_DWMP_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 2830
swis2-VHDL20_DWPG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2629
swis2-VHDL20_DWPG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2304
swis2-VHDL20_DWPG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2273
swis2-VHDL20_DWPG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2133
swis2-VHDL20_DWPG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 2484
swis2-VHDL20_DWPG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2467
swis2-VHDL20_DWPG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 2675
swis2-VHDL20_DWPG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:11 2807
swis2-VHDL20_DWPG_030400_COR-2512030400-dsw--0-ia5 03-Dec-2025 06:50:56 3017
swis2-VHDL20_DWPH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2761
swis2-VHDL20_DWPH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2475
swis2-VHDL20_DWPH_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:01 2491
swis2-VHDL20_DWPH_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:00:12 2313
swis2-VHDL20_DWPH_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:02 2517
swis2-VHDL20_DWPH_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 2353
swis2-VHDL20_DWPH_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 2504
swis2-VHDL20_DWPH_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:00:11 2806
swis2-VHDL20_DWSG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3576
swis2-VHDL20_DWSG_011300-2512011300-dsw--0-ia5 01-Dec-2025 14:45:04 3404
swis2-VHDL20_DWSG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3034
swis2-VHDL20_DWSG_020200-2512020200-dsw--0-ia5 02-Dec-2025 03:45:06 3326
swis2-VHDL20_DWSG_020400-2512020400-dsw--0-ia5 02-Dec-2025 06:15:01 3509
swis2-VHDL20_DWSG_020800-2512020800-dsw--0-ia5 02-Dec-2025 09:45:07 3736
swis2-VHDL20_DWSG_021300-2512021300-dsw--0-ia5 02-Dec-2025 14:45:04 3549
swis2-VHDL20_DWSG_021800-2512021800-dsw--0-ia5 02-Dec-2025 19:45:04 3206
swis2-VHDL20_DWSG_021800_COR-2512021800-dsw--0-ia5 02-Dec-2025 19:40:07 3210
swis2-VHDL20_DWSG_030200-2512030200-dsw--0-ia5 03-Dec-2025 03:45:02 3336
swis2-VHDL20_DWSG_030400-2512030400-dsw--0-ia5 03-Dec-2025 06:15:02 3368
wst04-VHDL20_DWEG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 226293
wst04-VHDL20_DWEG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 223788
wst04-VHDL20_DWEG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:12 224607
wst04-VHDL20_DWEG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:21 225688
wst04-VHDL20_DWEG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:21 227205
wst04-VHDL20_DWEG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:16 225434
wst04-VHDL20_DWEG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:16 226638
wst04-VHDL20_DWEG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:27 226047
wst04-VHDL20_DWEH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 225613
wst04-VHDL20_DWEH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 224144
wst04-VHDL20_DWEH_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:16 225541
wst04-VHDL20_DWEH_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:27 224667
wst04-VHDL20_DWEH_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:21 227497
wst04-VHDL20_DWEH_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:16 227111
wst04-VHDL20_DWEH_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:10 228267
wst04-VHDL20_DWEH_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:21 227965
wst04-VHDL20_DWEI_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 313146
wst04-VHDL20_DWEI_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 313430
wst04-VHDL20_DWEI_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:16 314194
wst04-VHDL20_DWEI_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:27 312822
wst04-VHDL20_DWEI_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:27 316685
wst04-VHDL20_DWEI_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:16 316178
wst04-VHDL20_DWEI_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:16 316659
wst04-VHDL20_DWEI_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:27 316421
wst04-VHDL20_DWHG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:16 305173
wst04-VHDL20_DWHG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 303931
wst04-VHDL20_DWHG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:12 304185
wst04-VHDL20_DWHG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:12 304111
wst04-VHDL20_DWHG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:17 308473
wst04-VHDL20_DWHG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:22 306827
wst04-VHDL20_DWHG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:12 307347
wst04-VHDL20_DWHG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:11 307353
wst04-VHDL20_DWHH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:12 294158
wst04-VHDL20_DWHH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 293375
wst04-VHDL20_DWHH_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:12 293472
wst04-VHDL20_DWHH_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:12 293509
wst04-VHDL20_DWHH_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:17 300129
wst04-VHDL20_DWHH_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:16 299128
wst04-VHDL20_DWHH_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:12 299249
wst04-VHDL20_DWHH_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:11 299287
wst04-VHDL20_DWLG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:26 301799
wst04-VHDL20_DWLG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:26 300768
wst04-VHDL20_DWLG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:22 301193
wst04-VHDL20_DWLG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:41 301289
wst04-VHDL20_DWLG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:37 308305
wst04-VHDL20_DWLG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:26 307737
wst04-VHDL20_DWLG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:26 308834
wst04-VHDL20_DWLG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:42 308742
wst04-VHDL20_DWLH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 307555
wst04-VHDL20_DWLH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 307239
wst04-VHDL20_DWLH_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:27 307243
wst04-VHDL20_DWLH_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:41 307281
wst04-VHDL20_DWLH_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:31 307484
wst04-VHDL20_DWLH_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:22 305725
wst04-VHDL20_DWLH_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:20 306613
wst04-VHDL20_DWLH_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:42 306983
wst04-VHDL20_DWLI_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 306103
wst04-VHDL20_DWLI_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 305681
wst04-VHDL20_DWLI_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:22 305590
wst04-VHDL20_DWLI_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:41 305627
wst04-VHDL20_DWLI_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:31 301844
wst04-VHDL20_DWLI_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:22 300760
wst04-VHDL20_DWLI_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:26 301875
wst04-VHDL20_DWLI_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:42 301608
wst04-VHDL20_DWMG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 491703
wst04-VHDL20_DWMG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 490658
wst04-VHDL20_DWMG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:16 490929
wst04-VHDL20_DWMG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:21 490870
wst04-VHDL20_DWMG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:17 511795
wst04-VHDL20_DWMG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:12 511342
wst04-VHDL20_DWMG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:22 511393
wst04-VHDL20_DWMG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:21 511359
wst04-VHDL20_DWMO_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 391651
wst04-VHDL20_DWMO_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 389727
wst04-VHDL20_DWMO_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:22 390983
wst04-VHDL20_DWMO_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:21 391459
wst04-VHDL20_DWMO_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:11 401693
wst04-VHDL20_DWMO_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:12 399877
wst04-VHDL20_DWMO_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:16 400679
wst04-VHDL20_DWMO_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:17 401197
wst04-VHDL20_DWMP_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 523370
wst04-VHDL20_DWMP_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:16 522408
wst04-VHDL20_DWMP_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:22 521596
wst04-VHDL20_DWMP_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:21 522667
wst04-VHDL20_DWMP_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:17 544223
wst04-VHDL20_DWMP_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:16 543700
wst04-VHDL20_DWMP_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:22 542723
wst04-VHDL20_DWMP_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:21 543691
wst04-VHDL20_DWPG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 354363
wst04-VHDL20_DWPG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:26 309133
wst04-VHDL20_DWPG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:27 309146
wst04-VHDL20_DWPG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:30 309230
wst04-VHDL20_DWPG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:31 364216
wst04-VHDL20_DWPG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:26 319177
wst04-VHDL20_DWPG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:26 319725
wst04-VHDL20_DWPG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:32 320200
wst04-VHDL20_DWPH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:26 267301
wst04-VHDL20_DWPH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 266784
wst04-VHDL20_DWPH_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:22 222176
wst04-VHDL20_DWPH_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:00:30 222318
wst04-VHDL20_DWPH_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:31 266941
wst04-VHDL20_DWPH_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:22 266604
wst04-VHDL20_DWPH_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:20 222509
wst04-VHDL20_DWPH_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:00:32 222840
wst04-VHDL20_DWSG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:12 333237
wst04-VHDL20_DWSG_011300-2512011300-omedes--0.pdf 01-Dec-2025 14:45:11 333186
wst04-VHDL20_DWSG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 332442
wst04-VHDL20_DWSG_020200-2512020200-omedes--0.pdf 02-Dec-2025 03:45:16 333463
wst04-VHDL20_DWSG_020400-2512020400-omedes--0.pdf 02-Dec-2025 06:15:17 333520
wst04-VHDL20_DWSG_020800-2512020800-omedes--0.pdf 02-Dec-2025 09:45:11 330956
wst04-VHDL20_DWSG_021300-2512021300-omedes--0.pdf 02-Dec-2025 14:45:12 330903
wst04-VHDL20_DWSG_021800-2512021800-omedes--0.pdf 02-Dec-2025 19:45:12 330287
wst04-VHDL20_DWSG_021800_COR-2512021800-omedes-..> 02-Dec-2025 19:40:17 330287
wst04-VHDL20_DWSG_030200-2512030200-omedes--0.pdf 03-Dec-2025 03:45:16 331513
wst04-VHDL20_DWSG_030400-2512030400-omedes--0.pdf 03-Dec-2025 06:15:17 331540