Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Feb-2026 13:23:48 2970
FPDL13_DWMZ_220600 22-Feb-2026 12:01:19 7447
SXDL31_DWAV_210800 21-Feb-2026 08:10:18 6502
SXDL31_DWAV_211800 21-Feb-2026 18:03:05 8175
SXDL31_DWAV_220800 22-Feb-2026 08:26:15 10907
SXDL31_DWAV_221800 22-Feb-2026 17:44:44 8445
SXDL31_DWAV_LATEST 22-Feb-2026 17:44:44 8445
SXDL33_DWAV_210000 21-Feb-2026 10:35:14 6594
SXDL33_DWAV_220000 22-Feb-2026 11:20:20 9521
SXDL33_DWAV_LATEST 22-Feb-2026 11:20:20 9521
ber01-FWDL39_DWMS_211230-2602211230-dsw--0-ia5 21-Feb-2026 11:57:31 1491
ber01-FWDL39_DWMS_221230-2602221230-dsw--0-ia5 22-Feb-2026 12:30:56 1717
ber01-FWDL39_DWMS_221230_COR-2602221230-dsw--0-ia5 22-Feb-2026 13:17:07 1721
ber01-VHDL13_DWEH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:12 2993
ber01-VHDL13_DWEH_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:13 2918
ber01-VHDL13_DWEH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:17 3436
ber01-VHDL13_DWEH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:28:16 2435
ber01-VHDL13_DWEH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:10 2715
ber01-VHDL13_DWEH_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2699
ber01-VHDL13_DWEH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:16 3091
ber01-VHDL13_DWEH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:18 2705
ber01-VHDL13_DWHG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 3337
ber01-VHDL13_DWHG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3226
ber01-VHDL13_DWHG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:09 3050
ber01-VHDL13_DWHG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2665
ber01-VHDL13_DWHG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 3392
ber01-VHDL13_DWHG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3403
ber01-VHDL13_DWHG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:15 3722
ber01-VHDL13_DWHG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3088
ber01-VHDL13_DWHH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2687
ber01-VHDL13_DWHH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 2665
ber01-VHDL13_DWHH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:09 2526
ber01-VHDL13_DWHH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2160
ber01-VHDL13_DWHH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 2727
ber01-VHDL13_DWHH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 2599
ber01-VHDL13_DWHH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2612
ber01-VHDL13_DWHH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2212
ber01-VHDL13_DWLG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2866
ber01-VHDL13_DWLG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2819
ber01-VHDL13_DWLG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2608
ber01-VHDL13_DWLG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2753
ber01-VHDL13_DWLG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2661
ber01-VHDL13_DWLG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2651
ber01-VHDL13_DWLG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3177
ber01-VHDL13_DWLG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3194
ber01-VHDL13_DWLH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2720
ber01-VHDL13_DWLH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2585
ber01-VHDL13_DWLH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2605
ber01-VHDL13_DWLH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2758
ber01-VHDL13_DWLH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2718
ber01-VHDL13_DWLH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2708
ber01-VHDL13_DWLH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3182
ber01-VHDL13_DWLH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3035
ber01-VHDL13_DWLI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2499
ber01-VHDL13_DWLI_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2507
ber01-VHDL13_DWLI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2606
ber01-VHDL13_DWLI_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2432
ber01-VHDL13_DWLI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2434
ber01-VHDL13_DWLI_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2424
ber01-VHDL13_DWLI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2880
ber01-VHDL13_DWLI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2755
ber01-VHDL13_DWMG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3952
ber01-VHDL13_DWMG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3794
ber01-VHDL13_DWMG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3489
ber01-VHDL13_DWMG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:02 2478
ber01-VHDL13_DWMG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3155
ber01-VHDL13_DWMG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 3153
ber01-VHDL13_DWMG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3317
ber01-VHDL13_DWMG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3065
ber01-VHDL13_DWMO_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3479
ber01-VHDL13_DWMO_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3386
ber01-VHDL13_DWMO_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3013
ber01-VHDL13_DWMO_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:02 2497
ber01-VHDL13_DWMO_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3005
ber01-VHDL13_DWMO_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2897
ber01-VHDL13_DWMO_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3156
ber01-VHDL13_DWMO_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2741
ber01-VHDL13_DWMP_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3654
ber01-VHDL13_DWMP_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3483
ber01-VHDL13_DWMP_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3238
ber01-VHDL13_DWMP_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:02 2608
ber01-VHDL13_DWMP_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3377
ber01-VHDL13_DWMP_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 3390
ber01-VHDL13_DWMP_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3506
ber01-VHDL13_DWMP_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:06 3231
ber01-VHDL13_DWOG_210300-2602210300-dsw--0-ia5 21-Feb-2026 04:00:02 5387
ber01-VHDL13_DWOG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:39:06 4533
ber01-VHDL13_DWOG_211700-2602211700-dsw--0-ia5 21-Feb-2026 19:00:01 4046
ber01-VHDL13_DWOG_220300-2602220300-dsw--0-ia5 22-Feb-2026 04:00:01 3559
ber01-VHDL13_DWOG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3932
ber01-VHDL13_DWOG_221700-2602221700-dsw--0-ia5 22-Feb-2026 19:00:06 3858
ber01-VHDL13_DWOH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:12 2927
ber01-VHDL13_DWOH_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:17 2851
ber01-VHDL13_DWOH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:17 3169
ber01-VHDL13_DWOH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:28:16 2237
ber01-VHDL13_DWOH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:16 2423
ber01-VHDL13_DWOH_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2393
ber01-VHDL13_DWOH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:16 2845
ber01-VHDL13_DWOH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:18 2647
ber01-VHDL13_DWOI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:28:16 2658
ber01-VHDL13_DWOI_210400-2602210400-dsw--0-ia5 21-Feb-2026 05:58:17 2582
ber01-VHDL13_DWOI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:28:11 2906
ber01-VHDL13_DWOI_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:28:16 2194
ber01-VHDL13_DWOI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:16 2420
ber01-VHDL13_DWOI_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2415
ber01-VHDL13_DWOI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:12 2643
ber01-VHDL13_DWOI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:12 2591
ber01-VHDL13_DWON_210222-2602210222-dsw--0-ia5 21-Feb-2026 02:22:37 4491
ber01-VHDL13_DWON_210334-2602210334-dsw--0-ia5 21-Feb-2026 03:34:54 4491
ber01-VHDL13_DWON_210630-2602210630-dsw--0-ia5 21-Feb-2026 06:30:27 4125
ber01-VHDL13_DWON_210710-2602210710-dsw--0-ia5 21-Feb-2026 07:11:01 3872
ber01-VHDL13_DWON_210938-2602210938-dsw--0-ia5 21-Feb-2026 09:38:38 3778
ber01-VHDL13_DWON_211431-2602211431-dsw--0-ia5 21-Feb-2026 14:31:16 3931
ber01-VHDL13_DWON_211531-2602211531-dsw--0-ia5 21-Feb-2026 15:31:12 3299
ber01-VHDL13_DWON_211822-2602211822-dsw--0-ia5 21-Feb-2026 18:22:51 3471
ber01-VHDL13_DWON_220100-2602220100-dsw--0-ia5 22-Feb-2026 01:00:10 3355
ber01-VHDL13_DWON_220341-2602220341-dsw--0-ia5 22-Feb-2026 03:41:37 3355
ber01-VHDL13_DWON_220628-2602220628-dsw--0-ia5 22-Feb-2026 06:28:51 3165
ber01-VHDL13_DWON_220703-2602220703-dsw--0-ia5 22-Feb-2026 07:03:46 3405
ber01-VHDL13_DWON_220853-2602220853-dsw--0-ia5 22-Feb-2026 08:53:54 3405
ber01-VHDL13_DWON_220925-2602220925-dsw--0-ia5 22-Feb-2026 09:25:26 3405
ber01-VHDL13_DWON_221549-2602221549-dsw--0-ia5 22-Feb-2026 15:49:37 2967
ber01-VHDL13_DWON_221759-2602221759-dsw--0-ia5 22-Feb-2026 17:59:07 3081
ber01-VHDL13_DWON_222336-2602222336-dsw--0-ia5 22-Feb-2026 23:36:37 3299
ber01-VHDL13_DWPG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2359
ber01-VHDL13_DWPG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2365
ber01-VHDL13_DWPG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2001
ber01-VHDL13_DWPG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2019
ber01-VHDL13_DWPG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 1971
ber01-VHDL13_DWPG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 1987
ber01-VHDL13_DWPG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:15 2646
ber01-VHDL13_DWPG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2619
ber01-VHDL13_DWPH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:09 2660
ber01-VHDL13_DWPH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:02 2673
ber01-VHDL13_DWPH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 2252
ber01-VHDL13_DWPH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:08 2568
ber01-VHDL13_DWPH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2121
ber01-VHDL13_DWPH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2177
ber01-VHDL13_DWPH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2722
ber01-VHDL13_DWPH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2632
ber01-VHDL13_DWSG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:30:03 3412
ber01-VHDL13_DWSG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3138
ber01-VHDL13_DWSG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:30:04 3370
ber01-VHDL13_DWSG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:30:02 3013
ber01-VHDL13_DWSG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 3595
ber01-VHDL13_DWSG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3520
ber01-VHDL13_DWSG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3768
ber01-VHDL13_DWSG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:06 2985
ber01-VHDL17_DWOG_211200-2602211200-dsw--0-ia5 21-Feb-2026 12:35:46 3037
ber01-VHDL17_DWOG_221200-2602221200-dsw--0-ia5 22-Feb-2026 12:59:06 3052
swis2-VHDL20_DWEG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3366
swis2-VHDL20_DWEG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 3174
swis2-VHDL20_DWEG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3649
swis2-VHDL20_DWEG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2566
swis2-VHDL20_DWEG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 2702
swis2-VHDL20_DWEG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 2715
swis2-VHDL20_DWEG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3326
swis2-VHDL20_DWEG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 2974
swis2-VHDL20_DWEH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3318
swis2-VHDL20_DWEH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 3256
swis2-VHDL20_DWEH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3941
swis2-VHDL20_DWEH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2792
swis2-VHDL20_DWEH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 3039
swis2-VHDL20_DWEH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 3036
swis2-VHDL20_DWEH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3597
swis2-VHDL20_DWEH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3060
swis2-VHDL20_DWEI_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2954
swis2-VHDL20_DWEI_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:15:02 2936
swis2-VHDL20_DWEI_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3433
swis2-VHDL20_DWEI_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2548
swis2-VHDL20_DWEI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 2715
swis2-VHDL20_DWEI_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 2768
swis2-VHDL20_DWEI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3171
swis2-VHDL20_DWEI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 2944
swis2-VHDL20_DWHG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3523
swis2-VHDL20_DWHG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 3409
swis2-VHDL20_DWHG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3586
swis2-VHDL20_DWHG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2848
swis2-VHDL20_DWHG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 3578
swis2-VHDL20_DWHG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3586
swis2-VHDL20_DWHG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 4256
swis2-VHDL20_DWHG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:06 3271
swis2-VHDL20_DWHH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 2873
swis2-VHDL20_DWHH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:06 2851
swis2-VHDL20_DWHH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3071
swis2-VHDL20_DWHH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2346
swis2-VHDL20_DWHH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 2913
swis2-VHDL20_DWHH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 2785
swis2-VHDL20_DWHH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3154
swis2-VHDL20_DWHH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:06 2398
swis2-VHDL20_DWLG_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3317
swis2-VHDL20_DWLG_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 3161
swis2-VHDL20_DWLG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3095
swis2-VHDL20_DWLG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:04 3095
swis2-VHDL20_DWLG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 3003
swis2-VHDL20_DWLG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 2992
swis2-VHDL20_DWLG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3755
swis2-VHDL20_DWLG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3535
swis2-VHDL20_DWLH_210200-2602210200-dsw--0-ia5 21-Feb-2026 03:45:04 3139
swis2-VHDL20_DWLH_210400-2602210400-dsw--0-ia5 21-Feb-2026 06:00:12 2934
swis2-VHDL20_DWLH_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 3103
swis2-VHDL20_DWLH_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:04 3107
swis2-VHDL20_DWLH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 3067
swis2-VHDL20_DWLH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 3056
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swis2-VHDL20_DWMO_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2873
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swis2-VHDL20_DWMP_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:06 2982
swis2-VHDL20_DWMP_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 3818
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swis2-VHDL20_DWMP_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:04 4042
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swis2-VHDL20_DWPG_210800-2602210800-dsw--0-ia5 21-Feb-2026 09:45:02 2459
swis2-VHDL20_DWPG_211800-2602211800-dsw--0-ia5 21-Feb-2026 19:45:04 2477
swis2-VHDL20_DWPG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 2300
swis2-VHDL20_DWPG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 2312
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swis2-VHDL20_DWPH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 2450
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swis2-VHDL20_DWSG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 3942
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wst04-VHDL20_DWEI_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:16 346865
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wst04-VHDL20_DWHG_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:22 343253
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wst04-VHDL20_DWHH_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:22 328086
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wst04-VHDL20_DWLG_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:26 333200
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wst04-VHDL20_DWLH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 334708
wst04-VHDL20_DWLH_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:20 334367
wst04-VHDL20_DWLH_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 334384
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wst04-VHDL20_DWLH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 341107
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wst04-VHDL20_DWLI_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 344246
wst04-VHDL20_DWLI_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:26 343131
wst04-VHDL20_DWLI_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 343260
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wst04-VHDL20_DWLI_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 344642
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wst04-VHDL20_DWMG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:26 567743
wst04-VHDL20_DWMG_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:16 565519
wst04-VHDL20_DWMG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 566763
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wst04-VHDL20_DWMO_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:16 457736
wst04-VHDL20_DWMO_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 459208
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wst04-VHDL20_DWMP_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:26 573187
wst04-VHDL20_DWMP_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:16 571385
wst04-VHDL20_DWMP_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 571452
wst04-VHDL20_DWMP_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:22 572256
wst04-VHDL20_DWMP_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:27 587346
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wst04-VHDL20_DWPG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:00:31 332746
wst04-VHDL20_DWPG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:36 388286
wst04-VHDL20_DWPG_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:26 343836
wst04-VHDL20_DWPG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 343528
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wst04-VHDL20_DWPG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:37 399239
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wst04-VHDL20_DWPH_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:30 287109
wst04-VHDL20_DWPH_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:20 287440
wst04-VHDL20_DWPH_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:21 242104
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wst04-VHDL20_DWPH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 292295
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wst04-VHDL20_DWSG_210400-2602210400-omedes--0.pdf 21-Feb-2026 06:15:11 347845
wst04-VHDL20_DWSG_210800-2602210800-omedes--0.pdf 21-Feb-2026 09:45:12 359970
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wst04-VHDL20_DWSG_211800-2602211800-omedes--0.pdf 21-Feb-2026 19:45:12 359440
wst04-VHDL20_DWSG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:17 360131
wst04-VHDL20_DWSG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:16 360230
wst04-VHDL20_DWSG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:12 359429
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wst04-VHDL20_DWSG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:12 358394