Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_100600 10-Mar-2026 11:21:34 4246
FPDL13_DWMZ_110600 11-Mar-2026 14:38:05 3789
SXDL31_DWAV_100800 10-Mar-2026 07:48:24 7983
SXDL31_DWAV_101800 10-Mar-2026 17:40:49 7388
SXDL31_DWAV_110800 11-Mar-2026 08:14:29 8497
SXDL31_DWAV_111800 11-Mar-2026 17:57:00 5964
SXDL31_DWAV_LATEST 11-Mar-2026 17:57:00 5964
SXDL33_DWAV_100000 10-Mar-2026 10:22:48 7505
SXDL33_DWAV_110000 11-Mar-2026 11:16:24 11006
SXDL33_DWAV_LATEST 11-Mar-2026 11:16:24 11006
ber01-FWDL39_DWMS_101230-2603101230-dsw--0-ia5 10-Mar-2026 12:50:11 2364
ber01-FWDL39_DWMS_101230_COR-2603101230-dsw--0-ia5 10-Mar-2026 13:34:43 2368
ber01-FWDL39_DWMS_111230-2603111230-dsw--0-ia5 11-Mar-2026 11:46:37 1264
ber01-VHDL13_DWEH_100400-2603100400-dsw--0-ia5 10-Mar-2026 05:58:17 3411
ber01-VHDL13_DWEH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:28:17 3303
ber01-VHDL13_DWEH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:28:17 2804
ber01-VHDL13_DWEH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:28:12 2702
ber01-VHDL13_DWEH_110400-2603110400-dsw--0-ia5 11-Mar-2026 05:58:11 2685
ber01-VHDL13_DWEH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:28:18 3180
ber01-VHDL13_DWEH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:28:16 2794
ber01-VHDL13_DWEH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:28:12 2942
ber01-VHDL13_DWHG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2752
ber01-VHDL13_DWHG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:07 2943
ber01-VHDL13_DWHG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:06 2648
ber01-VHDL13_DWHG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 3092
ber01-VHDL13_DWHG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 3134
ber01-VHDL13_DWHG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:10 3366
ber01-VHDL13_DWHG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2817
ber01-VHDL13_DWHG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:12 4358
ber01-VHDL13_DWHH_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2457
ber01-VHDL13_DWHH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:07 2991
ber01-VHDL13_DWHH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:06 2692
ber01-VHDL13_DWHH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2954
ber01-VHDL13_DWHH_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 3015
ber01-VHDL13_DWHH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:10 3131
ber01-VHDL13_DWHH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2666
ber01-VHDL13_DWHH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:12 3418
ber01-VHDL13_DWLG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2655
ber01-VHDL13_DWLG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 2652
ber01-VHDL13_DWLG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2294
ber01-VHDL13_DWLG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2369
ber01-VHDL13_DWLG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:05 2409
ber01-VHDL13_DWLG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2395
ber01-VHDL13_DWLG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:03 2676
ber01-VHDL13_DWLG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 3031
ber01-VHDL13_DWLH_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2949
ber01-VHDL13_DWLH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 3145
ber01-VHDL13_DWLH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2661
ber01-VHDL13_DWLH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2737
ber01-VHDL13_DWLH_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:05 2680
ber01-VHDL13_DWLH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2731
ber01-VHDL13_DWLH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:03 2925
ber01-VHDL13_DWLH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 3152
ber01-VHDL13_DWLI_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2910
ber01-VHDL13_DWLI_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 3038
ber01-VHDL13_DWLI_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2476
ber01-VHDL13_DWLI_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2735
ber01-VHDL13_DWLI_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:05 2760
ber01-VHDL13_DWLI_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2784
ber01-VHDL13_DWLI_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:03 2627
ber01-VHDL13_DWLI_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 2953
ber01-VHDL13_DWMG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:01 2879
ber01-VHDL13_DWMG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 3192
ber01-VHDL13_DWMG_100800_COR-2603100800-dsw--0-ia5 10-Mar-2026 09:36:59 3196
ber01-VHDL13_DWMG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2848
ber01-VHDL13_DWMG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2900
ber01-VHDL13_DWMG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 2785
ber01-VHDL13_DWMG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2771
ber01-VHDL13_DWMG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2394
ber01-VHDL13_DWMG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:06 2695
ber01-VHDL13_DWMO_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:01 2883
ber01-VHDL13_DWMO_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 2919
ber01-VHDL13_DWMO_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2551
ber01-VHDL13_DWMO_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2890
ber01-VHDL13_DWMO_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 2803
ber01-VHDL13_DWMO_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2736
ber01-VHDL13_DWMO_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2401
ber01-VHDL13_DWMO_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:06 2685
ber01-VHDL13_DWMP_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:01 2743
ber01-VHDL13_DWMP_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:07 3377
ber01-VHDL13_DWMP_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2766
ber01-VHDL13_DWMP_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2943
ber01-VHDL13_DWMP_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 2797
ber01-VHDL13_DWMP_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2669
ber01-VHDL13_DWMP_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2483
ber01-VHDL13_DWMP_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:06 2796
ber01-VHDL13_DWOG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 3819
ber01-VHDL13_DWOG_101700-2603101700-dsw--0-ia5 10-Mar-2026 19:00:02 4129
ber01-VHDL13_DWOG_110300-2603110300-dsw--0-ia5 11-Mar-2026 04:00:01 4957
ber01-VHDL13_DWOG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:10 4800
ber01-VHDL13_DWOG_111700-2603111700-dsw--0-ia5 11-Mar-2026 19:00:02 4401
ber01-VHDL13_DWOG_120300-2603120300-dsw--0-ia5 12-Mar-2026 04:00:01 5108
ber01-VHDL13_DWOH_100400-2603100400-dsw--0-ia5 10-Mar-2026 05:58:17 3136
ber01-VHDL13_DWOH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:28:17 3085
ber01-VHDL13_DWOH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:28:17 2649
ber01-VHDL13_DWOH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:28:12 2483
ber01-VHDL13_DWOH_110400-2603110400-dsw--0-ia5 11-Mar-2026 05:58:11 2518
ber01-VHDL13_DWOH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:28:18 2639
ber01-VHDL13_DWOH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:28:16 2244
ber01-VHDL13_DWOH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:28:12 2415
ber01-VHDL13_DWOI_100400-2603100400-dsw--0-ia5 10-Mar-2026 05:58:11 3375
ber01-VHDL13_DWOI_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:28:12 3271
ber01-VHDL13_DWOI_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:28:12 2736
ber01-VHDL13_DWOI_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:28:12 2605
ber01-VHDL13_DWOI_110400-2603110400-dsw--0-ia5 11-Mar-2026 05:58:16 2615
ber01-VHDL13_DWOI_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:28:11 2724
ber01-VHDL13_DWOI_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:28:12 2320
ber01-VHDL13_DWOI_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:28:16 2484
ber01-VHDL13_DWON_100456-2603100456-dsw--0-ia5 10-Mar-2026 04:57:01 3663
ber01-VHDL13_DWON_100627-2603100627-dsw--0-ia5 10-Mar-2026 06:28:02 3964
ber01-VHDL13_DWON_100652-2603100652-dsw--0-ia5 10-Mar-2026 06:52:31 3955
ber01-VHDL13_DWON_100900-2603100900-dsw--0-ia5 10-Mar-2026 09:00:12 3961
ber01-VHDL13_DWON_101532-2603101532-dsw--0-ia5 10-Mar-2026 15:32:58 3751
ber01-VHDL13_DWON_101815-2603101815-dsw--0-ia5 10-Mar-2026 18:15:27 3503
ber01-VHDL13_DWON_101930-2603101930-dsw--0-ia5 10-Mar-2026 19:30:38 3751
ber01-VHDL13_DWON_102259-2603102259-dsw--0-ia5 10-Mar-2026 22:59:16 3842
ber01-VHDL13_DWON_110009-2603110009-dsw--0-ia5 11-Mar-2026 00:09:37 4418
ber01-VHDL13_DWON_110147-2603110147-dsw--0-ia5 11-Mar-2026 01:47:21 4305
ber01-VHDL13_DWON_110345-2603110345-dsw--0-ia5 11-Mar-2026 03:45:26 4297
ber01-VHDL13_DWON_110620-2603110620-dsw--0-ia5 11-Mar-2026 06:20:46 4553
ber01-VHDL13_DWON_110646-2603110646-dsw--0-ia5 11-Mar-2026 06:46:27 4418
ber01-VHDL13_DWON_110911-2603110911-dsw--0-ia5 11-Mar-2026 09:11:51 4424
ber01-VHDL13_DWON_111538-2603111538-dsw--0-ia5 11-Mar-2026 15:38:56 3541
ber01-VHDL13_DWON_111837-2603111837-dsw--0-ia5 11-Mar-2026 18:37:30 3595
ber01-VHDL13_DWON_112002-2603112002-dsw--0-ia5 11-Mar-2026 20:02:12 3811
ber01-VHDL13_DWON_112039-2603112039-dsw--0-ia5 11-Mar-2026 20:39:37 3811
ber01-VHDL13_DWON_112242-2603112242-dsw--0-ia5 11-Mar-2026 22:42:41 3806
ber01-VHDL13_DWON_120003-2603120003-dsw--0-ia5 12-Mar-2026 00:03:06 4471
ber01-VHDL13_DWON_120142-2603120142-dsw--0-ia5 12-Mar-2026 01:42:30 4437
ber01-VHDL13_DWON_120337-2603120337-dsw--0-ia5 12-Mar-2026 03:38:00 4437
ber01-VHDL13_DWON_120338-2603120338-dsw--0-ia5 12-Mar-2026 03:38:52 4475
ber01-VHDL13_DWPG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2202
ber01-VHDL13_DWPG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 2399
ber01-VHDL13_DWPG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2292
ber01-VHDL13_DWPG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2425
ber01-VHDL13_DWPG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:05 2394
ber01-VHDL13_DWPG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2373
ber01-VHDL13_DWPG_110800_COR-2603110800-dsw--0-ia5 11-Mar-2026 16:18:05 2363
ber01-VHDL13_DWPG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:03 2091
ber01-VHDL13_DWPG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 2260
ber01-VHDL13_DWPH_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2848
ber01-VHDL13_DWPH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:01 2782
ber01-VHDL13_DWPH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:03 2287
ber01-VHDL13_DWPH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 2680
ber01-VHDL13_DWPH_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:05 2537
ber01-VHDL13_DWPH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 2519
ber01-VHDL13_DWPH_110800_COR-2603110800-dsw--0-ia5 11-Mar-2026 16:18:46 2612
ber01-VHDL13_DWPH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:03 2252
ber01-VHDL13_DWPH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 2373
ber01-VHDL13_DWSG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:08 3215
ber01-VHDL13_DWSG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:30:03 3125
ber01-VHDL13_DWSG_101300_COR-2603101300-dsw--0-ia5 10-Mar-2026 14:14:51 3487
ber01-VHDL13_DWSG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:30:06 3483
ber01-VHDL13_DWSG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:30:10 3329
ber01-VHDL13_DWSG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 3833
ber01-VHDL13_DWSG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:30:05 3854
ber01-VHDL13_DWSG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:30:09 2866
ber01-VHDL13_DWSG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:30:02 3028
ber01-VHDL17_DWOG_101200-2603101200-dsw--0-ia5 10-Mar-2026 12:28:56 3075
ber01-VHDL17_DWOG_111200-2603111200-dsw--0-ia5 11-Mar-2026 12:40:07 3720
swis2-VHDL20_DWEG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:15:07 3458
swis2-VHDL20_DWEG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:50:19 3566
swis2-VHDL20_DWEG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 2977
swis2-VHDL20_DWEG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:02 2761
swis2-VHDL20_DWEG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:15:01 2842
swis2-VHDL20_DWEG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:06 3122
swis2-VHDL20_DWEG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:45:07 2574
swis2-VHDL20_DWEG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:45:01 2695
swis2-VHDL20_DWEH_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:15:07 3748
swis2-VHDL20_DWEH_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:50:19 3809
swis2-VHDL20_DWEH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 3161
swis2-VHDL20_DWEH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:02 3025
swis2-VHDL20_DWEH_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:15:01 3024
swis2-VHDL20_DWEH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:06 3688
swis2-VHDL20_DWEH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:45:07 3155
swis2-VHDL20_DWEH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:45:01 3267
swis2-VHDL20_DWEI_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:15:07 3728
swis2-VHDL20_DWEI_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:50:19 3799
swis2-VHDL20_DWEI_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 3089
swis2-VHDL20_DWEI_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:02 2898
swis2-VHDL20_DWEI_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:15:01 2970
swis2-VHDL20_DWEI_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:06 3254
swis2-VHDL20_DWEI_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:45:07 2675
swis2-VHDL20_DWEI_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:45:01 2777
swis2-VHDL20_DWHG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2935
swis2-VHDL20_DWHG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:50:19 3571
swis2-VHDL20_DWHG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 2831
swis2-VHDL20_DWHG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:06 3278
swis2-VHDL20_DWHG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 3317
swis2-VHDL20_DWHG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:02 4014
swis2-VHDL20_DWHG_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:45:07 3000
swis2-VHDL20_DWHG_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:45:01 4544
swis2-VHDL20_DWHH_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:06 2643
swis2-VHDL20_DWHH_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 2878
swis2-VHDL20_DWHH_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:06 3140
swis2-VHDL20_DWHH_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:07 3201
swis2-VHDL20_DWHH_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:02 3784
swis2-VHDL20_DWHH_111800-2603111800-dsw--0-ia5 11-Mar-2026 19:45:07 2852
swis2-VHDL20_DWHH_120200-2603120200-dsw--0-ia5 12-Mar-2026 03:45:01 3604
swis2-VHDL20_DWLG_100400-2603100400-dsw--0-ia5 10-Mar-2026 06:00:12 2997
swis2-VHDL20_DWLG_100800-2603100800-dsw--0-ia5 10-Mar-2026 09:50:19 3147
swis2-VHDL20_DWLG_101800-2603101800-dsw--0-ia5 10-Mar-2026 19:45:04 2636
swis2-VHDL20_DWLG_110200-2603110200-dsw--0-ia5 11-Mar-2026 03:45:06 2711
swis2-VHDL20_DWLG_110400-2603110400-dsw--0-ia5 11-Mar-2026 06:00:17 2758
swis2-VHDL20_DWLG_110800-2603110800-dsw--0-ia5 11-Mar-2026 09:45:02 2894
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wst04-VHDL20_DWMG_100800_COR-2603100800-omedes-..> 10-Mar-2026 09:37:16 569269
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wst04-VHDL20_DWPG_110200-2603110200-omedes--0.pdf 11-Mar-2026 03:45:22 349604
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wst04-VHDL20_DWPH_110200-2603110200-omedes--0.pdf 11-Mar-2026 03:45:22 251211
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