Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Dec-2025 14:50:46 5124
FPDL13_DWMZ_050600 05-Dec-2025 14:30:38 6876
SXDL31_DWAV_041800 04-Dec-2025 17:32:31 4497
SXDL31_DWAV_050800 05-Dec-2025 09:11:33 14145
SXDL31_DWAV_051800 05-Dec-2025 17:44:00 5464
SXDL31_DWAV_060800 06-Dec-2025 08:39:52 7506
SXDL31_DWAV_LATEST 06-Dec-2025 08:39:52 7506
SXDL33_DWAV_040000 04-Dec-2025 14:46:47 8070
SXDL33_DWAV_050000 05-Dec-2025 09:47:54 9922
SXDL33_DWAV_060000 06-Dec-2025 10:48:19 9042
SXDL33_DWAV_LATEST 06-Dec-2025 10:48:19 9042
ber01-FWDL39_DWMS_041230-2512041230-dsw--0-ia5 04-Dec-2025 12:29:21 2227
ber01-FWDL39_DWMS_041230_COR-2512041230-dsw--0-ia5 04-Dec-2025 13:12:31 2225
ber01-FWDL39_DWMS_051230-2512051230-dsw--0-ia5 05-Dec-2025 13:35:56 2283
ber01-VHDL13_DWEH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:16 2742
ber01-VHDL13_DWEH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3326
ber01-VHDL13_DWEH_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:12 3488
ber01-VHDL13_DWEH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:28:16 3146
ber01-VHDL13_DWEH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:28:16 3133
ber01-VHDL13_DWEH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:28:16 3120
ber01-VHDL13_DWEH_060400-2512060400-dsw--0-ia5 06-Dec-2025 05:58:17 3014
ber01-VHDL13_DWEH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:28:16 2919
ber01-VHDL13_DWHG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 3436
ber01-VHDL13_DWHG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:07 3772
ber01-VHDL13_DWHG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3671
ber01-VHDL13_DWHG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 3778
ber01-VHDL13_DWHG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:06 3580
ber01-VHDL13_DWHG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:07 4224
ber01-VHDL13_DWHG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:08 3995
ber01-VHDL13_DWHG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 3098
ber01-VHDL13_DWHH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2545
ber01-VHDL13_DWHH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:07 3124
ber01-VHDL13_DWHH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3124
ber01-VHDL13_DWHH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 3141
ber01-VHDL13_DWHH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:06 3122
ber01-VHDL13_DWHH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:07 3535
ber01-VHDL13_DWHH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:08 3171
ber01-VHDL13_DWHH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2977
ber01-VHDL13_DWLG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 3069
ber01-VHDL13_DWLG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2923
ber01-VHDL13_DWLG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2727
ber01-VHDL13_DWLG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:01 2543
ber01-VHDL13_DWLG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2630
ber01-VHDL13_DWLG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:05 2838
ber01-VHDL13_DWLG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:14:46 2706
ber01-VHDL13_DWLG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2465
ber01-VHDL13_DWLH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2227
ber01-VHDL13_DWLH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2727
ber01-VHDL13_DWLH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2737
ber01-VHDL13_DWLH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:01 2649
ber01-VHDL13_DWLH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2766
ber01-VHDL13_DWLH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:05 2902
ber01-VHDL13_DWLH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:11:47 2817
ber01-VHDL13_DWLH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2465
ber01-VHDL13_DWLI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2654
ber01-VHDL13_DWLI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2743
ber01-VHDL13_DWLI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2755
ber01-VHDL13_DWLI_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:01 2610
ber01-VHDL13_DWLI_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2648
ber01-VHDL13_DWLI_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:05 2854
ber01-VHDL13_DWLI_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:02 2740
ber01-VHDL13_DWLI_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2461
ber01-VHDL13_DWMG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2685
ber01-VHDL13_DWMG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2773
ber01-VHDL13_DWMG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2715
ber01-VHDL13_DWMG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 2886
ber01-VHDL13_DWMG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2730
ber01-VHDL13_DWMG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:02 3442
ber01-VHDL13_DWMG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:06 3296
ber01-VHDL13_DWMG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 3075
ber01-VHDL13_DWMO_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2792
ber01-VHDL13_DWMO_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2935
ber01-VHDL13_DWMO_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2902
ber01-VHDL13_DWMO_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 2910
ber01-VHDL13_DWMO_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2534
ber01-VHDL13_DWMO_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:02 3014
ber01-VHDL13_DWMO_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:06 2890
ber01-VHDL13_DWMO_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2511
ber01-VHDL13_DWMP_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2848
ber01-VHDL13_DWMP_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 3050
ber01-VHDL13_DWMP_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 3023
ber01-VHDL13_DWMP_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 2907
ber01-VHDL13_DWMP_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2735
ber01-VHDL13_DWMP_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:02 3523
ber01-VHDL13_DWMP_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:06 3389
ber01-VHDL13_DWMP_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 3288
ber01-VHDL13_DWOG_041700-2512041700-dsw--0-ia5 04-Dec-2025 19:00:02 4227
ber01-VHDL13_DWOG_050300-2512050300-dsw--0-ia5 05-Dec-2025 04:00:01 4424
ber01-VHDL13_DWOG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 4306
ber01-VHDL13_DWOG_051700-2512051700-dsw--0-ia5 05-Dec-2025 19:00:07 3772
ber01-VHDL13_DWOG_060300-2512060300-dsw--0-ia5 06-Dec-2025 04:00:02 4191
ber01-VHDL13_DWOG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 4095
ber01-VHDL13_DWOH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:16 2806
ber01-VHDL13_DWOH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3287
ber01-VHDL13_DWOH_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:16 3349
ber01-VHDL13_DWOH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:28:16 3031
ber01-VHDL13_DWOH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:28:16 2860
ber01-VHDL13_DWOH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:28:11 2688
ber01-VHDL13_DWOH_060400-2512060400-dsw--0-ia5 06-Dec-2025 05:58:17 2730
ber01-VHDL13_DWOH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:28:16 2709
ber01-VHDL13_DWOI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:12 2532
ber01-VHDL13_DWOI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3013
ber01-VHDL13_DWOI_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:16 2858
ber01-VHDL13_DWOI_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:28:12 2620
ber01-VHDL13_DWOI_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:28:10 2437
ber01-VHDL13_DWOI_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:28:11 2362
ber01-VHDL13_DWOI_060400-2512060400-dsw--0-ia5 06-Dec-2025 05:58:12 2329
ber01-VHDL13_DWOI_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:28:12 2552
ber01-VHDL13_DWON_041535-2512041535-dsw--0-ia5 04-Dec-2025 15:35:48 3779
ber01-VHDL13_DWON_041734-2512041734-dsw--0-ia5 04-Dec-2025 17:35:00 3774
ber01-VHDL13_DWON_042159-2512042159-dsw--0-ia5 04-Dec-2025 21:59:37 3774
ber01-VHDL13_DWON_042347-2512042347-dsw--0-ia5 04-Dec-2025 23:47:37 3842
ber01-VHDL13_DWON_050127-2512050127-dsw--0-ia5 05-Dec-2025 01:27:51 3842
ber01-VHDL13_DWON_050435-2512050435-dsw--0-ia5 05-Dec-2025 04:35:53 3842
ber01-VHDL13_DWON_050628-2512050628-dsw--0-ia5 05-Dec-2025 06:29:01 3369
ber01-VHDL13_DWON_050722-2512050722-dsw--0-ia5 05-Dec-2025 07:22:26 4000
ber01-VHDL13_DWON_051348-2512051348-dsw--0-ia5 05-Dec-2025 13:48:57 3213
ber01-VHDL13_DWON_051745-2512051745-dsw--0-ia5 05-Dec-2025 17:45:16 3213
ber01-VHDL13_DWON_052020-2512052020-dsw--0-ia5 05-Dec-2025 20:20:37 3155
ber01-VHDL13_DWON_060019-2512060019-dsw--0-ia5 06-Dec-2025 00:19:17 3241
ber01-VHDL13_DWON_060353-2512060353-dsw--0-ia5 06-Dec-2025 03:53:51 3241
ber01-VHDL13_DWON_060629-2512060629-dsw--0-ia5 06-Dec-2025 06:29:26 3540
ber01-VHDL13_DWON_060652-2512060652-dsw--0-ia5 06-Dec-2025 06:52:31 3573
ber01-VHDL13_DWON_060856-2512060856-dsw--0-ia5 06-Dec-2025 08:56:48 3480
ber01-VHDL13_DWPG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 1979
ber01-VHDL13_DWPG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2229
ber01-VHDL13_DWPG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2437
ber01-VHDL13_DWPG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:01 2712
ber01-VHDL13_DWPG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 2422
ber01-VHDL13_DWPG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:05 2473
ber01-VHDL13_DWPG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:06 2467
ber01-VHDL13_DWPG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2011
ber01-VHDL13_DWPH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 1810
ber01-VHDL13_DWPH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2085
ber01-VHDL13_DWPH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2191
ber01-VHDL13_DWPH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:01 2530
ber01-VHDL13_DWPH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 1973
ber01-VHDL13_DWPH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:05 2200
ber01-VHDL13_DWPH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:06 2189
ber01-VHDL13_DWPH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 2020
ber01-VHDL13_DWSG_040800_COR-2512040800-dsw--0-ia5 04-Dec-2025 12:46:01 3234
ber01-VHDL13_DWSG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 3381
ber01-VHDL13_DWSG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 3818
ber01-VHDL13_DWSG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 4426
ber01-VHDL13_DWSG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:30:12 4310
ber01-VHDL13_DWSG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:30:02 4075
ber01-VHDL13_DWSG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:30:07 4037
ber01-VHDL13_DWSG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:08 3581
ber01-VHDL13_DWSG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:30:07 3395
ber01-VHDL17_DWOG_041200-2512041200-dsw--0-ia5 04-Dec-2025 12:55:06 3081
ber01-VHDL17_DWOG_051200-2512051200-dsw--0-ia5 05-Dec-2025 11:52:31 3067
swis2-VHDL20_DWEG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3257
swis2-VHDL20_DWEG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3666
swis2-VHDL20_DWEG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3815
swis2-VHDL20_DWEG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:06 3652
swis2-VHDL20_DWEG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:06 3332
swis2-VHDL20_DWEG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3006
swis2-VHDL20_DWEG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 3050
swis2-VHDL20_DWEG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:06 3186
swis2-VHDL20_DWEH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3233
swis2-VHDL20_DWEH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3767
swis2-VHDL20_DWEH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3885
swis2-VHDL20_DWEH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:06 3711
swis2-VHDL20_DWEH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:06 3552
swis2-VHDL20_DWEH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3479
swis2-VHDL20_DWEH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 3346
swis2-VHDL20_DWEH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:06 3421
swis2-VHDL20_DWEI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 2978
swis2-VHDL20_DWEI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3306
swis2-VHDL20_DWEI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:06 3212
swis2-VHDL20_DWEI_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:06 3145
swis2-VHDL20_DWEI_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:06 2791
swis2-VHDL20_DWEI_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 2657
swis2-VHDL20_DWEI_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 2680
swis2-VHDL20_DWEI_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:06 3076
swis2-VHDL20_DWHG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3619
swis2-VHDL20_DWHG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3958
swis2-VHDL20_DWHG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3854
swis2-VHDL20_DWHG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 4342
swis2-VHDL20_DWHG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:06 3763
swis2-VHDL20_DWHG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:01 4410
swis2-VHDL20_DWHG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:08 4178
swis2-VHDL20_DWHG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 3625
swis2-VHDL20_DWHH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 2731
swis2-VHDL20_DWHH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3310
swis2-VHDL20_DWHH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3310
swis2-VHDL20_DWHH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3687
swis2-VHDL20_DWHH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:06 3308
swis2-VHDL20_DWHH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:01 3721
swis2-VHDL20_DWHH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:08 3357
swis2-VHDL20_DWHH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 3516
swis2-VHDL20_DWLG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 3686
swis2-VHDL20_DWLG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3455
swis2-VHDL20_DWLG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3112
swis2-VHDL20_DWLG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3143
swis2-VHDL20_DWLG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3044
swis2-VHDL20_DWLG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3256
swis2-VHDL20_DWLG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:17:12 3073
swis2-VHDL20_DWLG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 2958
swis2-VHDL20_DWLH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2626
swis2-VHDL20_DWLH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3123
swis2-VHDL20_DWLH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3130
swis2-VHDL20_DWLH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3261
swis2-VHDL20_DWLH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3189
swis2-VHDL20_DWLH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3323
swis2-VHDL20_DWLH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:17:26 3191
swis2-VHDL20_DWLH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 2969
swis2-VHDL20_DWLI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 3153
swis2-VHDL20_DWLI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3215
swis2-VHDL20_DWLI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3142
swis2-VHDL20_DWLI_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3211
swis2-VHDL20_DWLI_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3064
swis2-VHDL20_DWLI_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3269
swis2-VHDL20_DWLI_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:13:22 3106
swis2-VHDL20_DWLI_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 2955
swis2-VHDL20_DWMG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3267
swis2-VHDL20_DWMG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3355
swis2-VHDL20_DWMG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3133
swis2-VHDL20_DWMG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3605
swis2-VHDL20_DWMG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3210
swis2-VHDL20_DWMG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3857
swis2-VHDL20_DWMG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 3878
swis2-VHDL20_DWMG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 3767
swis2-VHDL20_DWMO_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3378
swis2-VHDL20_DWMO_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3522
swis2-VHDL20_DWMO_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3324
swis2-VHDL20_DWMO_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3558
swis2-VHDL20_DWMO_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 2956
swis2-VHDL20_DWMO_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3435
swis2-VHDL20_DWMO_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 3264
swis2-VHDL20_DWMO_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 3044
swis2-VHDL20_DWMP_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3416
swis2-VHDL20_DWMP_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3634
swis2-VHDL20_DWMP_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3440
swis2-VHDL20_DWMP_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3630
swis2-VHDL20_DWMP_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3203
swis2-VHDL20_DWMP_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 3943
swis2-VHDL20_DWMP_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:07 3971
swis2-VHDL20_DWMP_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 3986
swis2-VHDL20_DWPG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2499
swis2-VHDL20_DWPG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 2637
swis2-VHDL20_DWPG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 2811
swis2-VHDL20_DWPG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 3224
swis2-VHDL20_DWPG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 3003
swis2-VHDL20_DWPG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 2897
swis2-VHDL20_DWPG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:12 2793
swis2-VHDL20_DWPG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 2469
swis2-VHDL20_DWPH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2330
swis2-VHDL20_DWPH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 2413
swis2-VHDL20_DWPH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 2520
swis2-VHDL20_DWPH_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:02 2992
swis2-VHDL20_DWPH_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 2557
swis2-VHDL20_DWPH_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 2532
swis2-VHDL20_DWPH_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:00:12 2517
swis2-VHDL20_DWPH_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:02 2478
swis2-VHDL20_DWSG_040800_COR-2512040800-dsw--0-ia5 04-Dec-2025 12:46:01 3465
swis2-VHDL20_DWSG_041300-2512041300-dsw--0-ia5 04-Dec-2025 14:45:05 4493
swis2-VHDL20_DWSG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3791
swis2-VHDL20_DWSG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 4400
swis2-VHDL20_DWSG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 4917
swis2-VHDL20_DWSG_050800-2512050800-dsw--0-ia5 05-Dec-2025 09:45:06 5039
swis2-VHDL20_DWSG_051300-2512051300-dsw--0-ia5 05-Dec-2025 14:45:02 4947
swis2-VHDL20_DWSG_051800-2512051800-dsw--0-ia5 05-Dec-2025 19:45:02 4594
swis2-VHDL20_DWSG_060200-2512060200-dsw--0-ia5 06-Dec-2025 03:45:07 4613
swis2-VHDL20_DWSG_060400-2512060400-dsw--0-ia5 06-Dec-2025 06:15:02 3934
swis2-VHDL20_DWSG_060800-2512060800-dsw--0-ia5 06-Dec-2025 09:45:06 4070
wst04-VHDL20_DWEG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 232484
wst04-VHDL20_DWEG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 235238
wst04-VHDL20_DWEG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:26 234856
wst04-VHDL20_DWEG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:22 233962
wst04-VHDL20_DWEG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:12 232456
wst04-VHDL20_DWEG_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:17 232365
wst04-VHDL20_DWEG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:21 231465
wst04-VHDL20_DWEG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:22 234485
wst04-VHDL20_DWEH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 231356
wst04-VHDL20_DWEH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 233571
wst04-VHDL20_DWEH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:20 233580
wst04-VHDL20_DWEH_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:22 232244
wst04-VHDL20_DWEH_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:12 231976
wst04-VHDL20_DWEH_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:17 232960
wst04-VHDL20_DWEH_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:21 231982
wst04-VHDL20_DWEH_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:22 236041
wst04-VHDL20_DWEI_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:18 325238
wst04-VHDL20_DWEI_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 326329
wst04-VHDL20_DWEI_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:26 326179
wst04-VHDL20_DWEI_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:22 327533
wst04-VHDL20_DWEI_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:12 326755
wst04-VHDL20_DWEI_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:21 327400
wst04-VHDL20_DWEI_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:27 326417
wst04-VHDL20_DWEI_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:22 329343
wst04-VHDL20_DWHG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:18 316659
wst04-VHDL20_DWHG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 317700
wst04-VHDL20_DWHG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:12 317724
wst04-VHDL20_DWHG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:18 313774
wst04-VHDL20_DWHG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:22 311254
wst04-VHDL20_DWHG_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:11 312871
wst04-VHDL20_DWHG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:00:12 311792
wst04-VHDL20_DWHG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:12 317270
wst04-VHDL20_DWHH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 305219
wst04-VHDL20_DWHH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 306040
wst04-VHDL20_DWHH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:12 306043
wst04-VHDL20_DWHH_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:18 307528
wst04-VHDL20_DWHH_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:22 306335
wst04-VHDL20_DWHH_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:11 306679
wst04-VHDL20_DWHH_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:00:12 305638
wst04-VHDL20_DWHH_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:16 307487
wst04-VHDL20_DWLG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 311105
wst04-VHDL20_DWLG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 311814
wst04-VHDL20_DWLG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 310983
wst04-VHDL20_DWLG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:32 315094
wst04-VHDL20_DWLG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:20 314636
wst04-VHDL20_DWLG_060200-2512060200-omedes--0.pdf 06-Dec-2025 06:19:41 315272
wst04-VHDL20_DWLG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:20:41 315166
wst04-VHDL20_DWLG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:32 312323
wst04-VHDL20_DWLH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 316453
wst04-VHDL20_DWLH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 317876
wst04-VHDL20_DWLH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 317248
wst04-VHDL20_DWLH_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:26 315487
wst04-VHDL20_DWLH_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:26 314704
wst04-VHDL20_DWLH_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:27 314830
wst04-VHDL20_DWLH_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:20:27 315014
wst04-VHDL20_DWLH_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:32 313198
wst04-VHDL20_DWLI_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:26 307584
wst04-VHDL20_DWLI_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 308023
wst04-VHDL20_DWLI_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 307828
wst04-VHDL20_DWLI_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:32 308320
wst04-VHDL20_DWLI_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:20 308144
wst04-VHDL20_DWLI_060200-2512060200-omedes--0.pdf 06-Dec-2025 06:20:06 308477
wst04-VHDL20_DWLI_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:21:01 308290
wst04-VHDL20_DWLI_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:26 316441
wst04-VHDL20_DWMG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 527090
wst04-VHDL20_DWMG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 527799
wst04-VHDL20_DWMG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:16 528198
wst04-VHDL20_DWMG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:18 535988
wst04-VHDL20_DWMG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:18 534773
wst04-VHDL20_DWMG_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:17 535248
wst04-VHDL20_DWMG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:17 535131
wst04-VHDL20_DWMG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:16 538438
wst04-VHDL20_DWMO_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 417951
wst04-VHDL20_DWMO_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 418795
wst04-VHDL20_DWMO_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:22 419358
wst04-VHDL20_DWMO_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:13 420798
wst04-VHDL20_DWMO_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:18 419264
wst04-VHDL20_DWMO_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:11 419090
wst04-VHDL20_DWMO_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:17 419440
wst04-VHDL20_DWMO_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:12 422825
wst04-VHDL20_DWMP_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 549327
wst04-VHDL20_DWMP_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 549206
wst04-VHDL20_DWMP_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:22 550625
wst04-VHDL20_DWMP_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:18 555577
wst04-VHDL20_DWMP_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:18 554290
wst04-VHDL20_DWMP_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:17 553993
wst04-VHDL20_DWMP_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:17 555143
wst04-VHDL20_DWMP_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:16 558690
wst04-VHDL20_DWPG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:26 319859
wst04-VHDL20_DWPG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 319997
wst04-VHDL20_DWPG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:31 320066
wst04-VHDL20_DWPG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:32 366496
wst04-VHDL20_DWPG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:26 321900
wst04-VHDL20_DWPG_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:27 321409
wst04-VHDL20_DWPG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:00:32 322047
wst04-VHDL20_DWPG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:32 365700
wst04-VHDL20_DWPH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 269434
wst04-VHDL20_DWPH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 224573
wst04-VHDL20_DWPH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:31 224712
wst04-VHDL20_DWPH_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:26 269491
wst04-VHDL20_DWPH_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:20 269001
wst04-VHDL20_DWPH_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:21 224634
wst04-VHDL20_DWPH_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:00:32 224602
wst04-VHDL20_DWPH_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:26 269410
wst04-VHDL20_DWSG_040800-2512040800-omedes--0.pdf 04-Dec-2025 12:46:07 338557
wst04-VHDL20_DWSG_041300-2512041300-omedes--0.pdf 04-Dec-2025 14:45:11 339214
wst04-VHDL20_DWSG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 338181
wst04-VHDL20_DWSG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 339311
wst04-VHDL20_DWSG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:16 339718
wst04-VHDL20_DWSG_050800-2512050800-omedes--0.pdf 05-Dec-2025 09:45:11 338548
wst04-VHDL20_DWSG_051300-2512051300-omedes--0.pdf 05-Dec-2025 14:45:13 339210
wst04-VHDL20_DWSG_051800-2512051800-omedes--0.pdf 05-Dec-2025 19:45:12 338997
wst04-VHDL20_DWSG_060200-2512060200-omedes--0.pdf 06-Dec-2025 03:45:21 339367
wst04-VHDL20_DWSG_060400-2512060400-omedes--0.pdf 06-Dec-2025 06:15:13 338469
wst04-VHDL20_DWSG_060800-2512060800-omedes--0.pdf 06-Dec-2025 09:45:12 338733