Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Feb-2026 14:23:54 4983
FPDL13_DWMZ_020600 02-Feb-2026 09:23:15 2445
SXDL31_DWAV_010800 01-Feb-2026 07:52:44 9514
SXDL31_DWAV_011800 01-Feb-2026 18:13:35 6807
SXDL31_DWAV_020800 02-Feb-2026 08:50:53 16271
SXDL31_DWAV_311800 31-Jan-2026 17:40:59 6595
SXDL31_DWAV_LATEST 02-Feb-2026 08:50:53 16271
SXDL33_DWAV_010000 01-Feb-2026 10:35:07 10495
SXDL33_DWAV_020000 02-Feb-2026 10:55:39 14279
SXDL33_DWAV_LATEST 02-Feb-2026 10:55:39 14279
ber01-FWDL39_DWMS_011230-2602011230-dsw--0-ia5 01-Feb-2026 12:24:37 1391
ber01-FWDL39_DWMS_021230-2602021230-dsw--0-ia5 02-Feb-2026 12:22:56 1432
ber01-VHDL13_DWEH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:28:11 3483
ber01-VHDL13_DWEH_010400-2602010400-dsw--0-ia5 01-Feb-2026 05:58:12 3931
ber01-VHDL13_DWEH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:28:17 3959
ber01-VHDL13_DWEH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:28:16 4691
ber01-VHDL13_DWEH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:28:11 4483
ber01-VHDL13_DWEH_020400-2602020400-dsw--0-ia5 02-Feb-2026 05:58:15 4438
ber01-VHDL13_DWEH_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:46 4808
ber01-VHDL13_DWEH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:28:17 4962
ber01-VHDL13_DWEH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:13 3011
ber01-VHDL13_DWHG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:07 4241
ber01-VHDL13_DWHG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 4241
ber01-VHDL13_DWHG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 5290
ber01-VHDL13_DWHG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:09 4344
ber01-VHDL13_DWHG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 4748
ber01-VHDL13_DWHG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:06 4747
ber01-VHDL13_DWHG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:10 4665
ber01-VHDL13_DWHG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3776
ber01-VHDL13_DWHH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:07 3775
ber01-VHDL13_DWHH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:08 3775
ber01-VHDL13_DWHH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 4596
ber01-VHDL13_DWHH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:09 3683
ber01-VHDL13_DWHH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 3963
ber01-VHDL13_DWHH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:06 3962
ber01-VHDL13_DWHH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:10 4307
ber01-VHDL13_DWHH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3358
ber01-VHDL13_DWLG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 2167
ber01-VHDL13_DWLG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2355
ber01-VHDL13_DWLG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 2391
ber01-VHDL13_DWLG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 1880
ber01-VHDL13_DWLG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 2107
ber01-VHDL13_DWLG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 2494
ber01-VHDL13_DWLG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 3253
ber01-VHDL13_DWLG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1670
ber01-VHDL13_DWLH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 2126
ber01-VHDL13_DWLH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2397
ber01-VHDL13_DWLH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 2489
ber01-VHDL13_DWLH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 2037
ber01-VHDL13_DWLH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 2180
ber01-VHDL13_DWLH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 2306
ber01-VHDL13_DWLH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 2911
ber01-VHDL13_DWLH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1674
ber01-VHDL13_DWLI_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 2261
ber01-VHDL13_DWLI_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2393
ber01-VHDL13_DWLI_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 2462
ber01-VHDL13_DWLI_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 2075
ber01-VHDL13_DWLI_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 2366
ber01-VHDL13_DWLI_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 2387
ber01-VHDL13_DWLI_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 2919
ber01-VHDL13_DWLI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1675
ber01-VHDL13_DWMG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 3218
ber01-VHDL13_DWMG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:02 3188
ber01-VHDL13_DWMG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 3417
ber01-VHDL13_DWMG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 3029
ber01-VHDL13_DWMG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:02 3648
ber01-VHDL13_DWMG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 3620
ber01-VHDL13_DWMG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:10 4024
ber01-VHDL13_DWMG_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:02 4531
ber01-VHDL13_DWMG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3295
ber01-VHDL13_DWMO_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 3088
ber01-VHDL13_DWMO_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:02 3055
ber01-VHDL13_DWMO_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 3236
ber01-VHDL13_DWMO_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 2860
ber01-VHDL13_DWMO_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:02 3525
ber01-VHDL13_DWMO_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 3506
ber01-VHDL13_DWMO_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:10 3742
ber01-VHDL13_DWMO_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:12 4239
ber01-VHDL13_DWMO_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3007
ber01-VHDL13_DWMP_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 3506
ber01-VHDL13_DWMP_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:02 3476
ber01-VHDL13_DWMP_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 3692
ber01-VHDL13_DWMP_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 3221
ber01-VHDL13_DWMP_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:02 3981
ber01-VHDL13_DWMP_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 3949
ber01-VHDL13_DWMP_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 3792
ber01-VHDL13_DWMP_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:16 3883
ber01-VHDL13_DWMP_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3425
ber01-VHDL13_DWOG_010300-2602010300-dsw--0-ia5 01-Feb-2026 04:00:06 5368
ber01-VHDL13_DWOG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:07 5514
ber01-VHDL13_DWOG_011700-2602011700-dsw--0-ia5 01-Feb-2026 19:00:01 4855
ber01-VHDL13_DWOG_020300-2602020300-dsw--0-ia5 02-Feb-2026 04:00:01 5832
ber01-VHDL13_DWOG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 6015
ber01-VHDL13_DWOG_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 10:40:57 5776
ber01-VHDL13_DWOG_311700-2601311700-dsw--0-ia5 31-Jan-2026 19:00:01 5120
ber01-VHDL13_DWOH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:28:11 3556
ber01-VHDL13_DWOH_010400-2602010400-dsw--0-ia5 01-Feb-2026 05:58:12 3888
ber01-VHDL13_DWOH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:28:17 3821
ber01-VHDL13_DWOH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:28:16 4133
ber01-VHDL13_DWOH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:28:11 4027
ber01-VHDL13_DWOH_020400-2602020400-dsw--0-ia5 02-Feb-2026 05:58:11 3985
ber01-VHDL13_DWOH_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:52 4376
ber01-VHDL13_DWOH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:28:13 4839
ber01-VHDL13_DWOH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:17 3120
ber01-VHDL13_DWOI_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:28:17 2696
ber01-VHDL13_DWOI_010400-2602010400-dsw--0-ia5 01-Feb-2026 05:58:16 2715
ber01-VHDL13_DWOI_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:28:11 2512
ber01-VHDL13_DWOI_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:28:12 3246
ber01-VHDL13_DWOI_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:28:17 3340
ber01-VHDL13_DWOI_020400-2602020400-dsw--0-ia5 02-Feb-2026 05:58:15 3293
ber01-VHDL13_DWOI_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:46 3886
ber01-VHDL13_DWOI_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:28:13 4154
ber01-VHDL13_DWOI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:13 2710
ber01-VHDL13_DWON_010121-2602010121-dsw--0-ia5 01-Feb-2026 01:21:37 4145
ber01-VHDL13_DWON_010159-2602010159-dsw--0-ia5 01-Feb-2026 01:59:36 4145
ber01-VHDL13_DWON_010629-2602010629-dsw--0-ia5 01-Feb-2026 06:29:06 4391
ber01-VHDL13_DWON_010710-2602010710-dsw--0-ia5 01-Feb-2026 07:10:52 4392
ber01-VHDL13_DWON_011212-2602011212-dsw--0-ia5 01-Feb-2026 12:12:47 5171
ber01-VHDL13_DWON_011508-2602011508-dsw--0-ia5 01-Feb-2026 15:08:32 4519
ber01-VHDL13_DWON_011828-2602011828-dsw--0-ia5 01-Feb-2026 18:28:07 4519
ber01-VHDL13_DWON_020155-2602020155-dsw--0-ia5 02-Feb-2026 01:55:17 4857
ber01-VHDL13_DWON_020348-2602020348-dsw--0-ia5 02-Feb-2026 03:48:46 5012
ber01-VHDL13_DWON_020352-2602020352-dsw--0-ia5 02-Feb-2026 03:52:31 5154
ber01-VHDL13_DWON_020630-2602020630-dsw--0-ia5 02-Feb-2026 06:30:06 4898
ber01-VHDL13_DWON_020727-2602020727-dsw--0-ia5 02-Feb-2026 07:27:31 4738
ber01-VHDL13_DWON_020821-2602020821-dsw--0-ia5 02-Feb-2026 08:21:51 4715
ber01-VHDL13_DWON_021040-2602021040-dsw--0-ia5 02-Feb-2026 10:40:38 4695
ber01-VHDL13_DWON_311529-2601311529-dsw--0-ia5 31-Jan-2026 15:29:41 3869
ber01-VHDL13_DWON_311840-2601311840-dsw--0-ia5 31-Jan-2026 18:40:06 4281
ber01-VHDL13_DWON_311946-2601311946-dsw--0-ia5 31-Jan-2026 19:46:32 4281
ber01-VHDL13_DWPG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 2165
ber01-VHDL13_DWPG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2152
ber01-VHDL13_DWPG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 2147
ber01-VHDL13_DWPG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 1905
ber01-VHDL13_DWPG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 1948
ber01-VHDL13_DWPG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 2024
ber01-VHDL13_DWPG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:10 2415
ber01-VHDL13_DWPG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1792
ber01-VHDL13_DWPH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 2595
ber01-VHDL13_DWPH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2581
ber01-VHDL13_DWPH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 2577
ber01-VHDL13_DWPH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 2413
ber01-VHDL13_DWPH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 2510
ber01-VHDL13_DWPH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:02 2687
ber01-VHDL13_DWPH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 3019
ber01-VHDL13_DWPH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 2293
ber01-VHDL13_DWSG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:30:02 3119
ber01-VHDL13_DWSG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 2982
ber01-VHDL13_DWSG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:30:01 3220
ber01-VHDL13_DWSG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:30:04 3166
ber01-VHDL13_DWSG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:30:07 3670
ber01-VHDL13_DWSG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:06 3774
ber01-VHDL13_DWSG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:30:04 3485
ber01-VHDL13_DWSG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 3038
ber01-VHDL17_DWOG_011200-2602011200-dsw--0-ia5 01-Feb-2026 11:57:22 4217
ber01-VHDL17_DWOG_021200-2602021200-dsw--0-ia5 02-Feb-2026 12:50:51 3656
swis2-VHDL20_DWEG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:07 3960
swis2-VHDL20_DWEG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:06 4485
swis2-VHDL20_DWEG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 4955
swis2-VHDL20_DWEG_010800_COR-2602010800-dsw--0-ia5 01-Feb-2026 10:05:11 4959
swis2-VHDL20_DWEG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 4815
swis2-VHDL20_DWEG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:01 4659
swis2-VHDL20_DWEG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 4674
swis2-VHDL20_DWEG_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:36 4584
swis2-VHDL20_DWEG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:01 5845
swis2-VHDL20_DWEG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3574
swis2-VHDL20_DWEH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:07 3973
swis2-VHDL20_DWEH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:06 4466
swis2-VHDL20_DWEH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 5053
swis2-VHDL20_DWEH_010800_COR-2602010800-dsw--0-ia5 01-Feb-2026 10:04:12 5057
swis2-VHDL20_DWEH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 5324
swis2-VHDL20_DWEH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:01 5101
swis2-VHDL20_DWEH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 5152
swis2-VHDL20_DWEH_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:36 4989
swis2-VHDL20_DWEH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:01 5903
swis2-VHDL20_DWEH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3455
swis2-VHDL20_DWEI_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:07 3092
swis2-VHDL20_DWEI_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:06 3145
swis2-VHDL20_DWEI_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 3552
swis2-VHDL20_DWEI_010800_COR-2602010800-dsw--0-ia5 01-Feb-2026 10:06:01 3556
swis2-VHDL20_DWEI_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 3791
swis2-VHDL20_DWEI_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:01 3827
swis2-VHDL20_DWEI_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 4083
swis2-VHDL20_DWEI_020400_COR-2602020400-dsw--0-ia5 02-Feb-2026 06:42:36 4071
swis2-VHDL20_DWEI_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:01 5244
swis2-VHDL20_DWEI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3165
swis2-VHDL20_DWHG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 4427
swis2-VHDL20_DWHG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:06 4424
swis2-VHDL20_DWHG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 6146
swis2-VHDL20_DWHG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 4527
swis2-VHDL20_DWHG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:01 4934
swis2-VHDL20_DWHG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:06 4930
swis2-VHDL20_DWHG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 5663
swis2-VHDL20_DWHG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:06 3959
swis2-VHDL20_DWHH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 3961
swis2-VHDL20_DWHH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:08 3961
swis2-VHDL20_DWHH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 5367
swis2-VHDL20_DWHH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 3869
swis2-VHDL20_DWHH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:04 4149
swis2-VHDL20_DWHH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:06 4148
swis2-VHDL20_DWHH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 5225
swis2-VHDL20_DWHH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:06 3544
swis2-VHDL20_DWLG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 2573
swis2-VHDL20_DWLG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:12 2751
swis2-VHDL20_DWLG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 2922
swis2-VHDL20_DWLG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 2250
swis2-VHDL20_DWLG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 2477
swis2-VHDL20_DWLG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:16 3024
swis2-VHDL20_DWLG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 3991
swis2-VHDL20_DWLG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2076
swis2-VHDL20_DWLH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 2537
swis2-VHDL20_DWLH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:12 2798
swis2-VHDL20_DWLH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 3029
swis2-VHDL20_DWLH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 2433
swis2-VHDL20_DWLH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 2574
swis2-VHDL20_DWLH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:16 2685
swis2-VHDL20_DWLH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 3517
swis2-VHDL20_DWLH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2085
swis2-VHDL20_DWLI_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 2671
swis2-VHDL20_DWLI_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:12 2800
swis2-VHDL20_DWLI_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 3003
swis2-VHDL20_DWLI_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 2510
swis2-VHDL20_DWLI_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 2796
swis2-VHDL20_DWLI_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:16 2865
swis2-VHDL20_DWLI_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 3586
swis2-VHDL20_DWLI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2085
swis2-VHDL20_DWMG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 3735
swis2-VHDL20_DWMG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:01 3604
swis2-VHDL20_DWMG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 4194
swis2-VHDL20_DWMG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:06 3451
swis2-VHDL20_DWMG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 4065
swis2-VHDL20_DWMG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 4097
swis2-VHDL20_DWMG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 4867
swis2-VHDL20_DWMG_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:02 5374
swis2-VHDL20_DWMG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3958
swis2-VHDL20_DWMO_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 3609
swis2-VHDL20_DWMO_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:01 3473
swis2-VHDL20_DWMO_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 3989
swis2-VHDL20_DWMO_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:06 3284
swis2-VHDL20_DWMO_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 3951
swis2-VHDL20_DWMO_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 3985
swis2-VHDL20_DWMO_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 4497
swis2-VHDL20_DWMO_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:12 4994
swis2-VHDL20_DWMO_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3630
swis2-VHDL20_DWMP_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 4026
swis2-VHDL20_DWMP_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:01 3890
swis2-VHDL20_DWMP_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:08 4436
swis2-VHDL20_DWMP_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:06 3688
swis2-VHDL20_DWMP_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 4406
swis2-VHDL20_DWMP_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 4424
swis2-VHDL20_DWMP_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 4537
swis2-VHDL20_DWMP_020800_COR-2602020800-dsw--0-ia5 02-Feb-2026 11:19:16 4628
swis2-VHDL20_DWMP_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 4038
swis2-VHDL20_DWPG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 2523
swis2-VHDL20_DWPG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:12 2503
swis2-VHDL20_DWPG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 2620
swis2-VHDL20_DWPG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 2419
swis2-VHDL20_DWPG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 2302
swis2-VHDL20_DWPG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:16 2380
swis2-VHDL20_DWPG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 3083
swis2-VHDL20_DWPG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2305
swis2-VHDL20_DWPH_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 2952
swis2-VHDL20_DWPH_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:00:12 2937
swis2-VHDL20_DWPH_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 3053
swis2-VHDL20_DWPH_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 2930
swis2-VHDL20_DWPH_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 2866
swis2-VHDL20_DWPH_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:00:16 3045
swis2-VHDL20_DWPH_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:06 3614
swis2-VHDL20_DWPH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2809
swis2-VHDL20_DWSG_010200-2602010200-dsw--0-ia5 01-Feb-2026 03:45:05 3623
swis2-VHDL20_DWSG_010400-2602010400-dsw--0-ia5 01-Feb-2026 06:15:01 3380
swis2-VHDL20_DWSG_010800-2602010800-dsw--0-ia5 01-Feb-2026 09:45:01 3865
swis2-VHDL20_DWSG_011300-2602011300-dsw--0-ia5 01-Feb-2026 14:45:05 3662
swis2-VHDL20_DWSG_011800-2602011800-dsw--0-ia5 01-Feb-2026 19:45:04 3618
swis2-VHDL20_DWSG_020200-2602020200-dsw--0-ia5 02-Feb-2026 03:45:06 4092
swis2-VHDL20_DWSG_020400-2602020400-dsw--0-ia5 02-Feb-2026 06:15:01 4219
swis2-VHDL20_DWSG_020800-2602020800-dsw--0-ia5 02-Feb-2026 09:45:01 4183
swis2-VHDL20_DWSG_021300-2602021300-dsw--0-ia5 02-Feb-2026 14:45:01 3995
swis2-VHDL20_DWSG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3530
wst04-VHDL20_DWEG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:12 229501
wst04-VHDL20_DWEG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:21 229223
wst04-VHDL20_DWEG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:12 229127
wst04-VHDL20_DWEG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 229582
wst04-VHDL20_DWEG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:18 230244
wst04-VHDL20_DWEG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:17 229769
wst04-VHDL20_DWEG_020400_COR-2602020400-omedes-..> 02-Feb-2026 06:42:46 229536
wst04-VHDL20_DWEG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:12 228103
wst04-VHDL20_DWEG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 228596
wst04-VHDL20_DWEH_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:16 228242
wst04-VHDL20_DWEH_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:17 227686
wst04-VHDL20_DWEH_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:12 231355
wst04-VHDL20_DWEH_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 231828
wst04-VHDL20_DWEH_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:18 232151
wst04-VHDL20_DWEH_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:11 231660
wst04-VHDL20_DWEH_020400_COR-2602020400-omedes-..> 02-Feb-2026 06:42:46 231381
wst04-VHDL20_DWEH_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:12 230483
wst04-VHDL20_DWEH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 226351
wst04-VHDL20_DWEI_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:16 324536
wst04-VHDL20_DWEI_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:21 324578
wst04-VHDL20_DWEI_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:16 319023
wst04-VHDL20_DWEI_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 319467
wst04-VHDL20_DWEI_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:18 319446
wst04-VHDL20_DWEI_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:17 319562
wst04-VHDL20_DWEI_020400_COR-2602020400-omedes-..> 02-Feb-2026 06:42:52 320085
wst04-VHDL20_DWEI_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:16 318601
wst04-VHDL20_DWEI_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 324683
wst04-VHDL20_DWHG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:12 306586
wst04-VHDL20_DWHG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:12 306576
wst04-VHDL20_DWHG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:12 304394
wst04-VHDL20_DWHG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 302711
wst04-VHDL20_DWHG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:12 303067
wst04-VHDL20_DWHG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:12 303054
wst04-VHDL20_DWHG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:16 304752
wst04-VHDL20_DWHG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 306550
wst04-VHDL20_DWHH_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:12 294135
wst04-VHDL20_DWHH_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:12 294163
wst04-VHDL20_DWHH_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:18 299076
wst04-VHDL20_DWHH_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 297231
wst04-VHDL20_DWHH_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:12 297576
wst04-VHDL20_DWHH_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:16 298315
wst04-VHDL20_DWHH_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:16 295041
wst04-VHDL20_DWHH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 294050
wst04-VHDL20_DWLG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:22 297656
wst04-VHDL20_DWLG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:41 297850
wst04-VHDL20_DWLG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:29 298659
wst04-VHDL20_DWLG_010800_COR-2602010800-omedes-..> 01-Feb-2026 10:11:11 298337
wst04-VHDL20_DWLG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:22 297534
wst04-VHDL20_DWLG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:26 297554
wst04-VHDL20_DWLG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:42 297503
wst04-VHDL20_DWLG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:22 300493
wst04-VHDL20_DWLG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 297851
wst04-VHDL20_DWLH_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:22 302460
wst04-VHDL20_DWLH_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:41 302611
wst04-VHDL20_DWLH_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:29 296005
wst04-VHDL20_DWLH_010800_COR-2602010800-omedes-..> 01-Feb-2026 10:10:37 295660
wst04-VHDL20_DWLH_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:26 295004
wst04-VHDL20_DWLH_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:22 294949
wst04-VHDL20_DWLH_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:42 295096
wst04-VHDL20_DWLH_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:26 292179
wst04-VHDL20_DWLH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 302752
wst04-VHDL20_DWLI_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:22 302747
wst04-VHDL20_DWLI_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:41 302900
wst04-VHDL20_DWLI_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:22 299860
wst04-VHDL20_DWLI_010800_COR-2602010800-omedes-..> 01-Feb-2026 10:11:45 299744
wst04-VHDL20_DWLI_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:22 298998
wst04-VHDL20_DWLI_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:22 299189
wst04-VHDL20_DWLI_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:42 299228
wst04-VHDL20_DWLI_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:26 299432
wst04-VHDL20_DWLI_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 303276
wst04-VHDL20_DWMG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:16 516452
wst04-VHDL20_DWMG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:17 516227
wst04-VHDL20_DWMG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:22 521992
wst04-VHDL20_DWMG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:16 521310
wst04-VHDL20_DWMG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:12 522097
wst04-VHDL20_DWMG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:21 521839
wst04-VHDL20_DWMG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:22 505315
wst04-VHDL20_DWMG_020800_COR-2602020800-omedes-..> 02-Feb-2026 11:19:12 505947
wst04-VHDL20_DWMG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 519198
wst04-VHDL20_DWMO_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:12 404675
wst04-VHDL20_DWMO_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:11 405054
wst04-VHDL20_DWMO_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:22 408148
wst04-VHDL20_DWMO_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:16 407273
wst04-VHDL20_DWMO_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:12 407643
wst04-VHDL20_DWMO_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:13 408436
wst04-VHDL20_DWMO_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:16 401207
wst04-VHDL20_DWMO_020800_COR-2602020800-omedes-..> 02-Feb-2026 11:19:22 401855
wst04-VHDL20_DWMO_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 405997
wst04-VHDL20_DWMP_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:16 555788
wst04-VHDL20_DWMP_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:17 556919
wst04-VHDL20_DWMP_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:22 556457
wst04-VHDL20_DWMP_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:16 554416
wst04-VHDL20_DWMP_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:16 553946
wst04-VHDL20_DWMP_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:17 555273
wst04-VHDL20_DWMP_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:22 537867
wst04-VHDL20_DWMP_020800_COR-2602020800-omedes-..> 02-Feb-2026 11:19:26 538406
wst04-VHDL20_DWMP_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 558992
wst04-VHDL20_DWPG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:26 307322
wst04-VHDL20_DWPG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:31 306975
wst04-VHDL20_DWPG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:29 347487
wst04-VHDL20_DWPG_010800_COR-2602010800-omedes-..> 01-Feb-2026 10:14:17 347188
wst04-VHDL20_DWPG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:22 301868
wst04-VHDL20_DWPG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:22 301399
wst04-VHDL20_DWPG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:30 301967
wst04-VHDL20_DWPG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:26 348926
wst04-VHDL20_DWPG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:26 306958
wst04-VHDL20_DWPH_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:22 219831
wst04-VHDL20_DWPH_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:00:31 219515
wst04-VHDL20_DWPH_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:22 266029
wst04-VHDL20_DWPH_010800_COR-2602010800-omedes-..> 01-Feb-2026 10:14:41 265743
wst04-VHDL20_DWPH_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:22 265424
wst04-VHDL20_DWPH_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:22 220355
wst04-VHDL20_DWPH_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:00:30 220491
wst04-VHDL20_DWPH_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:22 266342
wst04-VHDL20_DWPH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 264450
wst04-VHDL20_DWSG_010200-2602010200-omedes--0.pdf 01-Feb-2026 03:45:12 336094
wst04-VHDL20_DWSG_010400-2602010400-omedes--0.pdf 01-Feb-2026 06:15:11 336088
wst04-VHDL20_DWSG_010800-2602010800-omedes--0.pdf 01-Feb-2026 09:45:12 331782
wst04-VHDL20_DWSG_011300-2602011300-omedes--0.pdf 01-Feb-2026 14:45:17 331962
wst04-VHDL20_DWSG_011800-2602011800-omedes--0.pdf 01-Feb-2026 19:45:12 332660
wst04-VHDL20_DWSG_020200-2602020200-omedes--0.pdf 02-Feb-2026 03:45:12 333204
wst04-VHDL20_DWSG_020400-2602020400-omedes--0.pdf 02-Feb-2026 06:15:17 333945
wst04-VHDL20_DWSG_020800-2602020800-omedes--0.pdf 02-Feb-2026 09:45:12 330279
wst04-VHDL20_DWSG_021300-2602021300-omedes--0.pdf 02-Feb-2026 14:45:12 330223
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