Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jan-2025 13:38 4715
FPDL13_DWMZ_200600 20-Jan-2025 11:45 4067
SXDL31_DWAV_190800 19-Jan-2025 08:42 7812
SXDL31_DWAV_191800 19-Jan-2025 17:23 5193
SXDL31_DWAV_200800 20-Jan-2025 07:45 12727
SXDL31_DWAV_201800 20-Jan-2025 17:17 8210
SXDL31_DWAV_LATEST 20-Jan-2025 17:17 8210
SXDL33_DWAV_190000 19-Jan-2025 10:32 8649
SXDL33_DWAV_200000 20-Jan-2025 10:19 6049
SXDL33_DWAV_LATEST 20-Jan-2025 10:19 6049
ber01-FWDL39_DWMS_191230-2501191230-dsw--0-ia5 19-Jan-2025 12:59 1228
ber01-FWDL39_DWMS_201230-2501201230-dsw--0-ia5 20-Jan-2025 12:44 1171
ber01-VHDL13_DWEH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:28 3700
ber01-VHDL13_DWEH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:28 3562
ber01-VHDL13_DWEH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:28 3526
ber01-VHDL13_DWEH_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:58 3754
ber01-VHDL13_DWEH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:28 3805
ber01-VHDL13_DWEH_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:22 3914
ber01-VHDL13_DWEH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:28 3026
ber01-VHDL13_DWEH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:28 3247
ber01-VHDL13_DWEH_210400-2501210400-dsw--0-ia5 21-Jan-2025 05:58 3457
ber01-VHDL13_DWEH_210400_COR-2501210400-dsw--0-ia5 21-Jan-2025 06:21 3461
ber01-VHDL13_DWHG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 3053
ber01-VHDL13_DWHG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2811
ber01-VHDL13_DWHG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2940
ber01-VHDL13_DWHG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2940
ber01-VHDL13_DWHG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 3067
ber01-VHDL13_DWHG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2716
ber01-VHDL13_DWHG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2883
ber01-VHDL13_DWHG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2883
ber01-VHDL13_DWHH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2591
ber01-VHDL13_DWHH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2476
ber01-VHDL13_DWHH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2459
ber01-VHDL13_DWHH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2459
ber01-VHDL13_DWHH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2786
ber01-VHDL13_DWHH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2214
ber01-VHDL13_DWHH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2494
ber01-VHDL13_DWHH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2494
ber01-VHDL13_DWLG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 1983
ber01-VHDL13_DWLG_190800_COR-2501190800-dsw--0-ia5 19-Jan-2025 15:26 1955
ber01-VHDL13_DWLG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 1944
ber01-VHDL13_DWLG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2136
ber01-VHDL13_DWLG_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:59 1744
ber01-VHDL13_DWLG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2104
ber01-VHDL13_DWLG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 1927
ber01-VHDL13_DWLG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2494
ber01-VHDL13_DWLG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2219
ber01-VHDL13_DWLH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 1971
ber01-VHDL13_DWLH_190800_COR-2501190800-dsw--0-ia5 19-Jan-2025 15:26 1989
ber01-VHDL13_DWLH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 1798
ber01-VHDL13_DWLH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2022
ber01-VHDL13_DWLH_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:59 1651
ber01-VHDL13_DWLH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 1796
ber01-VHDL13_DWLH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 1623
ber01-VHDL13_DWLH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2346
ber01-VHDL13_DWLH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 1918
ber01-VHDL13_DWLI_190800-2501190800-dsw--0-ia5 19-Jan-2025 15:27 1943
ber01-VHDL13_DWLI_190800_COR-2501190800-dsw--0-ia5 19-Jan-2025 15:29 1947
ber01-VHDL13_DWLI_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 1746
ber01-VHDL13_DWLI_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2018
ber01-VHDL13_DWLI_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:59 1684
ber01-VHDL13_DWLI_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 1749
ber01-VHDL13_DWLI_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 1588
ber01-VHDL13_DWLI_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2205
ber01-VHDL13_DWLI_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 1915
ber01-VHDL13_DWMG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2941
ber01-VHDL13_DWMG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2758
ber01-VHDL13_DWMG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2940
ber01-VHDL13_DWMG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2956
ber01-VHDL13_DWMG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2566
ber01-VHDL13_DWMG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2437
ber01-VHDL13_DWMG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 3079
ber01-VHDL13_DWMG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3091
ber01-VHDL13_DWMO_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2835
ber01-VHDL13_DWMO_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2690
ber01-VHDL13_DWMO_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2981
ber01-VHDL13_DWMO_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2997
ber01-VHDL13_DWMO_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2725
ber01-VHDL13_DWMO_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2556
ber01-VHDL13_DWMO_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 3164
ber01-VHDL13_DWMO_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3188
ber01-VHDL13_DWMP_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 3353
ber01-VHDL13_DWMP_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2920
ber01-VHDL13_DWMP_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 3177
ber01-VHDL13_DWMP_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 3192
ber01-VHDL13_DWMP_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2824
ber01-VHDL13_DWMP_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2664
ber01-VHDL13_DWMP_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 3322
ber01-VHDL13_DWMP_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3345
ber01-VHDL13_DWOG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 4271
ber01-VHDL13_DWOG_191700-2501191700-dsw--0-ia5 19-Jan-2025 19:00 3818
ber01-VHDL13_DWOG_200300-2501200300-dsw--0-ia5 20-Jan-2025 04:00 5053
ber01-VHDL13_DWOG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 4879
ber01-VHDL13_DWOG_201700-2501201700-dsw--0-ia5 20-Jan-2025 19:00 3979
ber01-VHDL13_DWOG_210300-2501210300-dsw--0-ia5 21-Jan-2025 04:00 4456
ber01-VHDL13_DWOH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:28 3145
ber01-VHDL13_DWOH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:28 3031
ber01-VHDL13_DWOH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:28 3308
ber01-VHDL13_DWOH_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:58 3400
ber01-VHDL13_DWOH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:28 3364
ber01-VHDL13_DWOH_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:22 3786
ber01-VHDL13_DWOH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:28 3284
ber01-VHDL13_DWOH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:28 3455
ber01-VHDL13_DWOH_210400-2501210400-dsw--0-ia5 21-Jan-2025 05:58 3434
ber01-VHDL13_DWOI_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:28 3124
ber01-VHDL13_DWOI_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:28 3131
ber01-VHDL13_DWOI_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:28 3133
ber01-VHDL13_DWOI_200400-2501200400-dsw--0-ia5 20-Jan-2025 05:58 3165
ber01-VHDL13_DWOI_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:28 3330
ber01-VHDL13_DWOI_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:22 3499
ber01-VHDL13_DWOI_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:28 3160
ber01-VHDL13_DWOI_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:28 3201
ber01-VHDL13_DWOI_210400-2501210400-dsw--0-ia5 21-Jan-2025 05:58 3166
ber01-VHDL13_DWON_190724-2501190724-dsw--0-ia5 19-Jan-2025 07:24 4306
ber01-VHDL13_DWON_190749-2501190749-dsw--0-ia5 19-Jan-2025 07:49 4351
ber01-VHDL13_DWON_191454-2501191454-dsw--0-ia5 19-Jan-2025 14:54 3618
ber01-VHDL13_DWON_191800-2501191800-dsw--0-ia5 19-Jan-2025 18:00 3521
ber01-VHDL13_DWON_200338-2501200338-dsw--0-ia5 20-Jan-2025 03:39 3881
ber01-VHDL13_DWON_200611-2501200611-dsw--0-ia5 20-Jan-2025 06:11 3619
ber01-VHDL13_DWON_201010-2501201010-dsw--0-ia5 20-Jan-2025 10:10 3636
ber01-VHDL13_DWON_201534-2501201534-dsw--0-ia5 20-Jan-2025 15:34 3159
ber01-VHDL13_DWON_201738-2501201738-dsw--0-ia5 20-Jan-2025 17:38 3396
ber01-VHDL13_DWON_210337-2501210337-dsw--0-ia5 21-Jan-2025 03:38 3742
ber01-VHDL13_DWON_210629-2501210629-dsw--0-ia5 21-Jan-2025 06:29 3519
ber01-VHDL13_DWPG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2331
ber01-VHDL13_DWPG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 1963
ber01-VHDL13_DWPG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2157
ber01-VHDL13_DWPG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2586
ber01-VHDL13_DWPG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2718
ber01-VHDL13_DWPG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2333
ber01-VHDL13_DWPG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2495
ber01-VHDL13_DWPG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2849
ber01-VHDL13_DWPH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2583
ber01-VHDL13_DWPH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2109
ber01-VHDL13_DWPH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2357
ber01-VHDL13_DWPH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2649
ber01-VHDL13_DWPH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2608
ber01-VHDL13_DWPH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2171
ber01-VHDL13_DWPH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 2476
ber01-VHDL13_DWPH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2797
ber01-VHDL13_DWSG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 3033
ber01-VHDL13_DWSG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2383
ber01-VHDL13_DWSG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:30 2687
ber01-VHDL13_DWSG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2697
ber01-VHDL13_DWSG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2647
ber01-VHDL13_DWSG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2728
ber01-VHDL13_DWSG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:30 3156
ber01-VHDL13_DWSG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3169
ber01-VHDL13_DWSN_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2296
ber01-VHDL13_DWSN_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 1957
ber01-VHDL13_DWSN_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2148
ber01-VHDL13_DWSN_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2147
ber01-VHDL13_DWSN_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2072
ber01-VHDL13_DWSN_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2204
ber01-VHDL13_DWSO_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 3064
ber01-VHDL13_DWSO_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2401
ber01-VHDL13_DWSO_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2691
ber01-VHDL13_DWSO_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2691
ber01-VHDL13_DWSO_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2720
ber01-VHDL13_DWSO_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2960
ber01-VHDL13_DWSP_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:30 2710
ber01-VHDL13_DWSP_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:30 2272
ber01-VHDL13_DWSP_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2474
ber01-VHDL13_DWSP_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:30 2393
ber01-VHDL13_DWSP_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:30 2377
ber01-VHDL13_DWSP_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2502
ber01-VHDL17_DWOG_191200-2501191200-dsw--0-ia5 19-Jan-2025 11:25 3933
ber01-VHDL17_DWOG_201200-2501201200-dsw--0-ia5 20-Jan-2025 12:11 3346
swis2-VHDL20_DWEG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 4017
swis2-VHDL20_DWEG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3555
swis2-VHDL20_DWEG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3864
swis2-VHDL20_DWEG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3931
swis2-VHDL20_DWEG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 4337
swis2-VHDL20_DWEG_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:21 4679
swis2-VHDL20_DWEG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3822
swis2-VHDL20_DWEG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3929
swis2-VHDL20_DWEG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 4031
swis2-VHDL20_DWEH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 4748
swis2-VHDL20_DWEH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 4283
swis2-VHDL20_DWEH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 4245
swis2-VHDL20_DWEH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 4298
swis2-VHDL20_DWEH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 4692
swis2-VHDL20_DWEH_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:22 4718
swis2-VHDL20_DWEH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3593
swis2-VHDL20_DWEH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3765
swis2-VHDL20_DWEH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 4162
swis2-VHDL20_DWEI_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 4041
swis2-VHDL20_DWEI_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3675
swis2-VHDL20_DWEI_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3807
swis2-VHDL20_DWEI_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3722
swis2-VHDL20_DWEI_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 4280
swis2-VHDL20_DWEI_200800_COR-2501200800-dsw--0-ia5 20-Jan-2025 11:21 4434
swis2-VHDL20_DWEI_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3718
swis2-VHDL20_DWEI_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3684
swis2-VHDL20_DWEI_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 3882
swis2-VHDL20_DWHG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3784
swis2-VHDL20_DWHG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3331
swis2-VHDL20_DWHG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3460
swis2-VHDL20_DWHG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 3331
swis2-VHDL20_DWHG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3698
swis2-VHDL20_DWHG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3156
swis2-VHDL20_DWHG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3323
swis2-VHDL20_DWHG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3281
swis2-VHDL20_DWHH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3330
swis2-VHDL20_DWHH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3002
swis2-VHDL20_DWHH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2985
swis2-VHDL20_DWHH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2858
swis2-VHDL20_DWHH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3453
swis2-VHDL20_DWHH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2636
swis2-VHDL20_DWHH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 2916
swis2-VHDL20_DWHH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2901
swis2-VHDL20_DWLG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 2499
swis2-VHDL20_DWLG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2367
swis2-VHDL20_DWLG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2561
swis2-VHDL20_DWLG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2165
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swis2-VHDL20_DWLG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 2918
swis2-VHDL20_DWLG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2641
swis2-VHDL20_DWLH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 2498
swis2-VHDL20_DWLH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2229
swis2-VHDL20_DWLH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2454
swis2-VHDL20_DWLH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2079
swis2-VHDL20_DWLH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 2432
swis2-VHDL20_DWLH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2051
swis2-VHDL20_DWLH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 2777
swis2-VHDL20_DWLH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2347
swis2-VHDL20_DWLI_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 2430
swis2-VHDL20_DWLI_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2171
swis2-VHDL20_DWLI_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2445
swis2-VHDL20_DWLI_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2104
swis2-VHDL20_DWLI_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 2375
swis2-VHDL20_DWLI_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2011
swis2-VHDL20_DWLI_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 2631
swis2-VHDL20_DWLI_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 2336
swis2-VHDL20_DWMG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3578
swis2-VHDL20_DWMG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3139
swis2-VHDL20_DWMG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3362
swis2-VHDL20_DWMG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3380
swis2-VHDL20_DWMG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3204
swis2-VHDL20_DWMG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2861
swis2-VHDL20_DWMG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3501
swis2-VHDL20_DWMG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 3514
swis2-VHDL20_DWMO_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3451
swis2-VHDL20_DWMO_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3076
swis2-VHDL20_DWMO_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3407
swis2-VHDL20_DWMO_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3425
swis2-VHDL20_DWMO_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3342
swis2-VHDL20_DWMO_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2972
swis2-VHDL20_DWMO_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3592
swis2-VHDL20_DWMO_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 3615
swis2-VHDL20_DWMP_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3996
swis2-VHDL20_DWMP_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 3294
swis2-VHDL20_DWMP_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3602
swis2-VHDL20_DWMP_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3617
swis2-VHDL20_DWMP_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3469
swis2-VHDL20_DWMP_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3076
swis2-VHDL20_DWMP_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3749
swis2-VHDL20_DWMP_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 3769
swis2-VHDL20_DWPG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 2852
swis2-VHDL20_DWPG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2480
swis2-VHDL20_DWPG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2499
swis2-VHDL20_DWPG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 2950
swis2-VHDL20_DWPG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3540
swis2-VHDL20_DWPG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3156
swis2-VHDL20_DWPG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3175
swis2-VHDL20_DWPG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3221
swis2-VHDL20_DWPH_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3106
swis2-VHDL20_DWPH_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2626
swis2-VHDL20_DWPH_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 2698
swis2-VHDL20_DWPH_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:00 3015
swis2-VHDL20_DWPH_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3309
swis2-VHDL20_DWPH_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 2872
swis2-VHDL20_DWPH_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3052
swis2-VHDL20_DWPH_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:00 3171
swis2-VHDL20_DWSG_190800-2501190800-dsw--0-ia5 19-Jan-2025 09:45 3557
swis2-VHDL20_DWSG_191800-2501191800-dsw--0-ia5 19-Jan-2025 19:45 2750
swis2-VHDL20_DWSG_200200-2501200200-dsw--0-ia5 20-Jan-2025 03:45 3085
swis2-VHDL20_DWSG_200400-2501200400-dsw--0-ia5 20-Jan-2025 06:15 3103
swis2-VHDL20_DWSG_200800-2501200800-dsw--0-ia5 20-Jan-2025 09:45 3251
swis2-VHDL20_DWSG_201800-2501201800-dsw--0-ia5 20-Jan-2025 19:45 3136
swis2-VHDL20_DWSG_210200-2501210200-dsw--0-ia5 21-Jan-2025 03:45 3554
swis2-VHDL20_DWSG_210400-2501210400-dsw--0-ia5 21-Jan-2025 06:15 3575
wst04-VHDL20_DWEG_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 255583
wst04-VHDL20_DWEG_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 254461
wst04-VHDL20_DWEG_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 255469
wst04-VHDL20_DWEG_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 254995
wst04-VHDL20_DWEG_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 258894
wst04-VHDL20_DWEG_200800_COR-2501200800-omedes-..> 20-Jan-2025 11:22 259130
wst04-VHDL20_DWEG_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 256939
wst04-VHDL20_DWEG_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 257806
wst04-VHDL20_DWEG_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 257098
wst04-VHDL20_DWEH_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 253459
wst04-VHDL20_DWEH_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 252570
wst04-VHDL20_DWEH_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 252743
wst04-VHDL20_DWEH_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 252077
wst04-VHDL20_DWEH_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 254737
wst04-VHDL20_DWEH_200800_COR-2501200800-omedes-..> 20-Jan-2025 11:22 254745
wst04-VHDL20_DWEH_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 252697
wst04-VHDL20_DWEH_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 254062
wst04-VHDL20_DWEH_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 253910
wst04-VHDL20_DWEI_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 345451
wst04-VHDL20_DWEI_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 344737
wst04-VHDL20_DWEI_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 344692
wst04-VHDL20_DWEI_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 344549
wst04-VHDL20_DWEI_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 353337
wst04-VHDL20_DWEI_200800_COR-2501200800-omedes-..> 20-Jan-2025 11:22 353417
wst04-VHDL20_DWEI_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 351598
wst04-VHDL20_DWEI_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 351963
wst04-VHDL20_DWEI_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 351970
wst04-VHDL20_DWHG_190800-2501190800-oflxs888--0..> 19-Jan-2025 09:45 345440
wst04-VHDL20_DWHG_191800-2501191800-oflxs888--0..> 19-Jan-2025 19:45 344138
wst04-VHDL20_DWHG_200200-2501200200-oflxs888--0..> 20-Jan-2025 03:45 343539
wst04-VHDL20_DWHG_200400-2501200400-oflxs888--0..> 20-Jan-2025 06:00 343519
wst04-VHDL20_DWHG_200800-2501200800-oflxs888--0..> 20-Jan-2025 09:45 343655
wst04-VHDL20_DWHG_201800-2501201800-oflxs888--0..> 20-Jan-2025 19:45 341961
wst04-VHDL20_DWHG_210200-2501210200-oflxs888--0..> 21-Jan-2025 03:45 342893
wst04-VHDL20_DWHG_210400-2501210400-oflxs888--0..> 21-Jan-2025 06:00 342891
wst04-VHDL20_DWHH_190800-2501190800-oflxs888--0..> 19-Jan-2025 09:45 328030
wst04-VHDL20_DWHH_191800-2501191800-oflxs888--0..> 19-Jan-2025 19:45 327551
wst04-VHDL20_DWHH_200200-2501200200-oflxs888--0..> 20-Jan-2025 03:45 327566
wst04-VHDL20_DWHH_200400-2501200400-oflxs888--0..> 20-Jan-2025 06:00 327504
wst04-VHDL20_DWHH_200800-2501200800-oflxs888--0..> 20-Jan-2025 09:45 329543
wst04-VHDL20_DWHH_201800-2501201800-oflxs888--0..> 20-Jan-2025 19:45 327922
wst04-VHDL20_DWHH_210200-2501210200-oflxs888--0..> 21-Jan-2025 03:45 328284
wst04-VHDL20_DWHH_210400-2501210400-oflxs888--0..> 21-Jan-2025 06:00 328300
wst04-VHDL20_DWLG_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:40 340527
wst04-VHDL20_DWLG_190800_COR-2501190800-omedes-..> 19-Jan-2025 15:30 341327
wst04-VHDL20_DWLG_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:40 340913
wst04-VHDL20_DWLG_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:40 340100
wst04-VHDL20_DWLG_200400-2501200400-omedes--0.pdf 20-Jan-2025 05:59 340232
wst04-VHDL20_DWLG_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:40 339612
wst04-VHDL20_DWLG_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:40 338939
wst04-VHDL20_DWLG_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:40 338933
wst04-VHDL20_DWLG_210400-2501210400-omedes--0.pdf 21-Jan-2025 05:59 339011
wst04-VHDL20_DWLH_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:40 345002
wst04-VHDL20_DWLH_190800_COR-2501190800-omedes-..> 19-Jan-2025 15:30 346040
wst04-VHDL20_DWLH_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:40 345259
wst04-VHDL20_DWLH_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:40 344399
wst04-VHDL20_DWLH_200400-2501200400-omedes--0.pdf 20-Jan-2025 05:59 344079
wst04-VHDL20_DWLH_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:40 340671
wst04-VHDL20_DWLH_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:40 339958
wst04-VHDL20_DWLH_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:40 340386
wst04-VHDL20_DWLH_210400-2501210400-omedes--0.pdf 21-Jan-2025 05:59 340251
wst04-VHDL20_DWLI_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:40 345237
wst04-VHDL20_DWLI_190800_COR-2501190800-omedes-..> 19-Jan-2025 15:31 346332
wst04-VHDL20_DWLI_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:40 345547
wst04-VHDL20_DWLI_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:40 344848
wst04-VHDL20_DWLI_200400-2501200400-omedes--0.pdf 20-Jan-2025 05:59 345030
wst04-VHDL20_DWLI_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:40 347392
wst04-VHDL20_DWLI_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:40 346675
wst04-VHDL20_DWLI_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:40 347377
wst04-VHDL20_DWLI_210400-2501210400-omedes--0.pdf 21-Jan-2025 05:59 347473
wst04-VHDL20_DWMG_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 555365
wst04-VHDL20_DWMG_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 554844
wst04-VHDL20_DWMG_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 555307
wst04-VHDL20_DWMG_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 555489
wst04-VHDL20_DWMG_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 554553
wst04-VHDL20_DWMG_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 553050
wst04-VHDL20_DWMG_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 553072
wst04-VHDL20_DWMG_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 553327
wst04-VHDL20_DWMO_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 448648
wst04-VHDL20_DWMO_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 448025
wst04-VHDL20_DWMO_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 448460
wst04-VHDL20_DWMO_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 449297
wst04-VHDL20_DWMO_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 448970
wst04-VHDL20_DWMO_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 448048
wst04-VHDL20_DWMO_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 448191
wst04-VHDL20_DWMO_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 449013
wst04-VHDL20_DWMP_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 568371
wst04-VHDL20_DWMP_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 567483
wst04-VHDL20_DWMP_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 566994
wst04-VHDL20_DWMP_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 568251
wst04-VHDL20_DWMP_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 564086
wst04-VHDL20_DWMP_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 562832
wst04-VHDL20_DWMP_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 562186
wst04-VHDL20_DWMP_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 563140
wst04-VHDL20_DWPG_190800-2501190800-zblks892--0..> 19-Jan-2025 09:45 391504
wst04-VHDL20_DWPG_191800-2501191800-zblks892--0..> 19-Jan-2025 19:45 347196
wst04-VHDL20_DWPG_200200-2501200200-zblks892--0..> 20-Jan-2025 03:45 345968
wst04-VHDL20_DWPG_200400-2501200400-zblks892--0..> 20-Jan-2025 06:00 346362
wst04-VHDL20_DWPG_200800-2501200800-zblks892--0..> 20-Jan-2025 09:45 385977
wst04-VHDL20_DWPG_201800-2501201800-zblks892--0..> 20-Jan-2025 19:45 340666
wst04-VHDL20_DWPG_210200-2501210200-zblks892--0..> 21-Jan-2025 03:45 340838
wst04-VHDL20_DWPG_210400-2501210400-zblks892--0..> 21-Jan-2025 06:00 341461
wst04-VHDL20_DWPH_190800-2501190800-zblks892--0..> 19-Jan-2025 09:45 293288
wst04-VHDL20_DWPH_191800-2501191800-zblks892--0..> 19-Jan-2025 19:45 292766
wst04-VHDL20_DWPH_200200-2501200200-zblks892--0..> 20-Jan-2025 03:45 247524
wst04-VHDL20_DWPH_200400-2501200400-zblks892--0..> 20-Jan-2025 06:00 247759
wst04-VHDL20_DWPH_200800-2501200800-zblks892--0..> 20-Jan-2025 09:45 294662
wst04-VHDL20_DWPH_201800-2501201800-zblks892--0..> 20-Jan-2025 19:45 294306
wst04-VHDL20_DWPH_210200-2501210200-zblks892--0..> 21-Jan-2025 03:45 250519
wst04-VHDL20_DWPH_210400-2501210400-zblks892--0..> 21-Jan-2025 06:00 295615
wst04-VHDL20_DWSG_190800-2501190800-omedes--0.pdf 19-Jan-2025 09:45 365911
wst04-VHDL20_DWSG_191800-2501191800-omedes--0.pdf 19-Jan-2025 19:45 364930
wst04-VHDL20_DWSG_200200-2501200200-omedes--0.pdf 20-Jan-2025 03:45 364201
wst04-VHDL20_DWSG_200400-2501200400-omedes--0.pdf 20-Jan-2025 06:15 364375
wst04-VHDL20_DWSG_200800-2501200800-omedes--0.pdf 20-Jan-2025 09:45 367899
wst04-VHDL20_DWSG_201800-2501201800-omedes--0.pdf 20-Jan-2025 19:45 368965
wst04-VHDL20_DWSG_210200-2501210200-omedes--0.pdf 21-Jan-2025 03:45 369638
wst04-VHDL20_DWSG_210400-2501210400-omedes--0.pdf 21-Jan-2025 06:15 369747