Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Oct-2025 13:44:35 3290
FPDL13_DWMZ_160600 16-Oct-2025 12:48:15 6233
SXDL31_DWAV_150800 15-Oct-2025 06:38:29 6598
SXDL31_DWAV_151800 15-Oct-2025 16:43:59 4685
SXDL31_DWAV_160800 16-Oct-2025 06:43:31 13323
SXDL31_DWAV_161800 16-Oct-2025 16:51:55 4013
SXDL31_DWAV_LATEST 16-Oct-2025 16:51:55 4013
SXDL33_DWAV_150000 15-Oct-2025 09:22:29 13864
SXDL33_DWAV_160000 16-Oct-2025 09:34:10 8231
SXDL33_DWAV_LATEST 16-Oct-2025 09:34:10 8231
ber01-FWDL39_DWMS_151230-2510151230-dsw--0-ia5 15-Oct-2025 10:51:47 1569
ber01-FWDL39_DWMS_161230-2510161230-dsw--0-ia5 16-Oct-2025 11:40:26 2004
ber01-VHDL13_DWEH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:28:17 2208
ber01-VHDL13_DWEH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:28:16 2067
ber01-VHDL13_DWEH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:28:19 2410
ber01-VHDL13_DWEH_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:58:17 2381
ber01-VHDL13_DWEH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:28:16 2424
ber01-VHDL13_DWEH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:28:17 2276
ber01-VHDL13_DWEH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:28:13 2632
ber01-VHDL13_DWEH_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:58:12 2684
ber01-VHDL13_DWHG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:09 2442
ber01-VHDL13_DWHG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:06 2649
ber01-VHDL13_DWHG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2746
ber01-VHDL13_DWHG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:11 2785
ber01-VHDL13_DWHG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:11 2810
ber01-VHDL13_DWHG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:06 2535
ber01-VHDL13_DWHG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:06 3077
ber01-VHDL13_DWHG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:12 3077
ber01-VHDL13_DWHH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:09 2567
ber01-VHDL13_DWHH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:06 2713
ber01-VHDL13_DWHH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2649
ber01-VHDL13_DWHH_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:11 2659
ber01-VHDL13_DWHH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:11 2981
ber01-VHDL13_DWHH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:06 2499
ber01-VHDL13_DWHH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:06 2804
ber01-VHDL13_DWHH_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:12 2804
ber01-VHDL13_DWLG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:01 2593
ber01-VHDL13_DWLG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2066
ber01-VHDL13_DWLG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:03 2097
ber01-VHDL13_DWLG_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:59:57 2153
ber01-VHDL13_DWLG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2280
ber01-VHDL13_DWLG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2316
ber01-VHDL13_DWLG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2305
ber01-VHDL13_DWLG_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:59:56 2423
ber01-VHDL13_DWLH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:01 2181
ber01-VHDL13_DWLH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 1859
ber01-VHDL13_DWLH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:03 1863
ber01-VHDL13_DWLH_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:59:57 1863
ber01-VHDL13_DWLH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 1915
ber01-VHDL13_DWLH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 1948
ber01-VHDL13_DWLH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2050
ber01-VHDL13_DWLH_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:59:56 2084
ber01-VHDL13_DWLI_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:01 2319
ber01-VHDL13_DWLI_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 1871
ber01-VHDL13_DWLI_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:03 1941
ber01-VHDL13_DWLI_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:59:57 1893
ber01-VHDL13_DWLI_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 1921
ber01-VHDL13_DWLI_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2079
ber01-VHDL13_DWLI_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2080
ber01-VHDL13_DWLI_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:59:56 2104
ber01-VHDL13_DWMG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:09 2295
ber01-VHDL13_DWMG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2235
ber01-VHDL13_DWMG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2408
ber01-VHDL13_DWMG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:07 2455
ber01-VHDL13_DWMG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2628
ber01-VHDL13_DWMG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2371
ber01-VHDL13_DWMG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2773
ber01-VHDL13_DWMG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:02 2786
ber01-VHDL13_DWMO_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:09 2374
ber01-VHDL13_DWMO_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2221
ber01-VHDL13_DWMO_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2344
ber01-VHDL13_DWMO_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:07 2390
ber01-VHDL13_DWMO_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2545
ber01-VHDL13_DWMO_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2288
ber01-VHDL13_DWMO_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2391
ber01-VHDL13_DWMO_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:02 2428
ber01-VHDL13_DWMP_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:09 2383
ber01-VHDL13_DWMP_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2244
ber01-VHDL13_DWMP_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2400
ber01-VHDL13_DWMP_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:07 2469
ber01-VHDL13_DWMP_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2743
ber01-VHDL13_DWMP_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2512
ber01-VHDL13_DWMP_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2897
ber01-VHDL13_DWMP_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:02 2937
ber01-VHDL13_DWOG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:43:12 3720
ber01-VHDL13_DWOG_151700-2510151700-dsw--0-ia5 15-Oct-2025 18:00:07 3585
ber01-VHDL13_DWOG_160300-2510160300-dsw--0-ia5 16-Oct-2025 03:00:03 4212
ber01-VHDL13_DWOG_160800-2510160800-dsw--0-ia5 16-Oct-2025 15:03:01 3971
ber01-VHDL13_DWOG_160800_COR-2510160800-dsw--0-ia5 16-Oct-2025 14:32:43 3981
ber01-VHDL13_DWOG_161700-2510161700-dsw--0-ia5 16-Oct-2025 18:00:01 4003
ber01-VHDL13_DWOG_170300-2510170300-dsw--0-ia5 17-Oct-2025 03:00:07 4194
ber01-VHDL13_DWOH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:28:17 2392
ber01-VHDL13_DWOH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:28:12 2208
ber01-VHDL13_DWOH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:28:11 2450
ber01-VHDL13_DWOH_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:58:11 2418
ber01-VHDL13_DWOH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:28:16 2396
ber01-VHDL13_DWOH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:28:17 2195
ber01-VHDL13_DWOH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:28:17 2488
ber01-VHDL13_DWOH_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:58:12 2443
ber01-VHDL13_DWOI_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:28:17 2396
ber01-VHDL13_DWOI_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:28:12 2183
ber01-VHDL13_DWOI_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:28:19 2349
ber01-VHDL13_DWOI_160400-2510160400-dsw--0-ia5 16-Oct-2025 04:58:11 2312
ber01-VHDL13_DWOI_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:28:12 2321
ber01-VHDL13_DWOI_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:28:11 2158
ber01-VHDL13_DWOI_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:28:17 2353
ber01-VHDL13_DWOI_170400-2510170400-dsw--0-ia5 17-Oct-2025 04:58:17 2307
ber01-VHDL13_DWON_150842-2510150842-dsw--0-ia5 15-Oct-2025 08:42:37 3904
ber01-VHDL13_DWON_151448-2510151448-dsw--0-ia5 15-Oct-2025 14:48:42 3461
ber01-VHDL13_DWON_151701-2510151701-dsw--0-ia5 15-Oct-2025 17:01:46 3614
ber01-VHDL13_DWON_152041-2510152041-dsw--0-ia5 15-Oct-2025 20:41:07 3747
ber01-VHDL13_DWON_152043-2510152043-dsw--0-ia5 15-Oct-2025 20:43:11 3747
ber01-VHDL13_DWON_152107-2510152107-dsw--0-ia5 15-Oct-2025 21:07:12 3747
ber01-VHDL13_DWON_160127-2510160127-dsw--0-ia5 16-Oct-2025 01:27:17 4004
ber01-VHDL13_DWON_160246-2510160246-dsw--0-ia5 16-Oct-2025 02:46:38 3873
ber01-VHDL13_DWON_160529-2510160529-dsw--0-ia5 16-Oct-2025 05:29:47 3857
ber01-VHDL13_DWON_160604-2510160604-dsw--0-ia5 16-Oct-2025 06:04:26 3812
ber01-VHDL13_DWON_160818-2510160818-dsw--0-ia5 16-Oct-2025 08:18:07 3812
ber01-VHDL13_DWON_160901-2510160901-dsw--0-ia5 16-Oct-2025 09:01:37 3792
ber01-VHDL13_DWON_161431-2510161431-dsw--0-ia5 16-Oct-2025 14:31:26 3709
ber01-VHDL13_DWON_161502-2510161502-dsw--0-ia5 16-Oct-2025 15:02:38 3709
ber01-VHDL13_DWON_161731-2510161731-dsw--0-ia5 16-Oct-2025 17:31:48 3558
ber01-VHDL13_DWON_170140-2510170140-dsw--0-ia5 17-Oct-2025 01:40:31 3625
ber01-VHDL13_DWON_170258-2510170258-dsw--0-ia5 17-Oct-2025 02:58:31 3625
ber01-VHDL13_DWON_170525-2510170525-dsw--0-ia5 17-Oct-2025 05:25:51 3870
ber01-VHDL13_DWON_170603-2510170603-dsw--0-ia5 17-Oct-2025 06:03:16 3845
ber01-VHDL13_DWPG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:03 2193
ber01-VHDL13_DWPG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 1842
ber01-VHDL13_DWPG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 1881
ber01-VHDL13_DWPG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:01 1871
ber01-VHDL13_DWPG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 1901
ber01-VHDL13_DWPG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 1821
ber01-VHDL13_DWPG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 1954
ber01-VHDL13_DWPG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:02 2172
ber01-VHDL13_DWPH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:03 2703
ber01-VHDL13_DWPH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2289
ber01-VHDL13_DWPH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2230
ber01-VHDL13_DWPH_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:01 2304
ber01-VHDL13_DWPH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2378
ber01-VHDL13_DWPH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2156
ber01-VHDL13_DWPH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2275
ber01-VHDL13_DWPH_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:02 2688
ber01-VHDL13_DWSG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:30:01 2792
ber01-VHDL13_DWSG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:30:02 2527
ber01-VHDL13_DWSG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:30:08 2862
ber01-VHDL13_DWSG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:07 2928
ber01-VHDL13_DWSG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:30:02 2922
ber01-VHDL13_DWSG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:30:02 2502
ber01-VHDL13_DWSG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:30:02 2890
ber01-VHDL13_DWSG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:08 2830
ber01-VHDL17_DWOG_151200-2510151200-dsw--0-ia5 15-Oct-2025 10:50:42 2708
ber01-VHDL17_DWOG_161200-2510161200-dsw--0-ia5 16-Oct-2025 11:54:21 2939
swis2-VHDL20_DWEG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:03 2832
swis2-VHDL20_DWEG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:06 2518
swis2-VHDL20_DWEG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:07 2711
swis2-VHDL20_DWEG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:15:06 2719
swis2-VHDL20_DWEG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:06 2833
swis2-VHDL20_DWEG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:02 2502
swis2-VHDL20_DWEG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:12 2746
swis2-VHDL20_DWEG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:15:02 2744
swis2-VHDL20_DWEH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:27 2674
swis2-VHDL20_DWEH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:17 2408
swis2-VHDL20_DWEH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:25 2716
swis2-VHDL20_DWEH_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:15:22 2694
swis2-VHDL20_DWEH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:20 2887
swis2-VHDL20_DWEH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:16 2611
swis2-VHDL20_DWEH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:16 2934
swis2-VHDL20_DWEH_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:15:22 2998
swis2-VHDL20_DWEI_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:03 2883
swis2-VHDL20_DWEI_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:06 2518
swis2-VHDL20_DWEI_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:07 2622
swis2-VHDL20_DWEI_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:15:22 2644
swis2-VHDL20_DWEI_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:06 2805
swis2-VHDL20_DWEI_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:02 2490
swis2-VHDL20_DWEI_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:12 2626
swis2-VHDL20_DWEI_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:15:22 2639
swis2-VHDL20_DWHG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:07 2979
swis2-VHDL20_DWHG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:06 2832
swis2-VHDL20_DWHG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:04 2932
swis2-VHDL20_DWHG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:11 2968
swis2-VHDL20_DWHG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:06 3344
swis2-VHDL20_DWHG_160800_COR-2510160800-dsw--0-ia5 16-Oct-2025 08:58:02 3348
swis2-VHDL20_DWHG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:02 2718
swis2-VHDL20_DWHG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:12 3263
swis2-VHDL20_DWHG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:12 3260
swis2-VHDL20_DWHH_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:07 3113
swis2-VHDL20_DWHH_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:06 2899
swis2-VHDL20_DWHH_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:04 2835
swis2-VHDL20_DWHH_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:11 2845
swis2-VHDL20_DWHH_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:06 3524
swis2-VHDL20_DWHH_160800_COR-2510160800-dsw--0-ia5 16-Oct-2025 08:57:32 3528
swis2-VHDL20_DWHH_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:02 2685
swis2-VHDL20_DWHH_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:12 2990
swis2-VHDL20_DWHH_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:12 2990
swis2-VHDL20_DWLG_150800-2510150800-dsw--0-ia5 15-Oct-2025 08:45:07 3113
swis2-VHDL20_DWLG_151800-2510151800-dsw--0-ia5 15-Oct-2025 18:45:02 2437
swis2-VHDL20_DWLG_160200-2510160200-dsw--0-ia5 16-Oct-2025 02:45:04 2471
swis2-VHDL20_DWLG_160400-2510160400-dsw--0-ia5 16-Oct-2025 05:00:27 2520
swis2-VHDL20_DWLG_160800-2510160800-dsw--0-ia5 16-Oct-2025 08:45:06 2797
swis2-VHDL20_DWLG_161800-2510161800-dsw--0-ia5 16-Oct-2025 18:45:02 2683
swis2-VHDL20_DWLG_170200-2510170200-dsw--0-ia5 17-Oct-2025 02:45:12 2675
swis2-VHDL20_DWLG_170400-2510170400-dsw--0-ia5 17-Oct-2025 05:00:22 2791
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wst04-VHDL20_DWLG_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:40:51 339812
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wst04-VHDL20_DWLH_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:40:29 337315
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wst04-VHDL20_DWLI_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:40:51 341117
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wst04-VHDL20_DWLI_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:40:42 342196
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wst04-VHDL20_DWLI_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:40:42 336300
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wst04-VHDL20_DWMG_150800_COR-2510150800-omedes-..> 15-Oct-2025 09:13:47 543941
wst04-VHDL20_DWMG_151800-2510151800-omedes--0.pdf 15-Oct-2025 18:45:17 533816
wst04-VHDL20_DWMG_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 535414
wst04-VHDL20_DWMG_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:15:12 535413
wst04-VHDL20_DWMG_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:26 535103
wst04-VHDL20_DWMG_160800_COR-2510160800-omedes-..> 16-Oct-2025 12:05:28 530436
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wst04-VHDL20_DWMG_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:16 530078
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wst04-VHDL20_DWMO_150800_COR-2510150800-omedes-..> 15-Oct-2025 09:14:41 446804
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wst04-VHDL20_DWMO_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 435311
wst04-VHDL20_DWMO_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:15:12 435506
wst04-VHDL20_DWMO_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:26 436388
wst04-VHDL20_DWMO_160800_COR-2510160800-omedes-..> 16-Oct-2025 12:06:00 430460
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wst04-VHDL20_DWMO_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:12 428870
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wst04-VHDL20_DWMP_150800_COR-2510150800-omedes-..> 15-Oct-2025 09:15:51 543359
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wst04-VHDL20_DWMP_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 535188
wst04-VHDL20_DWMP_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:15:16 535741
wst04-VHDL20_DWMP_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:26 536221
wst04-VHDL20_DWMP_160800_COR-2510160800-omedes-..> 16-Oct-2025 12:06:37 544463
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wst04-VHDL20_DWMP_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:13 543474
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wst04-VHDL20_DWPG_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 345677
wst04-VHDL20_DWPG_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:00:13 345279
wst04-VHDL20_DWPG_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:12 390169
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wst04-VHDL20_DWPG_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:18 352141
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wst04-VHDL20_DWPH_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 254377
wst04-VHDL20_DWPH_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:00:13 254438
wst04-VHDL20_DWPH_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:12 299450
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wst04-VHDL20_DWPH_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:18 255875
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wst04-VHDL20_DWSG_160200-2510160200-omedes--0.pdf 16-Oct-2025 02:45:25 353227
wst04-VHDL20_DWSG_160400-2510160400-omedes--0.pdf 16-Oct-2025 05:15:12 353187
wst04-VHDL20_DWSG_160800-2510160800-omedes--0.pdf 16-Oct-2025 08:45:12 353260
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wst04-VHDL20_DWSG_170200-2510170200-omedes--0.pdf 17-Oct-2025 02:45:12 353415
wst04-VHDL20_DWSG_170400-2510170400-omedes--0.pdf 17-Oct-2025 05:15:12 353087