Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Feb-2026 12:42:45 4833
FPDL13_DWMZ_250600 25-Feb-2026 11:42:23 2827
SXDL31_DWAV_241800 24-Feb-2026 17:01:40 6555
SXDL31_DWAV_250800 25-Feb-2026 09:06:23 12053
SXDL31_DWAV_251800 25-Feb-2026 17:41:25 4859
SXDL31_DWAV_260800 26-Feb-2026 07:41:34 7337
SXDL31_DWAV_LATEST 26-Feb-2026 07:41:34 7337
SXDL33_DWAV_250000 25-Feb-2026 11:06:49 9515
SXDL33_DWAV_260000 26-Feb-2026 10:28:49 9240
SXDL33_DWAV_LATEST 26-Feb-2026 10:28:49 9240
ber01-FWDL39_DWMS_251230-2602251230-dsw--0-ia5 25-Feb-2026 12:12:22 1478
ber01-FWDL39_DWMS_261230-2602261230-dsw--0-ia5 26-Feb-2026 11:54:42 1473
ber01-VHDL13_DWEH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:17 2096
ber01-VHDL13_DWEH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:11 2416
ber01-VHDL13_DWEH_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:17 2424
ber01-VHDL13_DWEH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2416
ber01-VHDL13_DWEH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:28:16 2140
ber01-VHDL13_DWEH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:18 2267
ber01-VHDL13_DWEH_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:16 2287
ber01-VHDL13_DWEH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2278
ber01-VHDL13_DWHG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2854
ber01-VHDL13_DWHG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:11 2719
ber01-VHDL13_DWHG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2620
ber01-VHDL13_DWHG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2622
ber01-VHDL13_DWHG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:07 2374
ber01-VHDL13_DWHG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2466
ber01-VHDL13_DWHG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2473
ber01-VHDL13_DWHG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2462
ber01-VHDL13_DWHH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2712
ber01-VHDL13_DWHH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:11 2566
ber01-VHDL13_DWHH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2498
ber01-VHDL13_DWHH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2668
ber01-VHDL13_DWHH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:07 2663
ber01-VHDL13_DWHH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2587
ber01-VHDL13_DWHH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2592
ber01-VHDL13_DWHH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2493
ber01-VHDL13_DWLG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2255
ber01-VHDL13_DWLG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2349
ber01-VHDL13_DWLG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 1962
ber01-VHDL13_DWLG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 1964
ber01-VHDL13_DWLG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2041
ber01-VHDL13_DWLG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2214
ber01-VHDL13_DWLG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2324
ber01-VHDL13_DWLG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2175
ber01-VHDL13_DWLH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2164
ber01-VHDL13_DWLH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2327
ber01-VHDL13_DWLH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2133
ber01-VHDL13_DWLH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2138
ber01-VHDL13_DWLH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2167
ber01-VHDL13_DWLH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2348
ber01-VHDL13_DWLH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2553
ber01-VHDL13_DWLH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2726
ber01-VHDL13_DWLI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2129
ber01-VHDL13_DWLI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2280
ber01-VHDL13_DWLI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2143
ber01-VHDL13_DWLI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2148
ber01-VHDL13_DWLI_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2439
ber01-VHDL13_DWLI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2811
ber01-VHDL13_DWLI_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2661
ber01-VHDL13_DWLI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2495
ber01-VHDL13_DWMG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2647
ber01-VHDL13_DWMG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3240
ber01-VHDL13_DWMG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3280
ber01-VHDL13_DWMG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3088
ber01-VHDL13_DWMG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2895
ber01-VHDL13_DWMG_251800_COR-2602251800-dsw--0-ia5 25-Feb-2026 19:54:16 2976
ber01-VHDL13_DWMG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2929
ber01-VHDL13_DWMG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 2946
ber01-VHDL13_DWMG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2945
ber01-VHDL13_DWMO_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2555
ber01-VHDL13_DWMO_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3118
ber01-VHDL13_DWMO_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3157
ber01-VHDL13_DWMO_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2960
ber01-VHDL13_DWMO_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2594
ber01-VHDL13_DWMO_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 3012
ber01-VHDL13_DWMO_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 2989
ber01-VHDL13_DWMO_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 3077
ber01-VHDL13_DWMP_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2489
ber01-VHDL13_DWMP_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3260
ber01-VHDL13_DWMP_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:03 3302
ber01-VHDL13_DWMP_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3011
ber01-VHDL13_DWMP_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2639
ber01-VHDL13_DWMP_251800_COR-2602251800-dsw--0-ia5 25-Feb-2026 19:54:36 3033
ber01-VHDL13_DWMP_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2996
ber01-VHDL13_DWMP_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 3008
ber01-VHDL13_DWMP_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2874
ber01-VHDL13_DWOG_241700-2602241700-dsw--0-ia5 24-Feb-2026 19:00:02 4031
ber01-VHDL13_DWOG_250300-2602250300-dsw--0-ia5 25-Feb-2026 04:00:02 4420
ber01-VHDL13_DWOG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 4035
ber01-VHDL13_DWOG_251700-2602251700-dsw--0-ia5 25-Feb-2026 19:00:06 3290
ber01-VHDL13_DWOG_260300-2602260300-dsw--0-ia5 26-Feb-2026 04:00:02 3697
ber01-VHDL13_DWOG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:03 3017
ber01-VHDL13_DWOH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:17 2080
ber01-VHDL13_DWOH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:11 2264
ber01-VHDL13_DWOH_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:17 2289
ber01-VHDL13_DWOH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2220
ber01-VHDL13_DWOH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:28:16 2028
ber01-VHDL13_DWOH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:12 2220
ber01-VHDL13_DWOH_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:12 2113
ber01-VHDL13_DWOH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2184
ber01-VHDL13_DWOI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:28:11 2093
ber01-VHDL13_DWOI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:28:16 2340
ber01-VHDL13_DWOI_250400-2602250400-dsw--0-ia5 25-Feb-2026 05:58:11 2371
ber01-VHDL13_DWOI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:28:17 2308
ber01-VHDL13_DWOI_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:28:11 2097
ber01-VHDL13_DWOI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:12 2234
ber01-VHDL13_DWOI_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:16 2160
ber01-VHDL13_DWOI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2268
ber01-VHDL13_DWON_241545-2602241545-dsw--0-ia5 24-Feb-2026 15:45:51 3119
ber01-VHDL13_DWON_241659-2602241659-dsw--0-ia5 24-Feb-2026 16:59:21 3284
ber01-VHDL13_DWON_241817-2602241817-dsw--0-ia5 24-Feb-2026 18:17:16 3197
ber01-VHDL13_DWON_250355-2602250355-dsw--0-ia5 25-Feb-2026 03:55:07 4085
ber01-VHDL13_DWON_250554-2602250554-dsw--0-ia5 25-Feb-2026 05:54:57 3761
ber01-VHDL13_DWON_250708-2602250708-dsw--0-ia5 25-Feb-2026 07:08:16 3761
ber01-VHDL13_DWON_250953-2602250953-dsw--0-ia5 25-Feb-2026 09:53:36 3869
ber01-VHDL13_DWON_251229-2602251229-dsw--0-ia5 25-Feb-2026 12:29:07 3700
ber01-VHDL13_DWON_251426-2602251426-dsw--0-ia5 25-Feb-2026 14:26:57 3079
ber01-VHDL13_DWON_251518-2602251518-dsw--0-ia5 25-Feb-2026 15:18:35 3079
ber01-VHDL13_DWON_251746-2602251746-dsw--0-ia5 25-Feb-2026 17:46:27 2916
ber01-VHDL13_DWON_260358-2602260358-dsw--0-ia5 26-Feb-2026 03:58:12 3861
ber01-VHDL13_DWON_260613-2602260613-dsw--0-ia5 26-Feb-2026 06:13:41 3346
ber01-VHDL13_DWON_260649-2602260649-dsw--0-ia5 26-Feb-2026 06:50:02 3346
ber01-VHDL13_DWON_260911-2602260911-dsw--0-ia5 26-Feb-2026 09:11:58 3290
ber01-VHDL13_DWON_260946-2602260946-dsw--0-ia5 26-Feb-2026 09:46:37 3290
ber01-VHDL13_DWPG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 1910
ber01-VHDL13_DWPG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2245
ber01-VHDL13_DWPG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2008
ber01-VHDL13_DWPG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 1973
ber01-VHDL13_DWPG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2132
ber01-VHDL13_DWPG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2213
ber01-VHDL13_DWPG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2298
ber01-VHDL13_DWPG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2192
ber01-VHDL13_DWPH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:04 2033
ber01-VHDL13_DWPH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 2288
ber01-VHDL13_DWPH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:01 2000
ber01-VHDL13_DWPH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 2004
ber01-VHDL13_DWPH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2110
ber01-VHDL13_DWPH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2249
ber01-VHDL13_DWPH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2138
ber01-VHDL13_DWPH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2138
ber01-VHDL13_DWSG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:30:10 2558
ber01-VHDL13_DWSG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:30:05 3075
ber01-VHDL13_DWSG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 3179
ber01-VHDL13_DWSG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:30:11 3060
ber01-VHDL13_DWSG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:30:03 2720
ber01-VHDL13_DWSG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2870
ber01-VHDL13_DWSG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2663
ber01-VHDL13_DWSG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2618
ber01-VHDL17_DWOG_251200-2602251200-dsw--0-ia5 25-Feb-2026 11:41:26 3133
ber01-VHDL17_DWOG_261200-2602261200-dsw--0-ia5 26-Feb-2026 11:51:11 2913
swis2-VHDL20_DWEG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2407
swis2-VHDL20_DWEG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2541
swis2-VHDL20_DWEG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2612
swis2-VHDL20_DWEG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2698
swis2-VHDL20_DWEG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2357
swis2-VHDL20_DWEG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2499
swis2-VHDL20_DWEG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2433
swis2-VHDL20_DWEG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2662
swis2-VHDL20_DWEH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2452
swis2-VHDL20_DWEH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2738
swis2-VHDL20_DWEH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2762
swis2-VHDL20_DWEH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2919
swis2-VHDL20_DWEH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2500
swis2-VHDL20_DWEH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2591
swis2-VHDL20_DWEH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2622
swis2-VHDL20_DWEH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2781
swis2-VHDL20_DWEI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2445
swis2-VHDL20_DWEI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:07 2632
swis2-VHDL20_DWEI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:07 2725
swis2-VHDL20_DWEI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 2833
swis2-VHDL20_DWEI_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2451
swis2-VHDL20_DWEI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2526
swis2-VHDL20_DWEI_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2511
swis2-VHDL20_DWEI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2793
swis2-VHDL20_DWHG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 3037
swis2-VHDL20_DWHG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2905
swis2-VHDL20_DWHG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2803
swis2-VHDL20_DWHG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3159
swis2-VHDL20_DWHG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2557
swis2-VHDL20_DWHG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2652
swis2-VHDL20_DWHG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2656
swis2-VHDL20_DWHG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2996
swis2-VHDL20_DWHH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2898
swis2-VHDL20_DWHH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2752
swis2-VHDL20_DWHH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:07 2684
swis2-VHDL20_DWHH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3211
swis2-VHDL20_DWHH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2849
swis2-VHDL20_DWHH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2773
swis2-VHDL20_DWHH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2778
swis2-VHDL20_DWHH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 3036
swis2-VHDL20_DWLG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2663
swis2-VHDL20_DWLG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2757
swis2-VHDL20_DWLG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2307
swis2-VHDL20_DWLG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2457
swis2-VHDL20_DWLG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2386
swis2-VHDL20_DWLG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2559
swis2-VHDL20_DWLG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2668
swis2-VHDL20_DWLG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2665
swis2-VHDL20_DWLH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2513
swis2-VHDL20_DWLH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2676
swis2-VHDL20_DWLH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2485
swis2-VHDL20_DWLH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2640
swis2-VHDL20_DWLH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2519
swis2-VHDL20_DWLH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2700
swis2-VHDL20_DWLH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2902
swis2-VHDL20_DWLH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 3225
swis2-VHDL20_DWLI_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2472
swis2-VHDL20_DWLI_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2623
swis2-VHDL20_DWLI_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2490
swis2-VHDL20_DWLI_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2642
swis2-VHDL20_DWLI_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2786
swis2-VHDL20_DWLI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 3158
swis2-VHDL20_DWLI_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 3007
swis2-VHDL20_DWLI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2986
swis2-VHDL20_DWMG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 3136
swis2-VHDL20_DWMG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3715
swis2-VHDL20_DWMG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3740
swis2-VHDL20_DWMG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3791
swis2-VHDL20_DWMG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 3355
swis2-VHDL20_DWMG_251800_COR-2602251800-dsw--0-ia5 25-Feb-2026 19:54:16 3187
swis2-VHDL20_DWMG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:02 3378
swis2-VHDL20_DWMG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 3400
swis2-VHDL20_DWMG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 3618
swis2-VHDL20_DWMO_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 3028
swis2-VHDL20_DWMO_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3579
swis2-VHDL20_DWMO_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3607
swis2-VHDL20_DWMO_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3642
swis2-VHDL20_DWMO_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 3044
swis2-VHDL20_DWMO_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:02 3484
swis2-VHDL20_DWMO_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 3456
swis2-VHDL20_DWMO_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 3769
swis2-VHDL20_DWMP_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2963
swis2-VHDL20_DWMP_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3725
swis2-VHDL20_DWMP_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3765
swis2-VHDL20_DWMP_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3723
swis2-VHDL20_DWMP_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 3354
swis2-VHDL20_DWMP_251800_COR-2602251800-dsw--0-ia5 25-Feb-2026 19:54:36 3477
swis2-VHDL20_DWMP_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:02 3475
swis2-VHDL20_DWMP_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 3478
swis2-VHDL20_DWMP_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 3569
swis2-VHDL20_DWPG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2373
swis2-VHDL20_DWPG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2575
swis2-VHDL20_DWPG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2337
swis2-VHDL20_DWPG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2435
swis2-VHDL20_DWPG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2594
swis2-VHDL20_DWPG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2545
swis2-VHDL20_DWPG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2624
swis2-VHDL20_DWPG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2651
swis2-VHDL20_DWPH_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:02 2570
swis2-VHDL20_DWPH_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 2691
swis2-VHDL20_DWPH_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:00:11 2331
swis2-VHDL20_DWPH_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:02 2466
swis2-VHDL20_DWPH_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 2572
swis2-VHDL20_DWPH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2580
swis2-VHDL20_DWPH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2466
swis2-VHDL20_DWPH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2597
swis2-VHDL20_DWSG_241300-2602241300-dsw--0-ia5 24-Feb-2026 14:45:17 3423
swis2-VHDL20_DWSG_241800-2602241800-dsw--0-ia5 24-Feb-2026 19:45:06 2914
swis2-VHDL20_DWSG_250200-2602250200-dsw--0-ia5 25-Feb-2026 03:45:02 3481
swis2-VHDL20_DWSG_250400-2602250400-dsw--0-ia5 25-Feb-2026 06:15:02 3535
swis2-VHDL20_DWSG_250800-2602250800-dsw--0-ia5 25-Feb-2026 09:45:06 3563
swis2-VHDL20_DWSG_251300-2602251300-dsw--0-ia5 25-Feb-2026 14:45:06 3445
swis2-VHDL20_DWSG_251800-2602251800-dsw--0-ia5 25-Feb-2026 19:45:02 3078
swis2-VHDL20_DWSG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:02 3241
swis2-VHDL20_DWSG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 3016
swis2-VHDL20_DWSG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 3119
wst04-VHDL20_DWEG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 247344
wst04-VHDL20_DWEG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 248271
wst04-VHDL20_DWEG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:18 247312
wst04-VHDL20_DWEG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:12 223359
wst04-VHDL20_DWEG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:10 245599
wst04-VHDL20_DWEG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:21 247207
wst04-VHDL20_DWEG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:21 246199
wst04-VHDL20_DWEG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:12 246388
wst04-VHDL20_DWEH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 238396
wst04-VHDL20_DWEH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 239617
wst04-VHDL20_DWEH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:18 238739
wst04-VHDL20_DWEH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 240360
wst04-VHDL20_DWEH_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:10 239095
wst04-VHDL20_DWEH_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:21 240139
wst04-VHDL20_DWEH_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:21 239228
wst04-VHDL20_DWEH_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:16 243853
wst04-VHDL20_DWEI_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 355062
wst04-VHDL20_DWEI_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 355707
wst04-VHDL20_DWEI_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 355240
wst04-VHDL20_DWEI_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 353881
wst04-VHDL20_DWEI_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:17 352719
wst04-VHDL20_DWEI_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:21 353373
wst04-VHDL20_DWEI_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:27 352828
wst04-VHDL20_DWEI_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:22 350914
wst04-VHDL20_DWHG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 340079
wst04-VHDL20_DWHG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 340599
wst04-VHDL20_DWHG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:11 340420
wst04-VHDL20_DWHG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 346329
wst04-VHDL20_DWHG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:21 344474
wst04-VHDL20_DWHG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:17 344587
wst04-VHDL20_DWHG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:11 344587
wst04-VHDL20_DWHG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:26 346302
wst04-VHDL20_DWHH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 327816
wst04-VHDL20_DWHH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 328241
wst04-VHDL20_DWHH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:11 328158
wst04-VHDL20_DWHH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:26 311544
wst04-VHDL20_DWHH_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:21 329770
wst04-VHDL20_DWHH_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:17 329723
wst04-VHDL20_DWHH_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:11 329774
wst04-VHDL20_DWHH_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:26 327834
wst04-VHDL20_DWLG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 341591
wst04-VHDL20_DWLG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 342556
wst04-VHDL20_DWLG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 341728
wst04-VHDL20_DWLG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:36 322865
wst04-VHDL20_DWLG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:27 341050
wst04-VHDL20_DWLG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:27 341581
wst04-VHDL20_DWLG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:42 341117
wst04-VHDL20_DWLG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:32 351620
wst04-VHDL20_DWLH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 334034
wst04-VHDL20_DWLH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 335459
wst04-VHDL20_DWLH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 334935
wst04-VHDL20_DWLH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 316872
wst04-VHDL20_DWLH_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:27 341754
wst04-VHDL20_DWLH_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:27 342217
wst04-VHDL20_DWLH_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:42 342022
wst04-VHDL20_DWLH_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:36 344233
wst04-VHDL20_DWLI_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 342180
wst04-VHDL20_DWLI_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 343426
wst04-VHDL20_DWLI_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:41 343097
wst04-VHDL20_DWLI_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 322286
wst04-VHDL20_DWLI_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:21 340192
wst04-VHDL20_DWLI_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:27 340947
wst04-VHDL20_DWLI_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:42 340502
wst04-VHDL20_DWLI_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:32 346731
wst04-VHDL20_DWMG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 580687
wst04-VHDL20_DWMG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 580771
wst04-VHDL20_DWMG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:26 580663
wst04-VHDL20_DWMG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 432359
wst04-VHDL20_DWMG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:17 566956
wst04-VHDL20_DWMG_251800_COR-2602251800-omedes-..> 25-Feb-2026 19:54:22 565834
wst04-VHDL20_DWMG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:13 567216
wst04-VHDL20_DWMG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:23 567112
wst04-VHDL20_DWMG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:26 578744
wst04-VHDL20_DWMO_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:17 474108
wst04-VHDL20_DWMO_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:11 474238
wst04-VHDL20_DWMO_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 474761
wst04-VHDL20_DWMO_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:16 432230
wst04-VHDL20_DWMO_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:17 460020
wst04-VHDL20_DWMO_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:13 460767
wst04-VHDL20_DWMO_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:17 461233
wst04-VHDL20_DWMO_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:22 473061
wst04-VHDL20_DWMP_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 581018
wst04-VHDL20_DWMP_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:11 580416
wst04-VHDL20_DWMP_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:26 581540
wst04-VHDL20_DWMP_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:22 511786
wst04-VHDL20_DWMP_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:17 563195
wst04-VHDL20_DWMP_251800_COR-2602251800-omedes-..> 25-Feb-2026 19:54:42 563246
wst04-VHDL20_DWMP_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:17 562387
wst04-VHDL20_DWMP_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:23 563411
wst04-VHDL20_DWMP_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:26 573006
wst04-VHDL20_DWPG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:25 350293
wst04-VHDL20_DWPG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:26 350580
wst04-VHDL20_DWPG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:31 349995
wst04-VHDL20_DWPG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 351206
wst04-VHDL20_DWPG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:27 354278
wst04-VHDL20_DWPG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:27 354187
wst04-VHDL20_DWPG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:31 354004
wst04-VHDL20_DWPG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:36 402131
wst04-VHDL20_DWPH_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:21 286027
wst04-VHDL20_DWPH_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:22 241500
wst04-VHDL20_DWPH_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:00:31 241286
wst04-VHDL20_DWPH_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:32 268253
wst04-VHDL20_DWPH_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:21 286131
wst04-VHDL20_DWPH_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:21 241885
wst04-VHDL20_DWPH_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:00:31 241228
wst04-VHDL20_DWPH_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:32 288358
wst04-VHDL20_DWSG_241300-2602241300-omedes--0.pdf 24-Feb-2026 14:45:17 342466
wst04-VHDL20_DWSG_241800-2602241800-omedes--0.pdf 24-Feb-2026 19:45:12 360413
wst04-VHDL20_DWSG_250200-2602250200-omedes--0.pdf 25-Feb-2026 03:45:17 360993
wst04-VHDL20_DWSG_250400-2602250400-omedes--0.pdf 25-Feb-2026 06:15:22 361305
wst04-VHDL20_DWSG_250800-2602250800-omedes--0.pdf 25-Feb-2026 09:45:12 337662
wst04-VHDL20_DWSG_251300-2602251300-omedes--0.pdf 25-Feb-2026 14:45:18 353520
wst04-VHDL20_DWSG_251800-2602251800-omedes--0.pdf 25-Feb-2026 19:45:12 352477
wst04-VHDL20_DWSG_260200-2602260200-omedes--0.pdf 26-Feb-2026 03:45:17 353160
wst04-VHDL20_DWSG_260400-2602260400-omedes--0.pdf 26-Feb-2026 06:15:11 353379
wst04-VHDL20_DWSG_260800-2602260800-omedes--0.pdf 26-Feb-2026 09:45:12 359599