Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_300600 30-Jan-2026 16:05:55 6198
FPDL13_DWMZ_310600 31-Jan-2026 13:37:51 5440
SXDL31_DWAV_300800 30-Jan-2026 09:14:24 13765
SXDL31_DWAV_301800 30-Jan-2026 18:19:33 7133
SXDL31_DWAV_310800 31-Jan-2026 08:36:30 10845
SXDL31_DWAV_311800 31-Jan-2026 17:40:59 6595
SXDL31_DWAV_LATEST 31-Jan-2026 17:40:59 6595
SXDL33_DWAV_300000 30-Jan-2026 10:43:28 10467
SXDL33_DWAV_310000 31-Jan-2026 10:44:40 8245
SXDL33_DWAV_LATEST 31-Jan-2026 10:44:40 8245
ber01-FWDL39_DWMS_301230-2601301230-dsw--0-ia5 30-Jan-2026 12:16:21 1437
ber01-FWDL39_DWMS_311230-2601311230-dsw--0-ia5 31-Jan-2026 12:20:37 1333
ber01-VHDL13_DWEH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:11 3468
ber01-VHDL13_DWEH_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:12 3436
ber01-VHDL13_DWEH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:17 3412
ber01-VHDL13_DWEH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:17 3148
ber01-VHDL13_DWEH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 3059
ber01-VHDL13_DWEH_310400-2601310400-dsw--0-ia5 31-Jan-2026 05:58:16 3124
ber01-VHDL13_DWEH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:28:16 3372
ber01-VHDL13_DWEH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:13 3011
ber01-VHDL13_DWHG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3585
ber01-VHDL13_DWHG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:08 3709
ber01-VHDL13_DWHG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3876
ber01-VHDL13_DWHG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:07 3698
ber01-VHDL13_DWHG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 4089
ber01-VHDL13_DWHG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:06 4575
ber01-VHDL13_DWHG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 4550
ber01-VHDL13_DWHG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3776
ber01-VHDL13_DWHH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3859
ber01-VHDL13_DWHH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3858
ber01-VHDL13_DWHH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3895
ber01-VHDL13_DWHH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:07 3252
ber01-VHDL13_DWHH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3737
ber01-VHDL13_DWHH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:06 3737
ber01-VHDL13_DWHH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 3887
ber01-VHDL13_DWHH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3358
ber01-VHDL13_DWLG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 1982
ber01-VHDL13_DWLG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1984
ber01-VHDL13_DWLG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2254
ber01-VHDL13_DWLG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2643
ber01-VHDL13_DWLG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2741
ber01-VHDL13_DWLG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 1872
ber01-VHDL13_DWLG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 1866
ber01-VHDL13_DWLG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1670
ber01-VHDL13_DWLH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 1928
ber01-VHDL13_DWLH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1943
ber01-VHDL13_DWLH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2017
ber01-VHDL13_DWLH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2275
ber01-VHDL13_DWLH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2365
ber01-VHDL13_DWLH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 1732
ber01-VHDL13_DWLH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 1729
ber01-VHDL13_DWLH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1674
ber01-VHDL13_DWLI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:00 1838
ber01-VHDL13_DWLI_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1866
ber01-VHDL13_DWLI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 1936
ber01-VHDL13_DWLI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2307
ber01-VHDL13_DWLI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2389
ber01-VHDL13_DWLI_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 1719
ber01-VHDL13_DWLI_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 1805
ber01-VHDL13_DWLI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1675
ber01-VHDL13_DWMG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3506
ber01-VHDL13_DWMG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3413
ber01-VHDL13_DWMG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3358
ber01-VHDL13_DWMG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3289
ber01-VHDL13_DWMG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3204
ber01-VHDL13_DWMG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 3188
ber01-VHDL13_DWMG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 3576
ber01-VHDL13_DWMG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3295
ber01-VHDL13_DWMO_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3247
ber01-VHDL13_DWMO_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3173
ber01-VHDL13_DWMO_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3074
ber01-VHDL13_DWMO_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3160
ber01-VHDL13_DWMO_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3111
ber01-VHDL13_DWMO_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 3091
ber01-VHDL13_DWMO_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 3335
ber01-VHDL13_DWMO_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3007
ber01-VHDL13_DWMP_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3271
ber01-VHDL13_DWMP_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3267
ber01-VHDL13_DWMP_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3455
ber01-VHDL13_DWMP_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3162
ber01-VHDL13_DWMP_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3315
ber01-VHDL13_DWMP_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 3294
ber01-VHDL13_DWMP_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 3689
ber01-VHDL13_DWMP_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:10 3425
ber01-VHDL13_DWOG_300300-2601300300-dsw--0-ia5 30-Jan-2026 04:00:05 5457
ber01-VHDL13_DWOG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 5542
ber01-VHDL13_DWOG_301700-2601301700-dsw--0-ia5 30-Jan-2026 19:00:01 4748
ber01-VHDL13_DWOG_310300-2601310300-dsw--0-ia5 31-Jan-2026 04:00:01 5605
ber01-VHDL13_DWOG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:03 5623
ber01-VHDL13_DWOG_311700-2601311700-dsw--0-ia5 31-Jan-2026 19:00:01 5120
ber01-VHDL13_DWOH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:11 3709
ber01-VHDL13_DWOH_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:12 3778
ber01-VHDL13_DWOH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:17 3675
ber01-VHDL13_DWOH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:17 3369
ber01-VHDL13_DWOH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 3220
ber01-VHDL13_DWOH_310400-2601310400-dsw--0-ia5 31-Jan-2026 05:58:12 3421
ber01-VHDL13_DWOH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:28:12 3512
ber01-VHDL13_DWOH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:17 3120
ber01-VHDL13_DWOI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:15 3306
ber01-VHDL13_DWOI_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:18 3405
ber01-VHDL13_DWOI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:11 3225
ber01-VHDL13_DWOI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:11 2868
ber01-VHDL13_DWOI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 2652
ber01-VHDL13_DWOI_310400-2601310400-dsw--0-ia5 31-Jan-2026 05:58:16 2615
ber01-VHDL13_DWOI_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:28:12 2852
ber01-VHDL13_DWOI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:28:13 2710
ber01-VHDL13_DWON_292233-2601292233-dsw--0-ia5 29-Jan-2026 22:33:52 3613
ber01-VHDL13_DWON_292342-2601292342-dsw--0-ia5 29-Jan-2026 23:42:52 4195
ber01-VHDL13_DWON_292352-2601292352-dsw--0-ia5 29-Jan-2026 23:53:02 4195
ber01-VHDL13_DWON_292353-2601292353-dsw--0-ia5 29-Jan-2026 23:53:22 4195
ber01-VHDL13_DWON_300629-2601300629-dsw--0-ia5 30-Jan-2026 06:29:22 5077
ber01-VHDL13_DWON_300723-2601300723-dsw--0-ia5 30-Jan-2026 07:24:01 5127
ber01-VHDL13_DWON_301544-2601301544-dsw--0-ia5 30-Jan-2026 15:44:27 4595
ber01-VHDL13_DWON_301844-2601301844-dsw--0-ia5 30-Jan-2026 18:44:16 4033
ber01-VHDL13_DWON_302256-2601302256-dsw--0-ia5 30-Jan-2026 22:56:31 4097
ber01-VHDL13_DWON_310152-2601310152-dsw--0-ia5 31-Jan-2026 01:52:57 4431
ber01-VHDL13_DWON_310422-2601310422-dsw--0-ia5 31-Jan-2026 04:22:47 4431
ber01-VHDL13_DWON_310630-2601310630-dsw--0-ia5 31-Jan-2026 06:30:11 4298
ber01-VHDL13_DWON_310644-2601310644-dsw--0-ia5 31-Jan-2026 06:44:45 4293
ber01-VHDL13_DWON_310912-2601310912-dsw--0-ia5 31-Jan-2026 09:12:06 4289
ber01-VHDL13_DWON_311529-2601311529-dsw--0-ia5 31-Jan-2026 15:29:41 3869
ber01-VHDL13_DWON_311840-2601311840-dsw--0-ia5 31-Jan-2026 18:40:06 4281
ber01-VHDL13_DWON_311946-2601311946-dsw--0-ia5 31-Jan-2026 19:46:32 4281
ber01-VHDL13_DWPG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 2078
ber01-VHDL13_DWPG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 2212
ber01-VHDL13_DWPG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2372
ber01-VHDL13_DWPG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2113
ber01-VHDL13_DWPG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2522
ber01-VHDL13_DWPG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 1869
ber01-VHDL13_DWPG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 1868
ber01-VHDL13_DWPG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 1792
ber01-VHDL13_DWPH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 2547
ber01-VHDL13_DWPH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 2687
ber01-VHDL13_DWPH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2770
ber01-VHDL13_DWPH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2642
ber01-VHDL13_DWPH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3079
ber01-VHDL13_DWPH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:02 2554
ber01-VHDL13_DWPH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 2793
ber01-VHDL13_DWPH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 2293
ber01-VHDL13_DWSG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3929
ber01-VHDL13_DWSG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3939
ber01-VHDL13_DWSG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 3704
ber01-VHDL13_DWSG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3223
ber01-VHDL13_DWSG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3358
ber01-VHDL13_DWSG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:06 3361
ber01-VHDL13_DWSG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:30:05 3334
ber01-VHDL13_DWSG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:30:02 3038
ber01-VHDL17_DWOG_301200-2601301200-dsw--0-ia5 30-Jan-2026 12:29:26 3593
ber01-VHDL17_DWOG_311200-2601311200-dsw--0-ia5 31-Jan-2026 12:20:21 2693
swis2-VHDL20_DWEG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4199
swis2-VHDL20_DWEG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 4156
swis2-VHDL20_DWEG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4290
swis2-VHDL20_DWEG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3793
swis2-VHDL20_DWEG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3533
swis2-VHDL20_DWEG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3869
swis2-VHDL20_DWEG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4154
swis2-VHDL20_DWEG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3574
swis2-VHDL20_DWEH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4015
swis2-VHDL20_DWEH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3826
swis2-VHDL20_DWEH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4039
swis2-VHDL20_DWEH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3585
swis2-VHDL20_DWEH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3412
swis2-VHDL20_DWEH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3546
swis2-VHDL20_DWEH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4085
swis2-VHDL20_DWEH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3455
swis2-VHDL20_DWEI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3811
swis2-VHDL20_DWEI_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3814
swis2-VHDL20_DWEI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3931
swis2-VHDL20_DWEI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3302
swis2-VHDL20_DWEI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2985
swis2-VHDL20_DWEI_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3070
swis2-VHDL20_DWEI_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 3551
swis2-VHDL20_DWEI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3165
swis2-VHDL20_DWHG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3771
swis2-VHDL20_DWHG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3892
swis2-VHDL20_DWHG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4842
swis2-VHDL20_DWHG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3881
swis2-VHDL20_DWHG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:06 4275
swis2-VHDL20_DWHG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:06 4758
swis2-VHDL20_DWHG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 5336
swis2-VHDL20_DWHG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:06 3959
swis2-VHDL20_DWHH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4045
swis2-VHDL20_DWHH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 4044
swis2-VHDL20_DWHH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4691
swis2-VHDL20_DWHH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3438
swis2-VHDL20_DWHH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:06 3923
swis2-VHDL20_DWHH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:06 3923
swis2-VHDL20_DWHH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4613
swis2-VHDL20_DWHH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:06 3544
swis2-VHDL20_DWLG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2384
swis2-VHDL20_DWLG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2371
swis2-VHDL20_DWLG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2848
swis2-VHDL20_DWLG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3061
swis2-VHDL20_DWLG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3159
swis2-VHDL20_DWLG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:12 2300
swis2-VHDL20_DWLG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 2514
swis2-VHDL20_DWLG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2076
swis2-VHDL20_DWLH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2338
swis2-VHDL20_DWLH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2337
swis2-VHDL20_DWLH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2606
swis2-VHDL20_DWLH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 2700
swis2-VHDL20_DWLH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2790
swis2-VHDL20_DWLH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:12 2152
swis2-VHDL20_DWLH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 2370
swis2-VHDL20_DWLH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2085
swis2-VHDL20_DWLI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2241
swis2-VHDL20_DWLI_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2255
swis2-VHDL20_DWLI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2515
swis2-VHDL20_DWLI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 2727
swis2-VHDL20_DWLI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2809
swis2-VHDL20_DWLI_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:12 2133
swis2-VHDL20_DWLI_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 2437
swis2-VHDL20_DWLI_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2085
swis2-VHDL20_DWMG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 3927
swis2-VHDL20_DWMG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3862
swis2-VHDL20_DWMG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4040
swis2-VHDL20_DWMG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3872
swis2-VHDL20_DWMG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3721
swis2-VHDL20_DWMG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3705
swis2-VHDL20_DWMG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4443
swis2-VHDL20_DWMG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3958
swis2-VHDL20_DWMO_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 3671
swis2-VHDL20_DWMO_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3626
swis2-VHDL20_DWMO_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3764
swis2-VHDL20_DWMO_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3631
swis2-VHDL20_DWMO_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3632
swis2-VHDL20_DWMO_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3612
swis2-VHDL20_DWMO_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4166
swis2-VHDL20_DWMO_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3630
swis2-VHDL20_DWMP_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 3694
swis2-VHDL20_DWMP_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3716
swis2-VHDL20_DWMP_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4145
swis2-VHDL20_DWMP_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3747
swis2-VHDL20_DWMP_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3835
swis2-VHDL20_DWMP_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3811
swis2-VHDL20_DWMP_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4524
swis2-VHDL20_DWMP_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 4038
swis2-VHDL20_DWPG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2614
swis2-VHDL20_DWPG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2626
swis2-VHDL20_DWPG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2961
swis2-VHDL20_DWPG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 2702
swis2-VHDL20_DWPG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2941
swis2-VHDL20_DWPG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:12 2241
swis2-VHDL20_DWPG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 2458
swis2-VHDL20_DWPG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2305
swis2-VHDL20_DWPH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3038
swis2-VHDL20_DWPH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 3134
swis2-VHDL20_DWPH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3392
swis2-VHDL20_DWPH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3263
swis2-VHDL20_DWPH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3528
swis2-VHDL20_DWPH_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:00:12 2928
swis2-VHDL20_DWPH_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 3346
swis2-VHDL20_DWPH_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 2809
swis2-VHDL20_DWSG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 4326
swis2-VHDL20_DWSG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 4373
swis2-VHDL20_DWSG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:01 4361
swis2-VHDL20_DWSG_301300-2601301300-dsw--0-ia5 30-Jan-2026 14:45:07 4172
swis2-VHDL20_DWSG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3696
swis2-VHDL20_DWSG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3755
swis2-VHDL20_DWSG_310400-2601310400-dsw--0-ia5 31-Jan-2026 06:15:01 3856
swis2-VHDL20_DWSG_310800-2601310800-dsw--0-ia5 31-Jan-2026 09:45:02 4074
swis2-VHDL20_DWSG_311300-2601311300-dsw--0-ia5 31-Jan-2026 14:45:01 3848
swis2-VHDL20_DWSG_311800-2601311800-dsw--0-ia5 31-Jan-2026 19:45:02 3530
wst04-VHDL20_DWEG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 231589
wst04-VHDL20_DWEG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:17 230572
wst04-VHDL20_DWEG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:11 231278
wst04-VHDL20_DWEG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 230000
wst04-VHDL20_DWEG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 230142
wst04-VHDL20_DWEG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:17 229959
wst04-VHDL20_DWEG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:12 229720
wst04-VHDL20_DWEG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 228596
wst04-VHDL20_DWEH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 233155
wst04-VHDL20_DWEH_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:13 231966
wst04-VHDL20_DWEH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:11 229447
wst04-VHDL20_DWEH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 228769
wst04-VHDL20_DWEH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 229738
wst04-VHDL20_DWEH_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:17 229097
wst04-VHDL20_DWEH_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:12 228028
wst04-VHDL20_DWEH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 226351
wst04-VHDL20_DWEI_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 326731
wst04-VHDL20_DWEI_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:21 326445
wst04-VHDL20_DWEI_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 321175
wst04-VHDL20_DWEI_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 320248
wst04-VHDL20_DWEI_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 320109
wst04-VHDL20_DWEI_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:11 319884
wst04-VHDL20_DWEI_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:18 325710
wst04-VHDL20_DWEI_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 324683
wst04-VHDL20_DWHG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 295555
wst04-VHDL20_DWHG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:12 296460
wst04-VHDL20_DWHG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 298906
wst04-VHDL20_DWHG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 296227
wst04-VHDL20_DWHG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 297880
wst04-VHDL20_DWHG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:12 297821
wst04-VHDL20_DWHG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:16 308779
wst04-VHDL20_DWHG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 306550
wst04-VHDL20_DWHH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 296915
wst04-VHDL20_DWHH_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:12 296947
wst04-VHDL20_DWHH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 300376
wst04-VHDL20_DWHH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 298411
wst04-VHDL20_DWHH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 298885
wst04-VHDL20_DWHH_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:16 298976
wst04-VHDL20_DWHH_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:16 295984
wst04-VHDL20_DWHH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 294050
wst04-VHDL20_DWLG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 296505
wst04-VHDL20_DWLG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:42 296464
wst04-VHDL20_DWLG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 292960
wst04-VHDL20_DWLG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 293034
wst04-VHDL20_DWLG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 292826
wst04-VHDL20_DWLG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:42 292743
wst04-VHDL20_DWLG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:26 298515
wst04-VHDL20_DWLG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 297851
wst04-VHDL20_DWLH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 289636
wst04-VHDL20_DWLH_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:42 289600
wst04-VHDL20_DWLH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 291111
wst04-VHDL20_DWLH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 291035
wst04-VHDL20_DWLH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 290914
wst04-VHDL20_DWLH_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:42 290621
wst04-VHDL20_DWLH_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:26 302928
wst04-VHDL20_DWLH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 302752
wst04-VHDL20_DWLI_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 294772
wst04-VHDL20_DWLI_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:42 294784
wst04-VHDL20_DWLI_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 297991
wst04-VHDL20_DWLI_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 298062
wst04-VHDL20_DWLI_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 297951
wst04-VHDL20_DWLI_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:42 297881
wst04-VHDL20_DWLI_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:22 303544
wst04-VHDL20_DWLI_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 303276
wst04-VHDL20_DWMG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 521699
wst04-VHDL20_DWMG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:23 521580
wst04-VHDL20_DWMG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 518998
wst04-VHDL20_DWMG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 519143
wst04-VHDL20_DWMG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 518768
wst04-VHDL20_DWMG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:17 518595
wst04-VHDL20_DWMG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:22 520206
wst04-VHDL20_DWMG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 519198
wst04-VHDL20_DWMO_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 413620
wst04-VHDL20_DWMO_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:17 414060
wst04-VHDL20_DWMO_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 412895
wst04-VHDL20_DWMO_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 412397
wst04-VHDL20_DWMO_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 412555
wst04-VHDL20_DWMO_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:17 413060
wst04-VHDL20_DWMO_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:16 406912
wst04-VHDL20_DWMO_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 405997
wst04-VHDL20_DWMP_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 556736
wst04-VHDL20_DWMP_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:17 557875
wst04-VHDL20_DWMP_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 553312
wst04-VHDL20_DWMP_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 552371
wst04-VHDL20_DWMP_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 550392
wst04-VHDL20_DWMP_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:21 551664
wst04-VHDL20_DWMP_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:22 560445
wst04-VHDL20_DWMP_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:16 558992
wst04-VHDL20_DWPG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:27 300711
wst04-VHDL20_DWPG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:32 300334
wst04-VHDL20_DWPG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 349120
wst04-VHDL20_DWPG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:26 304321
wst04-VHDL20_DWPG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:27 304360
wst04-VHDL20_DWPG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:30 303922
wst04-VHDL20_DWPG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:26 352231
wst04-VHDL20_DWPG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:26 306958
wst04-VHDL20_DWPH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 218852
wst04-VHDL20_DWPH_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:32 218762
wst04-VHDL20_DWPH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 267292
wst04-VHDL20_DWPH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 266477
wst04-VHDL20_DWPH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 222316
wst04-VHDL20_DWPH_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:00:30 221714
wst04-VHDL20_DWPH_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:22 265937
wst04-VHDL20_DWPH_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:20 264450
wst04-VHDL20_DWSG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 342846
wst04-VHDL20_DWSG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:11 342946
wst04-VHDL20_DWSG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:11 341164
wst04-VHDL20_DWSG_301300-2601301300-omedes--0.pdf 30-Jan-2026 14:45:11 341137
wst04-VHDL20_DWSG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 340655
wst04-VHDL20_DWSG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:15 340180
wst04-VHDL20_DWSG_310400-2601310400-omedes--0.pdf 31-Jan-2026 06:15:11 340039
wst04-VHDL20_DWSG_310800-2601310800-omedes--0.pdf 31-Jan-2026 09:45:12 336340
wst04-VHDL20_DWSG_311300-2601311300-omedes--0.pdf 31-Jan-2026 14:45:12 336567
wst04-VHDL20_DWSG_311800-2601311800-omedes--0.pdf 31-Jan-2026 19:45:12 336513