Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Feb-2026 15:06:08 3911
SXDL31_DWAV_161800 16-Feb-2026 17:41:59 12456
SXDL31_DWAV_170800 17-Feb-2026 08:41:30 9799
SXDL31_DWAV_171800 17-Feb-2026 17:20:18 13308
SXDL31_DWAV_180800 18-Feb-2026 10:18:29 13723
SXDL31_DWAV_LATEST 18-Feb-2026 10:18:29 13723
SXDL33_DWAV_170000 17-Feb-2026 11:33:24 10627
SXDL33_DWAV_180000 18-Feb-2026 11:06:39 9949
SXDL33_DWAV_LATEST 18-Feb-2026 11:06:39 9949
ber01-FWDL39_DWMS_171230-2602171230-dsw--0-ia5 17-Feb-2026 13:38:24 2312
ber01-FWDL39_DWMS_181230-2602181230-dsw--0-ia5 18-Feb-2026 12:45:11 2123
ber01-VHDL13_DWEH_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:47 3906
ber01-VHDL13_DWEH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:28:17 3334
ber01-VHDL13_DWEH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:28:12 3463
ber01-VHDL13_DWEH_170400-2602170400-dsw--0-ia5 17-Feb-2026 05:58:16 3365
ber01-VHDL13_DWEH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:28:16 3346
ber01-VHDL13_DWEH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:28:18 3618
ber01-VHDL13_DWEH_171800_COR-2602171800-dsw--0-ia5 17-Feb-2026 21:55:42 3829
ber01-VHDL13_DWEH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:28:13 3792
ber01-VHDL13_DWEH_180400-2602180400-dsw--0-ia5 18-Feb-2026 05:58:16 3544
ber01-VHDL13_DWEH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:28:16 3248
ber01-VHDL13_DWHG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:05 3502
ber01-VHDL13_DWHG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:06 3734
ber01-VHDL13_DWHG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3735
ber01-VHDL13_DWHG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 3394
ber01-VHDL13_DWHG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 3308
ber01-VHDL13_DWHG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:08 2833
ber01-VHDL13_DWHG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 3029
ber01-VHDL13_DWHG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:06 3698
ber01-VHDL13_DWHH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:05 3205
ber01-VHDL13_DWHH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:06 3414
ber01-VHDL13_DWHH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3415
ber01-VHDL13_DWHH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 3023
ber01-VHDL13_DWHH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 2841
ber01-VHDL13_DWHH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:08 2644
ber01-VHDL13_DWHH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 2633
ber01-VHDL13_DWHH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:06 3394
ber01-VHDL13_DWLG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:01 3042
ber01-VHDL13_DWLG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3343
ber01-VHDL13_DWLG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:02 2974
ber01-VHDL13_DWLG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 2957
ber01-VHDL13_DWLG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:04 3609
ber01-VHDL13_DWLG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 3696
ber01-VHDL13_DWLG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:01 3516
ber01-VHDL13_DWLG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3350
ber01-VHDL13_DWLH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:01 2688
ber01-VHDL13_DWLH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3008
ber01-VHDL13_DWLH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:02 2848
ber01-VHDL13_DWLH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 2997
ber01-VHDL13_DWLH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:04 3704
ber01-VHDL13_DWLH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 3795
ber01-VHDL13_DWLH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:06 3363
ber01-VHDL13_DWLH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3227
ber01-VHDL13_DWLI_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:01 2695
ber01-VHDL13_DWLI_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 2970
ber01-VHDL13_DWLI_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:02 2713
ber01-VHDL13_DWLI_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 2890
ber01-VHDL13_DWLI_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:04 3500
ber01-VHDL13_DWLI_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 3584
ber01-VHDL13_DWLI_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:01 3279
ber01-VHDL13_DWLI_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3315
ber01-VHDL13_DWMG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:05 4093
ber01-VHDL13_DWMG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3931
ber01-VHDL13_DWMG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3928
ber01-VHDL13_DWMG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 4332
ber01-VHDL13_DWMG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 3777
ber01-VHDL13_DWMG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:06 3575
ber01-VHDL13_DWMG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 3786
ber01-VHDL13_DWMG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3810
ber01-VHDL13_DWMO_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:05 3506
ber01-VHDL13_DWMO_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3700
ber01-VHDL13_DWMO_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3695
ber01-VHDL13_DWMO_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 3413
ber01-VHDL13_DWMO_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 2986
ber01-VHDL13_DWMO_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:06 3222
ber01-VHDL13_DWMO_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 3681
ber01-VHDL13_DWMO_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3584
ber01-VHDL13_DWMP_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:05 4190
ber01-VHDL13_DWMP_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 4047
ber01-VHDL13_DWMP_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 4044
ber01-VHDL13_DWMP_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 3787
ber01-VHDL13_DWMP_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 3090
ber01-VHDL13_DWMP_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:06 3301
ber01-VHDL13_DWMP_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 3111
ber01-VHDL13_DWMP_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3173
ber01-VHDL13_DWOG_161700-2602161700-dsw--0-ia5 16-Feb-2026 19:00:06 6089
ber01-VHDL13_DWOG_170300-2602170300-dsw--0-ia5 17-Feb-2026 04:00:01 7583
ber01-VHDL13_DWOG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 6247
ber01-VHDL13_DWOG_171700-2602171700-dsw--0-ia5 17-Feb-2026 19:00:06 5797
ber01-VHDL13_DWOG_180300-2602180300-dsw--0-ia5 18-Feb-2026 04:00:01 5965
ber01-VHDL13_DWOG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 6059
ber01-VHDL13_DWOH_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:47 3651
ber01-VHDL13_DWOH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:28:17 3125
ber01-VHDL13_DWOH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:28:12 3223
ber01-VHDL13_DWOH_170400-2602170400-dsw--0-ia5 17-Feb-2026 05:58:16 3142
ber01-VHDL13_DWOH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:28:16 3081
ber01-VHDL13_DWOH_171800-2602171800-dsw--0-ia5 17-Feb-2026 21:56:17 3550
ber01-VHDL13_DWOH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:28:13 3650
ber01-VHDL13_DWOH_180400-2602180400-dsw--0-ia5 18-Feb-2026 05:58:12 3369
ber01-VHDL13_DWOH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:28:16 3146
ber01-VHDL13_DWOI_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:47 3526
ber01-VHDL13_DWOI_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:28:12 3365
ber01-VHDL13_DWOI_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:28:16 3199
ber01-VHDL13_DWOI_170400-2602170400-dsw--0-ia5 17-Feb-2026 05:58:11 3115
ber01-VHDL13_DWOI_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:28:12 3235
ber01-VHDL13_DWOI_171800-2602171800-dsw--0-ia5 17-Feb-2026 21:56:51 3194
ber01-VHDL13_DWOI_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:28:17 3453
ber01-VHDL13_DWOI_180400-2602180400-dsw--0-ia5 18-Feb-2026 05:58:16 3399
ber01-VHDL13_DWOI_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:28:16 3299
ber01-VHDL13_DWON_161538-2602161538-dsw--0-ia5 16-Feb-2026 15:38:57 4357
ber01-VHDL13_DWON_161728-2602161728-dsw--0-ia5 16-Feb-2026 17:28:46 4455
ber01-VHDL13_DWON_161742-2602161742-dsw--0-ia5 16-Feb-2026 17:42:07 4455
ber01-VHDL13_DWON_162136-2602162136-dsw--0-ia5 16-Feb-2026 21:36:41 4473
ber01-VHDL13_DWON_170017-2602170017-dsw--0-ia5 17-Feb-2026 00:17:17 4366
ber01-VHDL13_DWON_170135-2602170135-dsw--0-ia5 17-Feb-2026 01:35:46 4366
ber01-VHDL13_DWON_170350-2602170350-dsw--0-ia5 17-Feb-2026 03:50:17 4378
ber01-VHDL13_DWON_170628-2602170628-dsw--0-ia5 17-Feb-2026 06:28:22 4183
ber01-VHDL13_DWON_170656-2602170656-dsw--0-ia5 17-Feb-2026 06:56:56 4343
ber01-VHDL13_DWON_171527-2602171527-dsw--0-ia5 17-Feb-2026 15:27:47 4564
ber01-VHDL13_DWON_171753-2602171753-dsw--0-ia5 17-Feb-2026 17:53:21 4211
ber01-VHDL13_DWON_172036-2602172036-dsw--0-ia5 17-Feb-2026 20:36:31 4221
ber01-VHDL13_DWON_180219-2602180219-dsw--0-ia5 18-Feb-2026 02:19:42 4857
ber01-VHDL13_DWON_180346-2602180346-dsw--0-ia5 18-Feb-2026 03:46:56 4511
ber01-VHDL13_DWON_180356-2602180356-dsw--0-ia5 18-Feb-2026 03:56:12 4511
ber01-VHDL13_DWON_180630-2602180630-dsw--0-ia5 18-Feb-2026 06:30:06 4548
ber01-VHDL13_DWON_180730-2602180730-dsw--0-ia5 18-Feb-2026 07:30:08 4621
ber01-VHDL13_DWON_180912-2602180912-dsw--0-ia5 18-Feb-2026 09:12:46 4621
ber01-VHDL13_DWON_181221-2602181221-dsw--0-ia5 18-Feb-2026 12:21:26 4540
ber01-VHDL13_DWPG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:01 2503
ber01-VHDL13_DWPG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3100
ber01-VHDL13_DWPG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:02 2398
ber01-VHDL13_DWPG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 2494
ber01-VHDL13_DWPG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:04 2245
ber01-VHDL13_DWPG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 2768
ber01-VHDL13_DWPG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:01 2728
ber01-VHDL13_DWPG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 2616
ber01-VHDL13_DWPH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:01 2176
ber01-VHDL13_DWPH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 2570
ber01-VHDL13_DWPH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:02 2204
ber01-VHDL13_DWPH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 2378
ber01-VHDL13_DWPH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:04 2077
ber01-VHDL13_DWPH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 2703
ber01-VHDL13_DWPH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:01 2770
ber01-VHDL13_DWPH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 2634
ber01-VHDL13_DWSG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:30:10 3868
ber01-VHDL13_DWSG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:30:04 3619
ber01-VHDL13_DWSG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3835
ber01-VHDL13_DWSG_170400_COR-2602170400-dsw--0-ia5 17-Feb-2026 06:20:40 3956
ber01-VHDL13_DWSG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:30:07 4038
ber01-VHDL13_DWSG_170800_COR-2602170800-dsw--0-ia5 17-Feb-2026 09:38:18 4041
ber01-VHDL13_DWSG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:30:10 3303
ber01-VHDL13_DWSG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:30:04 3849
ber01-VHDL13_DWSG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:06 3671
ber01-VHDL13_DWSG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:30:01 3603
ber01-VHDL17_DWOG_171200-2602171200-dsw--0-ia5 17-Feb-2026 12:55:11 3173
ber01-VHDL17_DWOG_181200-2602181200-dsw--0-ia5 18-Feb-2026 12:59:31 3584
swis2-VHDL20_DWEG_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:35 4682
swis2-VHDL20_DWEG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3768
swis2-VHDL20_DWEG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3816
swis2-VHDL20_DWEG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:06 3687
swis2-VHDL20_DWEG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 3962
swis2-VHDL20_DWEG_171800-2602171800-dsw--0-ia5 17-Feb-2026 21:59:52 4062
swis2-VHDL20_DWEG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:02 4112
swis2-VHDL20_DWEG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 3950
swis2-VHDL20_DWEG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 3963
swis2-VHDL20_DWEH_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:35 4923
swis2-VHDL20_DWEH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3958
swis2-VHDL20_DWEH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 4053
swis2-VHDL20_DWEH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:06 3927
swis2-VHDL20_DWEH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 4246
swis2-VHDL20_DWEH_171800-2602171800-dsw--0-ia5 17-Feb-2026 22:00:16 4455
swis2-VHDL20_DWEH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:02 4299
swis2-VHDL20_DWEH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 4093
swis2-VHDL20_DWEH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4057
swis2-VHDL20_DWEI_160800_COR-2602160800-dsw--0-ia5 16-Feb-2026 16:08:35 4526
swis2-VHDL20_DWEI_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3958
swis2-VHDL20_DWEI_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3732
swis2-VHDL20_DWEI_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:06 3691
swis2-VHDL20_DWEI_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 4164
swis2-VHDL20_DWEI_171800-2602171800-dsw--0-ia5 17-Feb-2026 22:00:42 3672
swis2-VHDL20_DWEI_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:02 3886
swis2-VHDL20_DWEI_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 4015
swis2-VHDL20_DWEI_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4183
swis2-VHDL20_DWHG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:06 3685
swis2-VHDL20_DWHG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3920
swis2-VHDL20_DWHG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3918
swis2-VHDL20_DWHG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 4060
swis2-VHDL20_DWHG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:07 3491
swis2-VHDL20_DWHG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:02 3019
swis2-VHDL20_DWHG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:06 3212
swis2-VHDL20_DWHG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4367
swis2-VHDL20_DWHH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:06 3391
swis2-VHDL20_DWHH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3600
swis2-VHDL20_DWHH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:07 3601
swis2-VHDL20_DWHH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 3662
swis2-VHDL20_DWHH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:07 3027
swis2-VHDL20_DWHH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:02 2830
swis2-VHDL20_DWHH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:07 2819
swis2-VHDL20_DWHH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4007
swis2-VHDL20_DWLG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3538
swis2-VHDL20_DWLG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3838
swis2-VHDL20_DWLG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:11 3434
swis2-VHDL20_DWLG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 3583
swis2-VHDL20_DWLG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 4062
swis2-VHDL20_DWLG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:48:12 3863
swis2-VHDL20_DWLG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:11 3920
swis2-VHDL20_DWLG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 3910
swis2-VHDL20_DWLH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3157
swis2-VHDL20_DWLH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3497
swis2-VHDL20_DWLH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:11 3316
swis2-VHDL20_DWLH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 3635
swis2-VHDL20_DWLH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 4165
swis2-VHDL20_DWLH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:47:56 3890
swis2-VHDL20_DWLH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:11 3774
swis2-VHDL20_DWLH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 3806
swis2-VHDL20_DWLI_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3135
swis2-VHDL20_DWLI_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3405
swis2-VHDL20_DWLI_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:11 3177
swis2-VHDL20_DWLI_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 3557
swis2-VHDL20_DWLI_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 3960
swis2-VHDL20_DWLI_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:48:27 3805
swis2-VHDL20_DWLI_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:11 3751
swis2-VHDL20_DWLI_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 3956
swis2-VHDL20_DWMG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 4548
swis2-VHDL20_DWMG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 4338
swis2-VHDL20_DWMG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:02 4377
swis2-VHDL20_DWMG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 5113
swis2-VHDL20_DWMG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 4342
swis2-VHDL20_DWMG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:06 3974
swis2-VHDL20_DWMG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 4285
swis2-VHDL20_DWMG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4532
swis2-VHDL20_DWMO_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 4026
swis2-VHDL20_DWMO_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:06 4113
swis2-VHDL20_DWMO_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:02 4150
swis2-VHDL20_DWMO_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 4274
swis2-VHDL20_DWMO_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 3549
swis2-VHDL20_DWMO_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:06 3636
swis2-VHDL20_DWMO_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 4188
swis2-VHDL20_DWMO_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 4405
swis2-VHDL20_DWMP_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 4569
swis2-VHDL20_DWMP_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:06 4457
swis2-VHDL20_DWMP_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:02 4493
swis2-VHDL20_DWMP_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 4575
swis2-VHDL20_DWMP_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 3649
swis2-VHDL20_DWMP_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:06 3408
swis2-VHDL20_DWMP_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:01 3590
swis2-VHDL20_DWMP_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:06 3858
swis2-VHDL20_DWPG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 3315
swis2-VHDL20_DWPG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 3653
swis2-VHDL20_DWPG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:11 2857
swis2-VHDL20_DWPG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 3106
swis2-VHDL20_DWPG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 2809
swis2-VHDL20_DWPG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:50:31 3102
swis2-VHDL20_DWPG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:11 3118
swis2-VHDL20_DWPG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 3173
swis2-VHDL20_DWPH_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 2754
swis2-VHDL20_DWPH_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 2999
swis2-VHDL20_DWPH_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:00:11 2550
swis2-VHDL20_DWPH_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:06 2890
swis2-VHDL20_DWPH_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 2589
swis2-VHDL20_DWPH_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:50:51 3140
swis2-VHDL20_DWPH_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:00:11 3152
swis2-VHDL20_DWPH_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 3185
swis2-VHDL20_DWSG_161300-2602161300-dsw--0-ia5 16-Feb-2026 14:45:15 4508
swis2-VHDL20_DWSG_161800-2602161800-dsw--0-ia5 16-Feb-2026 19:45:02 4290
swis2-VHDL20_DWSG_170200-2602170200-dsw--0-ia5 17-Feb-2026 03:45:02 4019
swis2-VHDL20_DWSG_170400-2602170400-dsw--0-ia5 17-Feb-2026 06:15:02 4268
swis2-VHDL20_DWSG_170400_COR-2602170400-dsw--0-ia5 17-Feb-2026 06:20:40 4388
swis2-VHDL20_DWSG_170800-2602170800-dsw--0-ia5 17-Feb-2026 09:45:01 4718
swis2-VHDL20_DWSG_170800_COR-2602170800-dsw--0-ia5 17-Feb-2026 09:38:18 4271
swis2-VHDL20_DWSG_171300-2602171300-dsw--0-ia5 17-Feb-2026 14:45:06 4507
swis2-VHDL20_DWSG_171800-2602171800-dsw--0-ia5 17-Feb-2026 19:45:03 3742
swis2-VHDL20_DWSG_180200-2602180200-dsw--0-ia5 18-Feb-2026 03:45:06 4293
swis2-VHDL20_DWSG_180400-2602180400-dsw--0-ia5 18-Feb-2026 06:15:06 4124
swis2-VHDL20_DWSG_180800-2602180800-dsw--0-ia5 18-Feb-2026 09:45:02 4254
wst04-VHDL20_DWEG_160800_COR-2602160800-omedes-..> 16-Feb-2026 16:08:51 236820
wst04-VHDL20_DWEG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:12 235423
wst04-VHDL20_DWEG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:12 236115
wst04-VHDL20_DWEG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:16 235733
wst04-VHDL20_DWEG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:12 238262
wst04-VHDL20_DWEG_171800-2602171800-omedes--0.pdf 17-Feb-2026 21:57:37 237901
wst04-VHDL20_DWEG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:22 238805
wst04-VHDL20_DWEG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:18 237494
wst04-VHDL20_DWEG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:16 237875
wst04-VHDL20_DWEH_160800_COR-2602160800-omedes-..> 16-Feb-2026 16:08:51 232105
wst04-VHDL20_DWEH_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:12 230787
wst04-VHDL20_DWEH_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:12 231353
wst04-VHDL20_DWEH_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:16 230912
wst04-VHDL20_DWEH_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:12 232358
wst04-VHDL20_DWEH_171800-2602171800-omedes--0.pdf 17-Feb-2026 21:58:06 232377
wst04-VHDL20_DWEH_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:22 233131
wst04-VHDL20_DWEH_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:18 231858
wst04-VHDL20_DWEH_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:12 234393
wst04-VHDL20_DWEI_160800_COR-2602160800-omedes-..> 16-Feb-2026 16:08:51 329322
wst04-VHDL20_DWEI_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:16 327856
wst04-VHDL20_DWEI_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:16 327956
wst04-VHDL20_DWEI_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:16 328003
wst04-VHDL20_DWEI_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:18 335268
wst04-VHDL20_DWEI_171800-2602171800-omedes--0.pdf 17-Feb-2026 21:58:46 334536
wst04-VHDL20_DWEI_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:22 335218
wst04-VHDL20_DWEI_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:22 335170
wst04-VHDL20_DWEI_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:22 336229
wst04-VHDL20_DWHG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:22 317905
wst04-VHDL20_DWHG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:22 318549
wst04-VHDL20_DWHG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:13 318538
wst04-VHDL20_DWHG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:27 314672
wst04-VHDL20_DWHG_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:22 314061
wst04-VHDL20_DWHG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:18 313431
wst04-VHDL20_DWHG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:13 313583
wst04-VHDL20_DWHG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:26 321547
wst04-VHDL20_DWHH_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:22 304859
wst04-VHDL20_DWHH_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:22 304989
wst04-VHDL20_DWHH_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:13 305098
wst04-VHDL20_DWHH_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:27 304113
wst04-VHDL20_DWHH_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:22 303897
wst04-VHDL20_DWHH_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:18 303689
wst04-VHDL20_DWHH_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:13 303566
wst04-VHDL20_DWHH_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:26 313813
wst04-VHDL20_DWLG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:20 308327
wst04-VHDL20_DWLG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:26 308933
wst04-VHDL20_DWLG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:40 308192
wst04-VHDL20_DWLG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:31 310950
wst04-VHDL20_DWLG_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:26 311268
wst04-VHDL20_DWLG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:26 311399
wst04-VHDL20_DWLG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:41 311406
wst04-VHDL20_DWLG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:32 316040
wst04-VHDL20_DWLH_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:26 309905
wst04-VHDL20_DWLH_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:26 310586
wst04-VHDL20_DWLH_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:40 309891
wst04-VHDL20_DWLH_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:31 314099
wst04-VHDL20_DWLH_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:26 314351
wst04-VHDL20_DWLH_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:22 314039
wst04-VHDL20_DWLH_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:41 313837
wst04-VHDL20_DWLH_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:32 315110
wst04-VHDL20_DWLI_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:26 308903
wst04-VHDL20_DWLI_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:26 309175
wst04-VHDL20_DWLI_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:40 308525
wst04-VHDL20_DWLI_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:37 315614
wst04-VHDL20_DWLI_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:22 316159
wst04-VHDL20_DWLI_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:26 316106
wst04-VHDL20_DWLI_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:41 316056
wst04-VHDL20_DWLI_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:32 316111
wst04-VHDL20_DWMG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:16 519864
wst04-VHDL20_DWMG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:16 519038
wst04-VHDL20_DWMG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:26 519419
wst04-VHDL20_DWMG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:22 533136
wst04-VHDL20_DWMG_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:16 530656
wst04-VHDL20_DWMG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:12 530533
wst04-VHDL20_DWMG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:26 530636
wst04-VHDL20_DWMG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:22 547202
wst04-VHDL20_DWMO_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:16 421765
wst04-VHDL20_DWMO_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:16 421846
wst04-VHDL20_DWMO_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:22 422281
wst04-VHDL20_DWMO_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:22 425243
wst04-VHDL20_DWMO_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:16 423834
wst04-VHDL20_DWMO_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:12 423936
wst04-VHDL20_DWMO_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:22 424867
wst04-VHDL20_DWMO_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:16 433119
wst04-VHDL20_DWMP_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:16 541525
wst04-VHDL20_DWMP_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:16 539326
wst04-VHDL20_DWMP_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:22 541127
wst04-VHDL20_DWMP_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:22 554252
wst04-VHDL20_DWMP_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:16 551534
wst04-VHDL20_DWMP_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:16 550587
wst04-VHDL20_DWMP_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:22 551683
wst04-VHDL20_DWMP_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:22 558255
wst04-VHDL20_DWPG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:26 316360
wst04-VHDL20_DWPG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:26 316150
wst04-VHDL20_DWPG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:30 315093
wst04-VHDL20_DWPG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:31 362094
wst04-VHDL20_DWPG_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:26 317030
wst04-VHDL20_DWPG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:26 316668
wst04-VHDL20_DWPG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:31 317091
wst04-VHDL20_DWPG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:32 362204
wst04-VHDL20_DWPH_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:20 271180
wst04-VHDL20_DWPH_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:22 226687
wst04-VHDL20_DWPH_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:00:30 226143
wst04-VHDL20_DWPH_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:31 271195
wst04-VHDL20_DWPH_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:22 270958
wst04-VHDL20_DWPH_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:22 225839
wst04-VHDL20_DWPH_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:00:31 226042
wst04-VHDL20_DWPH_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:26 271434
wst04-VHDL20_DWSG_161300-2602161300-omedes--0.pdf 16-Feb-2026 14:45:15 329774
wst04-VHDL20_DWSG_161800-2602161800-omedes--0.pdf 16-Feb-2026 19:45:12 328340
wst04-VHDL20_DWSG_170200-2602170200-omedes--0.pdf 17-Feb-2026 03:45:12 328980
wst04-VHDL20_DWSG_170400-2602170400-omedes--0.pdf 17-Feb-2026 06:15:16 329761
wst04-VHDL20_DWSG_170400_COR-2602170400-omedes-..> 17-Feb-2026 06:20:46 329855
wst04-VHDL20_DWSG_170800-2602170800-omedes--0.pdf 17-Feb-2026 09:45:12 335883
wst04-VHDL20_DWSG_171300-2602171300-omedes--0.pdf 17-Feb-2026 14:45:12 335834
wst04-VHDL20_DWSG_171800-2602171800-omedes--0.pdf 17-Feb-2026 19:45:10 334674
wst04-VHDL20_DWSG_180200-2602180200-omedes--0.pdf 18-Feb-2026 03:45:12 335523
wst04-VHDL20_DWSG_180400-2602180400-omedes--0.pdf 18-Feb-2026 06:15:16 335630
wst04-VHDL20_DWSG_180800-2602180800-omedes--0.pdf 18-Feb-2026 09:45:12 337181