Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-Jan-2026 10:34:25 2436
FPDL13_DWMZ_030600 03-Jan-2026 09:55:09 2436
SXDL31_DWAV_020800 02-Jan-2026 08:33:28 8896
SXDL31_DWAV_021800 02-Jan-2026 17:46:19 14030
SXDL31_DWAV_030800 03-Jan-2026 07:56:01 11197
SXDL31_DWAV_031800 03-Jan-2026 18:02:29 11053
SXDL31_DWAV_LATEST 03-Jan-2026 18:02:29 11053
SXDL33_DWAV_020000 02-Jan-2026 11:18:33 6976
SXDL33_DWAV_030000 03-Jan-2026 10:43:43 8521
SXDL33_DWAV_LATEST 03-Jan-2026 10:43:43 8521
ber01-FWDL39_DWMS_021230-2601021230-dsw--0-ia5 02-Jan-2026 13:14:31 2011
ber01-FWDL39_DWMS_031230-2601031230-dsw--0-ia5 03-Jan-2026 12:39:52 1850
ber01-VHDL13_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 4355
ber01-VHDL13_DWEH_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:18 4391
ber01-VHDL13_DWEH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:17 4516
ber01-VHDL13_DWEH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:22 4668
ber01-VHDL13_DWEH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:16 3894
ber01-VHDL13_DWEH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 4146
ber01-VHDL13_DWEH_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:17 4234
ber01-VHDL13_DWEH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:17 4022
ber01-VHDL13_DWEH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:17 3682
ber01-VHDL13_DWEH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:42 3682
ber01-VHDL13_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3605
ber01-VHDL13_DWHG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3605
ber01-VHDL13_DWHG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:07 3641
ber01-VHDL13_DWHG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:07 4379
ber01-VHDL13_DWHG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 4462
ber01-VHDL13_DWHG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4146
ber01-VHDL13_DWHG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 4812
ber01-VHDL13_DWHG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:10 3851
ber01-VHDL13_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3589
ber01-VHDL13_DWHH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3589
ber01-VHDL13_DWHH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:07 3446
ber01-VHDL13_DWHH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:07 3853
ber01-VHDL13_DWHH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 4137
ber01-VHDL13_DWHH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4137
ber01-VHDL13_DWHH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 4392
ber01-VHDL13_DWHH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:10 3783
ber01-VHDL13_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3312
ber01-VHDL13_DWLG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3271
ber01-VHDL13_DWLG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3298
ber01-VHDL13_DWLG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:02:16 3349
ber01-VHDL13_DWLG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2996
ber01-VHDL13_DWLG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 2984
ber01-VHDL13_DWLG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 2905
ber01-VHDL13_DWLG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3191
ber01-VHDL13_DWLG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2921
ber01-VHDL13_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3105
ber01-VHDL13_DWLH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3063
ber01-VHDL13_DWLH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3341
ber01-VHDL13_DWLH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:02:28 3622
ber01-VHDL13_DWLH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3176
ber01-VHDL13_DWLH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3285
ber01-VHDL13_DWLH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3381
ber01-VHDL13_DWLH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3653
ber01-VHDL13_DWLH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3309
ber01-VHDL13_DWLH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:54:46 3476
ber01-VHDL13_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3053
ber01-VHDL13_DWLI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3010
ber01-VHDL13_DWLI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3059
ber01-VHDL13_DWLI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:03:11 3085
ber01-VHDL13_DWLI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2784
ber01-VHDL13_DWLI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 2768
ber01-VHDL13_DWLI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 2728
ber01-VHDL13_DWLI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 2982
ber01-VHDL13_DWLI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2900
ber01-VHDL13_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4217
ber01-VHDL13_DWMG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 4176
ber01-VHDL13_DWMG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 4226
ber01-VHDL13_DWMG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 4178
ber01-VHDL13_DWMG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3654
ber01-VHDL13_DWMG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3634
ber01-VHDL13_DWMG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 4056
ber01-VHDL13_DWMG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3543
ber01-VHDL13_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3649
ber01-VHDL13_DWMO_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 3616
ber01-VHDL13_DWMO_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3671
ber01-VHDL13_DWMO_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3154
ber01-VHDL13_DWMO_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3152
ber01-VHDL13_DWMO_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3154
ber01-VHDL13_DWMO_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 3217
ber01-VHDL13_DWMO_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2983
ber01-VHDL13_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4467
ber01-VHDL13_DWMP_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 4435
ber01-VHDL13_DWMP_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 4347
ber01-VHDL13_DWMP_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 4066
ber01-VHDL13_DWMP_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3209
ber01-VHDL13_DWMP_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3193
ber01-VHDL13_DWMP_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 3193
ber01-VHDL13_DWMP_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 09:43:21 3449
ber01-VHDL13_DWMP_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2802
ber01-VHDL13_DWOG_011700_COR-2601011700-dsw--0-ia5 01-Jan-2026 21:39:14 5574
ber01-VHDL13_DWOG_020300-2601020300-dsw--0-ia5 02-Jan-2026 04:00:02 5142
ber01-VHDL13_DWOG_020800-2601020800-dsw--0-ia5 02-Jan-2026 10:56:57 5591
ber01-VHDL13_DWOG_021700-2601021700-dsw--0-ia5 02-Jan-2026 19:00:01 5490
ber01-VHDL13_DWOG_030300-2601030300-dsw--0-ia5 03-Jan-2026 04:00:07 5716
ber01-VHDL13_DWOG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:02 5518
ber01-VHDL13_DWOG_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 13:23:01 5668
ber01-VHDL13_DWOG_031700-2601031700-dsw--0-ia5 03-Jan-2026 19:00:07 5362
ber01-VHDL13_DWOG_031700_COR-2601031700-dsw--0-ia5 03-Jan-2026 15:54:22 6330
ber01-VHDL13_DWOH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3698
ber01-VHDL13_DWOH_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:11 3690
ber01-VHDL13_DWOH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:17 4008
ber01-VHDL13_DWOH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:22 4174
ber01-VHDL13_DWOH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:16 3482
ber01-VHDL13_DWOH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 3567
ber01-VHDL13_DWOH_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:11 3824
ber01-VHDL13_DWOH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:17 3559
ber01-VHDL13_DWOH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:17 3623
ber01-VHDL13_DWOH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:42 3631
ber01-VHDL13_DWOI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3404
ber01-VHDL13_DWOI_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:11 3394
ber01-VHDL13_DWOI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:11 3321
ber01-VHDL13_DWOI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:16 3637
ber01-VHDL13_DWOI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:12 2933
ber01-VHDL13_DWOI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:28:28 3235
ber01-VHDL13_DWOI_030400-2601030400-dsw--0-ia5 03-Jan-2026 05:58:11 3299
ber01-VHDL13_DWOI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:28:11 3450
ber01-VHDL13_DWOI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:28:11 2800
ber01-VHDL13_DWOI_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:38 2774
ber01-VHDL13_DWON_012138-2601012138-dsw--0-ia5 01-Jan-2026 21:38:41 3434
ber01-VHDL13_DWON_012324-2601012324-dsw--0-ia5 01-Jan-2026 23:24:11 3289
ber01-VHDL13_DWON_020356-2601020356-dsw--0-ia5 02-Jan-2026 03:56:26 3289
ber01-VHDL13_DWON_020629-2601020629-dsw--0-ia5 02-Jan-2026 06:29:12 3755
ber01-VHDL13_DWON_020718-2601020718-dsw--0-ia5 02-Jan-2026 07:18:26 3896
ber01-VHDL13_DWON_021056-2601021056-dsw--0-ia5 02-Jan-2026 10:56:33 3896
ber01-VHDL13_DWON_021533-2601021533-dsw--0-ia5 02-Jan-2026 15:33:41 3205
ber01-VHDL13_DWON_021539-2601021539-dsw--0-ia5 02-Jan-2026 15:39:26 3452
ber01-VHDL13_DWON_021719-2601021719-dsw--0-ia5 02-Jan-2026 17:19:26 3599
ber01-VHDL13_DWON_021746-2601021746-dsw--0-ia5 02-Jan-2026 17:46:23 3599
ber01-VHDL13_DWON_022054-2601022054-dsw--0-ia5 02-Jan-2026 20:55:02 3471
ber01-VHDL13_DWON_030146-2601030146-dsw--0-ia5 03-Jan-2026 01:46:17 3861
ber01-VHDL13_DWON_030421-2601030421-dsw--0-ia5 03-Jan-2026 04:21:52 3861
ber01-VHDL13_DWON_030629-2601030629-dsw--0-ia5 03-Jan-2026 06:29:57 3732
ber01-VHDL13_DWON_030708-2601030708-dsw--0-ia5 03-Jan-2026 07:08:17 3973
ber01-VHDL13_DWON_030732-2601030732-dsw--0-ia5 03-Jan-2026 07:32:06 3983
ber01-VHDL13_DWON_031322-2601031322-dsw--0-ia5 03-Jan-2026 13:22:31 3987
ber01-VHDL13_DWON_031547-2601031547-dsw--0-ia5 03-Jan-2026 15:47:37 3985
ber01-VHDL13_DWON_031554-2601031554-dsw--0-ia5 03-Jan-2026 15:54:12 4021
ber01-VHDL13_DWON_031811-2601031811-dsw--0-ia5 03-Jan-2026 18:11:27 3561
ber01-VHDL13_DWON_032120-2601032120-dsw--0-ia5 03-Jan-2026 21:20:07 3408
ber01-VHDL13_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 2476
ber01-VHDL13_DWPG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 2524
ber01-VHDL13_DWPG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 2662
ber01-VHDL13_DWPG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:08:27 3064
ber01-VHDL13_DWPG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2853
ber01-VHDL13_DWPG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3353
ber01-VHDL13_DWPG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3070
ber01-VHDL13_DWPG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3244
ber01-VHDL13_DWPG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2848
ber01-VHDL13_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3099
ber01-VHDL13_DWPH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3115
ber01-VHDL13_DWPH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3122
ber01-VHDL13_DWPH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:09:32 3399
ber01-VHDL13_DWPH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3103
ber01-VHDL13_DWPH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:07 3179
ber01-VHDL13_DWPH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:02 3137
ber01-VHDL13_DWPH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 2940
ber01-VHDL13_DWPH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 3019
ber01-VHDL13_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3726
ber01-VHDL13_DWSG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 4144
ber01-VHDL13_DWSG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3908
ber01-VHDL13_DWSG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3472
ber01-VHDL13_DWSG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:30:04 3336
ber01-VHDL13_DWSG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:07 3174
ber01-VHDL13_DWSG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:30:06 3182
ber01-VHDL13_DWSG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:30:01 2913
ber01-VHDL17_DWOG_021200-2601021200-dsw--0-ia5 02-Jan-2026 12:38:21 2766
ber01-VHDL17_DWOG_031200-2601031200-dsw--0-ia5 03-Jan-2026 12:28:20 2622
swis2-VHDL20_DWEG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4171
swis2-VHDL20_DWEG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4093
swis2-VHDL20_DWEG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4819
swis2-VHDL20_DWEG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:02:56 5365
swis2-VHDL20_DWEG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4308
swis2-VHDL20_DWEG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 4308
swis2-VHDL20_DWEG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 4433
swis2-VHDL20_DWEG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4473
swis2-VHDL20_DWEG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4358
swis2-VHDL20_DWEG_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:00:18 4368
swis2-VHDL20_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4976
swis2-VHDL20_DWEH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4895
swis2-VHDL20_DWEH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 5503
swis2-VHDL20_DWEH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:01:46 5768
swis2-VHDL20_DWEH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4632
swis2-VHDL20_DWEH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 4853
swis2-VHDL20_DWEH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 4809
swis2-VHDL20_DWEH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4995
swis2-VHDL20_DWEH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4344
swis2-VHDL20_DWEH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:35:07 4736
swis2-VHDL20_DWEI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 3870
swis2-VHDL20_DWEI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 3871
swis2-VHDL20_DWEI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4474
swis2-VHDL20_DWEI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:04:21 4674
swis2-VHDL20_DWEI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3583
swis2-VHDL20_DWEI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3843
swis2-VHDL20_DWEI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:03 3874
swis2-VHDL20_DWEI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4117
swis2-VHDL20_DWEI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3372
swis2-VHDL20_DWEI_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 19:59:27 3376
swis2-VHDL20_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3791
swis2-VHDL20_DWHG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3788
swis2-VHDL20_DWHG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4373
swis2-VHDL20_DWHG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4562
swis2-VHDL20_DWHG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4648
swis2-VHDL20_DWHG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:06 4329
swis2-VHDL20_DWHG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 5521
swis2-VHDL20_DWHG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 4034
swis2-VHDL20_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3775
swis2-VHDL20_DWHH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3775
swis2-VHDL20_DWHH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4128
swis2-VHDL20_DWHH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4039
swis2-VHDL20_DWHH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4323
swis2-VHDL20_DWHH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:07 4323
swis2-VHDL20_DWHH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 5122
swis2-VHDL20_DWHH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3969
swis2-VHDL20_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3793
swis2-VHDL20_DWLG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3713
swis2-VHDL20_DWLG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3945
swis2-VHDL20_DWLG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:03:40 3996
swis2-VHDL20_DWLG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3438
swis2-VHDL20_DWLG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3429
swis2-VHDL20_DWLG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3332
swis2-VHDL20_DWLG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3795
swis2-VHDL20_DWLG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3324
swis2-VHDL20_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3588
swis2-VHDL20_DWLH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3510
swis2-VHDL20_DWLH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3994
swis2-VHDL20_DWLH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3623
swis2-VHDL20_DWLH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3734
swis2-VHDL20_DWLH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3843
swis2-VHDL20_DWLH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 4247
swis2-VHDL20_DWLH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3719
swis2-VHDL20_DWLH_031800_COR-2601031800-dsw--0-ia5 03-Jan-2026 20:55:41 3886
swis2-VHDL20_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3541
swis2-VHDL20_DWLI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3455
swis2-VHDL20_DWLI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3709
swis2-VHDL20_DWLI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3229
swis2-VHDL20_DWLI_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3216
swis2-VHDL20_DWLI_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3157
swis2-VHDL20_DWLI_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3587
swis2-VHDL20_DWLI_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3305
swis2-VHDL20_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4642
swis2-VHDL20_DWMG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4695
swis2-VHDL20_DWMG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4951
swis2-VHDL20_DWMG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4693
swis2-VHDL20_DWMG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 4064
swis2-VHDL20_DWMG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 4065
swis2-VHDL20_DWMG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 4706
swis2-VHDL20_DWMG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 4043
swis2-VHDL20_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4083
swis2-VHDL20_DWMO_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4091
swis2-VHDL20_DWMO_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4355
swis2-VHDL20_DWMO_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3626
swis2-VHDL20_DWMO_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 3588
swis2-VHDL20_DWMO_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3591
swis2-VHDL20_DWMO_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 3876
swis2-VHDL20_DWMO_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 3468
swis2-VHDL20_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4900
swis2-VHDL20_DWMP_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4946
swis2-VHDL20_DWMP_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 5069
swis2-VHDL20_DWMP_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4568
swis2-VHDL20_DWMP_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:06 3606
swis2-VHDL20_DWMP_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3584
swis2-VHDL20_DWMP_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:01 4124
swis2-VHDL20_DWMP_030800_COR-2601030800-dsw--0-ia5 03-Jan-2026 09:43:21 4128
swis2-VHDL20_DWMP_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:06 3334
swis2-VHDL20_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3015
swis2-VHDL20_DWPG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:16 3000
swis2-VHDL20_DWPG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3318
swis2-VHDL20_DWPG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:13:01 3750
swis2-VHDL20_DWPG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3534
swis2-VHDL20_DWPG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3793
swis2-VHDL20_DWPG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3601
swis2-VHDL20_DWPG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3846
swis2-VHDL20_DWPG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3528
swis2-VHDL20_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3637
swis2-VHDL20_DWPH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3593
swis2-VHDL20_DWPH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3776
swis2-VHDL20_DWPH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:13:16 4083
swis2-VHDL20_DWPH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3784
swis2-VHDL20_DWPH_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3618
swis2-VHDL20_DWPH_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:00:18 3641
swis2-VHDL20_DWPH_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:06 3542
swis2-VHDL20_DWPH_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3679
swis2-VHDL20_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 4187
swis2-VHDL20_DWSG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4614
swis2-VHDL20_DWSG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4571
swis2-VHDL20_DWSG_021300-2601021300-dsw--0-ia5 02-Jan-2026 14:45:07 4445
swis2-VHDL20_DWSG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3909
swis2-VHDL20_DWSG_030200-2601030200-dsw--0-ia5 03-Jan-2026 03:45:02 3816
swis2-VHDL20_DWSG_030400-2601030400-dsw--0-ia5 03-Jan-2026 06:15:01 3589
swis2-VHDL20_DWSG_030800-2601030800-dsw--0-ia5 03-Jan-2026 09:45:04 3798
swis2-VHDL20_DWSG_031300-2601031300-dsw--0-ia5 03-Jan-2026 14:45:15 3580
swis2-VHDL20_DWSG_031800-2601031800-dsw--0-ia5 03-Jan-2026 19:45:02 3330
wst04-VHDL20_DWEG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 226084
wst04-VHDL20_DWEG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:27 225388
wst04-VHDL20_DWEG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 230038
wst04-VHDL20_DWEG_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:32 230163
wst04-VHDL20_DWEG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 228453
wst04-VHDL20_DWEG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 229920
wst04-VHDL20_DWEG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 229594
wst04-VHDL20_DWEG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:22 224604
wst04-VHDL20_DWEG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 223645
wst04-VHDL20_DWEG_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 223646
wst04-VHDL20_DWEH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 223887
wst04-VHDL20_DWEH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:21 223353
wst04-VHDL20_DWEH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 225172
wst04-VHDL20_DWEH_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:22 225201
wst04-VHDL20_DWEH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 223694
wst04-VHDL20_DWEH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 224913
wst04-VHDL20_DWEH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:22 224398
wst04-VHDL20_DWEH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:22 225631
wst04-VHDL20_DWEH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 224498
wst04-VHDL20_DWEH_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 224557
wst04-VHDL20_DWEI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 310056
wst04-VHDL20_DWEI_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:27 309991
wst04-VHDL20_DWEI_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 314465
wst04-VHDL20_DWEI_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:26 314465
wst04-VHDL20_DWEI_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 313821
wst04-VHDL20_DWEI_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 314790
wst04-VHDL20_DWEI_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:22 314756
wst04-VHDL20_DWEI_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 307701
wst04-VHDL20_DWEI_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 306191
wst04-VHDL20_DWEI_031800_COR-2601031800-omedes-..> 03-Jan-2026 19:59:38 306191
wst04-VHDL20_DWHG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 303500
wst04-VHDL20_DWHG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:11 303534
wst04-VHDL20_DWHG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 308191
wst04-VHDL20_DWHG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 307802
wst04-VHDL20_DWHG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 307605
wst04-VHDL20_DWHG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:11 306521
wst04-VHDL20_DWHG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:16 307415
wst04-VHDL20_DWHG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 305691
wst04-VHDL20_DWHH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 310034
wst04-VHDL20_DWHH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:11 310078
wst04-VHDL20_DWHH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:12 309924
wst04-VHDL20_DWHH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 310099
wst04-VHDL20_DWHH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:13 309988
wst04-VHDL20_DWHH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:11 309988
wst04-VHDL20_DWHH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:12 299655
wst04-VHDL20_DWHH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 298725
wst04-VHDL20_DWLG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 295652
wst04-VHDL20_DWLG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 295828
wst04-VHDL20_DWLG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 305055
wst04-VHDL20_DWLG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 304799
wst04-VHDL20_DWLG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 304896
wst04-VHDL20_DWLG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 304818
wst04-VHDL20_DWLG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 298030
wst04-VHDL20_DWLG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 298083
wst04-VHDL20_DWLH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 293642
wst04-VHDL20_DWLH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 293828
wst04-VHDL20_DWLH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 304936
wst04-VHDL20_DWLH_020800_COR-2601020800-omedes-..> 02-Jan-2026 15:04:17 305582
wst04-VHDL20_DWLH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:27 305011
wst04-VHDL20_DWLH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 304818
wst04-VHDL20_DWLH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 304742
wst04-VHDL20_DWLH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 301938
wst04-VHDL20_DWLH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 301076
wst04-VHDL20_DWLH_031800_COR-2601031800-omedes-..> 03-Jan-2026 20:55:17 301276
wst04-VHDL20_DWLI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 292952
wst04-VHDL20_DWLI_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 293253
wst04-VHDL20_DWLI_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:26 298333
wst04-VHDL20_DWLI_020800_COR-2601020800-omedes-..> 02-Jan-2026 15:05:05 298049
wst04-VHDL20_DWLI_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 297174
wst04-VHDL20_DWLI_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:26 297087
wst04-VHDL20_DWLI_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:42 297065
wst04-VHDL20_DWLI_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 298378
wst04-VHDL20_DWLI_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 298310
wst04-VHDL20_DWMG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 496655
wst04-VHDL20_DWMG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:21 496599
wst04-VHDL20_DWMG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 509387
wst04-VHDL20_DWMG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 508707
wst04-VHDL20_DWMG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 507376
wst04-VHDL20_DWMG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 507339
wst04-VHDL20_DWMG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 505750
wst04-VHDL20_DWMG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 502900
wst04-VHDL20_DWMO_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 398751
wst04-VHDL20_DWMO_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:17 399245
wst04-VHDL20_DWMO_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 405986
wst04-VHDL20_DWMO_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 405090
wst04-VHDL20_DWMO_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 404070
wst04-VHDL20_DWMO_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 404648
wst04-VHDL20_DWMO_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 403199
wst04-VHDL20_DWMO_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:16 402323
wst04-VHDL20_DWMP_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 520595
wst04-VHDL20_DWMP_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:17 522472
wst04-VHDL20_DWMP_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 532753
wst04-VHDL20_DWMP_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 532322
wst04-VHDL20_DWMP_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 529005
wst04-VHDL20_DWMP_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:16 530100
wst04-VHDL20_DWMP_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:18 526594
wst04-VHDL20_DWMP_030800_COR-2601030800-omedes-..> 03-Jan-2026 09:43:27 526594
wst04-VHDL20_DWMP_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 524525
wst04-VHDL20_DWPG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 299185
wst04-VHDL20_DWPG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:31 299206
wst04-VHDL20_DWPG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 360782
wst04-VHDL20_DWPG_020800_COR-2601020800-omedes-..> 02-Jan-2026 14:11:57 360726
wst04-VHDL20_DWPG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:27 315864
wst04-VHDL20_DWPG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 316233
wst04-VHDL20_DWPG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:32 315759
wst04-VHDL20_DWPG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:32 351989
wst04-VHDL20_DWPG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:26 306898
wst04-VHDL20_DWPH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 223259
wst04-VHDL20_DWPH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:31 223408
wst04-VHDL20_DWPH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:26 269438
wst04-VHDL20_DWPH_020800_COR-2601020800-omedes-..> 02-Jan-2026 14:12:27 269311
wst04-VHDL20_DWPH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 269511
wst04-VHDL20_DWPH_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:22 224935
wst04-VHDL20_DWPH_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:00:32 224677
wst04-VHDL20_DWPH_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:26 267875
wst04-VHDL20_DWPH_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:22 268126
wst04-VHDL20_DWSG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 318413
wst04-VHDL20_DWSG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:17 318769
wst04-VHDL20_DWSG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:12 328154
wst04-VHDL20_DWSG_021300-2601021300-omedes--0.pdf 02-Jan-2026 14:45:12 328111
wst04-VHDL20_DWSG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:11 327760
wst04-VHDL20_DWSG_030200-2601030200-omedes--0.pdf 03-Jan-2026 03:45:17 327683
wst04-VHDL20_DWSG_030400-2601030400-omedes--0.pdf 03-Jan-2026 06:15:11 327266
wst04-VHDL20_DWSG_030800-2601030800-omedes--0.pdf 03-Jan-2026 09:45:12 317335
wst04-VHDL20_DWSG_031300-2601031300-omedes--0.pdf 03-Jan-2026 14:45:15 317258
wst04-VHDL20_DWSG_031800-2601031800-omedes--0.pdf 03-Jan-2026 19:45:12 317239