Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Nov-2025 14:29:55 3387
FPDL13_DWMZ_180600 18-Nov-2025 15:10:33 6195
SXDL31_DWAV_161800 16-Nov-2025 18:21:43 7704
SXDL31_DWAV_170800 17-Nov-2025 08:46:47 9673
SXDL31_DWAV_171800 17-Nov-2025 17:12:43 13055
SXDL31_DWAV_180800 18-Nov-2025 10:02:54 12266
SXDL31_DWAV_LATEST 18-Nov-2025 10:02:54 12266
SXDL33_DWAV_170000 17-Nov-2025 11:03:39 9165
SXDL33_DWAV_180000 18-Nov-2025 11:18:08 15773
SXDL33_DWAV_LATEST 18-Nov-2025 11:18:08 15773
ber01-FWDL39_DWMS_171230-2511171230-dsw--0-ia5 17-Nov-2025 12:26:57 1839
ber01-FWDL39_DWMS_181230-2511181230-dsw--0-ia5 18-Nov-2025 12:27:47 1827
ber01-VHDL13_DWEH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:12 3546
ber01-VHDL13_DWEH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:11 3548
ber01-VHDL13_DWEH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3486
ber01-VHDL13_DWEH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:17 3380
ber01-VHDL13_DWEH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:57:02 3589
ber01-VHDL13_DWEH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:28:17 3034
ber01-VHDL13_DWEH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:28:12 3093
ber01-VHDL13_DWEH_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:58:17 3271
ber01-VHDL13_DWEH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:28:11 3271
ber01-VHDL13_DWEH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:16 3631
ber01-VHDL13_DWHG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:11 4165
ber01-VHDL13_DWHG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:09 4319
ber01-VHDL13_DWHG_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:07:47 4307
ber01-VHDL13_DWHG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4303
ber01-VHDL13_DWHG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3940
ber01-VHDL13_DWHG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:08 3576
ber01-VHDL13_DWHG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:07 3704
ber01-VHDL13_DWHG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:08 3777
ber01-VHDL13_DWHG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:09 4048
ber01-VHDL13_DWHG_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 09:42:17 4072
ber01-VHDL13_DWHH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:11 3815
ber01-VHDL13_DWHH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:09 3860
ber01-VHDL13_DWHH_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:07:11 3842
ber01-VHDL13_DWHH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 3841
ber01-VHDL13_DWHH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3793
ber01-VHDL13_DWHH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:08 3373
ber01-VHDL13_DWHH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:07 3433
ber01-VHDL13_DWHH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:08 3463
ber01-VHDL13_DWHH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:09 3500
ber01-VHDL13_DWHH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 09:42:37 3461
ber01-VHDL13_DWLG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2755
ber01-VHDL13_DWLG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3488
ber01-VHDL13_DWLG_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 3262
ber01-VHDL13_DWLG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3386
ber01-VHDL13_DWLG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:08 2847
ber01-VHDL13_DWLG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:01 2911
ber01-VHDL13_DWLG_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:59:56 2871
ber01-VHDL13_DWLG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:01 2820
ber01-VHDL13_DWLH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2825
ber01-VHDL13_DWLH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3223
ber01-VHDL13_DWLH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 3017
ber01-VHDL13_DWLH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 3034
ber01-VHDL13_DWLH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:08 2621
ber01-VHDL13_DWLH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:01 3320
ber01-VHDL13_DWLH_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:59:56 2916
ber01-VHDL13_DWLH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:01 3262
ber01-VHDL13_DWLI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2638
ber01-VHDL13_DWLI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 2964
ber01-VHDL13_DWLI_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:59:57 2754
ber01-VHDL13_DWLI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:09 2753
ber01-VHDL13_DWLI_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:08 2583
ber01-VHDL13_DWLI_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:01 2879
ber01-VHDL13_DWLI_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:59:56 2699
ber01-VHDL13_DWLI_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:01 2875
ber01-VHDL13_DWMG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3471
ber01-VHDL13_DWMG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3463
ber01-VHDL13_DWMG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3563
ber01-VHDL13_DWMG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:56:57 4201
ber01-VHDL13_DWMG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 2934
ber01-VHDL13_DWMG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:03 3206
ber01-VHDL13_DWMG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 3206
ber01-VHDL13_DWMG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:09 3212
ber01-VHDL13_DWMO_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3180
ber01-VHDL13_DWMO_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3289
ber01-VHDL13_DWMO_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:30:42 3368
ber01-VHDL13_DWMO_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3364
ber01-VHDL13_DWMO_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3279
ber01-VHDL13_DWMO_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 2727
ber01-VHDL13_DWMO_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:03 3112
ber01-VHDL13_DWMO_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 3112
ber01-VHDL13_DWMO_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:09 3070
ber01-VHDL13_DWMP_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 3290
ber01-VHDL13_DWMP_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3290
ber01-VHDL13_DWMP_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:26:07 3106
ber01-VHDL13_DWMP_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3354
ber01-VHDL13_DWMP_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3587
ber01-VHDL13_DWMP_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 2557
ber01-VHDL13_DWMP_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:03 2763
ber01-VHDL13_DWMP_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 2763
ber01-VHDL13_DWMP_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:09 2225
ber01-VHDL13_DWOG_161700-2511161700-dsw--0-ia5 16-Nov-2025 19:00:02 4877
ber01-VHDL13_DWOG_170300-2511170300-dsw--0-ia5 17-Nov-2025 04:00:01 5990
ber01-VHDL13_DWOG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 5345
ber01-VHDL13_DWOG_171700-2511171700-dsw--0-ia5 17-Nov-2025 19:00:02 4815
ber01-VHDL13_DWOG_180300-2511180300-dsw--0-ia5 18-Nov-2025 04:00:02 4742
ber01-VHDL13_DWOG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:03 5081
ber01-VHDL13_DWOH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:16 3404
ber01-VHDL13_DWOH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:11 3529
ber01-VHDL13_DWOH_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3384
ber01-VHDL13_DWOH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:11 3030
ber01-VHDL13_DWOH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:57:02 3248
ber01-VHDL13_DWOH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:28:11 2827
ber01-VHDL13_DWOH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:28:16 3105
ber01-VHDL13_DWOH_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:58:17 3114
ber01-VHDL13_DWOH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:28:11 3114
ber01-VHDL13_DWOH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:16 3255
ber01-VHDL13_DWOI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:28:12 2822
ber01-VHDL13_DWOI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:28:17 3049
ber01-VHDL13_DWOI_170400-2511170400-dsw--0-ia5 17-Nov-2025 05:58:17 3014
ber01-VHDL13_DWOI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:28:11 2682
ber01-VHDL13_DWOI_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:56 2686
ber01-VHDL13_DWOI_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:28:17 2594
ber01-VHDL13_DWOI_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:28:12 2940
ber01-VHDL13_DWOI_180400-2511180400-dsw--0-ia5 18-Nov-2025 05:58:17 3030
ber01-VHDL13_DWOI_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:28:18 3036
ber01-VHDL13_DWOI_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:11 2907
ber01-VHDL13_DWON_161829-2511161829-dsw--0-ia5 16-Nov-2025 18:29:17 3916
ber01-VHDL13_DWON_170339-2511170339-dsw--0-ia5 17-Nov-2025 03:39:27 4706
ber01-VHDL13_DWON_170629-2511170629-dsw--0-ia5 17-Nov-2025 06:29:52 4231
ber01-VHDL13_DWON_170727-2511170727-dsw--0-ia5 17-Nov-2025 07:27:56 4244
ber01-VHDL13_DWON_170753-2511170753-dsw--0-ia5 17-Nov-2025 07:53:15 4308
ber01-VHDL13_DWON_170919-2511170919-dsw--0-ia5 17-Nov-2025 09:19:30 4256
ber01-VHDL13_DWON_171539-2511171539-dsw--0-ia5 17-Nov-2025 15:39:12 3778
ber01-VHDL13_DWON_171552-2511171552-dsw--0-ia5 17-Nov-2025 15:52:01 3765
ber01-VHDL13_DWON_171736-2511171736-dsw--0-ia5 17-Nov-2025 17:36:12 3880
ber01-VHDL13_DWON_180044-2511180044-dsw--0-ia5 18-Nov-2025 00:44:22 3868
ber01-VHDL13_DWON_180629-2511180629-dsw--0-ia5 18-Nov-2025 06:29:16 4232
ber01-VHDL13_DWON_180637-2511180637-dsw--0-ia5 18-Nov-2025 06:37:07 4352
ber01-VHDL13_DWON_180900-2511180900-dsw--0-ia5 18-Nov-2025 09:00:12 4352
ber01-VHDL13_DWON_180927-2511180927-dsw--0-ia5 18-Nov-2025 09:27:21 4352
ber01-VHDL13_DWON_181136-2511181136-dsw--0-ia5 18-Nov-2025 11:36:16 4352
ber01-VHDL13_DWON_181542-2511181542-dsw--0-ia5 18-Nov-2025 15:42:46 4607
ber01-VHDL13_DWPG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2340
ber01-VHDL13_DWPG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 2450
ber01-VHDL13_DWPG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 2432
ber01-VHDL13_DWPG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 2433
ber01-VHDL13_DWPG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 2270
ber01-VHDL13_DWPG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:03 2149
ber01-VHDL13_DWPG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 2216
ber01-VHDL13_DWPG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:03 2284
ber01-VHDL13_DWPH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2723
ber01-VHDL13_DWPH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:01 3138
ber01-VHDL13_DWPH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3119
ber01-VHDL13_DWPH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3121
ber01-VHDL13_DWPH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 3115
ber01-VHDL13_DWPH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:03 2850
ber01-VHDL13_DWPH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 2719
ber01-VHDL13_DWPH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:03 2866
ber01-VHDL13_DWSG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:30:03 2728
ber01-VHDL13_DWSG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:30:03 3000
ber01-VHDL13_DWSG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 3075
ber01-VHDL13_DWSG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:30:03 3367
ber01-VHDL13_DWSG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:30:02 2554
ber01-VHDL13_DWSG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:30:01 2926
ber01-VHDL13_DWSG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:06 3666
ber01-VHDL13_DWSG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:30:01 3715
ber01-VHDL17_DWOG_171200-2511171200-dsw--0-ia5 17-Nov-2025 12:47:07 3126
ber01-VHDL17_DWOG_181200-2511181200-dsw--0-ia5 18-Nov-2025 12:46:32 4116
swis2-VHDL20_DWEG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 3969
swis2-VHDL20_DWEG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4044
swis2-VHDL20_DWEG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3952
swis2-VHDL20_DWEG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3999
swis2-VHDL20_DWEG_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 3427
swis2-VHDL20_DWEG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:06 3401
swis2-VHDL20_DWEG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3629
swis2-VHDL20_DWEG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:06 3693
swis2-VHDL20_DWEG_180800-2511180800-dsw--0-ia5 18-Nov-2025 11:06:15 4216
swis2-VHDL20_DWEG_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3434
swis2-VHDL20_DWEH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 4103
swis2-VHDL20_DWEH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4073
swis2-VHDL20_DWEH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3994
swis2-VHDL20_DWEH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4302
swis2-VHDL20_DWEH_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 3767
swis2-VHDL20_DWEH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:06 3565
swis2-VHDL20_DWEH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3597
swis2-VHDL20_DWEH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:06 3862
swis2-VHDL20_DWEH_180400_COR-2511180400-dsw--0-ia5 18-Nov-2025 04:59:21 3811
swis2-VHDL20_DWEH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:06 4118
swis2-VHDL20_DWEH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3809
swis2-VHDL20_DWEI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:06 3311
swis2-VHDL20_DWEI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 3480
swis2-VHDL20_DWEI_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:06 3551
swis2-VHDL20_DWEI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3636
swis2-VHDL20_DWEI_170800_COR-2511170800-dsw--0-ia5 17-Nov-2025 10:56:52 2865
swis2-VHDL20_DWEI_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:06 3131
swis2-VHDL20_DWEI_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3417
swis2-VHDL20_DWEI_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:06 3666
swis2-VHDL20_DWEI_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 3774
swis2-VHDL20_DWEI_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3086
swis2-VHDL20_DWHG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 4348
swis2-VHDL20_DWHG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4505
swis2-VHDL20_DWHG_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:09:32 4493
swis2-VHDL20_DWHG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4486
swis2-VHDL20_DWHG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4516
swis2-VHDL20_DWHG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:06 3759
swis2-VHDL20_DWHG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:01 3890
swis2-VHDL20_DWHG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:08 3960
swis2-VHDL20_DWHG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:06 4780
swis2-VHDL20_DWHH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 4001
swis2-VHDL20_DWHH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:07 4046
swis2-VHDL20_DWHH_170200_COR-2511170200-dsw--0-ia5 17-Nov-2025 04:08:48 4028
swis2-VHDL20_DWHH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:06 4027
swis2-VHDL20_DWHH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4336
swis2-VHDL20_DWHH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:06 3559
swis2-VHDL20_DWHH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:01 3619
swis2-VHDL20_DWHH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:08 3649
swis2-VHDL20_DWHH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:06 4119
swis2-VHDL20_DWLG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3180
swis2-VHDL20_DWLG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3991
swis2-VHDL20_DWLG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:23 3767
swis2-VHDL20_DWLG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:06 4141
swis2-VHDL20_DWLG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3345
swis2-VHDL20_DWLG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3412
swis2-VHDL20_DWLG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:22 3269
swis2-VHDL20_DWLG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 3494
swis2-VHDL20_DWLH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3254
swis2-VHDL20_DWLH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3655
swis2-VHDL20_DWLH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:23 3528
swis2-VHDL20_DWLH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:06 3783
swis2-VHDL20_DWLH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3125
swis2-VHDL20_DWLH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3827
swis2-VHDL20_DWLH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:22 3551
swis2-VHDL20_DWLH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 4139
swis2-VHDL20_DWLI_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3056
swis2-VHDL20_DWLI_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3460
swis2-VHDL20_DWLI_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:23 3256
swis2-VHDL20_DWLI_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:06 3509
swis2-VHDL20_DWLI_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3081
swis2-VHDL20_DWLI_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3380
swis2-VHDL20_DWLI_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:22 3099
swis2-VHDL20_DWLI_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 3553
swis2-VHDL20_DWMG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 4015
swis2-VHDL20_DWMG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 4078
swis2-VHDL20_DWMG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:03 3968
swis2-VHDL20_DWMG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 5066
swis2-VHDL20_DWMG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3432
swis2-VHDL20_DWMG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:01 3715
swis2-VHDL20_DWMG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:02 3729
swis2-VHDL20_DWMG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 4018
swis2-VHDL20_DWMO_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3707
swis2-VHDL20_DWMO_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3816
swis2-VHDL20_DWMO_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:03 3774
swis2-VHDL20_DWMO_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4118
swis2-VHDL20_DWMO_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3155
swis2-VHDL20_DWMO_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:01 3540
swis2-VHDL20_DWMO_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:02 3629
swis2-VHDL20_DWMO_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 3910
swis2-VHDL20_DWMP_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3749
swis2-VHDL20_DWMP_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3766
swis2-VHDL20_DWMP_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:03 3762
swis2-VHDL20_DWMP_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 4297
swis2-VHDL20_DWMP_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3056
swis2-VHDL20_DWMP_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:01 3264
swis2-VHDL20_DWMP_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:02 3154
swis2-VHDL20_DWMP_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 2823
swis2-VHDL20_DWPG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 2841
swis2-VHDL20_DWPG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 2778
swis2-VHDL20_DWPG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 2810
swis2-VHDL20_DWPG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3009
swis2-VHDL20_DWPG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 2872
swis2-VHDL20_DWPG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:03 2542
swis2-VHDL20_DWPG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 2621
swis2-VHDL20_DWPG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 2825
swis2-VHDL20_DWPH_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3223
swis2-VHDL20_DWPH_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3465
swis2-VHDL20_DWPH_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:00:01 3498
swis2-VHDL20_DWPH_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3696
swis2-VHDL20_DWPH_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 3721
swis2-VHDL20_DWPH_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:03 3241
swis2-VHDL20_DWPH_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:00:02 3131
swis2-VHDL20_DWPH_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 3371
swis2-VHDL20_DWSG_161800-2511161800-dsw--0-ia5 16-Nov-2025 19:45:02 3160
swis2-VHDL20_DWSG_170200-2511170200-dsw--0-ia5 17-Nov-2025 03:45:03 3417
swis2-VHDL20_DWSG_170400-2511170400-dsw--0-ia5 17-Nov-2025 06:15:03 3464
swis2-VHDL20_DWSG_170800-2511170800-dsw--0-ia5 17-Nov-2025 09:45:04 3944
swis2-VHDL20_DWSG_171300-2511171300-dsw--0-ia5 17-Nov-2025 14:45:08 3784
swis2-VHDL20_DWSG_171800-2511171800-dsw--0-ia5 17-Nov-2025 19:45:02 2945
swis2-VHDL20_DWSG_180200-2511180200-dsw--0-ia5 18-Nov-2025 03:45:07 3192
swis2-VHDL20_DWSG_180400-2511180400-dsw--0-ia5 18-Nov-2025 06:15:06 4160
swis2-VHDL20_DWSG_180800-2511180800-dsw--0-ia5 18-Nov-2025 09:45:02 4387
swis2-VHDL20_DWSG_181300-2511181300-dsw--0-ia5 18-Nov-2025 14:45:08 3937
wst04-VHDL20_DWEG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:12 234522
wst04-VHDL20_DWEG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:23 235662
wst04-VHDL20_DWEG_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:26 234593
wst04-VHDL20_DWEG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:26 230772
wst04-VHDL20_DWEG_170800_COR-2511170800-omedes-..> 17-Nov-2025 10:57:02 229244
wst04-VHDL20_DWEG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:16 229325
wst04-VHDL20_DWEG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:17 230343
wst04-VHDL20_DWEG_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:27 230525
wst04-VHDL20_DWEG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:22 231585
wst04-VHDL20_DWEG_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:11 230304
wst04-VHDL20_DWEH_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:16 232655
wst04-VHDL20_DWEH_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:23 234020
wst04-VHDL20_DWEH_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:22 233362
wst04-VHDL20_DWEH_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:26 235836
wst04-VHDL20_DWEH_170800_COR-2511170800-omedes-..> 17-Nov-2025 10:57:06 234716
wst04-VHDL20_DWEH_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:16 234606
wst04-VHDL20_DWEH_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:21 235795
wst04-VHDL20_DWEH_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:21 235504
wst04-VHDL20_DWEH_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:16 234984
wst04-VHDL20_DWEH_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:16 234080
wst04-VHDL20_DWEI_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:16 321179
wst04-VHDL20_DWEI_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:23 321524
wst04-VHDL20_DWEI_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:26 320608
wst04-VHDL20_DWEI_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:32 320423
wst04-VHDL20_DWEI_170800_COR-2511170800-omedes-..> 17-Nov-2025 10:57:06 318823
wst04-VHDL20_DWEI_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:20 319553
wst04-VHDL20_DWEI_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:21 320660
wst04-VHDL20_DWEI_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:27 320838
wst04-VHDL20_DWEI_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:28 319730
wst04-VHDL20_DWEI_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:16 318311
wst04-VHDL20_DWHG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:16 346893
wst04-VHDL20_DWHG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:11 347162
wst04-VHDL20_DWHG_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:00:12 347050
wst04-VHDL20_DWHG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:22 353975
wst04-VHDL20_DWHG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:16 351481
wst04-VHDL20_DWHG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:13 351656
wst04-VHDL20_DWHG_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:00:12 351667
wst04-VHDL20_DWHG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:16 352765
wst04-VHDL20_DWHH_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:16 337527
wst04-VHDL20_DWHH_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 337825
wst04-VHDL20_DWHH_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:00:17 337863
wst04-VHDL20_DWHH_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:22 340880
wst04-VHDL20_DWHH_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:16 338462
wst04-VHDL20_DWHH_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:13 338551
wst04-VHDL20_DWHH_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:00:12 338505
wst04-VHDL20_DWHH_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:16 335099
wst04-VHDL20_DWLG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:40:31 306181
wst04-VHDL20_DWLG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:40:35 306554
wst04-VHDL20_DWLG_170400-2511170400-omedes--0.pdf 17-Nov-2025 05:59:41 306520
wst04-VHDL20_DWLG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:40:31 314843
wst04-VHDL20_DWLG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:40:31 314810
wst04-VHDL20_DWLG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:40:33 314289
wst04-VHDL20_DWLG_180400-2511180400-omedes--0.pdf 18-Nov-2025 05:59:41 314390
wst04-VHDL20_DWLG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:40:45 310142
wst04-VHDL20_DWLH_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:40:21 308927
wst04-VHDL20_DWLH_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:40:25 309301
wst04-VHDL20_DWLH_170400-2511170400-omedes--0.pdf 17-Nov-2025 05:59:41 309804
wst04-VHDL20_DWLH_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:40:21 322554
wst04-VHDL20_DWLH_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:40:21 321187
wst04-VHDL20_DWLH_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:40:28 322359
wst04-VHDL20_DWLH_180400-2511180400-omedes--0.pdf 18-Nov-2025 05:59:41 321992
wst04-VHDL20_DWLH_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:40:28 318047
wst04-VHDL20_DWLI_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:40:43 310217
wst04-VHDL20_DWLI_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:40:43 310641
wst04-VHDL20_DWLI_170400-2511170400-omedes--0.pdf 17-Nov-2025 05:59:41 311062
wst04-VHDL20_DWLI_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:40:41 309283
wst04-VHDL20_DWLI_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:40:41 308602
wst04-VHDL20_DWLI_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:40:41 308776
wst04-VHDL20_DWLI_180400-2511180400-omedes--0.pdf 18-Nov-2025 05:59:41 308698
wst04-VHDL20_DWLI_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:40:45 312727
wst04-VHDL20_DWMG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:22 518416
wst04-VHDL20_DWMG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:23 518342
wst04-VHDL20_DWMG_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:16 518110
wst04-VHDL20_DWMG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:16 524679
wst04-VHDL20_DWMG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:22 521692
wst04-VHDL20_DWMG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:23 521335
wst04-VHDL20_DWMG_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:21 521187
wst04-VHDL20_DWMG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:26 515988
wst04-VHDL20_DWMO_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:22 423022
wst04-VHDL20_DWMO_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 423204
wst04-VHDL20_DWMO_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:12 423629
wst04-VHDL20_DWMO_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:16 421350
wst04-VHDL20_DWMO_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:22 419363
wst04-VHDL20_DWMO_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:17 419453
wst04-VHDL20_DWMO_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:21 420340
wst04-VHDL20_DWMO_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:20 421506
wst04-VHDL20_DWMP_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:22 545950
wst04-VHDL20_DWMP_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 544875
wst04-VHDL20_DWMP_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:22 545983
wst04-VHDL20_DWMP_170400_COR-2511170400-omedes-..> 17-Nov-2025 05:53:42 545983
wst04-VHDL20_DWMP_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:22 549410
wst04-VHDL20_DWMP_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:22 546986
wst04-VHDL20_DWMP_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:23 545550
wst04-VHDL20_DWMP_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:21 546991
wst04-VHDL20_DWMP_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:32 528896
wst04-VHDL20_DWPG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:12 323415
wst04-VHDL20_DWPG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:11 323356
wst04-VHDL20_DWPG_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:00:12 323269
wst04-VHDL20_DWPG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:12 369155
wst04-VHDL20_DWPG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:12 324102
wst04-VHDL20_DWPG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:13 324223
wst04-VHDL20_DWPG_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:00:12 323513
wst04-VHDL20_DWPG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:16 363845
wst04-VHDL20_DWPH_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:12 277819
wst04-VHDL20_DWPH_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:11 231956
wst04-VHDL20_DWPH_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:00:12 232411
wst04-VHDL20_DWPH_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:12 276072
wst04-VHDL20_DWPH_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:12 275808
wst04-VHDL20_DWPH_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:13 229918
wst04-VHDL20_DWPH_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:00:12 229652
wst04-VHDL20_DWPH_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:12 277638
wst04-VHDL20_DWSG_161800-2511161800-omedes--0.pdf 16-Nov-2025 19:45:12 322633
wst04-VHDL20_DWSG_170200-2511170200-omedes--0.pdf 17-Nov-2025 03:45:17 322839
wst04-VHDL20_DWSG_170400-2511170400-omedes--0.pdf 17-Nov-2025 06:15:16 322995
wst04-VHDL20_DWSG_170800-2511170800-omedes--0.pdf 17-Nov-2025 09:45:12 331312
wst04-VHDL20_DWSG_171300-2511171300-omedes--0.pdf 17-Nov-2025 14:45:12 331233
wst04-VHDL20_DWSG_171800-2511171800-omedes--0.pdf 17-Nov-2025 19:45:12 329534
wst04-VHDL20_DWSG_180200-2511180200-omedes--0.pdf 18-Nov-2025 03:45:17 329879
wst04-VHDL20_DWSG_180400-2511180400-omedes--0.pdf 18-Nov-2025 06:15:17 330979
wst04-VHDL20_DWSG_180800-2511180800-omedes--0.pdf 18-Nov-2025 09:45:12 321333
wst04-VHDL20_DWSG_181300-2511181300-omedes--0.pdf 18-Nov-2025 14:45:18 321162