Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_070600 07-Sep-2026 14:04:05 28463
FPDL13_DWMZ_080600 08-Sep-2026 14:47:10 16682
SXDL31_DWAV_070800 07-Sep-2026 08:44:29 11476
SXDL31_DWAV_071800 07-Sep-2026 15:34:51 5918
SXDL31_DWAV_080800 08-Sep-2026 07:27:44 7438
SXDL31_DWAV_081800 08-Sep-2026 16:28:23 9599
SXDL31_DWAV_LATEST 08-Sep-2026 16:28:23 9599
SXDL33_DWAV_070000 07-Sep-2026 09:48:24 6837
SXDL33_DWAV_080000 08-Sep-2026 09:25:20 5755
SXDL33_DWAV_LATEST 08-Sep-2026 09:25:20 5755
ber01-FWDL39_DWMS_071200-2609071200-dsw--0-ia5 07-Sep-2026 10:50:49 1212
ber01-FWDL39_DWMS_081200-2609081200-dsw--0-ia5 08-Sep-2026 10:59:28 1663
ber01-VHDL13_DWEG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:28:18 2881
ber01-VHDL13_DWEG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:28:19 2894
ber01-VHDL13_DWEH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:28:18 2695
ber01-VHDL13_DWEH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:28:19 3231
ber01-VHDL13_DWEI_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:28:18 3076
ber01-VHDL13_DWEI_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:28:19 2992
ber01-VHDL13_DWHG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 3526
ber01-VHDL13_DWHG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 3690
ber01-VHDL13_DWHH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 3464
ber01-VHDL13_DWHH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 3668
ber01-VHDL13_DWLG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 2378
ber01-VHDL13_DWLG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2532
ber01-VHDL13_DWLH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 2753
ber01-VHDL13_DWLH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2967
ber01-VHDL13_DWLI_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 2472
ber01-VHDL13_DWLI_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2710
ber01-VHDL13_DWMO_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 3539
ber01-VHDL13_DWMO_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 3127
ber01-VHDL13_DWMP_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 3409
ber01-VHDL13_DWMP_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 4142
ber01-VHDL13_DWOG_061700-2609061700-dsw--0-ia5 06-Sep-2026 18:34:56 3847
ber01-VHDL13_DWOG_070300-2609070300-dsw--0-ia5 07-Sep-2026 03:00:39 3762
ber01-VHDL13_DWOG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 3763
ber01-VHDL13_DWOG_071700-2609071700-dsw--0-ia5 07-Sep-2026 18:00:03 3732
ber01-VHDL13_DWOG_080300-2609080300-dsw--0-ia5 08-Sep-2026 03:00:52 4338
ber01-VHDL13_DWOG_080800-2609080800-dsw--0-ia5 08-Sep-2026 14:40:35 4577
ber01-VHDL13_DWOG_080800_COR-2609080800-dsw--0-ia5 08-Sep-2026 08:41:21 4690
ber01-VHDL13_DWOG_081700-2609081700-dsw--0-ia5 08-Sep-2026 18:00:04 4971
ber01-VHDL13_DWON_061834-2609061834-dsw--0-ia5 06-Sep-2026 18:34:48 4002
ber01-VHDL13_DWON_070051-2609070051-dsw--0-ia5 07-Sep-2026 00:51:40 4020
ber01-VHDL13_DWON_070242-2609070242-dsw--0-ia5 07-Sep-2026 02:43:25 4022
ber01-VHDL13_DWON_070243-2609070243-dsw--0-ia5 07-Sep-2026 02:44:17 4022
ber01-VHDL13_DWON_070527-2609070527-dsw--0-ia5 07-Sep-2026 05:27:29 4301
ber01-VHDL13_DWON_070621-2609070621-dsw--0-ia5 07-Sep-2026 06:21:48 4301
ber01-VHDL13_DWON_070842-2609070842-dsw--0-ia5 07-Sep-2026 08:42:49 4301
ber01-VHDL13_DWON_071505-2609071505-dsw--0-ia5 07-Sep-2026 15:05:43 3667
ber01-VHDL13_DWON_071536-2609071536-dsw--0-ia5 07-Sep-2026 15:36:08 3682
ber01-VHDL13_DWON_071707-2609071707-dsw--0-ia5 07-Sep-2026 17:07:59 3682
ber01-VHDL13_DWON_071836-2609071836-dsw--0-ia5 07-Sep-2026 18:37:03 3916
ber01-VHDL13_DWON_072102-2609072102-dsw--0-ia5 07-Sep-2026 21:02:48 3897
ber01-VHDL13_DWON_080001-2609080001-dsw--0-ia5 08-Sep-2026 00:01:29 4156
ber01-VHDL13_DWON_080140-2609080140-dsw--0-ia5 08-Sep-2026 01:40:33 4132
ber01-VHDL13_DWON_080249-2609080249-dsw--0-ia5 08-Sep-2026 02:50:37 4116
ber01-VHDL13_DWON_080315-2609080315-dsw--0-ia5 08-Sep-2026 03:16:06 4122
ber01-VHDL13_DWON_080526-2609080526-dsw--0-ia5 08-Sep-2026 05:26:19 4547
ber01-VHDL13_DWON_080619-2609080619-dsw--0-ia5 08-Sep-2026 06:19:09 4547
ber01-VHDL13_DWON_080806-2609080806-dsw--0-ia5 08-Sep-2026 08:06:39 4547
ber01-VHDL13_DWON_080840-2609080840-dsw--0-ia5 08-Sep-2026 08:40:29 4551
ber01-VHDL13_DWON_081438-2609081438-dsw--0-ia5 08-Sep-2026 14:38:40 3430
ber01-VHDL13_DWON_081713-2609081713-dsw--0-ia5 08-Sep-2026 17:14:05 3831
ber01-VHDL13_DWPG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 2450
ber01-VHDL13_DWPG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2485
ber01-VHDL13_DWPH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 2633
ber01-VHDL13_DWPH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2766
ber01-VHDL13_DWSG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 3416
ber01-VHDL13_DWSG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:11 3669
ber01-VHDL17_DWOG_071200-2609071200-dsw--0-ia5 07-Sep-2026 11:52:32 2715
ber01-VHDL17_DWOG_081200-2609081200-dsw--0-ia5 08-Sep-2026 10:54:44 2165
swis2-VHDL20_DWEG_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1306
swis2-VHDL20_DWEG_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:01:23 1102
swis2-VHDL20_DWEG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 1298
swis2-VHDL20_DWEG_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:05 1405
swis2-VHDL20_DWEG_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1094
swis2-VHDL20_DWEG_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:01:16 1105
swis2-VHDL20_DWEG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:11 1292
swis2-VHDL20_DWEG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1227
swis2-VHDL20_DWEH_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1179
swis2-VHDL20_DWEH_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:01:23 941
swis2-VHDL20_DWEH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 1128
swis2-VHDL20_DWEH_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:05 1599
swis2-VHDL20_DWEH_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1239
swis2-VHDL20_DWEH_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:01:16 1237
swis2-VHDL20_DWEH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:11 1600
swis2-VHDL20_DWEH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1537
swis2-VHDL20_DWEI_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1330
swis2-VHDL20_DWEI_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:01:23 1126
swis2-VHDL20_DWEI_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 1322
swis2-VHDL20_DWEI_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:05 1370
swis2-VHDL20_DWEI_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1104
swis2-VHDL20_DWEI_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:01:16 1115
swis2-VHDL20_DWEI_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:11 1302
swis2-VHDL20_DWEI_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1209
swis2-VHDL20_DWHG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:45:17 1385
swis2-VHDL20_DWHG_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:45:56 1243
swis2-VHDL20_DWHG_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:19 1234
swis2-VHDL20_DWHG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:45:47 1789
swis2-VHDL20_DWHG_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:45:08 1804
swis2-VHDL20_DWHG_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:46:07 1743
swis2-VHDL20_DWHG_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:19 1758
swis2-VHDL20_DWHG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:45:32 1858
swis2-VHDL20_DWHH_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:45:17 1362
swis2-VHDL20_DWHH_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:45:56 1234
swis2-VHDL20_DWHH_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:19 1234
swis2-VHDL20_DWHH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:45:47 1802
swis2-VHDL20_DWHH_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:45:08 1820
swis2-VHDL20_DWHH_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:46:07 1650
swis2-VHDL20_DWHH_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:19 1708
swis2-VHDL20_DWHH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:45:32 1861
swis2-VHDL20_DWLG_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:24 995
swis2-VHDL20_DWLG_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 985
swis2-VHDL20_DWLG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:23 1102
swis2-VHDL20_DWLG_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:31:14 1098
swis2-VHDL20_DWLG_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:24 949
swis2-VHDL20_DWLG_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:13 913
swis2-VHDL20_DWLG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1066
swis2-VHDL20_DWLG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 986
swis2-VHDL20_DWLH_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:24 1245
swis2-VHDL20_DWLH_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 1163
swis2-VHDL20_DWLH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:23 1301
swis2-VHDL20_DWLH_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:31:14 1554
swis2-VHDL20_DWLH_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:24 1561
swis2-VHDL20_DWLH_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:13 1349
swis2-VHDL20_DWLH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1465
swis2-VHDL20_DWLH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1382
swis2-VHDL20_DWLI_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:24 1021
swis2-VHDL20_DWLI_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 998
swis2-VHDL20_DWLI_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:23 1116
swis2-VHDL20_DWLI_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:31:14 1340
swis2-VHDL20_DWLI_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:24 1200
swis2-VHDL20_DWLI_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:13 1166
swis2-VHDL20_DWLI_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1283
swis2-VHDL20_DWLI_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1008
swis2-VHDL20_DWMO_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1548
swis2-VHDL20_DWMO_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:03 1550
swis2-VHDL20_DWMO_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 1603
swis2-VHDL20_DWMO_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:03 1802
swis2-VHDL20_DWMO_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1442
swis2-VHDL20_DWMO_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:03 1444
swis2-VHDL20_DWMO_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1496
swis2-VHDL20_DWMO_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1588
swis2-VHDL20_DWMP_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1548
swis2-VHDL20_DWMP_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:03 1546
swis2-VHDL20_DWMP_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:11 1837
swis2-VHDL20_DWMP_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:03 2075
swis2-VHDL20_DWMP_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1806
swis2-VHDL20_DWMP_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:03 2138
swis2-VHDL20_DWMP_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 2152
swis2-VHDL20_DWMP_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 2075
swis2-VHDL20_DWPG_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:24 1099
swis2-VHDL20_DWPG_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 1078
swis2-VHDL20_DWPG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:23 1195
swis2-VHDL20_DWPG_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:31:14 1220
swis2-VHDL20_DWPG_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:29 1312
swis2-VHDL20_DWPG_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:13 1018
swis2-VHDL20_DWPG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1134
swis2-VHDL20_DWPG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1103
swis2-VHDL20_DWPH_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:24 1072
swis2-VHDL20_DWPH_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 1052
swis2-VHDL20_DWPH_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:23 1172
swis2-VHDL20_DWPH_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:31:14 1614
swis2-VHDL20_DWPH_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:24 1349
swis2-VHDL20_DWPH_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:13 1157
swis2-VHDL20_DWPH_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:21 1276
swis2-VHDL20_DWPH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1358
swis2-VHDL20_DWSG_070200-2609070200-dsw--0-ia5 07-Sep-2026 02:30:06 1591
swis2-VHDL20_DWSG_070400-2609070400-dsw--0-ia5 07-Sep-2026 05:00:13 1535
swis2-VHDL20_DWSG_070800-2609070800-dsw--0-ia5 07-Sep-2026 08:30:05 1679
swis2-VHDL20_DWSG_071800-2609071800-dsw--0-ia5 07-Sep-2026 18:30:03 1917
swis2-VHDL20_DWSG_080200-2609080200-dsw--0-ia5 08-Sep-2026 02:30:04 1818
swis2-VHDL20_DWSG_080400-2609080400-dsw--0-ia5 08-Sep-2026 05:00:19 1815
swis2-VHDL20_DWSG_080800-2609080800-dsw--0-ia5 08-Sep-2026 08:30:11 2039
swis2-VHDL20_DWSG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:17 1820
wst04-VHDL20_DWEG_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:14 243634
wst04-VHDL20_DWEG_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:13 243494
wst04-VHDL20_DWEG_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:15 244437
wst04-VHDL20_DWEG_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:13 248591
wst04-VHDL20_DWEG_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:14 247032
wst04-VHDL20_DWEG_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:15 247118
wst04-VHDL20_DWEG_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 247712
wst04-VHDL20_DWEG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 244419
wst04-VHDL20_DWEH_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:14 243089
wst04-VHDL20_DWEH_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:13 242507
wst04-VHDL20_DWEH_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:15 243477
wst04-VHDL20_DWEH_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:13 244516
wst04-VHDL20_DWEH_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:14 242778
wst04-VHDL20_DWEH_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:15 243608
wst04-VHDL20_DWEH_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 244786
wst04-VHDL20_DWEH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 244660
wst04-VHDL20_DWEI_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:21 352002
wst04-VHDL20_DWEI_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:19 351876
wst04-VHDL20_DWEI_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:15 352976
wst04-VHDL20_DWEI_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:19 355703
wst04-VHDL20_DWEI_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:18 354084
wst04-VHDL20_DWEI_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:15 354153
wst04-VHDL20_DWEI_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 354931
wst04-VHDL20_DWEI_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 350350
wst04-VHDL20_DWHG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:45:25 341204
wst04-VHDL20_DWHG_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:45:56 340156
wst04-VHDL20_DWHG_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:19 339947
wst04-VHDL20_DWHG_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:45:50 342290
wst04-VHDL20_DWHG_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:45:14 354304
wst04-VHDL20_DWHG_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:46:07 353951
wst04-VHDL20_DWHG_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:19 354031
wst04-VHDL20_DWHG_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:45:36 354823
wst04-VHDL20_DWHH_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:45:25 334003
wst04-VHDL20_DWHH_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:45:56 333416
wst04-VHDL20_DWHH_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:19 234660
wst04-VHDL20_DWHH_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:45:50 335436
wst04-VHDL20_DWHH_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:45:14 340089
wst04-VHDL20_DWHH_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:46:07 338779
wst04-VHDL20_DWHH_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:19 236661
wst04-VHDL20_DWHH_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:45:36 339774
wst04-VHDL20_DWLG_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:31 333316
wst04-VHDL20_DWLG_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:43 332886
wst04-VHDL20_DWLG_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:49 333096
wst04-VHDL20_DWLG_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:31:33 333896
wst04-VHDL20_DWLG_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:24 334487
wst04-VHDL20_DWLG_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:43 333691
wst04-VHDL20_DWLG_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:44 333911
wst04-VHDL20_DWLG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 332551
wst04-VHDL20_DWLH_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:24 337096
wst04-VHDL20_DWLH_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:43 336635
wst04-VHDL20_DWLH_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:51 336901
wst04-VHDL20_DWLH_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:31:33 343184
wst04-VHDL20_DWLH_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:24 343320
wst04-VHDL20_DWLH_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:43 342152
wst04-VHDL20_DWLH_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:44 342387
wst04-VHDL20_DWLH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 337871
wst04-VHDL20_DWLI_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:24 333683
wst04-VHDL20_DWLI_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:43 333234
wst04-VHDL20_DWLI_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:49 378042
wst04-VHDL20_DWLI_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:31:35 341928
wst04-VHDL20_DWLI_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:24 342023
wst04-VHDL20_DWLI_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:43 341214
wst04-VHDL20_DWLI_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:49 386029
wst04-VHDL20_DWLI_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 338386
wst04-VHDL20_DWMO_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:14 448224
wst04-VHDL20_DWMO_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:13 448431
wst04-VHDL20_DWMO_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:19 447954
wst04-VHDL20_DWMO_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:19 353547
wst04-VHDL20_DWMO_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:14 457710
wst04-VHDL20_DWMO_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:13 457498
wst04-VHDL20_DWMO_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 457529
wst04-VHDL20_DWMO_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 350559
wst04-VHDL20_DWMP_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:21 557762
wst04-VHDL20_DWMP_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:19 557891
wst04-VHDL20_DWMP_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:23 456290
wst04-VHDL20_DWMP_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:19 461630
wst04-VHDL20_DWMP_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:20 565490
wst04-VHDL20_DWMP_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:19 566708
wst04-VHDL20_DWMP_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 462014
wst04-VHDL20_DWMP_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 467840
wst04-VHDL20_DWPG_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:24 239742
wst04-VHDL20_DWPG_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:33 336761
wst04-VHDL20_DWPG_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:49 381508
wst04-VHDL20_DWPG_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:31:33 348790
wst04-VHDL20_DWPG_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:29 245950
wst04-VHDL20_DWPG_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:33 348647
wst04-VHDL20_DWPG_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:44 393395
wst04-VHDL20_DWPG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:33 339733
wst04-VHDL20_DWPH_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:24 241698
wst04-VHDL20_DWPH_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:33 241311
wst04-VHDL20_DWPH_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:49 241482
wst04-VHDL20_DWPH_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:31:33 247191
wst04-VHDL20_DWPH_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:24 247881
wst04-VHDL20_DWPH_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:33 246621
wst04-VHDL20_DWPH_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:44 246849
wst04-VHDL20_DWPH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 243161
wst04-VHDL20_DWSG_070200-2609070200-omedes--0.pdf 07-Sep-2026 02:30:14 349581
wst04-VHDL20_DWSG_070400-2609070400-omedes--0.pdf 07-Sep-2026 05:00:13 349144
wst04-VHDL20_DWSG_070800-2609070800-omedes--0.pdf 07-Sep-2026 08:30:19 350140
wst04-VHDL20_DWSG_071800-2609071800-omedes--0.pdf 07-Sep-2026 18:30:15 350268
wst04-VHDL20_DWSG_080200-2609080200-omedes--0.pdf 08-Sep-2026 02:30:14 349879
wst04-VHDL20_DWSG_080400-2609080400-omedes--0.pdf 08-Sep-2026 05:00:13 349480
wst04-VHDL20_DWSG_080800-2609080800-omedes--0.pdf 08-Sep-2026 08:30:21 349553
wst04-VHDL20_DWSG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 351499