Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Dec-2025 17:18:58 5037
FPDL13_DWMZ_300600 30-Nov-2025 12:33:17 2854
SXDL31_DWAV_010800 01-Dec-2025 08:40:30 11585
SXDL31_DWAV_011800 01-Dec-2025 16:58:44 7934
SXDL31_DWAV_300800 30-Nov-2025 08:34:11 7285
SXDL31_DWAV_301800 30-Nov-2025 18:01:05 7989
SXDL31_DWAV_LATEST 01-Dec-2025 16:58:44 7934
SXDL33_DWAV_010000 01-Dec-2025 11:12:19 8361
SXDL33_DWAV_300000 30-Nov-2025 11:12:49 11246
SXDL33_DWAV_LATEST 01-Dec-2025 11:12:19 8361
ber01-FWDL39_DWMS_011230-2512011230-dsw--0-ia5 01-Dec-2025 13:36:15 1166
ber01-FWDL39_DWMS_011230_COR-2512011230-dsw--0-ia5 01-Dec-2025 13:51:41 1240
ber01-FWDL39_DWMS_301230-2511301230-dsw--0-ia5 30-Nov-2025 13:19:57 1364
ber01-VHDL13_DWEH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:28:13 3103
ber01-VHDL13_DWEH_010400-2512010400-dsw--0-ia5 01-Dec-2025 05:58:17 3106
ber01-VHDL13_DWEH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:17 3102
ber01-VHDL13_DWEH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:17 2485
ber01-VHDL13_DWEH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:28:13 2790
ber01-VHDL13_DWEH_300400-2511300400-dsw--0-ia5 30-Nov-2025 05:58:11 3074
ber01-VHDL13_DWEH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:28:16 3062
ber01-VHDL13_DWEH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:28:17 3046
ber01-VHDL13_DWHG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:07 2758
ber01-VHDL13_DWHG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:07 2758
ber01-VHDL13_DWHG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2908
ber01-VHDL13_DWHG_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:55:26 3161
ber01-VHDL13_DWHG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:09 2964
ber01-VHDL13_DWHG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2911
ber01-VHDL13_DWHG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:07 3064
ber01-VHDL13_DWHG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 3257
ber01-VHDL13_DWHG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:06 2844
ber01-VHDL13_DWHH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:07 2613
ber01-VHDL13_DWHH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:07 2589
ber01-VHDL13_DWHH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2683
ber01-VHDL13_DWHH_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:54:41 2743
ber01-VHDL13_DWHH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:09 2551
ber01-VHDL13_DWHH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 3090
ber01-VHDL13_DWHH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:07 3164
ber01-VHDL13_DWHH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 3260
ber01-VHDL13_DWHH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:06 2824
ber01-VHDL13_DWLG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2713
ber01-VHDL13_DWLG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2463
ber01-VHDL13_DWLG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2799
ber01-VHDL13_DWLG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2510
ber01-VHDL13_DWLG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2644
ber01-VHDL13_DWLG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2331
ber01-VHDL13_DWLG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 2328
ber01-VHDL13_DWLG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2253
ber01-VHDL13_DWLH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2586
ber01-VHDL13_DWLH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2373
ber01-VHDL13_DWLH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2259
ber01-VHDL13_DWLH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2174
ber01-VHDL13_DWLH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2485
ber01-VHDL13_DWLH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2394
ber01-VHDL13_DWLH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 2213
ber01-VHDL13_DWLH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2279
ber01-VHDL13_DWLI_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2722
ber01-VHDL13_DWLI_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2515
ber01-VHDL13_DWLI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2699
ber01-VHDL13_DWLI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2671
ber01-VHDL13_DWLI_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2568
ber01-VHDL13_DWLI_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2526
ber01-VHDL13_DWLI_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 2493
ber01-VHDL13_DWLI_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2568
ber01-VHDL13_DWMG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2708
ber01-VHDL13_DWMG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2515
ber01-VHDL13_DWMG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2531
ber01-VHDL13_DWMG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2199
ber01-VHDL13_DWMG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:02 2822
ber01-VHDL13_DWMG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2824
ber01-VHDL13_DWMG_300800-2511300800-dsw--0-ia5 30-Nov-2025 12:26:31 3123
ber01-VHDL13_DWMG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2798
ber01-VHDL13_DWMO_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2352
ber01-VHDL13_DWMO_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2403
ber01-VHDL13_DWMO_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2403
ber01-VHDL13_DWMO_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2063
ber01-VHDL13_DWMO_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:02 2536
ber01-VHDL13_DWMO_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2449
ber01-VHDL13_DWMO_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:02 2673
ber01-VHDL13_DWMO_300800_COR-2511300800-dsw--0-ia5 30-Nov-2025 12:34:02 2894
ber01-VHDL13_DWMO_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2404
ber01-VHDL13_DWMP_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2511
ber01-VHDL13_DWMP_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2482
ber01-VHDL13_DWMP_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 2482
ber01-VHDL13_DWMP_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2282
ber01-VHDL13_DWMP_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:02 2728
ber01-VHDL13_DWMP_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2693
ber01-VHDL13_DWMP_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:02 2506
ber01-VHDL13_DWMP_300800_COR-2511300800-dsw--0-ia5 30-Nov-2025 12:30:33 2715
ber01-VHDL13_DWMP_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2530
ber01-VHDL13_DWOG_010300-2512010300-dsw--0-ia5 01-Dec-2025 04:00:08 4315
ber01-VHDL13_DWOG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:03 5327
ber01-VHDL13_DWOG_011700-2512011700-dsw--0-ia5 01-Dec-2025 19:00:01 4923
ber01-VHDL13_DWOG_300300-2511300300-dsw--0-ia5 30-Nov-2025 04:00:01 4535
ber01-VHDL13_DWOG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:02 4494
ber01-VHDL13_DWOG_301700-2511301700-dsw--0-ia5 30-Nov-2025 19:00:00 4269
ber01-VHDL13_DWOH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:28:13 2913
ber01-VHDL13_DWOH_010400-2512010400-dsw--0-ia5 01-Dec-2025 05:58:13 2826
ber01-VHDL13_DWOH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:17 2783
ber01-VHDL13_DWOH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:17 2569
ber01-VHDL13_DWOH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:28:13 2662
ber01-VHDL13_DWOH_300400-2511300400-dsw--0-ia5 30-Nov-2025 05:58:17 2746
ber01-VHDL13_DWOH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:28:16 2994
ber01-VHDL13_DWOH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:28:17 2815
ber01-VHDL13_DWOI_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:28:13 3056
ber01-VHDL13_DWOI_010400-2512010400-dsw--0-ia5 01-Dec-2025 05:58:17 2963
ber01-VHDL13_DWOI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:28:11 2948
ber01-VHDL13_DWOI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:28:11 2950
ber01-VHDL13_DWOI_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:28:13 2897
ber01-VHDL13_DWOI_300400-2511300400-dsw--0-ia5 30-Nov-2025 05:58:17 2932
ber01-VHDL13_DWOI_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:28:12 3076
ber01-VHDL13_DWOI_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:28:11 2988
ber01-VHDL13_DWON_010122-2512010122-dsw--0-ia5 01-Dec-2025 01:22:07 3722
ber01-VHDL13_DWON_010617-2512010617-dsw--0-ia5 01-Dec-2025 06:18:01 3919
ber01-VHDL13_DWON_010734-2512010734-dsw--0-ia5 01-Dec-2025 07:34:18 4393
ber01-VHDL13_DWON_010736-2512010736-dsw--0-ia5 01-Dec-2025 07:36:42 4548
ber01-VHDL13_DWON_010741-2512010741-dsw--0-ia5 01-Dec-2025 07:41:07 4569
ber01-VHDL13_DWON_010927-2512010927-dsw--0-ia5 01-Dec-2025 09:27:57 4569
ber01-VHDL13_DWON_011244-2512011244-dsw--0-ia5 01-Dec-2025 12:44:47 4514
ber01-VHDL13_DWON_011519-2512011519-dsw--0-ia5 01-Dec-2025 15:19:52 3831
ber01-VHDL13_DWON_011737-2512011737-dsw--0-ia5 01-Dec-2025 17:37:48 4061
ber01-VHDL13_DWON_011930-2512011930-dsw--0-ia5 01-Dec-2025 19:30:29 4032
ber01-VHDL13_DWON_020001-2512020001-dsw--0-ia5 02-Dec-2025 00:01:23 4691
ber01-VHDL13_DWON_020140-2512020140-dsw--0-ia5 02-Dec-2025 01:41:01 4657
ber01-VHDL13_DWON_300353-2511300353-dsw--0-ia5 30-Nov-2025 03:53:13 3710
ber01-VHDL13_DWON_300553-2511300553-dsw--0-ia5 30-Nov-2025 05:53:56 4191
ber01-VHDL13_DWON_300732-2511300732-dsw--0-ia5 30-Nov-2025 07:32:22 4191
ber01-VHDL13_DWON_301457-2511301457-dsw--0-ia5 30-Nov-2025 14:57:36 4194
ber01-VHDL13_DWON_301842-2511301842-dsw--0-ia5 30-Nov-2025 18:42:37 4147
ber01-VHDL13_DWPG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2153
ber01-VHDL13_DWPG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2153
ber01-VHDL13_DWPG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2122
ber01-VHDL13_DWPG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 1790
ber01-VHDL13_DWPG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2577
ber01-VHDL13_DWPG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2384
ber01-VHDL13_DWPG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 2383
ber01-VHDL13_DWPG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2150
ber01-VHDL13_DWPH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2236
ber01-VHDL13_DWPH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:01 2253
ber01-VHDL13_DWPH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2196
ber01-VHDL13_DWPH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 1961
ber01-VHDL13_DWPH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:06 2459
ber01-VHDL13_DWPH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:01 2405
ber01-VHDL13_DWPH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:16 2442
ber01-VHDL13_DWPH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2175
ber01-VHDL13_DWSG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:30:01 2600
ber01-VHDL13_DWSG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:07 2995
ber01-VHDL13_DWSG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:30:08 2965
ber01-VHDL13_DWSG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:30:02 2626
ber01-VHDL13_DWSG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:30:02 2925
ber01-VHDL13_DWSG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:08 2880
ber01-VHDL13_DWSG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:30:02 3089
ber01-VHDL13_DWSG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:30:02 2727
ber01-VHDL17_DWOG_011200-2512011200-dsw--0-ia5 01-Dec-2025 12:03:58 3996
ber01-VHDL17_DWOG_301200-2511301200-dsw--0-ia5 30-Nov-2025 12:35:34 4420
swis2-VHDL20_DWEG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3278
swis2-VHDL20_DWEG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 3386
swis2-VHDL20_DWEG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3550
swis2-VHDL20_DWEG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3094
swis2-VHDL20_DWEG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 2940
swis2-VHDL20_DWEG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3155
swis2-VHDL20_DWEG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3798
swis2-VHDL20_DWEG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 3230
swis2-VHDL20_DWEH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3581
swis2-VHDL20_DWEH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 3612
swis2-VHDL20_DWEH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3838
swis2-VHDL20_DWEH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3025
swis2-VHDL20_DWEH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3113
swis2-VHDL20_DWEH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3535
swis2-VHDL20_DWEH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3893
swis2-VHDL20_DWEH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 3556
swis2-VHDL20_DWEI_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3406
swis2-VHDL20_DWEI_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 3580
swis2-VHDL20_DWEI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3772
swis2-VHDL20_DWEI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3499
swis2-VHDL20_DWEI_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3191
swis2-VHDL20_DWEI_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3340
swis2-VHDL20_DWEI_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3921
swis2-VHDL20_DWEI_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 3396
swis2-VHDL20_DWHG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2944
swis2-VHDL20_DWHG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:07 2941
swis2-VHDL20_DWHG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3550
swis2-VHDL20_DWHG_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:57:51 3803
swis2-VHDL20_DWHG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3147
swis2-VHDL20_DWHG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3097
swis2-VHDL20_DWHG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:07 3247
swis2-VHDL20_DWHG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3921
swis2-VHDL20_DWHG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:06 3027
swis2-VHDL20_DWHH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2799
swis2-VHDL20_DWHH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:07 2775
swis2-VHDL20_DWHH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3225
swis2-VHDL20_DWHH_010800_COR-2512010800-dsw--0-ia5 01-Dec-2025 13:56:57 3285
swis2-VHDL20_DWHH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2737
swis2-VHDL20_DWHH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:08 3350
swis2-VHDL20_DWHH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3802
swis2-VHDL20_DWHH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:06 3010
swis2-VHDL20_DWLG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3131
swis2-VHDL20_DWLG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:11 2842
swis2-VHDL20_DWLG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3341
swis2-VHDL20_DWLG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2910
swis2-VHDL20_DWLG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 3198
swis2-VHDL20_DWLG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:13 2675
swis2-VHDL20_DWLG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 2874
swis2-VHDL20_DWLG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2668
swis2-VHDL20_DWLH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2987
swis2-VHDL20_DWLH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:11 2766
swis2-VHDL20_DWLH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2812
swis2-VHDL20_DWLH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2581
swis2-VHDL20_DWLH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 2840
swis2-VHDL20_DWLH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:13 2814
swis2-VHDL20_DWLH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 2834
swis2-VHDL20_DWLH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2677
swis2-VHDL20_DWLI_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3118
swis2-VHDL20_DWLI_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:11 2903
swis2-VHDL20_DWLI_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3242
swis2-VHDL20_DWLI_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3073
swis2-VHDL20_DWLI_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 2918
swis2-VHDL20_DWLI_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:13 2934
swis2-VHDL20_DWLI_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3097
swis2-VHDL20_DWLI_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2961
swis2-VHDL20_DWMG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3185
swis2-VHDL20_DWMG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 2935
swis2-VHDL20_DWMG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 3087
swis2-VHDL20_DWMG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2587
swis2-VHDL20_DWMG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3298
swis2-VHDL20_DWMG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3360
swis2-VHDL20_DWMG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3607
swis2-VHDL20_DWMG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:06 3310
swis2-VHDL20_DWMO_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2820
swis2-VHDL20_DWMO_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 2827
swis2-VHDL20_DWMO_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 2969
swis2-VHDL20_DWMO_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2455
swis2-VHDL20_DWMO_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3052
swis2-VHDL20_DWMO_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 2942
swis2-VHDL20_DWMO_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3332
swis2-VHDL20_DWMO_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:06 2853
swis2-VHDL20_DWMP_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2948
swis2-VHDL20_DWMP_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 2902
swis2-VHDL20_DWMP_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:02 2985
swis2-VHDL20_DWMP_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:06 2674
swis2-VHDL20_DWMP_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:06 3150
swis2-VHDL20_DWMP_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3119
swis2-VHDL20_DWMP_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3130
swis2-VHDL20_DWMP_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2939
swis2-VHDL20_DWPG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2563
swis2-VHDL20_DWPG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:11 2526
swis2-VHDL20_DWPG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2629
swis2-VHDL20_DWPG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2304
swis2-VHDL20_DWPG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 3115
swis2-VHDL20_DWPG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:13 2896
swis2-VHDL20_DWPG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3070
swis2-VHDL20_DWPG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2711
swis2-VHDL20_DWPH_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 2618
swis2-VHDL20_DWPH_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:00:11 2686
swis2-VHDL20_DWPH_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 2761
swis2-VHDL20_DWPH_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 2475
swis2-VHDL20_DWPH_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 2787
swis2-VHDL20_DWPH_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:00:13 2919
swis2-VHDL20_DWPH_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:07 3088
swis2-VHDL20_DWPH_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 2689
swis2-VHDL20_DWSG_010200-2512010200-dsw--0-ia5 01-Dec-2025 03:45:07 3117
swis2-VHDL20_DWSG_010400-2512010400-dsw--0-ia5 01-Dec-2025 06:15:02 3406
swis2-VHDL20_DWSG_010800-2512010800-dsw--0-ia5 01-Dec-2025 09:45:06 3576
swis2-VHDL20_DWSG_011300-2512011300-dsw--0-ia5 01-Dec-2025 14:45:04 3404
swis2-VHDL20_DWSG_011800-2512011800-dsw--0-ia5 01-Dec-2025 19:45:02 3034
swis2-VHDL20_DWSG_300200-2511300200-dsw--0-ia5 30-Nov-2025 03:45:01 3333
swis2-VHDL20_DWSG_300400-2511300400-dsw--0-ia5 30-Nov-2025 06:15:02 3296
swis2-VHDL20_DWSG_300800-2511300800-dsw--0-ia5 30-Nov-2025 09:45:03 3841
swis2-VHDL20_DWSG_301300-2511301300-dsw--0-ia5 30-Nov-2025 14:45:02 3722
swis2-VHDL20_DWSG_301800-2511301800-dsw--0-ia5 30-Nov-2025 19:45:04 3247
wst04-VHDL20_DWEG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:17 229461
wst04-VHDL20_DWEG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:26 229329
wst04-VHDL20_DWEG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 226293
wst04-VHDL20_DWEG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 223788
wst04-VHDL20_DWEG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:16 229948
wst04-VHDL20_DWEG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:21 229926
wst04-VHDL20_DWEG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:21 230668
wst04-VHDL20_DWEG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:12 228534
wst04-VHDL20_DWEH_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:17 224784
wst04-VHDL20_DWEH_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:22 224786
wst04-VHDL20_DWEH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 225613
wst04-VHDL20_DWEH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 224144
wst04-VHDL20_DWEH_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:16 234371
wst04-VHDL20_DWEH_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:21 234467
wst04-VHDL20_DWEH_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:21 225896
wst04-VHDL20_DWEH_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:12 224312
wst04-VHDL20_DWEI_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:17 319058
wst04-VHDL20_DWEI_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:26 319204
wst04-VHDL20_DWEI_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:22 313146
wst04-VHDL20_DWEI_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 313430
wst04-VHDL20_DWEI_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:12 324857
wst04-VHDL20_DWEI_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:27 325080
wst04-VHDL20_DWEI_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:27 320771
wst04-VHDL20_DWEI_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:18 319262
wst04-VHDL20_DWHG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:11 310975
wst04-VHDL20_DWHG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:11 311028
wst04-VHDL20_DWHG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:16 305173
wst04-VHDL20_DWHG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 303931
wst04-VHDL20_DWHG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:12 317658
wst04-VHDL20_DWHG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:13 317767
wst04-VHDL20_DWHG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:17 312256
wst04-VHDL20_DWHG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:22 310854
wst04-VHDL20_DWHH_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:11 300317
wst04-VHDL20_DWHH_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:11 300380
wst04-VHDL20_DWHH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:12 294158
wst04-VHDL20_DWHH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:18 293375
wst04-VHDL20_DWHH_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:12 304578
wst04-VHDL20_DWHH_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:13 304585
wst04-VHDL20_DWHH_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:11 301854
wst04-VHDL20_DWHH_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:22 300574
wst04-VHDL20_DWLG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:21 311528
wst04-VHDL20_DWLG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:42 311321
wst04-VHDL20_DWLG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:26 301799
wst04-VHDL20_DWLG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:26 300768
wst04-VHDL20_DWLG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:26 322473
wst04-VHDL20_DWLG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:40 321987
wst04-VHDL20_DWLG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:31 312522
wst04-VHDL20_DWLG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:22 311683
wst04-VHDL20_DWLH_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:25 315087
wst04-VHDL20_DWLH_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:42 314216
wst04-VHDL20_DWLH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 307555
wst04-VHDL20_DWLH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 307239
wst04-VHDL20_DWLH_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:20 323785
wst04-VHDL20_DWLH_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:40 323532
wst04-VHDL20_DWLH_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:31 314555
wst04-VHDL20_DWLH_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:26 314596
wst04-VHDL20_DWLI_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:21 311808
wst04-VHDL20_DWLI_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:42 311048
wst04-VHDL20_DWLI_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 306103
wst04-VHDL20_DWLI_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 305681
wst04-VHDL20_DWLI_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:26 314390
wst04-VHDL20_DWLI_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:40 314653
wst04-VHDL20_DWLI_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:31 312569
wst04-VHDL20_DWLI_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:22 311331
wst04-VHDL20_DWMG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:23 502541
wst04-VHDL20_DWMG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:22 501840
wst04-VHDL20_DWMG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 491703
wst04-VHDL20_DWMG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 490658
wst04-VHDL20_DWMG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:22 514089
wst04-VHDL20_DWMG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:17 514285
wst04-VHDL20_DWMG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:27 503169
wst04-VHDL20_DWMG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:16 502162
wst04-VHDL20_DWMO_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:17 405319
wst04-VHDL20_DWMO_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:16 405759
wst04-VHDL20_DWMO_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 391651
wst04-VHDL20_DWMO_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 389727
wst04-VHDL20_DWMO_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:22 416477
wst04-VHDL20_DWMO_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:21 416936
wst04-VHDL20_DWMO_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:17 406036
wst04-VHDL20_DWMO_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:16 404715
wst04-VHDL20_DWMP_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:23 532738
wst04-VHDL20_DWMP_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:16 533927
wst04-VHDL20_DWMP_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:18 523370
wst04-VHDL20_DWMP_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:16 522408
wst04-VHDL20_DWMP_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:16 542124
wst04-VHDL20_DWMP_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:21 543153
wst04-VHDL20_DWMP_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:21 534453
wst04-VHDL20_DWMP_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:16 533735
wst04-VHDL20_DWPG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:25 313160
wst04-VHDL20_DWPG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:31 312177
wst04-VHDL20_DWPG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:32 354363
wst04-VHDL20_DWPG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:26 309133
wst04-VHDL20_DWPG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:26 320760
wst04-VHDL20_DWPG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:31 320316
wst04-VHDL20_DWPG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:27 358459
wst04-VHDL20_DWPG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:22 313046
wst04-VHDL20_DWPH_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:21 223107
wst04-VHDL20_DWPH_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:00:31 222842
wst04-VHDL20_DWPH_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:26 267301
wst04-VHDL20_DWPH_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:22 266784
wst04-VHDL20_DWPH_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:20 227748
wst04-VHDL20_DWPH_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:00:31 228081
wst04-VHDL20_DWPH_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:31 268705
wst04-VHDL20_DWPH_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:26 267725
wst04-VHDL20_DWSG_010200-2512010200-omedes--0.pdf 01-Dec-2025 03:45:11 328960
wst04-VHDL20_DWSG_010400-2512010400-omedes--0.pdf 01-Dec-2025 06:15:12 329302
wst04-VHDL20_DWSG_010800-2512010800-omedes--0.pdf 01-Dec-2025 09:45:12 333237
wst04-VHDL20_DWSG_011300-2512011300-omedes--0.pdf 01-Dec-2025 14:45:11 333186
wst04-VHDL20_DWSG_011800-2512011800-omedes--0.pdf 01-Dec-2025 19:45:12 332442
wst04-VHDL20_DWSG_300200-2511300200-omedes--0.pdf 30-Nov-2025 03:45:16 343295
wst04-VHDL20_DWSG_300400-2511300400-omedes--0.pdf 30-Nov-2025 06:15:11 343469
wst04-VHDL20_DWSG_300800-2511300800-omedes--0.pdf 30-Nov-2025 09:45:13 329935
wst04-VHDL20_DWSG_301300-2511301300-omedes--0.pdf 30-Nov-2025 14:45:14 329932
wst04-VHDL20_DWSG_301800-2511301800-omedes--0.pdf 30-Nov-2025 19:45:12 328410