Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_160600 16-Aug-2026 12:13:05 2919
FPDL13_DWMZ_170600 17-Aug-2026 12:55:45 4530
SXDL31_DWAV_160800 16-Aug-2026 08:29:35 8701
SXDL31_DWAV_161800 16-Aug-2026 16:47:36 8712
SXDL31_DWAV_170800 17-Aug-2026 07:28:45 6832
SXDL31_DWAV_171800 17-Aug-2026 16:33:14 9469
SXDL31_DWAV_LATEST 17-Aug-2026 16:33:14 9469
SXDL33_DWAV_160000 16-Aug-2026 09:47:53 15407
SXDL33_DWAV_170000 17-Aug-2026 10:10:33 17646
SXDL33_DWAV_LATEST 17-Aug-2026 10:10:33 17646
ber01-FWDL39_DWMS_161200-2608161200-dsw--0-ia5 16-Aug-2026 12:20:08 1390
ber01-FWDL39_DWMS_171200-2608171200-dsw--0-ia5 17-Aug-2026 11:05:58 1580
ber01-VHDL13_DWEG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 3375
ber01-VHDL13_DWEG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2374
ber01-VHDL13_DWEH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 2440
ber01-VHDL13_DWEH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2415
ber01-VHDL13_DWEI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 3318
ber01-VHDL13_DWEI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2368
ber01-VHDL13_DWHG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2995
ber01-VHDL13_DWHG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3009
ber01-VHDL13_DWHH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3022
ber01-VHDL13_DWHH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3154
ber01-VHDL13_DWLG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3088
ber01-VHDL13_DWLG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2859
ber01-VHDL13_DWLG_170800_COR-2608170800-dsw--0-ia5 17-Aug-2026 08:48:11 2791
ber01-VHDL13_DWLH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2818
ber01-VHDL13_DWLH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2764
ber01-VHDL13_DWLI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2777
ber01-VHDL13_DWLI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2201
ber01-VHDL13_DWMO_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3654
ber01-VHDL13_DWMO_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3314
ber01-VHDL13_DWMP_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3691
ber01-VHDL13_DWMP_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3681
ber01-VHDL13_DWOG_160300-2608160300-dsw--0-ia5 16-Aug-2026 03:00:10 3602
ber01-VHDL13_DWOG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 4010
ber01-VHDL13_DWOG_161700-2608161700-dsw--0-ia5 16-Aug-2026 18:00:04 3657
ber01-VHDL13_DWOG_170300-2608170300-dsw--0-ia5 17-Aug-2026 03:00:24 4013
ber01-VHDL13_DWOG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 3673
ber01-VHDL13_DWOG_171700-2608171700-dsw--0-ia5 17-Aug-2026 18:00:04 3373
ber01-VHDL13_DWON_152156-2608152156-dsw--0-ia5 15-Aug-2026 21:56:34 2924
ber01-VHDL13_DWON_160129-2608160129-dsw--0-ia5 16-Aug-2026 01:29:18 2828
ber01-VHDL13_DWON_160134-2608160134-dsw--0-ia5 16-Aug-2026 01:35:14 3001
ber01-VHDL13_DWON_160152-2608160152-dsw--0-ia5 16-Aug-2026 01:52:54 3001
ber01-VHDL13_DWON_160531-2608160531-dsw--0-ia5 16-Aug-2026 05:31:25 3415
ber01-VHDL13_DWON_160628-2608160628-dsw--0-ia5 16-Aug-2026 06:28:54 3689
ber01-VHDL13_DWON_160635-2608160635-dsw--0-ia5 16-Aug-2026 06:35:23 3691
ber01-VHDL13_DWON_160912-2608160912-dsw--0-ia5 16-Aug-2026 09:12:17 3466
ber01-VHDL13_DWON_161153-2608161153-dsw--0-ia5 16-Aug-2026 11:53:08 3420
ber01-VHDL13_DWON_161434-2608161434-dsw--0-ia5 16-Aug-2026 14:34:22 3793
ber01-VHDL13_DWON_161438-2608161438-dsw--0-ia5 16-Aug-2026 14:38:50 3774
ber01-VHDL13_DWON_161738-2608161738-dsw--0-ia5 16-Aug-2026 17:38:46 3240
ber01-VHDL13_DWON_170131-2608170131-dsw--0-ia5 17-Aug-2026 01:31:35 3455
ber01-VHDL13_DWON_170512-2608170512-dsw--0-ia5 17-Aug-2026 05:12:29 3505
ber01-VHDL13_DWON_170915-2608170915-dsw--0-ia5 17-Aug-2026 09:15:33 3505
ber01-VHDL13_DWON_171340-2608171340-dsw--0-ia5 17-Aug-2026 13:40:19 3725
ber01-VHDL13_DWON_171432-2608171432-dsw--0-ia5 17-Aug-2026 14:32:39 3714
ber01-VHDL13_DWON_171722-2608171722-dsw--0-ia5 17-Aug-2026 17:22:54 3164
ber01-VHDL13_DWPG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2913
ber01-VHDL13_DWPG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2843
ber01-VHDL13_DWPH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2417
ber01-VHDL13_DWPH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2468
ber01-VHDL13_DWSG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3573
ber01-VHDL13_DWSG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3144
ber01-VHDL17_DWOG_161200-2608161200-dsw--0-ia5 16-Aug-2026 10:59:58 2999
ber01-VHDL17_DWOG_171200-2608171200-dsw--0-ia5 17-Aug-2026 11:34:31 4098
swis2-VHDL20_DWEG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 1599
swis2-VHDL20_DWEG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 1364
swis2-VHDL20_DWEG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1652
swis2-VHDL20_DWEG_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:10 1321
swis2-VHDL20_DWEG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 884
swis2-VHDL20_DWEG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 895
swis2-VHDL20_DWEG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1013
swis2-VHDL20_DWEG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1095
swis2-VHDL20_DWEH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 873
swis2-VHDL20_DWEH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 865
swis2-VHDL20_DWEH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1014
swis2-VHDL20_DWEH_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:10 1062
swis2-VHDL20_DWEH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:17 898
swis2-VHDL20_DWEH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 909
swis2-VHDL20_DWEH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1021
swis2-VHDL20_DWEH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1121
swis2-VHDL20_DWEI_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 1612
swis2-VHDL20_DWEI_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 1391
swis2-VHDL20_DWEI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1686
swis2-VHDL20_DWEI_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:10 1358
swis2-VHDL20_DWEI_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:17 905
swis2-VHDL20_DWEI_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 916
swis2-VHDL20_DWEI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1070
swis2-VHDL20_DWEI_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1109
swis2-VHDL20_DWHG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:45:47 1294
swis2-VHDL20_DWHG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 971
swis2-VHDL20_DWHG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:45:36 1250
swis2-VHDL20_DWHG_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:45:15 1211
swis2-VHDL20_DWHG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:45:51 1133
swis2-VHDL20_DWHG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1130
swis2-VHDL20_DWHG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:45:46 1277
swis2-VHDL20_DWHG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:45:21 1230
swis2-VHDL20_DWHH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:45:47 1340
swis2-VHDL20_DWHH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1230
swis2-VHDL20_DWHH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:45:36 1546
swis2-VHDL20_DWHH_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:45:15 1634
swis2-VHDL20_DWHH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:45:51 1490
swis2-VHDL20_DWHH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1477
swis2-VHDL20_DWHH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:45:47 1612
swis2-VHDL20_DWHH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:45:21 1342
swis2-VHDL20_DWLG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1527
swis2-VHDL20_DWLG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1615
swis2-VHDL20_DWLG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1414
swis2-VHDL20_DWLG_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:31:15 1212
swis2-VHDL20_DWLG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1089
swis2-VHDL20_DWLG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 1079
swis2-VHDL20_DWLG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1197
swis2-VHDL20_DWLG_170800_COR-2608170800-dsw--0-ia5 17-Aug-2026 08:48:49 1201
swis2-VHDL20_DWLG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1097
swis2-VHDL20_DWLH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1373
swis2-VHDL20_DWLH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1485
swis2-VHDL20_DWLH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1242
swis2-VHDL20_DWLH_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:31:15 1309
swis2-VHDL20_DWLH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1153
swis2-VHDL20_DWLH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 951
swis2-VHDL20_DWLH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1111
swis2-VHDL20_DWLH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1412
swis2-VHDL20_DWLI_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1479
swis2-VHDL20_DWLI_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1503
swis2-VHDL20_DWLI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1204
swis2-VHDL20_DWLI_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:31:15 1159
swis2-VHDL20_DWLI_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 993
swis2-VHDL20_DWLI_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 982
swis2-VHDL20_DWLI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 843
swis2-VHDL20_DWLI_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1020
swis2-VHDL20_DWMO_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1672
swis2-VHDL20_DWMO_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:08 1700
swis2-VHDL20_DWMO_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1767
swis2-VHDL20_DWMO_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:02 1597
swis2-VHDL20_DWMO_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1152
swis2-VHDL20_DWMO_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:04 1153
swis2-VHDL20_DWMO_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 1469
swis2-VHDL20_DWMO_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1276
swis2-VHDL20_DWMP_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1597
swis2-VHDL20_DWMP_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:08 1579
swis2-VHDL20_DWMP_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2006
swis2-VHDL20_DWMP_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:02 1608
swis2-VHDL20_DWMP_161800_COR-2608161800-dsw--0-ia5 16-Aug-2026 19:03:13 2816
swis2-VHDL20_DWMP_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1356
swis2-VHDL20_DWMP_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:04 1417
swis2-VHDL20_DWMP_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 1755
swis2-VHDL20_DWMP_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1749
swis2-VHDL20_DWPG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1458
swis2-VHDL20_DWPG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1222
swis2-VHDL20_DWPG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1243
swis2-VHDL20_DWPG_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:31:15 1053
swis2-VHDL20_DWPG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1022
swis2-VHDL20_DWPG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 1287
swis2-VHDL20_DWPG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1277
swis2-VHDL20_DWPG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 891
swis2-VHDL20_DWPH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 884
swis2-VHDL20_DWPH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 873
swis2-VHDL20_DWPH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 913
swis2-VHDL20_DWPH_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:31:15 913
swis2-VHDL20_DWPH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 774
swis2-VHDL20_DWPH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 784
swis2-VHDL20_DWPH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1008
swis2-VHDL20_DWPH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1073
swis2-VHDL20_DWSG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1595
swis2-VHDL20_DWSG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:18 1570
swis2-VHDL20_DWSG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1724
swis2-VHDL20_DWSG_161800-2608161800-dsw--0-ia5 16-Aug-2026 18:30:10 1425
swis2-VHDL20_DWSG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1139
swis2-VHDL20_DWSG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1121
swis2-VHDL20_DWSG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1234
swis2-VHDL20_DWSG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 772
wst04-VHDL20_DWEG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 242039
wst04-VHDL20_DWEG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 241262
wst04-VHDL20_DWEG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:10 242505
wst04-VHDL20_DWEG_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 244456
wst04-VHDL20_DWEG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 241580
wst04-VHDL20_DWEG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 241939
wst04-VHDL20_DWEG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 243289
wst04-VHDL20_DWEG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 243216
wst04-VHDL20_DWEH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 239377
wst04-VHDL20_DWEH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 239432
wst04-VHDL20_DWEH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:10 240628
wst04-VHDL20_DWEH_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 242060
wst04-VHDL20_DWEH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:17 240870
wst04-VHDL20_DWEH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 241453
wst04-VHDL20_DWEH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 242750
wst04-VHDL20_DWEH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 244807
wst04-VHDL20_DWEI_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:31 349152
wst04-VHDL20_DWEI_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:18 348079
wst04-VHDL20_DWEI_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:23 349490
wst04-VHDL20_DWEI_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 355013
wst04-VHDL20_DWEI_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:25 352713
wst04-VHDL20_DWEI_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 353032
wst04-VHDL20_DWEI_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 353830
wst04-VHDL20_DWEI_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 351790
wst04-VHDL20_DWHG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:45:47 350358
wst04-VHDL20_DWHG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:20 349244
wst04-VHDL20_DWHG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:45:36 351744
wst04-VHDL20_DWHG_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:45:17 362311
wst04-VHDL20_DWHG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:45:51 361570
wst04-VHDL20_DWHG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 361389
wst04-VHDL20_DWHG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:45:46 362263
wst04-VHDL20_DWHG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:45:23 351835
wst04-VHDL20_DWHH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:45:47 335482
wst04-VHDL20_DWHH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:20 231304
wst04-VHDL20_DWHH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:45:36 336417
wst04-VHDL20_DWHH_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:45:17 350739
wst04-VHDL20_DWHH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:45:51 350624
wst04-VHDL20_DWHH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 240785
wst04-VHDL20_DWHH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:45:47 350704
wst04-VHDL20_DWHH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:45:23 341185
wst04-VHDL20_DWLG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 339547
wst04-VHDL20_DWLG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:44 339442
wst04-VHDL20_DWLG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:48 339250
wst04-VHDL20_DWLG_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:31:34 346375
wst04-VHDL20_DWLG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:32 346783
wst04-VHDL20_DWLG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 346569
wst04-VHDL20_DWLG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 346820
wst04-VHDL20_DWLG_170800_COR-2608170800-omedes-..> 17-Aug-2026 08:48:14 346819
wst04-VHDL20_DWLG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 345074
wst04-VHDL20_DWLH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 347878
wst04-VHDL20_DWLH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:44 347565
wst04-VHDL20_DWLH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:54 347160
wst04-VHDL20_DWLH_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:31:34 344684
wst04-VHDL20_DWLH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 344198
wst04-VHDL20_DWLH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 343285
wst04-VHDL20_DWLH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 343668
wst04-VHDL20_DWLH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 355596
wst04-VHDL20_DWLI_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 341103
wst04-VHDL20_DWLI_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:44 340895
wst04-VHDL20_DWLI_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:48 385188
wst04-VHDL20_DWLI_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:31:34 341171
wst04-VHDL20_DWLI_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 341577
wst04-VHDL20_DWLI_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 341102
wst04-VHDL20_DWLI_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 384597
wst04-VHDL20_DWLI_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 338264
wst04-VHDL20_DWMO_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 459776
wst04-VHDL20_DWMO_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 459677
wst04-VHDL20_DWMO_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:23 458543
wst04-VHDL20_DWMO_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 349481
wst04-VHDL20_DWMO_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:17 456965
wst04-VHDL20_DWMO_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 456879
wst04-VHDL20_DWMO_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 456894
wst04-VHDL20_DWMO_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 350989
wst04-VHDL20_DWMP_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:31 578336
wst04-VHDL20_DWMP_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:18 579149
wst04-VHDL20_DWMP_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:26 471128
wst04-VHDL20_DWMP_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 469909
wst04-VHDL20_DWMP_161800_COR-2608161800-omedes-..> 16-Aug-2026 19:03:23 581735
wst04-VHDL20_DWMP_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 579475
wst04-VHDL20_DWMP_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 579652
wst04-VHDL20_DWMP_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:35 470095
wst04-VHDL20_DWMP_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 458676
wst04-VHDL20_DWPG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 247828
wst04-VHDL20_DWPG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:34 354096
wst04-VHDL20_DWPG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:48 398808
wst04-VHDL20_DWPG_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:31:34 352521
wst04-VHDL20_DWPG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 248001
wst04-VHDL20_DWPG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:32 353088
wst04-VHDL20_DWPG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 397781
wst04-VHDL20_DWPG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 349840
wst04-VHDL20_DWPH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 239696
wst04-VHDL20_DWPH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:34 239049
wst04-VHDL20_DWPH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:48 239166
wst04-VHDL20_DWPH_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:31:34 292684
wst04-VHDL20_DWPH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 248772
wst04-VHDL20_DWPH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:32 248177
wst04-VHDL20_DWPH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 248459
wst04-VHDL20_DWPH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 245729
wst04-VHDL20_DWSG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 353103
wst04-VHDL20_DWSG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 352820
wst04-VHDL20_DWSG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:23 353550
wst04-VHDL20_DWSG_161800-2608161800-omedes--0.pdf 16-Aug-2026 18:30:25 357844
wst04-VHDL20_DWSG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 357083
wst04-VHDL20_DWSG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:12 356650
wst04-VHDL20_DWSG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 357197
wst04-VHDL20_DWSG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 347392