Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Oct-2026 15:49:45 6496
FPDL13_DWMZ_280600 28-Oct-2026 11:35:14 6523
SXDL31_DWAV_271800 27-Oct-2026 16:56:24 6613
SXDL31_DWAV_280800 28-Oct-2026 08:27:39 6446
SXDL31_DWAV_281800 28-Oct-2026 16:32:45 7125
SXDL31_DWAV_290800 29-Oct-2026 08:33:38 13279
SXDL31_DWAV_LATEST 29-Oct-2026 08:33:38 13279
SXDL33_DWAV_280000 28-Oct-2026 09:37:46 5842
SXDL33_DWAV_290000 29-Oct-2026 10:33:26 15461
SXDL33_DWAV_LATEST 29-Oct-2026 10:33:26 15461
ber01-FWDL39_DWMS_271200-2610271200-dsw--0-ia5 27-Oct-2026 11:38:24 1622
ber01-FWDL39_DWMS_281200-2610281200-dsw--0-ia5 28-Oct-2026 12:18:59 1586
ber01-VHDL13_DWEG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2864
ber01-VHDL13_DWEG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:13 2644
ber01-VHDL13_DWEH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2566
ber01-VHDL13_DWEH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:13 2542
ber01-VHDL13_DWEI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2596
ber01-VHDL13_DWEI_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:13 2547
ber01-VHDL13_DWHG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 2961
ber01-VHDL13_DWHG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 2732
ber01-VHDL13_DWHH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 2880
ber01-VHDL13_DWHH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 2789
ber01-VHDL13_DWLG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2838
ber01-VHDL13_DWLG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 2358
ber01-VHDL13_DWLH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2960
ber01-VHDL13_DWLH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 2283
ber01-VHDL13_DWLI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2866
ber01-VHDL13_DWLI_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 2407
ber01-VHDL13_DWMO_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2934
ber01-VHDL13_DWMO_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 2706
ber01-VHDL13_DWMP_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3259
ber01-VHDL13_DWMP_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 3054
ber01-VHDL13_DWOG_271700-2610271700-dsw--0-ia5 27-Oct-2026 19:00:06 3457
ber01-VHDL13_DWOG_280300-2610280300-dsw--0-ia5 28-Oct-2026 04:00:09 3613
ber01-VHDL13_DWOG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3420
ber01-VHDL13_DWOG_281700-2610281700-dsw--0-ia5 28-Oct-2026 19:00:24 2842
ber01-VHDL13_DWOG_290300-2610290300-dsw--0-ia5 29-Oct-2026 04:00:06 3021
ber01-VHDL13_DWOG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 3326
ber01-VHDL13_DWON_271514-2610271514-dsw--0-ia5 27-Oct-2026 15:15:17 3278
ber01-VHDL13_DWON_271755-2610271755-dsw--0-ia5 27-Oct-2026 17:55:44 3200
ber01-VHDL13_DWON_280209-2610280209-dsw--0-ia5 28-Oct-2026 02:10:10 3166
ber01-VHDL13_DWON_280345-2610280345-dsw--0-ia5 28-Oct-2026 03:45:53 3166
ber01-VHDL13_DWON_280620-2610280620-dsw--0-ia5 28-Oct-2026 06:20:44 3671
ber01-VHDL13_DWON_280651-2610280651-dsw--0-ia5 28-Oct-2026 06:51:32 3638
ber01-VHDL13_DWON_280928-2610280928-dsw--0-ia5 28-Oct-2026 09:28:59 3638
ber01-VHDL13_DWON_281549-2610281549-dsw--0-ia5 28-Oct-2026 15:49:32 3258
ber01-VHDL13_DWON_281619-2610281619-dsw--0-ia5 28-Oct-2026 16:19:34 2882
ber01-VHDL13_DWON_281802-2610281802-dsw--0-ia5 28-Oct-2026 18:02:23 2882
ber01-VHDL13_DWON_290212-2610290212-dsw--0-ia5 29-Oct-2026 02:12:43 2846
ber01-VHDL13_DWON_290354-2610290354-dsw--0-ia5 29-Oct-2026 03:54:54 2847
ber01-VHDL13_DWON_290628-2610290628-dsw--0-ia5 29-Oct-2026 06:28:48 2821
ber01-VHDL13_DWON_290723-2610290723-dsw--0-ia5 29-Oct-2026 07:23:14 3625
ber01-VHDL13_DWON_290948-2610290948-dsw--0-ia5 29-Oct-2026 09:49:18 3625
ber01-VHDL13_DWPG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3061
ber01-VHDL13_DWPG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 2232
ber01-VHDL13_DWPH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2571
ber01-VHDL13_DWPH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 2414
ber01-VHDL13_DWSG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3463
ber01-VHDL13_DWSG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 3494
ber01-VHDL17_DWOG_271200-2610271200-dsw--0-ia5 27-Oct-2026 12:31:06 2881
ber01-VHDL17_DWOG_281200-2610281200-dsw--0-ia5 28-Oct-2026 12:11:28 2654
swis2-VHDL20_DWEG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1343
swis2-VHDL20_DWEG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1133
swis2-VHDL20_DWEG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1150
swis2-VHDL20_DWEG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1420
swis2-VHDL20_DWEG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1116
swis2-VHDL20_DWEG_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:08 1275
swis2-VHDL20_DWEG_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:01:04 1137
swis2-VHDL20_DWEG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1347
swis2-VHDL20_DWEH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1380
swis2-VHDL20_DWEH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1081
swis2-VHDL20_DWEH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1012
swis2-VHDL20_DWEH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1298
swis2-VHDL20_DWEH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1065
swis2-VHDL20_DWEH_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:08 1096
swis2-VHDL20_DWEH_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:01:04 1057
swis2-VHDL20_DWEH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1206
swis2-VHDL20_DWEI_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1352
swis2-VHDL20_DWEI_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1151
swis2-VHDL20_DWEI_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1153
swis2-VHDL20_DWEI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1436
swis2-VHDL20_DWEI_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1161
swis2-VHDL20_DWEI_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:08 1323
swis2-VHDL20_DWEI_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:01:04 1202
swis2-VHDL20_DWEI_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 1425
swis2-VHDL20_DWHG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:45:11 1796
swis2-VHDL20_DWHG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1330
swis2-VHDL20_DWHG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1712
swis2-VHDL20_DWHG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:45:22 1396
swis2-VHDL20_DWHG_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 1274
swis2-VHDL20_DWHG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1544
swis2-VHDL20_DWHH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:45:11 1795
swis2-VHDL20_DWHH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:45:10 1455
swis2-VHDL20_DWHH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:19 1311
swis2-VHDL20_DWHH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1628
swis2-VHDL20_DWHH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:45:22 1468
swis2-VHDL20_DWHH_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:45:22 1236
swis2-VHDL20_DWHH_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 1233
swis2-VHDL20_DWHH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1568
swis2-VHDL20_DWLG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1092
swis2-VHDL20_DWLG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 887
swis2-VHDL20_DWLG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1220
swis2-VHDL20_DWLG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1465
swis2-VHDL20_DWLG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 993
swis2-VHDL20_DWLG_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:30 859
swis2-VHDL20_DWLG_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 902
swis2-VHDL20_DWLG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:25 1150
swis2-VHDL20_DWLH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1094
swis2-VHDL20_DWLH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 896
swis2-VHDL20_DWLH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1215
swis2-VHDL20_DWLH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1467
swis2-VHDL20_DWLH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 985
swis2-VHDL20_DWLH_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:30 893
swis2-VHDL20_DWLH_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 916
swis2-VHDL20_DWLH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:25 1168
swis2-VHDL20_DWLI_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1091
swis2-VHDL20_DWLI_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 1011
swis2-VHDL20_DWLI_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1184
swis2-VHDL20_DWLI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1431
swis2-VHDL20_DWLI_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 998
swis2-VHDL20_DWLI_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:30 864
swis2-VHDL20_DWLI_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 907
swis2-VHDL20_DWLI_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:25 1154
swis2-VHDL20_DWMO_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1501
swis2-VHDL20_DWMO_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1416
swis2-VHDL20_DWMO_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:05 1414
swis2-VHDL20_DWMO_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1769
swis2-VHDL20_DWMO_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:05 1386
swis2-VHDL20_DWMO_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:06 1346
swis2-VHDL20_DWMO_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:16 1340
swis2-VHDL20_DWMO_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1724
swis2-VHDL20_DWMP_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1482
swis2-VHDL20_DWMP_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1456
swis2-VHDL20_DWMP_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:05 1474
swis2-VHDL20_DWMP_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1843
swis2-VHDL20_DWMP_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:05 1428
swis2-VHDL20_DWMP_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:06 1359
swis2-VHDL20_DWMP_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:15 1353
swis2-VHDL20_DWMP_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:09 1726
swis2-VHDL20_DWPG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1077
swis2-VHDL20_DWPG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 908
swis2-VHDL20_DWPG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1223
swis2-VHDL20_DWPG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1479
swis2-VHDL20_DWPG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 1002
swis2-VHDL20_DWPG_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:30 910
swis2-VHDL20_DWPG_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 932
swis2-VHDL20_DWPG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:25 1188
swis2-VHDL20_DWPH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1084
swis2-VHDL20_DWPH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 910
swis2-VHDL20_DWPH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 991
swis2-VHDL20_DWPH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1251
swis2-VHDL20_DWPH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 1007
swis2-VHDL20_DWPH_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:30 910
swis2-VHDL20_DWPH_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 935
swis2-VHDL20_DWPH_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:25 1195
swis2-VHDL20_DWSG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:09 1851
swis2-VHDL20_DWSG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1450
swis2-VHDL20_DWSG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:19 1455
swis2-VHDL20_DWSG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1862
swis2-VHDL20_DWSG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1568
swis2-VHDL20_DWSG_281800_COR-2610281800-dsw--0-ia5 28-Oct-2026 21:09:06 1622
swis2-VHDL20_DWSG_290200-2610290200-dsw--0-ia5 29-Oct-2026 03:30:06 1287
swis2-VHDL20_DWSG_290400-2610290400-dsw--0-ia5 29-Oct-2026 06:00:24 1242
swis2-VHDL20_DWSG_290800-2610290800-dsw--0-ia5 29-Oct-2026 09:30:07 1696
wst04-VHDL20_DWEG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 235355
wst04-VHDL20_DWEG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 235686
wst04-VHDL20_DWEG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 234965
wst04-VHDL20_DWEG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:30 234951
wst04-VHDL20_DWEG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 233926
wst04-VHDL20_DWEG_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:30 235178
wst04-VHDL20_DWEG_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 233594
wst04-VHDL20_DWEG_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:20 235085
wst04-VHDL20_DWEH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 227845
wst04-VHDL20_DWEH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 228221
wst04-VHDL20_DWEH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 226994
wst04-VHDL20_DWEH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:19 231526
wst04-VHDL20_DWEH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 231491
wst04-VHDL20_DWEH_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:30 232054
wst04-VHDL20_DWEH_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 231117
wst04-VHDL20_DWEH_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:20 231575
wst04-VHDL20_DWEI_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 328661
wst04-VHDL20_DWEI_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 328500
wst04-VHDL20_DWEI_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 328236
wst04-VHDL20_DWEI_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:38 334042
wst04-VHDL20_DWEI_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 332794
wst04-VHDL20_DWEI_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:30 334189
wst04-VHDL20_DWEI_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 332378
wst04-VHDL20_DWEI_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:20 334184
wst04-VHDL20_DWHG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:45:21 319278
wst04-VHDL20_DWHG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:45:14 317868
wst04-VHDL20_DWHG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 316853
wst04-VHDL20_DWHG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:38 322187
wst04-VHDL20_DWHG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:45:35 319735
wst04-VHDL20_DWHG_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:45:22 319311
wst04-VHDL20_DWHG_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 319099
wst04-VHDL20_DWHG_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:35 320793
wst04-VHDL20_DWHH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:45:21 314374
wst04-VHDL20_DWHH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:45:14 313114
wst04-VHDL20_DWHH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 219440
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wst04-VHDL20_DWHH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:45:35 309701
wst04-VHDL20_DWHH_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:45:22 308109
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wst04-VHDL20_DWLG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 322502
wst04-VHDL20_DWLG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 322026
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wst04-VHDL20_DWLG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 318459
wst04-VHDL20_DWLG_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:39 318520
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wst04-VHDL20_DWLH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 314029
wst04-VHDL20_DWLH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 313585
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wst04-VHDL20_DWLH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 316196
wst04-VHDL20_DWLH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 314519
wst04-VHDL20_DWLH_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:30 314601
wst04-VHDL20_DWLH_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:51 314473
wst04-VHDL20_DWLH_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:44 315670
wst04-VHDL20_DWLI_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 322142
wst04-VHDL20_DWLI_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 321900
wst04-VHDL20_DWLI_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:41 321865
wst04-VHDL20_DWLI_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 362779
wst04-VHDL20_DWLI_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:34 316762
wst04-VHDL20_DWLI_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:39 316848
wst04-VHDL20_DWLI_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:51 316695
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wst04-VHDL20_DWMO_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 438219
wst04-VHDL20_DWMO_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 438536
wst04-VHDL20_DWMO_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 439625
wst04-VHDL20_DWMO_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:13 446736
wst04-VHDL20_DWMO_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 445618
wst04-VHDL20_DWMO_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:14 445676
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wst04-VHDL20_DWMP_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 540456
wst04-VHDL20_DWMP_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 540329
wst04-VHDL20_DWMP_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 541188
wst04-VHDL20_DWMP_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:19 543852
wst04-VHDL20_DWMP_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:34 541922
wst04-VHDL20_DWMP_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:14 541181
wst04-VHDL20_DWMP_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 541956
wst04-VHDL20_DWMP_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:25 543055
wst04-VHDL20_DWPG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:37 325252
wst04-VHDL20_DWPG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 230971
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wst04-VHDL20_DWPG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:31:00 374410
wst04-VHDL20_DWPG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:34 328388
wst04-VHDL20_DWPG_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:39 235129
wst04-VHDL20_DWPG_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:42 328407
wst04-VHDL20_DWPG_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:44 374120
wst04-VHDL20_DWPH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 227603
wst04-VHDL20_DWPH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 227187
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wst04-VHDL20_DWPH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 234524
wst04-VHDL20_DWPH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 234156
wst04-VHDL20_DWPH_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:39 234665
wst04-VHDL20_DWPH_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:42 234094
wst04-VHDL20_DWPH_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:44 234468
wst04-VHDL20_DWSG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:20 327276
wst04-VHDL20_DWSG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 325602
wst04-VHDL20_DWSG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 325357
wst04-VHDL20_DWSG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:13 332292
wst04-VHDL20_DWSG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:18 336755
wst04-VHDL20_DWSG_281800_COR-2610281800-omedes-..> 28-Oct-2026 21:09:09 336637
wst04-VHDL20_DWSG_290200-2610290200-omedes--0.pdf 29-Oct-2026 03:30:14 335800
wst04-VHDL20_DWSG_290400-2610290400-omedes--0.pdf 29-Oct-2026 06:00:24 335041
wst04-VHDL20_DWSG_290800-2610290800-omedes--0.pdf 29-Oct-2026 09:30:20 335422