Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Oct-2026 11:26:03 2894
FPDL13_DWMZ_060600 06-Oct-2026 12:14:43 4177
SXDL31_DWAV_051800 05-Oct-2026 16:28:07 8164
SXDL31_DWAV_060800 06-Oct-2026 07:40:00 12622
SXDL31_DWAV_061800 06-Oct-2026 16:44:14 6035
SXDL31_DWAV_070800 07-Oct-2026 07:55:13 13311
SXDL31_DWAV_LATEST 07-Oct-2026 07:55:13 13311
SXDL33_DWAV_060000 06-Oct-2026 10:20:55 13211
SXDL33_DWAV_070000 07-Oct-2026 09:39:35 7538
SXDL33_DWAV_LATEST 07-Oct-2026 09:39:35 7538
ber01-FWDL39_DWMS_061200-2610061200-dsw--0-ia5 06-Oct-2026 11:39:00 1860
ber01-VHDL13_DWEG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:28:24 3635
ber01-VHDL13_DWEG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:28:23 3843
ber01-VHDL13_DWEH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:28:24 3882
ber01-VHDL13_DWEH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:28:23 3877
ber01-VHDL13_DWEI_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:28:18 3858
ber01-VHDL13_DWEI_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:28:14 3880
ber01-VHDL13_DWHG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:09 3032
ber01-VHDL13_DWHG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 3604
ber01-VHDL13_DWHH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:09 2882
ber01-VHDL13_DWHH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 3658
ber01-VHDL13_DWLG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2540
ber01-VHDL13_DWLG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 3179
ber01-VHDL13_DWLH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2914
ber01-VHDL13_DWLH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 3121
ber01-VHDL13_DWLI_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2540
ber01-VHDL13_DWLI_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 2861
ber01-VHDL13_DWMO_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2413
ber01-VHDL13_DWMO_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 2821
ber01-VHDL13_DWMP_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2851
ber01-VHDL13_DWMP_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 3511
ber01-VHDL13_DWOG_051700-2610051700-dsw--0-ia5 05-Oct-2026 18:00:05 3302
ber01-VHDL13_DWOG_060300-2610060300-dsw--0-ia5 06-Oct-2026 03:01:08 3440
ber01-VHDL13_DWOG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 3617
ber01-VHDL13_DWOG_061700-2610061700-dsw--0-ia5 06-Oct-2026 18:00:10 3781
ber01-VHDL13_DWOG_070300-2610070300-dsw--0-ia5 07-Oct-2026 03:05:51 4031
ber01-VHDL13_DWOG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 4177
ber01-VHDL13_DWON_051408-2610051408-dsw--0-ia5 05-Oct-2026 14:08:34 3695
ber01-VHDL13_DWON_051648-2610051648-dsw--0-ia5 05-Oct-2026 16:48:28 3600
ber01-VHDL13_DWON_052142-2610052142-dsw--0-ia5 05-Oct-2026 21:43:16 3343
ber01-VHDL13_DWON_060141-2610060141-dsw--0-ia5 06-Oct-2026 01:41:38 3409
ber01-VHDL13_DWON_060241-2610060241-dsw--0-ia5 06-Oct-2026 02:43:41 3409
ber01-VHDL13_DWON_060507-2610060507-dsw--0-ia5 06-Oct-2026 05:07:18 3934
ber01-VHDL13_DWON_060550-2610060550-dsw--0-ia5 06-Oct-2026 05:50:11 3934
ber01-VHDL13_DWON_060755-2610060755-dsw--0-ia5 06-Oct-2026 07:55:58 3894
ber01-VHDL13_DWON_060823-2610060823-dsw--0-ia5 06-Oct-2026 08:23:13 3894
ber01-VHDL13_DWON_061457-2610061457-dsw--0-ia5 06-Oct-2026 14:57:55 3483
ber01-VHDL13_DWON_061700-2610061700-dsw--0-ia5 06-Oct-2026 17:00:19 3503
ber01-VHDL13_DWON_062342-2610062342-dsw--0-ia5 06-Oct-2026 23:42:15 3531
ber01-VHDL13_DWON_070110-2610070110-dsw--0-ia5 07-Oct-2026 01:10:38 3525
ber01-VHDL13_DWON_070252-2610070252-dsw--0-ia5 07-Oct-2026 02:53:40 3488
ber01-VHDL13_DWON_070528-2610070528-dsw--0-ia5 07-Oct-2026 05:28:34 3915
ber01-VHDL13_DWON_070555-2610070555-dsw--0-ia5 07-Oct-2026 05:56:03 3941
ber01-VHDL13_DWON_070747-2610070747-dsw--0-ia5 07-Oct-2026 07:47:18 3919
ber01-VHDL13_DWON_070841-2610070841-dsw--0-ia5 07-Oct-2026 08:42:12 3922
ber01-VHDL13_DWPG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2406
ber01-VHDL13_DWPG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 2598
ber01-VHDL13_DWPH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:09 2865
ber01-VHDL13_DWPH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 3771
ber01-VHDL13_DWSG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:05 3480
ber01-VHDL13_DWSG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 4010
ber01-VHDL17_DWOG_051200-2610051200-dsw--0-ia5 05-Oct-2026 12:00:18 2449
ber01-VHDL17_DWOG_061200-2610061200-dsw--0-ia5 06-Oct-2026 10:59:06 2489
swis2-VHDL20_DWEG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2373
swis2-VHDL20_DWEG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1659
swis2-VHDL20_DWEG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1621
swis2-VHDL20_DWEG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2336
swis2-VHDL20_DWEG_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:08 2390
swis2-VHDL20_DWEG_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1853
swis2-VHDL20_DWEG_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:01:17 1803
swis2-VHDL20_DWEG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 2166
swis2-VHDL20_DWEH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2552
swis2-VHDL20_DWEH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1689
swis2-VHDL20_DWEH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1682
swis2-VHDL20_DWEH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2440
swis2-VHDL20_DWEH_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:08 2511
swis2-VHDL20_DWEH_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1886
swis2-VHDL20_DWEH_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:01:17 1834
swis2-VHDL20_DWEH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 2211
swis2-VHDL20_DWEI_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2459
swis2-VHDL20_DWEI_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1758
swis2-VHDL20_DWEI_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1752
swis2-VHDL20_DWEI_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 2487
swis2-VHDL20_DWEI_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:08 2536
swis2-VHDL20_DWEI_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1894
swis2-VHDL20_DWEI_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:01:17 1800
swis2-VHDL20_DWEI_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 2196
swis2-VHDL20_DWHG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:45:13 1617
swis2-VHDL20_DWHG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:45:35 1026
swis2-VHDL20_DWHG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1023
swis2-VHDL20_DWHG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:45:07 1492
swis2-VHDL20_DWHG_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:45:16 2080
swis2-VHDL20_DWHG_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:48:14 1726
swis2-VHDL20_DWHG_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:18 1710
swis2-VHDL20_DWHG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:45:34 1892
swis2-VHDL20_DWHH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:45:13 1557
swis2-VHDL20_DWHH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:45:35 1080
swis2-VHDL20_DWHH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1080
swis2-VHDL20_DWHH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:45:07 1539
swis2-VHDL20_DWHH_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:45:16 2110
swis2-VHDL20_DWHH_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:48:14 1756
swis2-VHDL20_DWHH_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:18 1743
swis2-VHDL20_DWHH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:45:34 1939
swis2-VHDL20_DWLG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1047
swis2-VHDL20_DWLG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 760
swis2-VHDL20_DWLG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 757
swis2-VHDL20_DWLG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:23 953
swis2-VHDL20_DWLG_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:31:03 1306
swis2-VHDL20_DWLG_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:36 1019
swis2-VHDL20_DWLG_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:14 1037
swis2-VHDL20_DWLG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:24 1244
swis2-VHDL20_DWLH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1084
swis2-VHDL20_DWLH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 767
swis2-VHDL20_DWLH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 895
swis2-VHDL20_DWLH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:23 1234
swis2-VHDL20_DWLH_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:31:03 1355
swis2-VHDL20_DWLH_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:36 1057
swis2-VHDL20_DWLH_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:14 1098
swis2-VHDL20_DWLH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:24 1361
swis2-VHDL20_DWLI_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1066
swis2-VHDL20_DWLI_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 762
swis2-VHDL20_DWLI_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 759
swis2-VHDL20_DWLI_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:23 879
swis2-VHDL20_DWLI_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:31:03 1216
swis2-VHDL20_DWLI_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:36 952
swis2-VHDL20_DWLI_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:14 923
swis2-VHDL20_DWLI_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:24 1101
swis2-VHDL20_DWMO_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1119
swis2-VHDL20_DWMO_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:03 820
swis2-VHDL20_DWMO_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:03 974
swis2-VHDL20_DWMO_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 1270
swis2-VHDL20_DWMO_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:08 1518
swis2-VHDL20_DWMO_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1313
swis2-VHDL20_DWMO_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:10 1331
swis2-VHDL20_DWMO_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 1443
swis2-VHDL20_DWMP_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1398
swis2-VHDL20_DWMP_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:03 1066
swis2-VHDL20_DWMP_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:03 1220
swis2-VHDL20_DWMP_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:03 1642
swis2-VHDL20_DWMP_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:08 1987
swis2-VHDL20_DWMP_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1641
swis2-VHDL20_DWMP_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:10 1658
swis2-VHDL20_DWMP_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:08 1924
swis2-VHDL20_DWPG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1034
swis2-VHDL20_DWPG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 765
swis2-VHDL20_DWPG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 762
swis2-VHDL20_DWPG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:23 880
swis2-VHDL20_DWPG_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:31:03 1180
swis2-VHDL20_DWPG_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:36 974
swis2-VHDL20_DWPG_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:14 984
swis2-VHDL20_DWPG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:24 1039
swis2-VHDL20_DWPH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 987
swis2-VHDL20_DWPH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 764
swis2-VHDL20_DWPH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 743
swis2-VHDL20_DWPH_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:23 1002
swis2-VHDL20_DWPH_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:31:03 1410
swis2-VHDL20_DWPH_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:36 1157
swis2-VHDL20_DWPH_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:14 1421
swis2-VHDL20_DWPH_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:24 1713
swis2-VHDL20_DWSG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1484
swis2-VHDL20_DWSG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1355
swis2-VHDL20_DWSG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1494
swis2-VHDL20_DWSG_060800-2610060800-dsw--0-ia5 06-Oct-2026 08:30:05 1616
swis2-VHDL20_DWSG_061800-2610061800-dsw--0-ia5 06-Oct-2026 18:30:10 1608
swis2-VHDL20_DWSG_070200-2610070200-dsw--0-ia5 07-Oct-2026 02:30:02 1567
swis2-VHDL20_DWSG_070400-2610070400-dsw--0-ia5 07-Oct-2026 05:00:18 1581
swis2-VHDL20_DWSG_070800-2610070800-dsw--0-ia5 07-Oct-2026 08:30:04 1854
wst04-VHDL20_DWEG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 244579
wst04-VHDL20_DWEG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 242573
wst04-VHDL20_DWEG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 242180
wst04-VHDL20_DWEG_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:13 244233
wst04-VHDL20_DWEG_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:23 244659
wst04-VHDL20_DWEG_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:25 243459
wst04-VHDL20_DWEG_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:14 243054
wst04-VHDL20_DWEG_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:14 244099
wst04-VHDL20_DWEH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 237770
wst04-VHDL20_DWEH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 236147
wst04-VHDL20_DWEH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 235660
wst04-VHDL20_DWEH_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:13 237802
wst04-VHDL20_DWEH_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:23 237644
wst04-VHDL20_DWEH_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:14 236942
wst04-VHDL20_DWEH_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:14 236453
wst04-VHDL20_DWEH_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:12 237554
wst04-VHDL20_DWEI_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 351104
wst04-VHDL20_DWEI_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 349603
wst04-VHDL20_DWEI_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 349141
wst04-VHDL20_DWEI_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:19 350715
wst04-VHDL20_DWEI_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:23 351131
wst04-VHDL20_DWEI_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:25 350456
wst04-VHDL20_DWEI_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:18 349770
wst04-VHDL20_DWEI_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:18 350396
wst04-VHDL20_DWHG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:45:15 349417
wst04-VHDL20_DWHG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:45:35 347298
wst04-VHDL20_DWHG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:23 347080
wst04-VHDL20_DWHG_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:45:13 349605
wst04-VHDL20_DWHG_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:45:16 351076
wst04-VHDL20_DWHG_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:48:14 349953
wst04-VHDL20_DWHG_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:18 349721
wst04-VHDL20_DWHG_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:45:34 350860
wst04-VHDL20_DWHH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:45:15 334584
wst04-VHDL20_DWHH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:45:35 332742
wst04-VHDL20_DWHH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 228589
wst04-VHDL20_DWHH_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:45:13 335193
wst04-VHDL20_DWHH_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:45:16 335082
wst04-VHDL20_DWHH_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:48:14 334395
wst04-VHDL20_DWHH_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:18 231623
wst04-VHDL20_DWHH_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:45:34 334533
wst04-VHDL20_DWLG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:29 333565
wst04-VHDL20_DWLG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 333371
wst04-VHDL20_DWLG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 332176
wst04-VHDL20_DWLG_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:44 333202
wst04-VHDL20_DWLG_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:31:22 334398
wst04-VHDL20_DWLG_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:36 333215
wst04-VHDL20_DWLG_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:44 332807
wst04-VHDL20_DWLG_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:44 333785
wst04-VHDL20_DWLH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:29 337966
wst04-VHDL20_DWLH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 337376
wst04-VHDL20_DWLH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 337136
wst04-VHDL20_DWLH_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:44 337992
wst04-VHDL20_DWLH_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:31:22 339215
wst04-VHDL20_DWLH_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:36 337671
wst04-VHDL20_DWLH_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:44 337269
wst04-VHDL20_DWLH_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:44 337940
wst04-VHDL20_DWLI_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 338693
wst04-VHDL20_DWLI_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:28 338456
wst04-VHDL20_DWLI_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 337253
wst04-VHDL20_DWLI_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:44 382446
wst04-VHDL20_DWLI_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:31:40 339094
wst04-VHDL20_DWLI_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:46 338276
wst04-VHDL20_DWLI_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:44 337803
wst04-VHDL20_DWLI_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:44 383028
wst04-VHDL20_DWMO_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 352416
wst04-VHDL20_DWMO_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 454923
wst04-VHDL20_DWMO_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 455174
wst04-VHDL20_DWMO_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:19 454466
wst04-VHDL20_DWMO_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:30 354038
wst04-VHDL20_DWMO_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:14 455894
wst04-VHDL20_DWMO_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:18 455483
wst04-VHDL20_DWMO_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:24 455436
wst04-VHDL20_DWMP_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:34 459971
wst04-VHDL20_DWMP_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 562162
wst04-VHDL20_DWMP_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 562241
wst04-VHDL20_DWMP_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:23 460319
wst04-VHDL20_DWMP_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:30 462306
wst04-VHDL20_DWMP_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:25 563872
wst04-VHDL20_DWMP_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:18 563849
wst04-VHDL20_DWMP_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:24 461757
wst04-VHDL20_DWPG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 348044
wst04-VHDL20_DWPG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:28 244259
wst04-VHDL20_DWPG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:33 346713
wst04-VHDL20_DWPG_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:48 391824
wst04-VHDL20_DWPG_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:31:40 348466
wst04-VHDL20_DWPG_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:36 244168
wst04-VHDL20_DWPG_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:34 347304
wst04-VHDL20_DWPG_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:48 392367
wst04-VHDL20_DWPH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 243301
wst04-VHDL20_DWPH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 242733
wst04-VHDL20_DWPH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:33 241541
wst04-VHDL20_DWPH_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:44 243053
wst04-VHDL20_DWPH_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:31:22 244347
wst04-VHDL20_DWPH_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:36 243977
wst04-VHDL20_DWPH_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:34 243719
wst04-VHDL20_DWPH_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:44 244831
wst04-VHDL20_DWSG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 350428
wst04-VHDL20_DWSG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 348391
wst04-VHDL20_DWSG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 349016
wst04-VHDL20_DWSG_060800-2610060800-omedes--0.pdf 06-Oct-2026 08:30:19 349937
wst04-VHDL20_DWSG_061800-2610061800-omedes--0.pdf 06-Oct-2026 18:30:23 342692
wst04-VHDL20_DWSG_070200-2610070200-omedes--0.pdf 07-Oct-2026 02:30:14 342011
wst04-VHDL20_DWSG_070400-2610070400-omedes--0.pdf 07-Oct-2026 05:00:14 341858
wst04-VHDL20_DWSG_070800-2610070800-omedes--0.pdf 07-Oct-2026 08:30:18 342658