Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_290600                                 29-May-2026 14:09:23                6155
FPDL13_DWMZ_300600                                 30-May-2026 13:49:04                3779
SXDL31_DWAV_281800                                 28-May-2026 17:11:09                8512
SXDL31_DWAV_290800                                 29-May-2026 06:47:44                9964
SXDL31_DWAV_291800                                 29-May-2026 15:37:06                3983
SXDL31_DWAV_300800                                 30-May-2026 06:53:49                9528
SXDL31_DWAV_LATEST                                 30-May-2026 06:53:49                9528
SXDL33_DWAV_290000                                 29-May-2026 10:30:12                8498
SXDL33_DWAV_300000                                 30-May-2026 10:08:38               12766
SXDL33_DWAV_LATEST                                 30-May-2026 10:08:38               12766
ber01-FWDL39_DWMS_291230-2605291230-dsw--0-ia5     29-May-2026 12:02:31                1102
ber01-FWDL39_DWMS_301230-2605301230-dsw--0-ia5     30-May-2026 12:08:32                1806
ber01-FWDL39_DWMS_301230_COR-2605301230-dsw--0-ia5 30-May-2026 12:49:16                1810
ber01-VHDL13_DWEG_280800_COR-2605280800-dsw--0-ia5 28-May-2026 17:45:16                3570
ber01-VHDL13_DWEG_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:17                3727
ber01-VHDL13_DWEG_300800-2605300800-dsw--0-ia5     30-May-2026 08:28:15                3267
ber01-VHDL13_DWEH_280800_COR-2605280800-dsw--0-ia5 28-May-2026 17:44:41                3438
ber01-VHDL13_DWEH_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:17                3586
ber01-VHDL13_DWEH_300800-2605300800-dsw--0-ia5     30-May-2026 08:28:15                3314
ber01-VHDL13_DWEI_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:21                3618
ber01-VHDL13_DWEI_300800-2605300800-dsw--0-ia5     30-May-2026 08:28:15                3248
ber01-VHDL13_DWHG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3451
ber01-VHDL13_DWHG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:15                3175
ber01-VHDL13_DWHH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3003
ber01-VHDL13_DWHH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:16                2574
ber01-VHDL13_DWLG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3414
ber01-VHDL13_DWLG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                3408
ber01-VHDL13_DWLH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                2959
ber01-VHDL13_DWLH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                2788
ber01-VHDL13_DWLI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3322
ber01-VHDL13_DWLI_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                3211
ber01-VHDL13_DWMO_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3485
ber01-VHDL13_DWMO_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                4058
ber01-VHDL13_DWMP_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3170
ber01-VHDL13_DWMP_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                4096
ber01-VHDL13_DWOG_281700-2605281700-dsw--0-ia5     28-May-2026 18:00:07                3796
ber01-VHDL13_DWOG_290300-2605290300-dsw--0-ia5     29-May-2026 03:00:02                4240
ber01-VHDL13_DWOG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                4126
ber01-VHDL13_DWOG_291700-2605291700-dsw--0-ia5     29-May-2026 18:00:02                4014
ber01-VHDL13_DWOG_300300-2605300300-dsw--0-ia5     30-May-2026 03:00:07                3606
ber01-VHDL13_DWOG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                3671
ber01-VHDL13_DWON_281729-2605281729-dsw--0-ia5     28-May-2026 17:29:28                3670
ber01-VHDL13_DWON_281737-2605281737-dsw--0-ia5     28-May-2026 17:37:42                3556
ber01-VHDL13_DWON_282121-2605282121-dsw--0-ia5     28-May-2026 21:21:37                3553
ber01-VHDL13_DWON_290153-2605290153-dsw--0-ia5     29-May-2026 01:53:53                3531
ber01-VHDL13_DWON_290244-2605290244-dsw--0-ia5     29-May-2026 02:44:57                3846
ber01-VHDL13_DWON_290526-2605290526-dsw--0-ia5     29-May-2026 05:26:51                3846
ber01-VHDL13_DWON_290627-2605290627-dsw--0-ia5     29-May-2026 06:27:51                4408
ber01-VHDL13_DWON_291444-2605291444-dsw--0-ia5     29-May-2026 14:44:24                3557
ber01-VHDL13_DWON_291724-2605291724-dsw--0-ia5     29-May-2026 17:24:23                3536
ber01-VHDL13_DWON_300200-2605300200-dsw--0-ia5     30-May-2026 02:00:47                3383
ber01-VHDL13_DWON_300450-2605300450-dsw--0-ia5     30-May-2026 04:50:15                3874
ber01-VHDL13_DWON_300625-2605300625-dsw--0-ia5     30-May-2026 06:25:56                3874
ber01-VHDL13_DWON_300746-2605300746-dsw--0-ia5     30-May-2026 07:47:02                3871
ber01-VHDL13_DWPG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3158
ber01-VHDL13_DWPG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                2921
ber01-VHDL13_DWPH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3356
ber01-VHDL13_DWPH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                2869
ber01-VHDL13_DWSG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3499
ber01-VHDL13_DWSG_290800_COR-2605290800-dsw--0-ia5 29-May-2026 08:35:49                3617
ber01-VHDL13_DWSG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:16                3954
ber01-VHDL13_DWSG_300800_COR-2605300800-dsw--0-ia5 30-May-2026 08:53:17                4102
ber01-VHDL17_DWOG_291200-2605291200-dsw--0-ia5     29-May-2026 11:51:31                3023
ber01-VHDL17_DWOG_301200-2605301200-dsw--0-ia5     30-May-2026 11:09:01                2988
swis2-VHDL20_DWEG_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2035
swis2-VHDL20_DWEG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1665
swis2-VHDL20_DWEG_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1665
swis2-VHDL20_DWEG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                2017
swis2-VHDL20_DWEG_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1943
swis2-VHDL20_DWEG_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:01                1372
swis2-VHDL20_DWEG_300400-2605300400-dsw--0-ia5     30-May-2026 05:01:21                1586
swis2-VHDL20_DWEG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                1629
swis2-VHDL20_DWEH_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2056
swis2-VHDL20_DWEH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1628
swis2-VHDL20_DWEH_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1629
swis2-VHDL20_DWEH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1977
swis2-VHDL20_DWEH_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1857
swis2-VHDL20_DWEH_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:01                1304
swis2-VHDL20_DWEH_300400-2605300400-dsw--0-ia5     30-May-2026 05:01:21                1719
swis2-VHDL20_DWEH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                1709
swis2-VHDL20_DWEI_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2025
swis2-VHDL20_DWEI_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1611
swis2-VHDL20_DWEI_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1607
swis2-VHDL20_DWEI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1992
swis2-VHDL20_DWEI_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1870
swis2-VHDL20_DWEI_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:05                1381
swis2-VHDL20_DWEI_300400-2605300400-dsw--0-ia5     30-May-2026 05:01:21                1637
swis2-VHDL20_DWEI_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                1616
swis2-VHDL20_DWHG_281800-2605281800-dsw--0-ia5     28-May-2026 18:45:02                1669
swis2-VHDL20_DWHG_290200-2605290200-dsw--0-ia5     29-May-2026 02:45:26                1501
swis2-VHDL20_DWHG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1498
swis2-VHDL20_DWHG_290800-2605290800-dsw--0-ia5     29-May-2026 08:45:06                1834
swis2-VHDL20_DWHG_291800-2605291800-dsw--0-ia5     29-May-2026 18:45:03                1992
swis2-VHDL20_DWHG_300200-2605300200-dsw--0-ia5     30-May-2026 02:45:08                1526
swis2-VHDL20_DWHG_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:16                1523
swis2-VHDL20_DWHG_300800-2605300800-dsw--0-ia5     30-May-2026 08:45:09                1767
swis2-VHDL20_DWHH_281800-2605281800-dsw--0-ia5     28-May-2026 18:45:02                1581
swis2-VHDL20_DWHH_290200-2605290200-dsw--0-ia5     29-May-2026 02:45:26                1402
swis2-VHDL20_DWHH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1402
swis2-VHDL20_DWHH_290800-2605290800-dsw--0-ia5     29-May-2026 08:45:06                1568
swis2-VHDL20_DWHH_291800-2605291800-dsw--0-ia5     29-May-2026 18:45:03                1625
swis2-VHDL20_DWHH_300200-2605300200-dsw--0-ia5     30-May-2026 02:45:08                1124
swis2-VHDL20_DWHH_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:16                1124
swis2-VHDL20_DWHH_300800-2605300800-dsw--0-ia5     30-May-2026 08:45:09                1236
swis2-VHDL20_DWLG_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1524
swis2-VHDL20_DWLG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1121
swis2-VHDL20_DWLG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1399
swis2-VHDL20_DWLG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1769
swis2-VHDL20_DWLG_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1865
swis2-VHDL20_DWLG_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:21                1085
swis2-VHDL20_DWLG_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:12                1352
swis2-VHDL20_DWLG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:22                1455
swis2-VHDL20_DWLH_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1375
swis2-VHDL20_DWLH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1117
swis2-VHDL20_DWLH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1171
swis2-VHDL20_DWLH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1392
swis2-VHDL20_DWLH_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1392
swis2-VHDL20_DWLH_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:21                 864
swis2-VHDL20_DWLH_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:12                1020
swis2-VHDL20_DWLH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:22                1276
swis2-VHDL20_DWLI_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1499
swis2-VHDL20_DWLI_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1124
swis2-VHDL20_DWLI_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1375
swis2-VHDL20_DWLI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1693
swis2-VHDL20_DWLI_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1786
swis2-VHDL20_DWLI_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:21                1105
swis2-VHDL20_DWLI_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:12                1234
swis2-VHDL20_DWLI_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:22                1468
swis2-VHDL20_DWMO_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1735
swis2-VHDL20_DWMO_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:04                1417
swis2-VHDL20_DWMO_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:02                1426
swis2-VHDL20_DWMO_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                2038
swis2-VHDL20_DWMO_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                2274
swis2-VHDL20_DWMO_291800_COR-2605291800-dsw--0-ia5 29-May-2026 21:11:22                3275
swis2-VHDL20_DWMO_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:01                2080
swis2-VHDL20_DWMO_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:01                2079
swis2-VHDL20_DWMO_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                2188
swis2-VHDL20_DWMP_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1654
swis2-VHDL20_DWMP_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:04                1252
swis2-VHDL20_DWMP_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:02                1272
swis2-VHDL20_DWMP_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                1839
swis2-VHDL20_DWMP_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                2004
swis2-VHDL20_DWMP_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:01                2091
swis2-VHDL20_DWMP_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:01                2084
swis2-VHDL20_DWMP_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:01                2111
swis2-VHDL20_DWPG_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1506
swis2-VHDL20_DWPG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1374
swis2-VHDL20_DWPG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1435
swis2-VHDL20_DWPG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1545
swis2-VHDL20_DWPG_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1545
swis2-VHDL20_DWPG_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:21                1239
swis2-VHDL20_DWPG_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:12                1281
swis2-VHDL20_DWPG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:22                1495
swis2-VHDL20_DWPH_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1475
swis2-VHDL20_DWPH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1604
swis2-VHDL20_DWPH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1682
swis2-VHDL20_DWPH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1775
swis2-VHDL20_DWPH_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1805
swis2-VHDL20_DWPH_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:21                1460
swis2-VHDL20_DWPH_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:12                1337
swis2-VHDL20_DWPH_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:22                1470
swis2-VHDL20_DWSG_280200-2605280200-dsw--0-ia5     28-May-2026 22:27:17                1111
swis2-VHDL20_DWSG_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1267
swis2-VHDL20_DWSG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:00                1034
swis2-VHDL20_DWSG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1494
swis2-VHDL20_DWSG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1760
swis2-VHDL20_DWSG_290800_COR-2605290800-dsw--0-ia5 29-May-2026 08:35:49                1792
swis2-VHDL20_DWSG_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1873
swis2-VHDL20_DWSG_300200-2605300200-dsw--0-ia5     30-May-2026 02:30:01                2024
swis2-VHDL20_DWSG_300400-2605300400-dsw--0-ia5     30-May-2026 05:00:18                1998
swis2-VHDL20_DWSG_300800-2605300800-dsw--0-ia5     30-May-2026 08:30:15                2059
swis2-VHDL20_DWSG_300800_COR-2605300800-dsw--0-ia5 30-May-2026 08:53:17                2063
wst04-VHDL20_DWEG_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:12              242994
wst04-VHDL20_DWEG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              242139
wst04-VHDL20_DWEG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              241716
wst04-VHDL20_DWEG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              242689
wst04-VHDL20_DWEG_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:12              242572
wst04-VHDL20_DWEG_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:10              241485
wst04-VHDL20_DWEG_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:12              241903
wst04-VHDL20_DWEG_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:16              242490
wst04-VHDL20_DWEH_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:12              238891
wst04-VHDL20_DWEH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              238639
wst04-VHDL20_DWEH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              238705
wst04-VHDL20_DWEH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              239686
wst04-VHDL20_DWEH_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:12              242740
wst04-VHDL20_DWEH_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:10              241425
wst04-VHDL20_DWEH_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:12              241743
wst04-VHDL20_DWEH_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:16              242327
wst04-VHDL20_DWEI_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              345404
wst04-VHDL20_DWEI_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              344053
wst04-VHDL20_DWEI_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:16              343595
wst04-VHDL20_DWEI_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              345194
wst04-VHDL20_DWEI_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              345953
wst04-VHDL20_DWEI_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:17              344989
wst04-VHDL20_DWEI_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:12              345381
wst04-VHDL20_DWEI_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:15              346129
wst04-VHDL20_DWHG_281800-2605281800-omedes--0.pdf  28-May-2026 18:45:12              357934
wst04-VHDL20_DWHG_290200-2605290200-omedes--0.pdf  29-May-2026 02:45:26              356897
wst04-VHDL20_DWHG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:16              356909
wst04-VHDL20_DWHG_290800-2605290800-omedes--0.pdf  29-May-2026 08:45:11              358653
wst04-VHDL20_DWHG_291800-2605291800-omedes--0.pdf  29-May-2026 18:45:11              357618
wst04-VHDL20_DWHG_300200-2605300200-omedes--0.pdf  30-May-2026 02:45:12              355636
wst04-VHDL20_DWHG_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:16              355424
wst04-VHDL20_DWHG_300800-2605300800-omedes--0.pdf  30-May-2026 08:45:12              357177
wst04-VHDL20_DWHH_281800-2605281800-omedes--0.pdf  28-May-2026 18:45:12              343270
wst04-VHDL20_DWHH_290200-2605290200-omedes--0.pdf  29-May-2026 02:45:26              343087
wst04-VHDL20_DWHH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:22              231593
wst04-VHDL20_DWHH_290800-2605290800-omedes--0.pdf  29-May-2026 08:45:11              343726
wst04-VHDL20_DWHH_291800-2605291800-omedes--0.pdf  29-May-2026 18:45:11              347687
wst04-VHDL20_DWHH_300200-2605300200-omedes--0.pdf  30-May-2026 02:45:12              345322
wst04-VHDL20_DWHH_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:22              234555
wst04-VHDL20_DWHH_300800-2605300800-omedes--0.pdf  30-May-2026 08:45:12              345724
wst04-VHDL20_DWLG_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:26              350532
wst04-VHDL20_DWLG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:26              349543
wst04-VHDL20_DWLG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              349730
wst04-VHDL20_DWLG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              350870
wst04-VHDL20_DWLG_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              343582
wst04-VHDL20_DWLG_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:21              341308
wst04-VHDL20_DWLG_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:42              341646
wst04-VHDL20_DWLG_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:40              342554
wst04-VHDL20_DWLH_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              349721
wst04-VHDL20_DWLH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              348863
wst04-VHDL20_DWLH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              348689
wst04-VHDL20_DWLH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              349032
wst04-VHDL20_DWLH_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              340094
wst04-VHDL20_DWLH_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:21              338438
wst04-VHDL20_DWLH_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:42              338962
wst04-VHDL20_DWLH_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:40              339320
wst04-VHDL20_DWLI_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              352560
wst04-VHDL20_DWLI_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              351617
wst04-VHDL20_DWLI_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              351726
wst04-VHDL20_DWLI_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:46              397428
wst04-VHDL20_DWLI_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:26              347832
wst04-VHDL20_DWLI_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:29              345814
wst04-VHDL20_DWLI_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:42              345763
wst04-VHDL20_DWLI_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:49              391436
wst04-VHDL20_DWMO_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              360542
wst04-VHDL20_DWMO_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              468762
wst04-VHDL20_DWMO_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              468976
wst04-VHDL20_DWMO_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:21              468808
wst04-VHDL20_DWMO_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              360495
wst04-VHDL20_DWMO_291800_COR-2605291800-omedes-..> 29-May-2026 21:11:28              466701
wst04-VHDL20_DWMO_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:17              464557
wst04-VHDL20_DWMO_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:16              464764
wst04-VHDL20_DWMO_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:22              464163
wst04-VHDL20_DWMP_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              474633
wst04-VHDL20_DWMP_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              576973
wst04-VHDL20_DWMP_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:18              577189
wst04-VHDL20_DWMP_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:21              474164
wst04-VHDL20_DWMP_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              472844
wst04-VHDL20_DWMP_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:17              580645
wst04-VHDL20_DWMP_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:16              580851
wst04-VHDL20_DWMP_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:22              472369
wst04-VHDL20_DWPG_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              349839
wst04-VHDL20_DWPG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              245751
wst04-VHDL20_DWPG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:32              349430
wst04-VHDL20_DWPG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              394962
wst04-VHDL20_DWPG_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:26              343044
wst04-VHDL20_DWPG_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:21              239489
wst04-VHDL20_DWPG_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:32              342432
wst04-VHDL20_DWPG_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:49              388011
wst04-VHDL20_DWPH_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              246292
wst04-VHDL20_DWPH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              246302
wst04-VHDL20_DWPH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:32              246178
wst04-VHDL20_DWPH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              246321
wst04-VHDL20_DWPH_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              248386
wst04-VHDL20_DWPH_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:21              247602
wst04-VHDL20_DWPH_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:32              248288
wst04-VHDL20_DWPH_300800-2605300800-omedes--0.pdf  30-May-2026 08:30:40              248437
wst04-VHDL20_DWSG_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:18              351833
wst04-VHDL20_DWSG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              351342
wst04-VHDL20_DWSG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              352545
wst04-VHDL20_DWSG_290800-2605290800-omedes--0.pdf  29-May-2026 08:35:59              353642
wst04-VHDL20_DWSG_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              355475
wst04-VHDL20_DWSG_300200-2605300200-omedes--0.pdf  30-May-2026 02:30:12              355204
wst04-VHDL20_DWSG_300400-2605300400-omedes--0.pdf  30-May-2026 05:00:12              355150
wst04-VHDL20_DWSG_300800-2605300800-omedes--0.pdf  30-May-2026 08:53:21              355235