Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Jan-2026 11:39:29 4417
FPDL13_DWMZ_310600 31-Dec-2025 11:16:43 7692
SXDL31_DWAV_010800 01-Jan-2026 10:16:09 14800
SXDL31_DWAV_011800 01-Jan-2026 18:10:43 8988
SXDL31_DWAV_310800 31-Dec-2025 09:20:20 16523
SXDL31_DWAV_311800 31-Dec-2025 17:53:35 13016
SXDL31_DWAV_LATEST 01-Jan-2026 18:10:43 8988
SXDL33_DWAV_010000 01-Jan-2026 12:29:58 7712
SXDL33_DWAV_310000 31-Dec-2025 11:11:53 11521
SXDL33_DWAV_LATEST 01-Jan-2026 12:29:58 7712
ber01-FWDL39_DWMS_011230-2601011230-dsw--0-ia5 01-Jan-2026 13:10:37 2304
ber01-FWDL39_DWMS_011230_COR-2601011230-dsw--0-ia5 01-Jan-2026 14:05:16 2308
ber01-FWDL39_DWMS_311230-2512311230-dsw--0-ia5 31-Dec-2025 13:13:31 2280
ber01-VHDL13_DWEH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:11 5149
ber01-VHDL13_DWEH_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 4881
ber01-VHDL13_DWEH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:16 4691
ber01-VHDL13_DWEH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:17 3293
ber01-VHDL13_DWEH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:36 3517
ber01-VHDL13_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 4355
ber01-VHDL13_DWEH_310400-2512310400-dsw--0-ia5 31-Dec-2025 05:58:12 4498
ber01-VHDL13_DWEH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:28:16 4556
ber01-VHDL13_DWEH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:28:12 4081
ber01-VHDL13_DWHG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:07 4969
ber01-VHDL13_DWHG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 5063
ber01-VHDL13_DWHG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3405
ber01-VHDL13_DWHG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:12 3542
ber01-VHDL13_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3605
ber01-VHDL13_DWHG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:07 4243
ber01-VHDL13_DWHG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:07 4740
ber01-VHDL13_DWHG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:07 3906
ber01-VHDL13_DWHH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:07 3607
ber01-VHDL13_DWHH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3582
ber01-VHDL13_DWHH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3043
ber01-VHDL13_DWHH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:12 3570
ber01-VHDL13_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3589
ber01-VHDL13_DWHH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:07 3489
ber01-VHDL13_DWHH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:07 3545
ber01-VHDL13_DWHH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:07 3100
ber01-VHDL13_DWLG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3532
ber01-VHDL13_DWLG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3774
ber01-VHDL13_DWLG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3910
ber01-VHDL13_DWLG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3192
ber01-VHDL13_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3312
ber01-VHDL13_DWLG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3831
ber01-VHDL13_DWLG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:00 3961
ber01-VHDL13_DWLG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3639
ber01-VHDL13_DWLH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3366
ber01-VHDL13_DWLH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3482
ber01-VHDL13_DWLH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3709
ber01-VHDL13_DWLH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3076
ber01-VHDL13_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3105
ber01-VHDL13_DWLH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3676
ber01-VHDL13_DWLH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:00 3829
ber01-VHDL13_DWLH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3375
ber01-VHDL13_DWLI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3278
ber01-VHDL13_DWLI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3481
ber01-VHDL13_DWLI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3559
ber01-VHDL13_DWLI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3096
ber01-VHDL13_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3053
ber01-VHDL13_DWLI_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3720
ber01-VHDL13_DWLI_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:00 3764
ber01-VHDL13_DWLI_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3312
ber01-VHDL13_DWMG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3851
ber01-VHDL13_DWMG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3851
ber01-VHDL13_DWMG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3945
ber01-VHDL13_DWMG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3568
ber01-VHDL13_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4217
ber01-VHDL13_DWMG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3738
ber01-VHDL13_DWMG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:02 4329
ber01-VHDL13_DWMG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3733
ber01-VHDL13_DWMO_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3491
ber01-VHDL13_DWMO_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3501
ber01-VHDL13_DWMO_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3685
ber01-VHDL13_DWMO_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 2933
ber01-VHDL13_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3649
ber01-VHDL13_DWMO_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3662
ber01-VHDL13_DWMO_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:02 4023
ber01-VHDL13_DWMO_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3204
ber01-VHDL13_DWMP_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3965
ber01-VHDL13_DWMP_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3976
ber01-VHDL13_DWMP_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3955
ber01-VHDL13_DWMP_010800_COR-2601010800-dsw--0-ia5 01-Jan-2026 09:40:07 4094
ber01-VHDL13_DWMP_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3737
ber01-VHDL13_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4467
ber01-VHDL13_DWMP_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3772
ber01-VHDL13_DWMP_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:02 4116
ber01-VHDL13_DWMP_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3509
ber01-VHDL13_DWOG_010300-2601010300-dsw--0-ia5 01-Jan-2026 04:00:01 6456
ber01-VHDL13_DWOG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 5931
ber01-VHDL13_DWOG_011700-2601011700-dsw--0-ia5 01-Jan-2026 19:00:03 5451
ber01-VHDL13_DWOG_011700_COR-2601011700-dsw--0-ia5 01-Jan-2026 21:39:14 5574
ber01-VHDL13_DWOG_020300-2601020300-dsw--0-ia5 02-Jan-2026 04:00:02 5142
ber01-VHDL13_DWOG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:02 7279
ber01-VHDL13_DWOG_310800_COR-2512310800-dsw--0-ia5 31-Dec-2025 15:03:09 7739
ber01-VHDL13_DWOG_311700-2512311700-dsw--0-ia5 31-Dec-2025 19:00:07 6591
ber01-VHDL13_DWOH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:11 4477
ber01-VHDL13_DWOH_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 4131
ber01-VHDL13_DWOH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:16 4107
ber01-VHDL13_DWOH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:17 2858
ber01-VHDL13_DWOH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:31 2862
ber01-VHDL13_DWOH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3698
ber01-VHDL13_DWOH_310400-2512310400-dsw--0-ia5 31-Dec-2025 05:58:12 4043
ber01-VHDL13_DWOH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:28:16 4168
ber01-VHDL13_DWOH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:28:18 3819
ber01-VHDL13_DWOI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:17 3854
ber01-VHDL13_DWOI_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 3789
ber01-VHDL13_DWOI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:12 3778
ber01-VHDL13_DWOI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:12 2783
ber01-VHDL13_DWOI_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:36 2787
ber01-VHDL13_DWOI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3404
ber01-VHDL13_DWOI_310400-2512310400-dsw--0-ia5 31-Dec-2025 05:58:16 3707
ber01-VHDL13_DWOI_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:28:12 3854
ber01-VHDL13_DWOI_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:28:12 3358
ber01-VHDL13_DWON_010228-2601010228-dsw--0-ia5 01-Jan-2026 02:28:51 4260
ber01-VHDL13_DWON_010625-2601010625-dsw--0-ia5 01-Jan-2026 06:25:47 4975
ber01-VHDL13_DWON_010929-2601010929-dsw--0-ia5 01-Jan-2026 09:29:28 4975
ber01-VHDL13_DWON_011410-2601011410-dsw--0-ia5 01-Jan-2026 14:11:01 4573
ber01-VHDL13_DWON_011841-2601011841-dsw--0-ia5 01-Jan-2026 18:41:21 3765
ber01-VHDL13_DWON_012138-2601012138-dsw--0-ia5 01-Jan-2026 21:38:41 3434
ber01-VHDL13_DWON_012324-2601012324-dsw--0-ia5 01-Jan-2026 23:24:11 3289
ber01-VHDL13_DWON_020356-2601020356-dsw--0-ia5 02-Jan-2026 03:56:26 3289
ber01-VHDL13_DWON_310630-2512310630-dsw--0-ia5 31-Dec-2025 06:30:51 5155
ber01-VHDL13_DWON_310634-2512310634-dsw--0-ia5 31-Dec-2025 06:34:51 5398
ber01-VHDL13_DWON_310651-2512310651-dsw--0-ia5 31-Dec-2025 06:51:37 5466
ber01-VHDL13_DWON_310732-2512310732-dsw--0-ia5 31-Dec-2025 07:32:41 5466
ber01-VHDL13_DWON_311502-2512311502-dsw--0-ia5 31-Dec-2025 15:02:31 5734
ber01-VHDL13_DWON_311534-2512311534-dsw--0-ia5 31-Dec-2025 15:34:57 5544
ber01-VHDL13_DWON_311839-2512311839-dsw--0-ia5 31-Dec-2025 18:39:56 4744
ber01-VHDL13_DWPG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 2685
ber01-VHDL13_DWPG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 2790
ber01-VHDL13_DWPG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 2918
ber01-VHDL13_DWPG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 2394
ber01-VHDL13_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 2476
ber01-VHDL13_DWPG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 3555
ber01-VHDL13_DWPG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:00 3500
ber01-VHDL13_DWPG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 2933
ber01-VHDL13_DWPH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3816
ber01-VHDL13_DWPH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3790
ber01-VHDL13_DWPH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3776
ber01-VHDL13_DWPH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3212
ber01-VHDL13_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3099
ber01-VHDL13_DWPH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:02 4323
ber01-VHDL13_DWPH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:00 4390
ber01-VHDL13_DWPH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 3911
ber01-VHDL13_DWSG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3286
ber01-VHDL13_DWSG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3560
ber01-VHDL13_DWSG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 4213
ber01-VHDL13_DWSG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:05 3579
ber01-VHDL13_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3726
ber01-VHDL13_DWSG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:07 2406
ber01-VHDL13_DWSG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:30:02 3175
ber01-VHDL13_DWSG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:30:02 2774
ber01-VHDL17_DWOG_011200-2601011200-dsw--0-ia5 01-Jan-2026 12:55:27 2759
ber01-VHDL17_DWOG_311200-2512311200-dsw--0-ia5 31-Dec-2025 12:49:36 3652
swis2-VHDL20_DWEG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4950
swis2-VHDL20_DWEG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 4723
swis2-VHDL20_DWEG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4929
swis2-VHDL20_DWEG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3452
swis2-VHDL20_DWEG_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 3456
swis2-VHDL20_DWEG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4171
swis2-VHDL20_DWEG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 4549
swis2-VHDL20_DWEG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4968
swis2-VHDL20_DWEG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4504
swis2-VHDL20_DWEH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 5728
swis2-VHDL20_DWEH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 5495
swis2-VHDL20_DWEH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 5627
swis2-VHDL20_DWEH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3921
swis2-VHDL20_DWEH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 4145
swis2-VHDL20_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4976
swis2-VHDL20_DWEH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 5088
swis2-VHDL20_DWEH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 5491
swis2-VHDL20_DWEH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4986
swis2-VHDL20_DWEI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:08 4303
swis2-VHDL20_DWEI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 4334
swis2-VHDL20_DWEI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4688
swis2-VHDL20_DWEI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3324
swis2-VHDL20_DWEI_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 3328
swis2-VHDL20_DWEI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 3870
swis2-VHDL20_DWEI_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 4263
swis2-VHDL20_DWEI_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4792
swis2-VHDL20_DWEI_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4124
swis2-VHDL20_DWHG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 5155
swis2-VHDL20_DWHG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 5246
swis2-VHDL20_DWHG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4400
swis2-VHDL20_DWHG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3725
swis2-VHDL20_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3791
swis2-VHDL20_DWHG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:07 4426
swis2-VHDL20_DWHG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 5357
swis2-VHDL20_DWHG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4089
swis2-VHDL20_DWHH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3793
swis2-VHDL20_DWHH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3768
swis2-VHDL20_DWHH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 3760
swis2-VHDL20_DWHH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3756
swis2-VHDL20_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3775
swis2-VHDL20_DWHH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:07 3675
swis2-VHDL20_DWHH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4124
swis2-VHDL20_DWHH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 3286
swis2-VHDL20_DWLG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3935
swis2-VHDL20_DWLG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 4252
swis2-VHDL20_DWLG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4634
swis2-VHDL20_DWLG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3670
swis2-VHDL20_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3793
swis2-VHDL20_DWLG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:17 4231
swis2-VHDL20_DWLG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:02 4559
swis2-VHDL20_DWLG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4039
swis2-VHDL20_DWLH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3789
swis2-VHDL20_DWLH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3962
swis2-VHDL20_DWLH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4437
swis2-VHDL20_DWLH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3556
swis2-VHDL20_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3588
swis2-VHDL20_DWLH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:17 4091
swis2-VHDL20_DWLH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4441
swis2-VHDL20_DWLH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 3795
swis2-VHDL20_DWLI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3710
swis2-VHDL20_DWLI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3960
swis2-VHDL20_DWLI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4284
swis2-VHDL20_DWLI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3575
swis2-VHDL20_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3541
swis2-VHDL20_DWLI_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:17 4149
swis2-VHDL20_DWLI_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4389
swis2-VHDL20_DWLI_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 3741
swis2-VHDL20_DWMG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4313
swis2-VHDL20_DWMG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 4348
swis2-VHDL20_DWMG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4648
swis2-VHDL20_DWMG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4004
swis2-VHDL20_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4642
swis2-VHDL20_DWMG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 4191
swis2-VHDL20_DWMG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:02 4993
swis2-VHDL20_DWMG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4221
swis2-VHDL20_DWMO_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4018
swis2-VHDL20_DWMO_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 3936
swis2-VHDL20_DWMO_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4329
swis2-VHDL20_DWMO_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3373
swis2-VHDL20_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4083
swis2-VHDL20_DWMO_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 4096
swis2-VHDL20_DWMO_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:02 4671
swis2-VHDL20_DWMO_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 3691
swis2-VHDL20_DWMP_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:08 4457
swis2-VHDL20_DWMP_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 4472
swis2-VHDL20_DWMP_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4797
swis2-VHDL20_DWMP_010800_COR-2601010800-dsw--0-ia5 01-Jan-2026 09:40:07 4801
swis2-VHDL20_DWMP_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4169
swis2-VHDL20_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4900
swis2-VHDL20_DWMP_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 4231
swis2-VHDL20_DWMP_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:02 4791
swis2-VHDL20_DWMP_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4018
swis2-VHDL20_DWPG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3011
swis2-VHDL20_DWPG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3326
swis2-VHDL20_DWPG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 3797
swis2-VHDL20_DWPG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3273
swis2-VHDL20_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3015
swis2-VHDL20_DWPG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:17 3942
swis2-VHDL20_DWPG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 4230
swis2-VHDL20_DWPG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 3667
swis2-VHDL20_DWPH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4219
swis2-VHDL20_DWPH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 4328
swis2-VHDL20_DWPH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4655
swis2-VHDL20_DWPH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4091
swis2-VHDL20_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3637
swis2-VHDL20_DWPH_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:00:17 4713
swis2-VHDL20_DWPH_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:06 5121
swis2-VHDL20_DWPH_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:01 4645
swis2-VHDL20_DWSG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3682
swis2-VHDL20_DWSG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 3998
swis2-VHDL20_DWSG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4894
swis2-VHDL20_DWSG_011300-2601011300-dsw--0-ia5 01-Jan-2026 14:45:07 4713
swis2-VHDL20_DWSG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4052
swis2-VHDL20_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 4187
swis2-VHDL20_DWSG_310400-2512310400-dsw--0-ia5 31-Dec-2025 06:15:01 2910
swis2-VHDL20_DWSG_310800-2512310800-dsw--0-ia5 31-Dec-2025 09:45:02 3843
swis2-VHDL20_DWSG_311300-2512311300-dsw--0-ia5 31-Dec-2025 14:45:06 3673
swis2-VHDL20_DWSG_311800-2512311800-dsw--0-ia5 31-Dec-2025 19:45:06 3246
wst04-VHDL20_DWEG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 227426
wst04-VHDL20_DWEG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:26 226701
wst04-VHDL20_DWEG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 227286
wst04-VHDL20_DWEG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 224295
wst04-VHDL20_DWEG_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:36 224295
wst04-VHDL20_DWEG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 226084
wst04-VHDL20_DWEG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:21 227708
wst04-VHDL20_DWEG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:26 226991
wst04-VHDL20_DWEG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:15 226603
wst04-VHDL20_DWEH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 224168
wst04-VHDL20_DWEH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:22 223435
wst04-VHDL20_DWEH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 224538
wst04-VHDL20_DWEH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 222030
wst04-VHDL20_DWEH_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:31 222348
wst04-VHDL20_DWEH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 223887
wst04-VHDL20_DWEH_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:17 222991
wst04-VHDL20_DWEH_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:22 223040
wst04-VHDL20_DWEH_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:15 223206
wst04-VHDL20_DWEI_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 309503
wst04-VHDL20_DWEI_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:26 309344
wst04-VHDL20_DWEI_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 312145
wst04-VHDL20_DWEI_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 310178
wst04-VHDL20_DWEI_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:36 310178
wst04-VHDL20_DWEI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 310056
wst04-VHDL20_DWEI_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:21 308969
wst04-VHDL20_DWEI_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:26 309853
wst04-VHDL20_DWEI_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:15 309264
wst04-VHDL20_DWHG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 312550
wst04-VHDL20_DWHG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:12 312682
wst04-VHDL20_DWHG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:12 306504
wst04-VHDL20_DWHG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 303262
wst04-VHDL20_DWHG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 303500
wst04-VHDL20_DWHG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:13 311332
wst04-VHDL20_DWHG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:16 313485
wst04-VHDL20_DWHG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:12 311048
wst04-VHDL20_DWHH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 307628
wst04-VHDL20_DWHH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:12 307639
wst04-VHDL20_DWHH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:12 310942
wst04-VHDL20_DWHH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 309971
wst04-VHDL20_DWHH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 310034
wst04-VHDL20_DWHH_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:13 307432
wst04-VHDL20_DWHH_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:16 308508
wst04-VHDL20_DWHH_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:12 307870
wst04-VHDL20_DWLG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:27 302849
wst04-VHDL20_DWLG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 303107
wst04-VHDL20_DWLG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 297347
wst04-VHDL20_DWLG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 295943
wst04-VHDL20_DWLG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 295652
wst04-VHDL20_DWLG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:41 306094
wst04-VHDL20_DWLG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:26 303466
wst04-VHDL20_DWLG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:27 302727
wst04-VHDL20_DWLH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 294276
wst04-VHDL20_DWLH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 294452
wst04-VHDL20_DWLH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 295811
wst04-VHDL20_DWLH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:25 294143
wst04-VHDL20_DWLH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 293642
wst04-VHDL20_DWLH_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:41 299167
wst04-VHDL20_DWLH_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:32 294833
wst04-VHDL20_DWLH_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:21 294128
wst04-VHDL20_DWLI_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 296417
wst04-VHDL20_DWLI_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 296725
wst04-VHDL20_DWLI_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 294356
wst04-VHDL20_DWLI_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 293514
wst04-VHDL20_DWLI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 292952
wst04-VHDL20_DWLI_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:41 299295
wst04-VHDL20_DWLI_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:32 297177
wst04-VHDL20_DWLI_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:21 296319
wst04-VHDL20_DWMG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 499648
wst04-VHDL20_DWMG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 499484
wst04-VHDL20_DWMG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 497385
wst04-VHDL20_DWMG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 495463
wst04-VHDL20_DWMG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 496655
wst04-VHDL20_DWMG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:11 503005
wst04-VHDL20_DWMG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:18 501052
wst04-VHDL20_DWMG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:17 499711
wst04-VHDL20_DWMO_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 399662
wst04-VHDL20_DWMO_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 399921
wst04-VHDL20_DWMO_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:16 399376
wst04-VHDL20_DWMO_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 398471
wst04-VHDL20_DWMO_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 398751
wst04-VHDL20_DWMO_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:17 402371
wst04-VHDL20_DWMO_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:12 399805
wst04-VHDL20_DWMO_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:17 399152
wst04-VHDL20_DWMP_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:23 516596
wst04-VHDL20_DWMP_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 518378
wst04-VHDL20_DWMP_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:16 523246
wst04-VHDL20_DWMP_010800_COR-2601010800-omedes-..> 01-Jan-2026 09:40:07 523246
wst04-VHDL20_DWMP_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 521250
wst04-VHDL20_DWMP_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 520595
wst04-VHDL20_DWMP_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:17 521127
wst04-VHDL20_DWMP_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:18 519429
wst04-VHDL20_DWMP_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:21 517988
wst04-VHDL20_DWPG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:27 307360
wst04-VHDL20_DWPG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:32 307868
wst04-VHDL20_DWPG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 344418
wst04-VHDL20_DWPG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:25 299446
wst04-VHDL20_DWPG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 299185
wst04-VHDL20_DWPG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:32 301747
wst04-VHDL20_DWPG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:32 353431
wst04-VHDL20_DWPG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:27 308227
wst04-VHDL20_DWPH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 225608
wst04-VHDL20_DWPH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:32 225898
wst04-VHDL20_DWPH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 269469
wst04-VHDL20_DWPH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 268173
wst04-VHDL20_DWPH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 223259
wst04-VHDL20_DWPH_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:00:32 229366
wst04-VHDL20_DWPH_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:26 271255
wst04-VHDL20_DWPH_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:21 270654
wst04-VHDL20_DWSG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 320814
wst04-VHDL20_DWSG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 321591
wst04-VHDL20_DWSG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:12 319694
wst04-VHDL20_DWSG_011300-2601011300-omedes--0.pdf 01-Jan-2026 14:45:26 319738
wst04-VHDL20_DWSG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 318146
wst04-VHDL20_DWSG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 318413
wst04-VHDL20_DWSG_310400-2512310400-omedes--0.pdf 31-Dec-2025 06:15:11 320924
wst04-VHDL20_DWSG_310800-2512310800-omedes--0.pdf 31-Dec-2025 09:45:12 321175
wst04-VHDL20_DWSG_311300-2512311300-omedes--0.pdf 31-Dec-2025 14:45:12 321114
wst04-VHDL20_DWSG_311800-2512311800-omedes--0.pdf 31-Dec-2025 19:45:12 320398