Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Jun-2026 12:40:56 6490
FPDL13_DWMZ_190600 19-Jun-2026 12:13:39 4018
SXDL31_DWAV_180800 18-Jun-2026 10:24:35 14091
SXDL31_DWAV_181800 18-Jun-2026 16:43:20 15220
SXDL31_DWAV_190800 19-Jun-2026 09:40:55 15939
SXDL31_DWAV_191800 19-Jun-2026 16:37:38 13609
SXDL31_DWAV_LATEST 19-Jun-2026 16:37:38 13609
SXDL33_DWAV_180000 18-Jun-2026 10:51:52 20679
SXDL33_DWAV_190000 19-Jun-2026 09:39:29 11287
SXDL33_DWAV_LATEST 19-Jun-2026 09:39:29 11287
ber01-FWDL39_DWMS_181200-2606181200-dsw--0-ia5 18-Jun-2026 09:48:23 1625
ber01-FWDL39_DWMS_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:25:51 1336
ber01-VHDL13_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3493
ber01-VHDL13_DWEG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:12 3431
ber01-VHDL13_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 4161
ber01-VHDL13_DWEH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:16 3906
ber01-VHDL13_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3393
ber01-VHDL13_DWEI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:16 3477
ber01-VHDL13_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3038
ber01-VHDL13_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 10:54:52 3231
ber01-VHDL13_DWHG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3715
ber01-VHDL13_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3044
ber01-VHDL13_DWHH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3595
ber01-VHDL13_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2514
ber01-VHDL13_DWLG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2629
ber01-VHDL13_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2480
ber01-VHDL13_DWLH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2770
ber01-VHDL13_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2411
ber01-VHDL13_DWLI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2722
ber01-VHDL13_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3033
ber01-VHDL13_DWMO_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3467
ber01-VHDL13_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3367
ber01-VHDL13_DWMP_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3413
ber01-VHDL13_DWOG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3756
ber01-VHDL13_DWOG_181700-2606181700-dsw--0-ia5 18-Jun-2026 18:00:01 4526
ber01-VHDL13_DWOG_190300-2606190300-dsw--0-ia5 19-Jun-2026 03:00:01 4739
ber01-VHDL13_DWOG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 4679
ber01-VHDL13_DWOG_191700-2606191700-dsw--0-ia5 19-Jun-2026 18:00:04 5005
ber01-VHDL13_DWOG_200300-2606200300-dsw--0-ia5 20-Jun-2026 03:00:02 4733
ber01-VHDL13_DWON_180644-2606180644-dsw--0-ia5 18-Jun-2026 06:44:27 3982
ber01-VHDL13_DWON_181231-2606181231-dsw--0-ia5 18-Jun-2026 12:31:06 3958
ber01-VHDL13_DWON_181448-2606181448-dsw--0-ia5 18-Jun-2026 14:48:56 3661
ber01-VHDL13_DWON_181653-2606181653-dsw--0-ia5 18-Jun-2026 16:53:21 3579
ber01-VHDL13_DWON_181737-2606181737-dsw--0-ia5 18-Jun-2026 17:37:31 3579
ber01-VHDL13_DWON_182159-2606182159-dsw--0-ia5 18-Jun-2026 22:00:01 3512
ber01-VHDL13_DWON_190034-2606190034-dsw--0-ia5 19-Jun-2026 00:34:48 3759
ber01-VHDL13_DWON_190211-2606190211-dsw--0-ia5 19-Jun-2026 02:11:22 3759
ber01-VHDL13_DWON_190519-2606190519-dsw--0-ia5 19-Jun-2026 05:19:31 3686
ber01-VHDL13_DWON_190733-2606190733-dsw--0-ia5 19-Jun-2026 07:34:00 3661
ber01-VHDL13_DWON_190931-2606190931-dsw--0-ia5 19-Jun-2026 09:31:47 3512
ber01-VHDL13_DWON_191416-2606191416-dsw--0-ia5 19-Jun-2026 14:16:07 3586
ber01-VHDL13_DWON_191701-2606191701-dsw--0-ia5 19-Jun-2026 17:01:11 4201
ber01-VHDL13_DWON_192159-2606192159-dsw--0-ia5 19-Jun-2026 21:59:52 4278
ber01-VHDL13_DWON_200137-2606200137-dsw--0-ia5 20-Jun-2026 01:37:31 3828
ber01-VHDL13_DWON_200156-2606200156-dsw--0-ia5 20-Jun-2026 01:56:27 3828
ber01-VHDL13_DWON_200339-2606200339-dsw--0-ia5 20-Jun-2026 03:39:08 3828
ber01-VHDL13_DWON_200529-2606200529-dsw--0-ia5 20-Jun-2026 05:29:41 3827
ber01-VHDL13_DWON_200612-2606200612-dsw--0-ia5 20-Jun-2026 06:12:27 4353
ber01-VHDL13_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2391
ber01-VHDL13_DWPG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2812
ber01-VHDL13_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2532
ber01-VHDL13_DWPH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2759
ber01-VHDL13_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3547
ber01-VHDL13_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 3906
ber01-VHDL13_DWSG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3826
ber01-VHDL13_DWSG_190800_COR-2606190800-dsw--0-ia5 19-Jun-2026 05:24:56 3841
ber01-VHDL17_DWOG_181200-2606181200-dsw--0-ia5 18-Jun-2026 11:51:17 3712
ber01-VHDL17_DWOG_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:05:47 3322
swis2-VHDL20_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2061
swis2-VHDL20_DWEG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 1927
swis2-VHDL20_DWEG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1507
swis2-VHDL20_DWEG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 2092
swis2-VHDL20_DWEG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2371
swis2-VHDL20_DWEG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2498
swis2-VHDL20_DWEG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1876
swis2-VHDL20_DWEG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2126
swis2-VHDL20_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2581
swis2-VHDL20_DWEH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2513
swis2-VHDL20_DWEH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1985
swis2-VHDL20_DWEH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 2250
swis2-VHDL20_DWEH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2729
swis2-VHDL20_DWEH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2512
swis2-VHDL20_DWEH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1782
swis2-VHDL20_DWEH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2096
swis2-VHDL20_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2017
swis2-VHDL20_DWEI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2257
swis2-VHDL20_DWEI_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:01 1742
swis2-VHDL20_DWEI_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 1715
swis2-VHDL20_DWEI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2365
swis2-VHDL20_DWEI_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2510
swis2-VHDL20_DWEI_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1649
swis2-VHDL20_DWEI_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2193
swis2-VHDL20_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1686
swis2-VHDL20_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 11:05:21 1691
swis2-VHDL20_DWHG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1656
swis2-VHDL20_DWHG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:45:10 1961
swis2-VHDL20_DWHG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 2024
swis2-VHDL20_DWHG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:45:12 2149
swis2-VHDL20_DWHG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:45:07 1935
swis2-VHDL20_DWHG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:45:10 1743
swis2-VHDL20_DWHG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1740
swis2-VHDL20_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1398
swis2-VHDL20_DWHH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1606
swis2-VHDL20_DWHH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:45:10 1898
swis2-VHDL20_DWHH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 1935
swis2-VHDL20_DWHH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:45:12 2078
swis2-VHDL20_DWHH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:45:07 1644
swis2-VHDL20_DWHH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:45:10 1550
swis2-VHDL20_DWHH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1550
swis2-VHDL20_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1627
swis2-VHDL20_DWLG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1315
swis2-VHDL20_DWLG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1308
swis2-VHDL20_DWLG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1303
swis2-VHDL20_DWLG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1558
swis2-VHDL20_DWLG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1912
swis2-VHDL20_DWLG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1490
swis2-VHDL20_DWLG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1448
swis2-VHDL20_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1716
swis2-VHDL20_DWLH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1441
swis2-VHDL20_DWLH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1314
swis2-VHDL20_DWLH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1299
swis2-VHDL20_DWLH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1600
swis2-VHDL20_DWLH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1953
swis2-VHDL20_DWLH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1750
swis2-VHDL20_DWLH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1442
swis2-VHDL20_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1633
swis2-VHDL20_DWLI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1405
swis2-VHDL20_DWLI_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1314
swis2-VHDL20_DWLI_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1293
swis2-VHDL20_DWLI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1559
swis2-VHDL20_DWLI_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1830
swis2-VHDL20_DWLI_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1597
swis2-VHDL20_DWLI_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1306
swis2-VHDL20_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 1416
swis2-VHDL20_DWMO_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1367
swis2-VHDL20_DWMO_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1419
swis2-VHDL20_DWMO_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:01 1427
swis2-VHDL20_DWMO_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1652
swis2-VHDL20_DWMO_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 1724
swis2-VHDL20_DWMO_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1460
swis2-VHDL20_DWMO_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:02 1448
swis2-VHDL20_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1662
swis2-VHDL20_DWMP_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1603
swis2-VHDL20_DWMP_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1472
swis2-VHDL20_DWMP_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:01 1464
swis2-VHDL20_DWMP_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1680
swis2-VHDL20_DWMP_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 1670
swis2-VHDL20_DWMP_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1423
swis2-VHDL20_DWMP_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:02 1448
swis2-VHDL20_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1590
swis2-VHDL20_DWPG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1508
swis2-VHDL20_DWPG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1410
swis2-VHDL20_DWPG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1431
swis2-VHDL20_DWPG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1764
swis2-VHDL20_DWPG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1680
swis2-VHDL20_DWPG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1489
swis2-VHDL20_DWPG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1457
swis2-VHDL20_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1571
swis2-VHDL20_DWPH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1288
swis2-VHDL20_DWPH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1467
swis2-VHDL20_DWPH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1348
swis2-VHDL20_DWPH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1447
swis2-VHDL20_DWPH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1430
swis2-VHDL20_DWPH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1346
swis2-VHDL20_DWPH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1311
swis2-VHDL20_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1561
swis2-VHDL20_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 1831
swis2-VHDL20_DWSG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1740
swis2-VHDL20_DWSG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:01 1527
swis2-VHDL20_DWSG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 1524
swis2-VHDL20_DWSG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1890
swis2-VHDL20_DWSG_190800_COR-2606190800-dsw--0-ia5 19-Jun-2026 05:24:56 1905
swis2-VHDL20_DWSG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2060
swis2-VHDL20_DWSG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1328
swis2-VHDL20_DWSG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1325
wst04-VHDL20_DWEG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246925
wst04-VHDL20_DWEG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249247
wst04-VHDL20_DWEG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 248752
wst04-VHDL20_DWEG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 249508
wst04-VHDL20_DWEG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 249956
wst04-VHDL20_DWEG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 252051
wst04-VHDL20_DWEG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 250229
wst04-VHDL20_DWEG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 250055
wst04-VHDL20_DWEH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246072
wst04-VHDL20_DWEH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249672
wst04-VHDL20_DWEH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 249798
wst04-VHDL20_DWEH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 249673
wst04-VHDL20_DWEH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 250386
wst04-VHDL20_DWEH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 246862
wst04-VHDL20_DWEH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 245556
wst04-VHDL20_DWEH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 245389
wst04-VHDL20_DWEI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 354320
wst04-VHDL20_DWEI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 360512
wst04-VHDL20_DWEI_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 360619
wst04-VHDL20_DWEI_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 360310
wst04-VHDL20_DWEI_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 361027
wst04-VHDL20_DWEI_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 363899
wst04-VHDL20_DWEI_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 362420
wst04-VHDL20_DWEI_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 362414
wst04-VHDL20_DWHG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 351740
wst04-VHDL20_DWHG_180800_COR-2606180800-omedes-..> 18-Jun-2026 11:07:07 363371
wst04-VHDL20_DWHG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 361512
wst04-VHDL20_DWHG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:45:14 363182
wst04-VHDL20_DWHG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 363215
wst04-VHDL20_DWHG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:45:12 364052
wst04-VHDL20_DWHG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:45:18 356475
wst04-VHDL20_DWHG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:45:16 355913
wst04-VHDL20_DWHG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:16 355914
wst04-VHDL20_DWHH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 331404
wst04-VHDL20_DWHH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 339012
wst04-VHDL20_DWHH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:45:14 340162
wst04-VHDL20_DWHH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 228387
wst04-VHDL20_DWHH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:45:12 341787
wst04-VHDL20_DWHH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:45:18 332569
wst04-VHDL20_DWHH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:45:16 332989
wst04-VHDL20_DWHH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:16 224791
wst04-VHDL20_DWLG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 342645
wst04-VHDL20_DWLG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348845
wst04-VHDL20_DWLG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 348841
wst04-VHDL20_DWLG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 348973
wst04-VHDL20_DWLG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 350185
wst04-VHDL20_DWLG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 393165
wst04-VHDL20_DWLG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:27 347610
wst04-VHDL20_DWLG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 346901
wst04-VHDL20_DWLH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 341229
wst04-VHDL20_DWLH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348533
wst04-VHDL20_DWLH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 347587
wst04-VHDL20_DWLH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 347716
wst04-VHDL20_DWLH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 348956
wst04-VHDL20_DWLH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 392141
wst04-VHDL20_DWLH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 347394
wst04-VHDL20_DWLH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 346199
wst04-VHDL20_DWLI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 390905
wst04-VHDL20_DWLI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:28 354450
wst04-VHDL20_DWLI_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 353539
wst04-VHDL20_DWLI_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 353653
wst04-VHDL20_DWLI_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 399449
wst04-VHDL20_DWLI_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:29 395503
wst04-VHDL20_DWLI_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 349928
wst04-VHDL20_DWLI_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 349436
wst04-VHDL20_DWMO_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:17 467840
wst04-VHDL20_DWMO_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 366447
wst04-VHDL20_DWMO_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 482435
wst04-VHDL20_DWMO_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 482327
wst04-VHDL20_DWMO_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 482491
wst04-VHDL20_DWMO_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 371241
wst04-VHDL20_DWMO_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:19 483816
wst04-VHDL20_DWMO_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:18 483718
wst04-VHDL20_DWMP_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:21 467930
wst04-VHDL20_DWMP_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 490164
wst04-VHDL20_DWMP_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:18 600461
wst04-VHDL20_DWMP_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 599678
wst04-VHDL20_DWMP_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 490297
wst04-VHDL20_DWMP_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 484715
wst04-VHDL20_DWMP_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:19 595962
wst04-VHDL20_DWMP_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:18 596321
wst04-VHDL20_DWPG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:47 390307
wst04-VHDL20_DWPG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 356284
wst04-VHDL20_DWPG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:25 247234
wst04-VHDL20_DWPG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:31 355761
wst04-VHDL20_DWPG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:53 401620
wst04-VHDL20_DWPG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 351741
wst04-VHDL20_DWPG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 246491
wst04-VHDL20_DWPG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:32 350885
wst04-VHDL20_DWPH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 239610
wst04-VHDL20_DWPH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 247781
wst04-VHDL20_DWPH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 247665
wst04-VHDL20_DWPH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:31 247815
wst04-VHDL20_DWPH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 247908
wst04-VHDL20_DWPH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 289943
wst04-VHDL20_DWPH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 245471
wst04-VHDL20_DWPH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:32 245316
wst04-VHDL20_DWSG_180800-2606180800-omedes--0.pdf 18-Jun-2026 14:46:21 365010
wst04-VHDL20_DWSG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 364914
wst04-VHDL20_DWSG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 364114
wst04-VHDL20_DWSG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 364112
wst04-VHDL20_DWSG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 365377
wst04-VHDL20_DWSG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 366288
wst04-VHDL20_DWSG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 363164
wst04-VHDL20_DWSG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 362966