Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Jul-2026 12:28:54 3089
FPDL13_DWMZ_260600 26-Jul-2026 13:09:18 2755
SXDL31_DWAV_250800 25-Jul-2026 07:12:30 15367
SXDL31_DWAV_251800 25-Jul-2026 16:59:39 7451
SXDL31_DWAV_260800 26-Jul-2026 07:41:47 9246
SXDL31_DWAV_261800 26-Jul-2026 15:35:47 9981
SXDL31_DWAV_LATEST 26-Jul-2026 15:35:47 9981
SXDL33_DWAV_250000 25-Jul-2026 10:40:57 8090
SXDL33_DWAV_260000 26-Jul-2026 10:39:20 9080
SXDL33_DWAV_LATEST 26-Jul-2026 10:39:20 9080
ber01-FWDL39_DWMS_251200-2607251200-dsw--0-ia5 25-Jul-2026 10:03:17 1593
ber01-FWDL39_DWMS_261200-2607261200-dsw--0-ia5 26-Jul-2026 11:11:35 1554
ber01-VHDL13_DWEG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:17 2715
ber01-VHDL13_DWEG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:12 2825
ber01-VHDL13_DWEH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:11 2665
ber01-VHDL13_DWEH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:18 3239
ber01-VHDL13_DWEI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:11 2677
ber01-VHDL13_DWEI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:18 2672
ber01-VHDL13_DWHG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 4066
ber01-VHDL13_DWHG_250800_COR-2607250800-dsw--0-ia5 25-Jul-2026 08:51:15 4070
ber01-VHDL13_DWHG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3883
ber01-VHDL13_DWHH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 4207
ber01-VHDL13_DWHH_250800_COR-2607250800-dsw--0-ia5 25-Jul-2026 08:51:45 4211
ber01-VHDL13_DWHH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3752
ber01-VHDL13_DWLG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2024
ber01-VHDL13_DWLG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2508
ber01-VHDL13_DWLH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2297
ber01-VHDL13_DWLH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2931
ber01-VHDL13_DWLI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2025
ber01-VHDL13_DWLI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2418
ber01-VHDL13_DWMO_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2818
ber01-VHDL13_DWMO_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2788
ber01-VHDL13_DWMP_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3207
ber01-VHDL13_DWMP_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3278
ber01-VHDL13_DWOG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3371
ber01-VHDL13_DWOG_251700-2607251700-dsw--0-ia5 25-Jul-2026 18:00:00 3933
ber01-VHDL13_DWOG_260300-2607260300-dsw--0-ia5 26-Jul-2026 03:00:12 3937
ber01-VHDL13_DWOG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 4068
ber01-VHDL13_DWOG_261700-2607261700-dsw--0-ia5 26-Jul-2026 18:00:00 3877
ber01-VHDL13_DWOG_261700_COR-2607261700-dsw--0-ia5 26-Jul-2026 19:10:07 4367
ber01-VHDL13_DWOG_270300-2607270300-dsw--0-ia5 27-Jul-2026 03:00:02 4058
ber01-VHDL13_DWOG_271700_COR-2607271700-dsw--0-ia5 27-Jul-2026 00:31:25 4125
ber01-VHDL13_DWON_250629-2607250629-dsw--0-ia5 25-Jul-2026 06:29:31 3607
ber01-VHDL13_DWON_250709-2607250709-dsw--0-ia5 25-Jul-2026 07:09:32 3657
ber01-VHDL13_DWON_251145-2607251145-dsw--0-ia5 25-Jul-2026 11:45:10 3658
ber01-VHDL13_DWON_251451-2607251451-dsw--0-ia5 25-Jul-2026 14:51:13 3821
ber01-VHDL13_DWON_251732-2607251732-dsw--0-ia5 25-Jul-2026 17:33:00 3331
ber01-VHDL13_DWON_260258-2607260258-dsw--0-ia5 26-Jul-2026 03:00:12 3657
ber01-VHDL13_DWON_260517-2607260517-dsw--0-ia5 26-Jul-2026 05:17:47 3560
ber01-VHDL13_DWON_260615-2607260615-dsw--0-ia5 26-Jul-2026 06:15:17 3435
ber01-VHDL13_DWON_260748-2607260748-dsw--0-ia5 26-Jul-2026 07:48:31 3558
ber01-VHDL13_DWON_261435-2607261435-dsw--0-ia5 26-Jul-2026 14:35:18 3309
ber01-VHDL13_DWON_261631-2607261631-dsw--0-ia5 26-Jul-2026 16:31:16 3083
ber01-VHDL13_DWON_261635-2607261635-dsw--0-ia5 26-Jul-2026 16:36:05 3083
ber01-VHDL13_DWON_261651-2607261651-dsw--0-ia5 26-Jul-2026 16:51:32 3083
ber01-VHDL13_DWON_261909-2607261909-dsw--0-ia5 26-Jul-2026 19:09:52 3542
ber01-VHDL13_DWON_270031-2607270031-dsw--0-ia5 27-Jul-2026 00:31:12 3849
ber01-VHDL13_DWON_270208-2607270208-dsw--0-ia5 27-Jul-2026 02:08:31 3842
ber01-VHDL13_DWON_270526-2607270526-dsw--0-ia5 27-Jul-2026 05:26:11 3868
ber01-VHDL13_DWPG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3006
ber01-VHDL13_DWPG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2884
ber01-VHDL13_DWPH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3262
ber01-VHDL13_DWPH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3152
ber01-VHDL13_DWSG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3507
ber01-VHDL13_DWSG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2748
ber01-VHDL17_DWOG_251200-2607251200-dsw--0-ia5 25-Jul-2026 11:32:05 3024
ber01-VHDL17_DWOG_261200-2607261200-dsw--0-ia5 26-Jul-2026 11:55:42 2730
swis2-VHDL20_DWEG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1218
swis2-VHDL20_DWEG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1285
swis2-VHDL20_DWEG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1036
swis2-VHDL20_DWEG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1231
swis2-VHDL20_DWEG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1404
swis2-VHDL20_DWEG_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:02 1053
swis2-VHDL20_DWEG_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:00 724
swis2-VHDL20_DWEG_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:01:15 912
swis2-VHDL20_DWEH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1202
swis2-VHDL20_DWEH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1259
swis2-VHDL20_DWEH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1083
swis2-VHDL20_DWEH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1478
swis2-VHDL20_DWEH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1742
swis2-VHDL20_DWEH_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:02 1101
swis2-VHDL20_DWEH_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:00 736
swis2-VHDL20_DWEH_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:01:15 921
swis2-VHDL20_DWEI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1254
swis2-VHDL20_DWEI_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:04 1328
swis2-VHDL20_DWEI_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1004
swis2-VHDL20_DWEI_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1188
swis2-VHDL20_DWEI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1361
swis2-VHDL20_DWEI_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:02 981
swis2-VHDL20_DWEI_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:00 744
swis2-VHDL20_DWEI_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:01:15 929
swis2-VHDL20_DWHG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:45:13 2247
swis2-VHDL20_DWHG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:45:07 2000
swis2-VHDL20_DWHG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:45:49 1933
swis2-VHDL20_DWHG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1879
swis2-VHDL20_DWHG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:45:07 2015
swis2-VHDL20_DWHG_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:45:04 1845
swis2-VHDL20_DWHG_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:45:11 1201
swis2-VHDL20_DWHG_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:17 1190
swis2-VHDL20_DWHH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:45:13 2233
swis2-VHDL20_DWHH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:45:07 2162
swis2-VHDL20_DWHH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:45:49 1860
swis2-VHDL20_DWHH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1792
swis2-VHDL20_DWHH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:45:07 2141
swis2-VHDL20_DWHH_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:45:04 1908
swis2-VHDL20_DWHH_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:45:11 1308
swis2-VHDL20_DWHH_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:17 1300
swis2-VHDL20_DWLG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1118
swis2-VHDL20_DWLG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1446
swis2-VHDL20_DWLG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1283
swis2-VHDL20_DWLG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1317
swis2-VHDL20_DWLG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1517
swis2-VHDL20_DWLG_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:31:03 1119
swis2-VHDL20_DWLG_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:26 871
swis2-VHDL20_DWLG_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:11 986
swis2-VHDL20_DWLH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1160
swis2-VHDL20_DWLH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1311
swis2-VHDL20_DWLH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1452
swis2-VHDL20_DWLH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1587
swis2-VHDL20_DWLH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1685
swis2-VHDL20_DWLH_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:31:03 1260
swis2-VHDL20_DWLH_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:26 897
swis2-VHDL20_DWLH_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:11 954
swis2-VHDL20_DWLI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1042
swis2-VHDL20_DWLI_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1314
swis2-VHDL20_DWLI_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1432
swis2-VHDL20_DWLI_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1353
swis2-VHDL20_DWLI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1448
swis2-VHDL20_DWLI_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:31:03 1009
swis2-VHDL20_DWLI_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:26 809
swis2-VHDL20_DWLI_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:11 843
swis2-VHDL20_DWMO_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1345
swis2-VHDL20_DWMO_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:15 1641
swis2-VHDL20_DWMO_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1450
swis2-VHDL20_DWMO_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:02 1466
swis2-VHDL20_DWMO_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1367
swis2-VHDL20_DWMO_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:10 1387
swis2-VHDL20_DWMO_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:08 1051
swis2-VHDL20_DWMO_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:07 1045
swis2-VHDL20_DWMP_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1609
swis2-VHDL20_DWMP_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:15 1812
swis2-VHDL20_DWMP_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1607
swis2-VHDL20_DWMP_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:02 1623
swis2-VHDL20_DWMP_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1720
swis2-VHDL20_DWMP_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:10 1588
swis2-VHDL20_DWMP_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:08 1144
swis2-VHDL20_DWMP_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:07 999
swis2-VHDL20_DWPG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1442
swis2-VHDL20_DWPG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1451
swis2-VHDL20_DWPG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1452
swis2-VHDL20_DWPG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1501
swis2-VHDL20_DWPG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1596
swis2-VHDL20_DWPG_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:31:03 1157
swis2-VHDL20_DWPG_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:26 1101
swis2-VHDL20_DWPG_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:11 905
swis2-VHDL20_DWPH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1603
swis2-VHDL20_DWPH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1582
swis2-VHDL20_DWPH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1596
swis2-VHDL20_DWPH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1652
swis2-VHDL20_DWPH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1746
swis2-VHDL20_DWPH_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:31:03 1370
swis2-VHDL20_DWPH_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:26 1320
swis2-VHDL20_DWPH_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:11 1218
swis2-VHDL20_DWSG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1693
swis2-VHDL20_DWSG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1720
swis2-VHDL20_DWSG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1505
swis2-VHDL20_DWSG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1502
swis2-VHDL20_DWSG_260400_COR-2607260400-dsw--0-ia5 26-Jul-2026 05:00:37 1549
swis2-VHDL20_DWSG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1385
swis2-VHDL20_DWSG_261800-2607261800-dsw--0-ia5 26-Jul-2026 18:30:10 1386
swis2-VHDL20_DWSG_261800_COR-2607261800-dsw--0-ia5 26-Jul-2026 18:42:16 1087
swis2-VHDL20_DWSG_270200-2607270200-dsw--0-ia5 27-Jul-2026 02:30:08 857
swis2-VHDL20_DWSG_270400-2607270400-dsw--0-ia5 27-Jul-2026 05:00:17 1096
wst04-VHDL20_DWEG_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:12 239027
wst04-VHDL20_DWEG_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 238933
wst04-VHDL20_DWEG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 237427
wst04-VHDL20_DWEG_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 237188
wst04-VHDL20_DWEG_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 237991
wst04-VHDL20_DWEG_261800-2607261800-omedes--0.pdf 26-Jul-2026 18:30:17 244365
wst04-VHDL20_DWEG_270200-2607270200-omedes--0.pdf 27-Jul-2026 02:30:17 242273
wst04-VHDL20_DWEG_270400-2607270400-omedes--0.pdf 27-Jul-2026 05:00:11 241823
wst04-VHDL20_DWEH_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:12 238734
wst04-VHDL20_DWEH_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 241019
wst04-VHDL20_DWEH_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 240113
wst04-VHDL20_DWEH_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 240188
wst04-VHDL20_DWEH_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 241111
wst04-VHDL20_DWEH_261800-2607261800-omedes--0.pdf 26-Jul-2026 18:30:17 243517
wst04-VHDL20_DWEH_270200-2607270200-omedes--0.pdf 27-Jul-2026 02:30:17 241931
wst04-VHDL20_DWEH_270400-2607270400-omedes--0.pdf 27-Jul-2026 05:00:11 241757
wst04-VHDL20_DWEI_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:18 340884
wst04-VHDL20_DWEI_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 340346
wst04-VHDL20_DWEI_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:31 339362
wst04-VHDL20_DWEI_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 339053
wst04-VHDL20_DWEI_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 339389
wst04-VHDL20_DWEI_261800-2607261800-omedes--0.pdf 26-Jul-2026 18:30:17 349145
wst04-VHDL20_DWEI_270200-2607270200-omedes--0.pdf 27-Jul-2026 02:30:17 348254
wst04-VHDL20_DWEI_270400-2607270400-omedes--0.pdf 27-Jul-2026 05:00:11 347740
wst04-VHDL20_DWHG_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:45:13 350027
wst04-VHDL20_DWHG_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:45:17 352710
wst04-VHDL20_DWHG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:45:49 352424
wst04-VHDL20_DWHG_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:17 351521
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wst04-VHDL20_DWSG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 341904
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