Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Feb-2026 14:16:05 4410
FPDL13_DWMZ_070600 07-Feb-2026 15:13:00 3199
SXDL31_DWAV_060800 06-Feb-2026 08:36:29 11512
SXDL31_DWAV_061800 06-Feb-2026 17:23:58 10211
SXDL31_DWAV_070800 07-Feb-2026 09:41:55 13488
SXDL31_DWAV_071800 07-Feb-2026 17:42:25 8308
SXDL31_DWAV_LATEST 07-Feb-2026 17:42:25 8308
SXDL33_DWAV_060000 06-Feb-2026 10:48:18 10060
SXDL33_DWAV_070000 07-Feb-2026 11:45:03 10791
SXDL33_DWAV_LATEST 07-Feb-2026 11:45:03 10791
ber01-FWDL39_DWMS_061230-2602061230-dsw--0-ia5 06-Feb-2026 11:50:21 1908
ber01-FWDL39_DWMS_071230-2602071230-dsw--0-ia5 07-Feb-2026 12:40:41 1642
ber01-VHDL13_DWEH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 3561
ber01-VHDL13_DWEH_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:12 3708
ber01-VHDL13_DWEH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:22 3267
ber01-VHDL13_DWEH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:16 2967
ber01-VHDL13_DWEH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:12 3264
ber01-VHDL13_DWEH_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:16 2934
ber01-VHDL13_DWEH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:28:16 2663
ber01-VHDL13_DWEH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:28:17 2620
ber01-VHDL13_DWHG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 3315
ber01-VHDL13_DWHG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 3159
ber01-VHDL13_DWHG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3064
ber01-VHDL13_DWHG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:07 3922
ber01-VHDL13_DWHG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:08 4408
ber01-VHDL13_DWHG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 4378
ber01-VHDL13_DWHG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:05 4307
ber01-VHDL13_DWHG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 3678
ber01-VHDL13_DWHH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 2700
ber01-VHDL13_DWHH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2551
ber01-VHDL13_DWHH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 2599
ber01-VHDL13_DWHH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:07 3035
ber01-VHDL13_DWHH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:08 3377
ber01-VHDL13_DWHH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3557
ber01-VHDL13_DWHH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:05 3490
ber01-VHDL13_DWHH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2917
ber01-VHDL13_DWLG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2096
ber01-VHDL13_DWLG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2285
ber01-VHDL13_DWLG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2180
ber01-VHDL13_DWLG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2080
ber01-VHDL13_DWLG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2517
ber01-VHDL13_DWLG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2274
ber01-VHDL13_DWLG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2189
ber01-VHDL13_DWLG_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:46:07 2193
ber01-VHDL13_DWLG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2313
ber01-VHDL13_DWLH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2186
ber01-VHDL13_DWLH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2174
ber01-VHDL13_DWLH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2210
ber01-VHDL13_DWLH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2454
ber01-VHDL13_DWLH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2617
ber01-VHDL13_DWLH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2235
ber01-VHDL13_DWLH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2181
ber01-VHDL13_DWLH_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:45:52 2185
ber01-VHDL13_DWLH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2221
ber01-VHDL13_DWLI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2161
ber01-VHDL13_DWLI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2211
ber01-VHDL13_DWLI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2218
ber01-VHDL13_DWLI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2113
ber01-VHDL13_DWLI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2219
ber01-VHDL13_DWLI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 1897
ber01-VHDL13_DWLI_070800-2602070800-dsw--0-ia5 07-Feb-2026 17:46:21 1884
ber01-VHDL13_DWLI_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:54:57 1888
ber01-VHDL13_DWLI_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 1953
ber01-VHDL13_DWMG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 3036
ber01-VHDL13_DWMG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 3130
ber01-VHDL13_DWMG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3149
ber01-VHDL13_DWMG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 3272
ber01-VHDL13_DWMG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3417
ber01-VHDL13_DWMG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3110
ber01-VHDL13_DWMG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 3172
ber01-VHDL13_DWMG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2705
ber01-VHDL13_DWMO_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2842
ber01-VHDL13_DWMO_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2823
ber01-VHDL13_DWMO_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 2828
ber01-VHDL13_DWMO_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2939
ber01-VHDL13_DWMO_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3106
ber01-VHDL13_DWMO_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 2876
ber01-VHDL13_DWMO_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2724
ber01-VHDL13_DWMO_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2448
ber01-VHDL13_DWMP_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 3068
ber01-VHDL13_DWMP_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 3142
ber01-VHDL13_DWMP_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:06 3017
ber01-VHDL13_DWMP_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 3066
ber01-VHDL13_DWMP_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 3441
ber01-VHDL13_DWMP_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3110
ber01-VHDL13_DWMP_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 3089
ber01-VHDL13_DWMP_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2561
ber01-VHDL13_DWOG_060300-2602060300-dsw--0-ia5 06-Feb-2026 04:00:02 6001
ber01-VHDL13_DWOG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 5404
ber01-VHDL13_DWOG_061700-2602061700-dsw--0-ia5 06-Feb-2026 19:00:03 5314
ber01-VHDL13_DWOG_070300-2602070300-dsw--0-ia5 07-Feb-2026 04:00:01 5231
ber01-VHDL13_DWOG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:05 4909
ber01-VHDL13_DWOG_071700-2602071700-dsw--0-ia5 07-Feb-2026 19:00:01 4496
ber01-VHDL13_DWOH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 3023
ber01-VHDL13_DWOH_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:16 3153
ber01-VHDL13_DWOH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:12 2976
ber01-VHDL13_DWOH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:16 2691
ber01-VHDL13_DWOH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:16 2919
ber01-VHDL13_DWOH_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:12 2683
ber01-VHDL13_DWOH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:28:16 2417
ber01-VHDL13_DWOH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:28:17 2256
ber01-VHDL13_DWOI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:28:13 2852
ber01-VHDL13_DWOI_060400-2602060400-dsw--0-ia5 06-Feb-2026 05:58:16 2735
ber01-VHDL13_DWOI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:28:12 2419
ber01-VHDL13_DWOI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:28:12 2375
ber01-VHDL13_DWOI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:28:12 2730
ber01-VHDL13_DWOI_070400-2602070400-dsw--0-ia5 07-Feb-2026 05:58:16 2421
ber01-VHDL13_DWOI_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:28:10 2220
ber01-VHDL13_DWOI_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:28:11 2232
ber01-VHDL13_DWON_060147-2602060147-dsw--0-ia5 06-Feb-2026 01:47:51 4491
ber01-VHDL13_DWON_060154-2602060154-dsw--0-ia5 06-Feb-2026 01:54:57 4491
ber01-VHDL13_DWON_060623-2602060623-dsw--0-ia5 06-Feb-2026 06:23:11 4970
ber01-VHDL13_DWON_060716-2602060716-dsw--0-ia5 06-Feb-2026 07:16:47 4964
ber01-VHDL13_DWON_060918-2602060918-dsw--0-ia5 06-Feb-2026 09:18:41 4868
ber01-VHDL13_DWON_061544-2602061544-dsw--0-ia5 06-Feb-2026 15:45:01 4012
ber01-VHDL13_DWON_061829-2602061829-dsw--0-ia5 06-Feb-2026 18:29:59 4037
ber01-VHDL13_DWON_062000-2602062000-dsw--0-ia5 06-Feb-2026 20:00:11 3972
ber01-VHDL13_DWON_070021-2602070021-dsw--0-ia5 07-Feb-2026 00:21:17 3938
ber01-VHDL13_DWON_070354-2602070354-dsw--0-ia5 07-Feb-2026 03:54:42 3938
ber01-VHDL13_DWON_070630-2602070630-dsw--0-ia5 07-Feb-2026 06:30:16 3846
ber01-VHDL13_DWON_070657-2602070657-dsw--0-ia5 07-Feb-2026 06:57:17 3841
ber01-VHDL13_DWON_070915-2602070915-dsw--0-ia5 07-Feb-2026 09:15:22 3841
ber01-VHDL13_DWON_071247-2602071247-dsw--0-ia5 07-Feb-2026 12:47:07 3841
ber01-VHDL13_DWON_071641-2602071641-dsw--0-ia5 07-Feb-2026 16:41:21 3769
ber01-VHDL13_DWON_071819-2602071819-dsw--0-ia5 07-Feb-2026 18:19:21 3827
ber01-VHDL13_DWON_072033-2602072033-dsw--0-ia5 07-Feb-2026 20:33:21 3827
ber01-VHDL13_DWON_072221-2602072221-dsw--0-ia5 07-Feb-2026 22:21:31 3785
ber01-VHDL13_DWON_080047-2602080047-dsw--0-ia5 08-Feb-2026 00:47:17 3991
ber01-VHDL13_DWPG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2275
ber01-VHDL13_DWPG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2328
ber01-VHDL13_DWPG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2087
ber01-VHDL13_DWPG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2571
ber01-VHDL13_DWPG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2509
ber01-VHDL13_DWPG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2514
ber01-VHDL13_DWPG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2367
ber01-VHDL13_DWPG_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:45:26 2667
ber01-VHDL13_DWPG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2591
ber01-VHDL13_DWPH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:02 2716
ber01-VHDL13_DWPH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:01 2562
ber01-VHDL13_DWPH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2617
ber01-VHDL13_DWPH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2610
ber01-VHDL13_DWPH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:00 2538
ber01-VHDL13_DWPH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:00 2491
ber01-VHDL13_DWPH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2442
ber01-VHDL13_DWPH_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:48:32 2641
ber01-VHDL13_DWPH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:09 2566
ber01-VHDL13_DWSG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:30:08 2663
ber01-VHDL13_DWSG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2653
ber01-VHDL13_DWSG_060400_COR-2602060400-dsw--0-ia5 06-Feb-2026 06:36:24 2854
ber01-VHDL13_DWSG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:30:02 2817
ber01-VHDL13_DWSG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:30:02 2398
ber01-VHDL13_DWSG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:30:02 2566
ber01-VHDL13_DWSG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 2417
ber01-VHDL13_DWSG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:30:02 2375
ber01-VHDL13_DWSG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:30:01 2253
ber01-VHDL17_DWOG_061200-2602061200-dsw--0-ia5 06-Feb-2026 12:37:03 3420
ber01-VHDL17_DWOG_071200-2602071200-dsw--0-ia5 07-Feb-2026 12:41:00 3340
swis2-VHDL20_DWEG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3359
swis2-VHDL20_DWEG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3634
swis2-VHDL20_DWEG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3683
swis2-VHDL20_DWEG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 3160
swis2-VHDL20_DWEG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3313
swis2-VHDL20_DWEG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3075
swis2-VHDL20_DWEG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 3039
swis2-VHDL20_DWEG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 2654
swis2-VHDL20_DWEH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 4219
swis2-VHDL20_DWEH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 4202
swis2-VHDL20_DWEH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 4028
swis2-VHDL20_DWEH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 3501
swis2-VHDL20_DWEH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3742
swis2-VHDL20_DWEH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3372
swis2-VHDL20_DWEH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:06 3341
swis2-VHDL20_DWEH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 3077
swis2-VHDL20_DWEI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3309
swis2-VHDL20_DWEI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3090
swis2-VHDL20_DWEI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3013
swis2-VHDL20_DWEI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:06 2730
swis2-VHDL20_DWEI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3026
swis2-VHDL20_DWEI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 2830
swis2-VHDL20_DWEI_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2857
swis2-VHDL20_DWEI_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 2641
swis2-VHDL20_DWHG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3501
swis2-VHDL20_DWHG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 3342
swis2-VHDL20_DWHG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3866
swis2-VHDL20_DWHG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 4105
swis2-VHDL20_DWHG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 4594
swis2-VHDL20_DWHG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 4561
swis2-VHDL20_DWHG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 5056
swis2-VHDL20_DWHG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 3861
swis2-VHDL20_DWHH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2886
swis2-VHDL20_DWHH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:07 2737
swis2-VHDL20_DWHH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3432
swis2-VHDL20_DWHH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3221
swis2-VHDL20_DWHH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3563
swis2-VHDL20_DWHH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:07 3743
swis2-VHDL20_DWHH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 4243
swis2-VHDL20_DWHH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 3103
swis2-VHDL20_DWLG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2514
swis2-VHDL20_DWLG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2685
swis2-VHDL20_DWLG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2793
swis2-VHDL20_DWLG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2480
swis2-VHDL20_DWLG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2917
swis2-VHDL20_DWLG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2695
swis2-VHDL20_DWLG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2780
swis2-VHDL20_DWLG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 2734
swis2-VHDL20_DWLH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2611
swis2-VHDL20_DWLH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2581
swis2-VHDL20_DWLH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2835
swis2-VHDL20_DWLH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2866
swis2-VHDL20_DWLH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 3029
swis2-VHDL20_DWLH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2664
swis2-VHDL20_DWLH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2784
swis2-VHDL20_DWLH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 2611
swis2-VHDL20_DWLI_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2582
swis2-VHDL20_DWLI_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2613
swis2-VHDL20_DWLI_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2832
swis2-VHDL20_DWLI_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2514
swis2-VHDL20_DWLI_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2620
swis2-VHDL20_DWLI_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2308
swis2-VHDL20_DWLI_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2464
swis2-VHDL20_DWLI_070800_COR-2602070800-dsw--0-ia5 07-Feb-2026 17:50:21 2468
swis2-VHDL20_DWLI_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 2334
swis2-VHDL20_DWMG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3456
swis2-VHDL20_DWMG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3722
swis2-VHDL20_DWMG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3965
swis2-VHDL20_DWMG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3812
swis2-VHDL20_DWMG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 4023
swis2-VHDL20_DWMG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3533
swis2-VHDL20_DWMG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 3832
swis2-VHDL20_DWMG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 3216
swis2-VHDL20_DWMO_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3264
swis2-VHDL20_DWMO_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3419
swis2-VHDL20_DWMO_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3634
swis2-VHDL20_DWMO_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3483
swis2-VHDL20_DWMO_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 3652
swis2-VHDL20_DWMO_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3296
swis2-VHDL20_DWMO_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 3371
swis2-VHDL20_DWMO_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 2944
swis2-VHDL20_DWMP_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3489
swis2-VHDL20_DWMP_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3692
swis2-VHDL20_DWMP_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3584
swis2-VHDL20_DWMP_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 3972
swis2-VHDL20_DWMP_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:06 3500
swis2-VHDL20_DWMP_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 3753
swis2-VHDL20_DWMP_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:04 3024
swis2-VHDL20_DWPG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 2669
swis2-VHDL20_DWPG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2699
swis2-VHDL20_DWPG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 2658
swis2-VHDL20_DWPG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3142
swis2-VHDL20_DWPG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2883
swis2-VHDL20_DWPG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2907
swis2-VHDL20_DWPG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2917
swis2-VHDL20_DWPG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 3341
swis2-VHDL20_DWPH_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:04 3087
swis2-VHDL20_DWPH_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:00:11 2936
swis2-VHDL20_DWPH_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:02 3190
swis2-VHDL20_DWPH_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 3183
swis2-VHDL20_DWPH_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:10 2912
swis2-VHDL20_DWPH_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:00:11 2886
swis2-VHDL20_DWPH_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2993
swis2-VHDL20_DWPH_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 3316
swis2-VHDL20_DWSG_060200-2602060200-dsw--0-ia5 06-Feb-2026 03:45:06 3126
swis2-VHDL20_DWSG_060400-2602060400-dsw--0-ia5 06-Feb-2026 06:15:01 3130
swis2-VHDL20_DWSG_060400_COR-2602060400-dsw--0-ia5 06-Feb-2026 06:36:24 3259
swis2-VHDL20_DWSG_060800-2602060800-dsw--0-ia5 06-Feb-2026 09:45:06 3388
swis2-VHDL20_DWSG_061300-2602061300-dsw--0-ia5 06-Feb-2026 14:45:04 3247
swis2-VHDL20_DWSG_061800-2602061800-dsw--0-ia5 06-Feb-2026 19:45:02 2805
swis2-VHDL20_DWSG_070200-2602070200-dsw--0-ia5 07-Feb-2026 03:45:04 2963
swis2-VHDL20_DWSG_070400-2602070400-dsw--0-ia5 07-Feb-2026 06:15:02 2829
swis2-VHDL20_DWSG_070800-2602070800-dsw--0-ia5 07-Feb-2026 09:45:02 2987
swis2-VHDL20_DWSG_071300-2602071300-dsw--0-ia5 07-Feb-2026 14:45:01 2781
swis2-VHDL20_DWSG_071800-2602071800-dsw--0-ia5 07-Feb-2026 19:45:06 2667
wst04-VHDL20_DWEG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 226759
wst04-VHDL20_DWEG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:20 226560
wst04-VHDL20_DWEG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 227127
wst04-VHDL20_DWEG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 224436
wst04-VHDL20_DWEG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 225413
wst04-VHDL20_DWEG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 224064
wst04-VHDL20_DWEG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:16 233088
wst04-VHDL20_DWEG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:12 231387
wst04-VHDL20_DWEH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 229077
wst04-VHDL20_DWEH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:18 228513
wst04-VHDL20_DWEH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 228733
wst04-VHDL20_DWEH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 225291
wst04-VHDL20_DWEH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 225737
wst04-VHDL20_DWEH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:26 224884
wst04-VHDL20_DWEH_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:16 229066
wst04-VHDL20_DWEH_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:12 227747
wst04-VHDL20_DWEI_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 318477
wst04-VHDL20_DWEI_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:20 318362
wst04-VHDL20_DWEI_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 318447
wst04-VHDL20_DWEI_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:10 316284
wst04-VHDL20_DWEI_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 316919
wst04-VHDL20_DWEI_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 316299
wst04-VHDL20_DWEI_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:16 321792
wst04-VHDL20_DWEI_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:12 321525
wst04-VHDL20_DWHG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 299327
wst04-VHDL20_DWHG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:11 298945
wst04-VHDL20_DWHG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 299715
wst04-VHDL20_DWHG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 302047
wst04-VHDL20_DWHG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 303410
wst04-VHDL20_DWHG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:11 303394
wst04-VHDL20_DWHG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:26 310698
wst04-VHDL20_DWHG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:22 307926
wst04-VHDL20_DWHH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 290088
wst04-VHDL20_DWHH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:11 289702
wst04-VHDL20_DWHH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 290061
wst04-VHDL20_DWHH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 287636
wst04-VHDL20_DWHH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 288094
wst04-VHDL20_DWHH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:11 288344
wst04-VHDL20_DWHH_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:22 296391
wst04-VHDL20_DWHH_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:16 295179
wst04-VHDL20_DWLG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 301896
wst04-VHDL20_DWLG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 301820
wst04-VHDL20_DWLG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 302056
wst04-VHDL20_DWLG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:26 295617
wst04-VHDL20_DWLG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 296111
wst04-VHDL20_DWLG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 295814
wst04-VHDL20_DWLG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:32 307764
wst04-VHDL20_DWLG_070800_COR-2602070800-omedes-..> 07-Feb-2026 17:50:01 308070
wst04-VHDL20_DWLG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:20 307617
wst04-VHDL20_DWLH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 297097
wst04-VHDL20_DWLH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 296826
wst04-VHDL20_DWLH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:32 296967
wst04-VHDL20_DWLH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 295245
wst04-VHDL20_DWLH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:26 295539
wst04-VHDL20_DWLH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 295353
wst04-VHDL20_DWLH_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:32 302461
wst04-VHDL20_DWLH_070800_COR-2602070800-omedes-..> 07-Feb-2026 17:49:35 302813
wst04-VHDL20_DWLH_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:26 301689
wst04-VHDL20_DWLI_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:26 288550
wst04-VHDL20_DWLI_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:41 288709
wst04-VHDL20_DWLI_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 288875
wst04-VHDL20_DWLI_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 290005
wst04-VHDL20_DWLI_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 290046
wst04-VHDL20_DWLI_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:41 289553
wst04-VHDL20_DWLI_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:26 297687
wst04-VHDL20_DWLI_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:20 297095
wst04-VHDL20_DWMG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 500585
wst04-VHDL20_DWMG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:16 500552
wst04-VHDL20_DWMG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:21 501515
wst04-VHDL20_DWMG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 499695
wst04-VHDL20_DWMG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 500460
wst04-VHDL20_DWMG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:16 499313
wst04-VHDL20_DWMG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:12 504814
wst04-VHDL20_DWMG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:16 503790
wst04-VHDL20_DWMO_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 400036
wst04-VHDL20_DWMO_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:16 400432
wst04-VHDL20_DWMO_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 400266
wst04-VHDL20_DWMO_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 402236
wst04-VHDL20_DWMO_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 402499
wst04-VHDL20_DWMO_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:16 402414
wst04-VHDL20_DWMO_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:12 406838
wst04-VHDL20_DWMO_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:16 406029
wst04-VHDL20_DWMP_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:16 534608
wst04-VHDL20_DWMP_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:22 535556
wst04-VHDL20_DWMP_060400_COR-2602060400-omedes-..> 06-Feb-2026 11:48:52 523189
wst04-VHDL20_DWMP_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:15 536571
wst04-VHDL20_DWMP_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:16 524042
wst04-VHDL20_DWMP_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:16 523596
wst04-VHDL20_DWMP_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:22 523948
wst04-VHDL20_DWMP_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:18 518778
wst04-VHDL20_DWMP_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:16 517764
wst04-VHDL20_DWPG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:26 304457
wst04-VHDL20_DWPG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:31 304420
wst04-VHDL20_DWPG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:32 348915
wst04-VHDL20_DWPG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:26 306531
wst04-VHDL20_DWPG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:26 306270
wst04-VHDL20_DWPG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:31 306069
wst04-VHDL20_DWPG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:32 353550
wst04-VHDL20_DWPG_070800_COR-2602070800-omedes-..> 07-Feb-2026 17:48:57 353787
wst04-VHDL20_DWPG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:26 309145
wst04-VHDL20_DWPH_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:22 221090
wst04-VHDL20_DWPH_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:00:31 220775
wst04-VHDL20_DWPH_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:27 265879
wst04-VHDL20_DWPH_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:22 266076
wst04-VHDL20_DWPH_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:22 220611
wst04-VHDL20_DWPH_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:00:31 220830
wst04-VHDL20_DWPH_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:26 269428
wst04-VHDL20_DWPH_070800_COR-2602070800-omedes-..> 07-Feb-2026 17:49:16 270671
wst04-VHDL20_DWPH_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:20 270249
wst04-VHDL20_DWSG_060200-2602060200-omedes--0.pdf 06-Feb-2026 03:45:12 325642
wst04-VHDL20_DWSG_060400-2602060400-omedes--0.pdf 06-Feb-2026 06:15:12 326162
wst04-VHDL20_DWSG_060400_COR-2602060400-omedes-..> 06-Feb-2026 06:36:24 326177
wst04-VHDL20_DWSG_060800-2602060800-omedes--0.pdf 06-Feb-2026 09:45:12 326295
wst04-VHDL20_DWSG_061300-2602061300-omedes--0.pdf 06-Feb-2026 14:45:12 329394
wst04-VHDL20_DWSG_061800-2602061800-omedes--0.pdf 06-Feb-2026 19:45:12 328994
wst04-VHDL20_DWSG_070200-2602070200-omedes--0.pdf 07-Feb-2026 03:45:12 328849
wst04-VHDL20_DWSG_070400-2602070400-omedes--0.pdf 07-Feb-2026 06:15:12 328690
wst04-VHDL20_DWSG_070800-2602070800-omedes--0.pdf 07-Feb-2026 09:45:12 317287
wst04-VHDL20_DWSG_071300-2602071300-omedes--0.pdf 07-Feb-2026 14:45:12 317463
wst04-VHDL20_DWSG_071800-2602071800-omedes--0.pdf 07-Feb-2026 19:45:12 317413