Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_300600 30-May-2025 11:44:33 4452
FPDL13_DWMZ_310600 31-May-2025 13:35:46 3410
SXDL31_DWAV_010800 01-Jun-2025 06:55:08 8256
SXDL31_DWAV_301800 30-May-2025 16:35:24 8211
SXDL31_DWAV_310800 31-May-2025 07:58:14 10368
SXDL31_DWAV_311800 31-May-2025 17:19:15 6323
SXDL31_DWAV_LATEST 01-Jun-2025 06:55:08 8256
SXDL33_DWAV_300000 30-May-2025 09:40:10 7162
SXDL33_DWAV_310000 31-May-2025 10:31:13 12742
SXDL33_DWAV_LATEST 31-May-2025 10:31:13 12742
ber01-FWDL39_DWMS_301230-2505301230-dsw--0-ia5 30-May-2025 11:47:01 1092
ber01-FWDL39_DWMS_311230-2505311230-dsw--0-ia5 31-May-2025 11:49:47 1259
ber01-VHDL13_DWEH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:28:11 2992
ber01-VHDL13_DWEH_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:58:07 2933
ber01-VHDL13_DWEH_300800-2505300800-dsw--0-ia5 30-May-2025 08:28:12 3027
ber01-VHDL13_DWEH_301800-2505301800-dsw--0-ia5 30-May-2025 18:28:11 3264
ber01-VHDL13_DWEH_310200-2505310200-dsw--0-ia5 31-May-2025 02:28:06 3445
ber01-VHDL13_DWEH_310400-2505310400-dsw--0-ia5 31-May-2025 04:58:11 3532
ber01-VHDL13_DWEH_310800-2505310800-dsw--0-ia5 31-May-2025 08:28:11 3511
ber01-VHDL13_DWEH_311800-2505311800-dsw--0-ia5 31-May-2025 18:28:11 2730
ber01-VHDL13_DWHG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:06 3202
ber01-VHDL13_DWHG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 3120
ber01-VHDL13_DWHG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:07 3261
ber01-VHDL13_DWHG_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2655
ber01-VHDL13_DWHG_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:06 3094
ber01-VHDL13_DWHG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 3090
ber01-VHDL13_DWHG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 3707
ber01-VHDL13_DWHG_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:06 3153
ber01-VHDL13_DWHH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:06 3128
ber01-VHDL13_DWHH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 3074
ber01-VHDL13_DWHH_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:07 3159
ber01-VHDL13_DWHH_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2570
ber01-VHDL13_DWHH_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:06 2822
ber01-VHDL13_DWHH_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 2808
ber01-VHDL13_DWHH_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 3435
ber01-VHDL13_DWHH_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:06 3170
ber01-VHDL13_DWLG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2667
ber01-VHDL13_DWLG_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:59:57 2547
ber01-VHDL13_DWLG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:07 2527
ber01-VHDL13_DWLG_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2309
ber01-VHDL13_DWLG_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2502
ber01-VHDL13_DWLG_310400-2505310400-dsw--0-ia5 31-May-2025 04:59:57 2580
ber01-VHDL13_DWLG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 2590
ber01-VHDL13_DWLG_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2534
ber01-VHDL13_DWLH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2455
ber01-VHDL13_DWLH_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:59:57 2262
ber01-VHDL13_DWLH_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:07 2521
ber01-VHDL13_DWLH_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2273
ber01-VHDL13_DWLH_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2419
ber01-VHDL13_DWLH_310400-2505310400-dsw--0-ia5 31-May-2025 04:59:57 2436
ber01-VHDL13_DWLH_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 2574
ber01-VHDL13_DWLH_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2400
ber01-VHDL13_DWLI_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2704
ber01-VHDL13_DWLI_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:59:57 2527
ber01-VHDL13_DWLI_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:07 2481
ber01-VHDL13_DWLI_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2237
ber01-VHDL13_DWLI_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2459
ber01-VHDL13_DWLI_310400-2505310400-dsw--0-ia5 31-May-2025 04:59:57 2585
ber01-VHDL13_DWLI_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 2600
ber01-VHDL13_DWLI_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2557
ber01-VHDL13_DWMG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2657
ber01-VHDL13_DWMG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2700
ber01-VHDL13_DWMG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 3174
ber01-VHDL13_DWMG_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2789
ber01-VHDL13_DWMG_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 3123
ber01-VHDL13_DWMG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3141
ber01-VHDL13_DWMG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 3305
ber01-VHDL13_DWMG_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2868
ber01-VHDL13_DWMO_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2727
ber01-VHDL13_DWMO_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2727
ber01-VHDL13_DWMO_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 3193
ber01-VHDL13_DWMO_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2736
ber01-VHDL13_DWMO_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 3132
ber01-VHDL13_DWMO_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3150
ber01-VHDL13_DWMO_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 3303
ber01-VHDL13_DWMO_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2749
ber01-VHDL13_DWMP_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2632
ber01-VHDL13_DWMP_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2632
ber01-VHDL13_DWMP_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 3100
ber01-VHDL13_DWMP_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:01 2604
ber01-VHDL13_DWMP_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2982
ber01-VHDL13_DWMP_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3000
ber01-VHDL13_DWMP_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:08 3102
ber01-VHDL13_DWMP_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2661
ber01-VHDL13_DWMP_311800_COR-2505311800-dsw--0-ia5 31-May-2025 18:38:52 2791
ber01-VHDL13_DWOG_010300-2506010300-dsw--0-ia5 01-Jun-2025 03:00:09 3973
ber01-VHDL13_DWOG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 3926
ber01-VHDL13_DWOG_301700-2505301700-dsw--0-ia5 30-May-2025 18:00:01 3659
ber01-VHDL13_DWOG_310300-2505310300-dsw--0-ia5 31-May-2025 03:00:08 4906
ber01-VHDL13_DWOG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 4802
ber01-VHDL13_DWOG_311700-2505311700-dsw--0-ia5 31-May-2025 18:00:08 4057
ber01-VHDL13_DWOH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:28:07 2969
ber01-VHDL13_DWOH_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:58:11 3041
ber01-VHDL13_DWOH_300800-2505300800-dsw--0-ia5 30-May-2025 08:28:12 2788
ber01-VHDL13_DWOH_301800-2505301800-dsw--0-ia5 30-May-2025 18:28:11 3076
ber01-VHDL13_DWOH_310200-2505310200-dsw--0-ia5 31-May-2025 02:28:12 3219
ber01-VHDL13_DWOH_310400-2505310400-dsw--0-ia5 31-May-2025 04:58:11 3422
ber01-VHDL13_DWOH_310800-2505310800-dsw--0-ia5 31-May-2025 08:28:11 3422
ber01-VHDL13_DWOH_311800-2505311800-dsw--0-ia5 31-May-2025 18:28:11 2768
ber01-VHDL13_DWOI_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:28:11 3179
ber01-VHDL13_DWOI_010400-2506010400-dsw--0-ia5 01-Jun-2025 04:58:11 3115
ber01-VHDL13_DWOI_300800-2505300800-dsw--0-ia5 30-May-2025 08:28:08 2969
ber01-VHDL13_DWOI_301800-2505301800-dsw--0-ia5 30-May-2025 18:28:07 3268
ber01-VHDL13_DWOI_310200-2505310200-dsw--0-ia5 31-May-2025 02:28:12 3375
ber01-VHDL13_DWOI_310400-2505310400-dsw--0-ia5 31-May-2025 04:58:11 3584
ber01-VHDL13_DWOI_310800-2505310800-dsw--0-ia5 31-May-2025 08:28:11 3620
ber01-VHDL13_DWOI_311800-2505311800-dsw--0-ia5 31-May-2025 18:28:05 3122
ber01-VHDL13_DWON_010119-2506010119-dsw--0-ia5 01-Jun-2025 01:19:11 3445
ber01-VHDL13_DWON_010517-2506010517-dsw--0-ia5 01-Jun-2025 05:17:12 3691
ber01-VHDL13_DWON_010608-2506010608-dsw--0-ia5 01-Jun-2025 06:09:01 3735
ber01-VHDL13_DWON_010615-2506010615-dsw--0-ia5 01-Jun-2025 06:15:56 3758
ber01-VHDL13_DWON_301507-2505301507-dsw--0-ia5 30-May-2025 15:07:23 3682
ber01-VHDL13_DWON_301717-2505301717-dsw--0-ia5 30-May-2025 17:17:57 3296
ber01-VHDL13_DWON_301830-2505301830-dsw--0-ia5 30-May-2025 18:30:52 4049
ber01-VHDL13_DWON_301938-2505301938-dsw--0-ia5 30-May-2025 19:39:01 4030
ber01-VHDL13_DWON_302131-2505302131-dsw--0-ia5 30-May-2025 21:31:27 4042
ber01-VHDL13_DWON_302148-2505302148-dsw--0-ia5 30-May-2025 21:48:32 4042
ber01-VHDL13_DWON_310002-2505310002-dsw--0-ia5 31-May-2025 00:02:21 4557
ber01-VHDL13_DWON_310140-2505310140-dsw--0-ia5 31-May-2025 01:40:46 4347
ber01-VHDL13_DWON_310242-2505310242-dsw--0-ia5 31-May-2025 02:42:47 4347
ber01-VHDL13_DWON_310517-2505310517-dsw--0-ia5 31-May-2025 05:17:05 4160
ber01-VHDL13_DWON_310536-2505310536-dsw--0-ia5 31-May-2025 05:36:50 4227
ber01-VHDL13_DWON_311109-2505311109-dsw--0-ia5 31-May-2025 11:09:52 4227
ber01-VHDL13_DWON_311425-2505311425-dsw--0-ia5 31-May-2025 14:25:41 3908
ber01-VHDL13_DWON_311743-2505311743-dsw--0-ia5 31-May-2025 17:43:51 3173
ber01-VHDL13_DWPG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:06 2585
ber01-VHDL13_DWPG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:01 2551
ber01-VHDL13_DWPG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 2855
ber01-VHDL13_DWPG_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2439
ber01-VHDL13_DWPG_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2567
ber01-VHDL13_DWPG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:07 2609
ber01-VHDL13_DWPG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 2612
ber01-VHDL13_DWPG_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:06 2557
ber01-VHDL13_DWPH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:06 2689
ber01-VHDL13_DWPH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:01 2566
ber01-VHDL13_DWPH_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 2707
ber01-VHDL13_DWPH_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2156
ber01-VHDL13_DWPH_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 2414
ber01-VHDL13_DWPH_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:07 2409
ber01-VHDL13_DWPH_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 2426
ber01-VHDL13_DWPH_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:06 2574
ber01-VHDL13_DWSG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:30:02 2871
ber01-VHDL13_DWSG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 2871
ber01-VHDL13_DWSG_010400_COR-2506010400-dsw--0-ia5 01-Jun-2025 05:44:06 3572
ber01-VHDL13_DWSG_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 2383
ber01-VHDL13_DWSG_300800_COR-2505300800-dsw--0-ia5 30-May-2025 14:57:36 3080
ber01-VHDL13_DWSG_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2878
ber01-VHDL13_DWSG_310200-2505310200-dsw--0-ia5 31-May-2025 02:30:02 3239
ber01-VHDL13_DWSG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 3665
ber01-VHDL13_DWSG_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 3670
ber01-VHDL13_DWSG_310800_COR-2505310800-dsw--0-ia5 31-May-2025 14:45:44 3522
ber01-VHDL13_DWSG_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2918
ber01-VHDL13_DWSN_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 2649
ber01-VHDL13_DWSN_010400_COR-2506010400-dsw--0-ia5 01-Jun-2025 05:44:06 3201
ber01-VHDL13_DWSN_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 1905
ber01-VHDL13_DWSN_300800_COR-2505300800-dsw--0-ia5 30-May-2025 15:00:33 2451
ber01-VHDL13_DWSN_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2257
ber01-VHDL13_DWSN_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 2498
ber01-VHDL13_DWSN_310400_COR-2505310400-dsw--0-ia5 31-May-2025 05:08:57 2904
ber01-VHDL13_DWSN_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 2899
ber01-VHDL13_DWSN_310800_COR-2505310800-dsw--0-ia5 31-May-2025 14:46:15 2843
ber01-VHDL13_DWSN_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2412
ber01-VHDL13_DWSO_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 3265
ber01-VHDL13_DWSO_010400_COR-2506010400-dsw--0-ia5 01-Jun-2025 05:44:06 3457
ber01-VHDL13_DWSO_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 2388
ber01-VHDL13_DWSO_300800_COR-2505300800-dsw--0-ia5 30-May-2025 15:01:01 2996
ber01-VHDL13_DWSO_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2804
ber01-VHDL13_DWSO_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 3163
ber01-VHDL13_DWSO_310400_COR-2505310400-dsw--0-ia5 31-May-2025 05:08:57 3620
ber01-VHDL13_DWSO_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 3608
ber01-VHDL13_DWSO_310800_COR-2505310800-dsw--0-ia5 31-May-2025 14:46:34 3540
ber01-VHDL13_DWSO_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2951
ber01-VHDL13_DWSP_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 2882
ber01-VHDL13_DWSP_010400_COR-2506010400-dsw--0-ia5 01-Jun-2025 05:44:06 3102
ber01-VHDL13_DWSP_300800-2505300800-dsw--0-ia5 30-May-2025 08:30:02 2191
ber01-VHDL13_DWSP_300800_COR-2505300800-dsw--0-ia5 30-May-2025 08:49:11 2605
ber01-VHDL13_DWSP_301800-2505301800-dsw--0-ia5 30-May-2025 18:30:09 2407
ber01-VHDL13_DWSP_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 2648
ber01-VHDL13_DWSP_310400_COR-2505310400-dsw--0-ia5 31-May-2025 05:08:51 2945
ber01-VHDL13_DWSP_310800-2505310800-dsw--0-ia5 31-May-2025 08:30:04 2970
ber01-VHDL13_DWSP_310800_COR-2505310800-dsw--0-ia5 31-May-2025 14:46:38 3183
ber01-VHDL13_DWSP_311800-2505311800-dsw--0-ia5 31-May-2025 18:30:03 2631
ber01-VHDL17_DWOG_301200-2505301200-dsw--0-ia5 30-May-2025 11:38:00 3249
ber01-VHDL17_DWOG_311200-2505311200-dsw--0-ia5 31-May-2025 11:55:51 4475
swis2-VHDL20_DWEG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3101
swis2-VHDL20_DWEG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:15:03 3249
swis2-VHDL20_DWEG_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:06 2967
swis2-VHDL20_DWEG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 3261
swis2-VHDL20_DWEG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3351
swis2-VHDL20_DWEG_310400-2505310400-dsw--0-ia5 31-May-2025 05:15:02 3630
swis2-VHDL20_DWEG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 3601
swis2-VHDL20_DWEG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2953
swis2-VHDL20_DWEH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3156
swis2-VHDL20_DWEH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:15:11 3111
swis2-VHDL20_DWEH_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:06 3205
swis2-VHDL20_DWEH_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:06 3464
swis2-VHDL20_DWEH_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3609
swis2-VHDL20_DWEH_310400-2505310400-dsw--0-ia5 31-May-2025 05:15:12 3710
swis2-VHDL20_DWEH_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:06 3689
swis2-VHDL20_DWEH_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:06 2930
swis2-VHDL20_DWEI_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3312
swis2-VHDL20_DWEI_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:15:11 3300
swis2-VHDL20_DWEI_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:06 3148
swis2-VHDL20_DWEI_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 3453
swis2-VHDL20_DWEI_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3508
swis2-VHDL20_DWEI_310400-2505310400-dsw--0-ia5 31-May-2025 05:15:12 3769
swis2-VHDL20_DWEI_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 3799
swis2-VHDL20_DWEI_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 3307
swis2-VHDL20_DWHG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3388
swis2-VHDL20_DWHG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 3303
swis2-VHDL20_DWHG_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:06 3444
swis2-VHDL20_DWHG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:06 2838
swis2-VHDL20_DWHG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3280
swis2-VHDL20_DWHG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 3273
swis2-VHDL20_DWHG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 3890
swis2-VHDL20_DWHG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:06 3336
swis2-VHDL20_DWHH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3314
swis2-VHDL20_DWHH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:11 3260
swis2-VHDL20_DWHH_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:06 3345
swis2-VHDL20_DWHH_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:06 2756
swis2-VHDL20_DWHH_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3008
swis2-VHDL20_DWHH_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:11 2994
swis2-VHDL20_DWHH_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 3621
swis2-VHDL20_DWHH_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:06 3356
swis2-VHDL20_DWLG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2888
swis2-VHDL20_DWLG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:21 2768
swis2-VHDL20_DWLG_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 2751
swis2-VHDL20_DWLG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2530
swis2-VHDL20_DWLG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 2723
swis2-VHDL20_DWLG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:21 2792
swis2-VHDL20_DWLG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 2814
swis2-VHDL20_DWLG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2755
swis2-VHDL20_DWLH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2676
swis2-VHDL20_DWLH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:21 2483
swis2-VHDL20_DWLH_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 2742
swis2-VHDL20_DWLH_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2494
swis2-VHDL20_DWLH_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 2640
swis2-VHDL20_DWLH_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:21 2720
swis2-VHDL20_DWLH_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 2795
swis2-VHDL20_DWLH_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2621
swis2-VHDL20_DWLI_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2925
swis2-VHDL20_DWLI_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:21 2745
swis2-VHDL20_DWLI_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 2702
swis2-VHDL20_DWLI_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2458
swis2-VHDL20_DWLI_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 2680
swis2-VHDL20_DWLI_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:21 2796
swis2-VHDL20_DWLI_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 2821
swis2-VHDL20_DWLI_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2778
swis2-VHDL20_DWMG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2871
swis2-VHDL20_DWMG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2911
swis2-VHDL20_DWMG_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 3385
swis2-VHDL20_DWMG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 3000
swis2-VHDL20_DWMG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3311
swis2-VHDL20_DWMG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3352
swis2-VHDL20_DWMG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:06 3516
swis2-VHDL20_DWMG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 3079
swis2-VHDL20_DWMO_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2942
swis2-VHDL20_DWMO_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2942
swis2-VHDL20_DWMO_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 3405
swis2-VHDL20_DWMO_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2948
swis2-VHDL20_DWMO_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3347
swis2-VHDL20_DWMO_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3365
swis2-VHDL20_DWMO_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:06 3515
swis2-VHDL20_DWMO_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2922
swis2-VHDL20_DWMP_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2844
swis2-VHDL20_DWMP_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:07 2844
swis2-VHDL20_DWMP_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 3312
swis2-VHDL20_DWMP_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2835
swis2-VHDL20_DWMP_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3194
swis2-VHDL20_DWMP_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:01 3212
swis2-VHDL20_DWMP_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:06 3314
swis2-VHDL20_DWMP_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2985
swis2-VHDL20_DWPG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2782
swis2-VHDL20_DWPG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:01 2746
swis2-VHDL20_DWPG_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 3052
swis2-VHDL20_DWPG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2636
swis2-VHDL20_DWPG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 2764
swis2-VHDL20_DWPG_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:07 2804
swis2-VHDL20_DWPG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 2809
swis2-VHDL20_DWPG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2754
swis2-VHDL20_DWPH_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 2886
swis2-VHDL20_DWPH_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:00:01 2763
swis2-VHDL20_DWPH_300800-2505300800-dsw--0-ia5 30-May-2025 08:45:02 2904
swis2-VHDL20_DWPH_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:04 2353
swis2-VHDL20_DWPH_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 2611
swis2-VHDL20_DWPH_310400-2505310400-dsw--0-ia5 31-May-2025 05:00:07 2606
swis2-VHDL20_DWPH_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 2623
swis2-VHDL20_DWPH_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 2771
swis2-VHDL20_DWSG_010200-2506010200-dsw--0-ia5 01-Jun-2025 02:45:11 3105
swis2-VHDL20_DWSG_010400-2506010400-dsw--0-ia5 01-Jun-2025 05:44:06 3799
swis2-VHDL20_DWSG_300800-2505300800-dsw--0-ia5 30-May-2025 08:49:11 3128
swis2-VHDL20_DWSG_301300-2505301300-dsw--0-ia5 30-May-2025 13:45:01 3159
swis2-VHDL20_DWSG_301800-2505301800-dsw--0-ia5 30-May-2025 18:45:06 3110
swis2-VHDL20_DWSG_310200-2505310200-dsw--0-ia5 31-May-2025 02:45:07 3473
swis2-VHDL20_DWSG_310400-2505310400-dsw--0-ia5 31-May-2025 05:15:02 3896
swis2-VHDL20_DWSG_310800-2505310800-dsw--0-ia5 31-May-2025 08:45:01 3900
swis2-VHDL20_DWSG_311300-2505311300-dsw--0-ia5 31-May-2025 13:45:02 3869
swis2-VHDL20_DWSG_311800-2505311800-dsw--0-ia5 31-May-2025 18:45:01 3150
wst04-VHDL20_DWEG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 269073
wst04-VHDL20_DWEG_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:15:07 269639
wst04-VHDL20_DWEG_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:06 267509
wst04-VHDL20_DWEG_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:06 264734
wst04-VHDL20_DWEG_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:07 264549
wst04-VHDL20_DWEG_310400-2505310400-omedes--0.pdf 31-May-2025 05:15:08 264891
wst04-VHDL20_DWEG_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:12 264904
wst04-VHDL20_DWEG_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:12 268885
wst04-VHDL20_DWEH_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 265777
wst04-VHDL20_DWEH_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:15:11 265716
wst04-VHDL20_DWEH_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:06 264046
wst04-VHDL20_DWEH_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:06 262082
wst04-VHDL20_DWEH_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:07 263117
wst04-VHDL20_DWEH_310400-2505310400-omedes--0.pdf 31-May-2025 05:15:08 262821
wst04-VHDL20_DWEH_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:12 262848
wst04-VHDL20_DWEH_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:06 265058
wst04-VHDL20_DWEI_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 373759
wst04-VHDL20_DWEI_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:15:11 373305
wst04-VHDL20_DWEI_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:12 370660
wst04-VHDL20_DWEI_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:11 369435
wst04-VHDL20_DWEI_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:13 370256
wst04-VHDL20_DWEI_310400-2505310400-omedes--0.pdf 31-May-2025 05:15:12 369621
wst04-VHDL20_DWEI_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:12 369607
wst04-VHDL20_DWEI_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:12 372784
wst04-VHDL20_DWHG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:20 374476
wst04-VHDL20_DWHG_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:07 374474
wst04-VHDL20_DWHG_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:23 364663
wst04-VHDL20_DWHG_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:21 359988
wst04-VHDL20_DWHG_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:22 359755
wst04-VHDL20_DWHG_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:11 359738
wst04-VHDL20_DWHG_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:21 361893
wst04-VHDL20_DWHG_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:22 374500
wst04-VHDL20_DWHH_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:20 367253
wst04-VHDL20_DWHH_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:11 367241
wst04-VHDL20_DWHH_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:16 354799
wst04-VHDL20_DWHH_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:21 349388
wst04-VHDL20_DWHH_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:22 349595
wst04-VHDL20_DWHH_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:07 349540
wst04-VHDL20_DWHH_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:21 351285
wst04-VHDL20_DWHH_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:22 367213
wst04-VHDL20_DWLG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:40:27 365652
wst04-VHDL20_DWLG_010400-2506010400-omedes--0.pdf 01-Jun-2025 04:59:36 365556
wst04-VHDL20_DWLG_300800-2505300800-omedes--0.pdf 30-May-2025 08:40:27 361866
wst04-VHDL20_DWLG_301800-2505301800-omedes--0.pdf 30-May-2025 18:40:26 355217
wst04-VHDL20_DWLG_310200-2505310200-omedes--0.pdf 31-May-2025 02:40:27 355689
wst04-VHDL20_DWLG_310400-2505310400-omedes--0.pdf 31-May-2025 04:59:36 355734
wst04-VHDL20_DWLG_310800-2505310800-omedes--0.pdf 31-May-2025 08:40:26 355771
wst04-VHDL20_DWLG_311800-2505311800-omedes--0.pdf 31-May-2025 18:40:27 365269
wst04-VHDL20_DWLH_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:40:17 365253
wst04-VHDL20_DWLH_010400-2506010400-omedes--0.pdf 01-Jun-2025 04:59:36 365578
wst04-VHDL20_DWLH_300800-2505300800-omedes--0.pdf 30-May-2025 08:40:16 353676
wst04-VHDL20_DWLH_301800-2505301800-omedes--0.pdf 30-May-2025 18:40:15 355585
wst04-VHDL20_DWLH_310200-2505310200-omedes--0.pdf 31-May-2025 02:40:16 355995
wst04-VHDL20_DWLH_310400-2505310400-omedes--0.pdf 31-May-2025 04:59:36 356512
wst04-VHDL20_DWLH_310800-2505310800-omedes--0.pdf 31-May-2025 08:40:16 356569
wst04-VHDL20_DWLH_311800-2505311800-omedes--0.pdf 31-May-2025 18:40:17 365369
wst04-VHDL20_DWLI_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:40:37 372921
wst04-VHDL20_DWLI_010400-2506010400-omedes--0.pdf 01-Jun-2025 04:59:36 372747
wst04-VHDL20_DWLI_300800-2505300800-omedes--0.pdf 30-May-2025 08:40:37 355686
wst04-VHDL20_DWLI_301800-2505301800-omedes--0.pdf 30-May-2025 18:40:36 359088
wst04-VHDL20_DWLI_310200-2505310200-omedes--0.pdf 31-May-2025 02:40:38 359621
wst04-VHDL20_DWLI_310400-2505310400-omedes--0.pdf 31-May-2025 04:59:36 359655
wst04-VHDL20_DWLI_310800-2505310800-omedes--0.pdf 31-May-2025 08:40:37 359711
wst04-VHDL20_DWLI_311800-2505311800-omedes--0.pdf 31-May-2025 18:40:35 372501
wst04-VHDL20_DWMG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:16 585535
wst04-VHDL20_DWMG_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:11 585196
wst04-VHDL20_DWMG_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:23 586897
wst04-VHDL20_DWMG_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:17 571620
wst04-VHDL20_DWMG_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:18 572422
wst04-VHDL20_DWMG_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:11 571863
wst04-VHDL20_DWMG_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:16 572625
wst04-VHDL20_DWMG_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:16 585739
wst04-VHDL20_DWMO_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 468358
wst04-VHDL20_DWMO_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:11 469497
wst04-VHDL20_DWMO_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:16 466605
wst04-VHDL20_DWMO_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:11 466874
wst04-VHDL20_DWMO_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:13 467949
wst04-VHDL20_DWMO_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:11 468526
wst04-VHDL20_DWMO_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:16 467651
wst04-VHDL20_DWMO_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:12 468955
wst04-VHDL20_DWMP_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:16 594033
wst04-VHDL20_DWMP_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:17 594385
wst04-VHDL20_DWMP_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:23 596156
wst04-VHDL20_DWMP_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:17 571792
wst04-VHDL20_DWMP_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:18 571716
wst04-VHDL20_DWMP_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:11 572084
wst04-VHDL20_DWMP_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:21 572317
wst04-VHDL20_DWMP_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:16 594263
wst04-VHDL20_DWPG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 372544
wst04-VHDL20_DWPG_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:07 372430
wst04-VHDL20_DWPG_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:16 407726
wst04-VHDL20_DWPG_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:11 365858
wst04-VHDL20_DWPG_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:18 366056
wst04-VHDL20_DWPG_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:07 366381
wst04-VHDL20_DWPG_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:06 410962
wst04-VHDL20_DWPG_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:12 372296
wst04-VHDL20_DWPH_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:11 267862
wst04-VHDL20_DWPH_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:00:07 267818
wst04-VHDL20_DWPH_300800-2505300800-omedes--0.pdf 30-May-2025 08:45:12 309579
wst04-VHDL20_DWPH_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:11 304127
wst04-VHDL20_DWPH_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:13 259896
wst04-VHDL20_DWPH_310400-2505310400-omedes--0.pdf 31-May-2025 05:00:07 260201
wst04-VHDL20_DWPH_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:06 304752
wst04-VHDL20_DWPH_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:06 311733
wst04-VHDL20_DWSG_010200-2506010200-omedes--0.pdf 01-Jun-2025 02:45:16 375952
wst04-VHDL20_DWSG_010400-2506010400-omedes--0.pdf 01-Jun-2025 05:44:12 377047
wst04-VHDL20_DWSG_300800-2505300800-omedes--0.pdf 30-May-2025 08:49:11 376713
wst04-VHDL20_DWSG_301300-2505301300-omedes--0.pdf 30-May-2025 13:45:06 373758
wst04-VHDL20_DWSG_301800-2505301800-omedes--0.pdf 30-May-2025 18:45:17 373677
wst04-VHDL20_DWSG_310200-2505310200-omedes--0.pdf 31-May-2025 02:45:13 373589
wst04-VHDL20_DWSG_310400-2505310400-omedes--0.pdf 31-May-2025 05:15:08 373946
wst04-VHDL20_DWSG_310800-2505310800-omedes--0.pdf 31-May-2025 08:45:16 373962
wst04-VHDL20_DWSG_311300-2505311300-omedes--0.pdf 31-May-2025 13:45:06 377292
wst04-VHDL20_DWSG_311800-2505311800-omedes--0.pdf 31-May-2025 18:45:16 376245