Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Jun-2026 13:48:28 4894
FPDL13_DWMZ_180600 18-Jun-2026 12:40:56 6490
SXDL31_DWAV_170800 17-Jun-2026 06:54:59 14478
SXDL31_DWAV_171800 17-Jun-2026 16:33:25 5710
SXDL31_DWAV_180800 18-Jun-2026 10:24:35 14091
SXDL31_DWAV_181800 18-Jun-2026 16:43:20 15220
SXDL31_DWAV_LATEST 18-Jun-2026 16:43:20 15220
SXDL33_DWAV_170000 17-Jun-2026 10:13:28 10835
SXDL33_DWAV_180000 18-Jun-2026 10:51:52 20679
SXDL33_DWAV_LATEST 18-Jun-2026 10:51:52 20679
ber01-FWDL39_DWMS_171200-2606171200-dsw--0-ia5 17-Jun-2026 11:58:55 1460
ber01-FWDL39_DWMS_181200-2606181200-dsw--0-ia5 18-Jun-2026 09:48:23 1625
ber01-VHDL13_DWEG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:28:17 3178
ber01-VHDL13_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3493
ber01-VHDL13_DWEH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:28:17 3400
ber01-VHDL13_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 4161
ber01-VHDL13_DWEI_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:28:17 2962
ber01-VHDL13_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3393
ber01-VHDL13_DWHG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 3463
ber01-VHDL13_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3038
ber01-VHDL13_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 10:54:52 3231
ber01-VHDL13_DWHH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 2802
ber01-VHDL13_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3044
ber01-VHDL13_DWLG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 2288
ber01-VHDL13_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2514
ber01-VHDL13_DWLH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 2106
ber01-VHDL13_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2480
ber01-VHDL13_DWLI_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 2157
ber01-VHDL13_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2411
ber01-VHDL13_DWMO_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 2775
ber01-VHDL13_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3033
ber01-VHDL13_DWMP_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 2846
ber01-VHDL13_DWMP_170800_COR-2606170800-dsw--0-ia5 17-Jun-2026 08:41:04 3007
ber01-VHDL13_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3367
ber01-VHDL13_DWOG_170300-2606170300-dsw--0-ia5 17-Jun-2026 03:00:06 3259
ber01-VHDL13_DWOG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 3393
ber01-VHDL13_DWOG_171700-2606171700-dsw--0-ia5 17-Jun-2026 18:00:01 2767
ber01-VHDL13_DWOG_180300-2606180300-dsw--0-ia5 18-Jun-2026 03:01:30 3374
ber01-VHDL13_DWOG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3756
ber01-VHDL13_DWOG_181700-2606181700-dsw--0-ia5 18-Jun-2026 18:00:01 4526
ber01-VHDL13_DWON_170126-2606170126-dsw--0-ia5 17-Jun-2026 01:26:36 3068
ber01-VHDL13_DWON_170230-2606170230-dsw--0-ia5 17-Jun-2026 02:30:15 3068
ber01-VHDL13_DWON_170530-2606170530-dsw--0-ia5 17-Jun-2026 05:30:08 3353
ber01-VHDL13_DWON_170613-2606170613-dsw--0-ia5 17-Jun-2026 06:13:11 3394
ber01-VHDL13_DWON_170649-2606170649-dsw--0-ia5 17-Jun-2026 06:49:07 3394
ber01-VHDL13_DWON_170823-2606170823-dsw--0-ia5 17-Jun-2026 08:23:46 3394
ber01-VHDL13_DWON_171417-2606171417-dsw--0-ia5 17-Jun-2026 14:17:57 3495
ber01-VHDL13_DWON_171713-2606171713-dsw--0-ia5 17-Jun-2026 17:13:56 2814
ber01-VHDL13_DWON_171725-2606171725-dsw--0-ia5 17-Jun-2026 17:25:51 2814
ber01-VHDL13_DWON_172109-2606172109-dsw--0-ia5 17-Jun-2026 21:09:41 2845
ber01-VHDL13_DWON_172215-2606172215-dsw--0-ia5 17-Jun-2026 22:15:11 3118
ber01-VHDL13_DWON_180127-2606180127-dsw--0-ia5 18-Jun-2026 01:27:42 3118
ber01-VHDL13_DWON_180511-2606180511-dsw--0-ia5 18-Jun-2026 05:11:56 3126
ber01-VHDL13_DWON_180529-2606180529-dsw--0-ia5 18-Jun-2026 05:29:13 3274
ber01-VHDL13_DWON_180537-2606180537-dsw--0-ia5 18-Jun-2026 05:37:22 3939
ber01-VHDL13_DWON_180644-2606180644-dsw--0-ia5 18-Jun-2026 06:44:27 3982
ber01-VHDL13_DWON_181231-2606181231-dsw--0-ia5 18-Jun-2026 12:31:06 3958
ber01-VHDL13_DWON_181448-2606181448-dsw--0-ia5 18-Jun-2026 14:48:56 3661
ber01-VHDL13_DWON_181653-2606181653-dsw--0-ia5 18-Jun-2026 16:53:21 3579
ber01-VHDL13_DWON_181737-2606181737-dsw--0-ia5 18-Jun-2026 17:37:31 3579
ber01-VHDL13_DWON_182159-2606182159-dsw--0-ia5 18-Jun-2026 22:00:01 3512
ber01-VHDL13_DWON_190034-2606190034-dsw--0-ia5 19-Jun-2026 00:34:48 3759
ber01-VHDL13_DWPG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 2207
ber01-VHDL13_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2391
ber01-VHDL13_DWPH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 2146
ber01-VHDL13_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2532
ber01-VHDL13_DWSG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 3022
ber01-VHDL13_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3547
ber01-VHDL13_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 3906
ber01-VHDL17_DWOG_171200-2606171200-dsw--0-ia5 17-Jun-2026 11:35:59 2895
ber01-VHDL17_DWOG_181200-2606181200-dsw--0-ia5 18-Jun-2026 11:51:17 3712
swis2-VHDL20_DWEG_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:06 1126
swis2-VHDL20_DWEG_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:01:22 1133
swis2-VHDL20_DWEG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 1501
swis2-VHDL20_DWEG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1927
swis2-VHDL20_DWEG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1621
swis2-VHDL20_DWEG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1614
swis2-VHDL20_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2061
swis2-VHDL20_DWEG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 1927
swis2-VHDL20_DWEH_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:06 1207
swis2-VHDL20_DWEH_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:01:22 1220
swis2-VHDL20_DWEH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 1743
swis2-VHDL20_DWEH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 2224
swis2-VHDL20_DWEH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1905
swis2-VHDL20_DWEH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1905
swis2-VHDL20_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2581
swis2-VHDL20_DWEH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2513
swis2-VHDL20_DWEI_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:06 1018
swis2-VHDL20_DWEI_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:01:22 1036
swis2-VHDL20_DWEI_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 1489
swis2-VHDL20_DWEI_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1932
swis2-VHDL20_DWEI_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1626
swis2-VHDL20_DWEI_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1622
swis2-VHDL20_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2017
swis2-VHDL20_DWEI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2257
swis2-VHDL20_DWHG_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:45:01 1132
swis2-VHDL20_DWHG_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:17 1129
swis2-VHDL20_DWHG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:45:18 1607
swis2-VHDL20_DWHG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:45:06 1493
swis2-VHDL20_DWHG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:45:42 1247
swis2-VHDL20_DWHG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1255
swis2-VHDL20_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1686
swis2-VHDL20_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 11:05:21 1691
swis2-VHDL20_DWHG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1656
swis2-VHDL20_DWHH_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:45:01 956
swis2-VHDL20_DWHH_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:17 956
swis2-VHDL20_DWHH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:45:18 1198
swis2-VHDL20_DWHH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:45:06 1313
swis2-VHDL20_DWHH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:45:42 1092
swis2-VHDL20_DWHH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1252
swis2-VHDL20_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1398
swis2-VHDL20_DWHH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1606
swis2-VHDL20_DWLG_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:22 726
swis2-VHDL20_DWLG_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:11 726
swis2-VHDL20_DWLG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:25 936
swis2-VHDL20_DWLG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1397
swis2-VHDL20_DWLG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1062
swis2-VHDL20_DWLG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1138
swis2-VHDL20_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1627
swis2-VHDL20_DWLG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1315
swis2-VHDL20_DWLH_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:22 733
swis2-VHDL20_DWLH_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:11 733
swis2-VHDL20_DWLH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:25 943
swis2-VHDL20_DWLH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1475
swis2-VHDL20_DWLH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1139
swis2-VHDL20_DWLH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1215
swis2-VHDL20_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1716
swis2-VHDL20_DWLH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1441
swis2-VHDL20_DWLI_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:22 728
swis2-VHDL20_DWLI_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:11 728
swis2-VHDL20_DWLI_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:25 938
swis2-VHDL20_DWLI_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1402
swis2-VHDL20_DWLI_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1069
swis2-VHDL20_DWLI_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1145
swis2-VHDL20_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1633
swis2-VHDL20_DWLI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1405
swis2-VHDL20_DWMO_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:02 885
swis2-VHDL20_DWMO_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:07 982
swis2-VHDL20_DWMO_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 1170
swis2-VHDL20_DWMO_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1324
swis2-VHDL20_DWMO_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:09 1098
swis2-VHDL20_DWMO_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:02 1235
swis2-VHDL20_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 1416
swis2-VHDL20_DWMO_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1367
swis2-VHDL20_DWMP_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:02 901
swis2-VHDL20_DWMP_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:07 997
swis2-VHDL20_DWMP_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:16 1204
swis2-VHDL20_DWMP_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1408
swis2-VHDL20_DWMP_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:09 1056
swis2-VHDL20_DWMP_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:02 1368
swis2-VHDL20_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1662
swis2-VHDL20_DWMP_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1603
swis2-VHDL20_DWPG_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:22 748
swis2-VHDL20_DWPG_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:11 756
swis2-VHDL20_DWPG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:25 959
swis2-VHDL20_DWPG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1536
swis2-VHDL20_DWPG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1187
swis2-VHDL20_DWPG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1169
swis2-VHDL20_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1590
swis2-VHDL20_DWPG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1508
swis2-VHDL20_DWPH_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:22 747
swis2-VHDL20_DWPH_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:11 754
swis2-VHDL20_DWPH_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:25 958
swis2-VHDL20_DWPH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1494
swis2-VHDL20_DWPH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1180
swis2-VHDL20_DWPH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1184
swis2-VHDL20_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1571
swis2-VHDL20_DWPH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1288
swis2-VHDL20_DWSG_170200-2606170200-dsw--0-ia5 17-Jun-2026 02:30:02 790
swis2-VHDL20_DWSG_170400-2606170400-dsw--0-ia5 17-Jun-2026 05:00:17 964
swis2-VHDL20_DWSG_170800-2606170800-dsw--0-ia5 17-Jun-2026 08:30:01 1160
swis2-VHDL20_DWSG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1116
swis2-VHDL20_DWSG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1156
swis2-VHDL20_DWSG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1344
swis2-VHDL20_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1561
swis2-VHDL20_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 1831
swis2-VHDL20_DWSG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1740
wst04-VHDL20_DWEG_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:15 244512
wst04-VHDL20_DWEG_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:11 244324
wst04-VHDL20_DWEG_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:16 246033
wst04-VHDL20_DWEG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 246900
wst04-VHDL20_DWEG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 246459
wst04-VHDL20_DWEG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 246034
wst04-VHDL20_DWEG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246925
wst04-VHDL20_DWEG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249247
wst04-VHDL20_DWEH_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:15 242320
wst04-VHDL20_DWEH_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:11 242459
wst04-VHDL20_DWEH_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:16 243824
wst04-VHDL20_DWEH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 244774
wst04-VHDL20_DWEH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 244967
wst04-VHDL20_DWEH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 244472
wst04-VHDL20_DWEH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246072
wst04-VHDL20_DWEH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249672
wst04-VHDL20_DWEI_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:15 349655
wst04-VHDL20_DWEI_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:11 349433
wst04-VHDL20_DWEI_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:16 351532
wst04-VHDL20_DWEI_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 354331
wst04-VHDL20_DWEI_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 354462
wst04-VHDL20_DWEI_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 353953
wst04-VHDL20_DWEI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 354320
wst04-VHDL20_DWEI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 360512
wst04-VHDL20_DWHG_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:45:12 343643
wst04-VHDL20_DWHG_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:17 343458
wst04-VHDL20_DWHG_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:45:18 345014
wst04-VHDL20_DWHG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:45:17 349681
wst04-VHDL20_DWHG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:45:42 348764
wst04-VHDL20_DWHG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 348538
wst04-VHDL20_DWHG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 351740
wst04-VHDL20_DWHG_180800_COR-2606180800-omedes-..> 18-Jun-2026 11:07:07 363371
wst04-VHDL20_DWHG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 361512
wst04-VHDL20_DWHH_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:45:12 326741
wst04-VHDL20_DWHH_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:17 226644
wst04-VHDL20_DWHH_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:45:18 327814
wst04-VHDL20_DWHH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:45:17 330835
wst04-VHDL20_DWHH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:45:42 330217
wst04-VHDL20_DWHH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 222334
wst04-VHDL20_DWHH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 331404
wst04-VHDL20_DWHH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 339012
wst04-VHDL20_DWLG_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 339103
wst04-VHDL20_DWLG_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:41 338947
wst04-VHDL20_DWLG_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:44 339589
wst04-VHDL20_DWLG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 341579
wst04-VHDL20_DWLG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 341653
wst04-VHDL20_DWLG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 341306
wst04-VHDL20_DWLG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 342645
wst04-VHDL20_DWLG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348845
wst04-VHDL20_DWLH_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 338565
wst04-VHDL20_DWLH_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:41 338402
wst04-VHDL20_DWLH_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:44 339057
wst04-VHDL20_DWLH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 340162
wst04-VHDL20_DWLH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 340257
wst04-VHDL20_DWLH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 339903
wst04-VHDL20_DWLH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 341229
wst04-VHDL20_DWLH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348533
wst04-VHDL20_DWLI_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 346695
wst04-VHDL20_DWLI_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:41 346518
wst04-VHDL20_DWLI_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:47 391742
wst04-VHDL20_DWLI_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 345243
wst04-VHDL20_DWLI_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:27 345370
wst04-VHDL20_DWLI_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 344983
wst04-VHDL20_DWLI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 390905
wst04-VHDL20_DWLI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:28 354450
wst04-VHDL20_DWMO_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 462647
wst04-VHDL20_DWMO_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:17 463833
wst04-VHDL20_DWMO_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:16 464259
wst04-VHDL20_DWMO_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:17 356000
wst04-VHDL20_DWMO_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:20 467596
wst04-VHDL20_DWMO_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 467607
wst04-VHDL20_DWMO_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:17 467840
wst04-VHDL20_DWMO_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 366447
wst04-VHDL20_DWMP_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 585519
wst04-VHDL20_DWMP_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:17 586597
wst04-VHDL20_DWMP_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:23 475434
wst04-VHDL20_DWMP_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:17 467440
wst04-VHDL20_DWMP_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:20 578377
wst04-VHDL20_DWMP_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 579190
wst04-VHDL20_DWMP_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:21 467930
wst04-VHDL20_DWMP_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 490164
wst04-VHDL20_DWPG_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 242405
wst04-VHDL20_DWPG_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:31 348431
wst04-VHDL20_DWPG_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:44 393597
wst04-VHDL20_DWPG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:29 345097
wst04-VHDL20_DWPG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 244194
wst04-VHDL20_DWPG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:32 344404
wst04-VHDL20_DWPG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:47 390307
wst04-VHDL20_DWPG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 356284
wst04-VHDL20_DWPH_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:22 234698
wst04-VHDL20_DWPH_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:31 234573
wst04-VHDL20_DWPH_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:44 235159
wst04-VHDL20_DWPH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 239793
wst04-VHDL20_DWPH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 239884
wst04-VHDL20_DWPH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:32 239131
wst04-VHDL20_DWPH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 239610
wst04-VHDL20_DWPH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 247781
wst04-VHDL20_DWSG_170200-2606170200-omedes--0.pdf 17-Jun-2026 02:30:10 347528
wst04-VHDL20_DWSG_170400-2606170400-omedes--0.pdf 17-Jun-2026 05:00:11 348654
wst04-VHDL20_DWSG_170800-2606170800-omedes--0.pdf 17-Jun-2026 08:30:16 349077
wst04-VHDL20_DWSG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 351338
wst04-VHDL20_DWSG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 351346
wst04-VHDL20_DWSG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 351778
wst04-VHDL20_DWSG_180800-2606180800-omedes--0.pdf 18-Jun-2026 14:46:21 365010
wst04-VHDL20_DWSG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 364914