Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Jun-2026 14:58:09 6678
FPDL13_DWMZ_140600 14-Jun-2026 11:49:54 4499
SXDL31_DWAV_130800 13-Jun-2026 08:37:03 12249
SXDL31_DWAV_131800 13-Jun-2026 16:38:16 5254
SXDL31_DWAV_140800 14-Jun-2026 07:08:34 5892
SXDL31_DWAV_141800 14-Jun-2026 16:37:37 7280
SXDL31_DWAV_LATEST 14-Jun-2026 16:37:37 7280
SXDL33_DWAV_130000 13-Jun-2026 10:32:11 21384
SXDL33_DWAV_140000 14-Jun-2026 10:44:30 8894
SXDL33_DWAV_LATEST 14-Jun-2026 10:44:30 8894
ber01-FWDL39_DWMS_131200-2606131200-dsw--0-ia5 13-Jun-2026 11:56:47 1265
ber01-FWDL39_DWMS_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:35:09 1268
ber01-VHDL13_DWEG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:17 2732
ber01-VHDL13_DWEG_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:16 2411
ber01-VHDL13_DWEH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:17 2646
ber01-VHDL13_DWEH_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:36 2297
ber01-VHDL13_DWEI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:11 2593
ber01-VHDL13_DWEI_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:52 2333
ber01-VHDL13_DWHG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 3732
ber01-VHDL13_DWHG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 3040
ber01-VHDL13_DWHH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 3662
ber01-VHDL13_DWHH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 3236
ber01-VHDL13_DWLG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2804
ber01-VHDL13_DWLG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 3020
ber01-VHDL13_DWLH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2659
ber01-VHDL13_DWLH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2874
ber01-VHDL13_DWLI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2237
ber01-VHDL13_DWLI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2337
ber01-VHDL13_DWMO_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 2893
ber01-VHDL13_DWMO_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2835
ber01-VHDL13_DWMP_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 3238
ber01-VHDL13_DWMP_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2892
ber01-VHDL13_DWOG_130300-2606130300-dsw--0-ia5 13-Jun-2026 03:00:02 4716
ber01-VHDL13_DWOG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 4839
ber01-VHDL13_DWOG_131700-2606131700-dsw--0-ia5 13-Jun-2026 18:00:02 4061
ber01-VHDL13_DWOG_140300-2606140300-dsw--0-ia5 14-Jun-2026 03:00:06 4526
ber01-VHDL13_DWOG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 4351
ber01-VHDL13_DWOG_141700-2606141700-dsw--0-ia5 14-Jun-2026 18:00:02 3580
ber01-VHDL13_DWON_130001-2606130001-dsw--0-ia5 13-Jun-2026 00:01:31 3865
ber01-VHDL13_DWON_130158-2606130158-dsw--0-ia5 13-Jun-2026 01:58:27 3881
ber01-VHDL13_DWON_130232-2606130232-dsw--0-ia5 13-Jun-2026 02:32:59 3881
ber01-VHDL13_DWON_130529-2606130529-dsw--0-ia5 13-Jun-2026 05:29:20 4421
ber01-VHDL13_DWON_130543-2606130543-dsw--0-ia5 13-Jun-2026 05:43:42 4298
ber01-VHDL13_DWON_130648-2606130648-dsw--0-ia5 13-Jun-2026 06:48:36 4465
ber01-VHDL13_DWON_130807-2606130807-dsw--0-ia5 13-Jun-2026 08:08:01 4418
ber01-VHDL13_DWON_130839-2606130839-dsw--0-ia5 13-Jun-2026 08:39:59 4418
ber01-VHDL13_DWON_130941-2606130941-dsw--0-ia5 13-Jun-2026 09:41:24 4418
ber01-VHDL13_DWON_131441-2606131441-dsw--0-ia5 13-Jun-2026 14:41:57 4321
ber01-VHDL13_DWON_131733-2606131733-dsw--0-ia5 13-Jun-2026 17:33:41 3449
ber01-VHDL13_DWON_131738-2606131738-dsw--0-ia5 13-Jun-2026 17:38:32 3439
ber01-VHDL13_DWON_131826-2606131826-dsw--0-ia5 13-Jun-2026 18:26:37 3516
ber01-VHDL13_DWON_132128-2606132128-dsw--0-ia5 13-Jun-2026 21:28:36 3500
ber01-VHDL13_DWON_140133-2606140133-dsw--0-ia5 14-Jun-2026 01:33:46 3980
ber01-VHDL13_DWON_140231-2606140231-dsw--0-ia5 14-Jun-2026 02:31:42 3980
ber01-VHDL13_DWON_140523-2606140523-dsw--0-ia5 14-Jun-2026 05:23:36 3744
ber01-VHDL13_DWON_141325-2606141325-dsw--0-ia5 14-Jun-2026 13:26:03 4154
ber01-VHDL13_DWON_141728-2606141728-dsw--0-ia5 14-Jun-2026 17:28:27 3385
ber01-VHDL13_DWON_141741-2606141741-dsw--0-ia5 14-Jun-2026 17:41:47 3385
ber01-VHDL13_DWPG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2322
ber01-VHDL13_DWPG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2708
ber01-VHDL13_DWPH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2757
ber01-VHDL13_DWPH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 3160
ber01-VHDL13_DWSG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2866
ber01-VHDL13_DWSG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 2665
ber01-VHDL17_DWOG_131200-2606131200-dsw--0-ia5 13-Jun-2026 11:41:26 3785
ber01-VHDL17_DWOG_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:36:53 3479
swis2-VHDL20_DWEG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1014
swis2-VHDL20_DWEG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1074
swis2-VHDL20_DWEG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1209
swis2-VHDL20_DWEG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 983
swis2-VHDL20_DWEG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 840
swis2-VHDL20_DWEG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 819
swis2-VHDL20_DWEG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 935
swis2-VHDL20_DWEG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1113
swis2-VHDL20_DWEH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1008
swis2-VHDL20_DWEH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1071
swis2-VHDL20_DWEH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1208
swis2-VHDL20_DWEH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1000
swis2-VHDL20_DWEH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 844
swis2-VHDL20_DWEH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 823
swis2-VHDL20_DWEH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 933
swis2-VHDL20_DWEH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1185
swis2-VHDL20_DWEI_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1019
swis2-VHDL20_DWEI_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1082
swis2-VHDL20_DWEI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1209
swis2-VHDL20_DWEI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 970
swis2-VHDL20_DWEI_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 826
swis2-VHDL20_DWEI_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 826
swis2-VHDL20_DWEI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 942
swis2-VHDL20_DWEI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1181
swis2-VHDL20_DWHG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:45:18 1834
swis2-VHDL20_DWHG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1997
swis2-VHDL20_DWHG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:45:04 2019
swis2-VHDL20_DWHG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 1795
swis2-VHDL20_DWHG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:45:06 1630
swis2-VHDL20_DWHG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1627
swis2-VHDL20_DWHG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:45:05 1446
swis2-VHDL20_DWHG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1538
swis2-VHDL20_DWHH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:45:18 1874
swis2-VHDL20_DWHH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1959
swis2-VHDL20_DWHH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:45:04 2090
swis2-VHDL20_DWHH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 2029
swis2-VHDL20_DWHH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:45:06 1568
swis2-VHDL20_DWHH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1641
swis2-VHDL20_DWHH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:45:05 1669
swis2-VHDL20_DWHH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1721
swis2-VHDL20_DWLG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1278
swis2-VHDL20_DWLG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1293
swis2-VHDL20_DWLG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1404
swis2-VHDL20_DWLG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1111
swis2-VHDL20_DWLG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1106
swis2-VHDL20_DWLG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1371
swis2-VHDL20_DWLG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1649
swis2-VHDL20_DWLG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1234
swis2-VHDL20_DWLH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1361
swis2-VHDL20_DWLH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1174
swis2-VHDL20_DWLH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1326
swis2-VHDL20_DWLH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1392
swis2-VHDL20_DWLH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1308
swis2-VHDL20_DWLH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1296
swis2-VHDL20_DWLH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1574
swis2-VHDL20_DWLH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1261
swis2-VHDL20_DWLI_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 998
swis2-VHDL20_DWLI_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1008
swis2-VHDL20_DWLI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1122
swis2-VHDL20_DWLI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 937
swis2-VHDL20_DWLI_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 965
swis2-VHDL20_DWLI_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 959
swis2-VHDL20_DWLI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1237
swis2-VHDL20_DWLI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1015
swis2-VHDL20_DWMO_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1280
swis2-VHDL20_DWMO_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:02 1285
swis2-VHDL20_DWMO_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 1272
swis2-VHDL20_DWMO_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1301
swis2-VHDL20_DWMO_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 1228
swis2-VHDL20_DWMO_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:06 1244
swis2-VHDL20_DWMO_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 1251
swis2-VHDL20_DWMO_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1113
swis2-VHDL20_DWMP_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1503
swis2-VHDL20_DWMP_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:02 1508
swis2-VHDL20_DWMP_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 1529
swis2-VHDL20_DWMP_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1551
swis2-VHDL20_DWMP_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 1461
swis2-VHDL20_DWMP_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:06 1476
swis2-VHDL20_DWMP_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 1351
swis2-VHDL20_DWMP_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1244
swis2-VHDL20_DWPG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1162
swis2-VHDL20_DWPG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1097
swis2-VHDL20_DWPG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1218
swis2-VHDL20_DWPG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1291
swis2-VHDL20_DWPG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1161
swis2-VHDL20_DWPG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1240
swis2-VHDL20_DWPG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1353
swis2-VHDL20_DWPG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1177
swis2-VHDL20_DWPH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1283
swis2-VHDL20_DWPH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1270
swis2-VHDL20_DWPH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1426
swis2-VHDL20_DWPH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1492
swis2-VHDL20_DWPH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1380
swis2-VHDL20_DWPH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1492
swis2-VHDL20_DWPH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1578
swis2-VHDL20_DWPH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1690
swis2-VHDL20_DWSG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1248
swis2-VHDL20_DWSG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1247
swis2-VHDL20_DWSG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1245
swis2-VHDL20_DWSG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1381
swis2-VHDL20_DWSG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:02 1155
swis2-VHDL20_DWSG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1154
swis2-VHDL20_DWSG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 1200
swis2-VHDL20_DWSG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1102
wst04-VHDL20_DWEG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 236127
wst04-VHDL20_DWEG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 235998
wst04-VHDL20_DWEG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 237338
wst04-VHDL20_DWEG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 238572
wst04-VHDL20_DWEG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 237721
wst04-VHDL20_DWEG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 237257
wst04-VHDL20_DWEG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 238010
wst04-VHDL20_DWEG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 241683
wst04-VHDL20_DWEH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 235883
wst04-VHDL20_DWEH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 235706
wst04-VHDL20_DWEH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 237081
wst04-VHDL20_DWEH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 236082
wst04-VHDL20_DWEH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 235563
wst04-VHDL20_DWEH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 235371
wst04-VHDL20_DWEH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 236119
wst04-VHDL20_DWEH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 239515
wst04-VHDL20_DWEI_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 336219
wst04-VHDL20_DWEI_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 336028
wst04-VHDL20_DWEI_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 336335
wst04-VHDL20_DWEI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 338034
wst04-VHDL20_DWEI_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 337767
wst04-VHDL20_DWEI_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 337773
wst04-VHDL20_DWEI_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:18 338040
wst04-VHDL20_DWEI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343740
wst04-VHDL20_DWHG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:45:18 337238
wst04-VHDL20_DWHG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 337054
wst04-VHDL20_DWHG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:45:12 338190
wst04-VHDL20_DWHG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 337810
wst04-VHDL20_DWHG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:45:12 337626
wst04-VHDL20_DWHG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 337621
wst04-VHDL20_DWHG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:45:16 336880
wst04-VHDL20_DWHG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 336568
wst04-VHDL20_DWHH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:45:18 325628
wst04-VHDL20_DWHH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 227717
wst04-VHDL20_DWHH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:45:12 325842
wst04-VHDL20_DWHH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 326363
wst04-VHDL20_DWHH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:45:12 325557
wst04-VHDL20_DWHH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 229095
wst04-VHDL20_DWHH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:45:16 325154
wst04-VHDL20_DWHH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 326497
wst04-VHDL20_DWLG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:25 335709
wst04-VHDL20_DWLG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 335881
wst04-VHDL20_DWLG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:45 336080
wst04-VHDL20_DWLG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 340325
wst04-VHDL20_DWLG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 340226
wst04-VHDL20_DWLG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 340578
wst04-VHDL20_DWLG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 341330
wst04-VHDL20_DWLG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337538
wst04-VHDL20_DWLH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 328724
wst04-VHDL20_DWLH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 328356
wst04-VHDL20_DWLH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:45 328620
wst04-VHDL20_DWLH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 331737
wst04-VHDL20_DWLH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 330448
wst04-VHDL20_DWLH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 330559
wst04-VHDL20_DWLH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 331355
wst04-VHDL20_DWLH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 333101
wst04-VHDL20_DWLI_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 334856
wst04-VHDL20_DWLI_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 334559
wst04-VHDL20_DWLI_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 379362
wst04-VHDL20_DWLI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 335223
wst04-VHDL20_DWLI_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 334906
wst04-VHDL20_DWLI_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 334940
wst04-VHDL20_DWLI_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 380650
wst04-VHDL20_DWLI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 341239
wst04-VHDL20_DWMO_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 447051
wst04-VHDL20_DWMO_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 447266
wst04-VHDL20_DWMO_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 446996
wst04-VHDL20_DWMO_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 347509
wst04-VHDL20_DWMO_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 451652
wst04-VHDL20_DWMO_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 451528
wst04-VHDL20_DWMO_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:18 451352
wst04-VHDL20_DWMO_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 353665
wst04-VHDL20_DWMP_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 567036
wst04-VHDL20_DWMP_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 567182
wst04-VHDL20_DWMP_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:23 459557
wst04-VHDL20_DWMP_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 464262
wst04-VHDL20_DWMP_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 570548
wst04-VHDL20_DWMP_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 570360
wst04-VHDL20_DWMP_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:28 463874
wst04-VHDL20_DWMP_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 459630
wst04-VHDL20_DWPG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 238598
wst04-VHDL20_DWPG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:32 336087
wst04-VHDL20_DWPG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 380925
wst04-VHDL20_DWPG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 341820
wst04-VHDL20_DWPG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 240610
wst04-VHDL20_DWPG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:32 341436
wst04-VHDL20_DWPG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 386206
wst04-VHDL20_DWPG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337780
wst04-VHDL20_DWPH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 239232
wst04-VHDL20_DWPH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:32 238946
wst04-VHDL20_DWPH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 239129
wst04-VHDL20_DWPH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 241359
wst04-VHDL20_DWPH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 240805
wst04-VHDL20_DWPH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:32 241091
wst04-VHDL20_DWPH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 241179
wst04-VHDL20_DWPH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 243201
wst04-VHDL20_DWSG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 345862
wst04-VHDL20_DWSG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 345592
wst04-VHDL20_DWSG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:17 345740
wst04-VHDL20_DWSG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 347303
wst04-VHDL20_DWSG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 346529
wst04-VHDL20_DWSG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 346545
wst04-VHDL20_DWSG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 347288
wst04-VHDL20_DWSG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343341