Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_240600                                 24-Jun-2026 09:39:15                2237
FPDL13_DWMZ_250600                                 25-Jun-2026 12:30:12                3432
SXDL31_DWAV_240800                                 24-Jun-2026 07:43:54               10568
SXDL31_DWAV_241800                                 24-Jun-2026 16:34:49                7014
SXDL31_DWAV_250800                                 25-Jun-2026 09:20:19                8619
SXDL31_DWAV_251800                                 25-Jun-2026 15:51:44                7555
SXDL31_DWAV_LATEST                                 25-Jun-2026 15:51:44                7555
SXDL33_DWAV_240000                                 24-Jun-2026 09:36:43               11093
SXDL33_DWAV_250000                                 25-Jun-2026 10:09:14                7899
SXDL33_DWAV_LATEST                                 25-Jun-2026 10:09:14                7899
ber01-FWDL39_DWMS_241200-2606241200-dsw--0-ia5     24-Jun-2026 12:29:11                1761
ber01-FWDL39_DWMS_241200_COR-2606241200-dsw--0-ia5 24-Jun-2026 12:20:42                1765
ber01-FWDL39_DWMS_251200-2606251200-dsw--0-ia5     25-Jun-2026 12:13:37                1982
ber01-VHDL13_DWEG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:28:17                2497
ber01-VHDL13_DWEG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:28:16                2515
ber01-VHDL13_DWEG_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:06:07                3268
ber01-VHDL13_DWEH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:28:17                2559
ber01-VHDL13_DWEH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:28:16                3099
ber01-VHDL13_DWEH_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:07:12                3335
ber01-VHDL13_DWEI_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:28:17                2617
ber01-VHDL13_DWEI_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:28:12                3194
ber01-VHDL13_DWEI_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:07:58                3110
ber01-VHDL13_DWHG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2135
ber01-VHDL13_DWHG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                2757
ber01-VHDL13_DWHH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2370
ber01-VHDL13_DWHH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                2413
ber01-VHDL13_DWLG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                1828
ber01-VHDL13_DWLG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                2425
ber01-VHDL13_DWLH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                1883
ber01-VHDL13_DWLH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                2501
ber01-VHDL13_DWLI_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                1966
ber01-VHDL13_DWLI_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                2510
ber01-VHDL13_DWMO_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2845
ber01-VHDL13_DWMO_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                2582
ber01-VHDL13_DWMP_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2820
ber01-VHDL13_DWMP_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 08:36:44                2923
ber01-VHDL13_DWMP_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                2596
ber01-VHDL13_DWOG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                3014
ber01-VHDL13_DWOG_241700-2606241700-dsw--0-ia5     24-Jun-2026 18:00:00                2956
ber01-VHDL13_DWOG_250300-2606250300-dsw--0-ia5     25-Jun-2026 03:00:06                3626
ber01-VHDL13_DWOG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                3406
ber01-VHDL13_DWOG_251700-2606251700-dsw--0-ia5     25-Jun-2026 18:00:01                2758
ber01-VHDL13_DWOG_260300-2606260300-dsw--0-ia5     26-Jun-2026 03:00:03                3396
ber01-VHDL13_DWON_240602-2606240602-dsw--0-ia5     24-Jun-2026 06:02:07                3191
ber01-VHDL13_DWON_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:00:57                3198
ber01-VHDL13_DWON_240941-2606240941-dsw--0-ia5     24-Jun-2026 09:41:25                3198
ber01-VHDL13_DWON_241442-2606241442-dsw--0-ia5     24-Jun-2026 14:42:59                3027
ber01-VHDL13_DWON_241656-2606241656-dsw--0-ia5     24-Jun-2026 16:56:17                2810
ber01-VHDL13_DWON_241852-2606241852-dsw--0-ia5     24-Jun-2026 18:52:32                2886
ber01-VHDL13_DWON_241900-2606241900-dsw--0-ia5     24-Jun-2026 19:00:52                2886
ber01-VHDL13_DWON_241901-2606241901-dsw--0-ia5     24-Jun-2026 19:01:21                2886
ber01-VHDL13_DWON_242144-2606242144-dsw--0-ia5     24-Jun-2026 21:45:03                2908
ber01-VHDL13_DWON_242359-2606242359-dsw--0-ia5     24-Jun-2026 23:59:27                3585
ber01-VHDL13_DWON_250126-2606250126-dsw--0-ia5     25-Jun-2026 01:26:52                3837
ber01-VHDL13_DWON_250132-2606250132-dsw--0-ia5     25-Jun-2026 01:32:42                3952
ber01-VHDL13_DWON_250237-2606250237-dsw--0-ia5     25-Jun-2026 02:37:18                3952
ber01-VHDL13_DWON_250513-2606250513-dsw--0-ia5     25-Jun-2026 05:13:50                4108
ber01-VHDL13_DWON_250557-2606250557-dsw--0-ia5     25-Jun-2026 05:58:02                3807
ber01-VHDL13_DWON_250625-2606250625-dsw--0-ia5     25-Jun-2026 06:26:03                3807
ber01-VHDL13_DWON_250817-2606250817-dsw--0-ia5     25-Jun-2026 08:18:01                3592
ber01-VHDL13_DWON_251503-2606251503-dsw--0-ia5     25-Jun-2026 15:03:06                3046
ber01-VHDL13_DWON_251751-2606251751-dsw--0-ia5     25-Jun-2026 17:51:17                3046
ber01-VHDL13_DWON_251825-2606251825-dsw--0-ia5     25-Jun-2026 18:25:38                3316
ber01-VHDL13_DWON_252208-2606252208-dsw--0-ia5     25-Jun-2026 22:08:17                3929
ber01-VHDL13_DWON_260002-2606260002-dsw--0-ia5     26-Jun-2026 00:02:56                3929
ber01-VHDL13_DWON_260127-2606260127-dsw--0-ia5     26-Jun-2026 01:27:22                3413
ber01-VHDL13_DWON_260242-2606260242-dsw--0-ia5     26-Jun-2026 02:42:46                3413
ber01-VHDL13_DWPG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2222
ber01-VHDL13_DWPG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                2523
ber01-VHDL13_DWPH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                2111
ber01-VHDL13_DWPH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                2685
ber01-VHDL13_DWSG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                3082
ber01-VHDL13_DWSG_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 16:58:46                2898
ber01-VHDL13_DWSG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                3269
ber01-VHDL17_DWOG_241200-2606241200-dsw--0-ia5     24-Jun-2026 11:42:06                2953
ber01-VHDL17_DWOG_251200-2606251200-dsw--0-ia5     25-Jun-2026 11:33:01                2912
swis2-VHDL20_DWEG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                1174
swis2-VHDL20_DWEG_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                 924
swis2-VHDL20_DWEG_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:03                 664
swis2-VHDL20_DWEG_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:01:20                 662
swis2-VHDL20_DWEG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                 916
swis2-VHDL20_DWEG_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                1850
swis2-VHDL20_DWEG_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:04                1381
swis2-VHDL20_DWEG_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:01:21                1297
swis2-VHDL20_DWEH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                1167
swis2-VHDL20_DWEH_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                1448
swis2-VHDL20_DWEH_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:03                1183
swis2-VHDL20_DWEH_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:01:20                1180
swis2-VHDL20_DWEH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                1454
swis2-VHDL20_DWEH_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                1743
swis2-VHDL20_DWEH_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:04                1389
swis2-VHDL20_DWEH_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:01:21                1381
swis2-VHDL20_DWEI_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                1180
swis2-VHDL20_DWEI_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                1426
swis2-VHDL20_DWEI_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:03                1177
swis2-VHDL20_DWEI_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:01:20                1174
swis2-VHDL20_DWEI_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                1462
swis2-VHDL20_DWEI_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                1981
swis2-VHDL20_DWEI_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:04                1414
swis2-VHDL20_DWEI_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:01:21                1313
swis2-VHDL20_DWHG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:45:05                1020
swis2-VHDL20_DWHG_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:45:07                1452
swis2-VHDL20_DWHG_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:45:50                1304
swis2-VHDL20_DWHG_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:20                1301
swis2-VHDL20_DWHG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:45:28                1283
swis2-VHDL20_DWHG_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:45:08                1575
swis2-VHDL20_DWHG_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:47:47                1332
swis2-VHDL20_DWHG_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:17                1352
swis2-VHDL20_DWHH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:45:05                1026
swis2-VHDL20_DWHH_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:45:07                1508
swis2-VHDL20_DWHH_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:45:50                1307
swis2-VHDL20_DWHH_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:20                1307
swis2-VHDL20_DWHH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:45:28                1059
swis2-VHDL20_DWHH_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:45:08                1461
swis2-VHDL20_DWHH_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:47:47                1280
swis2-VHDL20_DWHH_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:17                1299
swis2-VHDL20_DWLG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:22                1156
swis2-VHDL20_DWLG_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:31:05                1161
swis2-VHDL20_DWLG_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:21                1067
swis2-VHDL20_DWLG_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:10                1181
swis2-VHDL20_DWLG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:22                1578
swis2-VHDL20_DWLG_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:31:04                1593
swis2-VHDL20_DWLG_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:24                1124
swis2-VHDL20_DWLG_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:11                1124
swis2-VHDL20_DWLH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:22                1147
swis2-VHDL20_DWLH_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:31:05                1168
swis2-VHDL20_DWLH_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:21                1036
swis2-VHDL20_DWLH_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:10                1188
swis2-VHDL20_DWLH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:22                1532
swis2-VHDL20_DWLH_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:31:04                1810
swis2-VHDL20_DWLH_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:24                1381
swis2-VHDL20_DWLH_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:11                1386
swis2-VHDL20_DWLI_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:22                 892
swis2-VHDL20_DWLI_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:31:05                1163
swis2-VHDL20_DWLI_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:21                1031
swis2-VHDL20_DWLI_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:10                1183
swis2-VHDL20_DWLI_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:22                1527
swis2-VHDL20_DWLI_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:31:04                1809
swis2-VHDL20_DWLI_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:24                1360
swis2-VHDL20_DWLI_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:11                1365
swis2-VHDL20_DWMO_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                1428
swis2-VHDL20_DWMO_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                1314
swis2-VHDL20_DWMO_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:08                1003
swis2-VHDL20_DWMO_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:02                1003
swis2-VHDL20_DWMO_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                1244
swis2-VHDL20_DWMO_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                1360
swis2-VHDL20_DWMO_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:09                1083
swis2-VHDL20_DWMO_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:07                1091
swis2-VHDL20_DWMP_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:07                1549
swis2-VHDL20_DWMP_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 08:36:44                3199
swis2-VHDL20_DWMP_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                1397
swis2-VHDL20_DWMP_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:08                 983
swis2-VHDL20_DWMP_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:02                 982
swis2-VHDL20_DWMP_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:09                1407
swis2-VHDL20_DWMP_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                1520
swis2-VHDL20_DWMP_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:09                1299
swis2-VHDL20_DWMP_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:07                1306
swis2-VHDL20_DWPG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:22                1245
swis2-VHDL20_DWPG_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:31:05                1181
swis2-VHDL20_DWPG_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:21                1085
swis2-VHDL20_DWPG_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:10                1199
swis2-VHDL20_DWPG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:22                1601
swis2-VHDL20_DWPG_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:31:04                1827
swis2-VHDL20_DWPG_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:24                1376
swis2-VHDL20_DWPG_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:11                1381
swis2-VHDL20_DWPH_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:22                1258
swis2-VHDL20_DWPH_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:31:05                1210
swis2-VHDL20_DWPH_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:21                1050
swis2-VHDL20_DWPH_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:10                1249
swis2-VHDL20_DWPH_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:22                1646
swis2-VHDL20_DWPH_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:31:04                1876
swis2-VHDL20_DWPH_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:24                1425
swis2-VHDL20_DWPH_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:11                1430
swis2-VHDL20_DWSG_240800-2606240800-dsw--0-ia5     24-Jun-2026 08:30:01                1371
swis2-VHDL20_DWSG_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 16:58:46                1603
swis2-VHDL20_DWSG_241800-2606241800-dsw--0-ia5     24-Jun-2026 18:30:02                1507
swis2-VHDL20_DWSG_250200-2606250200-dsw--0-ia5     25-Jun-2026 02:30:03                1101
swis2-VHDL20_DWSG_250400-2606250400-dsw--0-ia5     25-Jun-2026 05:00:20                1100
swis2-VHDL20_DWSG_250800-2606250800-dsw--0-ia5     25-Jun-2026 08:30:04                1474
swis2-VHDL20_DWSG_251800-2606251800-dsw--0-ia5     25-Jun-2026 18:30:06                2128
swis2-VHDL20_DWSG_260200-2606260200-dsw--0-ia5     26-Jun-2026 02:30:04                1617
swis2-VHDL20_DWSG_260400-2606260400-dsw--0-ia5     26-Jun-2026 05:00:17                1624
wst04-VHDL20_DWEG_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:12              240452
wst04-VHDL20_DWEG_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:14              236055
wst04-VHDL20_DWEG_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:12              235209
wst04-VHDL20_DWEG_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:10              234647
wst04-VHDL20_DWEG_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:14              235929
wst04-VHDL20_DWEG_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:11              241378
wst04-VHDL20_DWEG_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:14              240363
wst04-VHDL20_DWEG_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:11              240243
wst04-VHDL20_DWEH_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:12              243900
wst04-VHDL20_DWEH_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:14              238841
wst04-VHDL20_DWEH_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:12              239011
wst04-VHDL20_DWEH_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:10              238460
wst04-VHDL20_DWEH_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:14              239333
wst04-VHDL20_DWEH_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:11              239915
wst04-VHDL20_DWEH_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:14              239584
wst04-VHDL20_DWEH_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:11              239342
wst04-VHDL20_DWEI_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:20              344308
wst04-VHDL20_DWEI_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:16              337069
wst04-VHDL20_DWEI_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:12              336571
wst04-VHDL20_DWEI_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:10              335970
wst04-VHDL20_DWEI_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:22              337033
wst04-VHDL20_DWEI_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:17              344941
wst04-VHDL20_DWEI_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:14              343327
wst04-VHDL20_DWEI_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:11              343058
wst04-VHDL20_DWHG_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:45:14              351185
wst04-VHDL20_DWHG_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:45:21              343694
wst04-VHDL20_DWHG_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:45:50              343783
wst04-VHDL20_DWHG_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:20              343543
wst04-VHDL20_DWHG_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:45:28              343881
wst04-VHDL20_DWHG_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:45:16              341693
wst04-VHDL20_DWHG_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:47:47              341055
wst04-VHDL20_DWHG_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:17              341055
wst04-VHDL20_DWHH_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:45:14              332418
wst04-VHDL20_DWHH_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:45:21              328586
wst04-VHDL20_DWHH_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:45:50              328340
wst04-VHDL20_DWHH_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:20              225656
wst04-VHDL20_DWHH_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:45:28              327677
wst04-VHDL20_DWHH_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:45:16              331295
wst04-VHDL20_DWHH_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:47:47              330874
wst04-VHDL20_DWHH_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:17              228444
wst04-VHDL20_DWLG_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:43              342164
wst04-VHDL20_DWLG_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:31:21              332838
wst04-VHDL20_DWLG_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:21              332905
wst04-VHDL20_DWLG_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:49              332843
wst04-VHDL20_DWLG_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:52              333295
wst04-VHDL20_DWLG_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:31:22              337532
wst04-VHDL20_DWLG_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:28              336888
wst04-VHDL20_DWLG_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:42              336753
wst04-VHDL20_DWLH_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:43              347160
wst04-VHDL20_DWLH_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:31:21              334693
wst04-VHDL20_DWLH_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:27              334767
wst04-VHDL20_DWLH_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:49              334726
wst04-VHDL20_DWLH_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:41              335116
wst04-VHDL20_DWLH_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:31:22              338340
wst04-VHDL20_DWLH_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:24              337306
wst04-VHDL20_DWLH_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:42              337140
wst04-VHDL20_DWLI_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:43              384701
wst04-VHDL20_DWLI_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:31:29              339491
wst04-VHDL20_DWLI_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:21              339584
wst04-VHDL20_DWLI_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:49              339485
wst04-VHDL20_DWLI_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:41              384488
wst04-VHDL20_DWLI_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:31:22              344436
wst04-VHDL20_DWLI_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:24              343371
wst04-VHDL20_DWLI_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:42              343199
wst04-VHDL20_DWMO_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:22              461523
wst04-VHDL20_DWMO_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:16              346036
wst04-VHDL20_DWMO_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:17              455120
wst04-VHDL20_DWMO_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:20              455007
wst04-VHDL20_DWMO_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:22              455380
wst04-VHDL20_DWMO_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:17              353434
wst04-VHDL20_DWMO_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:19              461773
wst04-VHDL20_DWMO_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:17              461674
wst04-VHDL20_DWMP_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:22              471287
wst04-VHDL20_DWMP_240800_COR-2606240800-omedes-..> 24-Jun-2026 08:36:59              581275
wst04-VHDL20_DWMP_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:16              454493
wst04-VHDL20_DWMP_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:17              556263
wst04-VHDL20_DWMP_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:20              556233
wst04-VHDL20_DWMP_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:22              454073
wst04-VHDL20_DWMP_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:17              460212
wst04-VHDL20_DWMP_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:19              560422
wst04-VHDL20_DWMP_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:17              560372
wst04-VHDL20_DWPG_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:48              400367
wst04-VHDL20_DWPG_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:31:21              340426
wst04-VHDL20_DWPG_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:21              240683
wst04-VHDL20_DWPG_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:32              340489
wst04-VHDL20_DWPG_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:41              385442
wst04-VHDL20_DWPG_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:31:27              351340
wst04-VHDL20_DWPG_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:24              244919
wst04-VHDL20_DWPG_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:30              350157
wst04-VHDL20_DWPH_240800-2606240800-omedes--0.pdf  24-Jun-2026 08:30:43              242755
wst04-VHDL20_DWPH_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:31:21              239792
wst04-VHDL20_DWPH_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:21              239243
wst04-VHDL20_DWPH_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:32              239811
wst04-VHDL20_DWPH_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:41              240146
wst04-VHDL20_DWPH_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:31:22              239047
wst04-VHDL20_DWPH_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:24              238764
wst04-VHDL20_DWPH_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:30              238611
wst04-VHDL20_DWSG_240800-2606240800-omedes--0.pdf  24-Jun-2026 16:58:56              337864
wst04-VHDL20_DWSG_241800-2606241800-omedes--0.pdf  24-Jun-2026 18:30:11              337643
wst04-VHDL20_DWSG_250200-2606250200-omedes--0.pdf  25-Jun-2026 02:30:12              335882
wst04-VHDL20_DWSG_250400-2606250400-omedes--0.pdf  25-Jun-2026 05:00:20              335900
wst04-VHDL20_DWSG_250800-2606250800-omedes--0.pdf  25-Jun-2026 08:30:22              336726
wst04-VHDL20_DWSG_251800-2606251800-omedes--0.pdf  25-Jun-2026 18:30:11              348272
wst04-VHDL20_DWSG_260200-2606260200-omedes--0.pdf  26-Jun-2026 02:30:14              346964
wst04-VHDL20_DWSG_260400-2606260400-omedes--0.pdf  26-Jun-2026 05:00:11              347080