Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Mar-2026 14:14:59 3268
FPDL13_DWMZ_070600 07-Mar-2026 12:26:09 11913
SXDL31_DWAV_061800 06-Mar-2026 17:12:33 3429
SXDL31_DWAV_070800 07-Mar-2026 08:01:15 5839
SXDL31_DWAV_071800 07-Mar-2026 17:33:37 6449
SXDL31_DWAV_080800 08-Mar-2026 08:52:18 7051
SXDL31_DWAV_LATEST 08-Mar-2026 08:52:18 7051
SXDL33_DWAV_060000 06-Mar-2026 10:27:55 5630
SXDL33_DWAV_070000 07-Mar-2026 11:29:13 11483
SXDL33_DWAV_LATEST 07-Mar-2026 11:29:13 11483
ber01-FWDL39_DWMS_061230-2603061230-dsw--0-ia5 06-Mar-2026 13:07:21 1332
ber01-FWDL39_DWMS_071230-2603071230-dsw--0-ia5 07-Mar-2026 12:39:17 1150
ber01-VHDL13_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2559
ber01-VHDL13_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2590
ber01-VHDL13_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2442
ber01-VHDL13_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2445
ber01-VHDL13_DWEH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2439
ber01-VHDL13_DWEH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:12 2845
ber01-VHDL13_DWEH_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2765
ber01-VHDL13_DWEH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:17 2667
ber01-VHDL13_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2424
ber01-VHDL13_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2735
ber01-VHDL13_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2897
ber01-VHDL13_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2897
ber01-VHDL13_DWHG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2415
ber01-VHDL13_DWHG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:14 2814
ber01-VHDL13_DWHG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2794
ber01-VHDL13_DWHG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3446
ber01-VHDL13_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2305
ber01-VHDL13_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2474
ber01-VHDL13_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2476
ber01-VHDL13_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2520
ber01-VHDL13_DWHH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2140
ber01-VHDL13_DWHH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:14 2415
ber01-VHDL13_DWHH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2403
ber01-VHDL13_DWHH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3459
ber01-VHDL13_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1541
ber01-VHDL13_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1718
ber01-VHDL13_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1927
ber01-VHDL13_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:07 2088
ber01-VHDL13_DWLG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1983
ber01-VHDL13_DWLG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2435
ber01-VHDL13_DWLG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 2382
ber01-VHDL13_DWLG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2528
ber01-VHDL13_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2015
ber01-VHDL13_DWLH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1937
ber01-VHDL13_DWLH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2129
ber01-VHDL13_DWLH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2155
ber01-VHDL13_DWLH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1874
ber01-VHDL13_DWLH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2216
ber01-VHDL13_DWLH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2150
ber01-VHDL13_DWLH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2026
ber01-VHDL13_DWLI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1512
ber01-VHDL13_DWLI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1711
ber01-VHDL13_DWLI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1801
ber01-VHDL13_DWLI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 1944
ber01-VHDL13_DWLI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1905
ber01-VHDL13_DWLI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:02 2223
ber01-VHDL13_DWLI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2236
ber01-VHDL13_DWLI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2132
ber01-VHDL13_DWMG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2370
ber01-VHDL13_DWMG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2370
ber01-VHDL13_DWMG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2320
ber01-VHDL13_DWMG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2202
ber01-VHDL13_DWMG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2330
ber01-VHDL13_DWMG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 1864
ber01-VHDL13_DWMG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 1869
ber01-VHDL13_DWMG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1706
ber01-VHDL13_DWMO_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2302
ber01-VHDL13_DWMO_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2435
ber01-VHDL13_DWMO_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2435
ber01-VHDL13_DWMO_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2322
ber01-VHDL13_DWMO_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2296
ber01-VHDL13_DWMO_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2088
ber01-VHDL13_DWMO_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 2096
ber01-VHDL13_DWMO_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1925
ber01-VHDL13_DWMP_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2283
ber01-VHDL13_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2412
ber01-VHDL13_DWMP_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2412
ber01-VHDL13_DWMP_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2279
ber01-VHDL13_DWMP_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2144
ber01-VHDL13_DWMP_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:02 2032
ber01-VHDL13_DWMP_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:00 2046
ber01-VHDL13_DWMP_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1921
ber01-VHDL13_DWOG_061700-2603061700-dsw--0-ia5 06-Mar-2026 19:00:06 3023
ber01-VHDL13_DWOG_070300-2603070300-dsw--0-ia5 07-Mar-2026 04:00:01 3613
ber01-VHDL13_DWOG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 3484
ber01-VHDL13_DWOG_071700-2603071700-dsw--0-ia5 07-Mar-2026 19:00:05 2785
ber01-VHDL13_DWOG_080300-2603080300-dsw--0-ia5 08-Mar-2026 04:00:07 3100
ber01-VHDL13_DWOG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 3375
ber01-VHDL13_DWOH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2410
ber01-VHDL13_DWOH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2650
ber01-VHDL13_DWOH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2599
ber01-VHDL13_DWOH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2521
ber01-VHDL13_DWOH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2497
ber01-VHDL13_DWOH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:12 2682
ber01-VHDL13_DWOH_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2671
ber01-VHDL13_DWOH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:17 2646
ber01-VHDL13_DWOI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2167
ber01-VHDL13_DWOI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:17 2367
ber01-VHDL13_DWOI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:08:07 2274
ber01-VHDL13_DWOI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2280
ber01-VHDL13_DWOI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2350
ber01-VHDL13_DWOI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:28:16 2591
ber01-VHDL13_DWOI_080400-2603080400-dsw--0-ia5 08-Mar-2026 05:58:17 2503
ber01-VHDL13_DWOI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:28:13 2483
ber01-VHDL13_DWON_061157-2603061157-dsw--0-ia5 06-Mar-2026 11:57:38 3365
ber01-VHDL13_DWON_061537-2603061537-dsw--0-ia5 06-Mar-2026 15:37:43 2935
ber01-VHDL13_DWON_061712-2603061712-dsw--0-ia5 06-Mar-2026 17:12:58 2935
ber01-VHDL13_DWON_061726-2603061726-dsw--0-ia5 06-Mar-2026 17:26:17 3145
ber01-VHDL13_DWON_062246-2603062246-dsw--0-ia5 06-Mar-2026 22:46:25 3207
ber01-VHDL13_DWON_070131-2603070131-dsw--0-ia5 07-Mar-2026 01:31:30 3260
ber01-VHDL13_DWON_070426-2603070426-dsw--0-ia5 07-Mar-2026 04:26:47 3260
ber01-VHDL13_DWON_070545-2603070545-dsw--0-ia5 07-Mar-2026 05:45:12 3440
ber01-VHDL13_DWON_071002-2603071002-dsw--0-ia5 07-Mar-2026 10:02:17 3440
ber01-VHDL13_DWON_071401-2603071401-dsw--0-ia5 07-Mar-2026 14:01:21 3590
ber01-VHDL13_DWON_071522-2603071522-dsw--0-ia5 07-Mar-2026 15:22:48 3590
ber01-VHDL13_DWON_071833-2603071833-dsw--0-ia5 07-Mar-2026 18:33:44 3013
ber01-VHDL13_DWON_080119-2603080119-dsw--0-ia5 08-Mar-2026 01:19:52 3342
ber01-VHDL13_DWON_080343-2603080343-dsw--0-ia5 08-Mar-2026 03:43:07 3342
ber01-VHDL13_DWON_080614-2603080614-dsw--0-ia5 08-Mar-2026 06:14:36 3491
ber01-VHDL13_DWON_080927-2603080927-dsw--0-ia5 08-Mar-2026 09:27:22 3390
ber01-VHDL13_DWON_080946-2603080946-dsw--0-ia5 08-Mar-2026 09:46:21 3599
ber01-VHDL13_DWPG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1848
ber01-VHDL13_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1829
ber01-VHDL13_DWPG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2243
ber01-VHDL13_DWPG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2115
ber01-VHDL13_DWPG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1901
ber01-VHDL13_DWPG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2018
ber01-VHDL13_DWPG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 1942
ber01-VHDL13_DWPG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 1937
ber01-VHDL13_DWPH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2034
ber01-VHDL13_DWPH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1780
ber01-VHDL13_DWPH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2278
ber01-VHDL13_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2191
ber01-VHDL13_DWPH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2001
ber01-VHDL13_DWPH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2154
ber01-VHDL13_DWPH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:06 2196
ber01-VHDL13_DWPH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2205
ber01-VHDL13_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2101
ber01-VHDL13_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2400
ber01-VHDL13_DWSG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2484
ber01-VHDL13_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2393
ber01-VHDL13_DWSG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2321
ber01-VHDL13_DWSG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:30:03 2389
ber01-VHDL13_DWSG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2577
ber01-VHDL13_DWSG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:30:05 2784
ber01-VHDL17_DWOG_061200-2603061200-dsw--0-ia5 06-Mar-2026 12:02:46 1871
ber01-VHDL17_DWOG_071200-2603071200-dsw--0-ia5 07-Mar-2026 10:53:51 3549
swis2-VHDL20_DWEG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2736
swis2-VHDL20_DWEG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2926
swis2-VHDL20_DWEG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2919
swis2-VHDL20_DWEG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2995
swis2-VHDL20_DWEG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2823
swis2-VHDL20_DWEG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2958
swis2-VHDL20_DWEG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 2990
swis2-VHDL20_DWEG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3124
swis2-VHDL20_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2913
swis2-VHDL20_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2911
swis2-VHDL20_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2777
swis2-VHDL20_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2944
swis2-VHDL20_DWEH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2793
swis2-VHDL20_DWEH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 3166
swis2-VHDL20_DWEH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 3099
swis2-VHDL20_DWEH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3170
swis2-VHDL20_DWEI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2518
swis2-VHDL20_DWEI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2659
swis2-VHDL20_DWEI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2625
swis2-VHDL20_DWEI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2801
swis2-VHDL20_DWEI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2701
swis2-VHDL20_DWEI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2883
swis2-VHDL20_DWEI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:06 2853
swis2-VHDL20_DWEI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3008
swis2-VHDL20_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2607
swis2-VHDL20_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2921
swis2-VHDL20_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 3080
swis2-VHDL20_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3428
swis2-VHDL20_DWHG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:06 2598
swis2-VHDL20_DWHG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 3000
swis2-VHDL20_DWHG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2977
swis2-VHDL20_DWHG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 4132
swis2-VHDL20_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2491
swis2-VHDL20_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2660
swis2-VHDL20_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2662
swis2-VHDL20_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3063
swis2-VHDL20_DWHH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:06 2326
swis2-VHDL20_DWHH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2601
swis2-VHDL20_DWHH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:07 2589
swis2-VHDL20_DWHH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 3998
swis2-VHDL20_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 1883
swis2-VHDL20_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2060
swis2-VHDL20_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2269
swis2-VHDL20_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2574
swis2-VHDL20_DWLG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2325
swis2-VHDL20_DWLG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2777
swis2-VHDL20_DWLG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2722
swis2-VHDL20_DWLG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 3015
swis2-VHDL20_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2363
swis2-VHDL20_DWLH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2285
swis2-VHDL20_DWLH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2478
swis2-VHDL20_DWLH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2652
swis2-VHDL20_DWLH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2223
swis2-VHDL20_DWLH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2565
swis2-VHDL20_DWLH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2497
swis2-VHDL20_DWLH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2523
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swis2-VHDL20_DWLI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2055
swis2-VHDL20_DWLI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:15 2145
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swis2-VHDL20_DWLI_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2567
swis2-VHDL20_DWLI_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2578
swis2-VHDL20_DWLI_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2620
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swis2-VHDL20_DWMG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2759
swis2-VHDL20_DWMG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2710
swis2-VHDL20_DWMG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2767
swis2-VHDL20_DWMG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2720
swis2-VHDL20_DWMG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2296
swis2-VHDL20_DWMG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2309
swis2-VHDL20_DWMG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2364
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swis2-VHDL20_DWMO_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2829
swis2-VHDL20_DWMO_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2829
swis2-VHDL20_DWMO_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2895
swis2-VHDL20_DWMO_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2690
swis2-VHDL20_DWMO_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2524
swis2-VHDL20_DWMO_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2531
swis2-VHDL20_DWMO_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2583
swis2-VHDL20_DWMP_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:07 2653
swis2-VHDL20_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2805
swis2-VHDL20_DWMP_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2802
swis2-VHDL20_DWMP_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2850
swis2-VHDL20_DWMP_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2526
swis2-VHDL20_DWMP_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2467
swis2-VHDL20_DWMP_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2416
swis2-VHDL20_DWMP_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 2515
swis2-VHDL20_DWPG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2307
swis2-VHDL20_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2158
swis2-VHDL20_DWPG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2569
swis2-VHDL20_DWPG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2573
swis2-VHDL20_DWPG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2359
swis2-VHDL20_DWPG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2347
swis2-VHDL20_DWPG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2267
swis2-VHDL20_DWPG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2394
swis2-VHDL20_DWPH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2493
swis2-VHDL20_DWPH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2108
swis2-VHDL20_DWPH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2606
swis2-VHDL20_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2649
swis2-VHDL20_DWPH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2459
swis2-VHDL20_DWPH_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:06 2482
swis2-VHDL20_DWPH_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:00:11 2523
swis2-VHDL20_DWPH_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:06 2663
swis2-VHDL20_DWSG_061300-2603061300-dsw--0-ia5 06-Mar-2026 14:45:06 2570
swis2-VHDL20_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2455
swis2-VHDL20_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2745
swis2-VHDL20_DWSG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2836
swis2-VHDL20_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2888
swis2-VHDL20_DWSG_071300-2603071300-dsw--0-ia5 07-Mar-2026 14:45:15 2820
swis2-VHDL20_DWSG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2695
swis2-VHDL20_DWSG_080200-2603080200-dsw--0-ia5 08-Mar-2026 03:45:02 2797
swis2-VHDL20_DWSG_080400-2603080400-dsw--0-ia5 08-Mar-2026 06:15:02 2998
swis2-VHDL20_DWSG_080800-2603080800-dsw--0-ia5 08-Mar-2026 09:45:02 3351
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wst04-VHDL20_DWEG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 247010
wst04-VHDL20_DWEG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 246038
wst04-VHDL20_DWEG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 247207
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wst04-VHDL20_DWEG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 247328
wst04-VHDL20_DWEG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 246376
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wst04-VHDL20_DWEH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 246239
wst04-VHDL20_DWEH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:17 244582
wst04-VHDL20_DWEH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 245375
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wst04-VHDL20_DWEH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 246465
wst04-VHDL20_DWEH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 245834
wst04-VHDL20_DWEH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:22 249051
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wst04-VHDL20_DWEI_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 355254
wst04-VHDL20_DWEI_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:21 354741
wst04-VHDL20_DWEI_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:11 356387
wst04-VHDL20_DWEI_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:16 355816
wst04-VHDL20_DWEI_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:23 356498
wst04-VHDL20_DWEI_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:22 355993
wst04-VHDL20_DWEI_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:26 350174
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wst04-VHDL20_DWHG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 354516
wst04-VHDL20_DWHG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:13 354659
wst04-VHDL20_DWHG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 356997
wst04-VHDL20_DWHG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 354547
wst04-VHDL20_DWHG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 354867
wst04-VHDL20_DWHG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:11 354938
wst04-VHDL20_DWHG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 358934
wst04-VHDL20_DWHH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 335844
wst04-VHDL20_DWHH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 336304
wst04-VHDL20_DWHH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:13 336323
wst04-VHDL20_DWHH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 336047
wst04-VHDL20_DWHH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 333802
wst04-VHDL20_DWHH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 334853
wst04-VHDL20_DWHH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:11 334923
wst04-VHDL20_DWHH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:22 337233
wst04-VHDL20_DWLG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 345004
wst04-VHDL20_DWLG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 345514
wst04-VHDL20_DWLG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 345321
wst04-VHDL20_DWLG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 353524
wst04-VHDL20_DWLG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 353732
wst04-VHDL20_DWLG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 353741
wst04-VHDL20_DWLG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 353726
wst04-VHDL20_DWLG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:36 342835
wst04-VHDL20_DWLH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 354103
wst04-VHDL20_DWLH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 354351
wst04-VHDL20_DWLH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 354460
wst04-VHDL20_DWLH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 347549
wst04-VHDL20_DWLH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 347424
wst04-VHDL20_DWLH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 347108
wst04-VHDL20_DWLH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 346988
wst04-VHDL20_DWLH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 339768
wst04-VHDL20_DWLI_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 345613
wst04-VHDL20_DWLI_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 345315
wst04-VHDL20_DWLI_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 345308
wst04-VHDL20_DWLI_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 343395
wst04-VHDL20_DWLI_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 342983
wst04-VHDL20_DWLI_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 342869
wst04-VHDL20_DWLI_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:42 342971
wst04-VHDL20_DWLI_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 337596
wst04-VHDL20_DWMG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 581388
wst04-VHDL20_DWMG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 581559
wst04-VHDL20_DWMG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 581767
wst04-VHDL20_DWMG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 588174
wst04-VHDL20_DWMG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 587223
wst04-VHDL20_DWMG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:17 586556
wst04-VHDL20_DWMG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:26 586445
wst04-VHDL20_DWMG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 557058
wst04-VHDL20_DWMO_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 481633
wst04-VHDL20_DWMO_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 482319
wst04-VHDL20_DWMO_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:21 482745
wst04-VHDL20_DWMO_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 476714
wst04-VHDL20_DWMO_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 475174
wst04-VHDL20_DWMO_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 476048
wst04-VHDL20_DWMO_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:16 476552
wst04-VHDL20_DWMO_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:12 460122
wst04-VHDL20_DWMP_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 569532
wst04-VHDL20_DWMP_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 568482
wst04-VHDL20_DWMP_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 569323
wst04-VHDL20_DWMP_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 573450
wst04-VHDL20_DWMP_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 572358
wst04-VHDL20_DWMP_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 571192
wst04-VHDL20_DWMP_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:22 572322
wst04-VHDL20_DWMP_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:16 555278
wst04-VHDL20_DWPG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 355913
wst04-VHDL20_DWPG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 356233
wst04-VHDL20_DWPG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:31 356676
wst04-VHDL20_DWPG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:37 403974
wst04-VHDL20_DWPG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 359188
wst04-VHDL20_DWPG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:27 358267
wst04-VHDL20_DWPG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:31 358173
wst04-VHDL20_DWPG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 394533
wst04-VHDL20_DWPH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 296230
wst04-VHDL20_DWPH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 251473
wst04-VHDL20_DWPH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:31 252332
wst04-VHDL20_DWPH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 295720
wst04-VHDL20_DWPH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 295732
wst04-VHDL20_DWPH_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:21 250145
wst04-VHDL20_DWPH_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:00:31 249877
wst04-VHDL20_DWPH_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:32 294479
wst04-VHDL20_DWSG_061300-2603061300-omedes--0.pdf 06-Mar-2026 14:45:12 367113
wst04-VHDL20_DWSG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:11 366955
wst04-VHDL20_DWSG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 367140
wst04-VHDL20_DWSG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:17 367503
wst04-VHDL20_DWSG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:11 360470
wst04-VHDL20_DWSG_071300-2603071300-omedes--0.pdf 07-Mar-2026 14:45:15 360437
wst04-VHDL20_DWSG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:12 360452
wst04-VHDL20_DWSG_080200-2603080200-omedes--0.pdf 08-Mar-2026 03:45:11 360370
wst04-VHDL20_DWSG_080400-2603080400-omedes--0.pdf 08-Mar-2026 06:15:12 360855
wst04-VHDL20_DWSG_080800-2603080800-omedes--0.pdf 08-Mar-2026 09:45:12 358109