Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_090600 09-Jul-2026 12:44:23 3139
FPDL13_DWMZ_100600 10-Jul-2026 14:11:19 4131
SXDL31_DWAV_090800 09-Jul-2026 07:06:39 5600
SXDL31_DWAV_091800 09-Jul-2026 15:07:39 10899
SXDL31_DWAV_100800 10-Jul-2026 07:44:32 10139
SXDL31_DWAV_101800 10-Jul-2026 16:12:34 4208
SXDL31_DWAV_LATEST 10-Jul-2026 16:12:34 4208
SXDL33_DWAV_090000 09-Jul-2026 09:21:55 8380
SXDL33_DWAV_100000 10-Jul-2026 09:50:10 6024
SXDL33_DWAV_LATEST 10-Jul-2026 09:50:10 6024
ber01-FWDL39_DWMS_091200-2607091200-dsw--0-ia5 09-Jul-2026 11:04:12 1683
ber01-FWDL39_DWMS_101200-2607101200-dsw--0-ia5 10-Jul-2026 11:28:38 1450
ber01-VHDL13_DWEG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:28:17 2272
ber01-VHDL13_DWEG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:12 2073
ber01-VHDL13_DWEH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:28:17 2222
ber01-VHDL13_DWEH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:16 2072
ber01-VHDL13_DWEI_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:28:17 1990
ber01-VHDL13_DWEI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:16 1906
ber01-VHDL13_DWHG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2838
ber01-VHDL13_DWHG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2726
ber01-VHDL13_DWHG_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:44:03 2695
ber01-VHDL13_DWHH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2754
ber01-VHDL13_DWHH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2646
ber01-VHDL13_DWHH_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:44:52 2650
ber01-VHDL13_DWLG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2159
ber01-VHDL13_DWLG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2023
ber01-VHDL13_DWLH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2115
ber01-VHDL13_DWLH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1903
ber01-VHDL13_DWLI_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 1990
ber01-VHDL13_DWLI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1873
ber01-VHDL13_DWMO_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2565
ber01-VHDL13_DWMO_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2104
ber01-VHDL13_DWMO_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:42 2118
ber01-VHDL13_DWMP_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2141
ber01-VHDL13_DWMP_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2092
ber01-VHDL13_DWMP_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:52 2098
ber01-VHDL13_DWOG_090300-2607090300-dsw--0-ia5 09-Jul-2026 03:00:10 2615
ber01-VHDL13_DWOG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 2616
ber01-VHDL13_DWOG_091700-2607091700-dsw--0-ia5 09-Jul-2026 18:00:08 2258
ber01-VHDL13_DWOG_100300-2607100300-dsw--0-ia5 10-Jul-2026 03:00:02 2569
ber01-VHDL13_DWOG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2497
ber01-VHDL13_DWOG_101700-2607101700-dsw--0-ia5 10-Jul-2026 18:00:01 2345
ber01-VHDL13_DWON_082356-2607082356-dsw--0-ia5 08-Jul-2026 23:56:17 3078
ber01-VHDL13_DWON_090211-2607090211-dsw--0-ia5 09-Jul-2026 02:11:10 3078
ber01-VHDL13_DWON_090341-2607090341-dsw--0-ia5 09-Jul-2026 03:41:50 3078
ber01-VHDL13_DWON_090503-2607090503-dsw--0-ia5 09-Jul-2026 05:03:42 3235
ber01-VHDL13_DWON_090538-2607090538-dsw--0-ia5 09-Jul-2026 05:38:50 3235
ber01-VHDL13_DWON_090547-2607090547-dsw--0-ia5 09-Jul-2026 05:47:41 3235
ber01-VHDL13_DWON_090746-2607090746-dsw--0-ia5 09-Jul-2026 07:46:43 3235
ber01-VHDL13_DWON_090844-2607090844-dsw--0-ia5 09-Jul-2026 08:45:00 3195
ber01-VHDL13_DWON_091453-2607091453-dsw--0-ia5 09-Jul-2026 14:53:47 2712
ber01-VHDL13_DWON_091633-2607091633-dsw--0-ia5 09-Jul-2026 16:33:18 2455
ber01-VHDL13_DWON_091635-2607091635-dsw--0-ia5 09-Jul-2026 16:35:48 2455
ber01-VHDL13_DWON_091841-2607091841-dsw--0-ia5 09-Jul-2026 18:41:42 2450
ber01-VHDL13_DWON_100017-2607100017-dsw--0-ia5 10-Jul-2026 00:17:57 2615
ber01-VHDL13_DWON_100215-2607100215-dsw--0-ia5 10-Jul-2026 02:15:21 2615
ber01-VHDL13_DWON_100530-2607100530-dsw--0-ia5 10-Jul-2026 05:30:12 3065
ber01-VHDL13_DWON_100627-2607100627-dsw--0-ia5 10-Jul-2026 06:27:51 3065
ber01-VHDL13_DWON_101140-2607101140-dsw--0-ia5 10-Jul-2026 11:40:16 3065
ber01-VHDL13_DWON_101505-2607101505-dsw--0-ia5 10-Jul-2026 15:05:32 2784
ber01-VHDL13_DWON_101629-2607101629-dsw--0-ia5 10-Jul-2026 16:29:52 2861
ber01-VHDL13_DWON_101632-2607101632-dsw--0-ia5 10-Jul-2026 16:32:11 2857
ber01-VHDL13_DWON_101819-2607101819-dsw--0-ia5 10-Jul-2026 18:20:01 3369
ber01-VHDL13_DWON_102143-2607102143-dsw--0-ia5 10-Jul-2026 21:43:41 3362
ber01-VHDL13_DWPG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2117
ber01-VHDL13_DWPG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2005
ber01-VHDL13_DWPH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 2224
ber01-VHDL13_DWPH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1969
ber01-VHDL13_DWSG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 2195
ber01-VHDL13_DWSG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2561
ber01-VHDL17_DWOG_091200-2607091200-dsw--0-ia5 09-Jul-2026 11:48:07 2923
ber01-VHDL17_DWOG_101200-2607101200-dsw--0-ia5 10-Jul-2026 11:22:02 3022
swis2-VHDL20_DWEG_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 807
swis2-VHDL20_DWEG_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:01:21 823
swis2-VHDL20_DWEG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 937
swis2-VHDL20_DWEG_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 954
swis2-VHDL20_DWEG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 737
swis2-VHDL20_DWEG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 724
swis2-VHDL20_DWEG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 888
swis2-VHDL20_DWEG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 923
swis2-VHDL20_DWEH_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 821
swis2-VHDL20_DWEH_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:01:21 821
swis2-VHDL20_DWEH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 929
swis2-VHDL20_DWEH_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 999
swis2-VHDL20_DWEH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 770
swis2-VHDL20_DWEH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 757
swis2-VHDL20_DWEH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 915
swis2-VHDL20_DWEH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 949
swis2-VHDL20_DWEI_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 845
swis2-VHDL20_DWEI_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:01:21 845
swis2-VHDL20_DWEI_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 959
swis2-VHDL20_DWEI_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 976
swis2-VHDL20_DWEI_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 759
swis2-VHDL20_DWEI_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 746
swis2-VHDL20_DWEI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 910
swis2-VHDL20_DWEI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 945
swis2-VHDL20_DWHG_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:45:02 964
swis2-VHDL20_DWHG_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:17 961
swis2-VHDL20_DWHG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:45:03 1038
swis2-VHDL20_DWHG_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:45:01 1085
swis2-VHDL20_DWHG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:45:13 931
swis2-VHDL20_DWHG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 928
swis2-VHDL20_DWHG_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:45:28 1013
swis2-VHDL20_DWHG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 966
swis2-VHDL20_DWHH_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:45:02 967
swis2-VHDL20_DWHH_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:17 967
swis2-VHDL20_DWHH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:45:03 1046
swis2-VHDL20_DWHH_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:45:01 1090
swis2-VHDL20_DWHH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:45:13 934
swis2-VHDL20_DWHH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 934
swis2-VHDL20_DWHH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:45:28 1038
swis2-VHDL20_DWHH_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:45:31 1042
swis2-VHDL20_DWHH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 972
swis2-VHDL20_DWLG_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:23 794
swis2-VHDL20_DWLG_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:11 791
swis2-VHDL20_DWLG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:21 898
swis2-VHDL20_DWLG_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:31:09 864
swis2-VHDL20_DWLG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 760
swis2-VHDL20_DWLG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 745
swis2-VHDL20_DWLG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 825
swis2-VHDL20_DWLG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 825
swis2-VHDL20_DWLH_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:23 805
swis2-VHDL20_DWLH_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:11 802
swis2-VHDL20_DWLH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:21 909
swis2-VHDL20_DWLH_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:31:09 873
swis2-VHDL20_DWLH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 769
swis2-VHDL20_DWLH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 754
swis2-VHDL20_DWLH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 834
swis2-VHDL20_DWLH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 834
swis2-VHDL20_DWLI_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:23 796
swis2-VHDL20_DWLI_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:11 793
swis2-VHDL20_DWLI_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:21 900
swis2-VHDL20_DWLI_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:31:09 866
swis2-VHDL20_DWLI_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 762
swis2-VHDL20_DWLI_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 747
swis2-VHDL20_DWLI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 827
swis2-VHDL20_DWLI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 827
swis2-VHDL20_DWMO_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 832
swis2-VHDL20_DWMO_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:03 833
swis2-VHDL20_DWMO_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 858
swis2-VHDL20_DWMO_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 865
swis2-VHDL20_DWMO_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 740
swis2-VHDL20_DWMO_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:01 741
swis2-VHDL20_DWMO_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 855
swis2-VHDL20_DWMO_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:42 2773
swis2-VHDL20_DWMO_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 905
swis2-VHDL20_DWMP_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 833
swis2-VHDL20_DWMP_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:03 833
swis2-VHDL20_DWMP_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:09 982
swis2-VHDL20_DWMP_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 865
swis2-VHDL20_DWMP_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 741
swis2-VHDL20_DWMP_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:01 741
swis2-VHDL20_DWMP_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 854
swis2-VHDL20_DWMP_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:52 2783
swis2-VHDL20_DWMP_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 877
swis2-VHDL20_DWPG_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:23 812
swis2-VHDL20_DWPG_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:11 810
swis2-VHDL20_DWPG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:21 904
swis2-VHDL20_DWPG_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:31:09 882
swis2-VHDL20_DWPG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 778
swis2-VHDL20_DWPG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 763
swis2-VHDL20_DWPG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 843
swis2-VHDL20_DWPG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 843
swis2-VHDL20_DWPH_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:23 817
swis2-VHDL20_DWPH_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:11 815
swis2-VHDL20_DWPH_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:21 909
swis2-VHDL20_DWPH_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:31:09 882
swis2-VHDL20_DWPH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 778
swis2-VHDL20_DWPH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 763
swis2-VHDL20_DWPH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 840
swis2-VHDL20_DWPH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 840
swis2-VHDL20_DWSG_090200-2607090200-dsw--0-ia5 09-Jul-2026 02:30:02 789
swis2-VHDL20_DWSG_090400-2607090400-dsw--0-ia5 09-Jul-2026 05:00:17 704
swis2-VHDL20_DWSG_090800-2607090800-dsw--0-ia5 09-Jul-2026 08:30:01 869
swis2-VHDL20_DWSG_091800-2607091800-dsw--0-ia5 09-Jul-2026 18:30:01 850
swis2-VHDL20_DWSG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 751
swis2-VHDL20_DWSG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 909
swis2-VHDL20_DWSG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1106
swis2-VHDL20_DWSG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 850
wst04-VHDL20_DWEG_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:13 237652
wst04-VHDL20_DWEG_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:11 237494
wst04-VHDL20_DWEG_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:15 238240
wst04-VHDL20_DWEG_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:10 235897
wst04-VHDL20_DWEG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 234130
wst04-VHDL20_DWEG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 233977
wst04-VHDL20_DWEG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 234756
wst04-VHDL20_DWEG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:13 236532
wst04-VHDL20_DWEH_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:13 237370
wst04-VHDL20_DWEH_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:11 237485
wst04-VHDL20_DWEH_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:15 238232
wst04-VHDL20_DWEH_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:17 238251
wst04-VHDL20_DWEH_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 236790
wst04-VHDL20_DWEH_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 236916
wst04-VHDL20_DWEH_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 237713
wst04-VHDL20_DWEH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 238400
wst04-VHDL20_DWEI_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:17 344775
wst04-VHDL20_DWEI_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:17 344582
wst04-VHDL20_DWEI_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:17 344803
wst04-VHDL20_DWEI_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:17 339131
wst04-VHDL20_DWEI_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 337898
wst04-VHDL20_DWEI_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 337749
wst04-VHDL20_DWEI_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 338003
wst04-VHDL20_DWEI_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 335245
wst04-VHDL20_DWHG_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:45:13 338191
wst04-VHDL20_DWHG_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:21 337963
wst04-VHDL20_DWHG_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:45:28 339098
wst04-VHDL20_DWHG_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:45:13 346688
wst04-VHDL20_DWHG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:45:13 346356
wst04-VHDL20_DWHG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:17 345610
wst04-VHDL20_DWHG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:45:28 346171
wst04-VHDL20_DWHG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:45:13 348239
wst04-VHDL20_DWHH_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:45:13 323107
wst04-VHDL20_DWHH_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:17 218847
wst04-VHDL20_DWHH_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:45:28 323484
wst04-VHDL20_DWHH_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:45:13 329176
wst04-VHDL20_DWHH_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:45:13 329013
wst04-VHDL20_DWHH_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:17 220941
wst04-VHDL20_DWHH_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:45:28 328666
wst04-VHDL20_DWHH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:45:13 335418
wst04-VHDL20_DWLG_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:23 339868
wst04-VHDL20_DWLG_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:41 339694
wst04-VHDL20_DWLG_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:41 339913
wst04-VHDL20_DWLG_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:31:26 341119
wst04-VHDL20_DWLG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:27 339933
wst04-VHDL20_DWLG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:41 340454
wst04-VHDL20_DWLG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:50 340616
wst04-VHDL20_DWLG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:31:24 337520
wst04-VHDL20_DWLH_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:23 330604
wst04-VHDL20_DWLH_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:41 330417
wst04-VHDL20_DWLH_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:41 330651
wst04-VHDL20_DWLH_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:31:26 338957
wst04-VHDL20_DWLH_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:21 337754
wst04-VHDL20_DWLH_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:41 338274
wst04-VHDL20_DWLH_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:41 338482
wst04-VHDL20_DWLH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:31:24 338480
wst04-VHDL20_DWLI_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:23 332989
wst04-VHDL20_DWLI_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:41 332780
wst04-VHDL20_DWLI_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:41 377597
wst04-VHDL20_DWLI_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:31:26 341817
wst04-VHDL20_DWLI_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:27 340642
wst04-VHDL20_DWLI_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:41 341150
wst04-VHDL20_DWLI_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:41 385907
wst04-VHDL20_DWLI_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:31:24 336245
wst04-VHDL20_DWMO_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:17 465639
wst04-VHDL20_DWMO_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:17 465497
wst04-VHDL20_DWMO_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:15 466903
wst04-VHDL20_DWMO_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:17 351013
wst04-VHDL20_DWMO_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:17 464601
wst04-VHDL20_DWMO_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:17 464433
wst04-VHDL20_DWMO_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 465714
wst04-VHDL20_DWMO_100800_COR-2607100800-omedes-..> 10-Jul-2026 09:13:52 469937
wst04-VHDL20_DWMO_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 347212
wst04-VHDL20_DWMP_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:17 583621
wst04-VHDL20_DWMP_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:17 583416
wst04-VHDL20_DWMP_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:21 471905
wst04-VHDL20_DWMP_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:17 472276
wst04-VHDL20_DWMP_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:17 578021
wst04-VHDL20_DWMP_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:17 577788
wst04-VHDL20_DWMP_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:21 472919
wst04-VHDL20_DWMP_100800_COR-2607100800-omedes-..> 10-Jul-2026 09:14:02 583822
wst04-VHDL20_DWMP_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 458304
wst04-VHDL20_DWPG_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:29 241159
wst04-VHDL20_DWPG_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:31 344254
wst04-VHDL20_DWPG_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:49 388994
wst04-VHDL20_DWPG_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:31:26 350661
wst04-VHDL20_DWPG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:27 242486
wst04-VHDL20_DWPG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:31 350070
wst04-VHDL20_DWPG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:41 394772
wst04-VHDL20_DWPG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:31:34 345520
wst04-VHDL20_DWPH_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:23 244317
wst04-VHDL20_DWPH_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:31 244172
wst04-VHDL20_DWPH_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:41 244285
wst04-VHDL20_DWPH_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:31:26 242377
wst04-VHDL20_DWPH_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:21 241182
wst04-VHDL20_DWPH_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:31 241732
wst04-VHDL20_DWPH_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:41 241902
wst04-VHDL20_DWPH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:31:24 239682
wst04-VHDL20_DWSG_090200-2607090200-omedes--0.pdf 09-Jul-2026 02:30:13 352238
wst04-VHDL20_DWSG_090400-2607090400-omedes--0.pdf 09-Jul-2026 05:00:11 352380
wst04-VHDL20_DWSG_090800-2607090800-omedes--0.pdf 09-Jul-2026 08:30:17 353093
wst04-VHDL20_DWSG_091800-2607091800-omedes--0.pdf 09-Jul-2026 18:30:17 344058
wst04-VHDL20_DWSG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 343470
wst04-VHDL20_DWSG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 343812
wst04-VHDL20_DWSG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 344066
wst04-VHDL20_DWSG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:13 341220