Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Dec-2025 12:16:44 2505
FPDL13_DWMZ_040600 04-Dec-2025 14:50:46 5124
SXDL31_DWAV_030800 03-Dec-2025 08:04:09 9585
SXDL31_DWAV_031800 03-Dec-2025 15:16:15 8111
SXDL31_DWAV_040800 04-Dec-2025 07:45:24 6666
SXDL31_DWAV_041800 04-Dec-2025 17:32:31 4497
SXDL31_DWAV_LATEST 04-Dec-2025 17:32:31 4497
SXDL33_DWAV_030000 03-Dec-2025 10:20:23 8370
SXDL33_DWAV_040000 04-Dec-2025 14:46:47 8070
SXDL33_DWAV_LATEST 04-Dec-2025 14:46:47 8070
ber01-FWDL39_DWMS_031230-2512031230-dsw--0-ia5 03-Dec-2025 12:56:01 1072
ber01-FWDL39_DWMS_041230-2512041230-dsw--0-ia5 04-Dec-2025 12:29:21 2227
ber01-FWDL39_DWMS_041230_COR-2512041230-dsw--0-ia5 04-Dec-2025 13:12:31 2225
ber01-VHDL13_DWEH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:28:17 2951
ber01-VHDL13_DWEH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:28:16 2916
ber01-VHDL13_DWEH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:28:11 3268
ber01-VHDL13_DWEH_040400-2512040400-dsw--0-ia5 04-Dec-2025 05:58:11 3413
ber01-VHDL13_DWEH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:28:16 3206
ber01-VHDL13_DWEH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:16 2742
ber01-VHDL13_DWEH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3326
ber01-VHDL13_DWEH_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:12 3488
ber01-VHDL13_DWHG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2761
ber01-VHDL13_DWHG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:06 2412
ber01-VHDL13_DWHG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:08 3355
ber01-VHDL13_DWHG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:16 3215
ber01-VHDL13_DWHG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 3372
ber01-VHDL13_DWHG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 3436
ber01-VHDL13_DWHG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:07 3772
ber01-VHDL13_DWHG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3671
ber01-VHDL13_DWHH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2137
ber01-VHDL13_DWHH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:06 2036
ber01-VHDL13_DWHH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:08 2904
ber01-VHDL13_DWHH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:16 2936
ber01-VHDL13_DWHH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 2935
ber01-VHDL13_DWHH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2545
ber01-VHDL13_DWHH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:07 3124
ber01-VHDL13_DWHH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3124
ber01-VHDL13_DWLG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2846
ber01-VHDL13_DWLG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2590
ber01-VHDL13_DWLG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 3622
ber01-VHDL13_DWLG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 3485
ber01-VHDL13_DWLG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 3528
ber01-VHDL13_DWLG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 3069
ber01-VHDL13_DWLG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2923
ber01-VHDL13_DWLG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2727
ber01-VHDL13_DWLH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2221
ber01-VHDL13_DWLH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 1838
ber01-VHDL13_DWLH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2326
ber01-VHDL13_DWLH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2234
ber01-VHDL13_DWLH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 2234
ber01-VHDL13_DWLH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2227
ber01-VHDL13_DWLH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2727
ber01-VHDL13_DWLH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2737
ber01-VHDL13_DWLI_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2677
ber01-VHDL13_DWLI_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2414
ber01-VHDL13_DWLI_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 3389
ber01-VHDL13_DWLI_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 3276
ber01-VHDL13_DWLI_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 3272
ber01-VHDL13_DWLI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 2654
ber01-VHDL13_DWLI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2743
ber01-VHDL13_DWLI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2755
ber01-VHDL13_DWMG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:04 2340
ber01-VHDL13_DWMG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2062
ber01-VHDL13_DWMG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2859
ber01-VHDL13_DWMG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2860
ber01-VHDL13_DWMG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 3050
ber01-VHDL13_DWMG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2685
ber01-VHDL13_DWMG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2773
ber01-VHDL13_DWMG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2715
ber01-VHDL13_DWMO_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:04 2453
ber01-VHDL13_DWMO_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2156
ber01-VHDL13_DWMO_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2944
ber01-VHDL13_DWMO_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2946
ber01-VHDL13_DWMO_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 3078
ber01-VHDL13_DWMO_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2792
ber01-VHDL13_DWMO_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2935
ber01-VHDL13_DWMO_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2902
ber01-VHDL13_DWMP_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:04 2378
ber01-VHDL13_DWMP_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2104
ber01-VHDL13_DWMP_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2970
ber01-VHDL13_DWMP_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2981
ber01-VHDL13_DWMP_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 3162
ber01-VHDL13_DWMP_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 2848
ber01-VHDL13_DWMP_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 3050
ber01-VHDL13_DWMP_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 3023
ber01-VHDL13_DWOG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:04 4896
ber01-VHDL13_DWOG_030800_COR-2512030800-dsw--0-ia5 03-Dec-2025 13:37:21 4746
ber01-VHDL13_DWOG_031700-2512031700-dsw--0-ia5 03-Dec-2025 19:00:02 5134
ber01-VHDL13_DWOG_040300-2512040300-dsw--0-ia5 04-Dec-2025 04:00:07 5528
ber01-VHDL13_DWOG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 5168
ber01-VHDL13_DWOG_041700-2512041700-dsw--0-ia5 04-Dec-2025 19:00:02 4227
ber01-VHDL13_DWOG_050300-2512050300-dsw--0-ia5 05-Dec-2025 04:00:01 4424
ber01-VHDL13_DWOH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:28:17 2881
ber01-VHDL13_DWOH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:28:16 2875
ber01-VHDL13_DWOH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:28:11 3427
ber01-VHDL13_DWOH_040400-2512040400-dsw--0-ia5 04-Dec-2025 05:58:17 3481
ber01-VHDL13_DWOH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:28:16 3107
ber01-VHDL13_DWOH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:16 2806
ber01-VHDL13_DWOH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3287
ber01-VHDL13_DWOH_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:16 3349
ber01-VHDL13_DWOI_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:28:11 2744
ber01-VHDL13_DWOI_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:28:12 2828
ber01-VHDL13_DWOI_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:28:11 3052
ber01-VHDL13_DWOI_040400-2512040400-dsw--0-ia5 04-Dec-2025 05:58:17 3197
ber01-VHDL13_DWOI_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:28:12 2967
ber01-VHDL13_DWOI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:28:12 2532
ber01-VHDL13_DWOI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:28:13 3013
ber01-VHDL13_DWOI_050400-2512050400-dsw--0-ia5 05-Dec-2025 05:58:16 2858
ber01-VHDL13_DWON_030630-2512030630-dsw--0-ia5 03-Dec-2025 06:30:53 4174
ber01-VHDL13_DWON_030729-2512030729-dsw--0-ia5 03-Dec-2025 07:29:08 4782
ber01-VHDL13_DWON_031138-2512031138-dsw--0-ia5 03-Dec-2025 11:38:53 4782
ber01-VHDL13_DWON_031538-2512031538-dsw--0-ia5 03-Dec-2025 15:38:16 4125
ber01-VHDL13_DWON_031812-2512031812-dsw--0-ia5 03-Dec-2025 18:12:32 4143
ber01-VHDL13_DWON_031914-2512031914-dsw--0-ia5 03-Dec-2025 19:14:06 4109
ber01-VHDL13_DWON_032245-2512032245-dsw--0-ia5 03-Dec-2025 22:45:46 4131
ber01-VHDL13_DWON_040031-2512040031-dsw--0-ia5 04-Dec-2025 00:31:57 4570
ber01-VHDL13_DWON_040154-2512040154-dsw--0-ia5 04-Dec-2025 01:54:37 4536
ber01-VHDL13_DWON_040342-2512040342-dsw--0-ia5 04-Dec-2025 03:42:42 4521
ber01-VHDL13_DWON_040629-2512040629-dsw--0-ia5 04-Dec-2025 06:29:37 4476
ber01-VHDL13_DWON_040646-2512040646-dsw--0-ia5 04-Dec-2025 06:46:51 4632
ber01-VHDL13_DWON_040828-2512040828-dsw--0-ia5 04-Dec-2025 08:28:47 4566
ber01-VHDL13_DWON_041114-2512041114-dsw--0-ia5 04-Dec-2025 11:14:52 4566
ber01-VHDL13_DWON_041535-2512041535-dsw--0-ia5 04-Dec-2025 15:35:48 3779
ber01-VHDL13_DWON_041734-2512041734-dsw--0-ia5 04-Dec-2025 17:35:00 3774
ber01-VHDL13_DWON_042159-2512042159-dsw--0-ia5 04-Dec-2025 21:59:37 3774
ber01-VHDL13_DWON_042347-2512042347-dsw--0-ia5 04-Dec-2025 23:47:37 3842
ber01-VHDL13_DWON_050127-2512050127-dsw--0-ia5 05-Dec-2025 01:27:51 3842
ber01-VHDL13_DWON_050435-2512050435-dsw--0-ia5 05-Dec-2025 04:35:53 3842
ber01-VHDL13_DWON_050628-2512050628-dsw--0-ia5 05-Dec-2025 06:29:01 3369
ber01-VHDL13_DWPG_030400_COR-2512030400-dsw--0-ia5 03-Dec-2025 07:01:36 2631
ber01-VHDL13_DWPG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2354
ber01-VHDL13_DWPG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2012
ber01-VHDL13_DWPG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2353
ber01-VHDL13_DWPG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2180
ber01-VHDL13_DWPG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 2179
ber01-VHDL13_DWPG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 1979
ber01-VHDL13_DWPG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2229
ber01-VHDL13_DWPG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2437
ber01-VHDL13_DWPH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:07 2357
ber01-VHDL13_DWPH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 2054
ber01-VHDL13_DWPH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 2288
ber01-VHDL13_DWPH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:01 2094
ber01-VHDL13_DWPH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:02 2094
ber01-VHDL13_DWPH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:06 1810
ber01-VHDL13_DWPH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 2085
ber01-VHDL13_DWPH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:02 2191
ber01-VHDL13_DWSG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:30:04 3108
ber01-VHDL13_DWSG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:30:02 3329
ber01-VHDL13_DWSG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:30:02 3631
ber01-VHDL13_DWSG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 3631
ber01-VHDL13_DWSG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:30:08 3073
ber01-VHDL13_DWSG_040800_COR-2512040800-dsw--0-ia5 04-Dec-2025 12:46:01 3234
ber01-VHDL13_DWSG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:30:02 3381
ber01-VHDL13_DWSG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:30:01 3818
ber01-VHDL13_DWSG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 4426
ber01-VHDL17_DWOG_031200-2512031200-dsw--0-ia5 03-Dec-2025 11:51:02 3380
ber01-VHDL17_DWOG_041200-2512041200-dsw--0-ia5 04-Dec-2025 12:55:06 3081
swis2-VHDL20_DWEG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:07 3694
swis2-VHDL20_DWEG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 3413
swis2-VHDL20_DWEG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3860
swis2-VHDL20_DWEG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3934
swis2-VHDL20_DWEG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:06 3923
swis2-VHDL20_DWEG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3257
swis2-VHDL20_DWEG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3666
swis2-VHDL20_DWEG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3815
swis2-VHDL20_DWEH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:07 3622
swis2-VHDL20_DWEH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 3348
swis2-VHDL20_DWEH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3655
swis2-VHDL20_DWEH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3872
swis2-VHDL20_DWEH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:06 3965
swis2-VHDL20_DWEH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3233
swis2-VHDL20_DWEH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3767
swis2-VHDL20_DWEH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3885
swis2-VHDL20_DWEI_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:07 3469
swis2-VHDL20_DWEI_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 3269
swis2-VHDL20_DWEI_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3421
swis2-VHDL20_DWEI_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3683
swis2-VHDL20_DWEI_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:06 3755
swis2-VHDL20_DWEI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 2978
swis2-VHDL20_DWEI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3306
swis2-VHDL20_DWEI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:06 3212
swis2-VHDL20_DWHG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:03 3392
swis2-VHDL20_DWHG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 2595
swis2-VHDL20_DWHG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 3541
swis2-VHDL20_DWHG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:16 3398
swis2-VHDL20_DWHG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 4170
swis2-VHDL20_DWHG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3619
swis2-VHDL20_DWHG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3958
swis2-VHDL20_DWHG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3854
swis2-VHDL20_DWHH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:03 2743
swis2-VHDL20_DWHH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 2222
swis2-VHDL20_DWHH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 3090
swis2-VHDL20_DWHH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:16 3122
swis2-VHDL20_DWHH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3541
swis2-VHDL20_DWHH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 2731
swis2-VHDL20_DWHH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3310
swis2-VHDL20_DWHH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:06 3310
swis2-VHDL20_DWLG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:05 3526
swis2-VHDL20_DWLG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 3034
swis2-VHDL20_DWLG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 4066
swis2-VHDL20_DWLG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 4102
swis2-VHDL20_DWLG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 4351
swis2-VHDL20_DWLG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 3686
swis2-VHDL20_DWLG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3455
swis2-VHDL20_DWLG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3112
swis2-VHDL20_DWLH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:05 2809
swis2-VHDL20_DWLH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2233
swis2-VHDL20_DWLH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 2724
swis2-VHDL20_DWLH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 2633
swis2-VHDL20_DWLH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 2827
swis2-VHDL20_DWLH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2626
swis2-VHDL20_DWLH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3123
swis2-VHDL20_DWLH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3130
swis2-VHDL20_DWLI_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:05 3345
swis2-VHDL20_DWLI_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2810
swis2-VHDL20_DWLI_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 3788
swis2-VHDL20_DWLI_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 3775
swis2-VHDL20_DWLI_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3976
swis2-VHDL20_DWLI_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 3153
swis2-VHDL20_DWLI_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3215
swis2-VHDL20_DWLI_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 3142
swis2-VHDL20_DWMG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:03 3050
swis2-VHDL20_DWMG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2524
swis2-VHDL20_DWMG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3325
swis2-VHDL20_DWMG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3339
swis2-VHDL20_DWMG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3829
swis2-VHDL20_DWMG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3267
swis2-VHDL20_DWMG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3355
swis2-VHDL20_DWMG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3133
swis2-VHDL20_DWMO_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:03 3194
swis2-VHDL20_DWMO_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2625
swis2-VHDL20_DWMO_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3418
swis2-VHDL20_DWMO_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3392
swis2-VHDL20_DWMO_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3885
swis2-VHDL20_DWMO_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3378
swis2-VHDL20_DWMO_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 3522
swis2-VHDL20_DWMO_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3324
swis2-VHDL20_DWMP_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:03 3098
swis2-VHDL20_DWMP_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2565
swis2-VHDL20_DWMP_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:04 3441
swis2-VHDL20_DWMP_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 3460
swis2-VHDL20_DWMP_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3966
swis2-VHDL20_DWMP_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3416
swis2-VHDL20_DWMP_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:07 3634
swis2-VHDL20_DWMP_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 3440
swis2-VHDL20_DWPG_030400_COR-2512030400-dsw--0-ia5 03-Dec-2025 06:50:56 3017
swis2-VHDL20_DWPG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:05 2869
swis2-VHDL20_DWPG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2527
swis2-VHDL20_DWPG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 2738
swis2-VHDL20_DWPG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 2526
swis2-VHDL20_DWPG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 2699
swis2-VHDL20_DWPG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2499
swis2-VHDL20_DWPG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 2637
swis2-VHDL20_DWPG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 2811
swis2-VHDL20_DWPH_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:05 2872
swis2-VHDL20_DWPH_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:06 2569
swis2-VHDL20_DWPH_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 2672
swis2-VHDL20_DWPH_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:00:12 2442
swis2-VHDL20_DWPH_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 2614
swis2-VHDL20_DWPH_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:06 2330
swis2-VHDL20_DWPH_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 2413
swis2-VHDL20_DWPH_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:00:12 2520
swis2-VHDL20_DWSG_030800-2512030800-dsw--0-ia5 03-Dec-2025 09:45:07 3813
swis2-VHDL20_DWSG_031300-2512031300-dsw--0-ia5 03-Dec-2025 14:45:06 3585
swis2-VHDL20_DWSG_031800-2512031800-dsw--0-ia5 03-Dec-2025 19:45:02 3847
swis2-VHDL20_DWSG_040200-2512040200-dsw--0-ia5 04-Dec-2025 03:45:06 4073
swis2-VHDL20_DWSG_040400-2512040400-dsw--0-ia5 04-Dec-2025 06:15:02 4099
swis2-VHDL20_DWSG_040800-2512040800-dsw--0-ia5 04-Dec-2025 09:45:03 3943
swis2-VHDL20_DWSG_040800_COR-2512040800-dsw--0-ia5 04-Dec-2025 12:46:01 3465
swis2-VHDL20_DWSG_041300-2512041300-dsw--0-ia5 04-Dec-2025 14:45:05 4493
swis2-VHDL20_DWSG_041800-2512041800-dsw--0-ia5 04-Dec-2025 19:45:02 3791
swis2-VHDL20_DWSG_050200-2512050200-dsw--0-ia5 05-Dec-2025 03:45:05 4400
swis2-VHDL20_DWSG_050400-2512050400-dsw--0-ia5 05-Dec-2025 06:15:01 4917
wst04-VHDL20_DWEG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:21 227558
wst04-VHDL20_DWEG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:16 226166
wst04-VHDL20_DWEG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:16 227141
wst04-VHDL20_DWEG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:23 226420
wst04-VHDL20_DWEG_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:26 234346
wst04-VHDL20_DWEG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 232484
wst04-VHDL20_DWEG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 235238
wst04-VHDL20_DWEG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:26 234856
wst04-VHDL20_DWEH_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:26 230172
wst04-VHDL20_DWEH_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:16 228642
wst04-VHDL20_DWEH_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:16 229557
wst04-VHDL20_DWEH_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:23 229204
wst04-VHDL20_DWEH_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:22 232789
wst04-VHDL20_DWEH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 231356
wst04-VHDL20_DWEH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 233571
wst04-VHDL20_DWEH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:20 233580
wst04-VHDL20_DWEI_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:26 320294
wst04-VHDL20_DWEI_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:16 319439
wst04-VHDL20_DWEI_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:16 319938
wst04-VHDL20_DWEI_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:23 319994
wst04-VHDL20_DWEI_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:26 326267
wst04-VHDL20_DWEI_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:18 325238
wst04-VHDL20_DWEI_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 326329
wst04-VHDL20_DWEI_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:26 326179
wst04-VHDL20_DWHG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:21 311386
wst04-VHDL20_DWHG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:16 309657
wst04-VHDL20_DWHG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:12 310543
wst04-VHDL20_DWHG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:12 310634
wst04-VHDL20_DWHG_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:22 318345
wst04-VHDL20_DWHG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:18 316659
wst04-VHDL20_DWHG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 317700
wst04-VHDL20_DWHG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:12 317724
wst04-VHDL20_DWHH_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:21 297509
wst04-VHDL20_DWHH_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:22 296732
wst04-VHDL20_DWHH_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:12 297489
wst04-VHDL20_DWHH_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:12 297619
wst04-VHDL20_DWHH_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:16 306435
wst04-VHDL20_DWHH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 305219
wst04-VHDL20_DWHH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 306040
wst04-VHDL20_DWHH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:12 306043
wst04-VHDL20_DWLG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:32 308070
wst04-VHDL20_DWLG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:27 306203
wst04-VHDL20_DWLG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:26 307807
wst04-VHDL20_DWLG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:42 307707
wst04-VHDL20_DWLG_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:32 312171
wst04-VHDL20_DWLG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 311105
wst04-VHDL20_DWLG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 311814
wst04-VHDL20_DWLG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 310983
wst04-VHDL20_DWLH_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:32 311491
wst04-VHDL20_DWLH_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:22 310171
wst04-VHDL20_DWLH_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:22 310803
wst04-VHDL20_DWLH_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:42 310934
wst04-VHDL20_DWLH_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:32 317161
wst04-VHDL20_DWLH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 316453
wst04-VHDL20_DWLH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 317876
wst04-VHDL20_DWLH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 317248
wst04-VHDL20_DWLI_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:32 307816
wst04-VHDL20_DWLI_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:22 306873
wst04-VHDL20_DWLI_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:26 308088
wst04-VHDL20_DWLI_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:42 307959
wst04-VHDL20_DWLI_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:32 308917
wst04-VHDL20_DWLI_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:26 307584
wst04-VHDL20_DWLI_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:26 308023
wst04-VHDL20_DWLI_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:41 307828
wst04-VHDL20_DWMG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:21 513686
wst04-VHDL20_DWMG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:12 512693
wst04-VHDL20_DWMG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:22 514199
wst04-VHDL20_DWMG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:17 513871
wst04-VHDL20_DWMG_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:16 528239
wst04-VHDL20_DWMG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 527090
wst04-VHDL20_DWMG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 527799
wst04-VHDL20_DWMG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:16 528198
wst04-VHDL20_DWMO_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:15 410311
wst04-VHDL20_DWMO_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:12 408787
wst04-VHDL20_DWMO_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:16 411273
wst04-VHDL20_DWMO_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:17 411530
wst04-VHDL20_DWMO_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:12 418776
wst04-VHDL20_DWMO_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 417951
wst04-VHDL20_DWMO_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:16 418795
wst04-VHDL20_DWMO_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:22 419358
wst04-VHDL20_DWMP_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:21 536662
wst04-VHDL20_DWMP_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:16 535321
wst04-VHDL20_DWMP_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:22 535908
wst04-VHDL20_DWMP_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:21 536834
wst04-VHDL20_DWMP_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:16 550702
wst04-VHDL20_DWMP_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:16 549327
wst04-VHDL20_DWMP_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 549206
wst04-VHDL20_DWMP_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:22 550625
wst04-VHDL20_DWPG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:32 356997
wst04-VHDL20_DWPG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:27 311138
wst04-VHDL20_DWPG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:26 311768
wst04-VHDL20_DWPG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:32 311671
wst04-VHDL20_DWPG_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:32 364743
wst04-VHDL20_DWPG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:26 319859
wst04-VHDL20_DWPG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 319997
wst04-VHDL20_DWPG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:31 320066
wst04-VHDL20_DWPH_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:26 266131
wst04-VHDL20_DWPH_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:22 264861
wst04-VHDL20_DWPH_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:22 220656
wst04-VHDL20_DWPH_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:00:32 220591
wst04-VHDL20_DWPH_040800-2512040800-omedes--0.pdf 04-Dec-2025 09:45:26 269929
wst04-VHDL20_DWPH_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:22 269434
wst04-VHDL20_DWPH_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:22 224573
wst04-VHDL20_DWPH_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:00:31 224712
wst04-VHDL20_DWSG_030800-2512030800-omedes--0.pdf 03-Dec-2025 09:45:15 333610
wst04-VHDL20_DWSG_031300-2512031300-omedes--0.pdf 03-Dec-2025 14:45:15 333808
wst04-VHDL20_DWSG_031800-2512031800-omedes--0.pdf 03-Dec-2025 19:45:12 333314
wst04-VHDL20_DWSG_040200-2512040200-omedes--0.pdf 04-Dec-2025 03:45:12 333028
wst04-VHDL20_DWSG_040400-2512040400-omedes--0.pdf 04-Dec-2025 06:15:17 333045
wst04-VHDL20_DWSG_040800-2512040800-omedes--0.pdf 04-Dec-2025 12:46:07 338557
wst04-VHDL20_DWSG_041300-2512041300-omedes--0.pdf 04-Dec-2025 14:45:11 339214
wst04-VHDL20_DWSG_041800-2512041800-omedes--0.pdf 04-Dec-2025 19:45:12 338181
wst04-VHDL20_DWSG_050200-2512050200-omedes--0.pdf 05-Dec-2025 03:45:12 339311
wst04-VHDL20_DWSG_050400-2512050400-omedes--0.pdf 05-Dec-2025 06:15:16 339718