Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Dec-2025 12:51:05 4781
FPDL13_DWMZ_280600 28-Dec-2025 13:16:29 5091
SXDL31_DWAV_271800 27-Dec-2025 18:12:59 6272
SXDL31_DWAV_280800 28-Dec-2025 10:13:55 12583
SXDL31_DWAV_281800 28-Dec-2025 17:50:45 7046
SXDL31_DWAV_290800 29-Dec-2025 09:23:38 16595
SXDL31_DWAV_LATEST 29-Dec-2025 09:23:38 16595
SXDL33_DWAV_280000 28-Dec-2025 11:34:35 26819
SXDL33_DWAV_LATEST 28-Dec-2025 11:34:35 26819
ber01-FWDL39_DWMS_271230-2512271230-dsw--0-ia5 27-Dec-2025 12:40:52 1529
ber01-FWDL39_DWMS_271230_COR-2512271230-dsw--0-ia5 27-Dec-2025 12:46:11 1533
ber01-FWDL39_DWMS_281230-2512281230-dsw--0-ia5 28-Dec-2025 12:45:21 1942
ber01-VHDL13_DWEH_270800_COR-2512270800-dsw--0-ia5 27-Dec-2025 13:59:32 3608
ber01-VHDL13_DWEH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:17 3394
ber01-VHDL13_DWEH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:28:12 3789
ber01-VHDL13_DWEH_280400-2512280400-dsw--0-ia5 28-Dec-2025 05:58:12 3738
ber01-VHDL13_DWEH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:28:17 4097
ber01-VHDL13_DWEH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:17 4135
ber01-VHDL13_DWEH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 4316
ber01-VHDL13_DWEH_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:17 4181
ber01-VHDL13_DWEH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:15 4181
ber01-VHDL13_DWHG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:06 3517
ber01-VHDL13_DWHG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:09 3930
ber01-VHDL13_DWHG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:08 3973
ber01-VHDL13_DWHG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:07 4062
ber01-VHDL13_DWHG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3473
ber01-VHDL13_DWHG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3870
ber01-VHDL13_DWHG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 3870
ber01-VHDL13_DWHG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:10 3855
ber01-VHDL13_DWHH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:06 3337
ber01-VHDL13_DWHH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:09 3604
ber01-VHDL13_DWHH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:08 3598
ber01-VHDL13_DWHH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:07 3558
ber01-VHDL13_DWHH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3290
ber01-VHDL13_DWHH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3393
ber01-VHDL13_DWHH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:07 3393
ber01-VHDL13_DWHH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:10 3222
ber01-VHDL13_DWLG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2139
ber01-VHDL13_DWLG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 2245
ber01-VHDL13_DWLG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 2514
ber01-VHDL13_DWLG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3471
ber01-VHDL13_DWLG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3285
ber01-VHDL13_DWLG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3974
ber01-VHDL13_DWLG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3685
ber01-VHDL13_DWLG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3311
ber01-VHDL13_DWLH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2000
ber01-VHDL13_DWLH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 2092
ber01-VHDL13_DWLH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 2290
ber01-VHDL13_DWLH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 2990
ber01-VHDL13_DWLH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2954
ber01-VHDL13_DWLH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3431
ber01-VHDL13_DWLH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3141
ber01-VHDL13_DWLH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3011
ber01-VHDL13_DWLI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1904
ber01-VHDL13_DWLI_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 1932
ber01-VHDL13_DWLI_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 2141
ber01-VHDL13_DWLI_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 2924
ber01-VHDL13_DWLI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2618
ber01-VHDL13_DWLI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3129
ber01-VHDL13_DWLI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 2940
ber01-VHDL13_DWLI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 2679
ber01-VHDL13_DWMG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2919
ber01-VHDL13_DWMG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 3127
ber01-VHDL13_DWMG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 3114
ber01-VHDL13_DWMG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3573
ber01-VHDL13_DWMG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3081
ber01-VHDL13_DWMG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3574
ber01-VHDL13_DWMG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3768
ber01-VHDL13_DWMG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3800
ber01-VHDL13_DWMO_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2661
ber01-VHDL13_DWMO_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 2961
ber01-VHDL13_DWMO_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 2891
ber01-VHDL13_DWMO_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3217
ber01-VHDL13_DWMO_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3217
ber01-VHDL13_DWMO_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3423
ber01-VHDL13_DWMO_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3423
ber01-VHDL13_DWMO_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3423
ber01-VHDL13_DWMO_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 09:42:57 3556
ber01-VHDL13_DWMP_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 3045
ber01-VHDL13_DWMP_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 3376
ber01-VHDL13_DWMP_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 3387
ber01-VHDL13_DWMP_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3608
ber01-VHDL13_DWMP_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3093
ber01-VHDL13_DWMP_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3619
ber01-VHDL13_DWMP_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3619
ber01-VHDL13_DWMP_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3619
ber01-VHDL13_DWMP_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 09:43:11 3498
ber01-VHDL13_DWOG_271700-2512271700-dsw--0-ia5 27-Dec-2025 19:00:02 4361
ber01-VHDL13_DWOG_280300-2512280300-dsw--0-ia5 28-Dec-2025 04:00:01 6284
ber01-VHDL13_DWOG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:07 5830
ber01-VHDL13_DWOG_280800_COR-2512280800-dsw--0-ia5 28-Dec-2025 15:55:58 5555
ber01-VHDL13_DWOG_281700-2512281700-dsw--0-ia5 28-Dec-2025 19:00:01 5551
ber01-VHDL13_DWOG_281700_COR-2512281700-dsw--0-ia5 28-Dec-2025 19:35:27 5256
ber01-VHDL13_DWOG_290300-2512290300-dsw--0-ia5 29-Dec-2025 04:00:07 5820
ber01-VHDL13_DWOG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 5360
ber01-VHDL13_DWOH_270800_COR-2512270800-dsw--0-ia5 27-Dec-2025 18:22:27 3514
ber01-VHDL13_DWOH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:17 3506
ber01-VHDL13_DWOH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:28:12 3608
ber01-VHDL13_DWOH_280400-2512280400-dsw--0-ia5 28-Dec-2025 05:58:12 3897
ber01-VHDL13_DWOH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:28:17 3912
ber01-VHDL13_DWOH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:13 3842
ber01-VHDL13_DWOH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 4098
ber01-VHDL13_DWOH_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:12 4026
ber01-VHDL13_DWOH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:15 4026
ber01-VHDL13_DWOI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:11 2803
ber01-VHDL13_DWOI_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:28:12 3261
ber01-VHDL13_DWOI_280400-2512280400-dsw--0-ia5 28-Dec-2025 05:58:16 3118
ber01-VHDL13_DWOI_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:28:11 2846
ber01-VHDL13_DWOI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:13 3121
ber01-VHDL13_DWOI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 3585
ber01-VHDL13_DWOI_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:17 3661
ber01-VHDL13_DWOI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:12 3667
ber01-VHDL13_DWON_271557-2512271557-dsw--0-ia5 27-Dec-2025 15:57:22 4078
ber01-VHDL13_DWON_271824-2512271824-dsw--0-ia5 27-Dec-2025 18:24:41 4103
ber01-VHDL13_DWON_272003-2512272003-dsw--0-ia5 27-Dec-2025 20:03:41 4438
ber01-VHDL13_DWON_272215-2512272215-dsw--0-ia5 27-Dec-2025 22:15:36 4455
ber01-VHDL13_DWON_280005-2512280005-dsw--0-ia5 28-Dec-2025 00:05:07 5630
ber01-VHDL13_DWON_280155-2512280155-dsw--0-ia5 28-Dec-2025 01:55:36 5601
ber01-VHDL13_DWON_280340-2512280340-dsw--0-ia5 28-Dec-2025 03:40:42 5623
ber01-VHDL13_DWON_280629-2512280629-dsw--0-ia5 28-Dec-2025 06:29:21 4869
ber01-VHDL13_DWON_280657-2512280657-dsw--0-ia5 28-Dec-2025 06:57:47 4873
ber01-VHDL13_DWON_280859-2512280859-dsw--0-ia5 28-Dec-2025 08:59:41 4775
ber01-VHDL13_DWON_280950-2512280950-dsw--0-ia5 28-Dec-2025 09:50:57 4799
ber01-VHDL13_DWON_281555-2512281555-dsw--0-ia5 28-Dec-2025 15:55:31 4355
ber01-VHDL13_DWON_281904-2512281904-dsw--0-ia5 28-Dec-2025 19:04:44 4331
ber01-VHDL13_DWON_281934-2512281934-dsw--0-ia5 28-Dec-2025 19:34:46 4724
ber01-VHDL13_DWON_281935-2512281935-dsw--0-ia5 28-Dec-2025 19:35:41 4724
ber01-VHDL13_DWON_282034-2512282034-dsw--0-ia5 28-Dec-2025 20:34:29 4790
ber01-VHDL13_DWON_290017-2512290017-dsw--0-ia5 29-Dec-2025 00:17:11 4796
ber01-VHDL13_DWON_290355-2512290355-dsw--0-ia5 29-Dec-2025 03:55:27 4796
ber01-VHDL13_DWON_290630-2512290630-dsw--0-ia5 29-Dec-2025 06:30:11 4676
ber01-VHDL13_DWON_290642-2512290642-dsw--0-ia5 29-Dec-2025 06:42:51 4696
ber01-VHDL13_DWON_290759-2512290759-dsw--0-ia5 29-Dec-2025 07:59:13 5029
ber01-VHDL13_DWPG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1808
ber01-VHDL13_DWPG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 1813
ber01-VHDL13_DWPG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 1970
ber01-VHDL13_DWPG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 2661
ber01-VHDL13_DWPG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2585
ber01-VHDL13_DWPG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 2716
ber01-VHDL13_DWPG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 2674
ber01-VHDL13_DWPG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 2370
ber01-VHDL13_DWPH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1996
ber01-VHDL13_DWPH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 2520
ber01-VHDL13_DWPH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:01 2588
ber01-VHDL13_DWPH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3377
ber01-VHDL13_DWPH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3317
ber01-VHDL13_DWPH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3466
ber01-VHDL13_DWPH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3110
ber01-VHDL13_DWPH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3061
ber01-VHDL13_DWSG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 3103
ber01-VHDL13_DWSG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:30:01 3201
ber01-VHDL13_DWSG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:08 3309
ber01-VHDL13_DWSG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:30:03 3461
ber01-VHDL13_DWSG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3074
ber01-VHDL13_DWSG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3400
ber01-VHDL13_DWSG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 3325
ber01-VHDL13_DWSG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3326
ber01-VHDL17_DWOG_271200-2512271200-dsw--0-ia5 27-Dec-2025 11:56:26 3524
ber01-VHDL17_DWOG_281200-2512281200-dsw--0-ia5 28-Dec-2025 13:11:51 4163
swis2-VHDL20_DWEG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 4083
swis2-VHDL20_DWEG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 4133
swis2-VHDL20_DWEG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:06 4446
swis2-VHDL20_DWEG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:07 4927
swis2-VHDL20_DWEG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 4534
swis2-VHDL20_DWEG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 4733
swis2-VHDL20_DWEG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4525
swis2-VHDL20_DWEG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4735
swis2-VHDL20_DWEH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 4140
swis2-VHDL20_DWEH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 4419
swis2-VHDL20_DWEH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:07 4420
swis2-VHDL20_DWEH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:07 5256
swis2-VHDL20_DWEH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 4978
swis2-VHDL20_DWEH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 5086
swis2-VHDL20_DWEH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4714
swis2-VHDL20_DWEH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4687
swis2-VHDL20_DWEI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3444
swis2-VHDL20_DWEI_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 3842
swis2-VHDL20_DWEI_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:06 3539
swis2-VHDL20_DWEI_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:07 3653
swis2-VHDL20_DWEI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3568
swis2-VHDL20_DWEI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 3975
swis2-VHDL20_DWEI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:06 4201
swis2-VHDL20_DWEI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4431
swis2-VHDL20_DWHG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:06 3700
swis2-VHDL20_DWHG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 4116
swis2-VHDL20_DWHG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 4156
swis2-VHDL20_DWHG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4828
swis2-VHDL20_DWHG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3656
swis2-VHDL20_DWHG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4056
swis2-VHDL20_DWHG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 4053
swis2-VHDL20_DWHG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4752
swis2-VHDL20_DWHH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:06 3523
swis2-VHDL20_DWHH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 3790
swis2-VHDL20_DWHH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 3784
swis2-VHDL20_DWHH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4189
swis2-VHDL20_DWHH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3476
swis2-VHDL20_DWHH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3579
swis2-VHDL20_DWHH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:07 3579
swis2-VHDL20_DWHH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4032
swis2-VHDL20_DWLG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 2531
swis2-VHDL20_DWLG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 2640
swis2-VHDL20_DWLG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 2891
swis2-VHDL20_DWLG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4101
swis2-VHDL20_DWLG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3688
swis2-VHDL20_DWLG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4380
swis2-VHDL20_DWLG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 4142
swis2-VHDL20_DWLG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3967
swis2-VHDL20_DWLH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 2419
swis2-VHDL20_DWLH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 2514
swis2-VHDL20_DWLH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 2672
swis2-VHDL20_DWLH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 3625
swis2-VHDL20_DWLH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3364
swis2-VHDL20_DWLH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3844
swis2-VHDL20_DWLH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3565
swis2-VHDL20_DWLH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3638
swis2-VHDL20_DWLI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 2357
swis2-VHDL20_DWLI_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 2422
swis2-VHDL20_DWLI_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 2520
swis2-VHDL20_DWLI_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 3552
swis2-VHDL20_DWLI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3023
swis2-VHDL20_DWLI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3537
swis2-VHDL20_DWLI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3363
swis2-VHDL20_DWLI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3300
swis2-VHDL20_DWMG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3405
swis2-VHDL20_DWMG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 3464
swis2-VHDL20_DWMG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:01 3503
swis2-VHDL20_DWMG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4133
swis2-VHDL20_DWMG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3463
swis2-VHDL20_DWMG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4010
swis2-VHDL20_DWMG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4251
swis2-VHDL20_DWMG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4548
swis2-VHDL20_DWMO_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3151
swis2-VHDL20_DWMO_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 3356
swis2-VHDL20_DWMO_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:01 3284
swis2-VHDL20_DWMO_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 3785
swis2-VHDL20_DWMO_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3344
swis2-VHDL20_DWMO_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3817
swis2-VHDL20_DWMO_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 3827
swis2-VHDL20_DWMO_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4263
swis2-VHDL20_DWMP_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3460
swis2-VHDL20_DWMP_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 3770
swis2-VHDL20_DWMP_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:01 3776
swis2-VHDL20_DWMP_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4174
swis2-VHDL20_DWMP_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3467
swis2-VHDL20_DWMP_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4012
swis2-VHDL20_DWMP_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4089
swis2-VHDL20_DWMP_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4218
swis2-VHDL20_DWPG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 2379
swis2-VHDL20_DWPG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 2255
swis2-VHDL20_DWPG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 2327
swis2-VHDL20_DWPG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 3408
swis2-VHDL20_DWPG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3316
swis2-VHDL20_DWPG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3242
swis2-VHDL20_DWPG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3049
swis2-VHDL20_DWPG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 2949
swis2-VHDL20_DWPH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 2484
swis2-VHDL20_DWPH_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:02 2878
swis2-VHDL20_DWPH_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:00:12 2916
swis2-VHDL20_DWPH_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4113
swis2-VHDL20_DWPH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 4056
swis2-VHDL20_DWPH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4012
swis2-VHDL20_DWPH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3487
swis2-VHDL20_DWPH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3639
swis2-VHDL20_DWSG_271300-2512271300-dsw--0-ia5 27-Dec-2025 14:45:16 3788
swis2-VHDL20_DWSG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3514
swis2-VHDL20_DWSG_280200-2512280200-dsw--0-ia5 28-Dec-2025 03:45:06 3564
swis2-VHDL20_DWSG_280400-2512280400-dsw--0-ia5 28-Dec-2025 06:15:01 3682
swis2-VHDL20_DWSG_280800-2512280800-dsw--0-ia5 28-Dec-2025 09:45:01 4171
swis2-VHDL20_DWSG_281300-2512281300-dsw--0-ia5 28-Dec-2025 14:45:11 3906
swis2-VHDL20_DWSG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3484
swis2-VHDL20_DWSG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 3771
swis2-VHDL20_DWSG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 3842
swis2-VHDL20_DWSG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3848
wst04-VHDL20_DWEG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 223503
wst04-VHDL20_DWEG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:16 224152
wst04-VHDL20_DWEG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:21 224453
wst04-VHDL20_DWEG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:21 226522
wst04-VHDL20_DWEG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 224793
wst04-VHDL20_DWEG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 225738
wst04-VHDL20_DWEG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:27 225190
wst04-VHDL20_DWEG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:22 228288
wst04-VHDL20_DWEH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 221302
wst04-VHDL20_DWEH_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:12 222645
wst04-VHDL20_DWEH_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:27 223340
wst04-VHDL20_DWEH_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:21 224205
wst04-VHDL20_DWEH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 223647
wst04-VHDL20_DWEH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 224502
wst04-VHDL20_DWEH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:21 223972
wst04-VHDL20_DWEH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:22 225293
wst04-VHDL20_DWEI_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:18 300939
wst04-VHDL20_DWEI_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:16 301819
wst04-VHDL20_DWEI_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:27 302253
wst04-VHDL20_DWEI_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:27 306545
wst04-VHDL20_DWEI_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 305473
wst04-VHDL20_DWEI_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 306445
wst04-VHDL20_DWEI_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:27 306577
wst04-VHDL20_DWEI_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 307938
wst04-VHDL20_DWHG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 313036
wst04-VHDL20_DWHG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:12 313223
wst04-VHDL20_DWHG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:12 313255
wst04-VHDL20_DWHG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:17 300184
wst04-VHDL20_DWHG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 297752
wst04-VHDL20_DWHG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 298747
wst04-VHDL20_DWHG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:12 298707
wst04-VHDL20_DWHG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 313645
wst04-VHDL20_DWHH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:16 305857
wst04-VHDL20_DWHH_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:12 305623
wst04-VHDL20_DWHH_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:12 305577
wst04-VHDL20_DWHH_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:17 302401
wst04-VHDL20_DWHH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 300714
wst04-VHDL20_DWHH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 301475
wst04-VHDL20_DWHH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:12 301586
wst04-VHDL20_DWHH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 305042
wst04-VHDL20_DWLG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:20 300060
wst04-VHDL20_DWLG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:26 300271
wst04-VHDL20_DWLG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:41 300226
wst04-VHDL20_DWLG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:27 297569
wst04-VHDL20_DWLG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:26 297613
wst04-VHDL20_DWLG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 298740
wst04-VHDL20_DWLG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 297842
wst04-VHDL20_DWLG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 305877
wst04-VHDL20_DWLH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 303651
wst04-VHDL20_DWLH_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:22 303792
wst04-VHDL20_DWLH_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:41 303711
wst04-VHDL20_DWLH_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:31 294417
wst04-VHDL20_DWLH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 294264
wst04-VHDL20_DWLH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 295793
wst04-VHDL20_DWLH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 295049
wst04-VHDL20_DWLH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 300762
wst04-VHDL20_DWLI_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 292279
wst04-VHDL20_DWLI_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:22 292463
wst04-VHDL20_DWLI_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:41 292312
wst04-VHDL20_DWLI_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:31 291923
wst04-VHDL20_DWLI_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 291905
wst04-VHDL20_DWLI_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 292815
wst04-VHDL20_DWLI_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 292144
wst04-VHDL20_DWLI_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 298801
wst04-VHDL20_DWMG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:22 489560
wst04-VHDL20_DWMG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:16 490453
wst04-VHDL20_DWMG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:21 490343
wst04-VHDL20_DWMG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:13 493186
wst04-VHDL20_DWMG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 491780
wst04-VHDL20_DWMG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 493694
wst04-VHDL20_DWMG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 493732
wst04-VHDL20_DWMG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 499639
wst04-VHDL20_DWMO_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:16 396091
wst04-VHDL20_DWMO_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:22 397598
wst04-VHDL20_DWMO_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:17 398397
wst04-VHDL20_DWMO_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:13 393581
wst04-VHDL20_DWMO_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 393069
wst04-VHDL20_DWMO_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 394787
wst04-VHDL20_DWMO_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 395332
wst04-VHDL20_DWMO_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:15 401778
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wst04-VHDL20_DWMP_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:22 498294
wst04-VHDL20_DWMP_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:21 499435
wst04-VHDL20_DWMP_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:17 509341
wst04-VHDL20_DWMP_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 507919
wst04-VHDL20_DWMP_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 508331
wst04-VHDL20_DWMP_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 509555
wst04-VHDL20_DWMP_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 518559
wst04-VHDL20_DWPG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 307578
wst04-VHDL20_DWPG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:26 307297
wst04-VHDL20_DWPG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:31 307123
wst04-VHDL20_DWPG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:31 346974
wst04-VHDL20_DWPG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:26 302052
wst04-VHDL20_DWPG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:27 302189
wst04-VHDL20_DWPG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:31 301747
wst04-VHDL20_DWPG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 355809
wst04-VHDL20_DWPH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:20 268655
wst04-VHDL20_DWPH_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:22 224203
wst04-VHDL20_DWPH_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:00:31 223957
wst04-VHDL20_DWPH_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:27 270909
wst04-VHDL20_DWPH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 271505
wst04-VHDL20_DWPH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:27 226494
wst04-VHDL20_DWPH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:31 225088
wst04-VHDL20_DWPH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 272605
wst04-VHDL20_DWSG_271300-2512271300-omedes--0.pdf 27-Dec-2025 14:45:16 309483
wst04-VHDL20_DWSG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 308974
wst04-VHDL20_DWSG_280200-2512280200-omedes--0.pdf 28-Dec-2025 03:45:16 309648
wst04-VHDL20_DWSG_280400-2512280400-omedes--0.pdf 28-Dec-2025 06:15:17 309846
wst04-VHDL20_DWSG_280800-2512280800-omedes--0.pdf 28-Dec-2025 09:45:11 319794
wst04-VHDL20_DWSG_281300-2512281300-omedes--0.pdf 28-Dec-2025 14:45:11 319739
wst04-VHDL20_DWSG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 318651
wst04-VHDL20_DWSG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 319767
wst04-VHDL20_DWSG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:11 319912
wst04-VHDL20_DWSG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:15 315300