Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Aug-2026 12:38:44 4233
FPDL13_DWMZ_190600 19-Aug-2026 13:43:17 6147
SXDL31_DWAV_181800 18-Aug-2026 15:59:40 13449
SXDL31_DWAV_190800 19-Aug-2026 08:14:55 12306
SXDL31_DWAV_191800 19-Aug-2026 16:51:59 6146
SXDL31_DWAV_200800 20-Aug-2026 08:08:39 13598
SXDL31_DWAV_LATEST 20-Aug-2026 08:08:39 13598
SXDL33_DWAV_180000 18-Aug-2026 10:08:04 9321
SXDL33_DWAV_190000 19-Aug-2026 11:08:55 7445
SXDL33_DWAV_LATEST 19-Aug-2026 11:08:55 7445
ber01-FWDL39_DWMS_181200-2608181200-dsw--0-ia5 18-Aug-2026 11:23:23 2153
ber01-FWDL39_DWMS_191200-2608191200-dsw--0-ia5 19-Aug-2026 10:35:35 2604
ber01-VHDL13_DWEG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:28:18 3179
ber01-VHDL13_DWEG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:28:20 2709
ber01-VHDL13_DWEH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:28:18 2908
ber01-VHDL13_DWEH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:28:14 2899
ber01-VHDL13_DWEI_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:28:18 3221
ber01-VHDL13_DWEI_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:28:20 2736
ber01-VHDL13_DWHG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3334
ber01-VHDL13_DWHG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 3530
ber01-VHDL13_DWHH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3001
ber01-VHDL13_DWHH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 2986
ber01-VHDL13_DWLG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3587
ber01-VHDL13_DWLG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 2358
ber01-VHDL13_DWLH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3275
ber01-VHDL13_DWLH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 2725
ber01-VHDL13_DWLI_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3285
ber01-VHDL13_DWLI_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 2257
ber01-VHDL13_DWMO_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3888
ber01-VHDL13_DWMO_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 3840
ber01-VHDL13_DWMP_180800_COR-2608180800-dsw--0-ia5 18-Aug-2026 08:52:08 3780
ber01-VHDL13_DWMP_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3746
ber01-VHDL13_DWMP_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 4468
ber01-VHDL13_DWOG_181700-2608181700-dsw--0-ia5 18-Aug-2026 18:00:03 4929
ber01-VHDL13_DWOG_190300-2608190300-dsw--0-ia5 19-Aug-2026 03:00:25 5210
ber01-VHDL13_DWOG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 5224
ber01-VHDL13_DWOG_191700-2608191700-dsw--0-ia5 19-Aug-2026 18:00:08 4695
ber01-VHDL13_DWOG_200300-2608200300-dsw--0-ia5 20-Aug-2026 03:00:41 4980
ber01-VHDL13_DWOG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 4764
ber01-VHDL13_DWON_181454-2608181454-dsw--0-ia5 18-Aug-2026 14:55:20 4031
ber01-VHDL13_DWON_181638-2608181638-dsw--0-ia5 18-Aug-2026 16:38:30 3799
ber01-VHDL13_DWON_181653-2608181653-dsw--0-ia5 18-Aug-2026 16:53:58 3799
ber01-VHDL13_DWON_190013-2608190013-dsw--0-ia5 19-Aug-2026 00:13:24 4833
ber01-VHDL13_DWON_190053-2608190053-dsw--0-ia5 19-Aug-2026 00:53:14 4833
ber01-VHDL13_DWON_190247-2608190247-dsw--0-ia5 19-Aug-2026 02:47:49 4833
ber01-VHDL13_DWON_190529-2608190529-dsw--0-ia5 19-Aug-2026 05:29:59 4745
ber01-VHDL13_DWON_190613-2608190613-dsw--0-ia5 19-Aug-2026 06:13:18 4530
ber01-VHDL13_DWON_191512-2608191512-dsw--0-ia5 19-Aug-2026 15:12:13 4560
ber01-VHDL13_DWON_191517-2608191517-dsw--0-ia5 19-Aug-2026 15:17:52 4560
ber01-VHDL13_DWON_191720-2608191720-dsw--0-ia5 19-Aug-2026 17:20:15 3630
ber01-VHDL13_DWON_191950-2608191950-dsw--0-ia5 19-Aug-2026 19:50:23 3986
ber01-VHDL13_DWON_192214-2608192214-dsw--0-ia5 19-Aug-2026 22:15:04 4585
ber01-VHDL13_DWON_192314-2608192314-dsw--0-ia5 19-Aug-2026 23:14:49 4507
ber01-VHDL13_DWON_192356-2608192356-dsw--0-ia5 19-Aug-2026 23:56:44 4481
ber01-VHDL13_DWON_200136-2608200136-dsw--0-ia5 20-Aug-2026 01:36:47 4255
ber01-VHDL13_DWON_200258-2608200258-dsw--0-ia5 20-Aug-2026 02:59:06 4161
ber01-VHDL13_DWON_200525-2608200525-dsw--0-ia5 20-Aug-2026 05:25:59 4316
ber01-VHDL13_DWON_200608-2608200608-dsw--0-ia5 20-Aug-2026 06:08:34 4335
ber01-VHDL13_DWON_200803-2608200803-dsw--0-ia5 20-Aug-2026 08:03:24 4299
ber01-VHDL13_DWON_200827-2608200827-dsw--0-ia5 20-Aug-2026 08:27:24 4299
ber01-VHDL13_DWPG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 2526
ber01-VHDL13_DWPG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 2566
ber01-VHDL13_DWPH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 2855
ber01-VHDL13_DWPH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 2382
ber01-VHDL13_DWSG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 3632
ber01-VHDL13_DWSG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 3655
ber01-VHDL17_DWOG_181200-2608181200-dsw--0-ia5 18-Aug-2026 11:57:10 3410
ber01-VHDL17_DWOG_191200-2608191200-dsw--0-ia5 19-Aug-2026 12:31:39 3943
swis2-VHDL20_DWEG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1841
swis2-VHDL20_DWEG_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:05 1534
swis2-VHDL20_DWEG_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:01:19 1394
swis2-VHDL20_DWEG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 1676
swis2-VHDL20_DWEG_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 1874
swis2-VHDL20_DWEG_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 872
swis2-VHDL20_DWEG_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:01:19 1148
swis2-VHDL20_DWEG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 1368
swis2-VHDL20_DWEH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1575
swis2-VHDL20_DWEH_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:05 1216
swis2-VHDL20_DWEH_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:01:19 1288
swis2-VHDL20_DWEH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 1564
swis2-VHDL20_DWEH_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 1710
swis2-VHDL20_DWEH_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 1019
swis2-VHDL20_DWEH_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:01:19 1316
swis2-VHDL20_DWEH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 1531
swis2-VHDL20_DWEI_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1904
swis2-VHDL20_DWEI_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:05 1564
swis2-VHDL20_DWEI_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:01:19 1403
swis2-VHDL20_DWEI_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 1684
swis2-VHDL20_DWEI_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 1787
swis2-VHDL20_DWEI_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 935
swis2-VHDL20_DWEI_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:01:19 1197
swis2-VHDL20_DWEI_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 1428
swis2-VHDL20_DWHG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:46:00 1214
swis2-VHDL20_DWHG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:45:11 1339
swis2-VHDL20_DWHG_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:45:13 1268
swis2-VHDL20_DWHG_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1265
swis2-VHDL20_DWHG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:45:45 1239
swis2-VHDL20_DWHG_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:45:10 2036
swis2-VHDL20_DWHG_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:47:04 1366
swis2-VHDL20_DWHG_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:18 1381
swis2-VHDL20_DWHH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:46:00 1271
swis2-VHDL20_DWHH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:45:19 1393
swis2-VHDL20_DWHH_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:45:13 1197
swis2-VHDL20_DWHH_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1180
swis2-VHDL20_DWHH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:45:45 1217
swis2-VHDL20_DWHH_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:45:10 1590
swis2-VHDL20_DWHH_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:47:04 1303
swis2-VHDL20_DWHH_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:18 1299
swis2-VHDL20_DWLG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1281
swis2-VHDL20_DWLG_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:37 1194
swis2-VHDL20_DWLG_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1422
swis2-VHDL20_DWLG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:35 1698
swis2-VHDL20_DWLG_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:31:21 1634
swis2-VHDL20_DWLG_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:32 800
swis2-VHDL20_DWLG_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:14 847
swis2-VHDL20_DWLG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:31 971
swis2-VHDL20_DWLH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1036
swis2-VHDL20_DWLH_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:37 926
swis2-VHDL20_DWLH_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1180
swis2-VHDL20_DWLH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:35 1557
swis2-VHDL20_DWLH_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:31:21 1427
swis2-VHDL20_DWLH_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:32 1063
swis2-VHDL20_DWLH_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:14 1063
swis2-VHDL20_DWLH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:31 1187
swis2-VHDL20_DWLI_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1346
swis2-VHDL20_DWLI_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:37 1271
swis2-VHDL20_DWLI_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1320
swis2-VHDL20_DWLI_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:35 1646
swis2-VHDL20_DWLI_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:31:21 1575
swis2-VHDL20_DWLI_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:32 798
swis2-VHDL20_DWLI_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:14 852
swis2-VHDL20_DWLI_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:31 976
swis2-VHDL20_DWMO_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1789
swis2-VHDL20_DWMO_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:03 1746
swis2-VHDL20_DWMO_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:02 1791
swis2-VHDL20_DWMO_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 1949
swis2-VHDL20_DWMO_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 2256
swis2-VHDL20_DWMO_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 1864
swis2-VHDL20_DWMO_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:08 1742
swis2-VHDL20_DWMO_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:19 2040
swis2-VHDL20_DWMP_180800_COR-2608180800-dsw--0-ia5 18-Aug-2026 08:52:08 3560
swis2-VHDL20_DWMP_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1753
swis2-VHDL20_DWMP_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:03 1803
swis2-VHDL20_DWMP_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:02 1696
swis2-VHDL20_DWMP_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 2081
swis2-VHDL20_DWMP_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 2631
swis2-VHDL20_DWMP_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 2282
swis2-VHDL20_DWMP_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:08 2318
swis2-VHDL20_DWMP_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 2637
swis2-VHDL20_DWPG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 859
swis2-VHDL20_DWPG_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:37 770
swis2-VHDL20_DWPG_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 936
swis2-VHDL20_DWPG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:35 1281
swis2-VHDL20_DWPG_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:31:21 1280
swis2-VHDL20_DWPG_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:32 941
swis2-VHDL20_DWPG_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:14 970
swis2-VHDL20_DWPG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:31 1094
swis2-VHDL20_DWPH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1051
swis2-VHDL20_DWPH_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:37 970
swis2-VHDL20_DWPH_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1076
swis2-VHDL20_DWPH_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:35 1371
swis2-VHDL20_DWPH_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:31:21 1054
swis2-VHDL20_DWPH_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:32 955
swis2-VHDL20_DWPH_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:14 946
swis2-VHDL20_DWPH_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:31 1065
swis2-VHDL20_DWSG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1584
swis2-VHDL20_DWSG_190200-2608190200-dsw--0-ia5 19-Aug-2026 02:30:03 1518
swis2-VHDL20_DWSG_190400-2608190400-dsw--0-ia5 19-Aug-2026 05:00:18 1515
swis2-VHDL20_DWSG_190800-2608190800-dsw--0-ia5 19-Aug-2026 08:30:14 1893
swis2-VHDL20_DWSG_191800-2608191800-dsw--0-ia5 19-Aug-2026 18:30:16 2069
swis2-VHDL20_DWSG_200200-2608200200-dsw--0-ia5 20-Aug-2026 02:30:10 1594
swis2-VHDL20_DWSG_200400-2608200400-dsw--0-ia5 20-Aug-2026 05:00:18 1823
swis2-VHDL20_DWSG_200400_COR-2608200400-dsw--0-ia5 20-Aug-2026 06:34:21 1923
swis2-VHDL20_DWSG_200800-2608200800-dsw--0-ia5 20-Aug-2026 08:30:20 2058
wst04-VHDL20_DWEG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 251406
wst04-VHDL20_DWEG_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 250300
wst04-VHDL20_DWEG_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:14 250034
wst04-VHDL20_DWEG_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:14 251743
wst04-VHDL20_DWEG_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 248303
wst04-VHDL20_DWEG_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 244785
wst04-VHDL20_DWEG_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:14 245863
wst04-VHDL20_DWEG_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:20 246792
wst04-VHDL20_DWEH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 245946
wst04-VHDL20_DWEH_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 245262
wst04-VHDL20_DWEH_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:14 244888
wst04-VHDL20_DWEH_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:14 246119
wst04-VHDL20_DWEH_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 245494
wst04-VHDL20_DWEH_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 242507
wst04-VHDL20_DWEH_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:14 243880
wst04-VHDL20_DWEH_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:20 244822
wst04-VHDL20_DWEI_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 359910
wst04-VHDL20_DWEI_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 358575
wst04-VHDL20_DWEI_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:18 358160
wst04-VHDL20_DWEI_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:20 359914
wst04-VHDL20_DWEI_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 356976
wst04-VHDL20_DWEI_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 353560
wst04-VHDL20_DWEI_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:18 354548
wst04-VHDL20_DWEI_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:20 355696
wst04-VHDL20_DWHG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:46:00 352196
wst04-VHDL20_DWHG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:45:19 349712
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wst04-VHDL20_DWHG_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:45:45 350026
wst04-VHDL20_DWHG_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:45:24 346317
wst04-VHDL20_DWHG_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:47:04 343273
wst04-VHDL20_DWHG_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:18 343062
wst04-VHDL20_DWHH_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:46:00 341218
wst04-VHDL20_DWHH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:45:19 339020
wst04-VHDL20_DWHH_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:46:13 338811
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wst04-VHDL20_DWHH_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:45:45 338900
wst04-VHDL20_DWHH_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:45:24 336575
wst04-VHDL20_DWHH_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:47:04 335953
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wst04-VHDL20_DWLG_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:44 340669
wst04-VHDL20_DWLG_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:49 341702
wst04-VHDL20_DWLG_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:31:21 347635
wst04-VHDL20_DWLG_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:32 344621
wst04-VHDL20_DWLG_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:44 345348
wst04-VHDL20_DWLG_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:43 390651
wst04-VHDL20_DWLH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 345815
wst04-VHDL20_DWLH_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:37 345557
wst04-VHDL20_DWLH_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:44 345855
wst04-VHDL20_DWLH_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:43 346348
wst04-VHDL20_DWLH_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:31:21 348577
wst04-VHDL20_DWLH_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:32 347499
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wst04-VHDL20_DWLH_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:43 348406
wst04-VHDL20_DWLI_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 349788
wst04-VHDL20_DWLI_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:37 349192
wst04-VHDL20_DWLI_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:44 348581
wst04-VHDL20_DWLI_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:43 394434
wst04-VHDL20_DWLI_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:31:38 352228
wst04-VHDL20_DWLI_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:32 350153
wst04-VHDL20_DWLI_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:44 351341
wst04-VHDL20_DWLI_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:53 396200
wst04-VHDL20_DWMO_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 360130
wst04-VHDL20_DWMO_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 464622
wst04-VHDL20_DWMO_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:14 465291
wst04-VHDL20_DWMO_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:20 464949
wst04-VHDL20_DWMO_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 362217
wst04-VHDL20_DWMO_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 467512
wst04-VHDL20_DWMO_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:14 467636
wst04-VHDL20_DWMO_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:20 468360
wst04-VHDL20_DWMP_180800_COR-2608180800-omedes-..> 18-Aug-2026 08:52:19 570405
wst04-VHDL20_DWMP_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 477040
wst04-VHDL20_DWMP_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 586972
wst04-VHDL20_DWMP_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:18 587184
wst04-VHDL20_DWMP_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:35 477710
wst04-VHDL20_DWMP_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 470269
wst04-VHDL20_DWMP_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 576189
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wst04-VHDL20_DWMP_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:31 471031
wst04-VHDL20_DWPG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 342911
wst04-VHDL20_DWPG_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:37 239699
wst04-VHDL20_DWPG_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:34 343747
wst04-VHDL20_DWPG_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:43 389481
wst04-VHDL20_DWPG_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:31:21 339712
wst04-VHDL20_DWPG_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:32 238956
wst04-VHDL20_DWPG_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:34 337920
wst04-VHDL20_DWPG_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:43 383139
wst04-VHDL20_DWPH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 246403
wst04-VHDL20_DWPH_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:37 246168
wst04-VHDL20_DWPH_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:34 246536
wst04-VHDL20_DWPH_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:43 246875
wst04-VHDL20_DWPH_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:31:21 245816
wst04-VHDL20_DWPH_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:32 245088
wst04-VHDL20_DWPH_200400-2608200400-omedes--0.pdf 20-Aug-2026 05:00:34 244850
wst04-VHDL20_DWPH_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:43 245446
wst04-VHDL20_DWSG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 356976
wst04-VHDL20_DWSG_190200-2608190200-omedes--0.pdf 19-Aug-2026 02:30:20 356435
wst04-VHDL20_DWSG_190400-2608190400-omedes--0.pdf 19-Aug-2026 05:00:14 356449
wst04-VHDL20_DWSG_190800-2608190800-omedes--0.pdf 19-Aug-2026 08:30:20 357457
wst04-VHDL20_DWSG_191800-2608191800-omedes--0.pdf 19-Aug-2026 18:30:16 353273
wst04-VHDL20_DWSG_200200-2608200200-omedes--0.pdf 20-Aug-2026 02:30:28 350978
wst04-VHDL20_DWSG_200400-2608200400-omedes--0.pdf 20-Aug-2026 06:34:30 352545
wst04-VHDL20_DWSG_200800-2608200800-omedes--0.pdf 20-Aug-2026 08:30:20 352532