Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Feb-2025 15:25 3048
FPDL13_DWMZ_220600 22-Feb-2025 13:00 5624
SXDL31_DWAV_201800 20-Feb-2025 18:07 6067
SXDL31_DWAV_210800 21-Feb-2025 08:59 10570
SXDL31_DWAV_211800 21-Feb-2025 17:34 5513
SXDL31_DWAV_220800 22-Feb-2025 07:51 8443
SXDL31_DWAV_LATEST 22-Feb-2025 07:51 8443
SXDL33_DWAV_210000 21-Feb-2025 11:13 7544
SXDL33_DWAV_220000 22-Feb-2025 10:58 13530
SXDL33_DWAV_LATEST 22-Feb-2025 10:58 13530
ber01-FWDL39_DWMS_211230-2502211230-dsw--0-ia5 21-Feb-2025 12:56 1649
ber01-FWDL39_DWMS_221230-2502221230-dsw--0-ia5 22-Feb-2025 12:08 1740
ber01-FWDL39_DWMS_221230_COR-2502221230-dsw--0-ia5 22-Feb-2025 12:10 1745
ber01-VHDL13_DWEH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:28 2313
ber01-VHDL13_DWEH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:28 2581
ber01-VHDL13_DWEH_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:58 2595
ber01-VHDL13_DWEH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:28 2676
ber01-VHDL13_DWEH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:28 2676
ber01-VHDL13_DWEH_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2382
ber01-VHDL13_DWEH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:28 2271
ber01-VHDL13_DWEH_220400-2502220400-dsw--0-ia5 22-Feb-2025 05:58 2434
ber01-VHDL13_DWEH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:28 2398
ber01-VHDL13_DWHG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2799
ber01-VHDL13_DWHG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2682
ber01-VHDL13_DWHG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2706
ber01-VHDL13_DWHG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 3023
ber01-VHDL13_DWHG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2797
ber01-VHDL13_DWHG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2931
ber01-VHDL13_DWHG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2931
ber01-VHDL13_DWHG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 3030
ber01-VHDL13_DWHH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2865
ber01-VHDL13_DWHH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2595
ber01-VHDL13_DWHH_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2581
ber01-VHDL13_DWHH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2750
ber01-VHDL13_DWHH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2624
ber01-VHDL13_DWHH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2753
ber01-VHDL13_DWHH_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2753
ber01-VHDL13_DWHH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2758
ber01-VHDL13_DWLG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2647
ber01-VHDL13_DWLG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2714
ber01-VHDL13_DWLG_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:59 2662
ber01-VHDL13_DWLG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2465
ber01-VHDL13_DWLG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2105
ber01-VHDL13_DWLG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2336
ber01-VHDL13_DWLG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2165
ber01-VHDL13_DWLG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2543
ber01-VHDL13_DWLH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2209
ber01-VHDL13_DWLH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2069
ber01-VHDL13_DWLH_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:59 1812
ber01-VHDL13_DWLH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 1800
ber01-VHDL13_DWLH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 1747
ber01-VHDL13_DWLH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 1941
ber01-VHDL13_DWLH_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 1878
ber01-VHDL13_DWLH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 1971
ber01-VHDL13_DWLI_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2268
ber01-VHDL13_DWLI_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2119
ber01-VHDL13_DWLI_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:59 2040
ber01-VHDL13_DWLI_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 1698
ber01-VHDL13_DWLI_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 1591
ber01-VHDL13_DWLI_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 1869
ber01-VHDL13_DWLI_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 1772
ber01-VHDL13_DWLI_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 1806
ber01-VHDL13_DWMG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2964
ber01-VHDL13_DWMG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 3406
ber01-VHDL13_DWMG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3407
ber01-VHDL13_DWMG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2707
ber01-VHDL13_DWMG_210800_COR-2502210800-dsw--0-ia5 21-Feb-2025 13:58 3193
ber01-VHDL13_DWMG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2921
ber01-VHDL13_DWMG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 3167
ber01-VHDL13_DWMG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 3197
ber01-VHDL13_DWMG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 3203
ber01-VHDL13_DWMO_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2669
ber01-VHDL13_DWMO_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 3273
ber01-VHDL13_DWMO_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3273
ber01-VHDL13_DWMO_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 3008
ber01-VHDL13_DWMO_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2601
ber01-VHDL13_DWMO_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2885
ber01-VHDL13_DWMO_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2938
ber01-VHDL13_DWMO_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 3082
ber01-VHDL13_DWMP_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2678
ber01-VHDL13_DWMP_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 3157
ber01-VHDL13_DWMP_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3157
ber01-VHDL13_DWMP_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2895
ber01-VHDL13_DWMP_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2617
ber01-VHDL13_DWMP_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2984
ber01-VHDL13_DWMP_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 3014
ber01-VHDL13_DWMP_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 3160
ber01-VHDL13_DWOG_201700-2502201700-dsw--0-ia5 20-Feb-2025 19:00 3903
ber01-VHDL13_DWOG_210300-2502210300-dsw--0-ia5 21-Feb-2025 04:00 3945
ber01-VHDL13_DWOG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 3846
ber01-VHDL13_DWOG_211700-2502211700-dsw--0-ia5 21-Feb-2025 19:00 3309
ber01-VHDL13_DWOG_220300-2502220300-dsw--0-ia5 22-Feb-2025 04:00 3966
ber01-VHDL13_DWOG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 3841
ber01-VHDL13_DWOH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:28 2428
ber01-VHDL13_DWOH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:28 2462
ber01-VHDL13_DWOH_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:58 2466
ber01-VHDL13_DWOH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:28 2571
ber01-VHDL13_DWOH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:28 2565
ber01-VHDL13_DWOH_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2294
ber01-VHDL13_DWOH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:28 2369
ber01-VHDL13_DWOH_220400-2502220400-dsw--0-ia5 22-Feb-2025 05:58 2381
ber01-VHDL13_DWOH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:28 2467
ber01-VHDL13_DWOI_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:28 2457
ber01-VHDL13_DWOI_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:28 2720
ber01-VHDL13_DWOI_210400-2502210400-dsw--0-ia5 21-Feb-2025 05:58 2579
ber01-VHDL13_DWOI_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:28 2708
ber01-VHDL13_DWOI_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:28 2702
ber01-VHDL13_DWOI_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2395
ber01-VHDL13_DWOI_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:28 2478
ber01-VHDL13_DWOI_220400-2502220400-dsw--0-ia5 22-Feb-2025 05:58 2505
ber01-VHDL13_DWOI_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:28 2472
ber01-VHDL13_DWON_201546-2502201546-dsw--0-ia5 20-Feb-2025 15:46 3805
ber01-VHDL13_DWON_202036-2502202036-dsw--0-ia5 20-Feb-2025 20:36 3904
ber01-VHDL13_DWON_210013-2502210013-dsw--0-ia5 21-Feb-2025 00:13 3628
ber01-VHDL13_DWON_210355-2502210355-dsw--0-ia5 21-Feb-2025 03:55 3674
ber01-VHDL13_DWON_210628-2502210628-dsw--0-ia5 21-Feb-2025 06:28 3979
ber01-VHDL13_DWON_210724-2502210724-dsw--0-ia5 21-Feb-2025 07:24 3897
ber01-VHDL13_DWON_211157-2502211157-dsw--0-ia5 21-Feb-2025 11:57 3854
ber01-VHDL13_DWON_211601-2502211601-dsw--0-ia5 21-Feb-2025 16:01 3810
ber01-VHDL13_DWON_211744-2502211744-dsw--0-ia5 21-Feb-2025 17:44 3297
ber01-VHDL13_DWON_211757-2502211757-dsw--0-ia5 21-Feb-2025 17:57 3262
ber01-VHDL13_DWON_211916-2502211916-dsw--0-ia5 21-Feb-2025 19:16 3319
ber01-VHDL13_DWON_212217-2502212217-dsw--0-ia5 21-Feb-2025 22:17 3289
ber01-VHDL13_DWON_220004-2502220004-dsw--0-ia5 22-Feb-2025 00:04 3728
ber01-VHDL13_DWON_220151-2502220151-dsw--0-ia5 22-Feb-2025 01:51 3714
ber01-VHDL13_DWON_220346-2502220346-dsw--0-ia5 22-Feb-2025 03:46 3714
ber01-VHDL13_DWON_220559-2502220559-dsw--0-ia5 22-Feb-2025 05:59 3595
ber01-VHDL13_DWON_220729-2502220729-dsw--0-ia5 22-Feb-2025 07:29 3679
ber01-VHDL13_DWON_220833-2502220833-dsw--0-ia5 22-Feb-2025 08:33 3679
ber01-VHDL13_DWON_220932-2502220932-dsw--0-ia5 22-Feb-2025 09:32 3679
ber01-VHDL13_DWPG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2955
ber01-VHDL13_DWPG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2757
ber01-VHDL13_DWPG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3056
ber01-VHDL13_DWPG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2542
ber01-VHDL13_DWPG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2409
ber01-VHDL13_DWPG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2670
ber01-VHDL13_DWPG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2518
ber01-VHDL13_DWPG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2436
ber01-VHDL13_DWPH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 3089
ber01-VHDL13_DWPH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2861
ber01-VHDL13_DWPH_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2932
ber01-VHDL13_DWPH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2418
ber01-VHDL13_DWPH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2288
ber01-VHDL13_DWPH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2397
ber01-VHDL13_DWPH_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2402
ber01-VHDL13_DWPH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2333
ber01-VHDL13_DWSG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 2186
ber01-VHDL13_DWSG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:30 2429
ber01-VHDL13_DWSG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2631
ber01-VHDL13_DWSG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2559
ber01-VHDL13_DWSG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2544
ber01-VHDL13_DWSG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:30 2930
ber01-VHDL13_DWSG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2977
ber01-VHDL13_DWSG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2689
ber01-VHDL13_DWSN_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 1669
ber01-VHDL13_DWSN_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2116
ber01-VHDL13_DWSN_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 1811
ber01-VHDL13_DWSN_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 1930
ber01-VHDL13_DWSN_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 1975
ber01-VHDL13_DWSN_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 1968
ber01-VHDL13_DWSO_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 1961
ber01-VHDL13_DWSO_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2005
ber01-VHDL13_DWSO_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2055
ber01-VHDL13_DWSO_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2251
ber01-VHDL13_DWSO_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2407
ber01-VHDL13_DWSO_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 2416
ber01-VHDL13_DWSP_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:30 1918
ber01-VHDL13_DWSP_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2323
ber01-VHDL13_DWSP_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:30 2158
ber01-VHDL13_DWSP_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:30 2002
ber01-VHDL13_DWSP_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 1963
ber01-VHDL13_DWSP_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:30 1861
ber01-VHDL17_DWOG_211200-2502211200-dsw--0-ia5 21-Feb-2025 12:49 2402
ber01-VHDL17_DWOG_221200-2502221200-dsw--0-ia5 22-Feb-2025 12:10 2890
swis2-VHDL20_DWEG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 2920
swis2-VHDL20_DWEG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 2905
swis2-VHDL20_DWEG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:15 2789
swis2-VHDL20_DWEG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3049
swis2-VHDL20_DWEG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2619
swis2-VHDL20_DWEG_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2479
swis2-VHDL20_DWEG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 2646
swis2-VHDL20_DWEG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:15 2701
swis2-VHDL20_DWEG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 2863
swis2-VHDL20_DWEH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 2667
swis2-VHDL20_DWEH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 2902
swis2-VHDL20_DWEH_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:15 2927
swis2-VHDL20_DWEH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3176
swis2-VHDL20_DWEH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2732
swis2-VHDL20_DWEH_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2582
swis2-VHDL20_DWEH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 2592
swis2-VHDL20_DWEH_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:15 2766
swis2-VHDL20_DWEH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 2819
swis2-VHDL20_DWEI_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 2811
swis2-VHDL20_DWEI_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 3015
swis2-VHDL20_DWEI_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:15 2930
swis2-VHDL20_DWEI_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3230
swis2-VHDL20_DWEI_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2742
swis2-VHDL20_DWEI_211800_COR-2502211800-dsw--0-ia5 21-Feb-2025 19:36 2580
swis2-VHDL20_DWEI_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 2770
swis2-VHDL20_DWEI_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:15 2856
swis2-VHDL20_DWEI_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 2915
swis2-VHDL20_DWHG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 3153
swis2-VHDL20_DWHG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 3036
swis2-VHDL20_DWHG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3066
swis2-VHDL20_DWHG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3554
swis2-VHDL20_DWHG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 3151
swis2-VHDL20_DWHG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 3285
swis2-VHDL20_DWHG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 3294
swis2-VHDL20_DWHG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 3610
swis2-VHDL20_DWHH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 3227
swis2-VHDL20_DWHH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 2957
swis2-VHDL20_DWHH_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 2947
swis2-VHDL20_DWHH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3293
swis2-VHDL20_DWHH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2987
swis2-VHDL20_DWHH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 3116
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swis2-VHDL20_DWMP_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 3577
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swis2-VHDL20_DWPG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 3324
swis2-VHDL20_DWPG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3430
swis2-VHDL20_DWPG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3049
swis2-VHDL20_DWPG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2916
swis2-VHDL20_DWPG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 2999
swis2-VHDL20_DWPG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2844
swis2-VHDL20_DWPG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 2894
swis2-VHDL20_DWPH_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 3761
swis2-VHDL20_DWPH_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 3427
swis2-VHDL20_DWPH_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:00 3260
swis2-VHDL20_DWPH_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 2879
swis2-VHDL20_DWPH_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2749
swis2-VHDL20_DWPH_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 2725
swis2-VHDL20_DWPH_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:00 2732
swis2-VHDL20_DWPH_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 2793
swis2-VHDL20_DWSG_201800-2502201800-dsw--0-ia5 20-Feb-2025 19:45 2604
swis2-VHDL20_DWSG_210200-2502210200-dsw--0-ia5 21-Feb-2025 03:45 2920
swis2-VHDL20_DWSG_210400-2502210400-dsw--0-ia5 21-Feb-2025 06:15 2985
swis2-VHDL20_DWSG_210800-2502210800-dsw--0-ia5 21-Feb-2025 09:45 3059
swis2-VHDL20_DWSG_211800-2502211800-dsw--0-ia5 21-Feb-2025 19:45 2986
swis2-VHDL20_DWSG_220200-2502220200-dsw--0-ia5 22-Feb-2025 03:45 3339
swis2-VHDL20_DWSG_220400-2502220400-dsw--0-ia5 22-Feb-2025 06:15 3331
swis2-VHDL20_DWSG_220800-2502220800-dsw--0-ia5 22-Feb-2025 09:45 3243
wst04-VHDL20_DWEG_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 263927
wst04-VHDL20_DWEG_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 264259
wst04-VHDL20_DWEG_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 263154
wst04-VHDL20_DWEG_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 271223
wst04-VHDL20_DWEG_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 269364
wst04-VHDL20_DWEG_211800_COR-2502211800-omedes-..> 21-Feb-2025 19:36 268919
wst04-VHDL20_DWEG_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 270326
wst04-VHDL20_DWEG_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 269363
wst04-VHDL20_DWEG_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 266809
wst04-VHDL20_DWEH_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 262277
wst04-VHDL20_DWEH_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 262963
wst04-VHDL20_DWEH_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 262168
wst04-VHDL20_DWEH_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 260738
wst04-VHDL20_DWEH_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 259811
wst04-VHDL20_DWEH_211800_COR-2502211800-omedes-..> 21-Feb-2025 19:36 259332
wst04-VHDL20_DWEH_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 260244
wst04-VHDL20_DWEH_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 259826
wst04-VHDL20_DWEH_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 264019
wst04-VHDL20_DWEI_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 364339
wst04-VHDL20_DWEI_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 364538
wst04-VHDL20_DWEI_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 363601
wst04-VHDL20_DWEI_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 373358
wst04-VHDL20_DWEI_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 372986
wst04-VHDL20_DWEI_211800_COR-2502211800-omedes-..> 21-Feb-2025 19:36 372594
wst04-VHDL20_DWEI_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 373087
wst04-VHDL20_DWEI_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 372578
wst04-VHDL20_DWEI_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 369456
wst04-VHDL20_DWHG_201800-2502201800-oflxs888--0..> 20-Feb-2025 19:45 357136
wst04-VHDL20_DWHG_210200-2502210200-oflxs888--0..> 21-Feb-2025 03:45 356856
wst04-VHDL20_DWHG_210400-2502210400-oflxs888--0..> 21-Feb-2025 06:00 356922
wst04-VHDL20_DWHG_210800-2502210800-oflxs888--0..> 21-Feb-2025 09:45 362464
wst04-VHDL20_DWHG_211800-2502211800-oflxs888--0..> 21-Feb-2025 19:45 360738
wst04-VHDL20_DWHG_220200-2502220200-oflxs888--0..> 22-Feb-2025 03:45 361460
wst04-VHDL20_DWHG_220400-2502220400-oflxs888--0..> 22-Feb-2025 06:00 361622
wst04-VHDL20_DWHG_220800-2502220800-oflxs888--0..> 22-Feb-2025 09:45 361156
wst04-VHDL20_DWHH_201800-2502201800-oflxs888--0..> 20-Feb-2025 19:45 344242
wst04-VHDL20_DWHH_210200-2502210200-oflxs888--0..> 21-Feb-2025 03:45 343768
wst04-VHDL20_DWHH_210400-2502210400-oflxs888--0..> 21-Feb-2025 06:00 343779
wst04-VHDL20_DWHH_210800-2502210800-oflxs888--0..> 21-Feb-2025 09:45 345490
wst04-VHDL20_DWHH_211800-2502211800-oflxs888--0..> 21-Feb-2025 19:45 344555
wst04-VHDL20_DWHH_220200-2502220200-oflxs888--0..> 22-Feb-2025 03:45 345679
wst04-VHDL20_DWHH_220400-2502220400-oflxs888--0..> 22-Feb-2025 06:00 345859
wst04-VHDL20_DWHH_220800-2502220800-oflxs888--0..> 22-Feb-2025 09:45 342853
wst04-VHDL20_DWLG_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:40 339092
wst04-VHDL20_DWLG_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:40 340146
wst04-VHDL20_DWLG_210400-2502210400-omedes--0.pdf 21-Feb-2025 05:59 340147
wst04-VHDL20_DWLG_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:40 365010
wst04-VHDL20_DWLG_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:40 363905
wst04-VHDL20_DWLG_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:40 364307
wst04-VHDL20_DWLG_220400-2502220400-omedes--0.pdf 22-Feb-2025 05:59 363919
wst04-VHDL20_DWLG_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:40 355526
wst04-VHDL20_DWLH_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:40 343870
wst04-VHDL20_DWLH_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:40 342997
wst04-VHDL20_DWLH_210400-2502210400-omedes--0.pdf 21-Feb-2025 05:59 343118
wst04-VHDL20_DWLH_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:40 358153
wst04-VHDL20_DWLH_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:40 357572
wst04-VHDL20_DWLH_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:40 358438
wst04-VHDL20_DWLH_220400-2502220400-omedes--0.pdf 22-Feb-2025 05:59 358822
wst04-VHDL20_DWLH_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:40 363562
wst04-VHDL20_DWLI_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:40 351668
wst04-VHDL20_DWLI_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:40 351947
wst04-VHDL20_DWLI_210400-2502210400-omedes--0.pdf 21-Feb-2025 05:59 351481
wst04-VHDL20_DWLI_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:40 360505
wst04-VHDL20_DWLI_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:40 359901
wst04-VHDL20_DWLI_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:40 360331
wst04-VHDL20_DWLI_220400-2502220400-omedes--0.pdf 22-Feb-2025 05:59 360615
wst04-VHDL20_DWLI_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:40 355895
wst04-VHDL20_DWMG_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 545661
wst04-VHDL20_DWMG_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 546197
wst04-VHDL20_DWMG_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 546128
wst04-VHDL20_DWMG_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 565493
wst04-VHDL20_DWMG_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 564272
wst04-VHDL20_DWMG_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 565017
wst04-VHDL20_DWMG_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 565106
wst04-VHDL20_DWMG_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 567120
wst04-VHDL20_DWMO_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 449032
wst04-VHDL20_DWMO_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 493975
wst04-VHDL20_DWMO_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 494469
wst04-VHDL20_DWMO_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 463978
wst04-VHDL20_DWMO_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 462496
wst04-VHDL20_DWMO_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 508339
wst04-VHDL20_DWMO_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 508850
wst04-VHDL20_DWMO_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 507319
wst04-VHDL20_DWMP_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 546363
wst04-VHDL20_DWMP_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 545433
wst04-VHDL20_DWMP_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 546644
wst04-VHDL20_DWMP_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 563235
wst04-VHDL20_DWMP_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 561585
wst04-VHDL20_DWMP_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 562162
wst04-VHDL20_DWMP_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 562902
wst04-VHDL20_DWMP_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 570101
wst04-VHDL20_DWPG_201800-2502201800-oflxs892--0..> 20-Feb-2025 19:45 352669
wst04-VHDL20_DWPG_210200-2502210200-oflxs892--0..> 21-Feb-2025 03:45 352705
wst04-VHDL20_DWPG_210400-2502210400-oflxs892--0..> 21-Feb-2025 06:00 352428
wst04-VHDL20_DWPG_210800-2502210800-oflxs892--0..> 21-Feb-2025 09:45 421276
wst04-VHDL20_DWPG_211800-2502211800-oflxs892--0..> 21-Feb-2025 19:45 376705
wst04-VHDL20_DWPG_220200-2502220200-oflxs892--0..> 22-Feb-2025 03:45 376843
wst04-VHDL20_DWPG_220400-2502220400-oflxs892--0..> 22-Feb-2025 06:00 376606
wst04-VHDL20_DWPG_220800-2502220800-oflxs892--0..> 22-Feb-2025 09:45 410603
wst04-VHDL20_DWPH_201800-2502201800-oflxs892--0..> 20-Feb-2025 19:45 303598
wst04-VHDL20_DWPH_210200-2502210200-oflxs892--0..> 21-Feb-2025 03:45 258166
wst04-VHDL20_DWPH_210400-2502210400-oflxs892--0..> 21-Feb-2025 06:00 257899
wst04-VHDL20_DWPH_210800-2502210800-oflxs892--0..> 21-Feb-2025 09:45 308618
wst04-VHDL20_DWPH_211800-2502211800-oflxs892--0..> 21-Feb-2025 19:45 308560
wst04-VHDL20_DWPH_220200-2502220200-oflxs892--0..> 22-Feb-2025 03:45 263216
wst04-VHDL20_DWPH_220400-2502220400-oflxs892--0..> 22-Feb-2025 06:00 263261
wst04-VHDL20_DWPH_220800-2502220800-oflxs892--0..> 22-Feb-2025 09:45 307347
wst04-VHDL20_DWSG_201800-2502201800-omedes--0.pdf 20-Feb-2025 19:45 372586
wst04-VHDL20_DWSG_210200-2502210200-omedes--0.pdf 21-Feb-2025 03:45 372662
wst04-VHDL20_DWSG_210400-2502210400-omedes--0.pdf 21-Feb-2025 06:15 373024
wst04-VHDL20_DWSG_210800-2502210800-omedes--0.pdf 21-Feb-2025 09:45 376007
wst04-VHDL20_DWSG_211800-2502211800-omedes--0.pdf 21-Feb-2025 19:45 376085
wst04-VHDL20_DWSG_220200-2502220200-omedes--0.pdf 22-Feb-2025 03:45 376495
wst04-VHDL20_DWSG_220400-2502220400-omedes--0.pdf 22-Feb-2025 06:15 376904
wst04-VHDL20_DWSG_220800-2502220800-omedes--0.pdf 22-Feb-2025 09:45 370764