Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Oct-2026 12:53:02 2309
FPDL13_DWMZ_220600 22-Oct-2026 14:42:13 6310
SXDL31_DWAV_210800 21-Oct-2026 07:40:56 8660
SXDL31_DWAV_211800 21-Oct-2026 16:49:06 8374
SXDL31_DWAV_220800 22-Oct-2026 08:18:00 11220
SXDL31_DWAV_221800 22-Oct-2026 16:21:49 15200
SXDL31_DWAV_LATEST 22-Oct-2026 16:21:49 15200
SXDL33_DWAV_210000 21-Oct-2026 10:34:13 11903
SXDL33_DWAV_220000 22-Oct-2026 10:16:08 11133
SXDL33_DWAV_LATEST 22-Oct-2026 10:16:08 11133
ber01-FWDL39_DWMS_211200-2610211200-dsw--0-ia5 21-Oct-2026 11:41:13 1894
ber01-FWDL39_DWMS_221200-2610221200-dsw--0-ia5 22-Oct-2026 12:12:58 2376
ber01-VHDL13_DWEG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:21 2568
ber01-VHDL13_DWEG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 3262
ber01-VHDL13_DWEH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:13 2608
ber01-VHDL13_DWEH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 4044
ber01-VHDL13_DWEI_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:21 2624
ber01-VHDL13_DWEI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 3250
ber01-VHDL13_DWHG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 3515
ber01-VHDL13_DWHG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4463
ber01-VHDL13_DWHH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 3570
ber01-VHDL13_DWHH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4108
ber01-VHDL13_DWLG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2856
ber01-VHDL13_DWLG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3411
ber01-VHDL13_DWLH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2952
ber01-VHDL13_DWLH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3347
ber01-VHDL13_DWLI_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2644
ber01-VHDL13_DWLI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3362
ber01-VHDL13_DWMO_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2901
ber01-VHDL13_DWMO_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3537
ber01-VHDL13_DWMP_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 4065
ber01-VHDL13_DWMP_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3388
ber01-VHDL13_DWOG_201700-2610201700-dsw--0-ia5 20-Oct-2026 18:00:05 3956
ber01-VHDL13_DWOG_210300-2610210300-dsw--0-ia5 21-Oct-2026 03:04:37 4767
ber01-VHDL13_DWOG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:03 5300
ber01-VHDL13_DWOG_211700-2610211700-dsw--0-ia5 21-Oct-2026 18:00:04 4783
ber01-VHDL13_DWOG_220300-2610220300-dsw--0-ia5 22-Oct-2026 03:03:52 5936
ber01-VHDL13_DWOG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 5456
ber01-VHDL13_DWON_210052-2610210052-dsw--0-ia5 21-Oct-2026 00:52:49 4325
ber01-VHDL13_DWON_210238-2610210238-dsw--0-ia5 21-Oct-2026 02:38:52 4325
ber01-VHDL13_DWON_210528-2610210528-dsw--0-ia5 21-Oct-2026 05:28:24 4230
ber01-VHDL13_DWON_210618-2610210618-dsw--0-ia5 21-Oct-2026 06:19:04 4475
ber01-VHDL13_DWON_210819-2610210819-dsw--0-ia5 21-Oct-2026 08:19:53 4562
ber01-VHDL13_DWON_211433-2610211433-dsw--0-ia5 21-Oct-2026 14:33:31 3910
ber01-VHDL13_DWON_211717-2610211717-dsw--0-ia5 21-Oct-2026 17:17:12 4104
ber01-VHDL13_DWON_211833-2610211833-dsw--0-ia5 21-Oct-2026 18:33:51 4375
ber01-VHDL13_DWON_212142-2610212142-dsw--0-ia5 21-Oct-2026 21:42:36 4335
ber01-VHDL13_DWON_220004-2610220004-dsw--0-ia5 22-Oct-2026 00:04:18 5214
ber01-VHDL13_DWON_220144-2610220144-dsw--0-ia5 22-Oct-2026 01:44:34 5188
ber01-VHDL13_DWON_220251-2610220251-dsw--0-ia5 22-Oct-2026 02:54:01 5209
ber01-VHDL13_DWON_220348-2610220348-dsw--0-ia5 22-Oct-2026 03:48:56 5209
ber01-VHDL13_DWON_220527-2610220527-dsw--0-ia5 22-Oct-2026 05:27:33 4937
ber01-VHDL13_DWON_220628-2610220628-dsw--0-ia5 22-Oct-2026 06:28:24 4884
ber01-VHDL13_DWON_220743-2610220743-dsw--0-ia5 22-Oct-2026 07:43:27 4693
ber01-VHDL13_DWON_220845-2610220845-dsw--0-ia5 22-Oct-2026 08:45:33 4518
ber01-VHDL13_DWON_221059-2610221059-dsw--0-ia5 22-Oct-2026 10:59:17 4365
ber01-VHDL13_DWON_221517-2610221517-dsw--0-ia5 22-Oct-2026 15:17:17 3894
ber01-VHDL13_DWON_221647-2610221647-dsw--0-ia5 22-Oct-2026 16:47:38 3894
ber01-VHDL13_DWON_221709-2610221709-dsw--0-ia5 22-Oct-2026 17:10:09 3894
ber01-VHDL13_DWPG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2106
ber01-VHDL13_DWPG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2084
ber01-VHDL13_DWPH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2435
ber01-VHDL13_DWPH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2572
ber01-VHDL13_DWSG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:03 3934
ber01-VHDL13_DWSG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4149
ber01-VHDL17_DWOG_211200-2610211200-dsw--0-ia5 21-Oct-2026 11:09:54 3690
ber01-VHDL17_DWOG_221200-2610221200-dsw--0-ia5 22-Oct-2026 11:55:13 3434
swis2-VHDL20_DWEG_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:04 1125
swis2-VHDL20_DWEG_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:09 1069
swis2-VHDL20_DWEG_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:01:18 1077
swis2-VHDL20_DWEG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 1597
swis2-VHDL20_DWEG_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:18 1227
swis2-VHDL20_DWEG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1056
swis2-VHDL20_DWEG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 1434
swis2-VHDL20_DWEG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 1842
swis2-VHDL20_DWEH_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:04 1314
swis2-VHDL20_DWEH_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:09 1083
swis2-VHDL20_DWEH_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:01:18 1130
swis2-VHDL20_DWEH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 1671
swis2-VHDL20_DWEH_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:18 1413
swis2-VHDL20_DWEH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1079
swis2-VHDL20_DWEH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 2078
swis2-VHDL20_DWEH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2673
swis2-VHDL20_DWEI_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:04 1280
swis2-VHDL20_DWEI_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:09 1132
swis2-VHDL20_DWEI_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:01:18 1141
swis2-VHDL20_DWEI_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 1679
swis2-VHDL20_DWEI_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:18 1366
swis2-VHDL20_DWEI_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1225
swis2-VHDL20_DWEI_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 1538
swis2-VHDL20_DWEI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 1945
swis2-VHDL20_DWHG_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:45:13 1878
swis2-VHDL20_DWHG_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:18 1560
swis2-VHDL20_DWHG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2517
swis2-VHDL20_DWHG_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:45:12 2044
swis2-VHDL20_DWHG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1884
swis2-VHDL20_DWHG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3871
swis2-VHDL20_DWHH_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:45:13 1947
swis2-VHDL20_DWHH_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:46:41 1751
swis2-VHDL20_DWHH_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:18 1685
swis2-VHDL20_DWHH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2516
swis2-VHDL20_DWHH_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:45:12 2117
swis2-VHDL20_DWHH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:46:53 1740
swis2-VHDL20_DWHH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1723
swis2-VHDL20_DWHH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3413
swis2-VHDL20_DWLG_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:31:15 1284
swis2-VHDL20_DWLG_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:31 1092
swis2-VHDL20_DWLG_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:14 997
swis2-VHDL20_DWLG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:23 1313
swis2-VHDL20_DWLG_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:31:08 1411
swis2-VHDL20_DWLG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1527
swis2-VHDL20_DWLG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1554
swis2-VHDL20_DWLG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1889
swis2-VHDL20_DWLH_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:31:15 1395
swis2-VHDL20_DWLH_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:31 1019
swis2-VHDL20_DWLH_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:14 979
swis2-VHDL20_DWLH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:23 1483
swis2-VHDL20_DWLH_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:31:08 1398
swis2-VHDL20_DWLH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1418
swis2-VHDL20_DWLH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1531
swis2-VHDL20_DWLH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1976
swis2-VHDL20_DWLI_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:31:15 1263
swis2-VHDL20_DWLI_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:31 971
swis2-VHDL20_DWLI_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:14 907
swis2-VHDL20_DWLI_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:23 1322
swis2-VHDL20_DWLI_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:31:08 1411
swis2-VHDL20_DWLI_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1483
swis2-VHDL20_DWLI_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1537
swis2-VHDL20_DWLI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1908
swis2-VHDL20_DWMO_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:04 1390
swis2-VHDL20_DWMO_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:03 1365
swis2-VHDL20_DWMO_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:04 1421
swis2-VHDL20_DWMO_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 1787
swis2-VHDL20_DWMO_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:08 1836
swis2-VHDL20_DWMO_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 1675
swis2-VHDL20_DWMO_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:03 1659
swis2-VHDL20_DWMO_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2285
swis2-VHDL20_DWMP_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:04 2044
swis2-VHDL20_DWMP_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:03 2049
swis2-VHDL20_DWMP_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:04 2096
swis2-VHDL20_DWMP_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:09 2519
swis2-VHDL20_DWMP_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:08 2574
swis2-VHDL20_DWMP_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 2016
swis2-VHDL20_DWMP_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:03 1753
swis2-VHDL20_DWMP_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2259
swis2-VHDL20_DWPG_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:31:15 1073
swis2-VHDL20_DWPG_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:31 968
swis2-VHDL20_DWPG_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:14 846
swis2-VHDL20_DWPG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:23 1057
swis2-VHDL20_DWPG_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:31:08 1080
swis2-VHDL20_DWPG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 862
swis2-VHDL20_DWPG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 891
swis2-VHDL20_DWPG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1476
swis2-VHDL20_DWPH_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:31:15 1264
swis2-VHDL20_DWPH_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:31 1031
swis2-VHDL20_DWPH_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:14 988
swis2-VHDL20_DWPH_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:23 1360
swis2-VHDL20_DWPH_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:31:08 1301
swis2-VHDL20_DWPH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1089
swis2-VHDL20_DWPH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1115
swis2-VHDL20_DWPH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1774
swis2-VHDL20_DWSG_201800-2610201800-dsw--0-ia5 20-Oct-2026 18:30:08 2078
swis2-VHDL20_DWSG_210200-2610210200-dsw--0-ia5 21-Oct-2026 02:30:03 1308
swis2-VHDL20_DWSG_210400-2610210400-dsw--0-ia5 21-Oct-2026 05:00:18 1483
swis2-VHDL20_DWSG_210800-2610210800-dsw--0-ia5 21-Oct-2026 08:30:03 2261
swis2-VHDL20_DWSG_211800-2610211800-dsw--0-ia5 21-Oct-2026 18:30:08 2517
swis2-VHDL20_DWSG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 1833
swis2-VHDL20_DWSG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1863
swis2-VHDL20_DWSG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2428
wst04-VHDL20_DWEG_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:30:24 239004
wst04-VHDL20_DWEG_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:26 239700
wst04-VHDL20_DWEG_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:12 239426
wst04-VHDL20_DWEG_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:21 240907
wst04-VHDL20_DWEG_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:30:20 245635
wst04-VHDL20_DWEG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 245946
wst04-VHDL20_DWEG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 245900
wst04-VHDL20_DWEG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 247058
wst04-VHDL20_DWEH_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:30:24 236340
wst04-VHDL20_DWEH_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:16 237472
wst04-VHDL20_DWEH_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:12 237230
wst04-VHDL20_DWEH_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:23 238413
wst04-VHDL20_DWEH_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:30:20 242164
wst04-VHDL20_DWEH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 243345
wst04-VHDL20_DWEH_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 243628
wst04-VHDL20_DWEH_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 245098
wst04-VHDL20_DWEI_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:30:24 340882
wst04-VHDL20_DWEI_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:26 340654
wst04-VHDL20_DWEI_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:18 340864
wst04-VHDL20_DWEI_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:38 342673
wst04-VHDL20_DWEI_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:30:20 349953
wst04-VHDL20_DWEI_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 349795
wst04-VHDL20_DWEI_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:19 349769
wst04-VHDL20_DWEI_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 350959
wst04-VHDL20_DWHG_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:45:15 332512
wst04-VHDL20_DWHG_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:46:41 330656
wst04-VHDL20_DWHG_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:18 330438
wst04-VHDL20_DWHG_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:49 333942
wst04-VHDL20_DWHG_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:45:19 345298
wst04-VHDL20_DWHG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:46:53 344569
wst04-VHDL20_DWHG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:19 344371
wst04-VHDL20_DWHG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:34 347619
wst04-VHDL20_DWHH_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:45:15 329890
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wst04-VHDL20_DWHH_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:45:19 336534
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wst04-VHDL20_DWLG_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:31 329581
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wst04-VHDL20_DWLG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 342130
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wst04-VHDL20_DWLH_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:31:25 333492
wst04-VHDL20_DWLH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 332448
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wst04-VHDL20_DWLI_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:31 329347
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wst04-VHDL20_DWLI_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:57 375615
wst04-VHDL20_DWLI_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:31:25 336445
wst04-VHDL20_DWLI_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 336824
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wst04-VHDL20_DWLI_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:44 382147
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wst04-VHDL20_DWMO_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:16 450856
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wst04-VHDL20_DWMO_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 455173
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wst04-VHDL20_DWMP_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:31 581077
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wst04-VHDL20_DWMP_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:23 582467
wst04-VHDL20_DWMP_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:30:30 581849
wst04-VHDL20_DWMP_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 579865
wst04-VHDL20_DWMP_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:19 580038
wst04-VHDL20_DWMP_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:28 582179
wst04-VHDL20_DWPG_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:31:32 341231
wst04-VHDL20_DWPG_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:31 241271
wst04-VHDL20_DWPG_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:34 341050
wst04-VHDL20_DWPG_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:57 386727
wst04-VHDL20_DWPG_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:31:29 343002
wst04-VHDL20_DWPG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 242456
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wst04-VHDL20_DWPH_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:31 238758
wst04-VHDL20_DWPH_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:34 238063
wst04-VHDL20_DWPH_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:57 239177
wst04-VHDL20_DWPH_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:31:25 240415
wst04-VHDL20_DWPH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 240098
wst04-VHDL20_DWPH_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:33 240332
wst04-VHDL20_DWPH_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:44 241776
wst04-VHDL20_DWSG_201800-2610201800-omedes--0.pdf 20-Oct-2026 18:30:17 354613
wst04-VHDL20_DWSG_210200-2610210200-omedes--0.pdf 21-Oct-2026 02:30:16 352114
wst04-VHDL20_DWSG_210400-2610210400-omedes--0.pdf 21-Oct-2026 05:00:12 353363
wst04-VHDL20_DWSG_210800-2610210800-omedes--0.pdf 21-Oct-2026 08:30:13 353713
wst04-VHDL20_DWSG_211800-2610211800-omedes--0.pdf 21-Oct-2026 18:30:20 355499
wst04-VHDL20_DWSG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 353520
wst04-VHDL20_DWSG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 353487
wst04-VHDL20_DWSG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 354121