Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Nov-2026 11:08:13 5698
FPDL13_DWMZ_150600 15-Nov-2026 14:16:09 4143
SXDL31_DWAV_131810 13-Nov-2026 15:16:05 7611
SXDL31_DWAV_140810 14-Nov-2026 08:18:09 17143
SXDL31_DWAV_141810 14-Nov-2026 17:19:35 12266
SXDL31_DWAV_150810 15-Nov-2026 09:08:34 21925
SXDL31_DWAV_LATEST 15-Nov-2026 09:08:34 21925
SXDL33_DWAV_140000 14-Nov-2026 11:28:16 11271
SXDL33_DWAV_150000 15-Nov-2026 11:39:50 9022
SXDL33_DWAV_LATEST 15-Nov-2026 11:39:50 9022
ber01-FWDL39_DWMS_141200-2611141200-dsw--0-ia5 14-Nov-2026 12:05:18 1581
ber01-FWDL39_DWMS_151200-2611151200-dsw--0-ia5 15-Nov-2026 12:19:18 1450
ber01-VHDL13_DWEG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4645
ber01-VHDL13_DWEG_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4629
ber01-VHDL13_DWEG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:18 3666
ber01-VHDL13_DWEH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4680
ber01-VHDL13_DWEH_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4684
ber01-VHDL13_DWEH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:18 4091
ber01-VHDL13_DWEI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4424
ber01-VHDL13_DWEI_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4394
ber01-VHDL13_DWEI_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 3968
ber01-VHDL13_DWHG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3473
ber01-VHDL13_DWHG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3165
ber01-VHDL13_DWHH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3442
ber01-VHDL13_DWHH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3271
ber01-VHDL13_DWLG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3601
ber01-VHDL13_DWLG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3683
ber01-VHDL13_DWLG_150800_COR-2611150800-dsw--0-ia5 15-Nov-2026 10:21:37 3751
ber01-VHDL13_DWLH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3044
ber01-VHDL13_DWLH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3539
ber01-VHDL13_DWLI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3095
ber01-VHDL13_DWLI_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3311
ber01-VHDL13_DWMO_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 3916
ber01-VHDL13_DWMO_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:08 3794
ber01-VHDL13_DWMP_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 3525
ber01-VHDL13_DWMP_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:08 4203
ber01-VHDL13_DWOG_131700-2611131700-dsw--0-ia5 13-Nov-2026 19:00:26 4157
ber01-VHDL13_DWOG_140300-2611140300-dsw--0-ia5 14-Nov-2026 04:00:25 4983
ber01-VHDL13_DWOG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 4424
ber01-VHDL13_DWOG_141700-2611141700-dsw--0-ia5 14-Nov-2026 19:00:08 4633
ber01-VHDL13_DWOG_150300-2611150300-dsw--0-ia5 15-Nov-2026 04:00:15 5328
ber01-VHDL13_DWOG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 4940
ber01-VHDL13_DWON_131758-2611131758-dsw--0-ia5 13-Nov-2026 17:58:38 3563
ber01-VHDL13_DWON_140314-2611140314-dsw--0-ia5 14-Nov-2026 03:14:52 4484
ber01-VHDL13_DWON_140557-2611140557-dsw--0-ia5 14-Nov-2026 05:58:04 4327
ber01-VHDL13_DWON_140657-2611140657-dsw--0-ia5 14-Nov-2026 06:57:43 4327
ber01-VHDL13_DWON_141253-2611141253-dsw--0-ia5 14-Nov-2026 12:54:01 3759
ber01-VHDL13_DWON_141309-2611141309-dsw--0-ia5 14-Nov-2026 13:09:34 3841
ber01-VHDL13_DWON_141819-2611141819-dsw--0-ia5 14-Nov-2026 18:19:38 3891
ber01-VHDL13_DWON_150355-2611150355-dsw--0-ia5 15-Nov-2026 03:56:32 4554
ber01-VHDL13_DWON_150628-2611150628-dsw--0-ia5 15-Nov-2026 06:28:31 3849
ber01-VHDL13_DWON_150654-2611150654-dsw--0-ia5 15-Nov-2026 06:54:34 4125
ber01-VHDL13_DWON_150903-2611150903-dsw--0-ia5 15-Nov-2026 09:03:19 4105
ber01-VHDL13_DWON_151004-2611151004-dsw--0-ia5 15-Nov-2026 10:04:48 4105
ber01-VHDL13_DWPG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2435
ber01-VHDL13_DWPG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 2638
ber01-VHDL13_DWPH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2934
ber01-VHDL13_DWPH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3024
ber01-VHDL13_DWSG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:17 4375
ber01-VHDL13_DWSG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:14 4765
ber01-VHDL13_DWSG_150800_COR-2611150800-dsw--0-ia5 15-Nov-2026 14:13:04 4969
ber01-VHDL17_DWOG_141200-2611141200-dsw--0-ia5 14-Nov-2026 12:48:24 3029
ber01-VHDL17_DWOG_151200-2611151200-dsw--0-ia5 15-Nov-2026 12:48:34 3101
swis2-VHDL20_DWEG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2102
swis2-VHDL20_DWEG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 2075
swis2-VHDL20_DWEG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2993
swis2-VHDL20_DWEG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3792
swis2-VHDL20_DWEG_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:48:40 3856
swis2-VHDL20_DWEG_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:12 2452
swis2-VHDL20_DWEG_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:14 2124
swis2-VHDL20_DWEG_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:59 1871
swis2-VHDL20_DWEG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 2530
swis2-VHDL20_DWEH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2250
swis2-VHDL20_DWEH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1969
swis2-VHDL20_DWEH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2965
swis2-VHDL20_DWEH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3692
swis2-VHDL20_DWEH_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:48:59 3756
swis2-VHDL20_DWEH_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:12 2664
swis2-VHDL20_DWEH_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:24 2157
swis2-VHDL20_DWEH_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:59 1965
swis2-VHDL20_DWEH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 2924
swis2-VHDL20_DWEI_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2154
swis2-VHDL20_DWEI_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 2118
swis2-VHDL20_DWEI_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2844
swis2-VHDL20_DWEI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3630
swis2-VHDL20_DWEI_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:49:25 3665
swis2-VHDL20_DWEI_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:12 2689
swis2-VHDL20_DWEI_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:24 2222
swis2-VHDL20_DWEI_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:59 2017
swis2-VHDL20_DWEI_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 3133
swis2-VHDL20_DWHG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:45:25 2994
swis2-VHDL20_DWHG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1956
swis2-VHDL20_DWHG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2579
swis2-VHDL20_DWHG_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:45:11 2422
swis2-VHDL20_DWHG_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:13 1781
swis2-VHDL20_DWHG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 2440
swis2-VHDL20_DWHH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:45:25 2675
swis2-VHDL20_DWHH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:45:11 1785
swis2-VHDL20_DWHH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1828
swis2-VHDL20_DWHH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2481
swis2-VHDL20_DWHH_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:45:11 2342
swis2-VHDL20_DWHH_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:45:22 1944
swis2-VHDL20_DWHH_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:13 1854
swis2-VHDL20_DWHH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:10 2206
swis2-VHDL20_DWLG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1651
swis2-VHDL20_DWLG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1544
swis2-VHDL20_DWLG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1531
swis2-VHDL20_DWLG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 2043
swis2-VHDL20_DWLG_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:31:11 2035
swis2-VHDL20_DWLG_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:33 1829
swis2-VHDL20_DWLG_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:17 1882
swis2-VHDL20_DWLG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 2123
swis2-VHDL20_DWLG_150800_COR-2611150800-dsw--0-ia5 15-Nov-2026 10:23:24 2243
swis2-VHDL20_DWLH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1821
swis2-VHDL20_DWLH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1418
swis2-VHDL20_DWLH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1457
swis2-VHDL20_DWLH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 2124
swis2-VHDL20_DWLH_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:31:11 2192
swis2-VHDL20_DWLH_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:33 1858
swis2-VHDL20_DWLH_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:17 1898
swis2-VHDL20_DWLH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 2354
swis2-VHDL20_DWLI_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1758
swis2-VHDL20_DWLI_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1517
swis2-VHDL20_DWLI_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1385
swis2-VHDL20_DWLI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1958
swis2-VHDL20_DWLI_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:31:11 2121
swis2-VHDL20_DWLI_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:33 1839
swis2-VHDL20_DWLI_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:17 1674
swis2-VHDL20_DWLI_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 2031
swis2-VHDL20_DWMO_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 1644
swis2-VHDL20_DWMO_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1920
swis2-VHDL20_DWMO_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:02 1903
swis2-VHDL20_DWMO_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2495
swis2-VHDL20_DWMO_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:12 2514
swis2-VHDL20_DWMO_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:24 2388
swis2-VHDL20_DWMO_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:03 2282
swis2-VHDL20_DWMO_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:08 2719
swis2-VHDL20_DWMP_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 1716
swis2-VHDL20_DWMP_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1976
swis2-VHDL20_DWMP_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:02 1971
swis2-VHDL20_DWMP_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2385
swis2-VHDL20_DWMP_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:12 2244
swis2-VHDL20_DWMP_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:24 2360
swis2-VHDL20_DWMP_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:03 2349
swis2-VHDL20_DWMP_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:08 3005
swis2-VHDL20_DWPG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 996
swis2-VHDL20_DWPG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1253
swis2-VHDL20_DWPG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1093
swis2-VHDL20_DWPG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1392
swis2-VHDL20_DWPG_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:31:11 1631
swis2-VHDL20_DWPG_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:33 1428
swis2-VHDL20_DWPG_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:17 1369
swis2-VHDL20_DWPG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 1690
swis2-VHDL20_DWPH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1527
swis2-VHDL20_DWPH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1459
swis2-VHDL20_DWPH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1152
swis2-VHDL20_DWPH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1691
swis2-VHDL20_DWPH_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:31:11 1852
swis2-VHDL20_DWPH_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:33 1578
swis2-VHDL20_DWPH_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:17 1515
swis2-VHDL20_DWPH_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:27 1745
swis2-VHDL20_DWSG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:08 2816
swis2-VHDL20_DWSG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:08 1956
swis2-VHDL20_DWSG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:08 2113
swis2-VHDL20_DWSG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2804
swis2-VHDL20_DWSG_141800-2611141800-dsw--0-ia5 14-Nov-2026 19:30:07 2605
swis2-VHDL20_DWSG_150200-2611150200-dsw--0-ia5 15-Nov-2026 03:30:14 2368
swis2-VHDL20_DWSG_150400-2611150400-dsw--0-ia5 15-Nov-2026 06:00:09 2191
swis2-VHDL20_DWSG_150800-2611150800-dsw--0-ia5 15-Nov-2026 09:30:08 3003
swis2-VHDL20_DWSG_150800_COR-2611150800-dsw--0-ia5 15-Nov-2026 14:12:54 3251
wst04-VHDL20_DWEG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 236414
wst04-VHDL20_DWEG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 236947
wst04-VHDL20_DWEG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 237491
wst04-VHDL20_DWEG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:21 240209
wst04-VHDL20_DWEG_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:05 243031
wst04-VHDL20_DWEG_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:26 239836
wst04-VHDL20_DWEG_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:33 239812
wst04-VHDL20_DWEG_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:13 239138
wst04-VHDL20_DWEG_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:27 240117
wst04-VHDL20_DWEH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:25 231563
wst04-VHDL20_DWEH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 233305
wst04-VHDL20_DWEH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 234679
wst04-VHDL20_DWEH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:21 236556
wst04-VHDL20_DWEH_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:46 243030
wst04-VHDL20_DWEH_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:27 237828
wst04-VHDL20_DWEH_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:33 240310
wst04-VHDL20_DWEH_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:13 239735
wst04-VHDL20_DWEH_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:18 240644
wst04-VHDL20_DWEI_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 333458
wst04-VHDL20_DWEI_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 333716
wst04-VHDL20_DWEI_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 334640
wst04-VHDL20_DWEI_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:30 336671
wst04-VHDL20_DWEI_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:58 341698
wst04-VHDL20_DWEI_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:37 339393
wst04-VHDL20_DWEI_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:33 339351
wst04-VHDL20_DWEI_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:19 339143
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wst04-VHDL20_DWHG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:45:25 325749
wst04-VHDL20_DWHG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:45:22 323876
wst04-VHDL20_DWHG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:24 323896
wst04-VHDL20_DWHG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:48 326428
wst04-VHDL20_DWHG_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:45:11 334118
wst04-VHDL20_DWHG_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:45:24 332459
wst04-VHDL20_DWHG_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:23 332206
wst04-VHDL20_DWHG_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:39 334323
wst04-VHDL20_DWHH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:45:25 315624
wst04-VHDL20_DWHH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:45:22 313914
wst04-VHDL20_DWHH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:24 222547
wst04-VHDL20_DWHH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:48 314855
wst04-VHDL20_DWHH_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:45:11 321435
wst04-VHDL20_DWHH_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:45:24 320682
wst04-VHDL20_DWHH_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:23 225346
wst04-VHDL20_DWHH_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:39 321019
wst04-VHDL20_DWLG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 312384
wst04-VHDL20_DWLG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 313294
wst04-VHDL20_DWLG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 313560
wst04-VHDL20_DWLG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 314623
wst04-VHDL20_DWLG_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:31:29 326201
wst04-VHDL20_DWLG_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:36 325616
wst04-VHDL20_DWLG_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:43 325511
wst04-VHDL20_DWLG_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:50 326224
wst04-VHDL20_DWLG_150800_COR-2611150800-omedes-..> 15-Nov-2026 10:22:48 326519
wst04-VHDL20_DWLH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 316176
wst04-VHDL20_DWLH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 315092
wst04-VHDL20_DWLH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 314677
wst04-VHDL20_DWLH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 316748
wst04-VHDL20_DWLH_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:31:23 323076
wst04-VHDL20_DWLH_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:36 321840
wst04-VHDL20_DWLH_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:43 322188
wst04-VHDL20_DWLH_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:54 322894
wst04-VHDL20_DWLI_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 315076
wst04-VHDL20_DWLI_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 314462
wst04-VHDL20_DWLI_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 313363
wst04-VHDL20_DWLI_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 360336
wst04-VHDL20_DWLI_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:31:23 319302
wst04-VHDL20_DWLI_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:36 318591
wst04-VHDL20_DWLI_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:43 318441
wst04-VHDL20_DWLI_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:50 364139
wst04-VHDL20_DWMO_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:25 416025
wst04-VHDL20_DWMO_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 416223
wst04-VHDL20_DWMO_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:18 416881
wst04-VHDL20_DWMO_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:30 417786
wst04-VHDL20_DWMO_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:37 432882
wst04-VHDL20_DWMO_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:24 432419
wst04-VHDL20_DWMO_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:19 433426
wst04-VHDL20_DWMO_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:27 433912
wst04-VHDL20_DWMP_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 525456
wst04-VHDL20_DWMP_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 525107
wst04-VHDL20_DWMP_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:18 525081
wst04-VHDL20_DWMP_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:37 527651
wst04-VHDL20_DWMP_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:37 539899
wst04-VHDL20_DWMP_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:33 539005
wst04-VHDL20_DWMP_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:19 539096
wst04-VHDL20_DWMP_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:27 540927
wst04-VHDL20_DWPG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:27 315413
wst04-VHDL20_DWPG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 227343
wst04-VHDL20_DWPG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:32 315727
wst04-VHDL20_DWPG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 361726
wst04-VHDL20_DWPG_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:31:23 328129
wst04-VHDL20_DWPG_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:36 232047
wst04-VHDL20_DWPG_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:33 327431
wst04-VHDL20_DWPG_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:50 372611
wst04-VHDL20_DWPH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 229754
wst04-VHDL20_DWPH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 228468
wst04-VHDL20_DWPH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:32 229140
wst04-VHDL20_DWPH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 229977
wst04-VHDL20_DWPH_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:31:23 233678
wst04-VHDL20_DWPH_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:33 233123
wst04-VHDL20_DWPH_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:23:32 232974
wst04-VHDL20_DWPH_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:50 233343
wst04-VHDL20_DWSG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:16 335061
wst04-VHDL20_DWSG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 332656
wst04-VHDL20_DWSG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 333245
wst04-VHDL20_DWSG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:17 333576
wst04-VHDL20_DWSG_141800-2611141800-omedes--0.pdf 14-Nov-2026 19:30:27 346316
wst04-VHDL20_DWSG_150200-2611150200-omedes--0.pdf 15-Nov-2026 03:30:24 345980
wst04-VHDL20_DWSG_150400-2611150400-omedes--0.pdf 15-Nov-2026 06:00:13 345860
wst04-VHDL20_DWSG_150800-2611150800-omedes--0.pdf 15-Nov-2026 09:30:18 347415
wst04-VHDL20_DWSG_150800_COR-2611150800-omedes-..> 15-Nov-2026 14:13:04 339129