Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Sep-2025 11:52:14 4545
FPDL13_DWMZ_150600 15-Sep-2025 12:33:05 3367
SXDL31_DWAV_140800 14-Sep-2025 08:03:59 10656
SXDL31_DWAV_141800 14-Sep-2025 15:50:03 1664
SXDL31_DWAV_150800 15-Sep-2025 08:01:53 12471
SXDL31_DWAV_151800 15-Sep-2025 16:55:25 5505
SXDL31_DWAV_LATEST 15-Sep-2025 16:55:25 5505
SXDL33_DWAV_140000 14-Sep-2025 10:09:23 11237
SXDL33_DWAV_150000 15-Sep-2025 10:16:44 12040
SXDL33_DWAV_LATEST 15-Sep-2025 10:16:44 12040
ber01-FWDL39_DWMS_141230-2509141230-dsw--0-ia5 14-Sep-2025 11:25:56 1196
ber01-FWDL39_DWMS_151230-2509151230-dsw--0-ia5 15-Sep-2025 12:29:07 2046
ber01-VHDL13_DWEH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:28:16 3637
ber01-VHDL13_DWEH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:28:17 3331
ber01-VHDL13_DWEH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:28:11 3039
ber01-VHDL13_DWEH_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:58:11 2980
ber01-VHDL13_DWEH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:28:16 3136
ber01-VHDL13_DWEH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:28:16 2806
ber01-VHDL13_DWEH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:28:13 2829
ber01-VHDL13_DWEH_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:58:17 2735
ber01-VHDL13_DWHG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:08 3789
ber01-VHDL13_DWHG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:05 3575
ber01-VHDL13_DWHG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:06 3723
ber01-VHDL13_DWHG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3718
ber01-VHDL13_DWHG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:08 3921
ber01-VHDL13_DWHG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:07 3592
ber01-VHDL13_DWHG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:06 3741
ber01-VHDL13_DWHG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 3865
ber01-VHDL13_DWHH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:08 3723
ber01-VHDL13_DWHH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:05 3546
ber01-VHDL13_DWHH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:06 3575
ber01-VHDL13_DWHH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3570
ber01-VHDL13_DWHH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:08 4023
ber01-VHDL13_DWHH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:07 3741
ber01-VHDL13_DWHH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:06 3761
ber01-VHDL13_DWHH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 3956
ber01-VHDL13_DWLG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:01 2726
ber01-VHDL13_DWLG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2378
ber01-VHDL13_DWLG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2889
ber01-VHDL13_DWLG_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:59:57 3008
ber01-VHDL13_DWLG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:08 3035
ber01-VHDL13_DWLG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2313
ber01-VHDL13_DWLG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2461
ber01-VHDL13_DWLG_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:59:56 2309
ber01-VHDL13_DWLH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:01 2917
ber01-VHDL13_DWLH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2602
ber01-VHDL13_DWLH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 3131
ber01-VHDL13_DWLH_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:59:57 3182
ber01-VHDL13_DWLH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:08 3325
ber01-VHDL13_DWLH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2465
ber01-VHDL13_DWLH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2420
ber01-VHDL13_DWLH_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:59:56 2616
ber01-VHDL13_DWLI_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:01 2661
ber01-VHDL13_DWLI_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2395
ber01-VHDL13_DWLI_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2926
ber01-VHDL13_DWLI_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:59:57 2650
ber01-VHDL13_DWLI_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:08 2718
ber01-VHDL13_DWLI_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2248
ber01-VHDL13_DWLI_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2248
ber01-VHDL13_DWLI_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:59:56 2136
ber01-VHDL13_DWMG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:03 2737
ber01-VHDL13_DWMG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2568
ber01-VHDL13_DWMG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2799
ber01-VHDL13_DWMG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 2739
ber01-VHDL13_DWMG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 3583
ber01-VHDL13_DWMG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 3431
ber01-VHDL13_DWMG_151800_COR-2509151800-dsw--0-ia5 15-Sep-2025 19:08:56 3566
ber01-VHDL13_DWMG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2806
ber01-VHDL13_DWMG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2609
ber01-VHDL13_DWMO_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:03 2587
ber01-VHDL13_DWMO_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2339
ber01-VHDL13_DWMO_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2448
ber01-VHDL13_DWMO_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 2428
ber01-VHDL13_DWMO_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 3033
ber01-VHDL13_DWMO_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2966
ber01-VHDL13_DWMO_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2674
ber01-VHDL13_DWMO_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2684
ber01-VHDL13_DWMP_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:03 2755
ber01-VHDL13_DWMP_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2482
ber01-VHDL13_DWMP_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2806
ber01-VHDL13_DWMP_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 2840
ber01-VHDL13_DWMP_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 3158
ber01-VHDL13_DWMP_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 3046
ber01-VHDL13_DWMP_151800_COR-2509151800-dsw--0-ia5 15-Sep-2025 19:09:06 3182
ber01-VHDL13_DWMP_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2444
ber01-VHDL13_DWMP_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2261
ber01-VHDL13_DWOG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:01 4606
ber01-VHDL13_DWOG_140800_COR-2509140800-dsw--0-ia5 14-Sep-2025 17:02:02 6087
ber01-VHDL13_DWOG_141700-2509141700-dsw--0-ia5 14-Sep-2025 18:00:02 6083
ber01-VHDL13_DWOG_150300-2509150300-dsw--0-ia5 15-Sep-2025 03:00:01 5149
ber01-VHDL13_DWOG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 5530
ber01-VHDL13_DWOG_151700-2509151700-dsw--0-ia5 15-Sep-2025 18:00:00 4806
ber01-VHDL13_DWOG_151700_COR-2509151700-dsw--0-ia5 15-Sep-2025 19:44:17 5549
ber01-VHDL13_DWOG_160300-2509160300-dsw--0-ia5 16-Sep-2025 03:00:09 5762
ber01-VHDL13_DWOH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:28:16 2965
ber01-VHDL13_DWOH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:28:17 2886
ber01-VHDL13_DWOH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:28:11 2899
ber01-VHDL13_DWOH_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:58:17 2843
ber01-VHDL13_DWOH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:28:16 3025
ber01-VHDL13_DWOH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:28:16 2522
ber01-VHDL13_DWOH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:28:17 2624
ber01-VHDL13_DWOH_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:58:11 2580
ber01-VHDL13_DWOI_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:28:12 3166
ber01-VHDL13_DWOI_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:28:11 2921
ber01-VHDL13_DWOI_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:28:17 2907
ber01-VHDL13_DWOI_150400-2509150400-dsw--0-ia5 15-Sep-2025 04:58:17 2882
ber01-VHDL13_DWOI_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:28:12 3043
ber01-VHDL13_DWOI_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:28:12 2628
ber01-VHDL13_DWOI_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:28:13 2642
ber01-VHDL13_DWOI_160400-2509160400-dsw--0-ia5 16-Sep-2025 04:58:11 2594
ber01-VHDL13_DWON_140801-2509140801-dsw--0-ia5 14-Sep-2025 08:01:27 4197
ber01-VHDL13_DWON_141349-2509141349-dsw--0-ia5 14-Sep-2025 13:49:22 3717
ber01-VHDL13_DWON_141701-2509141701-dsw--0-ia5 14-Sep-2025 17:01:41 4452
ber01-VHDL13_DWON_141956-2509141956-dsw--0-ia5 14-Sep-2025 19:56:07 4178
ber01-VHDL13_DWON_150143-2509150143-dsw--0-ia5 15-Sep-2025 01:43:11 4218
ber01-VHDL13_DWON_150257-2509150257-dsw--0-ia5 15-Sep-2025 02:57:27 3879
ber01-VHDL13_DWON_150514-2509150514-dsw--0-ia5 15-Sep-2025 05:14:31 4147
ber01-VHDL13_DWON_150608-2509150608-dsw--0-ia5 15-Sep-2025 06:09:02 4147
ber01-VHDL13_DWON_150814-2509150814-dsw--0-ia5 15-Sep-2025 08:14:48 4147
ber01-VHDL13_DWON_151454-2509151454-dsw--0-ia5 15-Sep-2025 14:55:11 3865
ber01-VHDL13_DWON_151703-2509151703-dsw--0-ia5 15-Sep-2025 17:03:16 3865
ber01-VHDL13_DWON_151943-2509151943-dsw--0-ia5 15-Sep-2025 19:43:42 4575
ber01-VHDL13_DWON_160157-2509160157-dsw--0-ia5 16-Sep-2025 01:57:07 4970
ber01-VHDL13_DWON_160522-2509160522-dsw--0-ia5 16-Sep-2025 05:22:26 4200
ber01-VHDL13_DWPG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:03 2361
ber01-VHDL13_DWPG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2034
ber01-VHDL13_DWPG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2225
ber01-VHDL13_DWPG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:01 2386
ber01-VHDL13_DWPG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 2683
ber01-VHDL13_DWPG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2039
ber01-VHDL13_DWPG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2148
ber01-VHDL13_DWPG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2341
ber01-VHDL13_DWPH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:03 2770
ber01-VHDL13_DWPH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 2403
ber01-VHDL13_DWPH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 2715
ber01-VHDL13_DWPH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:01 3100
ber01-VHDL13_DWPH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 3236
ber01-VHDL13_DWPH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2565
ber01-VHDL13_DWPH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2646
ber01-VHDL13_DWPH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2743
ber01-VHDL13_DWSG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:30:01 3142
ber01-VHDL13_DWSG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:30:02 3041
ber01-VHDL13_DWSG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:02 3132
ber01-VHDL13_DWSG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 3325
ber01-VHDL13_DWSG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:30:02 3326
ber01-VHDL13_DWSG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:30:02 2686
ber01-VHDL13_DWSG_151800_COR-2509151800-dsw--0-ia5 15-Sep-2025 19:41:01 2456
ber01-VHDL13_DWSG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:02 2133
ber01-VHDL13_DWSG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 2269
ber01-VHDL17_DWOG_141200-2509141200-dsw--0-ia5 14-Sep-2025 12:01:52 3642
ber01-VHDL17_DWOG_151200-2509151200-dsw--0-ia5 15-Sep-2025 11:46:22 4039
pid-VHDL12_DWHG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:06 3213
pid-VHDL12_DWHG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3206
pid-VHDL12_DWHG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:06 3323
pid-VHDL12_DWHG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:14 3445
pid-VHDL12_DWHH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:30:06 3112
pid-VHDL12_DWHH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3107
pid-VHDL12_DWHH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:30:08 3350
pid-VHDL12_DWHH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 3545
swis2-VHDL20_DWEG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:07 3144
swis2-VHDL20_DWEG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 3071
swis2-VHDL20_DWEG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3031
swis2-VHDL20_DWEG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:15:02 3051
swis2-VHDL20_DWEG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3204
swis2-VHDL20_DWEG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2707
swis2-VHDL20_DWEG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2756
swis2-VHDL20_DWEG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:15:04 2788
swis2-VHDL20_DWEH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:11 3815
swis2-VHDL20_DWEH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:13 3530
swis2-VHDL20_DWEH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:12 3203
swis2-VHDL20_DWEH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:15:17 3158
swis2-VHDL20_DWEH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:11 3314
swis2-VHDL20_DWEH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:12 3007
swis2-VHDL20_DWEH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:16 2993
swis2-VHDL20_DWEH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:15:16 2913
swis2-VHDL20_DWEI_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:07 3345
swis2-VHDL20_DWEI_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 3106
swis2-VHDL20_DWEI_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3040
swis2-VHDL20_DWEI_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:15:17 3067
swis2-VHDL20_DWEI_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3222
swis2-VHDL20_DWEI_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2813
swis2-VHDL20_DWEI_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2775
swis2-VHDL20_DWEI_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:15:16 2779
swis2-VHDL20_DWHG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 3972
swis2-VHDL20_DWHG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 3758
swis2-VHDL20_DWHG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:06 3909
swis2-VHDL20_DWHG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3901
swis2-VHDL20_DWHG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 4104
swis2-VHDL20_DWHG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 3775
swis2-VHDL20_DWHG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 3927
swis2-VHDL20_DWHG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 4048
swis2-VHDL20_DWHH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 3909
swis2-VHDL20_DWHH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 3732
swis2-VHDL20_DWHH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3761
swis2-VHDL20_DWHH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:11 3756
swis2-VHDL20_DWHH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 4209
swis2-VHDL20_DWHH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 3927
swis2-VHDL20_DWHH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 3947
swis2-VHDL20_DWHH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:12 4142
swis2-VHDL20_DWLG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2950
swis2-VHDL20_DWLG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 2599
swis2-VHDL20_DWLG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3110
swis2-VHDL20_DWLG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:23 3229
swis2-VHDL20_DWLG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3259
swis2-VHDL20_DWLG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2534
swis2-VHDL20_DWLG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2682
swis2-VHDL20_DWLG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:22 2530
swis2-VHDL20_DWLH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 3138
swis2-VHDL20_DWLH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 2823
swis2-VHDL20_DWLH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3352
swis2-VHDL20_DWLH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:23 3403
swis2-VHDL20_DWLH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3546
swis2-VHDL20_DWLH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2686
swis2-VHDL20_DWLH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2641
swis2-VHDL20_DWLH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:22 2837
swis2-VHDL20_DWLI_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2882
swis2-VHDL20_DWLI_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 2616
swis2-VHDL20_DWLI_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3147
swis2-VHDL20_DWLI_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:23 2868
swis2-VHDL20_DWLI_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 2939
swis2-VHDL20_DWLI_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2469
swis2-VHDL20_DWLI_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2469
swis2-VHDL20_DWLI_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:22 2354
swis2-VHDL20_DWMG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2948
swis2-VHDL20_DWMG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:07 2779
swis2-VHDL20_DWMG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3007
swis2-VHDL20_DWMG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 2950
swis2-VHDL20_DWMG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3786
swis2-VHDL20_DWMG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 3642
swis2-VHDL20_DWMG_151800_COR-2509151800-dsw--0-ia5 15-Sep-2025 19:08:56 3940
swis2-VHDL20_DWMG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 3019
swis2-VHDL20_DWMG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2820
swis2-VHDL20_DWMO_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2799
swis2-VHDL20_DWMO_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:07 2551
swis2-VHDL20_DWMO_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 2663
swis2-VHDL20_DWMO_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 2643
swis2-VHDL20_DWMO_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3245
swis2-VHDL20_DWMO_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 3178
swis2-VHDL20_DWMO_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2889
swis2-VHDL20_DWMO_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2899
swis2-VHDL20_DWMP_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2967
swis2-VHDL20_DWMP_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:07 2752
swis2-VHDL20_DWMP_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3017
swis2-VHDL20_DWMP_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:07 3052
swis2-VHDL20_DWMP_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3370
swis2-VHDL20_DWMP_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 3270
swis2-VHDL20_DWMP_151800_COR-2509151800-dsw--0-ia5 15-Sep-2025 19:09:06 3567
swis2-VHDL20_DWMP_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2656
swis2-VHDL20_DWMP_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2473
swis2-VHDL20_DWPG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2558
swis2-VHDL20_DWPG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 2231
swis2-VHDL20_DWPG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 2422
swis2-VHDL20_DWPG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:01 2581
swis2-VHDL20_DWPG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 2880
swis2-VHDL20_DWPG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2236
swis2-VHDL20_DWPG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2345
swis2-VHDL20_DWPG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2536
swis2-VHDL20_DWPH_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 2967
swis2-VHDL20_DWPH_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 2600
swis2-VHDL20_DWPH_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 2912
swis2-VHDL20_DWPH_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:00:01 3297
swis2-VHDL20_DWPH_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3433
swis2-VHDL20_DWPH_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:02 2762
swis2-VHDL20_DWPH_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2843
swis2-VHDL20_DWPH_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:00:02 2940
swis2-VHDL20_DWSG_140800-2509140800-dsw--0-ia5 14-Sep-2025 08:45:04 3372
swis2-VHDL20_DWSG_141300-2509141300-dsw--0-ia5 14-Sep-2025 13:45:09 3593
swis2-VHDL20_DWSG_141800-2509141800-dsw--0-ia5 14-Sep-2025 18:45:01 3273
swis2-VHDL20_DWSG_150200-2509150200-dsw--0-ia5 15-Sep-2025 02:45:01 3366
swis2-VHDL20_DWSG_150400-2509150400-dsw--0-ia5 15-Sep-2025 05:15:07 3556
swis2-VHDL20_DWSG_150800-2509150800-dsw--0-ia5 15-Sep-2025 08:45:07 3556
swis2-VHDL20_DWSG_151300-2509151300-dsw--0-ia5 15-Sep-2025 13:45:02 3556
swis2-VHDL20_DWSG_151800-2509151800-dsw--0-ia5 15-Sep-2025 18:45:00 2918
swis2-VHDL20_DWSG_160200-2509160200-dsw--0-ia5 16-Sep-2025 02:45:02 2367
swis2-VHDL20_DWSG_160400-2509160400-dsw--0-ia5 16-Sep-2025 05:15:04 2500
wst04-VHDL20_DWEG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:11 269203
wst04-VHDL20_DWEG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:21 265924
wst04-VHDL20_DWEG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:17 265504
wst04-VHDL20_DWEG_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:15:13 265062
wst04-VHDL20_DWEG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:17 265238
wst04-VHDL20_DWEG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:22 264599
wst04-VHDL20_DWEG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 264469
wst04-VHDL20_DWEG_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:15:12 264751
wst04-VHDL20_DWEH_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:11 265014
wst04-VHDL20_DWEH_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:21 265284
wst04-VHDL20_DWEH_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:17 265380
wst04-VHDL20_DWEH_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:15:13 264291
wst04-VHDL20_DWEH_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:17 264544
wst04-VHDL20_DWEH_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:22 259711
wst04-VHDL20_DWEH_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 259586
wst04-VHDL20_DWEH_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:15:12 259735
wst04-VHDL20_DWEI_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:17 375258
wst04-VHDL20_DWEI_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:21 365787
wst04-VHDL20_DWEI_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:22 366256
wst04-VHDL20_DWEI_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:15:17 364822
wst04-VHDL20_DWEI_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:23 364961
wst04-VHDL20_DWEI_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:22 362904
wst04-VHDL20_DWEI_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 363559
wst04-VHDL20_DWEI_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:15:16 362854
wst04-VHDL20_DWHG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:17 367073
wst04-VHDL20_DWHG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:27 361532
wst04-VHDL20_DWHG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:22 362271
wst04-VHDL20_DWHG_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:11 362288
wst04-VHDL20_DWHG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:23 363472
wst04-VHDL20_DWHG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:22 367281
wst04-VHDL20_DWHG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:26 367451
wst04-VHDL20_DWHG_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:16 367484
wst04-VHDL20_DWHH_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:17 354696
wst04-VHDL20_DWHH_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:27 356092
wst04-VHDL20_DWHH_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:22 356875
wst04-VHDL20_DWHH_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:11 356818
wst04-VHDL20_DWHH_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:23 357106
wst04-VHDL20_DWHH_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:27 354709
wst04-VHDL20_DWHH_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:26 354715
wst04-VHDL20_DWHH_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:12 355199
wst04-VHDL20_DWLG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:40:30 359421
wst04-VHDL20_DWLG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:40:31 354919
wst04-VHDL20_DWLG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:40:44 355517
wst04-VHDL20_DWLG_150400-2509150400-omedes--0.pdf 15-Sep-2025 04:59:41 355728
wst04-VHDL20_DWLG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:40:32 355727
wst04-VHDL20_DWLG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:40:32 356672
wst04-VHDL20_DWLG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:40:32 357007
wst04-VHDL20_DWLG_160400-2509160400-omedes--0.pdf 16-Sep-2025 04:59:41 356199
wst04-VHDL20_DWLH_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:40:22 356384
wst04-VHDL20_DWLH_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:40:21 354071
wst04-VHDL20_DWLH_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:40:44 354699
wst04-VHDL20_DWLH_150400-2509150400-omedes--0.pdf 15-Sep-2025 04:59:41 354370
wst04-VHDL20_DWLH_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:40:22 354386
wst04-VHDL20_DWLH_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:40:22 357459
wst04-VHDL20_DWLH_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:40:22 358070
wst04-VHDL20_DWLH_160400-2509160400-omedes--0.pdf 16-Sep-2025 04:59:41 357626
wst04-VHDL20_DWLI_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:40:42 358999
wst04-VHDL20_DWLI_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:40:42 351644
wst04-VHDL20_DWLI_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:40:44 352272
wst04-VHDL20_DWLI_150400-2509150400-omedes--0.pdf 15-Sep-2025 04:59:41 351784
wst04-VHDL20_DWLI_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:40:44 351794
wst04-VHDL20_DWLI_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:40:42 356659
wst04-VHDL20_DWLI_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:40:42 356983
wst04-VHDL20_DWLI_160400-2509160400-omedes--0.pdf 16-Sep-2025 04:59:41 355851
wst04-VHDL20_DWMG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:22 575520
wst04-VHDL20_DWMG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:17 563067
wst04-VHDL20_DWMG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:27 563935
wst04-VHDL20_DWMG_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:17 563301
wst04-VHDL20_DWMG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:11 564170
wst04-VHDL20_DWMG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:16 553696
wst04-VHDL20_DWMG_151800_COR-2509151800-omedes-..> 15-Sep-2025 19:09:02 555196
wst04-VHDL20_DWMG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 554064
wst04-VHDL20_DWMG_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:18 552404
wst04-VHDL20_DWMO_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:22 463588
wst04-VHDL20_DWMO_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:11 459249
wst04-VHDL20_DWMO_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:17 459233
wst04-VHDL20_DWMO_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:17 459694
wst04-VHDL20_DWMO_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:11 459669
wst04-VHDL20_DWMO_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:12 456763
wst04-VHDL20_DWMO_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 456369
wst04-VHDL20_DWMO_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:18 456825
wst04-VHDL20_DWMP_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:22 589056
wst04-VHDL20_DWMP_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:21 573084
wst04-VHDL20_DWMP_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:22 573575
wst04-VHDL20_DWMP_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:17 573665
wst04-VHDL20_DWMP_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:18 573786
wst04-VHDL20_DWMP_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:16 561833
wst04-VHDL20_DWMP_151800_COR-2509151800-omedes-..> 15-Sep-2025 19:09:16 562790
wst04-VHDL20_DWMP_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:24 561595
wst04-VHDL20_DWMP_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:18 560869
wst04-VHDL20_DWPG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:28 410947
wst04-VHDL20_DWPG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:17 362361
wst04-VHDL20_DWPG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:12 361887
wst04-VHDL20_DWPG_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:11 362104
wst04-VHDL20_DWPG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:25 407258
wst04-VHDL20_DWPG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:12 367854
wst04-VHDL20_DWPG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:11 369078
wst04-VHDL20_DWPG_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:12 369256
wst04-VHDL20_DWPH_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:22 309053
wst04-VHDL20_DWPH_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:13 307264
wst04-VHDL20_DWPH_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:12 262637
wst04-VHDL20_DWPH_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:00:11 262952
wst04-VHDL20_DWPH_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:25 307506
wst04-VHDL20_DWPH_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:12 306703
wst04-VHDL20_DWPH_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:11 262820
wst04-VHDL20_DWPH_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:00:12 262838
wst04-VHDL20_DWSG_140800-2509140800-omedes--0.pdf 14-Sep-2025 08:45:17 375557
wst04-VHDL20_DWSG_141300-2509141300-omedes--0.pdf 14-Sep-2025 13:45:11 367443
wst04-VHDL20_DWSG_141800-2509141800-omedes--0.pdf 14-Sep-2025 18:45:17 366930
wst04-VHDL20_DWSG_150200-2509150200-omedes--0.pdf 15-Sep-2025 02:45:17 368042
wst04-VHDL20_DWSG_150400-2509150400-omedes--0.pdf 15-Sep-2025 05:15:11 367985
wst04-VHDL20_DWSG_150800-2509150800-omedes--0.pdf 15-Sep-2025 08:45:17 368025
wst04-VHDL20_DWSG_151300-2509151300-omedes--0.pdf 15-Sep-2025 13:45:12 362272
wst04-VHDL20_DWSG_151800-2509151800-omedes--0.pdf 15-Sep-2025 18:45:16 361721
wst04-VHDL20_DWSG_160200-2509160200-omedes--0.pdf 16-Sep-2025 02:45:11 359866
wst04-VHDL20_DWSG_160400-2509160400-omedes--0.pdf 16-Sep-2025 05:15:12 361110