Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Aug-2026 14:26:49 6286
FPDL13_DWMZ_250600 25-Aug-2026 13:29:28 4249
SXDL31_DWAV_240800 24-Aug-2026 09:10:24 11614
SXDL31_DWAV_241800 24-Aug-2026 15:36:10 5890
SXDL31_DWAV_250800 25-Aug-2026 07:25:54 7217
SXDL31_DWAV_251800 25-Aug-2026 15:39:06 6092
SXDL31_DWAV_LATEST 25-Aug-2026 15:39:06 6092
SXDL33_DWAV_240000 24-Aug-2026 11:05:18 8825
SXDL33_DWAV_250000 25-Aug-2026 10:45:39 11145
SXDL33_DWAV_LATEST 25-Aug-2026 10:45:39 11145
ber01-FWDL39_DWMS_241200-2608241200-dsw--0-ia5 24-Aug-2026 11:09:58 1761
ber01-FWDL39_DWMS_251200-2608251200-dsw--0-ia5 25-Aug-2026 11:31:24 1866
ber01-VHDL13_DWEG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3141
ber01-VHDL13_DWEG_240800_COR-2608240800-dsw--0-ia5 24-Aug-2026 18:28:48 3257
ber01-VHDL13_DWEG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:14 2771
ber01-VHDL13_DWEG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 2818
ber01-VHDL13_DWEH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3113
ber01-VHDL13_DWEH_240800_COR-2608240800-dsw--0-ia5 24-Aug-2026 18:29:08 2777
ber01-VHDL13_DWEH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:14 2943
ber01-VHDL13_DWEH_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 3215
ber01-VHDL13_DWEI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3452
ber01-VHDL13_DWEI_240800_COR-2608240800-dsw--0-ia5 24-Aug-2026 18:29:24 3354
ber01-VHDL13_DWEI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:18 3314
ber01-VHDL13_DWEI_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 3448
ber01-VHDL13_DWHG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2718
ber01-VHDL13_DWHG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:10 3237
ber01-VHDL13_DWHH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2668
ber01-VHDL13_DWHH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:10 3078
ber01-VHDL13_DWLG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2212
ber01-VHDL13_DWLG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2521
ber01-VHDL13_DWLH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2348
ber01-VHDL13_DWLH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2930
ber01-VHDL13_DWLI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2497
ber01-VHDL13_DWLI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2804
ber01-VHDL13_DWMO_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2985
ber01-VHDL13_DWMO_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3566
ber01-VHDL13_DWMP_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2842
ber01-VHDL13_DWMP_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3619
ber01-VHDL13_DWOG_240300-2608240300-dsw--0-ia5 24-Aug-2026 03:00:09 2855
ber01-VHDL13_DWOG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2993
ber01-VHDL13_DWOG_241700-2608241700-dsw--0-ia5 24-Aug-2026 18:00:04 3187
ber01-VHDL13_DWOG_250300-2608250300-dsw--0-ia5 25-Aug-2026 03:00:11 4151
ber01-VHDL13_DWOG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 3783
ber01-VHDL13_DWOG_251700-2608251700-dsw--0-ia5 25-Aug-2026 18:00:03 3535
ber01-VHDL13_DWON_240107-2608240107-dsw--0-ia5 24-Aug-2026 01:07:38 2881
ber01-VHDL13_DWON_240245-2608240245-dsw--0-ia5 24-Aug-2026 02:45:36 2866
ber01-VHDL13_DWON_240530-2608240530-dsw--0-ia5 24-Aug-2026 05:30:15 2866
ber01-VHDL13_DWON_240634-2608240634-dsw--0-ia5 24-Aug-2026 06:34:55 3098
ber01-VHDL13_DWON_241123-2608241123-dsw--0-ia5 24-Aug-2026 11:23:18 3098
ber01-VHDL13_DWON_241528-2608241528-dsw--0-ia5 24-Aug-2026 15:28:48 2822
ber01-VHDL13_DWON_241755-2608241755-dsw--0-ia5 24-Aug-2026 17:55:18 2822
ber01-VHDL13_DWON_241850-2608241850-dsw--0-ia5 24-Aug-2026 18:50:34 3557
ber01-VHDL13_DWON_242001-2608242001-dsw--0-ia5 24-Aug-2026 20:01:14 3557
ber01-VHDL13_DWON_242154-2608242154-dsw--0-ia5 24-Aug-2026 21:54:33 3551
ber01-VHDL13_DWON_250004-2608250004-dsw--0-ia5 25-Aug-2026 00:04:09 3959
ber01-VHDL13_DWON_250149-2608250149-dsw--0-ia5 25-Aug-2026 01:49:48 4011
ber01-VHDL13_DWON_250253-2608250253-dsw--0-ia5 25-Aug-2026 02:53:50 4010
ber01-VHDL13_DWON_250307-2608250307-dsw--0-ia5 25-Aug-2026 03:08:08 4010
ber01-VHDL13_DWON_250528-2608250528-dsw--0-ia5 25-Aug-2026 05:28:20 3831
ber01-VHDL13_DWON_250624-2608250624-dsw--0-ia5 25-Aug-2026 06:24:58 3721
ber01-VHDL13_DWON_250811-2608250811-dsw--0-ia5 25-Aug-2026 08:11:09 3753
ber01-VHDL13_DWON_251454-2608251454-dsw--0-ia5 25-Aug-2026 14:54:25 3752
ber01-VHDL13_DWON_251546-2608251546-dsw--0-ia5 25-Aug-2026 15:46:53 3438
ber01-VHDL13_DWON_251723-2608251723-dsw--0-ia5 25-Aug-2026 17:23:39 3438
ber01-VHDL13_DWPG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2595
ber01-VHDL13_DWPG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2509
ber01-VHDL13_DWPH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2885
ber01-VHDL13_DWPH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2622
ber01-VHDL13_DWSG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 3169
ber01-VHDL13_DWSG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3757
ber01-VHDL13_DWSG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 10:51:49 3628
ber01-VHDL17_DWOG_241200-2608241200-dsw--0-ia5 24-Aug-2026 11:52:54 3191
ber01-VHDL17_DWOG_251200-2608251200-dsw--0-ia5 25-Aug-2026 11:57:09 3227
swis2-VHDL20_DWEG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1117
swis2-VHDL20_DWEG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1115
swis2-VHDL20_DWEG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1458
swis2-VHDL20_DWEG_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:12 1536
swis2-VHDL20_DWEG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 783
swis2-VHDL20_DWEG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 805
swis2-VHDL20_DWEG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1212
swis2-VHDL20_DWEG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1252
swis2-VHDL20_DWEG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1373
swis2-VHDL20_DWEH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1122
swis2-VHDL20_DWEH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1120
swis2-VHDL20_DWEH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1457
swis2-VHDL20_DWEH_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:12 1444
swis2-VHDL20_DWEH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1000
swis2-VHDL20_DWEH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 1004
swis2-VHDL20_DWEH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1405
swis2-VHDL20_DWEH_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1794
swis2-VHDL20_DWEH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1889
swis2-VHDL20_DWEI_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1357
swis2-VHDL20_DWEI_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1355
swis2-VHDL20_DWEI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1699
swis2-VHDL20_DWEI_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:12 1802
swis2-VHDL20_DWEI_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1413
swis2-VHDL20_DWEI_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 1284
swis2-VHDL20_DWEI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1691
swis2-VHDL20_DWEI_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1982
swis2-VHDL20_DWEI_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1689
swis2-VHDL20_DWHG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:45:24 898
swis2-VHDL20_DWHG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:19 895
swis2-VHDL20_DWHG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:45:30 1034
swis2-VHDL20_DWHG_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:45:14 2433
swis2-VHDL20_DWHG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:46:28 1201
swis2-VHDL20_DWHG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 1197
swis2-VHDL20_DWHG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:48:26 1482
swis2-VHDL20_DWHG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:45:08 1695
swis2-VHDL20_DWHH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:45:24 900
swis2-VHDL20_DWHH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:19 900
swis2-VHDL20_DWHH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:45:30 958
swis2-VHDL20_DWHH_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:45:14 2043
swis2-VHDL20_DWHH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:46:28 1368
swis2-VHDL20_DWHH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 1378
swis2-VHDL20_DWHH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:48:26 1637
swis2-VHDL20_DWHH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:45:08 1838
swis2-VHDL20_DWLG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 749
swis2-VHDL20_DWLG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 744
swis2-VHDL20_DWLG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 915
swis2-VHDL20_DWLG_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:31:18 965
swis2-VHDL20_DWLG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 738
swis2-VHDL20_DWLG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 751
swis2-VHDL20_DWLG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1138
swis2-VHDL20_DWLG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1207
swis2-VHDL20_DWLH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 756
swis2-VHDL20_DWLH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 751
swis2-VHDL20_DWLH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1037
swis2-VHDL20_DWLH_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:31:19 1000
swis2-VHDL20_DWLH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 745
swis2-VHDL20_DWLH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 943
swis2-VHDL20_DWLH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1367
swis2-VHDL20_DWLH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1422
swis2-VHDL20_DWLI_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 751
swis2-VHDL20_DWLI_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 814
swis2-VHDL20_DWLI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1242
swis2-VHDL20_DWLI_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:31:19 1239
swis2-VHDL20_DWLI_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 837
swis2-VHDL20_DWLI_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 880
swis2-VHDL20_DWLI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1159
swis2-VHDL20_DWLI_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1423
swis2-VHDL20_DWMO_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1445
swis2-VHDL20_DWMO_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:05 1345
swis2-VHDL20_DWMO_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1424
swis2-VHDL20_DWMO_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:12 1391
swis2-VHDL20_DWMO_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1145
swis2-VHDL20_DWMO_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:05 1274
swis2-VHDL20_DWMO_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1590
swis2-VHDL20_DWMO_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1754
swis2-VHDL20_DWMP_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1328
swis2-VHDL20_DWMP_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:05 1227
swis2-VHDL20_DWMP_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1520
swis2-VHDL20_DWMP_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:12 1525
swis2-VHDL20_DWMP_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1150
swis2-VHDL20_DWMP_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:05 1278
swis2-VHDL20_DWMP_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1919
swis2-VHDL20_DWMP_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 2098
swis2-VHDL20_DWPG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 792
swis2-VHDL20_DWPG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 878
swis2-VHDL20_DWPG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1000
swis2-VHDL20_DWPG_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:31:19 931
swis2-VHDL20_DWPG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 845
swis2-VHDL20_DWPG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 855
swis2-VHDL20_DWPG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 835
swis2-VHDL20_DWPG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 935
swis2-VHDL20_DWPH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 881
swis2-VHDL20_DWPH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 897
swis2-VHDL20_DWPH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1025
swis2-VHDL20_DWPH_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:31:19 1263
swis2-VHDL20_DWPH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 864
swis2-VHDL20_DWPH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 847
swis2-VHDL20_DWPH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 996
swis2-VHDL20_DWPH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1030
swis2-VHDL20_DWSG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:16 1351
swis2-VHDL20_DWSG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:23 1210
swis2-VHDL20_DWSG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1403
swis2-VHDL20_DWSG_241800-2608241800-dsw--0-ia5 24-Aug-2026 18:30:07 1484
swis2-VHDL20_DWSG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1184
swis2-VHDL20_DWSG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:19 1351
swis2-VHDL20_DWSG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1864
swis2-VHDL20_DWSG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 10:51:49 1735
swis2-VHDL20_DWSG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1977
wst04-VHDL20_DWEG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 244196
wst04-VHDL20_DWEG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:13 244402
wst04-VHDL20_DWEG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 245290
wst04-VHDL20_DWEG_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:19 248643
wst04-VHDL20_DWEG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 246737
wst04-VHDL20_DWEG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 246325
wst04-VHDL20_DWEG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:14 247711
wst04-VHDL20_DWEG_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 247719
wst04-VHDL20_DWEG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 243620
wst04-VHDL20_DWEH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 241352
wst04-VHDL20_DWEH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:13 241811
wst04-VHDL20_DWEH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 242732
wst04-VHDL20_DWEH_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:19 244177
wst04-VHDL20_DWEH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 243643
wst04-VHDL20_DWEH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 243489
wst04-VHDL20_DWEH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:14 244697
wst04-VHDL20_DWEH_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 245235
wst04-VHDL20_DWEH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 243461
wst04-VHDL20_DWEI_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 355645
wst04-VHDL20_DWEI_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 355778
wst04-VHDL20_DWEI_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 356819
wst04-VHDL20_DWEI_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:22 360639
wst04-VHDL20_DWEI_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 359701
wst04-VHDL20_DWEI_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 359098
wst04-VHDL20_DWEI_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:18 360469
wst04-VHDL20_DWEI_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 360588
wst04-VHDL20_DWEI_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 354148
wst04-VHDL20_DWHG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:45:24 343826
wst04-VHDL20_DWHG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 343816
wst04-VHDL20_DWHG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:45:30 345223
wst04-VHDL20_DWHG_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:45:16 348659
wst04-VHDL20_DWHG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:46:28 346184
wst04-VHDL20_DWHG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 345961
wst04-VHDL20_DWHG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:48:26 347334
wst04-VHDL20_DWHG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:45:29 351933
wst04-VHDL20_DWHH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:45:24 338709
wst04-VHDL20_DWHH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 232374
wst04-VHDL20_DWHH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:45:30 339431
wst04-VHDL20_DWHH_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:45:16 338363
wst04-VHDL20_DWHH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:46:28 336863
wst04-VHDL20_DWHH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 231355
wst04-VHDL20_DWHH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:48:26 338213
wst04-VHDL20_DWHH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:45:29 344069
wst04-VHDL20_DWLG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 333583
wst04-VHDL20_DWLG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 332857
wst04-VHDL20_DWLG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 333377
wst04-VHDL20_DWLG_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:31:32 337548
wst04-VHDL20_DWLG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 336474
wst04-VHDL20_DWLG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 336534
wst04-VHDL20_DWLG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:48 337709
wst04-VHDL20_DWLG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 343014
wst04-VHDL20_DWLH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 337454
wst04-VHDL20_DWLH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 336724
wst04-VHDL20_DWLH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 337561
wst04-VHDL20_DWLH_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:31:32 332710
wst04-VHDL20_DWLH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 331557
wst04-VHDL20_DWLH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 332086
wst04-VHDL20_DWLH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 333766
wst04-VHDL20_DWLH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 344652
wst04-VHDL20_DWLI_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 339169
wst04-VHDL20_DWLI_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 338623
wst04-VHDL20_DWLI_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 384114
wst04-VHDL20_DWLI_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:31:32 342236
wst04-VHDL20_DWLI_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 340969
wst04-VHDL20_DWLI_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 340838
wst04-VHDL20_DWLI_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 385956
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wst04-VHDL20_DWMO_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 460666
wst04-VHDL20_DWMO_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:22 351672
wst04-VHDL20_DWMO_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 461175
wst04-VHDL20_DWMO_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 461130
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wst04-VHDL20_DWMO_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 360128
wst04-VHDL20_DWMP_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 571962
wst04-VHDL20_DWMP_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 571617
wst04-VHDL20_DWMP_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 461098
wst04-VHDL20_DWMP_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:22 470770
wst04-VHDL20_DWMP_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 578204
wst04-VHDL20_DWMP_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 578098
wst04-VHDL20_DWMP_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:24 471507
wst04-VHDL20_DWMP_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 480845
wst04-VHDL20_DWPG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 238744
wst04-VHDL20_DWPG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:33 340734
wst04-VHDL20_DWPG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 385341
wst04-VHDL20_DWPG_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:31:32 340617
wst04-VHDL20_DWPG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:39 239515
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wst04-VHDL20_DWPG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 384565
wst04-VHDL20_DWPG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 350913
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wst04-VHDL20_DWPH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 245265
wst04-VHDL20_DWPH_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:31:32 240077
wst04-VHDL20_DWPH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 238321
wst04-VHDL20_DWPH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:34 238131
wst04-VHDL20_DWPH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 239162
wst04-VHDL20_DWPH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 244886
wst04-VHDL20_DWSG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 351469
wst04-VHDL20_DWSG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:15 351233
wst04-VHDL20_DWSG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 351470
wst04-VHDL20_DWSG_241800-2608241800-omedes--0.pdf 24-Aug-2026 18:30:22 358944
wst04-VHDL20_DWSG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 358074
wst04-VHDL20_DWSG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 359628
wst04-VHDL20_DWSG_250800-2608250800-omedes--0.pdf 25-Aug-2026 10:51:59 360268
wst04-VHDL20_DWSG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 359967