Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Apr-2026 11:04:19 5781
FPDL13_DWMZ_180600 18-Apr-2026 10:53:39 3953
SXDL31_DWAV_170800 17-Apr-2026 07:39:19 11366
SXDL31_DWAV_171800 17-Apr-2026 16:33:02 5503
SXDL31_DWAV_180800 18-Apr-2026 09:13:49 13531
SXDL31_DWAV_181800 18-Apr-2026 17:11:29 8468
SXDL31_DWAV_LATEST 18-Apr-2026 17:11:29 8468
SXDL33_DWAV_170000 17-Apr-2026 10:17:29 7700
SXDL33_DWAV_180000 18-Apr-2026 10:22:23 9113
SXDL33_DWAV_LATEST 18-Apr-2026 10:22:23 9113
ber01-FWDL39_DWMS_171230-2604171230-dsw--0-ia5 17-Apr-2026 11:23:51 1526
ber01-FWDL39_DWMS_181230-2604181230-dsw--0-ia5 18-Apr-2026 12:00:12 1329
ber01-VHDL13_DWEH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:28:11 2268
ber01-VHDL13_DWEH_170400-2604170400-dsw--0-ia5 17-Apr-2026 04:58:12 2213
ber01-VHDL13_DWEH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:28:17 2641
ber01-VHDL13_DWEH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:28:17 2641
ber01-VHDL13_DWEH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:28:11 2872
ber01-VHDL13_DWEH_180400-2604180400-dsw--0-ia5 18-Apr-2026 04:58:12 2771
ber01-VHDL13_DWEH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:28:16 3052
ber01-VHDL13_DWEH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:28:17 2870
ber01-VHDL13_DWHG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:10 2176
ber01-VHDL13_DWHG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:12 2181
ber01-VHDL13_DWHG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2555
ber01-VHDL13_DWHG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2272
ber01-VHDL13_DWHG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2583
ber01-VHDL13_DWHG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:11 2550
ber01-VHDL13_DWHG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:07 3568
ber01-VHDL13_DWHG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 3243
ber01-VHDL13_DWHH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:10 2169
ber01-VHDL13_DWHH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:12 2174
ber01-VHDL13_DWHH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2433
ber01-VHDL13_DWHH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2310
ber01-VHDL13_DWHH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2498
ber01-VHDL13_DWHH_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:11 2457
ber01-VHDL13_DWHH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:07 3086
ber01-VHDL13_DWHH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2597
ber01-VHDL13_DWLG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 1970
ber01-VHDL13_DWLG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 2169
ber01-VHDL13_DWLG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2140
ber01-VHDL13_DWLG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:03 2007
ber01-VHDL13_DWLG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2075
ber01-VHDL13_DWLG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2676
ber01-VHDL13_DWLG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 3074
ber01-VHDL13_DWLG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2443
ber01-VHDL13_DWLH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 1907
ber01-VHDL13_DWLH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 1981
ber01-VHDL13_DWLH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2090
ber01-VHDL13_DWLH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:03 1954
ber01-VHDL13_DWLH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:13 2064
ber01-VHDL13_DWLH_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2709
ber01-VHDL13_DWLH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 2911
ber01-VHDL13_DWLH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2251
ber01-VHDL13_DWLI_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 1771
ber01-VHDL13_DWLI_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 1991
ber01-VHDL13_DWLI_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2027
ber01-VHDL13_DWLI_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:03 1899
ber01-VHDL13_DWLI_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2291
ber01-VHDL13_DWLI_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2720
ber01-VHDL13_DWLI_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 2935
ber01-VHDL13_DWLI_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2215
ber01-VHDL13_DWMG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 2372
ber01-VHDL13_DWMG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 2394
ber01-VHDL13_DWMG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2473
ber01-VHDL13_DWMG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2563
ber01-VHDL13_DWMG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2798
ber01-VHDL13_DWMG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2655
ber01-VHDL13_DWMG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:07 3360
ber01-VHDL13_DWMG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2993
ber01-VHDL13_DWMO_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 2357
ber01-VHDL13_DWMO_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 2357
ber01-VHDL13_DWMO_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:11 2680
ber01-VHDL13_DWMO_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2569
ber01-VHDL13_DWMO_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2879
ber01-VHDL13_DWMO_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2733
ber01-VHDL13_DWMO_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:07 2733
ber01-VHDL13_DWMO_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2788
ber01-VHDL13_DWMP_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 2366
ber01-VHDL13_DWMP_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 2366
ber01-VHDL13_DWMP_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:11 2280
ber01-VHDL13_DWMP_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2192
ber01-VHDL13_DWMP_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2467
ber01-VHDL13_DWMP_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2431
ber01-VHDL13_DWMP_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:07 2982
ber01-VHDL13_DWMP_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2790
ber01-VHDL13_DWOG_170300-2604170300-dsw--0-ia5 17-Apr-2026 03:00:20 2850
ber01-VHDL13_DWOG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 3765
ber01-VHDL13_DWOG_171700-2604171700-dsw--0-ia5 17-Apr-2026 18:00:02 3802
ber01-VHDL13_DWOG_180300-2604180300-dsw--0-ia5 18-Apr-2026 03:00:06 4331
ber01-VHDL13_DWOG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 4236
ber01-VHDL13_DWOG_181700-2604181700-dsw--0-ia5 18-Apr-2026 18:00:03 4541
ber01-VHDL13_DWOH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:28:11 2241
ber01-VHDL13_DWOH_170400-2604170400-dsw--0-ia5 17-Apr-2026 04:58:12 2123
ber01-VHDL13_DWOH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:28:13 2306
ber01-VHDL13_DWOH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:28:17 2717
ber01-VHDL13_DWOH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:28:11 2923
ber01-VHDL13_DWOH_180400-2604180400-dsw--0-ia5 18-Apr-2026 04:58:16 2883
ber01-VHDL13_DWOH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:28:12 3186
ber01-VHDL13_DWOH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:28:11 2994
ber01-VHDL13_DWOI_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:28:11 2234
ber01-VHDL13_DWOI_170400-2604170400-dsw--0-ia5 17-Apr-2026 04:58:16 2070
ber01-VHDL13_DWOI_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:28:13 2301
ber01-VHDL13_DWOI_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:28:11 2684
ber01-VHDL13_DWOI_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:28:17 2787
ber01-VHDL13_DWOI_180400-2604180400-dsw--0-ia5 18-Apr-2026 04:58:12 2657
ber01-VHDL13_DWOI_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:28:16 2687
ber01-VHDL13_DWOI_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:28:17 2472
ber01-VHDL13_DWON_170043-2604170043-dsw--0-ia5 17-Apr-2026 00:43:32 3051
ber01-VHDL13_DWON_170222-2604170222-dsw--0-ia5 17-Apr-2026 02:22:27 3051
ber01-VHDL13_DWON_170529-2604170529-dsw--0-ia5 17-Apr-2026 05:29:16 3475
ber01-VHDL13_DWON_170607-2604170607-dsw--0-ia5 17-Apr-2026 06:07:56 4026
ber01-VHDL13_DWON_171433-2604171433-dsw--0-ia5 17-Apr-2026 14:34:01 3739
ber01-VHDL13_DWON_171658-2604171658-dsw--0-ia5 17-Apr-2026 16:58:28 3736
ber01-VHDL13_DWON_171844-2604171844-dsw--0-ia5 17-Apr-2026 18:44:51 4195
ber01-VHDL13_DWON_172044-2604172044-dsw--0-ia5 17-Apr-2026 20:44:44 4194
ber01-VHDL13_DWON_172125-2604172125-dsw--0-ia5 17-Apr-2026 21:25:32 4198
ber01-VHDL13_DWON_180004-2604180004-dsw--0-ia5 18-Apr-2026 00:04:06 4468
ber01-VHDL13_DWON_180132-2604180132-dsw--0-ia5 18-Apr-2026 01:32:41 4429
ber01-VHDL13_DWON_180243-2604180243-dsw--0-ia5 18-Apr-2026 02:43:53 4429
ber01-VHDL13_DWON_180526-2604180526-dsw--0-ia5 18-Apr-2026 05:26:41 4841
ber01-VHDL13_DWON_180600-2604180600-dsw--0-ia5 18-Apr-2026 06:00:51 4810
ber01-VHDL13_DWON_180842-2604180842-dsw--0-ia5 18-Apr-2026 08:42:26 4810
ber01-VHDL13_DWON_180849-2604180849-dsw--0-ia5 18-Apr-2026 08:49:52 4810
ber01-VHDL13_DWON_181512-2604181512-dsw--0-ia5 18-Apr-2026 15:12:58 4134
ber01-VHDL13_DWON_181722-2604181722-dsw--0-ia5 18-Apr-2026 17:22:57 4107
ber01-VHDL13_DWON_181726-2604181726-dsw--0-ia5 18-Apr-2026 17:26:43 4107
ber01-VHDL13_DWON_182107-2604182107-dsw--0-ia5 18-Apr-2026 21:08:01 4107
ber01-VHDL13_DWPG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 1918
ber01-VHDL13_DWPG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 1641
ber01-VHDL13_DWPG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 1702
ber01-VHDL13_DWPG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:03 1674
ber01-VHDL13_DWPG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 1927
ber01-VHDL13_DWPG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2417
ber01-VHDL13_DWPG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 2784
ber01-VHDL13_DWPG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2128
ber01-VHDL13_DWPH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 2074
ber01-VHDL13_DWPH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:06 1911
ber01-VHDL13_DWPH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:11 1998
ber01-VHDL13_DWPH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:03 1924
ber01-VHDL13_DWPH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:12 2110
ber01-VHDL13_DWPH_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:07 2188
ber01-VHDL13_DWPH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 2596
ber01-VHDL13_DWPH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 1880
ber01-VHDL13_DWSG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:30:04 2381
ber01-VHDL13_DWSG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:16 2476
ber01-VHDL13_DWSG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:30:10 2475
ber01-VHDL13_DWSG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:30:08 2233
ber01-VHDL13_DWSG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:30:13 2490
ber01-VHDL13_DWSG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:17 2484
ber01-VHDL13_DWSG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:30:03 2951
ber01-VHDL13_DWSG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:30:08 2364
ber01-VHDL17_DWOG_171200-2604171200-dsw--0-ia5 17-Apr-2026 11:59:41 2398
ber01-VHDL17_DWOG_181200-2604181200-dsw--0-ia5 18-Apr-2026 11:37:18 2207
swis2-VHDL20_DWEG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2518
swis2-VHDL20_DWEG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:15:02 2440
swis2-VHDL20_DWEG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:06 2482
swis2-VHDL20_DWEG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:07 3040
swis2-VHDL20_DWEG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:09 3199
swis2-VHDL20_DWEG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:15:07 3203
swis2-VHDL20_DWEG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:01 3663
swis2-VHDL20_DWEG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 3320
swis2-VHDL20_DWEH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2590
swis2-VHDL20_DWEH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:15:02 2542
swis2-VHDL20_DWEH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:06 3141
swis2-VHDL20_DWEH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:07 2992
swis2-VHDL20_DWEH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:10 3193
swis2-VHDL20_DWEH_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:15:07 3103
swis2-VHDL20_DWEH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:07 3554
swis2-VHDL20_DWEH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 3224
swis2-VHDL20_DWEI_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2527
swis2-VHDL20_DWEI_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:15:02 2418
swis2-VHDL20_DWEI_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:06 2823
swis2-VHDL20_DWEI_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:07 3032
swis2-VHDL20_DWEI_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:09 3079
swis2-VHDL20_DWEI_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:15:07 3008
swis2-VHDL20_DWEI_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:01 3211
swis2-VHDL20_DWEI_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 2823
swis2-VHDL20_DWHG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2362
swis2-VHDL20_DWHG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:16 2364
swis2-VHDL20_DWHG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:02 3080
swis2-VHDL20_DWHG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:01 2455
swis2-VHDL20_DWHG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:09 2769
swis2-VHDL20_DWHG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:11 2733
swis2-VHDL20_DWHG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:01 4095
swis2-VHDL20_DWHG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 3426
swis2-VHDL20_DWHH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2355
swis2-VHDL20_DWHH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:16 2360
swis2-VHDL20_DWHH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:02 2970
swis2-VHDL20_DWHH_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:01 2496
swis2-VHDL20_DWHH_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:09 2684
swis2-VHDL20_DWHH_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:11 2643
swis2-VHDL20_DWHH_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:01 3625
swis2-VHDL20_DWHH_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 2783
swis2-VHDL20_DWLG_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2312
swis2-VHDL20_DWLG_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:12 2511
swis2-VHDL20_DWLG_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:06 2628
swis2-VHDL20_DWLG_171800-2604171800-dsw--0-ia5 17-Apr-2026 18:45:01 2349
swis2-VHDL20_DWLG_180200-2604180200-dsw--0-ia5 18-Apr-2026 02:45:09 2417
swis2-VHDL20_DWLG_180400-2604180400-dsw--0-ia5 18-Apr-2026 05:00:11 3018
swis2-VHDL20_DWLG_180800-2604180800-dsw--0-ia5 18-Apr-2026 08:45:01 3561
swis2-VHDL20_DWLG_181800-2604181800-dsw--0-ia5 18-Apr-2026 18:45:02 2785
swis2-VHDL20_DWLH_170200-2604170200-dsw--0-ia5 17-Apr-2026 02:45:12 2255
swis2-VHDL20_DWLH_170400-2604170400-dsw--0-ia5 17-Apr-2026 05:00:12 2330
swis2-VHDL20_DWLH_170800-2604170800-dsw--0-ia5 17-Apr-2026 08:45:06 2589
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