Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Sep-2026 13:51:54 2996
FPDL13_DWMZ_240600 24-Sep-2026 12:20:19 4791
SXDL31_DWAV_230800 23-Sep-2026 07:30:36 6674
SXDL31_DWAV_231800 23-Sep-2026 18:37:30 4215
SXDL31_DWAV_240800 24-Sep-2026 07:28:28 6541
SXDL31_DWAV_241800 24-Sep-2026 16:46:37 3715
SXDL31_DWAV_LATEST 24-Sep-2026 16:46:37 3715
SXDL33_DWAV_230000 23-Sep-2026 09:33:14 9800
SXDL33_DWAV_240000 24-Sep-2026 09:49:55 5823
SXDL33_DWAV_LATEST 24-Sep-2026 09:49:55 5823
ber01-FWDL39_DWMS_231200-2609231200-dsw--0-ia5 23-Sep-2026 11:19:29 2366
ber01-FWDL39_DWMS_241200-2609241200-dsw--0-ia5 24-Sep-2026 11:22:13 1691
ber01-VHDL13_DWEG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2931
ber01-VHDL13_DWEG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:28:14 3279
ber01-VHDL13_DWEH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2902
ber01-VHDL13_DWEH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:28:18 3322
ber01-VHDL13_DWEI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2619
ber01-VHDL13_DWEI_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:28:18 2626
ber01-VHDL13_DWHG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3276
ber01-VHDL13_DWHG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 3222
ber01-VHDL13_DWHH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3234
ber01-VHDL13_DWHH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2991
ber01-VHDL13_DWLG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2568
ber01-VHDL13_DWLG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2269
ber01-VHDL13_DWLH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2534
ber01-VHDL13_DWLH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2295
ber01-VHDL13_DWLI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2164
ber01-VHDL13_DWLI_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2064
ber01-VHDL13_DWMO_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3363
ber01-VHDL13_DWMO_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 3219
ber01-VHDL13_DWMP_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3342
ber01-VHDL13_DWMP_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 3488
ber01-VHDL13_DWOG_230300-2609230300-dsw--0-ia5 23-Sep-2026 03:00:36 4597
ber01-VHDL13_DWOG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 4281
ber01-VHDL13_DWOG_231700-2609231700-dsw--0-ia5 23-Sep-2026 18:00:03 3771
ber01-VHDL13_DWOG_240300-2609240300-dsw--0-ia5 24-Sep-2026 03:00:10 3763
ber01-VHDL13_DWOG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 3728
ber01-VHDL13_DWOG_241700-2609241700-dsw--0-ia5 24-Sep-2026 18:00:06 2857
ber01-VHDL13_DWON_230017-2609230017-dsw--0-ia5 23-Sep-2026 00:17:29 4559
ber01-VHDL13_DWON_230105-2609230105-dsw--0-ia5 23-Sep-2026 01:06:06 4559
ber01-VHDL13_DWON_230348-2609230348-dsw--0-ia5 23-Sep-2026 03:48:23 4559
ber01-VHDL13_DWON_230529-2609230529-dsw--0-ia5 23-Sep-2026 05:29:51 4169
ber01-VHDL13_DWON_230556-2609230556-dsw--0-ia5 23-Sep-2026 05:56:28 4165
ber01-VHDL13_DWON_230629-2609230629-dsw--0-ia5 23-Sep-2026 06:29:54 4165
ber01-VHDL13_DWON_230630-2609230630-dsw--0-ia5 23-Sep-2026 06:30:14 4165
ber01-VHDL13_DWON_230758-2609230758-dsw--0-ia5 23-Sep-2026 07:58:29 4215
ber01-VHDL13_DWON_230808-2609230808-dsw--0-ia5 23-Sep-2026 08:08:48 4215
ber01-VHDL13_DWON_231432-2609231432-dsw--0-ia5 23-Sep-2026 14:33:18 4273
ber01-VHDL13_DWON_231456-2609231456-dsw--0-ia5 23-Sep-2026 14:58:02 4273
ber01-VHDL13_DWON_231729-2609231729-dsw--0-ia5 23-Sep-2026 17:30:09 3422
ber01-VHDL13_DWON_231838-2609231838-dsw--0-ia5 23-Sep-2026 18:38:36 3409
ber01-VHDL13_DWON_231943-2609231943-dsw--0-ia5 23-Sep-2026 19:43:44 3409
ber01-VHDL13_DWON_240003-2609240003-dsw--0-ia5 24-Sep-2026 00:03:58 3932
ber01-VHDL13_DWON_240201-2609240201-dsw--0-ia5 24-Sep-2026 02:01:49 3982
ber01-VHDL13_DWON_240326-2609240326-dsw--0-ia5 24-Sep-2026 03:27:03 3982
ber01-VHDL13_DWON_240525-2609240525-dsw--0-ia5 24-Sep-2026 05:25:28 4104
ber01-VHDL13_DWON_240611-2609240611-dsw--0-ia5 24-Sep-2026 06:11:14 4066
ber01-VHDL13_DWON_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:00:38 4066
ber01-VHDL13_DWON_241456-2609241456-dsw--0-ia5 24-Sep-2026 14:58:02 3755
ber01-VHDL13_DWON_241654-2609241654-dsw--0-ia5 24-Sep-2026 16:54:48 3122
ber01-VHDL13_DWON_242030-2609242030-dsw--0-ia5 24-Sep-2026 20:30:44 3118
ber01-VHDL13_DWPG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2083
ber01-VHDL13_DWPG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2077
ber01-VHDL13_DWPH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2713
ber01-VHDL13_DWPH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2366
ber01-VHDL13_DWSG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 2266
ber01-VHDL13_DWSG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 2557
ber01-VHDL17_DWOG_231200-2609231200-dsw--0-ia5 23-Sep-2026 11:41:04 3707
ber01-VHDL17_DWOG_241200-2609241200-dsw--0-ia5 24-Sep-2026 11:46:45 2492
swis2-VHDL20_DWEG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 1073
swis2-VHDL20_DWEG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 1057
swis2-VHDL20_DWEG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1279
swis2-VHDL20_DWEG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:03 1210
swis2-VHDL20_DWEG_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 970
swis2-VHDL20_DWEG_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:01:23 1011
swis2-VHDL20_DWEG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 1406
swis2-VHDL20_DWEG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1113
swis2-VHDL20_DWEH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 1321
swis2-VHDL20_DWEH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 1305
swis2-VHDL20_DWEH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1251
swis2-VHDL20_DWEH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1242
swis2-VHDL20_DWEH_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 989
swis2-VHDL20_DWEH_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:01:23 1030
swis2-VHDL20_DWEH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 1404
swis2-VHDL20_DWEH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1128
swis2-VHDL20_DWEI_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 882
swis2-VHDL20_DWEI_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 882
swis2-VHDL20_DWEI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1090
swis2-VHDL20_DWEI_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:03 1027
swis2-VHDL20_DWEI_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 783
swis2-VHDL20_DWEI_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:01:23 824
swis2-VHDL20_DWEI_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 989
swis2-VHDL20_DWEI_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 967
swis2-VHDL20_DWHG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:48:13 1399
swis2-VHDL20_DWHG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:10 1307
swis2-VHDL20_DWHG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:45:54 1547
swis2-VHDL20_DWHG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:45:19 1645
swis2-VHDL20_DWHG_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:47:22 1461
swis2-VHDL20_DWHG_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 1195
swis2-VHDL20_DWHG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:45:24 1398
swis2-VHDL20_DWHG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:45:22 1262
swis2-VHDL20_DWHG_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:06 1162
swis2-VHDL20_DWHH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:48:13 1567
swis2-VHDL20_DWHH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1449
swis2-VHDL20_DWHH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:45:54 1766
swis2-VHDL20_DWHH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:45:19 1902
swis2-VHDL20_DWHH_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:47:22 1649
swis2-VHDL20_DWHH_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 1383
swis2-VHDL20_DWHH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:45:24 1502
swis2-VHDL20_DWHH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:45:22 1116
swis2-VHDL20_DWHH_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:29 1011
swis2-VHDL20_DWLG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1133
swis2-VHDL20_DWLG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1104
swis2-VHDL20_DWLG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1214
swis2-VHDL20_DWLG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1091
swis2-VHDL20_DWLG_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:30 845
swis2-VHDL20_DWLG_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 1033
swis2-VHDL20_DWLG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:32 1182
swis2-VHDL20_DWLG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1032
swis2-VHDL20_DWLH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1264
swis2-VHDL20_DWLH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1200
swis2-VHDL20_DWLH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1310
swis2-VHDL20_DWLH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1141
swis2-VHDL20_DWLH_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:31 884
swis2-VHDL20_DWLH_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 951
swis2-VHDL20_DWLH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:32 1033
swis2-VHDL20_DWLH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 972
swis2-VHDL20_DWLI_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1255
swis2-VHDL20_DWLI_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 848
swis2-VHDL20_DWLI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 958
swis2-VHDL20_DWLI_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 898
swis2-VHDL20_DWLI_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:31 778
swis2-VHDL20_DWLI_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 909
swis2-VHDL20_DWLI_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:32 983
swis2-VHDL20_DWLI_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 969
swis2-VHDL20_DWMO_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 1168
swis2-VHDL20_DWMO_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:03 1249
swis2-VHDL20_DWMO_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 1598
swis2-VHDL20_DWMO_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1466
swis2-VHDL20_DWMO_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 1360
swis2-VHDL20_DWMO_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:03 1359
swis2-VHDL20_DWMO_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 1494
swis2-VHDL20_DWMO_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1211
swis2-VHDL20_DWMP_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 1414
swis2-VHDL20_DWMP_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:03 1494
swis2-VHDL20_DWMP_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 1596
swis2-VHDL20_DWMP_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1735
swis2-VHDL20_DWMP_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 1608
swis2-VHDL20_DWMP_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:03 1743
swis2-VHDL20_DWMP_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 1850
swis2-VHDL20_DWMP_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1254
swis2-VHDL20_DWPG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 973
swis2-VHDL20_DWPG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 891
swis2-VHDL20_DWPG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1005
swis2-VHDL20_DWPG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1039
swis2-VHDL20_DWPG_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:30 799
swis2-VHDL20_DWPG_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 913
swis2-VHDL20_DWPG_240400_COR-2609240400-dsw--0-ia5 24-Sep-2026 05:09:08 917
swis2-VHDL20_DWPG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:32 1060
swis2-VHDL20_DWPG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1046
swis2-VHDL20_DWPH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1213
swis2-VHDL20_DWPH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1103
swis2-VHDL20_DWPH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1213
swis2-VHDL20_DWPH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1153
swis2-VHDL20_DWPH_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:30 942
swis2-VHDL20_DWPH_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:14 1003
swis2-VHDL20_DWPH_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:32 1152
swis2-VHDL20_DWPH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1048
swis2-VHDL20_DWSG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 934
swis2-VHDL20_DWSG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1086
swis2-VHDL20_DWSG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 977
swis2-VHDL20_DWSG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1246
swis2-VHDL20_DWSG_240200-2609240200-dsw--0-ia5 24-Sep-2026 02:30:04 1124
swis2-VHDL20_DWSG_240400-2609240400-dsw--0-ia5 24-Sep-2026 05:00:18 1165
swis2-VHDL20_DWSG_240800-2609240800-dsw--0-ia5 24-Sep-2026 08:30:09 1232
swis2-VHDL20_DWSG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1053
wst04-VHDL20_DWEG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 241557
wst04-VHDL20_DWEG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 241394
wst04-VHDL20_DWEG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 242227
wst04-VHDL20_DWEG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 242877
wst04-VHDL20_DWEG_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:21 241678
wst04-VHDL20_DWEG_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:14 241756
wst04-VHDL20_DWEG_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:20 243602
wst04-VHDL20_DWEG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 242333
wst04-VHDL20_DWEH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 235573
wst04-VHDL20_DWEH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 235401
wst04-VHDL20_DWEH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 235710
wst04-VHDL20_DWEH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:13 235291
wst04-VHDL20_DWEH_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:21 234385
wst04-VHDL20_DWEH_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:14 234669
wst04-VHDL20_DWEH_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:20 236531
wst04-VHDL20_DWEH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 235220
wst04-VHDL20_DWEI_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 346755
wst04-VHDL20_DWEI_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:20 346519
wst04-VHDL20_DWEI_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 346697
wst04-VHDL20_DWEI_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 347158
wst04-VHDL20_DWEI_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:30 346416
wst04-VHDL20_DWEI_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:20 346440
wst04-VHDL20_DWEI_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:20 346658
wst04-VHDL20_DWEI_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 346768
wst04-VHDL20_DWHG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:48:14 349085
wst04-VHDL20_DWHG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 348689
wst04-VHDL20_DWHG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:45:54 350442
wst04-VHDL20_DWHG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:45:19 349964
wst04-VHDL20_DWHG_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:47:22 349474
wst04-VHDL20_DWHG_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:18 348663
wst04-VHDL20_DWHG_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:45:25 349314
wst04-VHDL20_DWHG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:45:22 347754
wst04-VHDL20_DWHH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:48:13 335480
wst04-VHDL20_DWHH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 230956
wst04-VHDL20_DWHH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:45:54 336318
wst04-VHDL20_DWHH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:45:19 336288
wst04-VHDL20_DWHH_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:47:22 335357
wst04-VHDL20_DWHH_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:18 230610
wst04-VHDL20_DWHH_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:45:24 334601
wst04-VHDL20_DWHH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:45:22 332929
wst04-VHDL20_DWLG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 333983
wst04-VHDL20_DWLG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 333781
wst04-VHDL20_DWLG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 333954
wst04-VHDL20_DWLG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 334185
wst04-VHDL20_DWLG_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:31 333726
wst04-VHDL20_DWLG_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:44 334349
wst04-VHDL20_DWLG_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:56 334584
wst04-VHDL20_DWLG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 333054
wst04-VHDL20_DWLH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 337832
wst04-VHDL20_DWLH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 337841
wst04-VHDL20_DWLH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 338036
wst04-VHDL20_DWLH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 338171
wst04-VHDL20_DWLH_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:31 337759
wst04-VHDL20_DWLH_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:44 337870
wst04-VHDL20_DWLH_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:51 338093
wst04-VHDL20_DWLH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 337005
wst04-VHDL20_DWLI_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 339265
wst04-VHDL20_DWLI_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 338244
wst04-VHDL20_DWLI_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 383053
wst04-VHDL20_DWLI_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 338729
wst04-VHDL20_DWLI_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:40 338706
wst04-VHDL20_DWLI_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:44 338883
wst04-VHDL20_DWLI_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:56 383653
wst04-VHDL20_DWLI_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 338031
wst04-VHDL20_DWMO_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:17 456039
wst04-VHDL20_DWMO_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 456301
wst04-VHDL20_DWMO_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 456861
wst04-VHDL20_DWMO_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 354421
wst04-VHDL20_DWMO_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:21 456408
wst04-VHDL20_DWMO_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:14 456369
wst04-VHDL20_DWMO_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:20 456575
wst04-VHDL20_DWMO_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 354194
wst04-VHDL20_DWMP_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:17 563512
wst04-VHDL20_DWMP_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:20 563777
wst04-VHDL20_DWMP_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 461555
wst04-VHDL20_DWMP_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 461462
wst04-VHDL20_DWMP_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:31 563818
wst04-VHDL20_DWMP_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:18 564391
wst04-VHDL20_DWMP_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:32 462952
wst04-VHDL20_DWMP_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 461094
wst04-VHDL20_DWPG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:34 244085
wst04-VHDL20_DWPG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:34 347730
wst04-VHDL20_DWPG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:53 392322
wst04-VHDL20_DWPG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 348567
wst04-VHDL20_DWPG_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:31 244510
wst04-VHDL20_DWPG_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:34 348292
wst04-VHDL20_DWPG_240400_COR-2609240400-omedes-..> 24-Sep-2026 05:08:54 348293
wst04-VHDL20_DWPG_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:51 393061
wst04-VHDL20_DWPG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:28 347451
wst04-VHDL20_DWPH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 243788
wst04-VHDL20_DWPH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:34 243560
wst04-VHDL20_DWPH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 243671
wst04-VHDL20_DWPH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 243501
wst04-VHDL20_DWPH_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:31 243172
wst04-VHDL20_DWPH_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:34 243699
wst04-VHDL20_DWPH_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:51 243946
wst04-VHDL20_DWPH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 242383
wst04-VHDL20_DWSG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:15 347625
wst04-VHDL20_DWSG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 347599
wst04-VHDL20_DWSG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 346540
wst04-VHDL20_DWSG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:13 347477
wst04-VHDL20_DWSG_240200-2609240200-omedes--0.pdf 24-Sep-2026 02:30:21 347211
wst04-VHDL20_DWSG_240400-2609240400-omedes--0.pdf 24-Sep-2026 05:00:14 347590
wst04-VHDL20_DWSG_240800-2609240800-omedes--0.pdf 24-Sep-2026 08:30:20 347806
wst04-VHDL20_DWSG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 347685