Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Nov-2025 14:53:33 3715
FPDL13_DWMZ_200600 20-Nov-2025 14:31:21 6572
SXDL31_DWAV_181800 18-Nov-2025 17:48:05 5412
SXDL31_DWAV_190800 19-Nov-2025 09:18:39 10784
SXDL31_DWAV_191800 19-Nov-2025 17:57:25 8196
SXDL31_DWAV_200800 20-Nov-2025 08:12:55 15921
SXDL31_DWAV_201800 20-Nov-2025 16:04:35 6278
SXDL31_DWAV_LATEST 20-Nov-2025 16:04:35 6278
SXDL33_DWAV_190000 19-Nov-2025 10:33:08 16359
SXDL33_DWAV_200000 20-Nov-2025 11:10:34 11173
SXDL33_DWAV_LATEST 20-Nov-2025 11:10:34 11173
ber01-FWDL39_DWMS_191230-2511191230-dsw--0-ia5 19-Nov-2025 12:35:34 2043
ber01-FWDL39_DWMS_201230-2511201230-dsw--0-ia5 20-Nov-2025 13:14:51 1835
ber01-VHDL13_DWEH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:16 3631
ber01-VHDL13_DWEH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:28:12 3379
ber01-VHDL13_DWEH_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:59 3383
ber01-VHDL13_DWEH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:28:11 3015
ber01-VHDL13_DWEH_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:58:17 3048
ber01-VHDL13_DWEH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:28:17 3260
ber01-VHDL13_DWEH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:28:17 3342
ber01-VHDL13_DWEH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:28:12 3447
ber01-VHDL13_DWEH_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:58:16 3520
ber01-VHDL13_DWEH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:28:18 3857
ber01-VHDL13_DWHG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 4090
ber01-VHDL13_DWHG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:06 3840
ber01-VHDL13_DWHG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:07 3840
ber01-VHDL13_DWHG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:08 3961
ber01-VHDL13_DWHG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:09 3912
ber01-VHDL13_DWHG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 4188
ber01-VHDL13_DWHG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:07 4187
ber01-VHDL13_DWHG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:08 4393
ber01-VHDL13_DWHH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 3364
ber01-VHDL13_DWHH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:06 3201
ber01-VHDL13_DWHH_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:07 3217
ber01-VHDL13_DWHH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:08 3224
ber01-VHDL13_DWHH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:09 3445
ber01-VHDL13_DWHH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 4107
ber01-VHDL13_DWHH_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:07 4107
ber01-VHDL13_DWHH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:08 4017
ber01-VHDL13_DWLG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 2250
ber01-VHDL13_DWLG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:06 3237
ber01-VHDL13_DWLG_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:59:56 3314
ber01-VHDL13_DWLG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:03 3311
ber01-VHDL13_DWLG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 2460
ber01-VHDL13_DWLG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 2450
ber01-VHDL13_DWLG_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:59:56 2469
ber01-VHDL13_DWLG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 2400
ber01-VHDL13_DWLH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 2687
ber01-VHDL13_DWLH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:06 2785
ber01-VHDL13_DWLH_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:59:56 2696
ber01-VHDL13_DWLH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:03 2696
ber01-VHDL13_DWLH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 2464
ber01-VHDL13_DWLH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 2489
ber01-VHDL13_DWLH_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:59:56 2521
ber01-VHDL13_DWLH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 2369
ber01-VHDL13_DWLI_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 2368
ber01-VHDL13_DWLI_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:06 3146
ber01-VHDL13_DWLI_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:59:56 3002
ber01-VHDL13_DWLI_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:03 2999
ber01-VHDL13_DWLI_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 2677
ber01-VHDL13_DWLI_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 2622
ber01-VHDL13_DWLI_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:59:56 2660
ber01-VHDL13_DWLI_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 2578
ber01-VHDL13_DWMG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:01 3011
ber01-VHDL13_DWMG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:02 3497
ber01-VHDL13_DWMG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:02 3497
ber01-VHDL13_DWMG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:08 3676
ber01-VHDL13_DWMG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 3749
ber01-VHDL13_DWMG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 3553
ber01-VHDL13_DWMG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:03 3553
ber01-VHDL13_DWMG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:08 3486
ber01-VHDL13_DWMO_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:01 3028
ber01-VHDL13_DWMO_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:02 3441
ber01-VHDL13_DWMO_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:02 3441
ber01-VHDL13_DWMO_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:08 3441
ber01-VHDL13_DWMO_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 2646
ber01-VHDL13_DWMO_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 2929
ber01-VHDL13_DWMO_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:03 2929
ber01-VHDL13_DWMO_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:08 2876
ber01-VHDL13_DWMP_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:01 2267
ber01-VHDL13_DWMP_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:02 3042
ber01-VHDL13_DWMP_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:02 3042
ber01-VHDL13_DWMP_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:08 3042
ber01-VHDL13_DWMP_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 3306
ber01-VHDL13_DWMP_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:09 3379
ber01-VHDL13_DWMP_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:03 3379
ber01-VHDL13_DWMP_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:08 3207
ber01-VHDL13_DWOG_181700-2511181700-dsw--0-ia5 18-Nov-2025 19:00:01 4639
ber01-VHDL13_DWOG_190300-2511190300-dsw--0-ia5 19-Nov-2025 04:00:02 5747
ber01-VHDL13_DWOG_190800-2511190800-dsw--0-ia5 19-Nov-2025 10:15:00 5899
ber01-VHDL13_DWOG_191700-2511191700-dsw--0-ia5 19-Nov-2025 19:00:01 5855
ber01-VHDL13_DWOG_200300-2511200300-dsw--0-ia5 20-Nov-2025 04:00:07 6315
ber01-VHDL13_DWOG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 6155
ber01-VHDL13_DWOH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:16 3255
ber01-VHDL13_DWOH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:28:16 2991
ber01-VHDL13_DWOH_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:59 3179
ber01-VHDL13_DWOH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:28:11 2989
ber01-VHDL13_DWOH_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:58:11 3000
ber01-VHDL13_DWOH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:28:17 3211
ber01-VHDL13_DWOH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:28:11 2741
ber01-VHDL13_DWOH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:28:12 2960
ber01-VHDL13_DWOH_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:58:12 3171
ber01-VHDL13_DWOH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:28:18 3392
ber01-VHDL13_DWOI_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:11 2907
ber01-VHDL13_DWOI_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:28:12 2868
ber01-VHDL13_DWOI_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:59 3050
ber01-VHDL13_DWOI_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:28:11 2917
ber01-VHDL13_DWOI_190400-2511190400-dsw--0-ia5 19-Nov-2025 05:58:17 2896
ber01-VHDL13_DWOI_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:28:11 3274
ber01-VHDL13_DWOI_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:28:11 2725
ber01-VHDL13_DWOI_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:28:12 2831
ber01-VHDL13_DWOI_200400-2511200400-dsw--0-ia5 20-Nov-2025 05:58:16 2959
ber01-VHDL13_DWOI_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:28:11 3384
ber01-VHDL13_DWON_181755-2511181755-dsw--0-ia5 18-Nov-2025 17:55:56 3952
ber01-VHDL13_DWON_182233-2511182233-dsw--0-ia5 18-Nov-2025 22:33:11 3920
ber01-VHDL13_DWON_190000-2511190000-dsw--0-ia5 19-Nov-2025 00:00:37 4582
ber01-VHDL13_DWON_190122-2511190122-dsw--0-ia5 19-Nov-2025 01:22:37 4582
ber01-VHDL13_DWON_190629-2511190629-dsw--0-ia5 19-Nov-2025 06:29:52 4725
ber01-VHDL13_DWON_190718-2511190718-dsw--0-ia5 19-Nov-2025 07:18:26 4722
ber01-VHDL13_DWON_190728-2511190728-dsw--0-ia5 19-Nov-2025 07:28:41 4834
ber01-VHDL13_DWON_190824-2511190824-dsw--0-ia5 19-Nov-2025 08:24:41 5038
ber01-VHDL13_DWON_191201-2511191201-dsw--0-ia5 19-Nov-2025 12:01:52 5043
ber01-VHDL13_DWON_191614-2511191614-dsw--0-ia5 19-Nov-2025 16:14:11 4647
ber01-VHDL13_DWON_191814-2511191814-dsw--0-ia5 19-Nov-2025 18:14:57 4571
ber01-VHDL13_DWON_200121-2511200121-dsw--0-ia5 20-Nov-2025 01:21:16 4638
ber01-VHDL13_DWON_200628-2511200628-dsw--0-ia5 20-Nov-2025 06:29:01 5130
ber01-VHDL13_DWON_200732-2511200732-dsw--0-ia5 20-Nov-2025 07:32:47 5130
ber01-VHDL13_DWON_200923-2511200923-dsw--0-ia5 20-Nov-2025 09:23:42 5130
ber01-VHDL13_DWON_201203-2511201203-dsw--0-ia5 20-Nov-2025 12:03:47 5011
ber01-VHDL13_DWON_201530-2511201530-dsw--0-ia5 20-Nov-2025 15:30:18 4215
ber01-VHDL13_DWPG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:01 1984
ber01-VHDL13_DWPG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:02 2491
ber01-VHDL13_DWPG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:02 2492
ber01-VHDL13_DWPG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:03 2389
ber01-VHDL13_DWPG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 1969
ber01-VHDL13_DWPG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:01 2072
ber01-VHDL13_DWPG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:03 2059
ber01-VHDL13_DWPG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 1938
ber01-VHDL13_DWPH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:01 2487
ber01-VHDL13_DWPH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:02 3114
ber01-VHDL13_DWPH_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:02 3114
ber01-VHDL13_DWPH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:03 2691
ber01-VHDL13_DWPH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:02 2578
ber01-VHDL13_DWPH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:01 3003
ber01-VHDL13_DWPH_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:03 2966
ber01-VHDL13_DWPH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 2807
ber01-VHDL13_DWSG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:30:06 3856
ber01-VHDL13_DWSG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:30:00 3927
ber01-VHDL13_DWSG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:07 3988
ber01-VHDL13_DWSG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:30:01 3978
ber01-VHDL13_DWSG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:30:06 4039
ber01-VHDL13_DWSG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:30:01 4318
ber01-VHDL13_DWSG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:07 3941
ber01-VHDL13_DWSG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:30:02 3577
ber01-VHDL17_DWOG_191200-2511191200-dsw--0-ia5 19-Nov-2025 11:11:11 3614
ber01-VHDL17_DWOG_201200-2511201200-dsw--0-ia5 20-Nov-2025 12:56:01 3842
swis2-VHDL20_DWEG_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3434
swis2-VHDL20_DWEG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:45:03 3576
swis2-VHDL20_DWEG_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:41 3364
swis2-VHDL20_DWEG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 3606
swis2-VHDL20_DWEG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:15:02 3710
swis2-VHDL20_DWEG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:07 4241
swis2-VHDL20_DWEG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 3347
swis2-VHDL20_DWEG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:07 3479
swis2-VHDL20_DWEG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:15:02 3618
swis2-VHDL20_DWEG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:45:06 4015
swis2-VHDL20_DWEH_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3809
swis2-VHDL20_DWEH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:45:03 3993
swis2-VHDL20_DWEH_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:41 3584
swis2-VHDL20_DWEH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 3595
swis2-VHDL20_DWEH_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:15:02 3643
swis2-VHDL20_DWEH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:07 4265
swis2-VHDL20_DWEH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 4026
swis2-VHDL20_DWEH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:07 4044
swis2-VHDL20_DWEH_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:15:07 3995
swis2-VHDL20_DWEH_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:45:06 4519
swis2-VHDL20_DWEI_180800_COR-2511180800-dsw--0-ia5 18-Nov-2025 16:56:07 3086
swis2-VHDL20_DWEI_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:45:03 3504
swis2-VHDL20_DWEI_181800_COR-2511181800-dsw--0-ia5 18-Nov-2025 20:36:41 3235
swis2-VHDL20_DWEI_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 3578
swis2-VHDL20_DWEI_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:15:02 3603
swis2-VHDL20_DWEI_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:07 4350
swis2-VHDL20_DWEI_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 3355
swis2-VHDL20_DWEI_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:07 3237
swis2-VHDL20_DWEI_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:15:07 3437
swis2-VHDL20_DWEI_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:45:06 4054
swis2-VHDL20_DWHG_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:45:03 4273
swis2-VHDL20_DWHG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 4026
swis2-VHDL20_DWHG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:07 4023
swis2-VHDL20_DWHG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:03 4596
swis2-VHDL20_DWHG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 4095
swis2-VHDL20_DWHG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:01 4374
swis2-VHDL20_DWHG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:07 4370
swis2-VHDL20_DWHG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:45:02 4957
swis2-VHDL20_DWHH_181800-2511181800-dsw--0-ia5 18-Nov-2025 19:45:03 3550
swis2-VHDL20_DWHH_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 3387
swis2-VHDL20_DWHH_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:00:07 3403
swis2-VHDL20_DWHH_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:03 3849
swis2-VHDL20_DWHH_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 3631
swis2-VHDL20_DWHH_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:01 4293
swis2-VHDL20_DWHH_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:00:11 4293
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swis2-VHDL20_DWSG_190200-2511190200-dsw--0-ia5 19-Nov-2025 03:45:08 4451
swis2-VHDL20_DWSG_190400-2511190400-dsw--0-ia5 19-Nov-2025 06:15:00 4381
swis2-VHDL20_DWSG_190800-2511190800-dsw--0-ia5 19-Nov-2025 09:45:03 4616
swis2-VHDL20_DWSG_191300-2511191300-dsw--0-ia5 19-Nov-2025 14:45:11 4381
swis2-VHDL20_DWSG_191800-2511191800-dsw--0-ia5 19-Nov-2025 19:45:04 4598
swis2-VHDL20_DWSG_200200-2511200200-dsw--0-ia5 20-Nov-2025 03:45:07 4866
swis2-VHDL20_DWSG_200400-2511200400-dsw--0-ia5 20-Nov-2025 06:15:02 4412
swis2-VHDL20_DWSG_200800-2511200800-dsw--0-ia5 20-Nov-2025 09:45:02 4184
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wst04-VHDL20_DWEG_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:11 230304
wst04-VHDL20_DWEG_181800-2511181800-omedes--0.pdf 18-Nov-2025 19:45:17 231035
wst04-VHDL20_DWEG_181800_COR-2511181800-omedes-..> 18-Nov-2025 20:36:59 230149
wst04-VHDL20_DWEG_190200-2511190200-omedes--0.pdf 19-Nov-2025 03:45:16 231982
wst04-VHDL20_DWEG_190400-2511190400-omedes--0.pdf 19-Nov-2025 06:15:20 230903
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wst04-VHDL20_DWEG_191800-2511191800-omedes--0.pdf 19-Nov-2025 19:45:18 232698
wst04-VHDL20_DWEG_200200-2511200200-omedes--0.pdf 20-Nov-2025 03:45:21 232453
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wst04-VHDL20_DWEH_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:16 234080
wst04-VHDL20_DWEH_181800-2511181800-omedes--0.pdf 18-Nov-2025 19:45:17 235053
wst04-VHDL20_DWEH_181800_COR-2511181800-omedes-..> 18-Nov-2025 20:36:59 233541
wst04-VHDL20_DWEH_190200-2511190200-omedes--0.pdf 19-Nov-2025 03:45:10 235162
wst04-VHDL20_DWEH_190400-2511190400-omedes--0.pdf 19-Nov-2025 06:15:20 234630
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wst04-VHDL20_DWEH_191800-2511191800-omedes--0.pdf 19-Nov-2025 19:45:18 232621
wst04-VHDL20_DWEH_200200-2511200200-omedes--0.pdf 20-Nov-2025 03:45:21 232780
wst04-VHDL20_DWEH_200400-2511200400-omedes--0.pdf 20-Nov-2025 06:15:27 232003
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wst04-VHDL20_DWEI_180800_COR-2511180800-omedes-..> 18-Nov-2025 16:56:16 318311
wst04-VHDL20_DWEI_181800-2511181800-omedes--0.pdf 18-Nov-2025 19:45:21 318693
wst04-VHDL20_DWEI_181800_COR-2511181800-omedes-..> 18-Nov-2025 20:36:59 317777
wst04-VHDL20_DWEI_190200-2511190200-omedes--0.pdf 19-Nov-2025 03:45:16 319206
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wst04-VHDL20_DWSG_200400-2511200400-omedes--0.pdf 20-Nov-2025 06:15:17 335199
wst04-VHDL20_DWSG_200800-2511200800-omedes--0.pdf 20-Nov-2025 09:45:12 322630
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