Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Aug-2026 10:17:29 3483
FPDL13_DWMZ_230600 23-Aug-2026 11:30:08 6653
SXDL31_DWAV_211800 21-Aug-2026 17:00:29 8467
SXDL31_DWAV_220800 22-Aug-2026 06:59:48 6837
SXDL31_DWAV_221800 22-Aug-2026 16:42:34 5571
SXDL31_DWAV_230800 23-Aug-2026 07:11:18 6834
SXDL31_DWAV_LATEST 23-Aug-2026 07:11:18 6834
SXDL33_DWAV_220000 22-Aug-2026 09:27:29 7174
SXDL33_DWAV_230000 23-Aug-2026 10:08:24 7782
SXDL33_DWAV_LATEST 23-Aug-2026 10:08:24 7782
ber01-FWDL39_DWMS_221200-2608221200-dsw--0-ia5 22-Aug-2026 11:54:01 1539
ber01-FWDL39_DWMS_231200-2608231200-dsw--0-ia5 23-Aug-2026 10:49:39 1282
ber01-VHDL13_DWEG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 2926
ber01-VHDL13_DWEG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:13 2738
ber01-VHDL13_DWEH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 3039
ber01-VHDL13_DWEH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:19 2826
ber01-VHDL13_DWEI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 2817
ber01-VHDL13_DWEI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:19 2868
ber01-VHDL13_DWHG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 3592
ber01-VHDL13_DWHG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3009
ber01-VHDL13_DWHH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 3301
ber01-VHDL13_DWHH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3234
ber01-VHDL13_DWLG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2393
ber01-VHDL13_DWLG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1968
ber01-VHDL13_DWLH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2321
ber01-VHDL13_DWLH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2100
ber01-VHDL13_DWLI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2391
ber01-VHDL13_DWLI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1951
ber01-VHDL13_DWMO_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 2853
ber01-VHDL13_DWMO_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2626
ber01-VHDL13_DWMP_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 2989
ber01-VHDL13_DWMP_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2571
ber01-VHDL13_DWOG_211700-2608211700-dsw--0-ia5 21-Aug-2026 18:00:04 3789
ber01-VHDL13_DWOG_220300-2608220300-dsw--0-ia5 22-Aug-2026 03:00:25 3670
ber01-VHDL13_DWOG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 3466
ber01-VHDL13_DWOG_221700-2608221700-dsw--0-ia5 22-Aug-2026 18:00:04 3566
ber01-VHDL13_DWOG_230300-2608230300-dsw--0-ia5 23-Aug-2026 03:00:07 3581
ber01-VHDL13_DWOG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3677
ber01-VHDL13_DWON_211502-2608211502-dsw--0-ia5 21-Aug-2026 15:02:25 3888
ber01-VHDL13_DWON_211705-2608211705-dsw--0-ia5 21-Aug-2026 17:05:48 3035
ber01-VHDL13_DWON_211718-2608211718-dsw--0-ia5 21-Aug-2026 17:18:53 3035
ber01-VHDL13_DWON_212050-2608212050-dsw--0-ia5 21-Aug-2026 20:50:51 3006
ber01-VHDL13_DWON_220131-2608220131-dsw--0-ia5 22-Aug-2026 01:32:14 2770
ber01-VHDL13_DWON_220234-2608220234-dsw--0-ia5 22-Aug-2026 02:35:11 2889
ber01-VHDL13_DWON_220446-2608220446-dsw--0-ia5 22-Aug-2026 04:46:18 3348
ber01-VHDL13_DWON_220526-2608220526-dsw--0-ia5 22-Aug-2026 05:26:23 3348
ber01-VHDL13_DWON_220552-2608220552-dsw--0-ia5 22-Aug-2026 05:52:53 3348
ber01-VHDL13_DWON_221232-2608221232-dsw--0-ia5 22-Aug-2026 12:32:14 3170
ber01-VHDL13_DWON_221346-2608221346-dsw--0-ia5 22-Aug-2026 13:46:49 3170
ber01-VHDL13_DWON_221425-2608221425-dsw--0-ia5 22-Aug-2026 14:25:19 3170
ber01-VHDL13_DWON_221653-2608221653-dsw--0-ia5 22-Aug-2026 16:53:24 3068
ber01-VHDL13_DWON_221935-2608221935-dsw--0-ia5 22-Aug-2026 19:35:43 3068
ber01-VHDL13_DWON_222031-2608222031-dsw--0-ia5 22-Aug-2026 20:31:49 3063
ber01-VHDL13_DWON_230129-2608230129-dsw--0-ia5 23-Aug-2026 01:29:28 2977
ber01-VHDL13_DWON_230215-2608230215-dsw--0-ia5 23-Aug-2026 02:15:54 2967
ber01-VHDL13_DWON_230329-2608230329-dsw--0-ia5 23-Aug-2026 03:29:33 2983
ber01-VHDL13_DWON_230513-2608230513-dsw--0-ia5 23-Aug-2026 05:13:54 3068
ber01-VHDL13_DWON_230914-2608230914-dsw--0-ia5 23-Aug-2026 09:14:48 3022
ber01-VHDL13_DWON_231245-2608231245-dsw--0-ia5 23-Aug-2026 12:46:08 2789
ber01-VHDL13_DWPG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1953
ber01-VHDL13_DWPG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2189
ber01-VHDL13_DWPH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2953
ber01-VHDL13_DWPH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3196
ber01-VHDL13_DWSG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2884
ber01-VHDL13_DWSG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:10 2551
ber01-VHDL17_DWOG_221200-2608221200-dsw--0-ia5 22-Aug-2026 10:47:13 2915
ber01-VHDL17_DWOG_231200-2608231200-dsw--0-ia5 23-Aug-2026 11:43:09 2501
swis2-VHDL20_DWEG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1729
swis2-VHDL20_DWEG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1524
swis2-VHDL20_DWEG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1225
swis2-VHDL20_DWEG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1287
swis2-VHDL20_DWEG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1083
swis2-VHDL20_DWEG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 911
swis2-VHDL20_DWEG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 877
swis2-VHDL20_DWEG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1000
swis2-VHDL20_DWEH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1807
swis2-VHDL20_DWEH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1521
swis2-VHDL20_DWEH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1100
swis2-VHDL20_DWEH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1267
swis2-VHDL20_DWEH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1182
swis2-VHDL20_DWEH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 924
swis2-VHDL20_DWEH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 891
swis2-VHDL20_DWEH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1107
swis2-VHDL20_DWEI_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1785
swis2-VHDL20_DWEI_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1592
swis2-VHDL20_DWEI_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1247
swis2-VHDL20_DWEI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1292
swis2-VHDL20_DWEI_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1286
swis2-VHDL20_DWEI_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 1171
swis2-VHDL20_DWEI_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 1078
swis2-VHDL20_DWEI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1362
swis2-VHDL20_DWHG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:46:05 1387
swis2-VHDL20_DWHG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:45:24 1533
swis2-VHDL20_DWHG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1530
swis2-VHDL20_DWHG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:45:29 1726
swis2-VHDL20_DWHG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:45:18 1226
swis2-VHDL20_DWHG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:46:07 1013
swis2-VHDL20_DWHG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 1013
swis2-VHDL20_DWHG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:46:52 1163
swis2-VHDL20_DWHH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:46:04 1207
swis2-VHDL20_DWHH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:45:24 1450
swis2-VHDL20_DWHH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1450
swis2-VHDL20_DWHH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:45:29 1577
swis2-VHDL20_DWHH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:45:18 1329
swis2-VHDL20_DWHH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:46:07 1258
swis2-VHDL20_DWHH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 1261
swis2-VHDL20_DWHH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:46:52 1411
swis2-VHDL20_DWLG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1517
swis2-VHDL20_DWLG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1186
swis2-VHDL20_DWLG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1011
swis2-VHDL20_DWLG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1133
swis2-VHDL20_DWLG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 984
swis2-VHDL20_DWLG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 853
swis2-VHDL20_DWLG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 766
swis2-VHDL20_DWLG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 876
swis2-VHDL20_DWLH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1396
swis2-VHDL20_DWLH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1133
swis2-VHDL20_DWLH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1039
swis2-VHDL20_DWLH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 993
swis2-VHDL20_DWLH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 929
swis2-VHDL20_DWLH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 834
swis2-VHDL20_DWLH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 772
swis2-VHDL20_DWLH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 882
swis2-VHDL20_DWLI_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1356
swis2-VHDL20_DWLI_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1322
swis2-VHDL20_DWLI_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1119
swis2-VHDL20_DWLI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1098
swis2-VHDL20_DWLI_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 950
swis2-VHDL20_DWLI_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 894
swis2-VHDL20_DWLI_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 768
swis2-VHDL20_DWLI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 860
swis2-VHDL20_DWMO_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1788
swis2-VHDL20_DWMO_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1203
swis2-VHDL20_DWMO_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:08 1220
swis2-VHDL20_DWMO_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1363
swis2-VHDL20_DWMO_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1194
swis2-VHDL20_DWMO_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 949
swis2-VHDL20_DWMO_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:03 984
swis2-VHDL20_DWMO_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1191
swis2-VHDL20_DWMP_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1740
swis2-VHDL20_DWMP_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1130
swis2-VHDL20_DWMP_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:08 1143
swis2-VHDL20_DWMP_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1398
swis2-VHDL20_DWMP_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1242
swis2-VHDL20_DWMP_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 997
swis2-VHDL20_DWMP_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:03 1127
swis2-VHDL20_DWMP_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1236
swis2-VHDL20_DWPG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1769
swis2-VHDL20_DWPG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1118
swis2-VHDL20_DWPG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 896
swis2-VHDL20_DWPG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 971
swis2-VHDL20_DWPG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 965
swis2-VHDL20_DWPG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 865
swis2-VHDL20_DWPG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 833
swis2-VHDL20_DWPG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 924
swis2-VHDL20_DWPH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1816
swis2-VHDL20_DWPH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1588
swis2-VHDL20_DWPH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1437
swis2-VHDL20_DWPH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1531
swis2-VHDL20_DWPH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 1676
swis2-VHDL20_DWPH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 1469
swis2-VHDL20_DWPH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 1455
swis2-VHDL20_DWPH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 1547
swis2-VHDL20_DWSG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1544
swis2-VHDL20_DWSG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1137
swis2-VHDL20_DWSG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1124
swis2-VHDL20_DWSG_220400_COR-2608220400-dsw--0-ia5 22-Aug-2026 05:00:49 1123
swis2-VHDL20_DWSG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1275
swis2-VHDL20_DWSG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1135
swis2-VHDL20_DWSG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 976
swis2-VHDL20_DWSG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 996
swis2-VHDL20_DWSG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:10 1256
wst04-VHDL20_DWEG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:25 245506
wst04-VHDL20_DWEG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 245469
wst04-VHDL20_DWEG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 243730
wst04-VHDL20_DWEG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 244437
wst04-VHDL20_DWEG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 244240
wst04-VHDL20_DWEG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 243110
wst04-VHDL20_DWEG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 242980
wst04-VHDL20_DWEG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:12 243972
wst04-VHDL20_DWEH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:25 243822
wst04-VHDL20_DWEH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 244290
wst04-VHDL20_DWEH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 242907
wst04-VHDL20_DWEH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 243708
wst04-VHDL20_DWEH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 236854
wst04-VHDL20_DWEH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 236290
wst04-VHDL20_DWEH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 236080
wst04-VHDL20_DWEH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:12 237218
wst04-VHDL20_DWEI_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 351534
wst04-VHDL20_DWEI_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 352244
wst04-VHDL20_DWEI_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 349910
wst04-VHDL20_DWEI_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 350840
wst04-VHDL20_DWEI_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 354576
wst04-VHDL20_DWEI_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 354504
wst04-VHDL20_DWEI_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 354513
wst04-VHDL20_DWEI_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 355642
wst04-VHDL20_DWHG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:46:05 348794
wst04-VHDL20_DWHG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:45:24 348340
wst04-VHDL20_DWHG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 348145
wst04-VHDL20_DWHG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:45:29 350253
wst04-VHDL20_DWHG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:45:33 344643
wst04-VHDL20_DWHG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:46:07 343672
wst04-VHDL20_DWHG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 343459
wst04-VHDL20_DWHG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:46:52 344888
wst04-VHDL20_DWHH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:46:05 333773
wst04-VHDL20_DWHH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:45:24 334725
wst04-VHDL20_DWHH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 229677
wst04-VHDL20_DWHH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:45:29 335341
wst04-VHDL20_DWHH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:45:33 334485
wst04-VHDL20_DWHH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:46:07 334128
wst04-VHDL20_DWHH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 232090
wst04-VHDL20_DWHH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:46:52 334549
wst04-VHDL20_DWLG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 346799
wst04-VHDL20_DWLG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 346245
wst04-VHDL20_DWLG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 345953
wst04-VHDL20_DWLG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 346142
wst04-VHDL20_DWLG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 337587
wst04-VHDL20_DWLG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 382162
wst04-VHDL20_DWLG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 336309
wst04-VHDL20_DWLG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 336365
wst04-VHDL20_DWLH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 348324
wst04-VHDL20_DWLH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 347484
wst04-VHDL20_DWLH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 347183
wst04-VHDL20_DWLH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:52 346799
wst04-VHDL20_DWLH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 336921
wst04-VHDL20_DWLH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 380514
wst04-VHDL20_DWLH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 335183
wst04-VHDL20_DWLH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 335245
wst04-VHDL20_DWLI_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 344353
wst04-VHDL20_DWLI_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 344195
wst04-VHDL20_DWLI_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 343876
wst04-VHDL20_DWLI_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 387818
wst04-VHDL20_DWLI_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 339289
wst04-VHDL20_DWLI_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 383934
wst04-VHDL20_DWLI_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 337851
wst04-VHDL20_DWLI_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:48 382915
wst04-VHDL20_DWMO_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 361526
wst04-VHDL20_DWMO_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 469206
wst04-VHDL20_DWMO_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 469156
wst04-VHDL20_DWMO_220800-2608220800-omedes--0.pdf 22-Aug-2026 11:10:49 455075
wst04-VHDL20_DWMO_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 346913
wst04-VHDL20_DWMO_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 453181
wst04-VHDL20_DWMO_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 453212
wst04-VHDL20_DWMO_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 453017
wst04-VHDL20_DWMP_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 474947
wst04-VHDL20_DWMP_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 581434
wst04-VHDL20_DWMP_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 580787
wst04-VHDL20_DWMP_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:29 474091
wst04-VHDL20_DWMP_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 456088
wst04-VHDL20_DWMP_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 560459
wst04-VHDL20_DWMP_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 560706
wst04-VHDL20_DWMP_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 455806
wst04-VHDL20_DWPG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 350535
wst04-VHDL20_DWPG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 243344
wst04-VHDL20_DWPG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:33 347757
wst04-VHDL20_DWPG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 392477
wst04-VHDL20_DWPG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 346271
wst04-VHDL20_DWPG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 242206
wst04-VHDL20_DWPG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:34 344919
wst04-VHDL20_DWPG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 389481
wst04-VHDL20_DWPH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 250117
wst04-VHDL20_DWPH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 249839
wst04-VHDL20_DWPH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:33 249641
wst04-VHDL20_DWPH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 249733
wst04-VHDL20_DWPH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 245633
wst04-VHDL20_DWPH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 290149
wst04-VHDL20_DWPH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:34 245378
wst04-VHDL20_DWPH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 245491
wst04-VHDL20_DWSG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 353092
wst04-VHDL20_DWSG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 351262
wst04-VHDL20_DWSG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:59 351539
wst04-VHDL20_DWSG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 351630
wst04-VHDL20_DWSG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 353696
wst04-VHDL20_DWSG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 352737
wst04-VHDL20_DWSG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 352548
wst04-VHDL20_DWSG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 353155