Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_090600 09-Sep-2026 11:32:06 4394
FPDL13_DWMZ_100600 10-Sep-2026 13:19:35 4659
SXDL31_DWAV_081800 08-Sep-2026 16:28:23 9599
SXDL31_DWAV_090800 09-Sep-2026 07:21:03 7295
SXDL31_DWAV_091800 09-Sep-2026 16:00:30 3312
SXDL31_DWAV_100800 10-Sep-2026 07:09:15 5398
SXDL31_DWAV_LATEST 10-Sep-2026 07:09:15 5398
SXDL33_DWAV_090000 09-Sep-2026 09:59:24 8182
SXDL33_DWAV_100000 10-Sep-2026 09:57:36 6669
SXDL33_DWAV_LATEST 10-Sep-2026 09:57:36 6669
ber01-FWDL39_DWMS_091200-2609091200-dsw--0-ia5 09-Sep-2026 12:25:29 1190
ber01-FWDL39_DWMS_101200-2609101200-dsw--0-ia5 10-Sep-2026 10:59:54 1999
ber01-VHDL13_DWEG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:28:23 2716
ber01-VHDL13_DWEG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2725
ber01-VHDL13_DWEH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:28:19 3154
ber01-VHDL13_DWEH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2527
ber01-VHDL13_DWEI_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:28:19 2733
ber01-VHDL13_DWEI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2719
ber01-VHDL13_DWHG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 3238
ber01-VHDL13_DWHG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 2838
ber01-VHDL13_DWHH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 3342
ber01-VHDL13_DWHH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 2806
ber01-VHDL13_DWLG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:07 2347
ber01-VHDL13_DWLG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2151
ber01-VHDL13_DWLH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:07 2756
ber01-VHDL13_DWLH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2238
ber01-VHDL13_DWLI_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:07 2485
ber01-VHDL13_DWLI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2293
ber01-VHDL13_DWMO_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 2733
ber01-VHDL13_DWMO_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2459
ber01-VHDL13_DWMP_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 3617
ber01-VHDL13_DWMP_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2778
ber01-VHDL13_DWOG_081700-2609081700-dsw--0-ia5 08-Sep-2026 18:00:04 4971
ber01-VHDL13_DWOG_090300-2609090300-dsw--0-ia5 09-Sep-2026 03:01:13 3792
ber01-VHDL13_DWOG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 3591
ber01-VHDL13_DWOG_091700-2609091700-dsw--0-ia5 09-Sep-2026 18:00:05 3253
ber01-VHDL13_DWOG_091700_COR-2609091700-dsw--0-ia5 09-Sep-2026 17:23:03 3257
ber01-VHDL13_DWOG_100300-2609100300-dsw--0-ia5 10-Sep-2026 03:00:20 3296
ber01-VHDL13_DWOG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 3403
ber01-VHDL13_DWOG_100800_COR-2609100800-dsw--0-ia5 10-Sep-2026 08:55:47 3303
ber01-VHDL13_DWON_081713-2609081713-dsw--0-ia5 08-Sep-2026 17:14:05 3831
ber01-VHDL13_DWON_082330-2609082330-dsw--0-ia5 08-Sep-2026 23:30:58 3495
ber01-VHDL13_DWON_090052-2609090052-dsw--0-ia5 09-Sep-2026 00:52:36 3495
ber01-VHDL13_DWON_090251-2609090251-dsw--0-ia5 09-Sep-2026 02:53:48 3495
ber01-VHDL13_DWON_090458-2609090458-dsw--0-ia5 09-Sep-2026 04:58:48 3223
ber01-VHDL13_DWON_090533-2609090533-dsw--0-ia5 09-Sep-2026 05:34:19 3382
ber01-VHDL13_DWON_090755-2609090755-dsw--0-ia5 09-Sep-2026 07:55:49 3382
ber01-VHDL13_DWON_090756-2609090756-dsw--0-ia5 09-Sep-2026 07:56:44 3382
ber01-VHDL13_DWON_091402-2609091402-dsw--0-ia5 09-Sep-2026 14:02:23 3142
ber01-VHDL13_DWON_091404-2609091404-dsw--0-ia5 09-Sep-2026 14:04:33 3142
ber01-VHDL13_DWON_091406-2609091406-dsw--0-ia5 09-Sep-2026 14:06:38 3142
ber01-VHDL13_DWON_091417-2609091417-dsw--0-ia5 09-Sep-2026 14:17:23 3142
ber01-VHDL13_DWON_091705-2609091705-dsw--0-ia5 09-Sep-2026 17:05:09 3484
ber01-VHDL13_DWON_091722-2609091722-dsw--0-ia5 09-Sep-2026 17:22:49 3484
ber01-VHDL13_DWON_091850-2609091850-dsw--0-ia5 09-Sep-2026 18:50:23 3485
ber01-VHDL13_DWON_091905-2609091905-dsw--0-ia5 09-Sep-2026 19:05:44 3435
ber01-VHDL13_DWON_100127-2609100127-dsw--0-ia5 10-Sep-2026 01:27:28 3250
ber01-VHDL13_DWON_100214-2609100214-dsw--0-ia5 10-Sep-2026 02:14:54 3197
ber01-VHDL13_DWON_100527-2609100527-dsw--0-ia5 10-Sep-2026 05:28:04 3671
ber01-VHDL13_DWON_100629-2609100629-dsw--0-ia5 10-Sep-2026 06:30:09 3671
ber01-VHDL13_DWON_100854-2609100854-dsw--0-ia5 10-Sep-2026 08:55:12 3671
ber01-VHDL13_DWON_101433-2609101433-dsw--0-ia5 10-Sep-2026 14:33:43 3472
ber01-VHDL13_DWPG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:07 2622
ber01-VHDL13_DWPG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2214
ber01-VHDL13_DWPH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:07 3004
ber01-VHDL13_DWPH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2380
ber01-VHDL13_DWSG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 3256
ber01-VHDL13_DWSG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2454
ber01-VHDL17_DWOG_091200-2609091200-dsw--0-ia5 09-Sep-2026 11:28:59 3486
ber01-VHDL17_DWOG_101200-2609101200-dsw--0-ia5 10-Sep-2026 11:07:30 2977
swis2-VHDL20_DWEG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1227
swis2-VHDL20_DWEG_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 785
swis2-VHDL20_DWEG_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:01:26 1066
swis2-VHDL20_DWEG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1279
swis2-VHDL20_DWEG_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:08 1155
swis2-VHDL20_DWEG_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:06 965
swis2-VHDL20_DWEG_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:01:18 1004
swis2-VHDL20_DWEG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1117
swis2-VHDL20_DWEH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1537
swis2-VHDL20_DWEH_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 1102
swis2-VHDL20_DWEH_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:01:24 1270
swis2-VHDL20_DWEH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1477
swis2-VHDL20_DWEH_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:06 1123
swis2-VHDL20_DWEH_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:06 931
swis2-VHDL20_DWEH_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:01:18 903
swis2-VHDL20_DWEH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 939
swis2-VHDL20_DWEI_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1209
swis2-VHDL20_DWEI_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 774
swis2-VHDL20_DWEI_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:01:26 1082
swis2-VHDL20_DWEI_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1295
swis2-VHDL20_DWEI_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:06 1196
swis2-VHDL20_DWEI_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:06 982
swis2-VHDL20_DWEI_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:01:18 1021
swis2-VHDL20_DWEI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1126
swis2-VHDL20_DWHG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:45:10 1992
swis2-VHDL20_DWHG_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:46:51 1680
swis2-VHDL20_DWHG_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1664
swis2-VHDL20_DWHG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:45:56 1722
swis2-VHDL20_DWHG_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:45:18 1273
swis2-VHDL20_DWHG_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:46:46 1011
swis2-VHDL20_DWHG_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:19 1008
swis2-VHDL20_DWHG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:45:25 1145
swis2-VHDL20_DWHH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:45:11 1965
swis2-VHDL20_DWHH_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:46:51 1739
swis2-VHDL20_DWHH_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1765
swis2-VHDL20_DWHH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:45:56 1687
swis2-VHDL20_DWHH_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:45:18 1405
swis2-VHDL20_DWHH_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:46:46 1102
swis2-VHDL20_DWHH_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:19 1102
swis2-VHDL20_DWHH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:45:25 1098
swis2-VHDL20_DWLG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 986
swis2-VHDL20_DWLG_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:23 998
swis2-VHDL20_DWLG_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 806
swis2-VHDL20_DWLG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:28 974
swis2-VHDL20_DWLG_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:31:20 937
swis2-VHDL20_DWLG_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:30 727
swis2-VHDL20_DWLG_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:13 795
swis2-VHDL20_DWLG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1000
swis2-VHDL20_DWLH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1382
swis2-VHDL20_DWLH_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:23 1283
swis2-VHDL20_DWLH_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1186
swis2-VHDL20_DWLH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:28 1326
swis2-VHDL20_DWLH_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:31:20 926
swis2-VHDL20_DWLH_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:30 734
swis2-VHDL20_DWLH_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:13 799
swis2-VHDL20_DWLH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1135
swis2-VHDL20_DWLI_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1008
swis2-VHDL20_DWLI_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:23 923
swis2-VHDL20_DWLI_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 968
swis2-VHDL20_DWLI_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:28 1187
swis2-VHDL20_DWLI_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:31:20 949
swis2-VHDL20_DWLI_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:30 775
swis2-VHDL20_DWLI_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:13 860
swis2-VHDL20_DWLI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1065
swis2-VHDL20_DWMO_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 1588
swis2-VHDL20_DWMO_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 999
swis2-VHDL20_DWMO_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:15 1013
swis2-VHDL20_DWMO_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1285
swis2-VHDL20_DWMO_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:06 1088
swis2-VHDL20_DWMO_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:08 879
swis2-VHDL20_DWMO_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:05 807
swis2-VHDL20_DWMO_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 968
swis2-VHDL20_DWMP_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:08 2075
swis2-VHDL20_DWMP_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 1429
swis2-VHDL20_DWMP_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:08 1442
swis2-VHDL20_DWMP_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1726
swis2-VHDL20_DWMP_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:06 1152
swis2-VHDL20_DWMP_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:08 1001
swis2-VHDL20_DWMP_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:05 838
swis2-VHDL20_DWMP_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1057
swis2-VHDL20_DWPG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1103
swis2-VHDL20_DWPG_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:23 938
swis2-VHDL20_DWPG_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1011
swis2-VHDL20_DWPG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:28 1158
swis2-VHDL20_DWPG_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:31:20 893
swis2-VHDL20_DWPG_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:30 745
swis2-VHDL20_DWPG_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:13 813
swis2-VHDL20_DWPG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1152
swis2-VHDL20_DWPH_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:31:07 1358
swis2-VHDL20_DWPH_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:23 905
swis2-VHDL20_DWPH_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1116
swis2-VHDL20_DWPH_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:28 1332
swis2-VHDL20_DWPH_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:31:20 1044
swis2-VHDL20_DWPH_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:30 894
swis2-VHDL20_DWPH_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:13 874
swis2-VHDL20_DWPH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1128
swis2-VHDL20_DWSG_081800-2609081800-dsw--0-ia5 08-Sep-2026 18:30:17 1820
swis2-VHDL20_DWSG_081800_COR-2609081800-dsw--0-ia5 08-Sep-2026 20:20:59 1840
swis2-VHDL20_DWSG_090200-2609090200-dsw--0-ia5 09-Sep-2026 02:30:04 1112
swis2-VHDL20_DWSG_090400-2609090400-dsw--0-ia5 09-Sep-2026 05:00:17 1134
swis2-VHDL20_DWSG_090400_COR-2609090400-dsw--0-ia5 09-Sep-2026 05:09:23 1524
swis2-VHDL20_DWSG_090800-2609090800-dsw--0-ia5 09-Sep-2026 08:30:14 1512
swis2-VHDL20_DWSG_091800-2609091800-dsw--0-ia5 09-Sep-2026 18:30:06 924
swis2-VHDL20_DWSG_100200-2609100200-dsw--0-ia5 10-Sep-2026 02:30:06 903
swis2-VHDL20_DWSG_100400-2609100400-dsw--0-ia5 10-Sep-2026 05:00:19 882
swis2-VHDL20_DWSG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 942
wst04-VHDL20_DWEG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 244419
wst04-VHDL20_DWEG_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 243143
wst04-VHDL20_DWEG_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 244153
wst04-VHDL20_DWEG_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:14 244923
wst04-VHDL20_DWEG_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:27 241800
wst04-VHDL20_DWEG_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:14 241189
wst04-VHDL20_DWEG_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:13 240882
wst04-VHDL20_DWEG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:16 241509
wst04-VHDL20_DWEH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 244660
wst04-VHDL20_DWEH_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 243617
wst04-VHDL20_DWEH_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 243176
wst04-VHDL20_DWEH_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:14 243917
wst04-VHDL20_DWEH_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:27 240821
wst04-VHDL20_DWEH_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:14 240442
wst04-VHDL20_DWEH_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:13 240427
wst04-VHDL20_DWEH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 240937
wst04-VHDL20_DWEI_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 350350
wst04-VHDL20_DWEI_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 349286
wst04-VHDL20_DWEI_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 350223
wst04-VHDL20_DWEI_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:14 350515
wst04-VHDL20_DWEI_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:27 345523
wst04-VHDL20_DWEI_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:14 345324
wst04-VHDL20_DWEI_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:19 345130
wst04-VHDL20_DWEI_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:16 345182
wst04-VHDL20_DWHG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:45:15 352548
wst04-VHDL20_DWHG_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:46:51 351148
wst04-VHDL20_DWHG_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 350916
wst04-VHDL20_DWHG_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:45:56 352649
wst04-VHDL20_DWHG_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:45:28 343381
wst04-VHDL20_DWHG_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:46:46 342088
wst04-VHDL20_DWHG_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:23 341877
wst04-VHDL20_DWHG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:45:25 342905
wst04-VHDL20_DWHH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:45:15 339312
wst04-VHDL20_DWHH_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:46:51 338299
wst04-VHDL20_DWHH_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 233211
wst04-VHDL20_DWHH_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:45:56 339094
wst04-VHDL20_DWHH_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:45:28 333090
wst04-VHDL20_DWHH_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:46:46 332353
wst04-VHDL20_DWHH_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:19 229221
wst04-VHDL20_DWHH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:45:25 332056
wst04-VHDL20_DWLG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 332551
wst04-VHDL20_DWLG_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 332587
wst04-VHDL20_DWLG_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:45 331672
wst04-VHDL20_DWLG_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:53 331710
wst04-VHDL20_DWLG_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:31:29 335561
wst04-VHDL20_DWLG_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:30 335381
wst04-VHDL20_DWLG_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:43 335146
wst04-VHDL20_DWLG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 335486
wst04-VHDL20_DWLH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 337871
wst04-VHDL20_DWLH_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 337630
wst04-VHDL20_DWLH_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:45 336934
wst04-VHDL20_DWLH_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:53 337157
wst04-VHDL20_DWLH_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:31:29 338913
wst04-VHDL20_DWLH_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:30 338037
wst04-VHDL20_DWLH_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:43 337797
wst04-VHDL20_DWLH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:52 339108
wst04-VHDL20_DWLI_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 338386
wst04-VHDL20_DWLI_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 338094
wst04-VHDL20_DWLI_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:45 337817
wst04-VHDL20_DWLI_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:53 382732
wst04-VHDL20_DWLI_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:31:39 336590
wst04-VHDL20_DWLI_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:30 336178
wst04-VHDL20_DWLI_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:43 336017
wst04-VHDL20_DWLI_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 380749
wst04-VHDL20_DWMO_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 350559
wst04-VHDL20_DWMO_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 456407
wst04-VHDL20_DWMO_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 456358
wst04-VHDL20_DWMO_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:28 456934
wst04-VHDL20_DWMO_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:27 355855
wst04-VHDL20_DWMO_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:14 457466
wst04-VHDL20_DWMO_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:13 457954
wst04-VHDL20_DWMO_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 457982
wst04-VHDL20_DWMP_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:30:19 467840
wst04-VHDL20_DWMP_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 575256
wst04-VHDL20_DWMP_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:17 576199
wst04-VHDL20_DWMP_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:28 467611
wst04-VHDL20_DWMP_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:29 469417
wst04-VHDL20_DWMP_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:19 574058
wst04-VHDL20_DWMP_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:19 574543
wst04-VHDL20_DWMP_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 469176
wst04-VHDL20_DWPG_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:33 339733
wst04-VHDL20_DWPG_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:42 240024
wst04-VHDL20_DWPG_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:42 339220
wst04-VHDL20_DWPG_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:55 383946
wst04-VHDL20_DWPG_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:31:29 339458
wst04-VHDL20_DWPG_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:30 238512
wst04-VHDL20_DWPG_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:33 338872
wst04-VHDL20_DWPG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 384744
wst04-VHDL20_DWPH_081800-2609081800-omedes--0.pdf 08-Sep-2026 18:31:31 243161
wst04-VHDL20_DWPH_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 241479
wst04-VHDL20_DWPH_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:00:42 242263
wst04-VHDL20_DWPH_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:53 241833
wst04-VHDL20_DWPH_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:31:29 240500
wst04-VHDL20_DWPH_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:30 239972
wst04-VHDL20_DWPH_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:33 239961
wst04-VHDL20_DWPH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 241534
wst04-VHDL20_DWSG_081800-2609081800-omedes--0.pdf 08-Sep-2026 20:21:03 351526
wst04-VHDL20_DWSG_090200-2609090200-omedes--0.pdf 09-Sep-2026 02:30:23 349330
wst04-VHDL20_DWSG_090400-2609090400-omedes--0.pdf 09-Sep-2026 05:09:42 351185
wst04-VHDL20_DWSG_090800-2609090800-omedes--0.pdf 09-Sep-2026 08:30:28 350014
wst04-VHDL20_DWSG_091800-2609091800-omedes--0.pdf 09-Sep-2026 18:30:27 348657
wst04-VHDL20_DWSG_100200-2609100200-omedes--0.pdf 10-Sep-2026 02:30:19 348339
wst04-VHDL20_DWSG_100400-2609100400-omedes--0.pdf 10-Sep-2026 05:00:13 348103
wst04-VHDL20_DWSG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 348119