Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Nov-2026 14:12:07 5370
FPDL13_DWMZ_050600 05-Nov-2026 15:07:45 6247
SXDL31_DWAV_040810 04-Nov-2026 08:20:24 7425
SXDL31_DWAV_041810 04-Nov-2026 17:24:45 6951
SXDL31_DWAV_050810 05-Nov-2026 08:13:34 14133
SXDL31_DWAV_051810 05-Nov-2026 16:08:50 5318
SXDL31_DWAV_LATEST 05-Nov-2026 16:08:50 5318
SXDL33_DWAV_040000 04-Nov-2026 11:02:29 6453
SXDL33_DWAV_050000 05-Nov-2026 10:43:17 7912
SXDL33_DWAV_LATEST 05-Nov-2026 10:43:17 7912
ber01-FWDL39_DWMS_041200-2611041200-dsw--0-ia5 04-Nov-2026 12:32:00 1446
ber01-FWDL39_DWMS_051200-2611051200-dsw--0-ia5 05-Nov-2026 12:28:48 1644
ber01-VHDL13_DWEG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 3030
ber01-VHDL13_DWEG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:13 2565
ber01-VHDL13_DWEH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 2889
ber01-VHDL13_DWEH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:13 2707
ber01-VHDL13_DWEI_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 2910
ber01-VHDL13_DWEI_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:13 2653
ber01-VHDL13_DWHG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 3402
ber01-VHDL13_DWHG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 3338
ber01-VHDL13_DWHH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 2731
ber01-VHDL13_DWHH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 2809
ber01-VHDL13_DWLG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2416
ber01-VHDL13_DWLG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:03 2414
ber01-VHDL13_DWLH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2427
ber01-VHDL13_DWLH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:03 2277
ber01-VHDL13_DWLI_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2672
ber01-VHDL13_DWLI_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:03 2456
ber01-VHDL13_DWMO_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 3183
ber01-VHDL13_DWMO_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:07 2753
ber01-VHDL13_DWMP_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 3581
ber01-VHDL13_DWMP_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:07 3502
ber01-VHDL13_DWOG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 3099
ber01-VHDL13_DWOG_041700-2611041700-dsw--0-ia5 04-Nov-2026 19:00:11 3053
ber01-VHDL13_DWOG_050300-2611050300-dsw--0-ia5 05-Nov-2026 04:00:06 3299
ber01-VHDL13_DWOG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:07 2848
ber01-VHDL13_DWOG_051700-2611051700-dsw--0-ia5 05-Nov-2026 19:00:11 3091
ber01-VHDL13_DWOG_060300-2611060300-dsw--0-ia5 06-Nov-2026 04:00:13 3390
ber01-VHDL13_DWON_040732-2611040732-dsw--0-ia5 04-Nov-2026 07:32:30 2990
ber01-VHDL13_DWON_041049-2611041049-dsw--0-ia5 04-Nov-2026 10:49:08 2990
ber01-VHDL13_DWON_041239-2611041239-dsw--0-ia5 04-Nov-2026 12:39:43 3006
ber01-VHDL13_DWON_041524-2611041524-dsw--0-ia5 04-Nov-2026 15:24:48 2465
ber01-VHDL13_DWON_041527-2611041527-dsw--0-ia5 04-Nov-2026 15:27:58 2465
ber01-VHDL13_DWON_041759-2611041759-dsw--0-ia5 04-Nov-2026 17:59:55 2527
ber01-VHDL13_DWON_042343-2611042343-dsw--0-ia5 04-Nov-2026 23:43:13 3184
ber01-VHDL13_DWON_050208-2611050208-dsw--0-ia5 05-Nov-2026 02:08:34 3185
ber01-VHDL13_DWON_050337-2611050337-dsw--0-ia5 05-Nov-2026 03:37:52 3190
ber01-VHDL13_DWON_050344-2611050344-dsw--0-ia5 05-Nov-2026 03:44:29 3190
ber01-VHDL13_DWON_050629-2611050629-dsw--0-ia5 05-Nov-2026 06:29:58 2855
ber01-VHDL13_DWON_050718-2611050718-dsw--0-ia5 05-Nov-2026 07:18:19 2791
ber01-VHDL13_DWON_051546-2611051546-dsw--0-ia5 05-Nov-2026 15:46:13 2624
ber01-VHDL13_DWON_051752-2611051752-dsw--0-ia5 05-Nov-2026 17:53:06 2866
ber01-VHDL13_DWON_060209-2611060209-dsw--0-ia5 06-Nov-2026 02:09:53 3093
ber01-VHDL13_DWON_060342-2611060342-dsw--0-ia5 06-Nov-2026 03:42:27 3093
ber01-VHDL13_DWON_060629-2611060629-dsw--0-ia5 06-Nov-2026 06:29:43 3639
ber01-VHDL13_DWPG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2542
ber01-VHDL13_DWPG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:03 2520
ber01-VHDL13_DWPH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2469
ber01-VHDL13_DWPH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:03 2401
ber01-VHDL13_DWSG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 3120
ber01-VHDL13_DWSG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 2783
ber01-VHDL17_DWOG_041200-2611041200-dsw--0-ia5 04-Nov-2026 12:33:02 2137
ber01-VHDL17_DWOG_051200-2611051200-dsw--0-ia5 05-Nov-2026 12:53:07 2872
swis2-VHDL20_DWEG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 1775
swis2-VHDL20_DWEG_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1461
swis2-VHDL20_DWEG_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1460
swis2-VHDL20_DWEG_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:01:03 1094
swis2-VHDL20_DWEG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 1452
swis2-VHDL20_DWEG_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:17 1464
swis2-VHDL20_DWEG_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:14 1413
swis2-VHDL20_DWEG_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:01:04 1463
swis2-VHDL20_DWEH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 1896
swis2-VHDL20_DWEH_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1452
swis2-VHDL20_DWEH_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1172
swis2-VHDL20_DWEH_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:01:03 1172
swis2-VHDL20_DWEH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 1491
swis2-VHDL20_DWEH_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:17 1465
swis2-VHDL20_DWEH_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:14 1207
swis2-VHDL20_DWEH_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:01:04 1550
swis2-VHDL20_DWEI_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 1837
swis2-VHDL20_DWEI_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1489
swis2-VHDL20_DWEI_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1445
swis2-VHDL20_DWEI_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:01:03 1059
swis2-VHDL20_DWEI_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 1411
swis2-VHDL20_DWEI_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:17 1261
swis2-VHDL20_DWEI_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:14 1212
swis2-VHDL20_DWEI_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:01:04 1385
swis2-VHDL20_DWHG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 2047
swis2-VHDL20_DWHG_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:45:03 1718
swis2-VHDL20_DWHG_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1678
swis2-VHDL20_DWHG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 2049
swis2-VHDL20_DWHG_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:45:06 1939
swis2-VHDL20_DWHG_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1781
swis2-VHDL20_DWHH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 1721
swis2-VHDL20_DWHH_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:45:03 1427
swis2-VHDL20_DWHH_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:45:09 1306
swis2-VHDL20_DWHH_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1365
swis2-VHDL20_DWHH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 1830
swis2-VHDL20_DWHH_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:45:06 1716
swis2-VHDL20_DWHH_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:45:11 1504
swis2-VHDL20_DWHH_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1469
swis2-VHDL20_DWLG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:40 1264
swis2-VHDL20_DWLG_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:31:17 1114
swis2-VHDL20_DWLG_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:35 1042
swis2-VHDL20_DWLG_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1064
swis2-VHDL20_DWLG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:29 1286
swis2-VHDL20_DWLG_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:31:09 1139
swis2-VHDL20_DWLG_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:40 1215
swis2-VHDL20_DWLG_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1288
swis2-VHDL20_DWLH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:40 1322
swis2-VHDL20_DWLH_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:31:17 1168
swis2-VHDL20_DWLH_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:35 1118
swis2-VHDL20_DWLH_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1223
swis2-VHDL20_DWLH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:29 1441
swis2-VHDL20_DWLH_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:31:09 1296
swis2-VHDL20_DWLH_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:40 1234
swis2-VHDL20_DWLH_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1428
swis2-VHDL20_DWLI_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:40 1438
swis2-VHDL20_DWLI_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:31:17 1289
swis2-VHDL20_DWLI_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:35 1099
swis2-VHDL20_DWLI_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1089
swis2-VHDL20_DWLI_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:29 1276
swis2-VHDL20_DWLI_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:31:09 1136
swis2-VHDL20_DWLI_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:40 1220
swis2-VHDL20_DWLI_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1313
swis2-VHDL20_DWMO_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2186
swis2-VHDL20_DWMO_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1802
swis2-VHDL20_DWMO_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1632
swis2-VHDL20_DWMO_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:04 1627
swis2-VHDL20_DWMO_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:07 1871
swis2-VHDL20_DWMO_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:11 1579
swis2-VHDL20_DWMO_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:03 1483
swis2-VHDL20_DWMO_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:04 1513
swis2-VHDL20_DWMP_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:10 2087
swis2-VHDL20_DWMP_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1888
swis2-VHDL20_DWMP_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1722
swis2-VHDL20_DWMP_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:04 1694
swis2-VHDL20_DWMP_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:07 2089
swis2-VHDL20_DWMP_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:11 1665
swis2-VHDL20_DWMP_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:03 1588
swis2-VHDL20_DWMP_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:04 1571
swis2-VHDL20_DWPG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:40 1383
swis2-VHDL20_DWPG_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:31:17 1225
swis2-VHDL20_DWPG_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:35 1137
swis2-VHDL20_DWPG_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1197
swis2-VHDL20_DWPG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:29 1409
swis2-VHDL20_DWPG_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:31:09 1220
swis2-VHDL20_DWPG_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:40 1178
swis2-VHDL20_DWPG_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1302
swis2-VHDL20_DWPH_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:40 1340
swis2-VHDL20_DWPH_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:31:17 1187
swis2-VHDL20_DWPH_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:35 1146
swis2-VHDL20_DWPH_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1255
swis2-VHDL20_DWPH_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:29 1352
swis2-VHDL20_DWPH_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:31:09 1168
swis2-VHDL20_DWPH_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:40 1218
swis2-VHDL20_DWPH_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1382
swis2-VHDL20_DWSG_040800-2611040800-dsw--0-ia5 04-Nov-2026 09:30:18 1757
swis2-VHDL20_DWSG_041800-2611041800-dsw--0-ia5 04-Nov-2026 19:30:11 1834
swis2-VHDL20_DWSG_050200-2611050200-dsw--0-ia5 05-Nov-2026 03:30:11 1351
swis2-VHDL20_DWSG_050400-2611050400-dsw--0-ia5 05-Nov-2026 06:00:14 1364
swis2-VHDL20_DWSG_050800-2611050800-dsw--0-ia5 05-Nov-2026 09:30:09 1287
swis2-VHDL20_DWSG_051800-2611051800-dsw--0-ia5 05-Nov-2026 19:30:11 1240
swis2-VHDL20_DWSG_060200-2611060200-dsw--0-ia5 06-Nov-2026 03:30:03 1186
swis2-VHDL20_DWSG_060400-2611060400-dsw--0-ia5 06-Nov-2026 06:00:14 1158
wst04-VHDL20_DWEG_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:18 226358
wst04-VHDL20_DWEG_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:32 225864
wst04-VHDL20_DWEG_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:19 226318
wst04-VHDL20_DWEG_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:14 225935
wst04-VHDL20_DWEG_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:19 227065
wst04-VHDL20_DWEG_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:18 228325
wst04-VHDL20_DWEG_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:29 228869
wst04-VHDL20_DWEG_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:14 228405
wst04-VHDL20_DWEH_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:18 232473
wst04-VHDL20_DWEH_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:32 223729
wst04-VHDL20_DWEH_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:16 225414
wst04-VHDL20_DWEH_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:14 223921
wst04-VHDL20_DWEH_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:19 225088
wst04-VHDL20_DWEH_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:18 225532
wst04-VHDL20_DWEH_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:29 226368
wst04-VHDL20_DWEH_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:14 225976
wst04-VHDL20_DWEI_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:31 317078
wst04-VHDL20_DWEI_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:32 320806
wst04-VHDL20_DWEI_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:19 320711
wst04-VHDL20_DWEI_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:14 318793
wst04-VHDL20_DWEI_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:19 320155
wst04-VHDL20_DWEI_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:18 321093
wst04-VHDL20_DWEI_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:29 321184
wst04-VHDL20_DWEI_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:18 321096
wst04-VHDL20_DWHG_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:40 313839
wst04-VHDL20_DWHG_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:45:17 314584
wst04-VHDL20_DWHG_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:45:12 313500
wst04-VHDL20_DWHG_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:18 313344
wst04-VHDL20_DWHG_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:33 314962
wst04-VHDL20_DWHG_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:45:17 320086
wst04-VHDL20_DWHG_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:45:27 319435
wst04-VHDL20_DWHG_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:18 319257
wst04-VHDL20_DWHH_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:40 304562
wst04-VHDL20_DWHH_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:45:17 304593
wst04-VHDL20_DWHH_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:45:12 302861
wst04-VHDL20_DWHH_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:18 214516
wst04-VHDL20_DWHH_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:33 304655
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wst04-VHDL20_DWHH_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:45:27 307696
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wst04-VHDL20_DWLG_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:31:23 310402
wst04-VHDL20_DWLG_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:35 309253
wst04-VHDL20_DWLG_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:43 309587
wst04-VHDL20_DWLG_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:43 310806
wst04-VHDL20_DWLG_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:31:23 314720
wst04-VHDL20_DWLG_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:40 313957
wst04-VHDL20_DWLG_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:44 314858
wst04-VHDL20_DWLH_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:58 311199
wst04-VHDL20_DWLH_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:31:29 311074
wst04-VHDL20_DWLH_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:35 309946
wst04-VHDL20_DWLH_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:43 310326
wst04-VHDL20_DWLH_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:43 311497
wst04-VHDL20_DWLH_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:31:29 313799
wst04-VHDL20_DWLH_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:40 312923
wst04-VHDL20_DWLH_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:44 313713
wst04-VHDL20_DWLI_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:58 358439
wst04-VHDL20_DWLI_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:31:23 311236
wst04-VHDL20_DWLI_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:35 309709
wst04-VHDL20_DWLI_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:43 310025
wst04-VHDL20_DWLI_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:43 355755
wst04-VHDL20_DWLI_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:31:23 313840
wst04-VHDL20_DWLI_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:40 313080
wst04-VHDL20_DWLI_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:44 313185
wst04-VHDL20_DWMO_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:18 421194
wst04-VHDL20_DWMO_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:32 421852
wst04-VHDL20_DWMO_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:13 421950
wst04-VHDL20_DWMO_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:18 422382
wst04-VHDL20_DWMO_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:29 422019
wst04-VHDL20_DWMO_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:18 435426
wst04-VHDL20_DWMO_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:14 435650
wst04-VHDL20_DWMO_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:18 436131
wst04-VHDL20_DWMP_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:22 524110
wst04-VHDL20_DWMP_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:32 539604
wst04-VHDL20_DWMP_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:13 539410
wst04-VHDL20_DWMP_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:18 539278
wst04-VHDL20_DWMP_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:29 540446
wst04-VHDL20_DWMP_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:33 540571
wst04-VHDL20_DWMP_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:14 540513
wst04-VHDL20_DWMP_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:18 539716
wst04-VHDL20_DWPG_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:58 358107
wst04-VHDL20_DWPG_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:31:23 317931
wst04-VHDL20_DWPG_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:35 227468
wst04-VHDL20_DWPG_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:35 317151
wst04-VHDL20_DWPG_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:47 362920
wst04-VHDL20_DWPG_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:31:23 317643
wst04-VHDL20_DWPG_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:40 228291
wst04-VHDL20_DWPG_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:32 317553
wst04-VHDL20_DWPH_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:58 226599
wst04-VHDL20_DWPH_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:31:23 227810
wst04-VHDL20_DWPH_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:35 227416
wst04-VHDL20_DWPH_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:35 227894
wst04-VHDL20_DWPH_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:43 228172
wst04-VHDL20_DWPH_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:31:23 227994
wst04-VHDL20_DWPH_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:40 227934
wst04-VHDL20_DWPH_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:32 228487
wst04-VHDL20_DWSG_040800-2611040800-omedes--0.pdf 04-Nov-2026 09:30:18 331414
wst04-VHDL20_DWSG_041800-2611041800-omedes--0.pdf 04-Nov-2026 19:30:11 335726
wst04-VHDL20_DWSG_050200-2611050200-omedes--0.pdf 05-Nov-2026 03:30:13 334574
wst04-VHDL20_DWSG_050400-2611050400-omedes--0.pdf 05-Nov-2026 06:00:14 334098
wst04-VHDL20_DWSG_050800-2611050800-omedes--0.pdf 05-Nov-2026 09:30:19 334082
wst04-VHDL20_DWSG_051800-2611051800-omedes--0.pdf 05-Nov-2026 19:30:17 330590
wst04-VHDL20_DWSG_060200-2611060200-omedes--0.pdf 06-Nov-2026 03:30:14 330307
wst04-VHDL20_DWSG_060400-2611060400-omedes--0.pdf 06-Nov-2026 06:00:14 329266