Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Dec-2025 12:14:03 3078
FPDL13_DWMZ_260600 26-Dec-2025 13:22:59 1807
SXDL31_DWAV_241800 24-Dec-2025 17:41:01 4605
SXDL31_DWAV_250800 25-Dec-2025 09:24:50 7494
SXDL31_DWAV_251800 25-Dec-2025 17:38:58 5434
SXDL31_DWAV_260800 26-Dec-2025 08:33:04 9993
SXDL31_DWAV_LATEST 26-Dec-2025 08:33:04 9993
SXDL33_DWAV_250000 25-Dec-2025 11:19:19 16571
SXDL33_DWAV_260000 26-Dec-2025 10:55:44 5445
SXDL33_DWAV_LATEST 26-Dec-2025 10:55:44 5445
ber01-FWDL39_DWMS_251230-2512251230-dsw--0-ia5 25-Dec-2025 12:30:36 1218
ber01-FWDL39_DWMS_261230-2512261230-dsw--0-ia5 26-Dec-2025 12:05:46 1069
ber01-VHDL13_DWEH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:28:17 3248
ber01-VHDL13_DWEH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:28:11 3218
ber01-VHDL13_DWEH_250400-2512250400-dsw--0-ia5 25-Dec-2025 05:58:11 3214
ber01-VHDL13_DWEH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:28:17 2955
ber01-VHDL13_DWEH_250800_COR-2512250800-dsw--0-ia5 25-Dec-2025 14:19:27 3071
ber01-VHDL13_DWEH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:28:16 2583
ber01-VHDL13_DWEH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:16 3351
ber01-VHDL13_DWEH_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:11 3309
ber01-VHDL13_DWEH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:16 3180
ber01-VHDL13_DWHG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:07 2867
ber01-VHDL13_DWHG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 3392
ber01-VHDL13_DWHG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:07 3428
ber01-VHDL13_DWHG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 3968
ber01-VHDL13_DWHG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 3408
ber01-VHDL13_DWHG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:09 3394
ber01-VHDL13_DWHG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3402
ber01-VHDL13_DWHG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 3385
ber01-VHDL13_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 10:02:31 3370
ber01-VHDL13_DWHH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:07 2772
ber01-VHDL13_DWHH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 3119
ber01-VHDL13_DWHH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:07 3122
ber01-VHDL13_DWHH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 3335
ber01-VHDL13_DWHH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 3125
ber01-VHDL13_DWHH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:09 3041
ber01-VHDL13_DWHH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3009
ber01-VHDL13_DWHH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2836
ber01-VHDL13_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 10:03:47 2813
ber01-VHDL13_DWLG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 2123
ber01-VHDL13_DWLG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 1993
ber01-VHDL13_DWLG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 1917
ber01-VHDL13_DWLG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 1914
ber01-VHDL13_DWLG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 1839
ber01-VHDL13_DWLG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2063
ber01-VHDL13_DWLG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2130
ber01-VHDL13_DWLG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2303
ber01-VHDL13_DWLH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 2064
ber01-VHDL13_DWLH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 1980
ber01-VHDL13_DWLH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 1904
ber01-VHDL13_DWLH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 1904
ber01-VHDL13_DWLH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 1663
ber01-VHDL13_DWLH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 1972
ber01-VHDL13_DWLH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2105
ber01-VHDL13_DWLH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2629
ber01-VHDL13_DWLI_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 2186
ber01-VHDL13_DWLI_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 2171
ber01-VHDL13_DWLI_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 1899
ber01-VHDL13_DWLI_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 1899
ber01-VHDL13_DWLI_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 1470
ber01-VHDL13_DWLI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 1763
ber01-VHDL13_DWLI_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2061
ber01-VHDL13_DWLI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2529
ber01-VHDL13_DWMG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 3346
ber01-VHDL13_DWMG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:01 3211
ber01-VHDL13_DWMG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 3214
ber01-VHDL13_DWMG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 3146
ber01-VHDL13_DWMG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 3135
ber01-VHDL13_DWMG_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:31 3139
ber01-VHDL13_DWMG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 3184
ber01-VHDL13_DWMG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 3202
ber01-VHDL13_DWMG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2885
ber01-VHDL13_DWMO_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 3821
ber01-VHDL13_DWMO_241800_COR-2512241800-dsw--0-ia5 24-Dec-2025 19:35:06 2931
ber01-VHDL13_DWMO_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:01 2951
ber01-VHDL13_DWMO_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 2951
ber01-VHDL13_DWMO_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 2577
ber01-VHDL13_DWMO_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 1925
ber01-VHDL13_DWMO_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:47 2405
ber01-VHDL13_DWMO_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2530
ber01-VHDL13_DWMO_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2548
ber01-VHDL13_DWMO_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2311
ber01-VHDL13_DWMP_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 3126
ber01-VHDL13_DWMP_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:01 3122
ber01-VHDL13_DWMP_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 3125
ber01-VHDL13_DWMP_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 2937
ber01-VHDL13_DWMP_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 2653
ber01-VHDL13_DWMP_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:37 3150
ber01-VHDL13_DWMP_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 3338
ber01-VHDL13_DWMP_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 3356
ber01-VHDL13_DWMP_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 3151
ber01-VHDL13_DWOG_241700-2512241700-dsw--0-ia5 24-Dec-2025 19:00:04 4657
ber01-VHDL13_DWOG_250300-2512250300-dsw--0-ia5 25-Dec-2025 04:00:02 5028
ber01-VHDL13_DWOG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 4942
ber01-VHDL13_DWOG_251700-2512251700-dsw--0-ia5 25-Dec-2025 19:00:03 3525
ber01-VHDL13_DWOG_260300-2512260300-dsw--0-ia5 26-Dec-2025 04:00:02 4631
ber01-VHDL13_DWOG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 4507
ber01-VHDL13_DWOG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 12:23:57 5146
ber01-VHDL13_DWOH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:28:17 3298
ber01-VHDL13_DWOH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:28:11 3240
ber01-VHDL13_DWOH_250400-2512250400-dsw--0-ia5 25-Dec-2025 05:58:17 3247
ber01-VHDL13_DWOH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:28:17 2953
ber01-VHDL13_DWOH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:28:16 2182
ber01-VHDL13_DWOH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:12 2664
ber01-VHDL13_DWOH_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:17 2622
ber01-VHDL13_DWOH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:16 2632
ber01-VHDL13_DWOI_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:28:11 3141
ber01-VHDL13_DWOI_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:28:17 2979
ber01-VHDL13_DWOI_250400-2512250400-dsw--0-ia5 25-Dec-2025 05:58:17 2867
ber01-VHDL13_DWOI_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:28:11 2617
ber01-VHDL13_DWOI_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:28:12 1994
ber01-VHDL13_DWOI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:12 2303
ber01-VHDL13_DWOI_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:17 2256
ber01-VHDL13_DWOI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:13 2290
ber01-VHDL13_DWON_241501-2512241501-dsw--0-ia5 24-Dec-2025 15:01:58 3913
ber01-VHDL13_DWON_241752-2512241752-dsw--0-ia5 24-Dec-2025 17:52:11 3881
ber01-VHDL13_DWON_242243-2512242243-dsw--0-ia5 24-Dec-2025 22:43:41 3677
ber01-VHDL13_DWON_250310-2512250310-dsw--0-ia5 25-Dec-2025 03:10:37 3855
ber01-VHDL13_DWON_250556-2512250556-dsw--0-ia5 25-Dec-2025 05:57:01 4271
ber01-VHDL13_DWON_250717-2512250717-dsw--0-ia5 25-Dec-2025 07:17:11 4271
ber01-VHDL13_DWON_250950-2512250950-dsw--0-ia5 25-Dec-2025 09:50:31 4271
ber01-VHDL13_DWON_251404-2512251404-dsw--0-ia5 25-Dec-2025 14:05:01 3904
ber01-VHDL13_DWON_251829-2512251829-dsw--0-ia5 25-Dec-2025 18:29:59 3695
ber01-VHDL13_DWON_252259-2512252259-dsw--0-ia5 25-Dec-2025 22:59:17 3561
ber01-VHDL13_DWON_252312-2512252312-dsw--0-ia5 25-Dec-2025 23:12:13 4315
ber01-VHDL13_DWON_260254-2512260254-dsw--0-ia5 26-Dec-2025 02:55:03 3792
ber01-VHDL13_DWON_260629-2512260629-dsw--0-ia5 26-Dec-2025 06:29:53 4238
ber01-VHDL13_DWON_260702-2512260702-dsw--0-ia5 26-Dec-2025 07:02:16 4274
ber01-VHDL13_DWON_261222-2512261222-dsw--0-ia5 26-Dec-2025 12:22:42 4352
ber01-VHDL13_DWPG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 1963
ber01-VHDL13_DWPG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 2040
ber01-VHDL13_DWPG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 1681
ber01-VHDL13_DWPG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 1680
ber01-VHDL13_DWPG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 2061
ber01-VHDL13_DWPG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2326
ber01-VHDL13_DWPG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2197
ber01-VHDL13_DWPG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2149
ber01-VHDL13_DWPH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 2114
ber01-VHDL13_DWPH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 2184
ber01-VHDL13_DWPH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:01 1831
ber01-VHDL13_DWPH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 1831
ber01-VHDL13_DWPH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 2004
ber01-VHDL13_DWPH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2136
ber01-VHDL13_DWPH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2177
ber01-VHDL13_DWPH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2486
ber01-VHDL13_DWSG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:30:02 3128
ber01-VHDL13_DWSG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:30:07 3298
ber01-VHDL13_DWSG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:07 3560
ber01-VHDL13_DWSG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:30:08 3387
ber01-VHDL13_DWSG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:30:10 2514
ber01-VHDL13_DWSG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:00 2980
ber01-VHDL13_DWSG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:07 2992
ber01-VHDL13_DWSG_260400_COR-2512260400-dsw--0-ia5 26-Dec-2025 06:17:51 3248
ber01-VHDL13_DWSG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 3245
ber01-VHDL17_DWOG_251200-2512251200-dsw--0-ia5 25-Dec-2025 12:18:31 4468
ber01-VHDL17_DWOG_261200-2512261200-dsw--0-ia5 26-Dec-2025 12:33:10 3947
swis2-VHDL20_DWEG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:07 3791
swis2-VHDL20_DWEG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 3684
swis2-VHDL20_DWEG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:15:07 3662
swis2-VHDL20_DWEG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:02 3620
swis2-VHDL20_DWEG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 2603
swis2-VHDL20_DWEG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3035
swis2-VHDL20_DWEG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 3043
swis2-VHDL20_DWEG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3382
swis2-VHDL20_DWEH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:07 3772
swis2-VHDL20_DWEH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 3707
swis2-VHDL20_DWEH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:15:07 3641
swis2-VHDL20_DWEH_250800-2512250800-dsw--0-ia5 25-Dec-2025 13:22:23 3817
swis2-VHDL20_DWEH_250800_COR-2512250800-dsw--0-ia5 25-Dec-2025 14:21:28 3946
swis2-VHDL20_DWEH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 3085
swis2-VHDL20_DWEH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3820
swis2-VHDL20_DWEH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 3935
swis2-VHDL20_DWEH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 4165
swis2-VHDL20_DWEI_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:07 3659
swis2-VHDL20_DWEI_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 3436
swis2-VHDL20_DWEI_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:15:07 3313
swis2-VHDL20_DWEI_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:02 3331
swis2-VHDL20_DWEI_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 2440
swis2-VHDL20_DWEI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 2690
swis2-VHDL20_DWEI_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 2708
swis2-VHDL20_DWEI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 2934
swis2-VHDL20_DWHG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:05 3050
swis2-VHDL20_DWHG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:04 3578
swis2-VHDL20_DWHG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:07 3611
swis2-VHDL20_DWHG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:06 4613
swis2-VHDL20_DWHG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 3591
swis2-VHDL20_DWHG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3580
swis2-VHDL20_DWHG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3585
swis2-VHDL20_DWHG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 4164
swis2-VHDL20_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 10:04:17 4146
swis2-VHDL20_DWHH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:05 2958
swis2-VHDL20_DWHH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:04 3305
swis2-VHDL20_DWHH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:07 3308
swis2-VHDL20_DWHH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:06 3992
swis2-VHDL20_DWHH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 3311
swis2-VHDL20_DWHH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3227
swis2-VHDL20_DWHH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3195
swis2-VHDL20_DWHH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3532
swis2-VHDL20_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 10:04:37 3506
swis2-VHDL20_DWLG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:03 2542
swis2-VHDL20_DWLG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 2403
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swis2-VHDL20_DWMP_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:01 3758
swis2-VHDL20_DWMP_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:02 3785
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swis2-VHDL20_DWPG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:03 2426
swis2-VHDL20_DWPG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 2376
swis2-VHDL20_DWPG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:11 2007
swis2-VHDL20_DWPG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:06 2149
swis2-VHDL20_DWPG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:04 2530
swis2-VHDL20_DWPG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:01 2655
swis2-VHDL20_DWPG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 2559
swis2-VHDL20_DWPG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 2712
swis2-VHDL20_DWPH_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:03 2576
swis2-VHDL20_DWPH_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:06 2518
swis2-VHDL20_DWPH_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:00:11 2159
swis2-VHDL20_DWPH_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:06 2290
swis2-VHDL20_DWPH_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:04 2463
swis2-VHDL20_DWPH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:01 2464
swis2-VHDL20_DWPH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 2505
swis2-VHDL20_DWPH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3058
swis2-VHDL20_DWSG_241300-2512241300-dsw--0-ia5 24-Dec-2025 14:45:10 4513
swis2-VHDL20_DWSG_241800-2512241800-dsw--0-ia5 24-Dec-2025 19:45:03 3583
swis2-VHDL20_DWSG_250200-2512250200-dsw--0-ia5 25-Dec-2025 03:45:04 3745
swis2-VHDL20_DWSG_250400-2512250400-dsw--0-ia5 25-Dec-2025 06:15:02 4026
swis2-VHDL20_DWSG_250800-2512250800-dsw--0-ia5 25-Dec-2025 09:45:06 4112
swis2-VHDL20_DWSG_251300-2512251300-dsw--0-ia5 25-Dec-2025 14:45:12 3882
swis2-VHDL20_DWSG_251800-2512251800-dsw--0-ia5 25-Dec-2025 19:45:06 2982
swis2-VHDL20_DWSG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3439
swis2-VHDL20_DWSG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:02 3401
swis2-VHDL20_DWSG_260400_COR-2512260400-dsw--0-ia5 26-Dec-2025 06:17:51 3614
swis2-VHDL20_DWSG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3769
wst04-VHDL20_DWEG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:11 230767
wst04-VHDL20_DWEG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:16 231115
wst04-VHDL20_DWEG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:21 230762
wst04-VHDL20_DWEG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:22 220060
wst04-VHDL20_DWEG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:16 216232
wst04-VHDL20_DWEG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 217593
wst04-VHDL20_DWEG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 217041
wst04-VHDL20_DWEG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:22 227182
wst04-VHDL20_DWEH_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:11 222564
wst04-VHDL20_DWEH_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:16 223288
wst04-VHDL20_DWEH_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:27 222558
wst04-VHDL20_DWEH_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:22 217610
wst04-VHDL20_DWEH_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:16 215639
wst04-VHDL20_DWEH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 217582
wst04-VHDL20_DWEH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:26 217406
wst04-VHDL20_DWEH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:22 225450
wst04-VHDL20_DWEI_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:17 314347
wst04-VHDL20_DWEI_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:16 313728
wst04-VHDL20_DWEI_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:27 313713
wst04-VHDL20_DWEI_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:26 291254
wst04-VHDL20_DWEI_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:16 288816
wst04-VHDL20_DWEI_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 289607
wst04-VHDL20_DWEI_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:26 289502
wst04-VHDL20_DWEI_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:26 309233
wst04-VHDL20_DWHG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:21 303107
wst04-VHDL20_DWHG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:12 303889
wst04-VHDL20_DWHG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:11 303883
wst04-VHDL20_DWHG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:16 309545
wst04-VHDL20_DWHG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:16 306827
wst04-VHDL20_DWHG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 306726
wst04-VHDL20_DWHG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:11 306804
wst04-VHDL20_DWHG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 311638
wst04-VHDL20_DWHH_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:21 296823
wst04-VHDL20_DWHH_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:12 298061
wst04-VHDL20_DWHH_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:11 298091
wst04-VHDL20_DWHH_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:22 303621
wst04-VHDL20_DWHH_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:22 302120
wst04-VHDL20_DWHH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 302081
wst04-VHDL20_DWHH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:11 302162
wst04-VHDL20_DWHH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:22 305922
wst04-VHDL20_DWLG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:27 302266
wst04-VHDL20_DWLG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:20 301594
wst04-VHDL20_DWLG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:40 301408
wst04-VHDL20_DWLG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:30 294118
wst04-VHDL20_DWLG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:22 293368
wst04-VHDL20_DWLG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 294178
wst04-VHDL20_DWLG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 293819
wst04-VHDL20_DWLG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 295621
wst04-VHDL20_DWLH_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:21 298879
wst04-VHDL20_DWLH_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:26 298750
wst04-VHDL20_DWLH_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:40 297997
wst04-VHDL20_DWLH_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:30 297898
wst04-VHDL20_DWLH_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:26 297214
wst04-VHDL20_DWLH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:26 297730
wst04-VHDL20_DWLH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 297884
wst04-VHDL20_DWLH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 300213
wst04-VHDL20_DWLI_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:21 301491
wst04-VHDL20_DWLI_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:26 300983
wst04-VHDL20_DWLI_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:40 301051
wst04-VHDL20_DWLI_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:30 290782
wst04-VHDL20_DWLI_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:26 289701
wst04-VHDL20_DWLI_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 290051
wst04-VHDL20_DWLI_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 290292
wst04-VHDL20_DWLI_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 300816
wst04-VHDL20_DWMG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:17 486302
wst04-VHDL20_DWMG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:16 486286
wst04-VHDL20_DWMG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:21 486114
wst04-VHDL20_DWMG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:16 477026
wst04-VHDL20_DWMG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:16 476283
wst04-VHDL20_DWMG_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:37 476283
wst04-VHDL20_DWMG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 476302
wst04-VHDL20_DWMG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 476195
wst04-VHDL20_DWMG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 486489
wst04-VHDL20_DWMO_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:17 394137
wst04-VHDL20_DWMO_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:16 393897
wst04-VHDL20_DWMO_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:17 394273
wst04-VHDL20_DWMO_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:12 392087
wst04-VHDL20_DWMO_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:12 390201
wst04-VHDL20_DWMO_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:51 390201
wst04-VHDL20_DWMO_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:18 390898
wst04-VHDL20_DWMO_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 391384
wst04-VHDL20_DWMO_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:12 397869
wst04-VHDL20_DWMP_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:17 499291
wst04-VHDL20_DWMP_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:22 498430
wst04-VHDL20_DWMP_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:21 499546
wst04-VHDL20_DWMP_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:16 492111
wst04-VHDL20_DWMP_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:12 491459
wst04-VHDL20_DWMP_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:47 491459
wst04-VHDL20_DWMP_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:18 490318
wst04-VHDL20_DWMP_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 491523
wst04-VHDL20_DWMP_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 492902
wst04-VHDL20_DWPG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:27 299343
wst04-VHDL20_DWPG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:26 298935
wst04-VHDL20_DWPG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:31 298149
wst04-VHDL20_DWPG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:30 347094
wst04-VHDL20_DWPG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:22 303135
wst04-VHDL20_DWPG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:26 303324
wst04-VHDL20_DWPG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:31 303183
wst04-VHDL20_DWPG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 355557
wst04-VHDL20_DWPH_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:21 263734
wst04-VHDL20_DWPH_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:20 218779
wst04-VHDL20_DWPH_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:00:31 218820
wst04-VHDL20_DWPH_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:26 270672
wst04-VHDL20_DWPH_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:22 270707
wst04-VHDL20_DWPH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 226467
wst04-VHDL20_DWPH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:31 225685
wst04-VHDL20_DWPH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:26 268530
wst04-VHDL20_DWSG_241300-2512241300-omedes--0.pdf 24-Dec-2025 14:45:15 313160
wst04-VHDL20_DWSG_241800-2512241800-omedes--0.pdf 24-Dec-2025 19:45:11 311174
wst04-VHDL20_DWSG_250200-2512250200-omedes--0.pdf 25-Dec-2025 03:45:12 311739
wst04-VHDL20_DWSG_250400-2512250400-omedes--0.pdf 25-Dec-2025 06:15:17 312256
wst04-VHDL20_DWSG_250800-2512250800-omedes--0.pdf 25-Dec-2025 09:45:12 303553
wst04-VHDL20_DWSG_251300-2512251300-omedes--0.pdf 25-Dec-2025 14:45:12 303496
wst04-VHDL20_DWSG_251800-2512251800-omedes--0.pdf 25-Dec-2025 19:45:12 302511
wst04-VHDL20_DWSG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 302504
wst04-VHDL20_DWSG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:16 303072
wst04-VHDL20_DWSG_260400_COR-2512260400-omedes-..> 26-Dec-2025 06:18:01 303883
wst04-VHDL20_DWSG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:12 308699