Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Mar-2026 14:47:32 2850
FPDL13_DWMZ_060600 06-Mar-2026 14:14:59 3268
SXDL31_DWAV_051800 05-Mar-2026 17:04:58 6604
SXDL31_DWAV_060800 06-Mar-2026 09:05:08 12624
SXDL31_DWAV_061800 06-Mar-2026 17:12:33 3429
SXDL31_DWAV_070800 07-Mar-2026 08:01:15 5839
SXDL31_DWAV_LATEST 07-Mar-2026 08:01:15 5839
SXDL33_DWAV_060000 06-Mar-2026 10:27:55 5630
SXDL33_DWAV_070000 07-Mar-2026 10:22:00 11482
SXDL33_DWAV_LATEST 07-Mar-2026 10:22:00 11482
ber01-FWDL39_DWMS_051230-2603051230-dsw--0-ia5 05-Mar-2026 12:18:17 1910
ber01-FWDL39_DWMS_061230-2603061230-dsw--0-ia5 06-Mar-2026 13:07:21 1332
ber01-VHDL13_DWEH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:28:16 2061
ber01-VHDL13_DWEH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:11 2259
ber01-VHDL13_DWEH_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:17 2474
ber01-VHDL13_DWEH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:16 2477
ber01-VHDL13_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2559
ber01-VHDL13_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2590
ber01-VHDL13_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2442
ber01-VHDL13_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2445
ber01-VHDL13_DWHG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:08 2355
ber01-VHDL13_DWHG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2754
ber01-VHDL13_DWHG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2679
ber01-VHDL13_DWHG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2727
ber01-VHDL13_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2424
ber01-VHDL13_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2735
ber01-VHDL13_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2897
ber01-VHDL13_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2897
ber01-VHDL13_DWHH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:08 1997
ber01-VHDL13_DWHH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2368
ber01-VHDL13_DWHH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2368
ber01-VHDL13_DWHH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2536
ber01-VHDL13_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2305
ber01-VHDL13_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2474
ber01-VHDL13_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2476
ber01-VHDL13_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2520
ber01-VHDL13_DWLG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 1445
ber01-VHDL13_DWLG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1686
ber01-VHDL13_DWLG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1555
ber01-VHDL13_DWLG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1616
ber01-VHDL13_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1541
ber01-VHDL13_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1718
ber01-VHDL13_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1927
ber01-VHDL13_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:07 2088
ber01-VHDL13_DWLH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 1673
ber01-VHDL13_DWLH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1669
ber01-VHDL13_DWLH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1598
ber01-VHDL13_DWLH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1747
ber01-VHDL13_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2015
ber01-VHDL13_DWLH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1937
ber01-VHDL13_DWLH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2129
ber01-VHDL13_DWLH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2155
ber01-VHDL13_DWLI_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 1720
ber01-VHDL13_DWLI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1760
ber01-VHDL13_DWLI_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1458
ber01-VHDL13_DWLI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1518
ber01-VHDL13_DWLI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1512
ber01-VHDL13_DWLI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1711
ber01-VHDL13_DWLI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1801
ber01-VHDL13_DWLI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 1944
ber01-VHDL13_DWMG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 2198
ber01-VHDL13_DWMG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2136
ber01-VHDL13_DWMG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2147
ber01-VHDL13_DWMG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 1928
ber01-VHDL13_DWMG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2370
ber01-VHDL13_DWMG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2370
ber01-VHDL13_DWMG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2320
ber01-VHDL13_DWMG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2202
ber01-VHDL13_DWMO_050800_COR-2603050800-dsw--0-ia5 05-Mar-2026 12:00:42 2721
ber01-VHDL13_DWMO_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 2381
ber01-VHDL13_DWMO_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2308
ber01-VHDL13_DWMO_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2308
ber01-VHDL13_DWMO_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2177
ber01-VHDL13_DWMO_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2302
ber01-VHDL13_DWMO_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2435
ber01-VHDL13_DWMO_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2435
ber01-VHDL13_DWMO_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2322
ber01-VHDL13_DWMP_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 2280
ber01-VHDL13_DWMP_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2329
ber01-VHDL13_DWMP_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2329
ber01-VHDL13_DWMP_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2183
ber01-VHDL13_DWMP_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2283
ber01-VHDL13_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2412
ber01-VHDL13_DWMP_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2412
ber01-VHDL13_DWMP_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2279
ber01-VHDL13_DWOG_051700-2603051700-dsw--0-ia5 05-Mar-2026 19:00:02 3334
ber01-VHDL13_DWOG_060300-2603060300-dsw--0-ia5 06-Mar-2026 04:00:01 3645
ber01-VHDL13_DWOG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 3261
ber01-VHDL13_DWOG_061700-2603061700-dsw--0-ia5 06-Mar-2026 19:00:06 3023
ber01-VHDL13_DWOG_070300-2603070300-dsw--0-ia5 07-Mar-2026 04:00:01 3613
ber01-VHDL13_DWOG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 3484
ber01-VHDL13_DWOH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:28:16 2203
ber01-VHDL13_DWOH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:11 2496
ber01-VHDL13_DWOH_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:11 2498
ber01-VHDL13_DWOH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:16 2478
ber01-VHDL13_DWOH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2410
ber01-VHDL13_DWOH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2650
ber01-VHDL13_DWOH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2599
ber01-VHDL13_DWOH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2521
ber01-VHDL13_DWOI_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:28:12 2172
ber01-VHDL13_DWOI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:18 2352
ber01-VHDL13_DWOI_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:17 2270
ber01-VHDL13_DWOI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:12 2276
ber01-VHDL13_DWOI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2167
ber01-VHDL13_DWOI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:17 2367
ber01-VHDL13_DWOI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:08:07 2274
ber01-VHDL13_DWOI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2280
ber01-VHDL13_DWON_051533-2603051533-dsw--0-ia5 05-Mar-2026 15:33:17 3103
ber01-VHDL13_DWON_051812-2603051812-dsw--0-ia5 05-Mar-2026 18:12:58 3053
ber01-VHDL13_DWON_051822-2603051822-dsw--0-ia5 05-Mar-2026 18:22:42 3053
ber01-VHDL13_DWON_052144-2603052144-dsw--0-ia5 05-Mar-2026 21:44:52 3027
ber01-VHDL13_DWON_060228-2603060228-dsw--0-ia5 06-Mar-2026 02:28:41 3293
ber01-VHDL13_DWON_060314-2603060314-dsw--0-ia5 06-Mar-2026 03:14:06 3293
ber01-VHDL13_DWON_060624-2603060624-dsw--0-ia5 06-Mar-2026 06:24:37 3687
ber01-VHDL13_DWON_060629-2603060629-dsw--0-ia5 06-Mar-2026 06:29:21 3514
ber01-VHDL13_DWON_060714-2603060714-dsw--0-ia5 06-Mar-2026 07:14:31 3365
ber01-VHDL13_DWON_061157-2603061157-dsw--0-ia5 06-Mar-2026 11:57:38 3365
ber01-VHDL13_DWON_061537-2603061537-dsw--0-ia5 06-Mar-2026 15:37:43 2935
ber01-VHDL13_DWON_061712-2603061712-dsw--0-ia5 06-Mar-2026 17:12:58 2935
ber01-VHDL13_DWON_061726-2603061726-dsw--0-ia5 06-Mar-2026 17:26:17 3145
ber01-VHDL13_DWON_062246-2603062246-dsw--0-ia5 06-Mar-2026 22:46:25 3207
ber01-VHDL13_DWON_070131-2603070131-dsw--0-ia5 07-Mar-2026 01:31:30 3260
ber01-VHDL13_DWON_070426-2603070426-dsw--0-ia5 07-Mar-2026 04:26:47 3260
ber01-VHDL13_DWON_070545-2603070545-dsw--0-ia5 07-Mar-2026 05:45:12 3440
ber01-VHDL13_DWON_071002-2603071002-dsw--0-ia5 07-Mar-2026 10:02:17 3440
ber01-VHDL13_DWPG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 1681
ber01-VHDL13_DWPG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1738
ber01-VHDL13_DWPG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1685
ber01-VHDL13_DWPG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1831
ber01-VHDL13_DWPG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1848
ber01-VHDL13_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1829
ber01-VHDL13_DWPG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2243
ber01-VHDL13_DWPG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2115
ber01-VHDL13_DWPH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 1739
ber01-VHDL13_DWPH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2085
ber01-VHDL13_DWPH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1982
ber01-VHDL13_DWPH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2143
ber01-VHDL13_DWPH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2034
ber01-VHDL13_DWPH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1780
ber01-VHDL13_DWPH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2278
ber01-VHDL13_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2191
ber01-VHDL13_DWSG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:30:04 2300
ber01-VHDL13_DWSG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2449
ber01-VHDL13_DWSG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:06 2494
ber01-VHDL13_DWSG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2389
ber01-VHDL13_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2101
ber01-VHDL13_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2400
ber01-VHDL13_DWSG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2484
ber01-VHDL13_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2393
ber01-VHDL17_DWOG_051200-2603051200-dsw--0-ia5 05-Mar-2026 15:31:49 2507
ber01-VHDL17_DWOG_061200-2603061200-dsw--0-ia5 06-Mar-2026 12:02:46 1871
ber01-VHDL17_DWOG_071200-2603071200-dsw--0-ia5 07-Mar-2026 10:53:51 3549
swis2-VHDL20_DWEG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:04 2529
swis2-VHDL20_DWEG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2772
swis2-VHDL20_DWEG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2818
swis2-VHDL20_DWEG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2953
swis2-VHDL20_DWEG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2736
swis2-VHDL20_DWEG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2926
swis2-VHDL20_DWEG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2919
swis2-VHDL20_DWEG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2995
swis2-VHDL20_DWEH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:04 2415
swis2-VHDL20_DWEH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2580
swis2-VHDL20_DWEH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2809
swis2-VHDL20_DWEH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2977
swis2-VHDL20_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2913
swis2-VHDL20_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2911
swis2-VHDL20_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2777
swis2-VHDL20_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2944
swis2-VHDL20_DWEI_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:04 2523
swis2-VHDL20_DWEI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2644
swis2-VHDL20_DWEI_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2621
swis2-VHDL20_DWEI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2798
swis2-VHDL20_DWEI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2518
swis2-VHDL20_DWEI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2659
swis2-VHDL20_DWEI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2625
swis2-VHDL20_DWEI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2801
swis2-VHDL20_DWHG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:06 2538
swis2-VHDL20_DWHG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2940
swis2-VHDL20_DWHG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2862
swis2-VHDL20_DWHG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 3263
swis2-VHDL20_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2607
swis2-VHDL20_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2921
swis2-VHDL20_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 3080
swis2-VHDL20_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3428
swis2-VHDL20_DWHH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:06 2183
swis2-VHDL20_DWHH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2554
swis2-VHDL20_DWHH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2554
swis2-VHDL20_DWHH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 3083
swis2-VHDL20_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2491
swis2-VHDL20_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2660
swis2-VHDL20_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2662
swis2-VHDL20_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3063
swis2-VHDL20_DWLG_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:04 1790
swis2-VHDL20_DWLG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2031
swis2-VHDL20_DWLG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 1897
swis2-VHDL20_DWLG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2104
swis2-VHDL20_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 1883
swis2-VHDL20_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2060
swis2-VHDL20_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2269
swis2-VHDL20_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2574
swis2-VHDL20_DWLH_051800-2603051800-dsw--0-ia5 05-Mar-2026 19:45:04 2025
swis2-VHDL20_DWLH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2021
swis2-VHDL20_DWLH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 1946
swis2-VHDL20_DWLH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2245
swis2-VHDL20_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2363
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swis2-VHDL20_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2805
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swis2-VHDL20_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2158
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swis2-VHDL20_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2649
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swis2-VHDL20_DWSG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:07 2796
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swis2-VHDL20_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2455
swis2-VHDL20_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2745
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swis2-VHDL20_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2888
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wst04-VHDL20_DWLH_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 353863
wst04-VHDL20_DWLH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:42 353765
wst04-VHDL20_DWLH_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 354553
wst04-VHDL20_DWLH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 354103
wst04-VHDL20_DWLH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 354351
wst04-VHDL20_DWLH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 354460
wst04-VHDL20_DWLH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 347549
wst04-VHDL20_DWLI_051800-2603051800-omedes--0.pdf 05-Mar-2026 19:45:26 354737
wst04-VHDL20_DWLI_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 354824
wst04-VHDL20_DWLI_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:42 354630
wst04-VHDL20_DWLI_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 346059
wst04-VHDL20_DWLI_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 345613
wst04-VHDL20_DWLI_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 345315
wst04-VHDL20_DWLI_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 345308
wst04-VHDL20_DWLI_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 343395
wst04-VHDL20_DWMG_051800-2603051800-omedes--0.pdf 05-Mar-2026 19:45:16 584121
wst04-VHDL20_DWMG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:16 584735
wst04-VHDL20_DWMG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:22 584986
wst04-VHDL20_DWMG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 581717
wst04-VHDL20_DWMG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 581388
wst04-VHDL20_DWMG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 581559
wst04-VHDL20_DWMG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 581767
wst04-VHDL20_DWMG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 588174
wst04-VHDL20_DWMO_050800_COR-2603050800-omedes-..> 05-Mar-2026 12:00:52 485482
wst04-VHDL20_DWMO_051800-2603051800-omedes--0.pdf 05-Mar-2026 19:45:16 483548
wst04-VHDL20_DWMO_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:11 484158
wst04-VHDL20_DWMO_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:16 485329
wst04-VHDL20_DWMO_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:12 482693
wst04-VHDL20_DWMO_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 481633
wst04-VHDL20_DWMO_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 482319
wst04-VHDL20_DWMO_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:21 482745
wst04-VHDL20_DWMO_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 476714
wst04-VHDL20_DWMP_051800-2603051800-omedes--0.pdf 05-Mar-2026 19:45:16 578180
wst04-VHDL20_DWMP_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:11 577812
wst04-VHDL20_DWMP_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:22 578699
wst04-VHDL20_DWMP_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 569755
wst04-VHDL20_DWMP_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 569532
wst04-VHDL20_DWMP_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 568482
wst04-VHDL20_DWMP_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 569323
wst04-VHDL20_DWMP_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 573450
wst04-VHDL20_DWPG_051800-2603051800-omedes--0.pdf 05-Mar-2026 19:45:26 354809
wst04-VHDL20_DWPG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 354517
wst04-VHDL20_DWPG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:30 354431
wst04-VHDL20_DWPG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:36 400648
wst04-VHDL20_DWPG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 355913
wst04-VHDL20_DWPG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 356233
wst04-VHDL20_DWPG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:31 356676
wst04-VHDL20_DWPG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:37 403974
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wst04-VHDL20_DWPH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:30 250436
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wst04-VHDL20_DWPH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 296230
wst04-VHDL20_DWPH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 251473
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wst04-VHDL20_DWSG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:16 364422
wst04-VHDL20_DWSG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:12 364782
wst04-VHDL20_DWSG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:12 367425
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wst04-VHDL20_DWSG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:17 367503
wst04-VHDL20_DWSG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:11 360470