Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_200600 20-Dec-2025 13:49:35 4625
FPDL13_DWMZ_210600 21-Dec-2025 11:50:49 3475
SXDL31_DWAV_200800 20-Dec-2025 09:06:33 12820
SXDL31_DWAV_201800 20-Dec-2025 17:31:30 6288
SXDL31_DWAV_210800 21-Dec-2025 09:41:59 13747
SXDL31_DWAV_211800 21-Dec-2025 16:45:39 7183
SXDL31_DWAV_LATEST 21-Dec-2025 16:45:39 7183
SXDL33_DWAV_200000 20-Dec-2025 10:11:53 9222
SXDL33_DWAV_210000 21-Dec-2025 09:21:05 7849
SXDL33_DWAV_LATEST 21-Dec-2025 09:21:05 7849
ber01-FWDL39_DWMS_201230-2512201230-dsw--0-ia5 20-Dec-2025 12:17:06 1197
ber01-FWDL39_DWMS_211230-2512211230-dsw--0-ia5 21-Dec-2025 12:13:32 1195
ber01-VHDL13_DWEH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:16 2592
ber01-VHDL13_DWEH_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:22 3261
ber01-VHDL13_DWEH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:28:16 3057
ber01-VHDL13_DWEH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:28:11 3564
ber01-VHDL13_DWEH_210400-2512210400-dsw--0-ia5 21-Dec-2025 05:58:11 3416
ber01-VHDL13_DWEH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:28:17 3416
ber01-VHDL13_DWEH_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:27 3386
ber01-VHDL13_DWEH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:28:17 3272
ber01-VHDL13_DWEH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:28:11 3264
ber01-VHDL13_DWEH_220400-2512220400-dsw--0-ia5 22-Dec-2025 05:58:16 3317
ber01-VHDL13_DWHG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 2957
ber01-VHDL13_DWHG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:10 2823
ber01-VHDL13_DWHG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 3184
ber01-VHDL13_DWHG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:12 3184
ber01-VHDL13_DWHG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 3241
ber01-VHDL13_DWHG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:08 2933
ber01-VHDL13_DWHG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:07 3130
ber01-VHDL13_DWHG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:08 3130
ber01-VHDL13_DWHH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 2675
ber01-VHDL13_DWHH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:10 2531
ber01-VHDL13_DWHH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2507
ber01-VHDL13_DWHH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:12 2507
ber01-VHDL13_DWHH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 2480
ber01-VHDL13_DWHH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:08 2715
ber01-VHDL13_DWHH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:07 2980
ber01-VHDL13_DWHH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:08 2980
ber01-VHDL13_DWLG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2680
ber01-VHDL13_DWLG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 2381
ber01-VHDL13_DWLG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2750
ber01-VHDL13_DWLG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:06 2666
ber01-VHDL13_DWLG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 2908
ber01-VHDL13_DWLG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2930
ber01-VHDL13_DWLG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3220
ber01-VHDL13_DWLG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 2954
ber01-VHDL13_DWLH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2190
ber01-VHDL13_DWLH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 1989
ber01-VHDL13_DWLH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2217
ber01-VHDL13_DWLH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:06 2279
ber01-VHDL13_DWLH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 2345
ber01-VHDL13_DWLH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2344
ber01-VHDL13_DWLH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 2915
ber01-VHDL13_DWLH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 2717
ber01-VHDL13_DWLI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2435
ber01-VHDL13_DWLI_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 2291
ber01-VHDL13_DWLI_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2859
ber01-VHDL13_DWLI_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:06 2769
ber01-VHDL13_DWLI_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 2966
ber01-VHDL13_DWLI_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 14:04:46 2922
ber01-VHDL13_DWLI_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2834
ber01-VHDL13_DWLI_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3186
ber01-VHDL13_DWLI_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 2873
ber01-VHDL13_DWMG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3395
ber01-VHDL13_DWMG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 2999
ber01-VHDL13_DWMG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:02 3418
ber01-VHDL13_DWMG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:02 3451
ber01-VHDL13_DWMG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 3319
ber01-VHDL13_DWMG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2865
ber01-VHDL13_DWMG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3473
ber01-VHDL13_DWMG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 3491
ber01-VHDL13_DWMO_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3442
ber01-VHDL13_DWMO_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 3008
ber01-VHDL13_DWMO_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:02 3568
ber01-VHDL13_DWMO_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:02 3501
ber01-VHDL13_DWMO_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 3328
ber01-VHDL13_DWMO_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2910
ber01-VHDL13_DWMO_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3455
ber01-VHDL13_DWMO_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 3383
ber01-VHDL13_DWMP_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3186
ber01-VHDL13_DWMP_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 2895
ber01-VHDL13_DWMP_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:02 3387
ber01-VHDL13_DWMP_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:02 3373
ber01-VHDL13_DWMP_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 3405
ber01-VHDL13_DWMP_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2804
ber01-VHDL13_DWMP_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3499
ber01-VHDL13_DWMP_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 3433
ber01-VHDL13_DWOG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:09 3915
ber01-VHDL13_DWOG_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 12:50:40 3721
ber01-VHDL13_DWOG_201700-2512201700-dsw--0-ia5 20-Dec-2025 19:00:03 3557
ber01-VHDL13_DWOG_210300-2512210300-dsw--0-ia5 21-Dec-2025 04:00:06 4360
ber01-VHDL13_DWOG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 4409
ber01-VHDL13_DWOG_211700-2512211700-dsw--0-ia5 21-Dec-2025 19:00:01 3789
ber01-VHDL13_DWOG_220300-2512220300-dsw--0-ia5 22-Dec-2025 04:00:01 4211
ber01-VHDL13_DWOH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:16 2393
ber01-VHDL13_DWOH_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:22 2951
ber01-VHDL13_DWOH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:28:16 2876
ber01-VHDL13_DWOH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:28:11 3333
ber01-VHDL13_DWOH_210400-2512210400-dsw--0-ia5 21-Dec-2025 05:58:16 3347
ber01-VHDL13_DWOH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:28:17 3347
ber01-VHDL13_DWOH_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:27 3483
ber01-VHDL13_DWOH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:28:17 3281
ber01-VHDL13_DWOH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:28:11 3345
ber01-VHDL13_DWOH_220400-2512220400-dsw--0-ia5 22-Dec-2025 05:58:10 3342
ber01-VHDL13_DWOI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:28:12 2335
ber01-VHDL13_DWOI_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:22 2928
ber01-VHDL13_DWOI_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:28:12 2769
ber01-VHDL13_DWOI_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:28:17 3261
ber01-VHDL13_DWOI_210400-2512210400-dsw--0-ia5 21-Dec-2025 05:58:16 3335
ber01-VHDL13_DWOI_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:28:12 3341
ber01-VHDL13_DWOI_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:27 3437
ber01-VHDL13_DWOI_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:28:11 3179
ber01-VHDL13_DWOI_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:28:17 3193
ber01-VHDL13_DWOI_220400-2512220400-dsw--0-ia5 22-Dec-2025 05:58:16 3175
ber01-VHDL13_DWON_200725-2512200725-dsw--0-ia5 20-Dec-2025 07:25:23 3767
ber01-VHDL13_DWON_201250-2512201250-dsw--0-ia5 20-Dec-2025 12:50:12 3739
ber01-VHDL13_DWON_201533-2512201533-dsw--0-ia5 20-Dec-2025 15:33:57 3366
ber01-VHDL13_DWON_201820-2512201820-dsw--0-ia5 20-Dec-2025 18:20:57 3366
ber01-VHDL13_DWON_201833-2512201833-dsw--0-ia5 20-Dec-2025 18:33:56 3427
ber01-VHDL13_DWON_202012-2512202012-dsw--0-ia5 20-Dec-2025 20:12:47 3449
ber01-VHDL13_DWON_210016-2512210016-dsw--0-ia5 21-Dec-2025 00:16:52 3515
ber01-VHDL13_DWON_210354-2512210354-dsw--0-ia5 21-Dec-2025 03:54:12 3515
ber01-VHDL13_DWON_210622-2512210622-dsw--0-ia5 21-Dec-2025 06:22:07 3522
ber01-VHDL13_DWON_210952-2512210952-dsw--0-ia5 21-Dec-2025 09:52:31 4127
ber01-VHDL13_DWON_211402-2512211402-dsw--0-ia5 21-Dec-2025 14:02:57 3484
ber01-VHDL13_DWON_211831-2512211831-dsw--0-ia5 21-Dec-2025 18:31:58 3252
ber01-VHDL13_DWON_212244-2512212244-dsw--0-ia5 21-Dec-2025 22:44:07 3252
ber01-VHDL13_DWON_212323-2512212323-dsw--0-ia5 21-Dec-2025 23:23:48 3680
ber01-VHDL13_DWON_212337-2512212337-dsw--0-ia5 21-Dec-2025 23:37:27 3718
ber01-VHDL13_DWON_220109-2512220109-dsw--0-ia5 22-Dec-2025 01:09:21 3718
ber01-VHDL13_DWON_220626-2512220626-dsw--0-ia5 22-Dec-2025 06:26:07 3583
ber01-VHDL13_DWPG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 1868
ber01-VHDL13_DWPG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 1698
ber01-VHDL13_DWPG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2021
ber01-VHDL13_DWPG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:06 1983
ber01-VHDL13_DWPG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 1934
ber01-VHDL13_DWPG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 1768
ber01-VHDL13_DWPG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 2037
ber01-VHDL13_DWPG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 2123
ber01-VHDL13_DWPH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 2051
ber01-VHDL13_DWPH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 2120
ber01-VHDL13_DWPH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:08 2387
ber01-VHDL13_DWPH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:06 2553
ber01-VHDL13_DWPH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 2648
ber01-VHDL13_DWPH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 2305
ber01-VHDL13_DWPH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 2546
ber01-VHDL13_DWPH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:02 2965
ber01-VHDL13_DWSG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:30:04 3345
ber01-VHDL13_DWSG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:30:02 3023
ber01-VHDL13_DWSG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:30:02 3382
ber01-VHDL13_DWSG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:08 3434
ber01-VHDL13_DWSG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:30:07 3403
ber01-VHDL13_DWSG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:30:02 3526
ber01-VHDL13_DWSG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:30:01 3629
ber01-VHDL13_DWSG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:06 3469
ber01-VHDL17_DWOG_201200-2512201200-dsw--0-ia5 20-Dec-2025 11:44:31 3168
ber01-VHDL17_DWOG_211200-2512211200-dsw--0-ia5 21-Dec-2025 12:01:36 2767
swis2-VHDL20_DWEG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3356
swis2-VHDL20_DWEG_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:12 3541
swis2-VHDL20_DWEG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:06 3205
swis2-VHDL20_DWEG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3612
swis2-VHDL20_DWEG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:07 3761
swis2-VHDL20_DWEG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 4083
swis2-VHDL20_DWEG_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:08 3662
swis2-VHDL20_DWEG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3670
swis2-VHDL20_DWEG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3684
swis2-VHDL20_DWEG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:06 3913
swis2-VHDL20_DWEH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3563
swis2-VHDL20_DWEH_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:12 3879
swis2-VHDL20_DWEH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:06 3414
swis2-VHDL20_DWEH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3888
swis2-VHDL20_DWEH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:07 3845
swis2-VHDL20_DWEH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 4025
swis2-VHDL20_DWEH_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:08 3564
swis2-VHDL20_DWEH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3702
swis2-VHDL20_DWEH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3662
swis2-VHDL20_DWEH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:06 3882
swis2-VHDL20_DWEI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3201
swis2-VHDL20_DWEI_200800_COR-2512200800-dsw--0-ia5 20-Dec-2025 14:54:12 3565
swis2-VHDL20_DWEI_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:06 3123
swis2-VHDL20_DWEI_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3556
swis2-VHDL20_DWEI_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:07 3780
swis2-VHDL20_DWEI_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 4085
swis2-VHDL20_DWEI_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 09:33:08 3616
swis2-VHDL20_DWEI_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3594
swis2-VHDL20_DWEI_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3550
swis2-VHDL20_DWEI_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:06 3645
swis2-VHDL20_DWHG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3484
swis2-VHDL20_DWHG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 3006
swis2-VHDL20_DWHG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3370
swis2-VHDL20_DWHG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:12 3367
swis2-VHDL20_DWHG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:06 3775
swis2-VHDL20_DWHG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:06 3116
swis2-VHDL20_DWHG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 3316
swis2-VHDL20_DWHG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:08 3313
swis2-VHDL20_DWHH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3214
swis2-VHDL20_DWHH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2717
swis2-VHDL20_DWHH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 2693
swis2-VHDL20_DWHH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:12 2693
swis2-VHDL20_DWHH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:06 3022
swis2-VHDL20_DWHH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:06 2898
swis2-VHDL20_DWHH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 3166
swis2-VHDL20_DWHH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:08 3166
swis2-VHDL20_DWLG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 3160
swis2-VHDL20_DWLG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2719
swis2-VHDL20_DWLG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3091
swis2-VHDL20_DWLG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:16 3004
swis2-VHDL20_DWLG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 3447
swis2-VHDL20_DWLG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3268
swis2-VHDL20_DWLG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 3561
swis2-VHDL20_DWLG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:17 3351
swis2-VHDL20_DWLH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2681
swis2-VHDL20_DWLH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2334
swis2-VHDL20_DWLH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 2565
swis2-VHDL20_DWLH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:12 2624
swis2-VHDL20_DWLH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 2900
swis2-VHDL20_DWLH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 2689
swis2-VHDL20_DWLH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 3263
swis2-VHDL20_DWLH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:17 3139
swis2-VHDL20_DWLI_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2915
swis2-VHDL20_DWLI_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2631
swis2-VHDL20_DWLI_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3202
swis2-VHDL20_DWLI_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:16 3108
swis2-VHDL20_DWLI_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 3511
swis2-VHDL20_DWLI_210800_COR-2512210800-dsw--0-ia5 21-Dec-2025 14:05:22 3467
swis2-VHDL20_DWLI_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3173
swis2-VHDL20_DWLI_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 3528
swis2-VHDL20_DWLI_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:17 3298
swis2-VHDL20_DWMG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 4036
swis2-VHDL20_DWMG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 3426
swis2-VHDL20_DWMG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3962
swis2-VHDL20_DWMG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:01 3880
swis2-VHDL20_DWMG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 3967
swis2-VHDL20_DWMG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:06 3306
swis2-VHDL20_DWMG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3900
swis2-VHDL20_DWMG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:02 3922
swis2-VHDL20_DWMO_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 4090
swis2-VHDL20_DWMO_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 3440
swis2-VHDL20_DWMO_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 4091
swis2-VHDL20_DWMO_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:01 3935
swis2-VHDL20_DWMO_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 3983
swis2-VHDL20_DWMO_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:06 3358
swis2-VHDL20_DWMO_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3888
swis2-VHDL20_DWMO_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:02 3820
swis2-VHDL20_DWMP_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:09 3838
swis2-VHDL20_DWMP_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 3321
swis2-VHDL20_DWMP_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 3937
swis2-VHDL20_DWMP_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:01 3804
swis2-VHDL20_DWMP_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 4061
swis2-VHDL20_DWMP_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:06 3227
swis2-VHDL20_DWMP_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 3933
swis2-VHDL20_DWMP_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:02 3866
swis2-VHDL20_DWPG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2326
swis2-VHDL20_DWPG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2156
swis2-VHDL20_DWPG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 2350
swis2-VHDL20_DWPG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:16 2308
swis2-VHDL20_DWPG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 2393
swis2-VHDL20_DWPG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 2227
swis2-VHDL20_DWPG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 2365
swis2-VHDL20_DWPG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:17 2450
swis2-VHDL20_DWPH_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 2509
swis2-VHDL20_DWPH_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 2578
swis2-VHDL20_DWPH_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:06 2715
swis2-VHDL20_DWPH_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:00:16 2880
swis2-VHDL20_DWPH_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 3107
swis2-VHDL20_DWPH_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 2764
swis2-VHDL20_DWPH_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:03 2873
swis2-VHDL20_DWPH_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:00:17 3395
swis2-VHDL20_DWSG_200800-2512200800-dsw--0-ia5 20-Dec-2025 09:45:04 4071
swis2-VHDL20_DWSG_201300-2512201300-dsw--0-ia5 20-Dec-2025 14:45:04 3784
swis2-VHDL20_DWSG_201800-2512201800-dsw--0-ia5 20-Dec-2025 19:45:02 3454
swis2-VHDL20_DWSG_210200-2512210200-dsw--0-ia5 21-Dec-2025 03:45:01 3803
swis2-VHDL20_DWSG_210400-2512210400-dsw--0-ia5 21-Dec-2025 06:15:01 3843
swis2-VHDL20_DWSG_210800-2512210800-dsw--0-ia5 21-Dec-2025 09:45:02 4064
swis2-VHDL20_DWSG_211300-2512211300-dsw--0-ia5 21-Dec-2025 14:45:04 3962
swis2-VHDL20_DWSG_211800-2512211800-dsw--0-ia5 21-Dec-2025 19:45:04 3934
swis2-VHDL20_DWSG_220200-2512220200-dsw--0-ia5 22-Dec-2025 03:45:07 4028
swis2-VHDL20_DWSG_220400-2512220400-dsw--0-ia5 22-Dec-2025 06:15:02 3880
wst04-VHDL20_DWEG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 226964
wst04-VHDL20_DWEG_200800_COR-2512200800-omedes-..> 20-Dec-2025 14:54:26 227569
wst04-VHDL20_DWEG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:12 225356
wst04-VHDL20_DWEG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:16 226832
wst04-VHDL20_DWEG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:27 226582
wst04-VHDL20_DWEG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:22 228118
wst04-VHDL20_DWEG_210800_COR-2512210800-omedes-..> 21-Dec-2025 09:33:27 226063
wst04-VHDL20_DWEG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:12 227096
wst04-VHDL20_DWEG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:17 228594
wst04-VHDL20_DWEG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:26 227955
wst04-VHDL20_DWEH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 224778
wst04-VHDL20_DWEH_200800_COR-2512200800-omedes-..> 20-Dec-2025 14:54:22 224981
wst04-VHDL20_DWEH_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:12 223816
wst04-VHDL20_DWEH_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:16 224699
wst04-VHDL20_DWEH_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:21 224209
wst04-VHDL20_DWEH_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:22 222821
wst04-VHDL20_DWEH_210800_COR-2512210800-omedes-..> 21-Dec-2025 09:33:27 221689
wst04-VHDL20_DWEH_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:12 222344
wst04-VHDL20_DWEH_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:11 223333
wst04-VHDL20_DWEH_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:22 223281
wst04-VHDL20_DWEI_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 312603
wst04-VHDL20_DWEI_200800_COR-2512200800-omedes-..> 20-Dec-2025 14:54:26 312592
wst04-VHDL20_DWEI_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:12 311194
wst04-VHDL20_DWEI_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:22 311578
wst04-VHDL20_DWEI_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:27 312306
wst04-VHDL20_DWEI_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:28 310396
wst04-VHDL20_DWEI_210800_COR-2512210800-omedes-..> 21-Dec-2025 09:33:27 309390
wst04-VHDL20_DWEI_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:16 309764
wst04-VHDL20_DWEI_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:17 310722
wst04-VHDL20_DWEI_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:26 310499
wst04-VHDL20_DWHG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 302096
wst04-VHDL20_DWHG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:18 301506
wst04-VHDL20_DWHG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:12 302010
wst04-VHDL20_DWHG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:12 302051
wst04-VHDL20_DWHG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:16 302668
wst04-VHDL20_DWHG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:16 300592
wst04-VHDL20_DWHG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:13 301437
wst04-VHDL20_DWHG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:12 301525
wst04-VHDL20_DWHH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 286983
wst04-VHDL20_DWHH_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:22 286908
wst04-VHDL20_DWHH_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:12 286286
wst04-VHDL20_DWHH_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:12 286315
wst04-VHDL20_DWHH_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:16 289241
wst04-VHDL20_DWHH_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:16 289613
wst04-VHDL20_DWHH_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:13 289738
wst04-VHDL20_DWHH_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:12 289820
wst04-VHDL20_DWLG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 299110
wst04-VHDL20_DWLG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:22 298126
wst04-VHDL20_DWLG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:26 299947
wst04-VHDL20_DWLG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:41 299180
wst04-VHDL20_DWLG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:32 299114
wst04-VHDL20_DWLG_210800_COR-2512210800-omedes-..> 21-Dec-2025 14:03:01 298879
wst04-VHDL20_DWLG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:26 298161
wst04-VHDL20_DWLG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:27 299071
wst04-VHDL20_DWLG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:42 298871
wst04-VHDL20_DWLH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 295194
wst04-VHDL20_DWLH_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:26 294649
wst04-VHDL20_DWLH_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:26 295359
wst04-VHDL20_DWLH_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:41 294576
wst04-VHDL20_DWLH_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:32 299653
wst04-VHDL20_DWLH_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:22 299064
wst04-VHDL20_DWLH_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:27 299902
wst04-VHDL20_DWLH_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:42 299663
wst04-VHDL20_DWLI_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:31 299737
wst04-VHDL20_DWLI_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:26 298938
wst04-VHDL20_DWLI_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:22 300173
wst04-VHDL20_DWLI_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:41 300518
wst04-VHDL20_DWLI_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:32 302105
wst04-VHDL20_DWLI_210800_COR-2512210800-omedes-..> 21-Dec-2025 14:04:06 301779
wst04-VHDL20_DWLI_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:22 301035
wst04-VHDL20_DWLI_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:27 302038
wst04-VHDL20_DWLI_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:42 301474
wst04-VHDL20_DWMG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:17 496853
wst04-VHDL20_DWMG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:16 496058
wst04-VHDL20_DWMG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:16 497291
wst04-VHDL20_DWMG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:21 496939
wst04-VHDL20_DWMG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:18 491745
wst04-VHDL20_DWMG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:22 490401
wst04-VHDL20_DWMG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:21 491861
wst04-VHDL20_DWMG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:22 491515
wst04-VHDL20_DWMO_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:11 404089
wst04-VHDL20_DWMO_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:16 403201
wst04-VHDL20_DWMO_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:22 404240
wst04-VHDL20_DWMO_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:21 404428
wst04-VHDL20_DWMO_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:12 402152
wst04-VHDL20_DWMO_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:16 401414
wst04-VHDL20_DWMO_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:17 402266
wst04-VHDL20_DWMO_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:22 402558
wst04-VHDL20_DWMP_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:21 514439
wst04-VHDL20_DWMP_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:16 513680
wst04-VHDL20_DWMP_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:16 513322
wst04-VHDL20_DWMP_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:21 514207
wst04-VHDL20_DWMP_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:22 499438
wst04-VHDL20_DWMP_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:22 496908
wst04-VHDL20_DWMP_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:21 497018
wst04-VHDL20_DWMP_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:22 497989
wst04-VHDL20_DWPG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 344333
wst04-VHDL20_DWPG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:22 299058
wst04-VHDL20_DWPG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:26 299293
wst04-VHDL20_DWPG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:31 299750
wst04-VHDL20_DWPG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:32 343017
wst04-VHDL20_DWPG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:26 298249
wst04-VHDL20_DWPG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:21 298694
wst04-VHDL20_DWPG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:31 298878
wst04-VHDL20_DWPH_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:26 264053
wst04-VHDL20_DWPH_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:22 264248
wst04-VHDL20_DWPH_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:22 219710
wst04-VHDL20_DWPH_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:00:31 219476
wst04-VHDL20_DWPH_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:26 268659
wst04-VHDL20_DWPH_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:22 267404
wst04-VHDL20_DWPH_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:21 223104
wst04-VHDL20_DWPH_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:00:31 223738
wst04-VHDL20_DWSG_200800-2512200800-omedes--0.pdf 20-Dec-2025 09:45:11 315201
wst04-VHDL20_DWSG_201300-2512201300-omedes--0.pdf 20-Dec-2025 14:45:23 314783
wst04-VHDL20_DWSG_201800-2512201800-omedes--0.pdf 20-Dec-2025 19:45:12 314087
wst04-VHDL20_DWSG_210200-2512210200-omedes--0.pdf 21-Dec-2025 03:45:12 314273
wst04-VHDL20_DWSG_210400-2512210400-omedes--0.pdf 21-Dec-2025 06:15:17 314259
wst04-VHDL20_DWSG_210800-2512210800-omedes--0.pdf 21-Dec-2025 09:45:12 320056
wst04-VHDL20_DWSG_211300-2512211300-omedes--0.pdf 21-Dec-2025 14:45:15 320224
wst04-VHDL20_DWSG_211800-2512211800-omedes--0.pdf 21-Dec-2025 19:45:12 320223
wst04-VHDL20_DWSG_220200-2512220200-omedes--0.pdf 22-Dec-2025 03:45:17 319594
wst04-VHDL20_DWSG_220400-2512220400-omedes--0.pdf 22-Dec-2025 06:15:16 319271