Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Jul-2026 13:43:23 3775
FPDL13_DWMZ_180600 18-Jul-2026 12:23:44 4623
FPDL13_DWMZ_190600 19-Jul-2026 12:58:04 3910
SXDL31_DWAV_171800 17-Jul-2026 16:53:48 10244
SXDL31_DWAV_180800 18-Jul-2026 07:12:53 8208
SXDL31_DWAV_181800 18-Jul-2026 16:40:38 11949
SXDL31_DWAV_190800 19-Jul-2026 07:17:08 7622
SXDL31_DWAV_LATEST 19-Jul-2026 07:17:08 7622
SXDL33_DWAV_180000 18-Jul-2026 09:50:43 6036
SXDL33_DWAV_190000 19-Jul-2026 10:07:24 8080
SXDL33_DWAV_LATEST 19-Jul-2026 10:07:24 8080
ber01-FWDL39_DWMS_181200-2607181200-dsw--0-ia5 18-Jul-2026 11:56:15 1270
ber01-FWDL39_DWMS_191200-2607191200-dsw--0-ia5 19-Jul-2026 10:17:32 1279
ber01-VHDL13_DWEG_170800_COR-2607170800-dsw--0-ia5 18-Jul-2026 04:59:27 3201
ber01-VHDL13_DWEG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:28:16 3339
ber01-VHDL13_DWEG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:17 3050
ber01-VHDL13_DWEH_170800_COR-2607170800-dsw--0-ia5 18-Jul-2026 04:59:41 2659
ber01-VHDL13_DWEH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:28:16 2655
ber01-VHDL13_DWEH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:17 3008
ber01-VHDL13_DWEI_170800_COR-2607170800-dsw--0-ia5 18-Jul-2026 05:00:22 2576
ber01-VHDL13_DWEI_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:28:16 2716
ber01-VHDL13_DWEI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:12 2202
ber01-VHDL13_DWHG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3737
ber01-VHDL13_DWHG_180800_COR-2607180800-dsw--0-ia5 18-Jul-2026 14:16:57 4320
ber01-VHDL13_DWHG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3637
ber01-VHDL13_DWHH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3636
ber01-VHDL13_DWHH_180800_COR-2607180800-dsw--0-ia5 18-Jul-2026 14:16:21 4109
ber01-VHDL13_DWHH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3362
ber01-VHDL13_DWLG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 2893
ber01-VHDL13_DWLG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2582
ber01-VHDL13_DWLH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 2899
ber01-VHDL13_DWLH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2823
ber01-VHDL13_DWLI_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 2710
ber01-VHDL13_DWLI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2284
ber01-VHDL13_DWMO_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3599
ber01-VHDL13_DWMO_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2466
ber01-VHDL13_DWMP_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3639
ber01-VHDL13_DWMP_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2963
ber01-VHDL13_DWOG_171700-2607171700-dsw--0-ia5 17-Jul-2026 18:00:03 4612
ber01-VHDL13_DWOG_180300-2607180300-dsw--0-ia5 18-Jul-2026 03:00:07 3924
ber01-VHDL13_DWOG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 4016
ber01-VHDL13_DWOG_181700-2607181700-dsw--0-ia5 18-Jul-2026 18:00:01 4549
ber01-VHDL13_DWOG_190300-2607190300-dsw--0-ia5 19-Jul-2026 03:00:19 4660
ber01-VHDL13_DWOG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 4312
ber01-VHDL13_DWON_171450-2607171450-dsw--0-ia5 17-Jul-2026 14:52:10 4183
ber01-VHDL13_DWON_171741-2607171741-dsw--0-ia5 17-Jul-2026 17:41:55 3922
ber01-VHDL13_DWON_180107-2607180107-dsw--0-ia5 18-Jul-2026 01:07:56 3490
ber01-VHDL13_DWON_180255-2607180255-dsw--0-ia5 18-Jul-2026 02:55:58 3490
ber01-VHDL13_DWON_180526-2607180526-dsw--0-ia5 18-Jul-2026 05:26:57 4018
ber01-VHDL13_DWON_180550-2607180550-dsw--0-ia5 18-Jul-2026 05:50:21 4018
ber01-VHDL13_DWON_180811-2607180811-dsw--0-ia5 18-Jul-2026 08:11:11 3993
ber01-VHDL13_DWON_180855-2607180855-dsw--0-ia5 18-Jul-2026 08:55:36 3993
ber01-VHDL13_DWON_181455-2607181455-dsw--0-ia5 18-Jul-2026 14:56:18 3130
ber01-VHDL13_DWON_181649-2607181649-dsw--0-ia5 18-Jul-2026 16:49:17 3497
ber01-VHDL13_DWON_181859-2607181859-dsw--0-ia5 18-Jul-2026 18:59:11 3566
ber01-VHDL13_DWON_182324-2607182324-dsw--0-ia5 18-Jul-2026 23:24:27 3817
ber01-VHDL13_DWON_190110-2607190110-dsw--0-ia5 19-Jul-2026 01:10:54 3817
ber01-VHDL13_DWON_190320-2607190320-dsw--0-ia5 19-Jul-2026 03:20:47 3800
ber01-VHDL13_DWON_190529-2607190529-dsw--0-ia5 19-Jul-2026 05:29:22 3913
ber01-VHDL13_DWON_190616-2607190616-dsw--0-ia5 19-Jul-2026 06:16:57 3932
ber01-VHDL13_DWON_190642-2607190642-dsw--0-ia5 19-Jul-2026 06:42:19 3854
ber01-VHDL13_DWON_190756-2607190756-dsw--0-ia5 19-Jul-2026 07:56:47 3867
ber01-VHDL13_DWON_191052-2607191052-dsw--0-ia5 19-Jul-2026 10:52:37 3742
ber01-VHDL13_DWON_191322-2607191322-dsw--0-ia5 19-Jul-2026 13:22:06 3715
ber01-VHDL13_DWPG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 2872
ber01-VHDL13_DWPG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2791
ber01-VHDL13_DWPH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3482
ber01-VHDL13_DWPH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3515
ber01-VHDL13_DWSG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 3354
ber01-VHDL13_DWSG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2594
ber01-VHDL17_DWOG_181200-2607181200-dsw--0-ia5 18-Jul-2026 11:42:19 2681
ber01-VHDL17_DWOG_191200-2607191200-dsw--0-ia5 19-Jul-2026 11:03:16 2932
swis2-VHDL20_DWEG_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 1402
swis2-VHDL20_DWEG_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 1186
swis2-VHDL20_DWEG_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:01:23 1177
swis2-VHDL20_DWEG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1357
swis2-VHDL20_DWEG_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:07 1494
swis2-VHDL20_DWEG_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1098
swis2-VHDL20_DWEG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:17 1102
swis2-VHDL20_DWEG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1191
swis2-VHDL20_DWEH_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 1266
swis2-VHDL20_DWEH_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 944
swis2-VHDL20_DWEH_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:01:23 1010
swis2-VHDL20_DWEH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1097
swis2-VHDL20_DWEH_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:07 1325
swis2-VHDL20_DWEH_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1166
swis2-VHDL20_DWEH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:21 1207
swis2-VHDL20_DWEH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1333
swis2-VHDL20_DWEI_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 1433
swis2-VHDL20_DWEI_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 1220
swis2-VHDL20_DWEI_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:01:23 1043
swis2-VHDL20_DWEI_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1221
swis2-VHDL20_DWEI_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:07 1405
swis2-VHDL20_DWEI_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1084
swis2-VHDL20_DWEI_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:21 739
swis2-VHDL20_DWEI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 828
swis2-VHDL20_DWHG_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:45:06 2378
swis2-VHDL20_DWHG_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:45:11 1660
swis2-VHDL20_DWHG_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:16 1472
swis2-VHDL20_DWHG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:45:25 1825
swis2-VHDL20_DWHG_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:45:11 2246
swis2-VHDL20_DWHG_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:46:00 1889
swis2-VHDL20_DWHG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1886
swis2-VHDL20_DWHG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:45:18 1740
swis2-VHDL20_DWHH_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:45:06 2353
swis2-VHDL20_DWHH_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:45:11 1630
swis2-VHDL20_DWHH_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:16 1445
swis2-VHDL20_DWHH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:45:25 1874
swis2-VHDL20_DWHH_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:45:11 2132
swis2-VHDL20_DWHH_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:46:00 1746
swis2-VHDL20_DWHH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1746
swis2-VHDL20_DWHH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:45:18 1635
swis2-VHDL20_DWLG_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:31:08 1387
swis2-VHDL20_DWLG_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:25 1175
swis2-VHDL20_DWLG_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:12 1133
swis2-VHDL20_DWLG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:26 1264
swis2-VHDL20_DWLG_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:31:07 1177
swis2-VHDL20_DWLG_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:28 1233
swis2-VHDL20_DWLG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 942
swis2-VHDL20_DWLG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1060
swis2-VHDL20_DWLH_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:31:08 1444
swis2-VHDL20_DWLH_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:25 1296
swis2-VHDL20_DWLH_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:12 1160
swis2-VHDL20_DWLH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:26 1261
swis2-VHDL20_DWLH_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:31:07 1318
swis2-VHDL20_DWLH_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:28 1276
swis2-VHDL20_DWLH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1246
swis2-VHDL20_DWLH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1362
swis2-VHDL20_DWLI_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:31:08 1225
swis2-VHDL20_DWLI_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:25 1229
swis2-VHDL20_DWLI_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:12 1125
swis2-VHDL20_DWLI_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:26 1241
swis2-VHDL20_DWLI_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:31:07 1149
swis2-VHDL20_DWLI_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:28 1243
swis2-VHDL20_DWLI_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 928
swis2-VHDL20_DWLI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1046
swis2-VHDL20_DWMO_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 1960
swis2-VHDL20_DWMO_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 1538
swis2-VHDL20_DWMO_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:02 1484
swis2-VHDL20_DWMO_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1779
swis2-VHDL20_DWMO_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:07 1378
swis2-VHDL20_DWMO_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1000
swis2-VHDL20_DWMO_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:03 1010
swis2-VHDL20_DWMO_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 884
swis2-VHDL20_DWMP_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 1674
swis2-VHDL20_DWMP_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 1480
swis2-VHDL20_DWMP_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:02 1505
swis2-VHDL20_DWMP_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1868
swis2-VHDL20_DWMP_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:07 1523
swis2-VHDL20_DWMP_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1126
swis2-VHDL20_DWMP_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:03 1256
swis2-VHDL20_DWMP_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1384
swis2-VHDL20_DWPG_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:31:08 1402
swis2-VHDL20_DWPG_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:25 1244
swis2-VHDL20_DWPG_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:12 1206
swis2-VHDL20_DWPG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:26 1307
swis2-VHDL20_DWPG_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:31:07 1258
swis2-VHDL20_DWPG_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:28 1245
swis2-VHDL20_DWPG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1236
swis2-VHDL20_DWPG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1324
swis2-VHDL20_DWPH_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:31:08 1612
swis2-VHDL20_DWPH_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:25 1568
swis2-VHDL20_DWPH_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:12 1601
swis2-VHDL20_DWPH_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:26 1797
swis2-VHDL20_DWPH_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:31:07 1792
swis2-VHDL20_DWPH_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:28 1735
swis2-VHDL20_DWPH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1719
swis2-VHDL20_DWPH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1908
swis2-VHDL20_DWSG_171800-2607171800-dsw--0-ia5 17-Jul-2026 18:30:09 2060
swis2-VHDL20_DWSG_180200-2607180200-dsw--0-ia5 18-Jul-2026 02:30:07 1432
swis2-VHDL20_DWSG_180400-2607180400-dsw--0-ia5 18-Jul-2026 05:00:16 1490
swis2-VHDL20_DWSG_180800-2607180800-dsw--0-ia5 18-Jul-2026 08:30:06 1610
swis2-VHDL20_DWSG_181800-2607181800-dsw--0-ia5 18-Jul-2026 18:30:08 1301
swis2-VHDL20_DWSG_190200-2607190200-dsw--0-ia5 19-Jul-2026 02:30:05 1052
swis2-VHDL20_DWSG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1043
swis2-VHDL20_DWSG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1096
wst04-VHDL20_DWEG_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:22 242584
wst04-VHDL20_DWEG_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 241106
wst04-VHDL20_DWEG_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:12 240526
wst04-VHDL20_DWEG_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:17 241399
wst04-VHDL20_DWEG_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 242081
wst04-VHDL20_DWEG_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 240871
wst04-VHDL20_DWEG_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 240478
wst04-VHDL20_DWEG_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:12 241196
wst04-VHDL20_DWEH_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:12 235859
wst04-VHDL20_DWEH_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 235298
wst04-VHDL20_DWEH_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:12 235726
wst04-VHDL20_DWEH_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:17 236643
wst04-VHDL20_DWEH_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 237393
wst04-VHDL20_DWEH_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 237051
wst04-VHDL20_DWEH_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 236917
wst04-VHDL20_DWEH_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:12 237678
wst04-VHDL20_DWEI_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:22 349019
wst04-VHDL20_DWEI_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 346976
wst04-VHDL20_DWEI_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:12 346024
wst04-VHDL20_DWEI_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:17 346698
wst04-VHDL20_DWEI_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 343735
wst04-VHDL20_DWEI_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 342039
wst04-VHDL20_DWEI_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 340560
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wst04-VHDL20_DWHG_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:45:17 355866
wst04-VHDL20_DWHG_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:45:11 354432
wst04-VHDL20_DWHG_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:16 353603
wst04-VHDL20_DWHG_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:45:25 355228
wst04-VHDL20_DWHG_180800_COR-2607180800-omedes-..> 18-Jul-2026 14:18:16 345107
wst04-VHDL20_DWHG_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:45:11 345496
wst04-VHDL20_DWHG_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:46:00 343874
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wst04-VHDL20_DWHG_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:45:18 345515
wst04-VHDL20_DWHH_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:45:17 347958
wst04-VHDL20_DWHH_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:45:11 347010
wst04-VHDL20_DWHH_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:16 236553
wst04-VHDL20_DWHH_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:45:25 347131
wst04-VHDL20_DWHH_180800_COR-2607180800-omedes-..> 18-Jul-2026 14:17:50 332038
wst04-VHDL20_DWHH_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:45:11 332093
wst04-VHDL20_DWHH_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:46:00 331255
wst04-VHDL20_DWHH_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:17 231729
wst04-VHDL20_DWHH_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:45:18 331583
wst04-VHDL20_DWLG_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:31:20 343871
wst04-VHDL20_DWLG_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:25 343015
wst04-VHDL20_DWLG_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:42 342816
wst04-VHDL20_DWLG_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:41 343029
wst04-VHDL20_DWLG_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:31:24 333488
wst04-VHDL20_DWLG_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:28 334146
wst04-VHDL20_DWLG_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:41 333023
wst04-VHDL20_DWLG_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:42 333231
wst04-VHDL20_DWLH_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:31:20 343989
wst04-VHDL20_DWLH_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:25 342930
wst04-VHDL20_DWLH_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:42 343259
wst04-VHDL20_DWLH_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:41 343466
wst04-VHDL20_DWLH_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:31:24 338645
wst04-VHDL20_DWLH_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:28 338547
wst04-VHDL20_DWLH_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:41 338318
wst04-VHDL20_DWLH_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:51 338554
wst04-VHDL20_DWLI_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:31:20 349108
wst04-VHDL20_DWLI_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:25 348995
wst04-VHDL20_DWLI_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:42 348783
wst04-VHDL20_DWLI_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:45 393576
wst04-VHDL20_DWLI_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:31:24 339671
wst04-VHDL20_DWLI_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:28 340321
wst04-VHDL20_DWLI_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:41 339149
wst04-VHDL20_DWLI_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:42 383955
wst04-VHDL20_DWMO_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:22 360569
wst04-VHDL20_DWMO_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 470502
wst04-VHDL20_DWMO_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:18 470397
wst04-VHDL20_DWMO_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:17 470190
wst04-VHDL20_DWMO_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 354781
wst04-VHDL20_DWMO_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 461310
wst04-VHDL20_DWMO_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:17 461179
wst04-VHDL20_DWMO_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:20 460076
wst04-VHDL20_DWMP_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:22 476537
wst04-VHDL20_DWMP_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 583714
wst04-VHDL20_DWMP_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:18 583847
wst04-VHDL20_DWMP_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:26 476648
wst04-VHDL20_DWMP_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 473150
wst04-VHDL20_DWMP_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 575402
wst04-VHDL20_DWMP_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:17 575231
wst04-VHDL20_DWMP_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:23 472935
wst04-VHDL20_DWPG_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:31:30 352034
wst04-VHDL20_DWPG_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:25 247070
wst04-VHDL20_DWPG_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:32 351917
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wst04-VHDL20_DWPG_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:31:24 341613
wst04-VHDL20_DWPG_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:28 240503
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wst04-VHDL20_DWPH_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:31:20 247743
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wst04-VHDL20_DWPH_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:41 247491
wst04-VHDL20_DWPH_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:31:24 241013
wst04-VHDL20_DWPH_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:28 241382
wst04-VHDL20_DWPH_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:31 241321
wst04-VHDL20_DWPH_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:42 241643
wst04-VHDL20_DWSG_171800-2607171800-omedes--0.pdf 17-Jul-2026 18:30:12 358157
wst04-VHDL20_DWSG_180200-2607180200-omedes--0.pdf 18-Jul-2026 02:30:17 357110
wst04-VHDL20_DWSG_180400-2607180400-omedes--0.pdf 18-Jul-2026 05:00:12 357078
wst04-VHDL20_DWSG_180800-2607180800-omedes--0.pdf 18-Jul-2026 08:30:17 356657
wst04-VHDL20_DWSG_181800-2607181800-omedes--0.pdf 18-Jul-2026 18:30:20 349517
wst04-VHDL20_DWSG_190200-2607190200-omedes--0.pdf 19-Jul-2026 02:30:18 348941
wst04-VHDL20_DWSG_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:13 349185
wst04-VHDL20_DWSG_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:20 349351