Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Jun-2026 12:43:44 4546
FPDL13_DWMZ_130600 13-Jun-2026 14:58:09 6678
SXDL31_DWAV_120800 12-Jun-2026 08:05:50 13214
SXDL31_DWAV_121800 12-Jun-2026 16:56:23 4838
SXDL31_DWAV_130800 13-Jun-2026 08:37:03 12249
SXDL31_DWAV_131800 13-Jun-2026 16:38:16 5254
SXDL31_DWAV_LATEST 13-Jun-2026 16:38:16 5254
SXDL33_DWAV_120000 12-Jun-2026 09:56:59 10435
SXDL33_DWAV_130000 13-Jun-2026 10:32:11 21384
SXDL33_DWAV_LATEST 13-Jun-2026 10:32:11 21384
ber01-FWDL39_DWMS_121200-2606121200-dsw--0-ia5 12-Jun-2026 11:06:37 1648
ber01-FWDL39_DWMS_131200-2606131200-dsw--0-ia5 13-Jun-2026 11:56:47 1265
ber01-VHDL13_DWEG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:16 2808
ber01-VHDL13_DWEG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:17 2732
ber01-VHDL13_DWEH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:12 2695
ber01-VHDL13_DWEH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:17 2646
ber01-VHDL13_DWEI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:16 2644
ber01-VHDL13_DWEI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:28:11 2593
ber01-VHDL13_DWHG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:08 3125
ber01-VHDL13_DWHG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 3732
ber01-VHDL13_DWHH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:08 3102
ber01-VHDL13_DWHH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 3662
ber01-VHDL13_DWLG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2393
ber01-VHDL13_DWLG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2804
ber01-VHDL13_DWLH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2689
ber01-VHDL13_DWLH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2659
ber01-VHDL13_DWLI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2240
ber01-VHDL13_DWLI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2237
ber01-VHDL13_DWMO_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3207
ber01-VHDL13_DWMO_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 2893
ber01-VHDL13_DWMP_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3445
ber01-VHDL13_DWMP_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 3238
ber01-VHDL13_DWOG_120300-2606120300-dsw--0-ia5 12-Jun-2026 03:00:06 3498
ber01-VHDL13_DWOG_120800-2606120800-dsw--0-ia5 12-Jun-2026 09:28:11 4759
ber01-VHDL13_DWOG_121700-2606121700-dsw--0-ia5 12-Jun-2026 18:00:06 4531
ber01-VHDL13_DWOG_130300-2606130300-dsw--0-ia5 13-Jun-2026 03:00:02 4716
ber01-VHDL13_DWOG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 4839
ber01-VHDL13_DWOG_131700-2606131700-dsw--0-ia5 13-Jun-2026 18:00:02 4061
ber01-VHDL13_DWON_120251-2606120251-dsw--0-ia5 12-Jun-2026 02:51:32 2914
ber01-VHDL13_DWON_120530-2606120530-dsw--0-ia5 12-Jun-2026 05:30:14 3296
ber01-VHDL13_DWON_120559-2606120559-dsw--0-ia5 12-Jun-2026 05:59:26 3936
ber01-VHDL13_DWON_120624-2606120624-dsw--0-ia5 12-Jun-2026 06:25:02 3962
ber01-VHDL13_DWON_120926-2606120926-dsw--0-ia5 12-Jun-2026 09:26:36 3938
ber01-VHDL13_DWON_121430-2606121430-dsw--0-ia5 12-Jun-2026 14:30:22 3866
ber01-VHDL13_DWON_121702-2606121702-dsw--0-ia5 12-Jun-2026 17:02:16 3855
ber01-VHDL13_DWON_121828-2606121828-dsw--0-ia5 12-Jun-2026 18:28:47 3286
ber01-VHDL13_DWON_122144-2606122144-dsw--0-ia5 12-Jun-2026 21:44:11 3376
ber01-VHDL13_DWON_130001-2606130001-dsw--0-ia5 13-Jun-2026 00:01:31 3865
ber01-VHDL13_DWON_130158-2606130158-dsw--0-ia5 13-Jun-2026 01:58:27 3881
ber01-VHDL13_DWON_130232-2606130232-dsw--0-ia5 13-Jun-2026 02:32:59 3881
ber01-VHDL13_DWON_130529-2606130529-dsw--0-ia5 13-Jun-2026 05:29:20 4421
ber01-VHDL13_DWON_130543-2606130543-dsw--0-ia5 13-Jun-2026 05:43:42 4298
ber01-VHDL13_DWON_130648-2606130648-dsw--0-ia5 13-Jun-2026 06:48:36 4465
ber01-VHDL13_DWON_130807-2606130807-dsw--0-ia5 13-Jun-2026 08:08:01 4418
ber01-VHDL13_DWON_130839-2606130839-dsw--0-ia5 13-Jun-2026 08:39:59 4418
ber01-VHDL13_DWON_130941-2606130941-dsw--0-ia5 13-Jun-2026 09:41:24 4418
ber01-VHDL13_DWON_131441-2606131441-dsw--0-ia5 13-Jun-2026 14:41:57 4321
ber01-VHDL13_DWON_131733-2606131733-dsw--0-ia5 13-Jun-2026 17:33:41 3449
ber01-VHDL13_DWON_131738-2606131738-dsw--0-ia5 13-Jun-2026 17:38:32 3439
ber01-VHDL13_DWON_131826-2606131826-dsw--0-ia5 13-Jun-2026 18:26:37 3516
ber01-VHDL13_DWON_132128-2606132128-dsw--0-ia5 13-Jun-2026 21:28:36 3500
ber01-VHDL13_DWON_140133-2606140133-dsw--0-ia5 14-Jun-2026 01:33:46 3980
ber01-VHDL13_DWPG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2334
ber01-VHDL13_DWPG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2322
ber01-VHDL13_DWPH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2741
ber01-VHDL13_DWPH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2757
ber01-VHDL13_DWSG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3123
ber01-VHDL13_DWSG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 2866
ber01-VHDL17_DWOG_121200-2606121200-dsw--0-ia5 12-Jun-2026 11:57:22 3430
ber01-VHDL17_DWOG_131200-2606131200-dsw--0-ia5 13-Jun-2026 11:41:26 3785
swis2-VHDL20_DWEG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1009
swis2-VHDL20_DWEG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1141
swis2-VHDL20_DWEG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1323
swis2-VHDL20_DWEG_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:08 1164
swis2-VHDL20_DWEG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1014
swis2-VHDL20_DWEG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1074
swis2-VHDL20_DWEG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1209
swis2-VHDL20_DWEG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 983
swis2-VHDL20_DWEH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1010
swis2-VHDL20_DWEH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1132
swis2-VHDL20_DWEH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1282
swis2-VHDL20_DWEH_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:08 1177
swis2-VHDL20_DWEH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1008
swis2-VHDL20_DWEH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1071
swis2-VHDL20_DWEH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1208
swis2-VHDL20_DWEH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1000
swis2-VHDL20_DWEI_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1034
swis2-VHDL20_DWEI_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1135
swis2-VHDL20_DWEI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1248
swis2-VHDL20_DWEI_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:08 1160
swis2-VHDL20_DWEI_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1019
swis2-VHDL20_DWEI_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:01:23 1082
swis2-VHDL20_DWEI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1209
swis2-VHDL20_DWEI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 970
swis2-VHDL20_DWHG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:45:01 1560
swis2-VHDL20_DWHG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1513
swis2-VHDL20_DWHG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:45:14 1513
swis2-VHDL20_DWHG_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:45:03 1967
swis2-VHDL20_DWHG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:45:18 1834
swis2-VHDL20_DWHG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1997
swis2-VHDL20_DWHG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:45:04 2019
swis2-VHDL20_DWHG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 1795
swis2-VHDL20_DWHH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:45:01 1579
swis2-VHDL20_DWHH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1535
swis2-VHDL20_DWHH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:45:14 1568
swis2-VHDL20_DWHH_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:45:03 1964
swis2-VHDL20_DWHH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:45:18 1874
swis2-VHDL20_DWHH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1959
swis2-VHDL20_DWHH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:45:04 2090
swis2-VHDL20_DWHH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 2029
swis2-VHDL20_DWLG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 723
swis2-VHDL20_DWLG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 711
swis2-VHDL20_DWLG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1085
swis2-VHDL20_DWLG_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:31:04 1225
swis2-VHDL20_DWLG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1278
swis2-VHDL20_DWLG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1293
swis2-VHDL20_DWLG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1404
swis2-VHDL20_DWLG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1111
swis2-VHDL20_DWLH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 733
swis2-VHDL20_DWLH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1119
swis2-VHDL20_DWLH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1361
swis2-VHDL20_DWLH_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:31:04 1415
swis2-VHDL20_DWLH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1361
swis2-VHDL20_DWLH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1174
swis2-VHDL20_DWLH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1326
swis2-VHDL20_DWLH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1392
swis2-VHDL20_DWLI_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 703
swis2-VHDL20_DWLI_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 810
swis2-VHDL20_DWLI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 929
swis2-VHDL20_DWLI_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:31:04 991
swis2-VHDL20_DWLI_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 998
swis2-VHDL20_DWLI_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1008
swis2-VHDL20_DWLI_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1122
swis2-VHDL20_DWLI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 937
swis2-VHDL20_DWMO_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1215
swis2-VHDL20_DWMO_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:07 1255
swis2-VHDL20_DWMO_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1361
swis2-VHDL20_DWMO_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:08 1594
swis2-VHDL20_DWMO_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1280
swis2-VHDL20_DWMO_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:02 1285
swis2-VHDL20_DWMO_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:16 1272
swis2-VHDL20_DWMO_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1301
swis2-VHDL20_DWMP_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1414
swis2-VHDL20_DWMP_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:07 1478
swis2-VHDL20_DWMP_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1654
swis2-VHDL20_DWMP_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:08 1549
swis2-VHDL20_DWMP_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1503
swis2-VHDL20_DWMP_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:02 1508
swis2-VHDL20_DWMP_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:17 1529
swis2-VHDL20_DWMP_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1551
swis2-VHDL20_DWPG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 719
swis2-VHDL20_DWPG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 997
swis2-VHDL20_DWPG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1293
swis2-VHDL20_DWPG_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:31:04 1154
swis2-VHDL20_DWPG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1162
swis2-VHDL20_DWPG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1097
swis2-VHDL20_DWPG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1218
swis2-VHDL20_DWPG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1291
swis2-VHDL20_DWPH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 925
swis2-VHDL20_DWPH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1146
swis2-VHDL20_DWPH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1545
swis2-VHDL20_DWPH_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:31:04 1351
swis2-VHDL20_DWPH_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:20 1283
swis2-VHDL20_DWPH_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:12 1270
swis2-VHDL20_DWPH_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:29 1426
swis2-VHDL20_DWPH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1492
swis2-VHDL20_DWSG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1250
swis2-VHDL20_DWSG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1252
swis2-VHDL20_DWSG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1355
swis2-VHDL20_DWSG_121800-2606121800-dsw--0-ia5 12-Jun-2026 18:30:01 1287
swis2-VHDL20_DWSG_130200-2606130200-dsw--0-ia5 13-Jun-2026 02:30:01 1248
swis2-VHDL20_DWSG_130400-2606130400-dsw--0-ia5 13-Jun-2026 05:00:16 1247
swis2-VHDL20_DWSG_130800-2606130800-dsw--0-ia5 13-Jun-2026 08:30:01 1245
swis2-VHDL20_DWSG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1381
wst04-VHDL20_DWEG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 239809
wst04-VHDL20_DWEG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 239754
wst04-VHDL20_DWEG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 240548
wst04-VHDL20_DWEG_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:15 237035
wst04-VHDL20_DWEG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 236127
wst04-VHDL20_DWEG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 235998
wst04-VHDL20_DWEG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 237338
wst04-VHDL20_DWEG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 238572
wst04-VHDL20_DWEH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 236779
wst04-VHDL20_DWEH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 236924
wst04-VHDL20_DWEH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 237785
wst04-VHDL20_DWEH_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:15 236132
wst04-VHDL20_DWEH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 235883
wst04-VHDL20_DWEH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 235706
wst04-VHDL20_DWEH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 237081
wst04-VHDL20_DWEH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 236082
wst04-VHDL20_DWEI_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 342126
wst04-VHDL20_DWEI_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 341987
wst04-VHDL20_DWEI_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 342205
wst04-VHDL20_DWEI_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:23 336530
wst04-VHDL20_DWEI_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 336219
wst04-VHDL20_DWEI_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 336028
wst04-VHDL20_DWEI_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 336335
wst04-VHDL20_DWEI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 338034
wst04-VHDL20_DWHG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:45:11 337769
wst04-VHDL20_DWHG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 337492
wst04-VHDL20_DWHG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:45:14 338453
wst04-VHDL20_DWHG_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:45:12 337403
wst04-VHDL20_DWHG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:45:18 337238
wst04-VHDL20_DWHG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 337054
wst04-VHDL20_DWHG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:45:12 338190
wst04-VHDL20_DWHG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 337810
wst04-VHDL20_DWHH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:45:11 322534
wst04-VHDL20_DWHH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 225554
wst04-VHDL20_DWHH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:45:14 322515
wst04-VHDL20_DWHH_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:45:12 325378
wst04-VHDL20_DWHH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:45:18 325628
wst04-VHDL20_DWHH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 227717
wst04-VHDL20_DWHH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:45:12 325842
wst04-VHDL20_DWHH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 326363
wst04-VHDL20_DWLG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 337072
wst04-VHDL20_DWLG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 336629
wst04-VHDL20_DWLG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 337054
wst04-VHDL20_DWLG_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:31:22 335250
wst04-VHDL20_DWLG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:25 335709
wst04-VHDL20_DWLG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 335881
wst04-VHDL20_DWLG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:45 336080
wst04-VHDL20_DWLG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 340325
wst04-VHDL20_DWLH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 332772
wst04-VHDL20_DWLH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 333064
wst04-VHDL20_DWLH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:46 333349
wst04-VHDL20_DWLH_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:31:22 329548
wst04-VHDL20_DWLH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 328724
wst04-VHDL20_DWLH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 328356
wst04-VHDL20_DWLH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:45 328620
wst04-VHDL20_DWLH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 331737
wst04-VHDL20_DWLI_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:30 337321
wst04-VHDL20_DWLI_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 337272
wst04-VHDL20_DWLI_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 382129
wst04-VHDL20_DWLI_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:31:25 334780
wst04-VHDL20_DWLI_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 334856
wst04-VHDL20_DWLI_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:40 334559
wst04-VHDL20_DWLI_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 379362
wst04-VHDL20_DWLI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 335223
wst04-VHDL20_DWMO_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:17 456818
wst04-VHDL20_DWMO_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 457496
wst04-VHDL20_DWMO_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:19 457357
wst04-VHDL20_DWMO_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:23 343914
wst04-VHDL20_DWMO_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 447051
wst04-VHDL20_DWMO_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 447266
wst04-VHDL20_DWMO_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:16 446996
wst04-VHDL20_DWMO_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 347509
wst04-VHDL20_DWMP_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:17 579105
wst04-VHDL20_DWMP_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 579261
wst04-VHDL20_DWMP_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:23 471236
wst04-VHDL20_DWMP_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:23 459518
wst04-VHDL20_DWMP_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 567036
wst04-VHDL20_DWMP_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:16 567182
wst04-VHDL20_DWMP_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:23 459557
wst04-VHDL20_DWMP_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 464262
wst04-VHDL20_DWPG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 236917
wst04-VHDL20_DWPG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:31 335226
wst04-VHDL20_DWPG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 380155
wst04-VHDL20_DWPG_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:31:22 336020
wst04-VHDL20_DWPG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 238598
wst04-VHDL20_DWPG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:32 336087
wst04-VHDL20_DWPG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 380925
wst04-VHDL20_DWPG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 341820
wst04-VHDL20_DWPH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 238713
wst04-VHDL20_DWPH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:31 239019
wst04-VHDL20_DWPH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 239418
wst04-VHDL20_DWPH_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:31:22 238873
wst04-VHDL20_DWPH_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:20 239232
wst04-VHDL20_DWPH_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:32 238946
wst04-VHDL20_DWPH_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:40 239129
wst04-VHDL20_DWPH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 241359
wst04-VHDL20_DWSG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 346625
wst04-VHDL20_DWSG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 346651
wst04-VHDL20_DWSG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:19 346866
wst04-VHDL20_DWSG_121800-2606121800-omedes--0.pdf 12-Jun-2026 18:30:23 346004
wst04-VHDL20_DWSG_130200-2606130200-omedes--0.pdf 13-Jun-2026 02:30:12 345862
wst04-VHDL20_DWSG_130400-2606130400-omedes--0.pdf 13-Jun-2026 05:00:12 345592
wst04-VHDL20_DWSG_130800-2606130800-omedes--0.pdf 13-Jun-2026 08:30:17 345740
wst04-VHDL20_DWSG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 347303