Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_250600                                 25-May-2026 12:33:17               16142
FPDL13_DWMZ_260600                                 26-May-2026 13:50:05                3749
SXDL31_DWAV_251800                                 25-May-2026 16:15:45                6151
SXDL31_DWAV_260800                                 26-May-2026 07:06:23               11711
SXDL31_DWAV_261800                                 26-May-2026 17:08:09                6240
SXDL31_DWAV_270800                                 27-May-2026 07:27:03               11554
SXDL31_DWAV_LATEST                                 27-May-2026 07:27:03               11554
SXDL33_DWAV_260000                                 26-May-2026 10:42:09                8108
SXDL33_DWAV_LATEST                                 26-May-2026 10:42:09                8108
ber01-FWDL39_DWMS_251230-2605251230-dsw--0-ia5     25-May-2026 11:42:16                 999
ber01-FWDL39_DWMS_261230-2605261230-dsw--0-ia5     26-May-2026 11:21:41                1721
ber01-VHDL13_DWEG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:30:43                2412
ber01-VHDL13_DWEG_260800-2605260800-dsw--0-ia5     26-May-2026 08:28:21                2833
ber01-VHDL13_DWEG_270800-2605270800-dsw--0-ia5     27-May-2026 08:28:22                2910
ber01-VHDL13_DWEH_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:30:57                2039
ber01-VHDL13_DWEH_260800-2605260800-dsw--0-ia5     26-May-2026 08:28:21                2328
ber01-VHDL13_DWEH_270800-2605270800-dsw--0-ia5     27-May-2026 08:28:16                2263
ber01-VHDL13_DWEI_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:31:19                2188
ber01-VHDL13_DWEI_260800-2605260800-dsw--0-ia5     26-May-2026 08:28:17                2582
ber01-VHDL13_DWEI_270800-2605270800-dsw--0-ia5     27-May-2026 08:28:16                2658
ber01-VHDL13_DWHG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2600
ber01-VHDL13_DWHG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                3011
ber01-VHDL13_DWHH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2833
ber01-VHDL13_DWHH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                3240
ber01-VHDL13_DWLG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2150
ber01-VHDL13_DWLG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2180
ber01-VHDL13_DWLH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2266
ber01-VHDL13_DWLH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2125
ber01-VHDL13_DWLI_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2105
ber01-VHDL13_DWLI_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2116
ber01-VHDL13_DWMO_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2864
ber01-VHDL13_DWMO_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2790
ber01-VHDL13_DWMP_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                3016
ber01-VHDL13_DWMP_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                3272
ber01-VHDL13_DWOG_251700-2605251700-dsw--0-ia5     25-May-2026 18:00:01                3023
ber01-VHDL13_DWOG_251700_COR-2605251700-dsw--0-ia5 25-May-2026 19:59:31                2905
ber01-VHDL13_DWOG_260300-2605260300-dsw--0-ia5     26-May-2026 03:00:02                3144
ber01-VHDL13_DWOG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                3073
ber01-VHDL13_DWOG_261700-2605261700-dsw--0-ia5     26-May-2026 18:00:02                3183
ber01-VHDL13_DWOG_270300-2605270300-dsw--0-ia5     27-May-2026 03:00:20                3724
ber01-VHDL13_DWOG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                3975
ber01-VHDL13_DWON_251444-2605251444-dsw--0-ia5     25-May-2026 14:44:14                3096
ber01-VHDL13_DWON_251633-2605251633-dsw--0-ia5     25-May-2026 16:33:21                3510
ber01-VHDL13_DWON_251958-2605251958-dsw--0-ia5     25-May-2026 19:58:57                3482
ber01-VHDL13_DWON_260232-2605260232-dsw--0-ia5     26-May-2026 02:32:27                3587
ber01-VHDL13_DWON_260529-2605260529-dsw--0-ia5     26-May-2026 05:29:41                3395
ber01-VHDL13_DWON_260530-2605260530-dsw--0-ia5     26-May-2026 05:30:57                3395
ber01-VHDL13_DWON_260608-2605260608-dsw--0-ia5     26-May-2026 06:08:07                3692
ber01-VHDL13_DWON_261126-2605261126-dsw--0-ia5     26-May-2026 11:26:37                3510
ber01-VHDL13_DWON_261435-2605261435-dsw--0-ia5     26-May-2026 14:35:29                3238
ber01-VHDL13_DWON_261706-2605261706-dsw--0-ia5     26-May-2026 17:07:01                2961
ber01-VHDL13_DWON_270255-2605270255-dsw--0-ia5     27-May-2026 02:55:17                3454
ber01-VHDL13_DWON_270531-2605270531-dsw--0-ia5     27-May-2026 05:31:27                3812
ber01-VHDL13_DWON_270604-2605270604-dsw--0-ia5     27-May-2026 06:04:42                3776
ber01-VHDL13_DWON_270807-2605270807-dsw--0-ia5     27-May-2026 08:07:37                4088
ber01-VHDL13_DWON_270849-2605270849-dsw--0-ia5     27-May-2026 08:49:53                4088
ber01-VHDL13_DWPG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2252
ber01-VHDL13_DWPG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2329
ber01-VHDL13_DWPH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2472
ber01-VHDL13_DWPH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                2536
ber01-VHDL13_DWSG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 12:36:03                2285
ber01-VHDL13_DWSG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                2451
ber01-VHDL13_DWSG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                3452
ber01-VHDL17_DWOG_251200-2605251200-dsw--0-ia5     25-May-2026 11:54:02                2623
ber01-VHDL17_DWOG_261200-2605261200-dsw--0-ia5     26-May-2026 12:00:38                2942
swis2-VHDL20_DWEG_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                 906
swis2-VHDL20_DWEG_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                 789
swis2-VHDL20_DWEG_260400-2605260400-dsw--0-ia5     26-May-2026 05:01:21                 912
swis2-VHDL20_DWEG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                1198
swis2-VHDL20_DWEG_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:01                1197
swis2-VHDL20_DWEG_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:00                 967
swis2-VHDL20_DWEG_270400-2605270400-dsw--0-ia5     27-May-2026 05:01:21                 975
swis2-VHDL20_DWEG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:01                1183
swis2-VHDL20_DWEH_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                 810
swis2-VHDL20_DWEH_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                 678
swis2-VHDL20_DWEH_260400-2605260400-dsw--0-ia5     26-May-2026 05:01:21                 771
swis2-VHDL20_DWEH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                 958
swis2-VHDL20_DWEH_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:01                 910
swis2-VHDL20_DWEH_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:00                 686
swis2-VHDL20_DWEH_270400-2605270400-dsw--0-ia5     27-May-2026 05:01:21                 686
swis2-VHDL20_DWEH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:01                 891
swis2-VHDL20_DWEI_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                 932
swis2-VHDL20_DWEI_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                 812
swis2-VHDL20_DWEI_260400-2605260400-dsw--0-ia5     26-May-2026 05:01:21                 934
swis2-VHDL20_DWEI_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                1222
swis2-VHDL20_DWEI_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:01                1221
swis2-VHDL20_DWEI_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:00                 991
swis2-VHDL20_DWEI_270400-2605270400-dsw--0-ia5     27-May-2026 05:01:21                 988
swis2-VHDL20_DWEI_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:01                1196
swis2-VHDL20_DWHG_251800-2605251800-dsw--0-ia5     25-May-2026 18:45:06                1076
swis2-VHDL20_DWHG_260200-2605260200-dsw--0-ia5     26-May-2026 02:45:04                 941
swis2-VHDL20_DWHG_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:22                 938
swis2-VHDL20_DWHG_260800-2605260800-dsw--0-ia5     26-May-2026 08:45:01                1013
swis2-VHDL20_DWHG_261800-2605261800-dsw--0-ia5     26-May-2026 18:45:02                1238
swis2-VHDL20_DWHG_270200-2605270200-dsw--0-ia5     27-May-2026 02:45:04                1003
swis2-VHDL20_DWHG_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:16                1000
swis2-VHDL20_DWHG_270800-2605270800-dsw--0-ia5     27-May-2026 08:45:08                1414
swis2-VHDL20_DWHH_251800-2605251800-dsw--0-ia5     25-May-2026 18:45:06                1083
swis2-VHDL20_DWHH_260200-2605260200-dsw--0-ia5     26-May-2026 02:45:04                 936
swis2-VHDL20_DWHH_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:22                 936
swis2-VHDL20_DWHH_260800-2605260800-dsw--0-ia5     26-May-2026 08:45:01                1121
swis2-VHDL20_DWHH_261800-2605261800-dsw--0-ia5     26-May-2026 18:45:02                1313
swis2-VHDL20_DWHH_270200-2605270200-dsw--0-ia5     27-May-2026 02:45:04                1102
swis2-VHDL20_DWHH_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:16                1102
swis2-VHDL20_DWHH_270800-2605270800-dsw--0-ia5     27-May-2026 08:45:08                1539
swis2-VHDL20_DWLG_251800-2605251800-dsw--0-ia5     25-May-2026 18:31:03                 812
swis2-VHDL20_DWLG_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:21                 715
swis2-VHDL20_DWLG_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                 962
swis2-VHDL20_DWLG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:22                1056
swis2-VHDL20_DWLG_261800-2605261800-dsw--0-ia5     26-May-2026 18:31:06                1243
swis2-VHDL20_DWLG_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:21                1160
swis2-VHDL20_DWLG_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:12                 805
swis2-VHDL20_DWLG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:20                1008
swis2-VHDL20_DWLH_251800-2605251800-dsw--0-ia5     25-May-2026 18:31:03                 819
swis2-VHDL20_DWLH_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:21                 722
swis2-VHDL20_DWLH_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                 968
swis2-VHDL20_DWLH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:22                1062
swis2-VHDL20_DWLH_261800-2605261800-dsw--0-ia5     26-May-2026 18:31:06                1168
swis2-VHDL20_DWLH_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:21                1082
swis2-VHDL20_DWLH_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:12                 816
swis2-VHDL20_DWLH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:20                 918
swis2-VHDL20_DWLI_251800-2605251800-dsw--0-ia5     25-May-2026 18:31:03                 814
swis2-VHDL20_DWLI_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:21                 717
swis2-VHDL20_DWLI_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                 964
swis2-VHDL20_DWLI_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:22                1058
swis2-VHDL20_DWLI_261800-2605261800-dsw--0-ia5     26-May-2026 18:31:06                1245
swis2-VHDL20_DWLI_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:21                1075
swis2-VHDL20_DWLI_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:12                 809
swis2-VHDL20_DWLI_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:20                1030
swis2-VHDL20_DWMO_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                1409
swis2-VHDL20_DWMO_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                1218
swis2-VHDL20_DWMO_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:02                1185
swis2-VHDL20_DWMO_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                1311
swis2-VHDL20_DWMO_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:03                1188
swis2-VHDL20_DWMO_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:00                 966
swis2-VHDL20_DWMO_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:02                1131
swis2-VHDL20_DWMO_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                1258
swis2-VHDL20_DWMP_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                1543
swis2-VHDL20_DWMP_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                1310
swis2-VHDL20_DWMP_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:02                1265
swis2-VHDL20_DWMP_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                1400
swis2-VHDL20_DWMP_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:03                1531
swis2-VHDL20_DWMP_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:00                1315
swis2-VHDL20_DWMP_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:02                1559
swis2-VHDL20_DWMP_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                1515
swis2-VHDL20_DWPG_251800-2605251800-dsw--0-ia5     25-May-2026 18:31:03                 830
swis2-VHDL20_DWPG_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:21                 733
swis2-VHDL20_DWPG_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                 980
swis2-VHDL20_DWPG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:22                1074
swis2-VHDL20_DWPG_261800-2605261800-dsw--0-ia5     26-May-2026 18:31:06                1185
swis2-VHDL20_DWPG_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:21                1091
swis2-VHDL20_DWPG_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:12                1069
swis2-VHDL20_DWPG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:20                1171
swis2-VHDL20_DWPH_251800-2605251800-dsw--0-ia5     25-May-2026 18:31:03                 858
swis2-VHDL20_DWPH_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:21                 782
swis2-VHDL20_DWPH_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                1028
swis2-VHDL20_DWPH_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:22                1122
swis2-VHDL20_DWPH_261800-2605261800-dsw--0-ia5     26-May-2026 18:31:06                1320
swis2-VHDL20_DWPH_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:21                1183
swis2-VHDL20_DWPH_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:12                1133
swis2-VHDL20_DWPH_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:20                1241
swis2-VHDL20_DWSG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 12:36:03                 964
swis2-VHDL20_DWSG_251800-2605251800-dsw--0-ia5     25-May-2026 18:30:01                1226
swis2-VHDL20_DWSG_260200-2605260200-dsw--0-ia5     26-May-2026 02:30:03                1117
swis2-VHDL20_DWSG_260400-2605260400-dsw--0-ia5     26-May-2026 05:00:16                1134
swis2-VHDL20_DWSG_260800-2605260800-dsw--0-ia5     26-May-2026 08:30:16                1288
swis2-VHDL20_DWSG_261800-2605261800-dsw--0-ia5     26-May-2026 18:30:01                1402
swis2-VHDL20_DWSG_270200-2605270200-dsw--0-ia5     27-May-2026 02:30:06                1090
swis2-VHDL20_DWSG_270400-2605270400-dsw--0-ia5     27-May-2026 05:00:22                1302
swis2-VHDL20_DWSG_270800-2605270800-dsw--0-ia5     27-May-2026 08:30:17                1472
wst04-VHDL20_DWEG_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:11              243082
wst04-VHDL20_DWEG_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:10              242252
wst04-VHDL20_DWEG_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:12              242970
wst04-VHDL20_DWEG_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:16              244024
wst04-VHDL20_DWEG_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:11              242691
wst04-VHDL20_DWEG_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:13              241757
wst04-VHDL20_DWEG_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:12              241617
wst04-VHDL20_DWEG_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:17              242440
wst04-VHDL20_DWEH_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:11              236942
wst04-VHDL20_DWEH_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:10              236514
wst04-VHDL20_DWEH_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:12              237126
wst04-VHDL20_DWEH_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:16              238300
wst04-VHDL20_DWEH_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:11              238936
wst04-VHDL20_DWEH_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:13              237909
wst04-VHDL20_DWEH_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:12              238030
wst04-VHDL20_DWEH_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:17              239284
wst04-VHDL20_DWEI_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:18              345305
wst04-VHDL20_DWEI_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:16              345024
wst04-VHDL20_DWEI_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:12              345673
wst04-VHDL20_DWEI_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:16              346249
wst04-VHDL20_DWEI_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:16              346151
wst04-VHDL20_DWEI_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:13              345856
wst04-VHDL20_DWEI_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:12              345593
wst04-VHDL20_DWEI_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:17              345869
wst04-VHDL20_DWHG_251800-2605251800-omedes--0.pdf  25-May-2026 18:45:12              341379
wst04-VHDL20_DWHG_260200-2605260200-omedes--0.pdf  26-May-2026 02:45:19              341170
wst04-VHDL20_DWHG_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:22              340947
wst04-VHDL20_DWHG_260800-2605260800-omedes--0.pdf  26-May-2026 08:45:12              341421
wst04-VHDL20_DWHG_261800-2605261800-omedes--0.pdf  26-May-2026 18:45:12              341204
wst04-VHDL20_DWHG_270200-2605270200-omedes--0.pdf  27-May-2026 02:45:12              340340
wst04-VHDL20_DWHG_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:16              340108
wst04-VHDL20_DWHG_270800-2605270800-omedes--0.pdf  27-May-2026 08:45:13              342251
wst04-VHDL20_DWHH_251800-2605251800-omedes--0.pdf  25-May-2026 18:45:12              334876
wst04-VHDL20_DWHH_260200-2605260200-omedes--0.pdf  26-May-2026 02:45:19              334360
wst04-VHDL20_DWHH_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:16              229063
wst04-VHDL20_DWHH_260800-2605260800-omedes--0.pdf  26-May-2026 08:45:12              334654
wst04-VHDL20_DWHH_261800-2605261800-omedes--0.pdf  26-May-2026 18:45:12              339124
wst04-VHDL20_DWHH_270200-2605270200-omedes--0.pdf  27-May-2026 02:45:12              338524
wst04-VHDL20_DWHH_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:16              230995
wst04-VHDL20_DWHH_270800-2605270800-omedes--0.pdf  27-May-2026 08:45:13              340244
wst04-VHDL20_DWLG_251800-2605251800-omedes--0.pdf  25-May-2026 18:31:24              325745
wst04-VHDL20_DWLG_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:21              325634
wst04-VHDL20_DWLG_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:52              326579
wst04-VHDL20_DWLG_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:42              326592
wst04-VHDL20_DWLG_261800-2605261800-omedes--0.pdf  26-May-2026 18:31:22              337487
wst04-VHDL20_DWLG_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:21              337541
wst04-VHDL20_DWLG_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:40              335833
wst04-VHDL20_DWLG_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:46              336458
wst04-VHDL20_DWLH_251800-2605251800-omedes--0.pdf  25-May-2026 18:31:24              326204
wst04-VHDL20_DWLH_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:21              326077
wst04-VHDL20_DWLH_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:46              327017
wst04-VHDL20_DWLH_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:42              327039
wst04-VHDL20_DWLH_261800-2605261800-omedes--0.pdf  26-May-2026 18:31:22              337634
wst04-VHDL20_DWLH_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:21              337057
wst04-VHDL20_DWLH_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:40              336065
wst04-VHDL20_DWLH_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:46              336624
wst04-VHDL20_DWLI_251800-2605251800-omedes--0.pdf  25-May-2026 18:31:24              335366
wst04-VHDL20_DWLI_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:28              335271
wst04-VHDL20_DWLI_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:42              336182
wst04-VHDL20_DWLI_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:49              380792
wst04-VHDL20_DWLI_261800-2605261800-omedes--0.pdf  26-May-2026 18:31:26              342400
wst04-VHDL20_DWLI_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:26              341774
wst04-VHDL20_DWLI_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:40              340762
wst04-VHDL20_DWLI_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:46              386011
wst04-VHDL20_DWMO_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:18              349432
wst04-VHDL20_DWMO_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:16              456761
wst04-VHDL20_DWMO_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:16              457458
wst04-VHDL20_DWMO_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:22              457527
wst04-VHDL20_DWMO_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:16              356924
wst04-VHDL20_DWMO_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:15              470220
wst04-VHDL20_DWMO_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:16              469253
wst04-VHDL20_DWMO_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:23              469447
wst04-VHDL20_DWMP_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:18              471660
wst04-VHDL20_DWMP_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:16              574742
wst04-VHDL20_DWMP_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:16              574514
wst04-VHDL20_DWMP_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:22              471244
wst04-VHDL20_DWMP_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:22              477692
wst04-VHDL20_DWMP_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:15              584852
wst04-VHDL20_DWMP_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:22              584402
wst04-VHDL20_DWMP_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:23              477758
wst04-VHDL20_DWPG_251800-2605251800-omedes--0.pdf  25-May-2026 18:31:26              333976
wst04-VHDL20_DWPG_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:21              234031
wst04-VHDL20_DWPG_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:32              334836
wst04-VHDL20_DWPG_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:42              379409
wst04-VHDL20_DWPG_261800-2605261800-omedes--0.pdf  26-May-2026 18:31:22              333323
wst04-VHDL20_DWPG_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:21              234770
wst04-VHDL20_DWPG_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:32              332592
wst04-VHDL20_DWPG_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:46              377674
wst04-VHDL20_DWPH_251800-2605251800-omedes--0.pdf  25-May-2026 18:31:24              240384
wst04-VHDL20_DWPH_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:21              240137
wst04-VHDL20_DWPH_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:32              240614
wst04-VHDL20_DWPH_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:42              240775
wst04-VHDL20_DWPH_261800-2605261800-omedes--0.pdf  26-May-2026 18:31:22              240093
wst04-VHDL20_DWPH_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:21              239477
wst04-VHDL20_DWPH_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:32              239302
wst04-VHDL20_DWPH_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:46              239845
wst04-VHDL20_DWSG_250800-2605250800-omedes--0.pdf  25-May-2026 12:36:03              343699
wst04-VHDL20_DWSG_251800-2605251800-omedes--0.pdf  25-May-2026 18:30:18              345234
wst04-VHDL20_DWSG_260200-2605260200-omedes--0.pdf  26-May-2026 02:30:10              344564
wst04-VHDL20_DWSG_260400-2605260400-omedes--0.pdf  26-May-2026 05:00:12              345270
wst04-VHDL20_DWSG_260800-2605260800-omedes--0.pdf  26-May-2026 08:30:16              345781
wst04-VHDL20_DWSG_261800-2605261800-omedes--0.pdf  26-May-2026 18:30:16              352435
wst04-VHDL20_DWSG_270200-2605270200-omedes--0.pdf  27-May-2026 02:30:10              351609
wst04-VHDL20_DWSG_270400-2605270400-omedes--0.pdf  27-May-2026 05:00:12              353146
wst04-VHDL20_DWSG_270800-2605270800-omedes--0.pdf  27-May-2026 08:30:17              353284