Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Jul-2026 13:40:45 4034
FPDL13_DWMZ_160600 16-Jul-2026 13:04:34 5972
SXDL31_DWAV_151800 15-Jul-2026 17:13:19 10555
SXDL31_DWAV_160800 16-Jul-2026 07:35:41 8891
SXDL31_DWAV_161800 16-Jul-2026 17:21:53 11065
SXDL31_DWAV_170800 17-Jul-2026 07:49:25 18211
SXDL31_DWAV_LATEST 17-Jul-2026 07:49:25 18211
SXDL33_DWAV_160000 16-Jul-2026 09:45:11 13108
SXDL33_DWAV_170000 17-Jul-2026 09:25:59 5210
SXDL33_DWAV_LATEST 17-Jul-2026 09:25:59 5210
ber01-FWDL39_DWMS_151200-2607151200-dsw--0-ia5 15-Jul-2026 10:38:55 1524
ber01-FWDL39_DWMS_161200-2607161200-dsw--0-ia5 16-Jul-2026 11:11:17 2461
ber01-VHDL13_DWEG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3684
ber01-VHDL13_DWEG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:28:17 3526
ber01-VHDL13_DWEH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3286
ber01-VHDL13_DWEH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:28:17 3011
ber01-VHDL13_DWEI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3676
ber01-VHDL13_DWEI_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:28:17 3355
ber01-VHDL13_DWHG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 4261
ber01-VHDL13_DWHG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:11 4170
ber01-VHDL13_DWHH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 3961
ber01-VHDL13_DWHH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:11 3975
ber01-VHDL13_DWLG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3464
ber01-VHDL13_DWLG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3647
ber01-VHDL13_DWLH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3569
ber01-VHDL13_DWLH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3639
ber01-VHDL13_DWLI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3315
ber01-VHDL13_DWLI_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3408
ber01-VHDL13_DWMO_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3834
ber01-VHDL13_DWMO_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 08:59:56 3843
ber01-VHDL13_DWMO_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3873
ber01-VHDL13_DWMP_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3670
ber01-VHDL13_DWMP_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 09:01:27 3679
ber01-VHDL13_DWMP_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 4099
ber01-VHDL13_DWOG_151700-2607151700-dsw--0-ia5 15-Jul-2026 18:00:01 4427
ber01-VHDL13_DWOG_160300-2607160300-dsw--0-ia5 16-Jul-2026 03:00:10 4223
ber01-VHDL13_DWOG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 5466
ber01-VHDL13_DWOG_161700-2607161700-dsw--0-ia5 16-Jul-2026 18:00:02 5242
ber01-VHDL13_DWOG_170300-2607170300-dsw--0-ia5 17-Jul-2026 03:00:06 4804
ber01-VHDL13_DWOG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 4997
ber01-VHDL13_DWON_151443-2607151443-dsw--0-ia5 15-Jul-2026 14:43:17 3903
ber01-VHDL13_DWON_151447-2607151447-dsw--0-ia5 15-Jul-2026 14:48:40 3900
ber01-VHDL13_DWON_151718-2607151718-dsw--0-ia5 15-Jul-2026 17:18:01 3276
ber01-VHDL13_DWON_160126-2607160126-dsw--0-ia5 16-Jul-2026 01:26:22 3839
ber01-VHDL13_DWON_160232-2607160232-dsw--0-ia5 16-Jul-2026 02:32:50 3839
ber01-VHDL13_DWON_160513-2607160513-dsw--0-ia5 16-Jul-2026 05:13:37 4045
ber01-VHDL13_DWON_160531-2607160531-dsw--0-ia5 16-Jul-2026 05:31:27 4356
ber01-VHDL13_DWON_160651-2607160651-dsw--0-ia5 16-Jul-2026 06:51:07 4356
ber01-VHDL13_DWON_160823-2607160823-dsw--0-ia5 16-Jul-2026 08:23:27 4316
ber01-VHDL13_DWON_161341-2607161341-dsw--0-ia5 16-Jul-2026 13:41:51 4252
ber01-VHDL13_DWON_161447-2607161447-dsw--0-ia5 16-Jul-2026 14:48:32 4188
ber01-VHDL13_DWON_161728-2607161728-dsw--0-ia5 16-Jul-2026 17:28:06 3705
ber01-VHDL13_DWON_162141-2607162141-dsw--0-ia5 16-Jul-2026 21:41:20 3957
ber01-VHDL13_DWON_170100-2607170100-dsw--0-ia5 17-Jul-2026 01:01:02 4051
ber01-VHDL13_DWON_170240-2607170240-dsw--0-ia5 17-Jul-2026 02:40:30 4050
ber01-VHDL13_DWON_170453-2607170453-dsw--0-ia5 17-Jul-2026 04:54:02 4435
ber01-VHDL13_DWON_170534-2607170534-dsw--0-ia5 17-Jul-2026 05:34:47 4435
ber01-VHDL13_DWON_170612-2607170612-dsw--0-ia5 17-Jul-2026 06:12:37 4435
ber01-VHDL13_DWON_170805-2607170805-dsw--0-ia5 17-Jul-2026 08:05:32 4435
ber01-VHDL13_DWPG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3692
ber01-VHDL13_DWPG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3742
ber01-VHDL13_DWPH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3973
ber01-VHDL13_DWPH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3912
ber01-VHDL13_DWSG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3629
ber01-VHDL13_DWSG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 3588
ber01-VHDL17_DWOG_151200-2607151200-dsw--0-ia5 15-Jul-2026 11:22:41 2858
ber01-VHDL17_DWOG_161200-2607161200-dsw--0-ia5 16-Jul-2026 10:47:01 3829
swis2-VHDL20_DWEG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 2002
swis2-VHDL20_DWEG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1737
swis2-VHDL20_DWEG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1699
swis2-VHDL20_DWEG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 2006
swis2-VHDL20_DWEG_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1666
swis2-VHDL20_DWEG_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1374
swis2-VHDL20_DWEG_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:01:17 1566
swis2-VHDL20_DWEG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 1748
swis2-VHDL20_DWEH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1613
swis2-VHDL20_DWEH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1371
swis2-VHDL20_DWEH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1358
swis2-VHDL20_DWEH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 1525
swis2-VHDL20_DWEH_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1724
swis2-VHDL20_DWEH_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1183
swis2-VHDL20_DWEH_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:01:17 1317
swis2-VHDL20_DWEH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 1494
swis2-VHDL20_DWEI_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1943
swis2-VHDL20_DWEI_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1753
swis2-VHDL20_DWEI_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1716
swis2-VHDL20_DWEI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 2077
swis2-VHDL20_DWEI_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1945
swis2-VHDL20_DWEI_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1578
swis2-VHDL20_DWEI_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:01:17 1783
swis2-VHDL20_DWEI_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 1826
swis2-VHDL20_DWHG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:45:06 2553
swis2-VHDL20_DWHG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:45:40 2181
swis2-VHDL20_DWHG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:16 2178
swis2-VHDL20_DWHG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:45:13 2402
swis2-VHDL20_DWHG_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:45:17 2158
swis2-VHDL20_DWHG_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:45:05 2035
swis2-VHDL20_DWHG_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:17 2033
swis2-VHDL20_DWHG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:45:16 2199
swis2-VHDL20_DWHH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:45:06 2441
swis2-VHDL20_DWHH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:45:40 2081
swis2-VHDL20_DWHH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:16 2120
swis2-VHDL20_DWHH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:45:03 2435
swis2-VHDL20_DWHH_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:45:17 2162
swis2-VHDL20_DWHH_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:45:05 2001
swis2-VHDL20_DWHH_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:17 2002
swis2-VHDL20_DWHH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:45:16 2169
swis2-VHDL20_DWLG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1678
swis2-VHDL20_DWLG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1452
swis2-VHDL20_DWLG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1509
swis2-VHDL20_DWLG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1768
swis2-VHDL20_DWLG_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:31:07 1546
swis2-VHDL20_DWLG_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:24 1335
swis2-VHDL20_DWLG_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:11 1664
swis2-VHDL20_DWLG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:21 1851
swis2-VHDL20_DWLH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1521
swis2-VHDL20_DWLH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1292
swis2-VHDL20_DWLH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1506
swis2-VHDL20_DWLH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1850
swis2-VHDL20_DWLH_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:31:07 1785
swis2-VHDL20_DWLH_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:24 1531
swis2-VHDL20_DWLH_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:11 1632
swis2-VHDL20_DWLH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:21 1917
swis2-VHDL20_DWLI_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1527
swis2-VHDL20_DWLI_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1347
swis2-VHDL20_DWLI_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1389
swis2-VHDL20_DWLI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1650
swis2-VHDL20_DWLI_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:31:07 1530
swis2-VHDL20_DWLI_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:24 1314
swis2-VHDL20_DWLI_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:11 1456
swis2-VHDL20_DWLI_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:21 1682
swis2-VHDL20_DWMO_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1620
swis2-VHDL20_DWMO_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1462
swis2-VHDL20_DWMO_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:02 1540
swis2-VHDL20_DWMO_160400_COR-2607160400-dsw--0-ia5 16-Jul-2026 05:48:32 3138
swis2-VHDL20_DWMO_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 2110
swis2-VHDL20_DWMO_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 08:59:56 3623
swis2-VHDL20_DWMO_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1919
swis2-VHDL20_DWMO_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1640
swis2-VHDL20_DWMO_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:01 1641
swis2-VHDL20_DWMO_170400_COR-2607170400-dsw--0-ia5 17-Jul-2026 05:09:06 3042
swis2-VHDL20_DWMO_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 2120
swis2-VHDL20_DWMP_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1757
swis2-VHDL20_DWMP_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1513
swis2-VHDL20_DWMP_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:02 1590
swis2-VHDL20_DWMP_160400_COR-2607160400-dsw--0-ia5 16-Jul-2026 05:57:11 3275
swis2-VHDL20_DWMP_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 2168
swis2-VHDL20_DWMP_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 09:01:27 3483
swis2-VHDL20_DWMP_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1926
swis2-VHDL20_DWMP_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1698
swis2-VHDL20_DWMP_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:01 1698
swis2-VHDL20_DWMP_170400_COR-2607170400-dsw--0-ia5 17-Jul-2026 05:09:11 3065
swis2-VHDL20_DWMP_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 2260
swis2-VHDL20_DWPG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1573
swis2-VHDL20_DWPG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1394
swis2-VHDL20_DWPG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1592
swis2-VHDL20_DWPG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1932
swis2-VHDL20_DWPG_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:31:07 1723
swis2-VHDL20_DWPG_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:24 1386
swis2-VHDL20_DWPG_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:11 1643
swis2-VHDL20_DWPG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:21 1975
swis2-VHDL20_DWPH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1579
swis2-VHDL20_DWPH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1428
swis2-VHDL20_DWPH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1681
swis2-VHDL20_DWPH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 2082
swis2-VHDL20_DWPH_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:31:07 1907
swis2-VHDL20_DWPH_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:24 1540
swis2-VHDL20_DWPH_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:11 1829
swis2-VHDL20_DWPH_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:21 1985
swis2-VHDL20_DWSG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1894
swis2-VHDL20_DWSG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:07 1481
swis2-VHDL20_DWSG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:18 1489
swis2-VHDL20_DWSG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 1860
swis2-VHDL20_DWSG_161800-2607161800-dsw--0-ia5 16-Jul-2026 18:30:08 1760
swis2-VHDL20_DWSG_170200-2607170200-dsw--0-ia5 17-Jul-2026 02:30:02 1821
swis2-VHDL20_DWSG_170400-2607170400-dsw--0-ia5 17-Jul-2026 05:00:21 1574
swis2-VHDL20_DWSG_170800-2607170800-dsw--0-ia5 17-Jul-2026 08:30:02 1797
wst04-VHDL20_DWEG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:14 244029
wst04-VHDL20_DWEG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 243367
wst04-VHDL20_DWEG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 242939
wst04-VHDL20_DWEG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:11 244541
wst04-VHDL20_DWEG_161800-2607161800-omedes--0.pdf 16-Jul-2026 18:30:16 244828
wst04-VHDL20_DWEG_170200-2607170200-omedes--0.pdf 17-Jul-2026 02:30:13 244439
wst04-VHDL20_DWEG_170400-2607170400-omedes--0.pdf 17-Jul-2026 05:00:11 244071
wst04-VHDL20_DWEG_170800-2607170800-omedes--0.pdf 17-Jul-2026 08:30:11 244920
wst04-VHDL20_DWEH_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:14 238224
wst04-VHDL20_DWEH_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 238190
wst04-VHDL20_DWEH_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 237651
wst04-VHDL20_DWEH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:11 238406
wst04-VHDL20_DWEH_161800-2607161800-omedes--0.pdf 16-Jul-2026 18:30:16 234359
wst04-VHDL20_DWEH_170200-2607170200-omedes--0.pdf 17-Jul-2026 02:30:13 234392
wst04-VHDL20_DWEH_170400-2607170400-omedes--0.pdf 17-Jul-2026 05:00:11 233808
wst04-VHDL20_DWEH_170800-2607170800-omedes--0.pdf 17-Jul-2026 08:30:11 234645
wst04-VHDL20_DWEI_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:22 351835
wst04-VHDL20_DWEI_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 351769
wst04-VHDL20_DWEI_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 351334
wst04-VHDL20_DWEI_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:18 352836
wst04-VHDL20_DWEI_161800-2607161800-omedes--0.pdf 16-Jul-2026 18:30:16 349075
wst04-VHDL20_DWEI_170200-2607170200-omedes--0.pdf 17-Jul-2026 02:30:17 349045
wst04-VHDL20_DWEI_170400-2607170400-omedes--0.pdf 17-Jul-2026 05:00:11 348958
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wst04-VHDL20_DWHH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:45:13 343595
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wst04-VHDL20_DWLH_170800-2607170800-omedes--0.pdf 17-Jul-2026 08:30:40 338628
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wst04-VHDL20_DWLI_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 344746
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wst04-VHDL20_DWLI_170200-2607170200-omedes--0.pdf 17-Jul-2026 02:30:24 340471
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wst04-VHDL20_DWMO_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:18 474347
wst04-VHDL20_DWMO_160400_COR-2607160400-omedes-..> 16-Jul-2026 05:48:42 478862
wst04-VHDL20_DWMO_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:18 476001
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wst04-VHDL20_DWMO_170200-2607170200-omedes--0.pdf 17-Jul-2026 02:30:13 470675
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wst04-VHDL20_DWMP_170400_COR-2607170400-omedes-..> 17-Jul-2026 05:09:17 584237
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wst04-VHDL20_DWSG_170800-2607170800-omedes--0.pdf 17-Jul-2026 08:30:19 359198