Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_290600 29-Jul-2026 13:58:19 4318
FPDL13_DWMZ_300600 30-Jul-2026 13:13:54 5536
SXDL31_DWAV_290800 29-Jul-2026 08:47:28 7174
SXDL31_DWAV_291800 29-Jul-2026 16:00:53 4115
SXDL31_DWAV_300800 30-Jul-2026 08:24:38 8868
SXDL31_DWAV_301800 30-Jul-2026 16:14:21 3931
SXDL31_DWAV_LATEST 30-Jul-2026 16:14:21 3931
SXDL33_DWAV_290000 29-Jul-2026 09:26:39 12922
SXDL33_DWAV_300000 30-Jul-2026 09:43:43 21627
SXDL33_DWAV_LATEST 30-Jul-2026 09:43:43 21627
ber01-FWDL39_DWMS_291200-2607291200-dsw--0-ia5 29-Jul-2026 11:38:38 1605
ber01-FWDL39_DWMS_301200-2607301200-dsw--0-ia5 30-Jul-2026 11:02:17 2011
ber01-VHDL13_DWEG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:17 3680
ber01-VHDL13_DWEG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:27 4849
ber01-VHDL13_DWEH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:27 3604
ber01-VHDL13_DWEH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:21 4847
ber01-VHDL13_DWEI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:27 3732
ber01-VHDL13_DWEI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:21 4705
ber01-VHDL13_DWHG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3776
ber01-VHDL13_DWHG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4199
ber01-VHDL13_DWHH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3769
ber01-VHDL13_DWHH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4142
ber01-VHDL13_DWLG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3478
ber01-VHDL13_DWLG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 4155
ber01-VHDL13_DWLH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3523
ber01-VHDL13_DWLH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4045
ber01-VHDL13_DWLI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3380
ber01-VHDL13_DWLI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4065
ber01-VHDL13_DWMO_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3464
ber01-VHDL13_DWMO_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4078
ber01-VHDL13_DWMP_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3594
ber01-VHDL13_DWMP_290800_COR-2607290800-dsw--0-ia5 29-Jul-2026 16:51:48 3846
ber01-VHDL13_DWMP_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 3972
ber01-VHDL13_DWOG_290300-2607290300-dsw--0-ia5 29-Jul-2026 03:00:24 4258
ber01-VHDL13_DWOG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 4100
ber01-VHDL13_DWOG_291700-2607291700-dsw--0-ia5 29-Jul-2026 18:00:07 3823
ber01-VHDL13_DWOG_300300-2607300300-dsw--0-ia5 30-Jul-2026 03:00:04 4299
ber01-VHDL13_DWOG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4250
ber01-VHDL13_DWOG_301700-2607301700-dsw--0-ia5 30-Jul-2026 18:00:08 3919
ber01-VHDL13_DWON_290008-2607290008-dsw--0-ia5 29-Jul-2026 00:08:07 4150
ber01-VHDL13_DWON_290131-2607290131-dsw--0-ia5 29-Jul-2026 01:32:03 4042
ber01-VHDL13_DWON_290248-2607290248-dsw--0-ia5 29-Jul-2026 02:49:03 4042
ber01-VHDL13_DWON_290541-2607290541-dsw--0-ia5 29-Jul-2026 05:41:05 3628
ber01-VHDL13_DWON_290835-2607290835-dsw--0-ia5 29-Jul-2026 08:35:26 3580
ber01-VHDL13_DWON_291511-2607291511-dsw--0-ia5 29-Jul-2026 15:11:22 3990
ber01-VHDL13_DWON_291722-2607291722-dsw--0-ia5 29-Jul-2026 17:22:21 3463
ber01-VHDL13_DWON_292214-2607292214-dsw--0-ia5 29-Jul-2026 22:14:23 4012
ber01-VHDL13_DWON_300054-2607300054-dsw--0-ia5 30-Jul-2026 00:54:56 4012
ber01-VHDL13_DWON_300239-2607300239-dsw--0-ia5 30-Jul-2026 02:39:34 4043
ber01-VHDL13_DWON_300530-2607300530-dsw--0-ia5 30-Jul-2026 05:31:01 4043
ber01-VHDL13_DWON_300612-2607300612-dsw--0-ia5 30-Jul-2026 06:12:16 3939
ber01-VHDL13_DWON_300849-2607300849-dsw--0-ia5 30-Jul-2026 08:49:33 3939
ber01-VHDL13_DWON_301103-2607301103-dsw--0-ia5 30-Jul-2026 11:03:11 3939
ber01-VHDL13_DWON_301534-2607301534-dsw--0-ia5 30-Jul-2026 15:34:51 3270
ber01-VHDL13_DWON_301719-2607301719-dsw--0-ia5 30-Jul-2026 17:19:07 3329
ber01-VHDL13_DWON_301804-2607301804-dsw--0-ia5 30-Jul-2026 18:04:57 3329
ber01-VHDL13_DWON_302052-2607302052-dsw--0-ia5 30-Jul-2026 20:52:58 3900
ber01-VHDL13_DWON_302059-2607302059-dsw--0-ia5 30-Jul-2026 20:59:11 3900
ber01-VHDL13_DWON_302145-2607302145-dsw--0-ia5 30-Jul-2026 21:45:30 3896
ber01-VHDL13_DWPG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3352
ber01-VHDL13_DWPG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 4129
ber01-VHDL13_DWPH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3495
ber01-VHDL13_DWPH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4181
ber01-VHDL13_DWSG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3458
ber01-VHDL13_DWSG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 3854
ber01-VHDL13_DWSG_300800_COR-2607300800-dsw--0-ia5 30-Jul-2026 14:29:57 4076
ber01-VHDL17_DWOG_291200-2607291200-dsw--0-ia5 29-Jul-2026 11:05:32 2973
ber01-VHDL17_DWOG_301200-2607301200-dsw--0-ia5 30-Jul-2026 10:51:21 3321
swis2-VHDL20_DWEG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1616
swis2-VHDL20_DWEG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1633
swis2-VHDL20_DWEG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1891
swis2-VHDL20_DWEG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2669
swis2-VHDL20_DWEG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2201
swis2-VHDL20_DWEG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2202
swis2-VHDL20_DWEG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2524
swis2-VHDL20_DWEG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2034
swis2-VHDL20_DWEH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1628
swis2-VHDL20_DWEH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1645
swis2-VHDL20_DWEH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1815
swis2-VHDL20_DWEH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2685
swis2-VHDL20_DWEH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2301
swis2-VHDL20_DWEH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2302
swis2-VHDL20_DWEH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2545
swis2-VHDL20_DWEH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 1485
swis2-VHDL20_DWEI_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1634
swis2-VHDL20_DWEI_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1634
swis2-VHDL20_DWEI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1909
swis2-VHDL20_DWEI_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2536
swis2-VHDL20_DWEI_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2098
swis2-VHDL20_DWEI_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2099
swis2-VHDL20_DWEI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2405
swis2-VHDL20_DWEI_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2051
swis2-VHDL20_DWHG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:45:20 1609
swis2-VHDL20_DWHG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1680
swis2-VHDL20_DWHG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:45:05 2369
swis2-VHDL20_DWHG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:45:13 2307
swis2-VHDL20_DWHG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:45:37 2284
swis2-VHDL20_DWHG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 2364
swis2-VHDL20_DWHG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:45:57 2586
swis2-VHDL20_DWHG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:45:05 2216
swis2-VHDL20_DWHH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:45:20 1671
swis2-VHDL20_DWHH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1816
swis2-VHDL20_DWHH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:45:05 2463
swis2-VHDL20_DWHH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:45:13 2410
swis2-VHDL20_DWHH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:45:37 2373
swis2-VHDL20_DWHH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 2394
swis2-VHDL20_DWHH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:45:57 2627
swis2-VHDL20_DWHH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:45:05 1730
swis2-VHDL20_DWLG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1272
swis2-VHDL20_DWLG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1547
swis2-VHDL20_DWLG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1723
swis2-VHDL20_DWLG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2223
swis2-VHDL20_DWLG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2041
swis2-VHDL20_DWLG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:16 2043
swis2-VHDL20_DWLG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2390
swis2-VHDL20_DWLG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2333
swis2-VHDL20_DWLH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1471
swis2-VHDL20_DWLH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1533
swis2-VHDL20_DWLH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1697
swis2-VHDL20_DWLH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2173
swis2-VHDL20_DWLH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 1967
swis2-VHDL20_DWLH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 1962
swis2-VHDL20_DWLH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2304
swis2-VHDL20_DWLH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2142
swis2-VHDL20_DWLI_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1466
swis2-VHDL20_DWLI_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1528
swis2-VHDL20_DWLI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1704
swis2-VHDL20_DWLI_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2115
swis2-VHDL20_DWLI_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 1931
swis2-VHDL20_DWLI_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 1932
swis2-VHDL20_DWLI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2273
swis2-VHDL20_DWLI_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2067
swis2-VHDL20_DWMO_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:01 1397
swis2-VHDL20_DWMO_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:01 1509
swis2-VHDL20_DWMO_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 1699
swis2-VHDL20_DWMO_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 1993
swis2-VHDL20_DWMO_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1927
swis2-VHDL20_DWMO_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:08 2153
swis2-VHDL20_DWMO_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2427
swis2-VHDL20_DWMO_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2008
swis2-VHDL20_DWMP_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1237
swis2-VHDL20_DWMP_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:01 1409
swis2-VHDL20_DWMP_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 1672
swis2-VHDL20_DWMP_290800_COR-2607290800-dsw--0-ia5 29-Jul-2026 16:51:45 3577
swis2-VHDL20_DWMP_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 1875
swis2-VHDL20_DWMP_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1798
swis2-VHDL20_DWMP_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:08 1798
swis2-VHDL20_DWMP_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2180
swis2-VHDL20_DWMP_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2188
swis2-VHDL20_DWPG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1293
swis2-VHDL20_DWPG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1542
swis2-VHDL20_DWPG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1718
swis2-VHDL20_DWPG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2313
swis2-VHDL20_DWPG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2133
swis2-VHDL20_DWPG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:16 2130
swis2-VHDL20_DWPG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2476
swis2-VHDL20_DWPG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2223
swis2-VHDL20_DWPH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1534
swis2-VHDL20_DWPH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1609
swis2-VHDL20_DWPH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1786
swis2-VHDL20_DWPH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2147
swis2-VHDL20_DWPH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2083
swis2-VHDL20_DWPH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 2085
swis2-VHDL20_DWPH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2431
swis2-VHDL20_DWPH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 1803
swis2-VHDL20_DWSG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:01 1216
swis2-VHDL20_DWSG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1237
swis2-VHDL20_DWSG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1594
swis2-VHDL20_DWSG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:01 1845
swis2-VHDL20_DWSG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1543
swis2-VHDL20_DWSG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 1596
swis2-VHDL20_DWSG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 1850
swis2-VHDL20_DWSG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:01 1437
wst04-VHDL20_DWEG_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:20 241956
wst04-VHDL20_DWEG_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:16 241796
wst04-VHDL20_DWEG_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:12 242729
wst04-VHDL20_DWEG_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 245514
wst04-VHDL20_DWEG_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 244413
wst04-VHDL20_DWEG_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:12 244286
wst04-VHDL20_DWEG_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 246152
wst04-VHDL20_DWEG_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 248717
wst04-VHDL20_DWEH_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:20 240990
wst04-VHDL20_DWEH_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:22 241093
wst04-VHDL20_DWEH_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:12 241898
wst04-VHDL20_DWEH_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 242654
wst04-VHDL20_DWEH_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 242248
wst04-VHDL20_DWEH_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:12 242247
wst04-VHDL20_DWEH_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 243818
wst04-VHDL20_DWEH_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 242670
wst04-VHDL20_DWEI_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:26 349863
wst04-VHDL20_DWEI_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:16 349646
wst04-VHDL20_DWEI_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:16 350066
wst04-VHDL20_DWEI_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 350770
wst04-VHDL20_DWEI_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 350270
wst04-VHDL20_DWEI_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:18 350070
wst04-VHDL20_DWEI_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 351313
wst04-VHDL20_DWEI_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 360153
wst04-VHDL20_DWHG_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:45:20 351026
wst04-VHDL20_DWHG_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:22 350791
wst04-VHDL20_DWHG_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:45:13 353304
wst04-VHDL20_DWHG_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:45:13 358084
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wst04-VHDL20_DWMP_290800_COR-2607290800-omedes-..> 29-Jul-2026 16:51:56 603209
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