Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Sep-2026 12:47:13 5662
FPDL13_DWMZ_260600 26-Sep-2026 11:09:25 3984
SXDL31_DWAV_241800 24-Sep-2026 16:46:37 3715
SXDL31_DWAV_250800 25-Sep-2026 07:58:56 8834
SXDL31_DWAV_251800 25-Sep-2026 16:50:23 4327
SXDL31_DWAV_260800 26-Sep-2026 07:28:08 6036
SXDL31_DWAV_LATEST 26-Sep-2026 07:28:08 6036
SXDL33_DWAV_250000 25-Sep-2026 08:28:24 8042
SXDL33_DWAV_260000 26-Sep-2026 09:26:48 7722
SXDL33_DWAV_LATEST 26-Sep-2026 09:26:48 7722
ber01-FWDL39_DWMS_251200-2609251200-dsw--0-ia5 25-Sep-2026 11:02:14 1247
ber01-FWDL39_DWMS_261200-2609261200-dsw--0-ia5 26-Sep-2026 11:01:18 1246
ber01-VHDL13_DWEG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:28:18 2658
ber01-VHDL13_DWEG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:28:18 2607
ber01-VHDL13_DWEH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:28:18 2852
ber01-VHDL13_DWEH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:28:18 2809
ber01-VHDL13_DWEI_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:28:18 2589
ber01-VHDL13_DWEI_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:28:12 2547
ber01-VHDL13_DWHG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:16 2716
ber01-VHDL13_DWHG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:15 2825
ber01-VHDL13_DWHH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:16 2633
ber01-VHDL13_DWHH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:15 2803
ber01-VHDL13_DWLG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 2511
ber01-VHDL13_DWLG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2476
ber01-VHDL13_DWLH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 2599
ber01-VHDL13_DWLH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2438
ber01-VHDL13_DWLI_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 2365
ber01-VHDL13_DWLI_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2135
ber01-VHDL13_DWMO_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 2966
ber01-VHDL13_DWMO_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2642
ber01-VHDL13_DWMP_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 2751
ber01-VHDL13_DWMP_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2368
ber01-VHDL13_DWOG_241700-2609241700-dsw--0-ia5 24-Sep-2026 18:00:06 2857
ber01-VHDL13_DWOG_250300-2609250300-dsw--0-ia5 25-Sep-2026 03:00:27 3215
ber01-VHDL13_DWOG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 3215
ber01-VHDL13_DWOG_251700-2609251700-dsw--0-ia5 25-Sep-2026 18:00:03 2869
ber01-VHDL13_DWOG_260300-2609260300-dsw--0-ia5 26-Sep-2026 03:00:46 2851
ber01-VHDL13_DWOG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2988
ber01-VHDL13_DWON_241456-2609241456-dsw--0-ia5 24-Sep-2026 14:58:02 3755
ber01-VHDL13_DWON_241654-2609241654-dsw--0-ia5 24-Sep-2026 16:54:48 3122
ber01-VHDL13_DWON_242030-2609242030-dsw--0-ia5 24-Sep-2026 20:30:44 3118
ber01-VHDL13_DWON_250119-2609250119-dsw--0-ia5 25-Sep-2026 01:19:28 3043
ber01-VHDL13_DWON_250238-2609250238-dsw--0-ia5 25-Sep-2026 02:40:34 3296
ber01-VHDL13_DWON_250529-2609250529-dsw--0-ia5 25-Sep-2026 05:29:29 3136
ber01-VHDL13_DWON_250535-2609250535-dsw--0-ia5 25-Sep-2026 05:35:13 3173
ber01-VHDL13_DWON_250811-2609250811-dsw--0-ia5 25-Sep-2026 08:11:39 3173
ber01-VHDL13_DWON_251446-2609251446-dsw--0-ia5 25-Sep-2026 14:46:33 3122
ber01-VHDL13_DWON_251451-2609251451-dsw--0-ia5 25-Sep-2026 14:52:01 3397
ber01-VHDL13_DWON_251732-2609251732-dsw--0-ia5 25-Sep-2026 17:33:08 2841
ber01-VHDL13_DWON_260120-2609260120-dsw--0-ia5 26-Sep-2026 01:20:09 3159
ber01-VHDL13_DWON_260245-2609260245-dsw--0-ia5 26-Sep-2026 02:47:03 3159
ber01-VHDL13_DWON_260446-2609260446-dsw--0-ia5 26-Sep-2026 04:46:35 3450
ber01-VHDL13_DWON_260535-2609260535-dsw--0-ia5 26-Sep-2026 05:35:50 3450
ber01-VHDL13_DWON_261212-2609261212-dsw--0-ia5 26-Sep-2026 12:13:03 3450
ber01-VHDL13_DWPG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 2708
ber01-VHDL13_DWPG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 2683
ber01-VHDL13_DWPH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:04 2666
ber01-VHDL13_DWPH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:15 2564
ber01-VHDL13_DWSG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 2170
ber01-VHDL13_DWSG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:15 2275
ber01-VHDL17_DWOG_251200-2609251200-dsw--0-ia5 25-Sep-2026 09:16:08 3149
ber01-VHDL17_DWOG_261200-2609261200-dsw--0-ia5 26-Sep-2026 11:32:16 3008
swis2-VHDL20_DWEG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1113
swis2-VHDL20_DWEG_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:04 980
swis2-VHDL20_DWEG_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:01:22 942
swis2-VHDL20_DWEG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 1193
swis2-VHDL20_DWEG_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:05 1160
swis2-VHDL20_DWEG_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:18 889
swis2-VHDL20_DWEG_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:01:18 940
swis2-VHDL20_DWEG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 1097
swis2-VHDL20_DWEH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1128
swis2-VHDL20_DWEH_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:04 961
swis2-VHDL20_DWEH_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:01:22 959
swis2-VHDL20_DWEH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 1189
swis2-VHDL20_DWEH_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:05 1312
swis2-VHDL20_DWEH_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:18 904
swis2-VHDL20_DWEH_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:01:18 818
swis2-VHDL20_DWEH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 983
swis2-VHDL20_DWEI_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 967
swis2-VHDL20_DWEI_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:04 828
swis2-VHDL20_DWEI_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:01:22 777
swis2-VHDL20_DWEI_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 1059
swis2-VHDL20_DWEI_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:05 1026
swis2-VHDL20_DWEI_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:18 771
swis2-VHDL20_DWEI_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:01:18 822
swis2-VHDL20_DWEI_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 961
swis2-VHDL20_DWHG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:45:22 1262
swis2-VHDL20_DWHG_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:06 1162
swis2-VHDL20_DWHG_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:47:34 1141
swis2-VHDL20_DWHG_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:18 1138
swis2-VHDL20_DWHG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:45:21 1075
swis2-VHDL20_DWHG_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:45:11 1194
swis2-VHDL20_DWHG_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:47:08 1096
swis2-VHDL20_DWHG_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:14 1093
swis2-VHDL20_DWHG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:45:51 1178
swis2-VHDL20_DWHH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:45:22 1116
swis2-VHDL20_DWHH_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:29 1011
swis2-VHDL20_DWHH_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:47:34 972
swis2-VHDL20_DWHH_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:18 972
swis2-VHDL20_DWHH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:45:21 1085
swis2-VHDL20_DWHH_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:45:11 1321
swis2-VHDL20_DWHH_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:47:08 1220
swis2-VHDL20_DWHH_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:14 1220
swis2-VHDL20_DWHH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:45:51 1213
swis2-VHDL20_DWLG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1032
swis2-VHDL20_DWLG_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:35 871
swis2-VHDL20_DWLG_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:14 921
swis2-VHDL20_DWLG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:26 996
swis2-VHDL20_DWLG_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:31:04 997
swis2-VHDL20_DWLG_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:43 894
swis2-VHDL20_DWLG_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:18 870
swis2-VHDL20_DWLG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:37 962
swis2-VHDL20_DWLH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 972
swis2-VHDL20_DWLH_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:35 878
swis2-VHDL20_DWLH_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:14 901
swis2-VHDL20_DWLH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:26 976
swis2-VHDL20_DWLH_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:31:04 978
swis2-VHDL20_DWLH_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:43 872
swis2-VHDL20_DWLH_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:18 879
swis2-VHDL20_DWLH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:37 971
swis2-VHDL20_DWLI_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 969
swis2-VHDL20_DWLI_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:35 967
swis2-VHDL20_DWLI_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:14 941
swis2-VHDL20_DWLI_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:26 995
swis2-VHDL20_DWLI_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:31:04 987
swis2-VHDL20_DWLI_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:43 885
swis2-VHDL20_DWLI_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:18 849
swis2-VHDL20_DWLI_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:37 940
swis2-VHDL20_DWMO_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1211
swis2-VHDL20_DWMO_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:02 1101
swis2-VHDL20_DWMO_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:04 1124
swis2-VHDL20_DWMO_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 1276
swis2-VHDL20_DWMO_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:09 1323
swis2-VHDL20_DWMO_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:03 1134
swis2-VHDL20_DWMO_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:04 893
swis2-VHDL20_DWMO_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 1050
swis2-VHDL20_DWMP_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1254
swis2-VHDL20_DWMP_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:02 1070
swis2-VHDL20_DWMP_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:04 1098
swis2-VHDL20_DWMP_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 1320
swis2-VHDL20_DWMP_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:09 1321
swis2-VHDL20_DWMP_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:03 1132
swis2-VHDL20_DWMP_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:04 890
swis2-VHDL20_DWMP_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:12 1041
swis2-VHDL20_DWPG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1046
swis2-VHDL20_DWPG_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:35 905
swis2-VHDL20_DWPG_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:14 921
swis2-VHDL20_DWPG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:26 1019
swis2-VHDL20_DWPG_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:31:04 989
swis2-VHDL20_DWPG_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:43 879
swis2-VHDL20_DWPG_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:18 926
swis2-VHDL20_DWPG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:37 1017
swis2-VHDL20_DWPH_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:31:14 1048
swis2-VHDL20_DWPH_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:35 792
swis2-VHDL20_DWPH_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:14 943
swis2-VHDL20_DWPH_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:26 1042
swis2-VHDL20_DWPH_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:31:04 1018
swis2-VHDL20_DWPH_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:43 915
swis2-VHDL20_DWPH_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:18 921
swis2-VHDL20_DWPH_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:37 1013
swis2-VHDL20_DWSG_241800-2609241800-dsw--0-ia5 24-Sep-2026 18:30:04 1053
swis2-VHDL20_DWSG_250200-2609250200-dsw--0-ia5 25-Sep-2026 02:30:04 1028
swis2-VHDL20_DWSG_250400-2609250400-dsw--0-ia5 25-Sep-2026 05:00:20 869
swis2-VHDL20_DWSG_250800-2609250800-dsw--0-ia5 25-Sep-2026 08:30:06 930
swis2-VHDL20_DWSG_251800-2609251800-dsw--0-ia5 25-Sep-2026 18:30:09 1015
swis2-VHDL20_DWSG_260200-2609260200-dsw--0-ia5 26-Sep-2026 02:30:18 875
swis2-VHDL20_DWSG_260400-2609260400-dsw--0-ia5 26-Sep-2026 05:00:14 851
swis2-VHDL20_DWSG_260800-2609260800-dsw--0-ia5 26-Sep-2026 08:30:15 943
wst04-VHDL20_DWEG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 242333
wst04-VHDL20_DWEG_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:14 241400
wst04-VHDL20_DWEG_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:14 241019
wst04-VHDL20_DWEG_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 241929
wst04-VHDL20_DWEG_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 242132
wst04-VHDL20_DWEG_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 241167
wst04-VHDL20_DWEG_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:14 241187
wst04-VHDL20_DWEG_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:15 241899
wst04-VHDL20_DWEH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 235220
wst04-VHDL20_DWEH_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:14 234546
wst04-VHDL20_DWEH_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:14 234472
wst04-VHDL20_DWEH_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 235272
wst04-VHDL20_DWEH_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 235129
wst04-VHDL20_DWEH_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 234347
wst04-VHDL20_DWEH_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:14 233669
wst04-VHDL20_DWEH_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:15 234440
wst04-VHDL20_DWEI_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 346768
wst04-VHDL20_DWEI_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:14 346446
wst04-VHDL20_DWEI_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:20 346173
wst04-VHDL20_DWEI_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 346995
wst04-VHDL20_DWEI_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 347134
wst04-VHDL20_DWEI_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 346406
wst04-VHDL20_DWEI_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:18 346430
wst04-VHDL20_DWEI_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:15 346602
wst04-VHDL20_DWHG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:45:22 347754
wst04-VHDL20_DWHG_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:47:34 347802
wst04-VHDL20_DWHG_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:18 347582
wst04-VHDL20_DWHG_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:45:21 347763
wst04-VHDL20_DWHG_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:45:13 347693
wst04-VHDL20_DWHG_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:47:08 347406
wst04-VHDL20_DWHG_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:18 347190
wst04-VHDL20_DWHG_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:45:51 347985
wst04-VHDL20_DWHH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:45:22 332929
wst04-VHDL20_DWHH_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:47:34 333134
wst04-VHDL20_DWHH_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:18 228990
wst04-VHDL20_DWHH_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:45:21 332906
wst04-VHDL20_DWHH_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:45:13 334263
wst04-VHDL20_DWHH_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:47:08 334100
wst04-VHDL20_DWHH_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:18 230031
wst04-VHDL20_DWHH_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:45:51 333218
wst04-VHDL20_DWLG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 333054
wst04-VHDL20_DWLG_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:35 333583
wst04-VHDL20_DWLG_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:44 333166
wst04-VHDL20_DWLG_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:54 333223
wst04-VHDL20_DWLG_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:31:34 333686
wst04-VHDL20_DWLG_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:43 333567
wst04-VHDL20_DWLG_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:44 333106
wst04-VHDL20_DWLG_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:58 333147
wst04-VHDL20_DWLH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 337005
wst04-VHDL20_DWLH_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:35 337606
wst04-VHDL20_DWLH_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:44 337204
wst04-VHDL20_DWLH_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:54 337247
wst04-VHDL20_DWLH_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:31:47 337688
wst04-VHDL20_DWLH_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:43 337574
wst04-VHDL20_DWLH_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:44 337149
wst04-VHDL20_DWLH_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:58 337196
wst04-VHDL20_DWLI_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 338031
wst04-VHDL20_DWLI_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:35 338795
wst04-VHDL20_DWLI_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:44 338288
wst04-VHDL20_DWLI_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:54 382924
wst04-VHDL20_DWLI_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:31:34 338781
wst04-VHDL20_DWLI_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:43 338667
wst04-VHDL20_DWLI_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:44 338138
wst04-VHDL20_DWLI_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:58 382810
wst04-VHDL20_DWMO_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 354194
wst04-VHDL20_DWMO_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:24 455872
wst04-VHDL20_DWMO_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:14 455831
wst04-VHDL20_DWMO_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 455864
wst04-VHDL20_DWMO_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 354446
wst04-VHDL20_DWMO_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 455677
wst04-VHDL20_DWMO_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:14 454482
wst04-VHDL20_DWMO_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:37 454556
wst04-VHDL20_DWMP_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 461094
wst04-VHDL20_DWMP_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:24 562232
wst04-VHDL20_DWMP_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:18 562245
wst04-VHDL20_DWMP_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 461126
wst04-VHDL20_DWMP_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 461379
wst04-VHDL20_DWMP_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 562069
wst04-VHDL20_DWMP_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:18 560918
wst04-VHDL20_DWMP_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:37 459767
wst04-VHDL20_DWPG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:28 347451
wst04-VHDL20_DWPG_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:35 244427
wst04-VHDL20_DWPG_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:34 347664
wst04-VHDL20_DWPG_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:54 392265
wst04-VHDL20_DWPG_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:31:34 348138
wst04-VHDL20_DWPG_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:43 244434
wst04-VHDL20_DWPG_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:32 347667
wst04-VHDL20_DWPG_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:58 392254
wst04-VHDL20_DWPH_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:31:24 242383
wst04-VHDL20_DWPH_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:35 242692
wst04-VHDL20_DWPH_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:34 242558
wst04-VHDL20_DWPH_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:54 242554
wst04-VHDL20_DWPH_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:31:34 243025
wst04-VHDL20_DWPH_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:43 242921
wst04-VHDL20_DWPH_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:32 242553
wst04-VHDL20_DWPH_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:58 242529
wst04-VHDL20_DWSG_241800-2609241800-omedes--0.pdf 24-Sep-2026 18:30:25 347685
wst04-VHDL20_DWSG_250200-2609250200-omedes--0.pdf 25-Sep-2026 02:30:12 347591
wst04-VHDL20_DWSG_250400-2609250400-omedes--0.pdf 25-Sep-2026 05:00:14 346350
wst04-VHDL20_DWSG_250800-2609250800-omedes--0.pdf 25-Sep-2026 08:30:26 346364
wst04-VHDL20_DWSG_251800-2609251800-omedes--0.pdf 25-Sep-2026 18:30:25 346968
wst04-VHDL20_DWSG_260200-2609260200-omedes--0.pdf 26-Sep-2026 02:30:20 346606
wst04-VHDL20_DWSG_260400-2609260400-omedes--0.pdf 26-Sep-2026 05:00:14 346421
wst04-VHDL20_DWSG_260800-2609260800-omedes--0.pdf 26-Sep-2026 08:30:37 346427