Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Feb-2026 13:50:19 5407
FPDL13_DWMZ_200600 20-Feb-2026 15:22:29 4946
SXDL31_DWAV_190800 19-Feb-2026 08:52:00 9845
SXDL31_DWAV_191800 19-Feb-2026 17:49:39 7976
SXDL31_DWAV_200800 20-Feb-2026 07:58:39 8639
SXDL31_DWAV_201800 20-Feb-2026 16:18:05 9647
SXDL31_DWAV_LATEST 20-Feb-2026 16:18:05 9647
SXDL33_DWAV_190000 19-Feb-2026 10:40:09 12645
SXDL33_DWAV_200000 20-Feb-2026 11:03:09 8185
SXDL33_DWAV_LATEST 20-Feb-2026 11:03:09 8185
ber01-FWDL39_DWMS_191230-2602191230-dsw--0-ia5 19-Feb-2026 10:54:21 2024
ber01-FWDL39_DWMS_201230-2602201230-dsw--0-ia5 20-Feb-2026 13:26:07 1825
ber01-FWDL39_DWMS_201230_COR-2602201230-dsw--0-ia5 20-Feb-2026 14:10:21 1829
ber01-VHDL13_DWEH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:28:12 3479
ber01-VHDL13_DWEH_190400-2602190400-dsw--0-ia5 19-Feb-2026 05:58:17 4106
ber01-VHDL13_DWEH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:28:16 4217
ber01-VHDL13_DWEH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:17 3033
ber01-VHDL13_DWEH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:12 3647
ber01-VHDL13_DWEH_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:12 3911
ber01-VHDL13_DWEH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:16 3772
ber01-VHDL13_DWEH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:16 2995
ber01-VHDL13_DWHG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:08 3057
ber01-VHDL13_DWHG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:06 3057
ber01-VHDL13_DWHG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3769
ber01-VHDL13_DWHG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 3493
ber01-VHDL13_DWHG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:13 3567
ber01-VHDL13_DWHG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3578
ber01-VHDL13_DWHG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 3578
ber01-VHDL13_DWHG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 09:40:07 3918
ber01-VHDL13_DWHG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3095
ber01-VHDL13_DWHH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:08 2804
ber01-VHDL13_DWHH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:06 2804
ber01-VHDL13_DWHH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3519
ber01-VHDL13_DWHH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 3514
ber01-VHDL13_DWHH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:13 3662
ber01-VHDL13_DWHH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3696
ber01-VHDL13_DWHH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 3696
ber01-VHDL13_DWHH_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 09:42:07 3475
ber01-VHDL13_DWHH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2597
ber01-VHDL13_DWLG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 3271
ber01-VHDL13_DWLG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 3485
ber01-VHDL13_DWLG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3524
ber01-VHDL13_DWLG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2843
ber01-VHDL13_DWLG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3082
ber01-VHDL13_DWLG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3226
ber01-VHDL13_DWLG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3365
ber01-VHDL13_DWLG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3234
ber01-VHDL13_DWLH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 3070
ber01-VHDL13_DWLH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 3088
ber01-VHDL13_DWLH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3112
ber01-VHDL13_DWLH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2788
ber01-VHDL13_DWLH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2973
ber01-VHDL13_DWLH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 2912
ber01-VHDL13_DWLH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3136
ber01-VHDL13_DWLH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2978
ber01-VHDL13_DWLI_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 3280
ber01-VHDL13_DWLI_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 3404
ber01-VHDL13_DWLI_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3647
ber01-VHDL13_DWLI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2727
ber01-VHDL13_DWLI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2725
ber01-VHDL13_DWLI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 2781
ber01-VHDL13_DWLI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 2998
ber01-VHDL13_DWLI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2986
ber01-VHDL13_DWMG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 4350
ber01-VHDL13_DWMG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 4389
ber01-VHDL13_DWMG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:03 4063
ber01-VHDL13_DWMG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:38:33 3863
ber01-VHDL13_DWMG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3930
ber01-VHDL13_DWMG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3208
ber01-VHDL13_DWMG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3463
ber01-VHDL13_DWMG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3752
ber01-VHDL13_DWMG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3695
ber01-VHDL13_DWMO_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 4064
ber01-VHDL13_DWMO_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 4036
ber01-VHDL13_DWMO_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:03 3567
ber01-VHDL13_DWMO_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3112
ber01-VHDL13_DWMO_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3247
ber01-VHDL13_DWMO_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3463
ber01-VHDL13_DWMO_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3850
ber01-VHDL13_DWMO_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3223
ber01-VHDL13_DWMP_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 4304
ber01-VHDL13_DWMP_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 4320
ber01-VHDL13_DWMP_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:03 3377
ber01-VHDL13_DWMP_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:40:32 3038
ber01-VHDL13_DWMP_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 3256
ber01-VHDL13_DWMP_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3269
ber01-VHDL13_DWMP_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:57 3524
ber01-VHDL13_DWMP_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3860
ber01-VHDL13_DWMP_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3309
ber01-VHDL13_DWOG_190300-2602190300-dsw--0-ia5 19-Feb-2026 04:00:02 7134
ber01-VHDL13_DWOG_190800-2602190800-dsw--0-ia5 19-Feb-2026 18:20:01 5122
ber01-VHDL13_DWOG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 15:36:06 5147
ber01-VHDL13_DWOG_191700-2602191700-dsw--0-ia5 19-Feb-2026 19:00:03 5122
ber01-VHDL13_DWOG_200300-2602200300-dsw--0-ia5 20-Feb-2026 04:00:06 5756
ber01-VHDL13_DWOG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 5163
ber01-VHDL13_DWOG_201700-2602201700-dsw--0-ia5 20-Feb-2026 19:00:06 5044
ber01-VHDL13_DWOH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:28:12 3184
ber01-VHDL13_DWOH_190400-2602190400-dsw--0-ia5 19-Feb-2026 05:58:11 3723
ber01-VHDL13_DWOH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:28:16 3879
ber01-VHDL13_DWOH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:17 2911
ber01-VHDL13_DWOH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:12 3509
ber01-VHDL13_DWOH_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:16 3535
ber01-VHDL13_DWOH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:16 3676
ber01-VHDL13_DWOH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:16 3071
ber01-VHDL13_DWOI_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:28:16 3000
ber01-VHDL13_DWOI_190400-2602190400-dsw--0-ia5 19-Feb-2026 05:58:17 3888
ber01-VHDL13_DWOI_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:28:12 3846
ber01-VHDL13_DWOI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:28:11 2704
ber01-VHDL13_DWOI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:28:17 3069
ber01-VHDL13_DWOI_200400-2602200400-dsw--0-ia5 20-Feb-2026 05:58:16 3156
ber01-VHDL13_DWOI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:28:12 3419
ber01-VHDL13_DWOI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:28:12 2809
ber01-VHDL13_DWON_182207-2602182207-dsw--0-ia5 18-Feb-2026 22:07:26 4258
ber01-VHDL13_DWON_190003-2602190003-dsw--0-ia5 19-Feb-2026 00:03:32 4887
ber01-VHDL13_DWON_190141-2602190141-dsw--0-ia5 19-Feb-2026 01:41:27 4853
ber01-VHDL13_DWON_190356-2602190356-dsw--0-ia5 19-Feb-2026 03:56:57 4986
ber01-VHDL13_DWON_190624-2602190624-dsw--0-ia5 19-Feb-2026 06:25:01 4232
ber01-VHDL13_DWON_190925-2602190925-dsw--0-ia5 19-Feb-2026 09:25:31 4260
ber01-VHDL13_DWON_191016-2602191016-dsw--0-ia5 19-Feb-2026 10:16:07 4313
ber01-VHDL13_DWON_191527-2602191527-dsw--0-ia5 19-Feb-2026 15:27:22 3831
ber01-VHDL13_DWON_191819-2602191819-dsw--0-ia5 19-Feb-2026 18:19:37 3746
ber01-VHDL13_DWON_191936-2602191936-dsw--0-ia5 19-Feb-2026 19:36:33 3896
ber01-VHDL13_DWON_192238-2602192238-dsw--0-ia5 19-Feb-2026 22:38:12 3867
ber01-VHDL13_DWON_200004-2602200004-dsw--0-ia5 20-Feb-2026 00:04:26 4405
ber01-VHDL13_DWON_200144-2602200144-dsw--0-ia5 20-Feb-2026 01:44:32 4242
ber01-VHDL13_DWON_200342-2602200342-dsw--0-ia5 20-Feb-2026 03:42:47 4151
ber01-VHDL13_DWON_200628-2602200628-dsw--0-ia5 20-Feb-2026 06:28:36 4416
ber01-VHDL13_DWON_200728-2602200728-dsw--0-ia5 20-Feb-2026 07:28:47 4495
ber01-VHDL13_DWON_200808-2602200808-dsw--0-ia5 20-Feb-2026 08:08:10 4482
ber01-VHDL13_DWON_200924-2602200924-dsw--0-ia5 20-Feb-2026 09:24:32 4078
ber01-VHDL13_DWON_201256-2602201256-dsw--0-ia5 20-Feb-2026 12:56:51 3996
ber01-VHDL13_DWON_201553-2602201553-dsw--0-ia5 20-Feb-2026 15:54:02 3523
ber01-VHDL13_DWON_201752-2602201752-dsw--0-ia5 20-Feb-2026 17:52:17 3625
ber01-VHDL13_DWPG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 2479
ber01-VHDL13_DWPG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 2569
ber01-VHDL13_DWPG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 2857
ber01-VHDL13_DWPG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2632
ber01-VHDL13_DWPG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2937
ber01-VHDL13_DWPG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3043
ber01-VHDL13_DWPG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3154
ber01-VHDL13_DWPG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 2675
ber01-VHDL13_DWPG_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:08:30 2612
ber01-VHDL13_DWPH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 2815
ber01-VHDL13_DWPH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:01 2941
ber01-VHDL13_DWPH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:11 3196
ber01-VHDL13_DWPH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:06 2987
ber01-VHDL13_DWPH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 3242
ber01-VHDL13_DWPH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:01 3503
ber01-VHDL13_DWPH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:01 3556
ber01-VHDL13_DWPH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:09 3106
ber01-VHDL13_DWPH_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:08:51 3059
ber01-VHDL13_DWSG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:30:04 3741
ber01-VHDL13_DWSG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:06 3527
ber01-VHDL13_DWSG_190400_COR-2602190400-dsw--0-ia5 19-Feb-2026 06:29:11 2689
ber01-VHDL13_DWSG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:30:03 2512
ber01-VHDL13_DWSG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 10:47:47 2598
ber01-VHDL13_DWSG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:30:02 2301
ber01-VHDL13_DWSG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:30:12 2792
ber01-VHDL13_DWSG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 2805
ber01-VHDL13_DWSG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:30:13 2558
ber01-VHDL13_DWSG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 12:05:37 3105
ber01-VHDL13_DWSG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:30:03 3238
ber01-VHDL17_DWOG_191200-2602191200-dsw--0-ia5 19-Feb-2026 12:37:48 3331
ber01-VHDL17_DWOG_201200-2602201200-dsw--0-ia5 20-Feb-2026 11:25:57 3456
swis2-VHDL20_DWEG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 3751
swis2-VHDL20_DWEG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:07 4124
swis2-VHDL20_DWEG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4598
swis2-VHDL20_DWEG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3318
swis2-VHDL20_DWEG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3866
swis2-VHDL20_DWEG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4018
swis2-VHDL20_DWEG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4317
swis2-VHDL20_DWEG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3560
swis2-VHDL20_DWEH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 4014
swis2-VHDL20_DWEH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:07 4536
swis2-VHDL20_DWEH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4816
swis2-VHDL20_DWEH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3482
swis2-VHDL20_DWEH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 4063
swis2-VHDL20_DWEH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4250
swis2-VHDL20_DWEH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4279
swis2-VHDL20_DWEH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3353
swis2-VHDL20_DWEI_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 3392
swis2-VHDL20_DWEI_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:07 4336
swis2-VHDL20_DWEI_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4469
swis2-VHDL20_DWEI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3152
swis2-VHDL20_DWEI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3458
swis2-VHDL20_DWEI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3511
swis2-VHDL20_DWEI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 3948
swis2-VHDL20_DWEI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3164
swis2-VHDL20_DWHG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 3243
swis2-VHDL20_DWHG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:06 3240
swis2-VHDL20_DWHG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4341
swis2-VHDL20_DWHG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3676
swis2-VHDL20_DWHG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3753
swis2-VHDL20_DWHG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3761
swis2-VHDL20_DWHG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4489
swis2-VHDL20_DWHG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3278
swis2-VHDL20_DWHH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 2990
swis2-VHDL20_DWHH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:06 2990
swis2-VHDL20_DWHH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4201
swis2-VHDL20_DWHH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3700
swis2-VHDL20_DWHH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3848
swis2-VHDL20_DWHH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:07 3882
swis2-VHDL20_DWHH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:06 4121
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swis2-VHDL20_DWLG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 3673
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swis2-VHDL20_DWLG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3770
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swis2-VHDL20_DWLH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 3486
swis2-VHDL20_DWLH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:12 3450
swis2-VHDL20_DWLH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 3795
swis2-VHDL20_DWLH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3150
swis2-VHDL20_DWLH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3335
swis2-VHDL20_DWLH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3404
swis2-VHDL20_DWLH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3778
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swis2-VHDL20_DWLI_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 3759
swis2-VHDL20_DWLI_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:12 3761
swis2-VHDL20_DWLI_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4379
swis2-VHDL20_DWLI_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3084
swis2-VHDL20_DWLI_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3160
swis2-VHDL20_DWLI_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3328
swis2-VHDL20_DWLI_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3690
swis2-VHDL20_DWLI_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3505
swis2-VHDL20_DWMG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 4853
swis2-VHDL20_DWMG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:01 4840
swis2-VHDL20_DWMG_190400_COR-2602190400-dsw--0-ia5 20-Feb-2026 06:13:42 4844
swis2-VHDL20_DWMG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4831
swis2-VHDL20_DWMG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:38:33 4631
swis2-VHDL20_DWMG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 4421
swis2-VHDL20_DWMG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3678
swis2-VHDL20_DWMG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3979
swis2-VHDL20_DWMG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4523
swis2-VHDL20_DWMG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 4287
swis2-VHDL20_DWMO_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 4526
swis2-VHDL20_DWMO_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:01 4474
swis2-VHDL20_DWMO_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4177
swis2-VHDL20_DWMO_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3614
swis2-VHDL20_DWMO_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3715
swis2-VHDL20_DWMO_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4005
swis2-VHDL20_DWMO_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4566
swis2-VHDL20_DWMO_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3692
swis2-VHDL20_DWMP_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 4818
swis2-VHDL20_DWMP_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:01 4771
swis2-VHDL20_DWMP_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 4209
swis2-VHDL20_DWMP_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 13:40:32 3870
swis2-VHDL20_DWMP_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 3707
swis2-VHDL20_DWMP_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3742
swis2-VHDL20_DWMP_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 4023
swis2-VHDL20_DWMP_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4696
swis2-VHDL20_DWMP_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:07 3883
swis2-VHDL20_DWPG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 2862
swis2-VHDL20_DWPG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:12 2909
swis2-VHDL20_DWPG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 3607
swis2-VHDL20_DWPG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3391
swis2-VHDL20_DWPG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3280
swis2-VHDL20_DWPG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 3733
swis2-VHDL20_DWPG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4207
swis2-VHDL20_DWPG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3405
swis2-VHDL20_DWPG_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:09:51 3409
swis2-VHDL20_DWPH_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:01 3222
swis2-VHDL20_DWPH_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:00:12 3283
swis2-VHDL20_DWPH_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:02 3948
swis2-VHDL20_DWPH_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:07 3739
swis2-VHDL20_DWPH_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:06 3584
swis2-VHDL20_DWPH_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:00:11 4170
swis2-VHDL20_DWPH_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 4595
swis2-VHDL20_DWPH_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3975
swis2-VHDL20_DWPH_201800_COR-2602201800-dsw--0-ia5 20-Feb-2026 20:10:03 3979
swis2-VHDL20_DWSG_190200-2602190200-dsw--0-ia5 19-Feb-2026 03:45:07 4206
swis2-VHDL20_DWSG_190400-2602190400-dsw--0-ia5 19-Feb-2026 06:15:01 3983
swis2-VHDL20_DWSG_190400_COR-2602190400-dsw--0-ia5 19-Feb-2026 06:29:11 3121
swis2-VHDL20_DWSG_190800-2602190800-dsw--0-ia5 19-Feb-2026 09:45:06 3092
swis2-VHDL20_DWSG_190800_COR-2602190800-dsw--0-ia5 19-Feb-2026 10:47:47 3178
swis2-VHDL20_DWSG_191300-2602191300-dsw--0-ia5 19-Feb-2026 14:45:14 3073
swis2-VHDL20_DWSG_191800-2602191800-dsw--0-ia5 19-Feb-2026 19:45:03 2735
swis2-VHDL20_DWSG_200200-2602200200-dsw--0-ia5 20-Feb-2026 03:45:02 3293
swis2-VHDL20_DWSG_200400-2602200400-dsw--0-ia5 20-Feb-2026 06:15:01 3160
swis2-VHDL20_DWSG_200800-2602200800-dsw--0-ia5 20-Feb-2026 09:45:02 3060
swis2-VHDL20_DWSG_200800_COR-2602200800-dsw--0-ia5 20-Feb-2026 12:05:37 3607
swis2-VHDL20_DWSG_201300-2602201300-dsw--0-ia5 20-Feb-2026 14:45:02 3556
swis2-VHDL20_DWSG_201800-2602201800-dsw--0-ia5 20-Feb-2026 19:45:02 3598
wst04-VHDL20_DWEG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:17 237458
wst04-VHDL20_DWEG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:21 237127
wst04-VHDL20_DWEG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:11 239698
wst04-VHDL20_DWEG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:11 236236
wst04-VHDL20_DWEG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 238778
wst04-VHDL20_DWEG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 238369
wst04-VHDL20_DWEG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:12 243817
wst04-VHDL20_DWEG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:11 242450
wst04-VHDL20_DWEH_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:21 234352
wst04-VHDL20_DWEH_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:21 234030
wst04-VHDL20_DWEH_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:17 235852
wst04-VHDL20_DWEH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:11 232635
wst04-VHDL20_DWEH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 235303
wst04-VHDL20_DWEH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 234931
wst04-VHDL20_DWEH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:12 239022
wst04-VHDL20_DWEH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:11 237987
wst04-VHDL20_DWEI_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:21 335419
wst04-VHDL20_DWEI_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:27 336088
wst04-VHDL20_DWEI_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:17 336413
wst04-VHDL20_DWEI_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 334421
wst04-VHDL20_DWEI_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 334812
wst04-VHDL20_DWEI_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:27 334671
wst04-VHDL20_DWEI_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 341769
wst04-VHDL20_DWEI_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 340687
wst04-VHDL20_DWHG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:17 319392
wst04-VHDL20_DWHG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:12 319345
wst04-VHDL20_DWHG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:29 325111
wst04-VHDL20_DWHG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 323061
wst04-VHDL20_DWHG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:16 322597
wst04-VHDL20_DWHG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:11 322601
wst04-VHDL20_DWHG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 336712
wst04-VHDL20_DWHG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 335103
wst04-VHDL20_DWHH_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:17 312355
wst04-VHDL20_DWHH_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:12 312393
wst04-VHDL20_DWHH_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:29 318352
wst04-VHDL20_DWHH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 317345
wst04-VHDL20_DWHH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:16 317649
wst04-VHDL20_DWHH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:11 317581
wst04-VHDL20_DWHH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 326594
wst04-VHDL20_DWHH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 324385
wst04-VHDL20_DWLG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:27 315900
wst04-VHDL20_DWLG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:40 315897
wst04-VHDL20_DWLG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:36 314728
wst04-VHDL20_DWLG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 313062
wst04-VHDL20_DWLG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 313290
wst04-VHDL20_DWLG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 314225
wst04-VHDL20_DWLG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 322350
wst04-VHDL20_DWLG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 322933
wst04-VHDL20_DWLH_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:27 314614
wst04-VHDL20_DWLH_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:40 314286
wst04-VHDL20_DWLH_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:33 317263
wst04-VHDL20_DWLH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 316812
wst04-VHDL20_DWLH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 316415
wst04-VHDL20_DWLH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 316288
wst04-VHDL20_DWLH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 323994
wst04-VHDL20_DWLH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 325193
wst04-VHDL20_DWLI_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:21 316192
wst04-VHDL20_DWLI_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:40 316048
wst04-VHDL20_DWLI_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:33 324106
wst04-VHDL20_DWLI_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 322300
wst04-VHDL20_DWLI_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 322326
wst04-VHDL20_DWLI_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:41 323142
wst04-VHDL20_DWLI_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 327157
wst04-VHDL20_DWLI_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 327924
wst04-VHDL20_DWMG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:11 547009
wst04-VHDL20_DWMG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:17 546088
wst04-VHDL20_DWMG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:25 547748
wst04-VHDL20_DWMG_190800_COR-2602190800-omedes-..> 19-Feb-2026 13:38:43 547695
wst04-VHDL20_DWMG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 544105
wst04-VHDL20_DWMG_200200-2602200200-omedes--0.pdf 20-Feb-2026 06:03:07 544189
wst04-VHDL20_DWMG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:17 544886
wst04-VHDL20_DWMG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 553504
wst04-VHDL20_DWMG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 552533
wst04-VHDL20_DWMO_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:11 432061
wst04-VHDL20_DWMO_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:17 432415
wst04-VHDL20_DWMO_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:17 434656
wst04-VHDL20_DWMO_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 431610
wst04-VHDL20_DWMO_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:12 432171
wst04-VHDL20_DWMO_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:11 433326
wst04-VHDL20_DWMO_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:22 443482
wst04-VHDL20_DWMO_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 442834
wst04-VHDL20_DWMP_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:11 556640
wst04-VHDL20_DWMP_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:21 558986
wst04-VHDL20_DWMP_190400_COR-2602190400-omedes-..> 20-Feb-2026 06:10:27 558986
wst04-VHDL20_DWMP_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:21 561387
wst04-VHDL20_DWMP_190800_COR-2602190800-omedes-..> 19-Feb-2026 13:40:36 561092
wst04-VHDL20_DWMP_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:17 558891
wst04-VHDL20_DWMP_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:12 558591
wst04-VHDL20_DWMP_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:15:17 560541
wst04-VHDL20_DWMP_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:26 565816
wst04-VHDL20_DWMP_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:16 564157
wst04-VHDL20_DWPG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:27 317462
wst04-VHDL20_DWPG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:32 316875
wst04-VHDL20_DWPG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:33 370693
wst04-VHDL20_DWPG_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:27 326161
wst04-VHDL20_DWPG_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:26 325538
wst04-VHDL20_DWPG_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:31 325833
wst04-VHDL20_DWPG_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:36 378816
wst04-VHDL20_DWPG_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:26 334134
wst04-VHDL20_DWPG_201800_COR-2602201800-omedes-..> 20-Feb-2026 20:09:11 334135
wst04-VHDL20_DWPH_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:21 227220
wst04-VHDL20_DWPH_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:00:32 227285
wst04-VHDL20_DWPH_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:33 277501
wst04-VHDL20_DWPH_191800-2602191800-omedes--0.pdf 19-Feb-2026 19:45:21 277264
wst04-VHDL20_DWPH_200200-2602200200-omedes--0.pdf 20-Feb-2026 03:45:22 231562
wst04-VHDL20_DWPH_200400-2602200400-omedes--0.pdf 20-Feb-2026 06:00:31 233311
wst04-VHDL20_DWPH_200800-2602200800-omedes--0.pdf 20-Feb-2026 09:45:32 284456
wst04-VHDL20_DWPH_201800-2602201800-omedes--0.pdf 20-Feb-2026 19:45:22 284278
wst04-VHDL20_DWPH_201800_COR-2602201800-omedes-..> 20-Feb-2026 20:09:37 284671
wst04-VHDL20_DWSG_190200-2602190200-omedes--0.pdf 19-Feb-2026 03:45:17 336355
wst04-VHDL20_DWSG_190400-2602190400-omedes--0.pdf 19-Feb-2026 06:15:21 336914
wst04-VHDL20_DWSG_190400_COR-2602190400-omedes-..> 19-Feb-2026 06:29:16 335708
wst04-VHDL20_DWSG_190800-2602190800-omedes--0.pdf 19-Feb-2026 09:45:11 339821
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