Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Nov-2026 11:33:55 6933
FPDL13_DWMZ_140600 14-Nov-2026 11:08:13 5698
SXDL31_DWAV_130810 13-Nov-2026 08:57:19 12757
SXDL31_DWAV_131810 13-Nov-2026 15:16:05 7611
SXDL31_DWAV_140810 14-Nov-2026 08:18:09 17143
SXDL31_DWAV_141810 14-Nov-2026 17:19:35 12266
SXDL31_DWAV_LATEST 14-Nov-2026 17:19:35 12266
SXDL33_DWAV_130000 13-Nov-2026 11:03:44 10613
SXDL33_DWAV_140000 14-Nov-2026 11:28:16 11271
SXDL33_DWAV_LATEST 14-Nov-2026 11:28:16 11271
ber01-FWDL39_DWMS_131200-2611131200-dsw--0-ia5 13-Nov-2026 12:09:38 1476
ber01-FWDL39_DWMS_141200-2611141200-dsw--0-ia5 14-Nov-2026 12:05:18 1581
ber01-VHDL13_DWEG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:14 3486
ber01-VHDL13_DWEG_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:44 3595
ber01-VHDL13_DWEG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4645
ber01-VHDL13_DWEG_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4629
ber01-VHDL13_DWEH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:14 3786
ber01-VHDL13_DWEH_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:38 4032
ber01-VHDL13_DWEH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4680
ber01-VHDL13_DWEH_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4684
ber01-VHDL13_DWEI_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:14 3296
ber01-VHDL13_DWEI_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:38 3344
ber01-VHDL13_DWEI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:21 4424
ber01-VHDL13_DWEI_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:37:00 4394
ber01-VHDL13_DWHG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:10 4267
ber01-VHDL13_DWHG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3473
ber01-VHDL13_DWHH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:10 3953
ber01-VHDL13_DWHH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3442
ber01-VHDL13_DWLG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2833
ber01-VHDL13_DWLG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3601
ber01-VHDL13_DWLH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2689
ber01-VHDL13_DWLH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3044
ber01-VHDL13_DWLI_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2467
ber01-VHDL13_DWLI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3095
ber01-VHDL13_DWMO_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 3209
ber01-VHDL13_DWMO_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 3916
ber01-VHDL13_DWMP_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 3191
ber01-VHDL13_DWMP_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 3525
ber01-VHDL13_DWOG_130300-2611130300-dsw--0-ia5 13-Nov-2026 04:00:19 4203
ber01-VHDL13_DWOG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:08 4043
ber01-VHDL13_DWOG_131700-2611131700-dsw--0-ia5 13-Nov-2026 19:00:26 4157
ber01-VHDL13_DWOG_140300-2611140300-dsw--0-ia5 14-Nov-2026 04:00:25 4983
ber01-VHDL13_DWOG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 4424
ber01-VHDL13_DWOG_141700-2611141700-dsw--0-ia5 14-Nov-2026 19:00:08 4633
ber01-VHDL13_DWON_122152-2611122152-dsw--0-ia5 12-Nov-2026 21:52:12 3619
ber01-VHDL13_DWON_122153-2611122153-dsw--0-ia5 12-Nov-2026 21:53:28 3610
ber01-VHDL13_DWON_130017-2611130017-dsw--0-ia5 13-Nov-2026 00:17:58 3134
ber01-VHDL13_DWON_130204-2611130204-dsw--0-ia5 13-Nov-2026 02:04:45 3134
ber01-VHDL13_DWON_130622-2611130622-dsw--0-ia5 13-Nov-2026 06:22:18 3811
ber01-VHDL13_DWON_130906-2611130906-dsw--0-ia5 13-Nov-2026 09:06:55 3703
ber01-VHDL13_DWON_131419-2611131419-dsw--0-ia5 13-Nov-2026 14:19:15 3950
ber01-VHDL13_DWON_131758-2611131758-dsw--0-ia5 13-Nov-2026 17:58:38 3563
ber01-VHDL13_DWON_140314-2611140314-dsw--0-ia5 14-Nov-2026 03:14:52 4484
ber01-VHDL13_DWON_140557-2611140557-dsw--0-ia5 14-Nov-2026 05:58:04 4327
ber01-VHDL13_DWON_140657-2611140657-dsw--0-ia5 14-Nov-2026 06:57:43 4327
ber01-VHDL13_DWON_141253-2611141253-dsw--0-ia5 14-Nov-2026 12:54:01 3759
ber01-VHDL13_DWON_141309-2611141309-dsw--0-ia5 14-Nov-2026 13:09:34 3841
ber01-VHDL13_DWON_141819-2611141819-dsw--0-ia5 14-Nov-2026 18:19:38 3891
ber01-VHDL13_DWPG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2288
ber01-VHDL13_DWPG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2435
ber01-VHDL13_DWPH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 3326
ber01-VHDL13_DWPH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2934
ber01-VHDL13_DWSG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:28 3584
ber01-VHDL13_DWSG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:17 4375
ber01-VHDL17_DWOG_131200-2611131200-dsw--0-ia5 13-Nov-2026 12:04:21 2444
ber01-VHDL17_DWOG_141200-2611141200-dsw--0-ia5 14-Nov-2026 12:48:24 3029
swis2-VHDL20_DWEG_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 2155
swis2-VHDL20_DWEG_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 1982
swis2-VHDL20_DWEG_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:01:07 2090
swis2-VHDL20_DWEG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:08 2643
swis2-VHDL20_DWEG_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:38 2030
swis2-VHDL20_DWEG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2102
swis2-VHDL20_DWEG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 2075
swis2-VHDL20_DWEG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2993
swis2-VHDL20_DWEG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3792
swis2-VHDL20_DWEG_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:48:40 3856
swis2-VHDL20_DWEH_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 2381
swis2-VHDL20_DWEH_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 2352
swis2-VHDL20_DWEH_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:01:07 2255
swis2-VHDL20_DWEH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:08 2794
swis2-VHDL20_DWEH_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:36 2282
swis2-VHDL20_DWEH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2250
swis2-VHDL20_DWEH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1969
swis2-VHDL20_DWEH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2965
swis2-VHDL20_DWEH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3692
swis2-VHDL20_DWEH_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:48:59 3756
swis2-VHDL20_DWEI_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 2109
swis2-VHDL20_DWEI_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 2062
swis2-VHDL20_DWEI_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:01:07 2103
swis2-VHDL20_DWEI_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:08 2615
swis2-VHDL20_DWEI_130800_COR-2611130800-dsw--0-ia5 13-Nov-2026 09:36:38 1917
swis2-VHDL20_DWEI_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 2154
swis2-VHDL20_DWEI_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 2118
swis2-VHDL20_DWEI_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:58 2844
swis2-VHDL20_DWEI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 3630
swis2-VHDL20_DWEI_140800_COR-2611140800-dsw--0-ia5 14-Nov-2026 10:49:25 3665
swis2-VHDL20_DWHG_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:45:11 2789
swis2-VHDL20_DWHG_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 2278
swis2-VHDL20_DWHG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:10 3255
swis2-VHDL20_DWHG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:45:25 2994
swis2-VHDL20_DWHG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1956
swis2-VHDL20_DWHG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2579
swis2-VHDL20_DWHH_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:45:11 2510
swis2-VHDL20_DWHH_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:45:15 2158
swis2-VHDL20_DWHH_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 2281
swis2-VHDL20_DWHH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:10 2945
swis2-VHDL20_DWHH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:45:25 2675
swis2-VHDL20_DWHH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:45:11 1785
swis2-VHDL20_DWHH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1828
swis2-VHDL20_DWHH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:09 2481
swis2-VHDL20_DWLG_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:31:09 1982
swis2-VHDL20_DWLG_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:40 1551
swis2-VHDL20_DWLG_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 1248
swis2-VHDL20_DWLG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:24 1694
swis2-VHDL20_DWLG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1651
swis2-VHDL20_DWLG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1544
swis2-VHDL20_DWLG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1531
swis2-VHDL20_DWLG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 2043
swis2-VHDL20_DWLH_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:31:09 1651
swis2-VHDL20_DWLH_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:40 1491
swis2-VHDL20_DWLH_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 1353
swis2-VHDL20_DWLH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:24 1930
swis2-VHDL20_DWLH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1821
swis2-VHDL20_DWLH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1418
swis2-VHDL20_DWLH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1457
swis2-VHDL20_DWLH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 2124
swis2-VHDL20_DWLI_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:31:09 1321
swis2-VHDL20_DWLI_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:40 1353
swis2-VHDL20_DWLI_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 999
swis2-VHDL20_DWLI_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:24 1516
swis2-VHDL20_DWLI_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1758
swis2-VHDL20_DWLI_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1517
swis2-VHDL20_DWLI_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1385
swis2-VHDL20_DWLI_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1958
swis2-VHDL20_DWMO_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 1920
swis2-VHDL20_DWMO_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 1937
swis2-VHDL20_DWMO_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:04 1815
swis2-VHDL20_DWMO_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 1951
swis2-VHDL20_DWMO_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 1644
swis2-VHDL20_DWMO_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1920
swis2-VHDL20_DWMO_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:02 1903
swis2-VHDL20_DWMO_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2495
swis2-VHDL20_DWMP_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 2151
swis2-VHDL20_DWMP_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 2058
swis2-VHDL20_DWMP_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:04 1998
swis2-VHDL20_DWMP_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2056
swis2-VHDL20_DWMP_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:04 1716
swis2-VHDL20_DWMP_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:04 1976
swis2-VHDL20_DWMP_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:02 1971
swis2-VHDL20_DWMP_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2385
swis2-VHDL20_DWPG_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:31:09 1244
swis2-VHDL20_DWPG_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:40 1287
swis2-VHDL20_DWPG_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 1135
swis2-VHDL20_DWPG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:24 1345
swis2-VHDL20_DWPG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 996
swis2-VHDL20_DWPG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1253
swis2-VHDL20_DWPG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1093
swis2-VHDL20_DWPG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1392
swis2-VHDL20_DWPH_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:31:09 1646
swis2-VHDL20_DWPH_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:40 1612
swis2-VHDL20_DWPH_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:14 1658
swis2-VHDL20_DWPH_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:24 1901
swis2-VHDL20_DWPH_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:31:08 1527
swis2-VHDL20_DWPH_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:29 1459
swis2-VHDL20_DWPH_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:14 1152
swis2-VHDL20_DWPH_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:30 1691
swis2-VHDL20_DWSG_121800-2611121800-dsw--0-ia5 12-Nov-2026 19:30:05 1764
swis2-VHDL20_DWSG_130200-2611130200-dsw--0-ia5 13-Nov-2026 03:30:04 1577
swis2-VHDL20_DWSG_130400-2611130400-dsw--0-ia5 13-Nov-2026 06:00:08 1626
swis2-VHDL20_DWSG_130800-2611130800-dsw--0-ia5 13-Nov-2026 09:30:04 2047
swis2-VHDL20_DWSG_131800-2611131800-dsw--0-ia5 13-Nov-2026 19:30:08 2816
swis2-VHDL20_DWSG_140200-2611140200-dsw--0-ia5 14-Nov-2026 03:30:08 1956
swis2-VHDL20_DWSG_140400-2611140400-dsw--0-ia5 14-Nov-2026 06:00:08 2113
swis2-VHDL20_DWSG_140800-2611140800-dsw--0-ia5 14-Nov-2026 09:30:07 2804
wst04-VHDL20_DWEG_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:18 235933
wst04-VHDL20_DWEG_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 236481
wst04-VHDL20_DWEG_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:14 235799
wst04-VHDL20_DWEG_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:18 237603
wst04-VHDL20_DWEG_130800_COR-2611130800-omedes-..> 13-Nov-2026 09:36:44 237357
wst04-VHDL20_DWEG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 236414
wst04-VHDL20_DWEG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 236947
wst04-VHDL20_DWEG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 237491
wst04-VHDL20_DWEG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:21 240209
wst04-VHDL20_DWEG_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:05 243031
wst04-VHDL20_DWEH_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:18 233002
wst04-VHDL20_DWEH_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 234879
wst04-VHDL20_DWEH_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:14 234147
wst04-VHDL20_DWEH_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:18 235326
wst04-VHDL20_DWEH_130800_COR-2611130800-omedes-..> 13-Nov-2026 09:36:44 233423
wst04-VHDL20_DWEH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:25 231563
wst04-VHDL20_DWEH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 233305
wst04-VHDL20_DWEH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 234679
wst04-VHDL20_DWEH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:21 236556
wst04-VHDL20_DWEH_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:46 243030
wst04-VHDL20_DWEI_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:18 335207
wst04-VHDL20_DWEI_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 335443
wst04-VHDL20_DWEI_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:14 334936
wst04-VHDL20_DWEI_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:18 336145
wst04-VHDL20_DWEI_130800_COR-2611130800-omedes-..> 13-Nov-2026 09:36:44 333135
wst04-VHDL20_DWEI_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 333458
wst04-VHDL20_DWEI_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 333716
wst04-VHDL20_DWEI_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 334640
wst04-VHDL20_DWEI_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:30 336671
wst04-VHDL20_DWEI_140800_COR-2611140800-omedes-..> 14-Nov-2026 10:47:58 341698
wst04-VHDL20_DWHG_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:45:13 326833
wst04-VHDL20_DWHG_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:45:15 325500
wst04-VHDL20_DWHG_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:24 326100
wst04-VHDL20_DWHG_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:34 328252
wst04-VHDL20_DWHG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:45:25 325749
wst04-VHDL20_DWHG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:45:22 323876
wst04-VHDL20_DWHG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:24 323896
wst04-VHDL20_DWHG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:48 326428
wst04-VHDL20_DWHH_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:45:13 318855
wst04-VHDL20_DWHH_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:45:15 318672
wst04-VHDL20_DWHH_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:24 225010
wst04-VHDL20_DWHH_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:39 319829
wst04-VHDL20_DWHH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:45:25 315624
wst04-VHDL20_DWHH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:45:22 313914
wst04-VHDL20_DWHH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:24 222547
wst04-VHDL20_DWHH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:48 314855
wst04-VHDL20_DWLG_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:31:23 317037
wst04-VHDL20_DWLG_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 315753
wst04-VHDL20_DWLG_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:47 314596
wst04-VHDL20_DWLG_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:43 316338
wst04-VHDL20_DWLG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 312384
wst04-VHDL20_DWLG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 313294
wst04-VHDL20_DWLG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 313560
wst04-VHDL20_DWLG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 314623
wst04-VHDL20_DWLH_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:31:38 320701
wst04-VHDL20_DWLH_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 320294
wst04-VHDL20_DWLH_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:47 319311
wst04-VHDL20_DWLH_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:43 320833
wst04-VHDL20_DWLH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 316176
wst04-VHDL20_DWLH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 315092
wst04-VHDL20_DWLH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 314677
wst04-VHDL20_DWLH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 316748
wst04-VHDL20_DWLI_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:31:23 323996
wst04-VHDL20_DWLI_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 323067
wst04-VHDL20_DWLI_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:47 322628
wst04-VHDL20_DWLI_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:49 368899
wst04-VHDL20_DWLI_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 315076
wst04-VHDL20_DWLI_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 314462
wst04-VHDL20_DWLI_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:44 313363
wst04-VHDL20_DWLI_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 360336
wst04-VHDL20_DWMO_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:24 430061
wst04-VHDL20_DWMO_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:13 430407
wst04-VHDL20_DWMO_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:18 431053
wst04-VHDL20_DWMO_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:14 430719
wst04-VHDL20_DWMO_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:25 416025
wst04-VHDL20_DWMO_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 416223
wst04-VHDL20_DWMO_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:18 416881
wst04-VHDL20_DWMO_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:30 417786
wst04-VHDL20_DWMP_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:24 553479
wst04-VHDL20_DWMP_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 553016
wst04-VHDL20_DWMP_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:18 552951
wst04-VHDL20_DWMP_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:28 553816
wst04-VHDL20_DWMP_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:33 525456
wst04-VHDL20_DWMP_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 525107
wst04-VHDL20_DWMP_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:18 525081
wst04-VHDL20_DWMP_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:37 527651
wst04-VHDL20_DWPG_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:31:23 319153
wst04-VHDL20_DWPG_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 229595
wst04-VHDL20_DWPG_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:35 318018
wst04-VHDL20_DWPG_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:49 363807
wst04-VHDL20_DWPG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:27 315413
wst04-VHDL20_DWPG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 227343
wst04-VHDL20_DWPG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:32 315727
wst04-VHDL20_DWPG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 361726
wst04-VHDL20_DWPH_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:31:23 228512
wst04-VHDL20_DWPH_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:40 228350
wst04-VHDL20_DWPH_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:35 228357
wst04-VHDL20_DWPH_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:43 228908
wst04-VHDL20_DWPH_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:31:23 229754
wst04-VHDL20_DWPH_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:29 228468
wst04-VHDL20_DWPH_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:32 229140
wst04-VHDL20_DWPH_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:51 229977
wst04-VHDL20_DWSG_121800-2611121800-omedes--0.pdf 12-Nov-2026 19:30:13 339719
wst04-VHDL20_DWSG_130200-2611130200-omedes--0.pdf 13-Nov-2026 03:30:13 339787
wst04-VHDL20_DWSG_130400-2611130400-omedes--0.pdf 13-Nov-2026 06:00:14 340038
wst04-VHDL20_DWSG_130800-2611130800-omedes--0.pdf 13-Nov-2026 09:30:28 340404
wst04-VHDL20_DWSG_131800-2611131800-omedes--0.pdf 13-Nov-2026 19:30:16 335061
wst04-VHDL20_DWSG_140200-2611140200-omedes--0.pdf 14-Nov-2026 03:30:18 332656
wst04-VHDL20_DWSG_140400-2611140400-omedes--0.pdf 14-Nov-2026 06:00:14 333245
wst04-VHDL20_DWSG_140800-2611140800-omedes--0.pdf 14-Nov-2026 09:30:17 333576