Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Jan-2026 14:39:52 6049
SXDL31_DWAV_171800 17-Jan-2026 17:13:13 6369
SXDL31_DWAV_180800 18-Jan-2026 10:31:18 10271
SXDL31_DWAV_181800 18-Jan-2026 16:25:15 4662
SXDL31_DWAV_190800 19-Jan-2026 07:42:49 12185
SXDL31_DWAV_LATEST 19-Jan-2026 07:42:49 12185
SXDL33_DWAV_180000 18-Jan-2026 11:27:40 7373
SXDL33_DWAV_190000 19-Jan-2026 10:59:53 5684
SXDL33_DWAV_LATEST 19-Jan-2026 10:59:53 5684
ber01-FWDL39_DWMS_181230-2601181230-dsw--0-ia5 18-Jan-2026 12:45:31 1708
ber01-FWDL39_DWMS_191230-2601191230-dsw--0-ia5 19-Jan-2026 12:33:10 1328
ber01-VHDL13_DWEH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:17 2814
ber01-VHDL13_DWEH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 3122
ber01-VHDL13_DWEH_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:12 3052
ber01-VHDL13_DWEH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2741
ber01-VHDL13_DWEH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:28:13 2751
ber01-VHDL13_DWEH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:11 3271
ber01-VHDL13_DWEH_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:12 3026
ber01-VHDL13_DWEH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:16 2674
ber01-VHDL13_DWHG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2877
ber01-VHDL13_DWHG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:09 2903
ber01-VHDL13_DWHG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2784
ber01-VHDL13_DWHG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:11 2578
ber01-VHDL13_DWHG_180800_COR-2601180800-dsw--0-ia5 18-Jan-2026 09:40:27 2582
ber01-VHDL13_DWHG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:21 2340
ber01-VHDL13_DWHG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2558
ber01-VHDL13_DWHG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2564
ber01-VHDL13_DWHG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2634
ber01-VHDL13_DWHH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2229
ber01-VHDL13_DWHH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:09 2530
ber01-VHDL13_DWHH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2530
ber01-VHDL13_DWHH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:11 2406
ber01-VHDL13_DWHH_180800_COR-2601180800-dsw--0-ia5 18-Jan-2026 09:40:57 2410
ber01-VHDL13_DWHH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:21 2238
ber01-VHDL13_DWHH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2559
ber01-VHDL13_DWHH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2559
ber01-VHDL13_DWHH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2483
ber01-VHDL13_DWLG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 3129
ber01-VHDL13_DWLG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3163
ber01-VHDL13_DWLG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3244
ber01-VHDL13_DWLG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3231
ber01-VHDL13_DWLG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 2787
ber01-VHDL13_DWLG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2898
ber01-VHDL13_DWLG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 2792
ber01-VHDL13_DWLG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2594
ber01-VHDL13_DWLH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2011
ber01-VHDL13_DWLH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 1944
ber01-VHDL13_DWLH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2053
ber01-VHDL13_DWLH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1803
ber01-VHDL13_DWLH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 1663
ber01-VHDL13_DWLH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1801
ber01-VHDL13_DWLH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1825
ber01-VHDL13_DWLH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1696
ber01-VHDL13_DWLI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 1807
ber01-VHDL13_DWLI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 1827
ber01-VHDL13_DWLI_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 1860
ber01-VHDL13_DWLI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1773
ber01-VHDL13_DWLI_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 1431
ber01-VHDL13_DWLI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1579
ber01-VHDL13_DWLI_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1566
ber01-VHDL13_DWLI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1437
ber01-VHDL13_DWMG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2987
ber01-VHDL13_DWMG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3420
ber01-VHDL13_DWMG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3421
ber01-VHDL13_DWMG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3293
ber01-VHDL13_DWMG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 3072
ber01-VHDL13_DWMG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 3180
ber01-VHDL13_DWMG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 3251
ber01-VHDL13_DWMG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3527
ber01-VHDL13_DWMG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:19:01 3629
ber01-VHDL13_DWMO_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2583
ber01-VHDL13_DWMO_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2978
ber01-VHDL13_DWMO_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2960
ber01-VHDL13_DWMO_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 2657
ber01-VHDL13_DWMO_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 2270
ber01-VHDL13_DWMO_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 2618
ber01-VHDL13_DWMO_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 2618
ber01-VHDL13_DWMO_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2632
ber01-VHDL13_DWMP_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 3132
ber01-VHDL13_DWMP_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3558
ber01-VHDL13_DWMP_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3612
ber01-VHDL13_DWMP_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3444
ber01-VHDL13_DWMP_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 3172
ber01-VHDL13_DWMP_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 3160
ber01-VHDL13_DWMP_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 3233
ber01-VHDL13_DWMP_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3415
ber01-VHDL13_DWMP_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:20:41 3516
ber01-VHDL13_DWOG_171700-2601171700-dsw--0-ia5 17-Jan-2026 19:00:07 3874
ber01-VHDL13_DWOG_180300-2601180300-dsw--0-ia5 18-Jan-2026 04:00:02 4415
ber01-VHDL13_DWOG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 4154
ber01-VHDL13_DWOG_181700-2601181700-dsw--0-ia5 18-Jan-2026 19:00:07 3961
ber01-VHDL13_DWOG_190300-2601190300-dsw--0-ia5 19-Jan-2026 04:00:03 4833
ber01-VHDL13_DWOG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 4768
ber01-VHDL13_DWOH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:11 2713
ber01-VHDL13_DWOH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 2938
ber01-VHDL13_DWOH_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:12 2755
ber01-VHDL13_DWOH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2474
ber01-VHDL13_DWOH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:28:17 2813
ber01-VHDL13_DWOH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:17 2994
ber01-VHDL13_DWOH_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:12 2912
ber01-VHDL13_DWOH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:16 2639
ber01-VHDL13_DWOI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:11 2910
ber01-VHDL13_DWOI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 3140
ber01-VHDL13_DWOI_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:16 3027
ber01-VHDL13_DWOI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2770
ber01-VHDL13_DWOI_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:28:13 3170
ber01-VHDL13_DWOI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:11 3416
ber01-VHDL13_DWOI_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:15 3109
ber01-VHDL13_DWOI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:12 2563
ber01-VHDL13_DWON_171555-2601171555-dsw--0-ia5 17-Jan-2026 15:55:28 3105
ber01-VHDL13_DWON_171729-2601171729-dsw--0-ia5 17-Jan-2026 17:29:42 3093
ber01-VHDL13_DWON_180330-2601180330-dsw--0-ia5 18-Jan-2026 03:30:09 3558
ber01-VHDL13_DWON_180617-2601180617-dsw--0-ia5 18-Jan-2026 06:17:56 3606
ber01-VHDL13_DWON_180715-2601180715-dsw--0-ia5 18-Jan-2026 07:15:31 3630
ber01-VHDL13_DWON_181546-2601181546-dsw--0-ia5 18-Jan-2026 15:46:21 2861
ber01-VHDL13_DWON_181715-2601181715-dsw--0-ia5 18-Jan-2026 17:15:42 2895
ber01-VHDL13_DWON_181754-2601181754-dsw--0-ia5 18-Jan-2026 17:54:28 2895
ber01-VHDL13_DWON_190313-2601190313-dsw--0-ia5 19-Jan-2026 03:13:54 3464
ber01-VHDL13_DWON_190629-2601190629-dsw--0-ia5 19-Jan-2026 06:29:52 4068
ber01-VHDL13_DWON_190720-2601190720-dsw--0-ia5 19-Jan-2026 07:20:11 4061
ber01-VHDL13_DWON_190928-2601190928-dsw--0-ia5 19-Jan-2026 09:28:37 4061
ber01-VHDL13_DWON_190954-2601190954-dsw--0-ia5 19-Jan-2026 09:54:46 4061
ber01-VHDL13_DWPG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2159
ber01-VHDL13_DWPG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2119
ber01-VHDL13_DWPG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2280
ber01-VHDL13_DWPG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1922
ber01-VHDL13_DWPG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 1598
ber01-VHDL13_DWPG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1719
ber01-VHDL13_DWPG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1723
ber01-VHDL13_DWPG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1580
ber01-VHDL13_DWPH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2068
ber01-VHDL13_DWPH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2130
ber01-VHDL13_DWPH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2412
ber01-VHDL13_DWPH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1950
ber01-VHDL13_DWPH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 1672
ber01-VHDL13_DWPH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1942
ber01-VHDL13_DWPH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1911
ber01-VHDL13_DWPH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1769
ber01-VHDL13_DWSG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2120
ber01-VHDL13_DWSG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2896
ber01-VHDL13_DWSG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:07 2664
ber01-VHDL13_DWSG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 2637
ber01-VHDL13_DWSG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:30:04 2489
ber01-VHDL13_DWSG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 2829
ber01-VHDL13_DWSG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 3111
ber01-VHDL13_DWSG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3184
ber01-VHDL13_DWSG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:48:52 3466
ber01-VHDL17_DWOG_181200-2601181200-dsw--0-ia5 18-Jan-2026 13:03:56 2760
ber01-VHDL17_DWOG_191200-2601191200-dsw--0-ia5 19-Jan-2026 12:16:57 2707
swis2-VHDL20_DWEG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3121
swis2-VHDL20_DWEG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3296
swis2-VHDL20_DWEG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3110
swis2-VHDL20_DWEG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3021
swis2-VHDL20_DWEG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 3274
swis2-VHDL20_DWEG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3372
swis2-VHDL20_DWEG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3325
swis2-VHDL20_DWEG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3256
swis2-VHDL20_DWEH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3237
swis2-VHDL20_DWEH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3512
swis2-VHDL20_DWEH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3455
swis2-VHDL20_DWEH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3385
swis2-VHDL20_DWEH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 3214
swis2-VHDL20_DWEH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3669
swis2-VHDL20_DWEH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3259
swis2-VHDL20_DWEH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3296
swis2-VHDL20_DWEI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3297
swis2-VHDL20_DWEI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3468
swis2-VHDL20_DWEI_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3413
swis2-VHDL20_DWEI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3364
swis2-VHDL20_DWEI_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 3678
swis2-VHDL20_DWEI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3836
swis2-VHDL20_DWEI_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3422
swis2-VHDL20_DWEI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3229
swis2-VHDL20_DWHG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:06 3060
swis2-VHDL20_DWHG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3089
swis2-VHDL20_DWHG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2967
swis2-VHDL20_DWHG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3226
swis2-VHDL20_DWHG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 2523
swis2-VHDL20_DWHG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 2744
swis2-VHDL20_DWHG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2747
swis2-VHDL20_DWHG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3244
swis2-VHDL20_DWHH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:06 2415
swis2-VHDL20_DWHH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2716
swis2-VHDL20_DWHH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2716
swis2-VHDL20_DWHH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3065
swis2-VHDL20_DWHH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 2424
swis2-VHDL20_DWHH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 2745
swis2-VHDL20_DWHH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2745
swis2-VHDL20_DWHH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3104
swis2-VHDL20_DWLG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3519
swis2-VHDL20_DWLG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3556
swis2-VHDL20_DWLG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 3599
swis2-VHDL20_DWLG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3774
swis2-VHDL20_DWLG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 3135
swis2-VHDL20_DWLG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 3252
swis2-VHDL20_DWLG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 3132
swis2-VHDL20_DWLG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3078
swis2-VHDL20_DWLH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2408
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swis2-VHDL20_DWLH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2415
swis2-VHDL20_DWLH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 2357
swis2-VHDL20_DWLH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 2018
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swis2-VHDL20_DWLH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 2172
swis2-VHDL20_DWLH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2191
swis2-VHDL20_DWLI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2198
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swis2-VHDL20_DWLI_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 1781
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swis2-VHDL20_DWLI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 1922
swis2-VHDL20_DWMG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3415
swis2-VHDL20_DWMG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3875
swis2-VHDL20_DWMG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3840
swis2-VHDL20_DWMG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3965
swis2-VHDL20_DWMG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:01 3535
swis2-VHDL20_DWMG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3694
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swis2-VHDL20_DWMO_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3015
swis2-VHDL20_DWMO_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3404
swis2-VHDL20_DWMO_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3383
swis2-VHDL20_DWMO_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3303
swis2-VHDL20_DWMO_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:01 2706
swis2-VHDL20_DWMO_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3128
swis2-VHDL20_DWMO_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:02 3057
swis2-VHDL20_DWMO_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3272
swis2-VHDL20_DWMP_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3556
swis2-VHDL20_DWMP_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3982
swis2-VHDL20_DWMP_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 4030
swis2-VHDL20_DWMP_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 4105
swis2-VHDL20_DWMP_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:01 3606
swis2-VHDL20_DWMP_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3679
swis2-VHDL20_DWMP_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3657
swis2-VHDL20_DWMP_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 4052
swis2-VHDL20_DWPG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2692
swis2-VHDL20_DWPG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2505
swis2-VHDL20_DWPG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2623
swis2-VHDL20_DWPG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 2443
swis2-VHDL20_DWPG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 2119
swis2-VHDL20_DWPG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 2068
swis2-VHDL20_DWPG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 2050
swis2-VHDL20_DWPG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2041
swis2-VHDL20_DWPH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2600
swis2-VHDL20_DWPH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2515
swis2-VHDL20_DWPH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2756
swis2-VHDL20_DWPH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 2470
swis2-VHDL20_DWPH_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:06 2192
swis2-VHDL20_DWPH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 2289
swis2-VHDL20_DWPH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 2240
swis2-VHDL20_DWPH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2230
swis2-VHDL20_DWSG_171300-2601171300-dsw--0-ia5 17-Jan-2026 14:45:09 2935
swis2-VHDL20_DWSG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2531
swis2-VHDL20_DWSG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3298
swis2-VHDL20_DWSG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3072
swis2-VHDL20_DWSG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3250
swis2-VHDL20_DWSG_181300-2601181300-dsw--0-ia5 18-Jan-2026 14:45:09 3052
swis2-VHDL20_DWSG_181800-2601181800-dsw--0-ia5 18-Jan-2026 19:45:01 2997
swis2-VHDL20_DWSG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 3312
swis2-VHDL20_DWSG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:02 3519
swis2-VHDL20_DWSG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3892
swis2-VHDL20_DWSG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:48:52 3696
wst04-VHDL20_DWEG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 226789
wst04-VHDL20_DWEG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 227664
wst04-VHDL20_DWEG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:21 226667
wst04-VHDL20_DWEG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:21 228389
wst04-VHDL20_DWEG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:12 228317
wst04-VHDL20_DWEG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 229525
wst04-VHDL20_DWEG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 228992
wst04-VHDL20_DWEG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:21 227519
wst04-VHDL20_DWEH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 225895
wst04-VHDL20_DWEH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 227353
wst04-VHDL20_DWEH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 226876
wst04-VHDL20_DWEH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:21 229329
wst04-VHDL20_DWEH_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:12 228575
wst04-VHDL20_DWEH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 229783
wst04-VHDL20_DWEH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:27 228999
wst04-VHDL20_DWEH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:21 226731
wst04-VHDL20_DWEI_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 318100
wst04-VHDL20_DWEI_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 318416
wst04-VHDL20_DWEI_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:11 318191
wst04-VHDL20_DWEI_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:27 323817
wst04-VHDL20_DWEI_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:12 324183
wst04-VHDL20_DWEI_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 324569
wst04-VHDL20_DWEI_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:27 324293
wst04-VHDL20_DWEI_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:27 321937
wst04-VHDL20_DWHG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 313204
wst04-VHDL20_DWHG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 312959
wst04-VHDL20_DWHG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:12 312643
wst04-VHDL20_DWHG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 311906
wst04-VHDL20_DWHG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:20 310619
wst04-VHDL20_DWHG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 310945
wst04-VHDL20_DWHG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:11 310970
wst04-VHDL20_DWHG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 306774
wst04-VHDL20_DWHH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 292938
wst04-VHDL20_DWHH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 293642
wst04-VHDL20_DWHH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:12 293500
wst04-VHDL20_DWHH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:11 295486
wst04-VHDL20_DWHH_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:16 294763
wst04-VHDL20_DWHH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 295642
wst04-VHDL20_DWHH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:11 295754
wst04-VHDL20_DWHH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 294363
wst04-VHDL20_DWLG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:46:02 301794
wst04-VHDL20_DWLG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 301884
wst04-VHDL20_DWLG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 301965
wst04-VHDL20_DWLG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 305286
wst04-VHDL20_DWLG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:20 304428
wst04-VHDL20_DWLG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 304604
wst04-VHDL20_DWLG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 304757
wst04-VHDL20_DWLG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 311428
wst04-VHDL20_DWLH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 309466
wst04-VHDL20_DWLH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 309491
wst04-VHDL20_DWLH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 309537
wst04-VHDL20_DWLH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 309287
wst04-VHDL20_DWLH_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:26 309316
wst04-VHDL20_DWLH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:27 309917
wst04-VHDL20_DWLH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 309868
wst04-VHDL20_DWLH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:25 309700
wst04-VHDL20_DWLI_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 308978
wst04-VHDL20_DWLI_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 309079
wst04-VHDL20_DWLI_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 309043
wst04-VHDL20_DWLI_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 317179
wst04-VHDL20_DWLI_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:26 316922
wst04-VHDL20_DWLI_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 317542
wst04-VHDL20_DWLI_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 317501
wst04-VHDL20_DWLI_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 320680
wst04-VHDL20_DWMG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 523530
wst04-VHDL20_DWMG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 525430
wst04-VHDL20_DWMG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 524956
wst04-VHDL20_DWMG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:23 538966
wst04-VHDL20_DWMG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:16 538325
wst04-VHDL20_DWMG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 539642
wst04-VHDL20_DWMG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 539622
wst04-VHDL20_DWMG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 535821
wst04-VHDL20_DWMO_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 422767
wst04-VHDL20_DWMO_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 423798
wst04-VHDL20_DWMO_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 424218
wst04-VHDL20_DWMO_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 433711
wst04-VHDL20_DWMO_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:16 432907
wst04-VHDL20_DWMO_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 433738
wst04-VHDL20_DWMO_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:17 434196
wst04-VHDL20_DWMO_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 432968
wst04-VHDL20_DWMP_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 552893
wst04-VHDL20_DWMP_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 552739
wst04-VHDL20_DWMP_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 553667
wst04-VHDL20_DWMP_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 560290
wst04-VHDL20_DWMP_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:16 559416
wst04-VHDL20_DWMP_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 559287
wst04-VHDL20_DWMP_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 560373
wst04-VHDL20_DWMP_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:17 550681
wst04-VHDL20_DWPG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:46:02 305189
wst04-VHDL20_DWPG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 304683
wst04-VHDL20_DWPG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:31 305166
wst04-VHDL20_DWPG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 352372
wst04-VHDL20_DWPG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:20 307972
wst04-VHDL20_DWPG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:27 307796
wst04-VHDL20_DWPG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:31 307747
wst04-VHDL20_DWPG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 349755
wst04-VHDL20_DWPH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 266579
wst04-VHDL20_DWPH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 222068
wst04-VHDL20_DWPH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:31 222385
wst04-VHDL20_DWPH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:27 267149
wst04-VHDL20_DWPH_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:20 266999
wst04-VHDL20_DWPH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 222509
wst04-VHDL20_DWPH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:31 222355
wst04-VHDL20_DWPH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:25 266033
wst04-VHDL20_DWSG_171300-2601171300-omedes--0.pdf 17-Jan-2026 14:45:12 340651
wst04-VHDL20_DWSG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 339884
wst04-VHDL20_DWSG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 340562
wst04-VHDL20_DWSG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:11 340211
wst04-VHDL20_DWSG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:11 338948
wst04-VHDL20_DWSG_181300-2601181300-omedes--0.pdf 18-Jan-2026 14:45:40 338879
wst04-VHDL20_DWSG_181800-2601181800-omedes--0.pdf 18-Jan-2026 19:45:12 338605
wst04-VHDL20_DWSG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 339227
wst04-VHDL20_DWSG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:11 339682
wst04-VHDL20_DWSG_190800-2601190800-omedes--0.pdf 19-Jan-2026 10:49:03 328862