Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Jan-2026 14:44:49 4448
SXDL31_DWAV_231800 23-Jan-2026 18:04:55 8199
SXDL31_DWAV_240800 24-Jan-2026 08:01:53 10662
SXDL31_DWAV_241800 24-Jan-2026 18:25:44 7812
SXDL31_DWAV_250800 25-Jan-2026 10:03:35 14981
SXDL31_DWAV_LATEST 25-Jan-2026 10:03:35 14981
SXDL33_DWAV_240000 24-Jan-2026 10:01:49 6715
SXDL33_DWAV_250000 25-Jan-2026 13:51:14 10600
SXDL33_DWAV_LATEST 25-Jan-2026 13:51:14 10600
ber01-FWDL39_DWMS_241230-2601241230-dsw--0-ia5 24-Jan-2026 12:47:42 1914
ber01-FWDL39_DWMS_251230-2601251230-dsw--0-ia5 25-Jan-2026 12:19:42 1226
ber01-VHDL13_DWEH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:22 3284
ber01-VHDL13_DWEH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3745
ber01-VHDL13_DWEH_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3699
ber01-VHDL13_DWEH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:22 3989
ber01-VHDL13_DWEH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:22 2468
ber01-VHDL13_DWEH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3258
ber01-VHDL13_DWEH_250400-2601250400-dsw--0-ia5 25-Jan-2026 05:58:16 3694
ber01-VHDL13_DWEH_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3657
ber01-VHDL13_DWEH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 09:58:52 3483
ber01-VHDL13_DWHG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 4496
ber01-VHDL13_DWHG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 4510
ber01-VHDL13_DWHG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 4635
ber01-VHDL13_DWHG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 4635
ber01-VHDL13_DWHG_240800_COR-2601240800-dsw--0-ia5 24-Jan-2026 09:43:01 4765
ber01-VHDL13_DWHG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 3581
ber01-VHDL13_DWHG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3848
ber01-VHDL13_DWHG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3847
ber01-VHDL13_DWHG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4131
ber01-VHDL13_DWHH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 3263
ber01-VHDL13_DWHH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 3214
ber01-VHDL13_DWHH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3240
ber01-VHDL13_DWHH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3240
ber01-VHDL13_DWHH_240800_COR-2601240800-dsw--0-ia5 24-Jan-2026 09:43:21 3470
ber01-VHDL13_DWHH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3006
ber01-VHDL13_DWHH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3894
ber01-VHDL13_DWHH_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3894
ber01-VHDL13_DWHH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4280
ber01-VHDL13_DWLG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 2253
ber01-VHDL13_DWLG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2546
ber01-VHDL13_DWLG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2693
ber01-VHDL13_DWLG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3431
ber01-VHDL13_DWLG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3559
ber01-VHDL13_DWLG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3609
ber01-VHDL13_DWLG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3648
ber01-VHDL13_DWLG_250400_COR-2601250400-dsw--0-ia5 25-Jan-2026 06:13:52 3626
ber01-VHDL13_DWLG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4033
ber01-VHDL13_DWLH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 1954
ber01-VHDL13_DWLH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2262
ber01-VHDL13_DWLH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2388
ber01-VHDL13_DWLH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2779
ber01-VHDL13_DWLH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 3008
ber01-VHDL13_DWLH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3242
ber01-VHDL13_DWLH_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3201
ber01-VHDL13_DWLH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3436
ber01-VHDL13_DWLI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:07 2014
ber01-VHDL13_DWLI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2195
ber01-VHDL13_DWLI_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2281
ber01-VHDL13_DWLI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2504
ber01-VHDL13_DWLI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:27 2788
ber01-VHDL13_DWLI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 2997
ber01-VHDL13_DWLI_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3119
ber01-VHDL13_DWLI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3516
ber01-VHDL13_DWMG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2919
ber01-VHDL13_DWMG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:01 3004
ber01-VHDL13_DWMG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3123
ber01-VHDL13_DWMG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3965
ber01-VHDL13_DWMG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3148
ber01-VHDL13_DWMG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4332
ber01-VHDL13_DWMG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:08 4358
ber01-VHDL13_DWMG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3982
ber01-VHDL13_DWMO_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2820
ber01-VHDL13_DWMO_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 3200
ber01-VHDL13_DWMO_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3200
ber01-VHDL13_DWMO_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 3589
ber01-VHDL13_DWMO_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 2796
ber01-VHDL13_DWMO_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3424
ber01-VHDL13_DWMO_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:08 3424
ber01-VHDL13_DWMO_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3284
ber01-VHDL13_DWMP_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:02 2863
ber01-VHDL13_DWMP_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 3137
ber01-VHDL13_DWMP_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3198
ber01-VHDL13_DWMP_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:06 4105
ber01-VHDL13_DWMP_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3167
ber01-VHDL13_DWMP_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4407
ber01-VHDL13_DWMP_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:08 4407
ber01-VHDL13_DWMP_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 4125
ber01-VHDL13_DWOG_231700-2601231700-dsw--0-ia5 23-Jan-2026 19:00:02 4108
ber01-VHDL13_DWOG_240300-2601240300-dsw--0-ia5 24-Jan-2026 04:00:03 4695
ber01-VHDL13_DWOG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 5077
ber01-VHDL13_DWOG_241700-2601241700-dsw--0-ia5 24-Jan-2026 19:00:06 4604
ber01-VHDL13_DWOG_250300-2601250300-dsw--0-ia5 25-Jan-2026 04:00:01 5679
ber01-VHDL13_DWOG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 6138
ber01-VHDL13_DWOH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:16 2787
ber01-VHDL13_DWOH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3394
ber01-VHDL13_DWOH_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3343
ber01-VHDL13_DWOH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:16 3750
ber01-VHDL13_DWOH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:16 2670
ber01-VHDL13_DWOH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3050
ber01-VHDL13_DWOH_250400-2601250400-dsw--0-ia5 25-Jan-2026 05:58:16 3351
ber01-VHDL13_DWOH_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3391
ber01-VHDL13_DWOH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 09:58:52 3246
ber01-VHDL13_DWOI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:28:16 2695
ber01-VHDL13_DWOI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:28:16 3392
ber01-VHDL13_DWOI_240400-2601240400-dsw--0-ia5 24-Jan-2026 05:58:18 3334
ber01-VHDL13_DWOI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:28:16 3269
ber01-VHDL13_DWOI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:28:16 3007
ber01-VHDL13_DWOI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:28:20 3550
ber01-VHDL13_DWOI_250400-2601250400-dsw--0-ia5 25-Jan-2026 05:58:23 3883
ber01-VHDL13_DWOI_250800-2601250800-dsw--0-ia5 25-Jan-2026 12:21:23 3776
ber01-VHDL13_DWOI_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 09:59:08 3769
ber01-VHDL13_DWON_231421-2601231421-dsw--0-ia5 23-Jan-2026 14:21:47 3581
ber01-VHDL13_DWON_231823-2601231823-dsw--0-ia5 23-Jan-2026 18:23:41 3242
ber01-VHDL13_DWON_232351-2601232351-dsw--0-ia5 23-Jan-2026 23:51:41 3910
ber01-VHDL13_DWON_240147-2601240147-dsw--0-ia5 24-Jan-2026 01:47:06 3309
ber01-VHDL13_DWON_240303-2601240303-dsw--0-ia5 24-Jan-2026 03:03:27 3309
ber01-VHDL13_DWON_240314-2601240314-dsw--0-ia5 24-Jan-2026 03:14:17 3696
ber01-VHDL13_DWON_240447-2601240447-dsw--0-ia5 24-Jan-2026 04:47:32 3684
ber01-VHDL13_DWON_240451-2601240451-dsw--0-ia5 24-Jan-2026 04:51:54 3684
ber01-VHDL13_DWON_240630-2601240630-dsw--0-ia5 24-Jan-2026 06:30:32 4083
ber01-VHDL13_DWON_240710-2601240710-dsw--0-ia5 24-Jan-2026 07:10:07 4239
ber01-VHDL13_DWON_240718-2601240718-dsw--0-ia5 24-Jan-2026 07:19:02 4232
ber01-VHDL13_DWON_240913-2601240913-dsw--0-ia5 24-Jan-2026 09:13:22 4194
ber01-VHDL13_DWON_241539-2601241539-dsw--0-ia5 24-Jan-2026 15:41:09 3299
ber01-VHDL13_DWON_241849-2601241849-dsw--0-ia5 24-Jan-2026 18:49:52 3472
ber01-VHDL13_DWON_242341-2601242341-dsw--0-ia5 24-Jan-2026 23:41:15 3315
ber01-VHDL13_DWON_250119-2601250119-dsw--0-ia5 25-Jan-2026 01:19:51 3315
ber01-VHDL13_DWON_250151-2601250151-dsw--0-ia5 25-Jan-2026 01:51:17 3560
ber01-VHDL13_DWON_250316-2601250316-dsw--0-ia5 25-Jan-2026 03:16:52 3560
ber01-VHDL13_DWON_250439-2601250439-dsw--0-ia5 25-Jan-2026 04:39:26 3560
ber01-VHDL13_DWON_250628-2601250628-dsw--0-ia5 25-Jan-2026 06:28:21 3560
ber01-VHDL13_DWON_250724-2601250724-dsw--0-ia5 25-Jan-2026 07:24:56 4785
ber01-VHDL13_DWPG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2413
ber01-VHDL13_DWPG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2661
ber01-VHDL13_DWPG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2719
ber01-VHDL13_DWPG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3002
ber01-VHDL13_DWPG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3370
ber01-VHDL13_DWPG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3527
ber01-VHDL13_DWPG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3361
ber01-VHDL13_DWPG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3198
ber01-VHDL13_DWPH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2500
ber01-VHDL13_DWPH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:03 2689
ber01-VHDL13_DWPH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:01 2500
ber01-VHDL13_DWPH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 2801
ber01-VHDL13_DWPH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3409
ber01-VHDL13_DWPH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 3693
ber01-VHDL13_DWPH_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3696
ber01-VHDL13_DWPH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3866
ber01-VHDL13_DWSG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:30:05 2755
ber01-VHDL13_DWSG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:30:07 3016
ber01-VHDL13_DWSG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:08 2972
ber01-VHDL13_DWSG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:30:01 3243
ber01-VHDL13_DWSG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:30:25 3261
ber01-VHDL13_DWSG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:30:10 4137
ber01-VHDL13_DWSG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 3550
ber01-VHDL13_DWSG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:30:09 3551
ber01-VHDL13_DWSG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 09:38:50 3931
ber01-VHDL17_DWOG_241200-2601241200-dsw--0-ia5 24-Jan-2026 11:47:02 2682
ber01-VHDL17_DWOG_251200-2601251200-dsw--0-ia5 25-Jan-2026 12:56:13 3011
swis2-VHDL20_DWEG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3285
swis2-VHDL20_DWEG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3910
swis2-VHDL20_DWEG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3722
swis2-VHDL20_DWEG_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:26:37 4133
swis2-VHDL20_DWEG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4627
swis2-VHDL20_DWEG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3183
swis2-VHDL20_DWEG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3496
swis2-VHDL20_DWEG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:06 3961
swis2-VHDL20_DWEG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4431
swis2-VHDL20_DWEG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 12:28:01 4477
swis2-VHDL20_DWEH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3760
swis2-VHDL20_DWEH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 4188
swis2-VHDL20_DWEH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 4102
swis2-VHDL20_DWEH_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:27:21 4396
swis2-VHDL20_DWEH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4935
swis2-VHDL20_DWEH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 2947
swis2-VHDL20_DWEH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3704
swis2-VHDL20_DWEH_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:06 4385
swis2-VHDL20_DWEH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4840
swis2-VHDL20_DWEH_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 12:28:22 4807
swis2-VHDL20_DWEI_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3225
swis2-VHDL20_DWEI_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3913
swis2-VHDL20_DWEI_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3759
swis2-VHDL20_DWEI_240400_COR-2601240400-dsw--0-ia5 24-Jan-2026 11:28:11 3692
swis2-VHDL20_DWEI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4144
swis2-VHDL20_DWEI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3532
swis2-VHDL20_DWEI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4016
swis2-VHDL20_DWEI_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:06 4502
swis2-VHDL20_DWEI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4894
swis2-VHDL20_DWEI_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 12:28:56 4785
swis2-VHDL20_DWHG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:04 4679
swis2-VHDL20_DWHG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 4696
swis2-VHDL20_DWHG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 4818
swis2-VHDL20_DWHG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:01 5723
swis2-VHDL20_DWHG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:02 3764
swis2-VHDL20_DWHG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4034
swis2-VHDL20_DWHG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:06 4030
swis2-VHDL20_DWHG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4969
swis2-VHDL20_DWHH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:04 3449
swis2-VHDL20_DWHH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3400
swis2-VHDL20_DWHH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:06 3426
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swis2-VHDL20_DWHH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4080
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swis2-VHDL20_DWLH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3666
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swis2-VHDL20_DWLI_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:12 2706
swis2-VHDL20_DWLI_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 3081
swis2-VHDL20_DWLI_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3206
swis2-VHDL20_DWLI_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3415
swis2-VHDL20_DWLI_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:16 3544
swis2-VHDL20_DWLI_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4162
swis2-VHDL20_DWMG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3391
swis2-VHDL20_DWMG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3430
swis2-VHDL20_DWMG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:01 3547
swis2-VHDL20_DWMG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4572
swis2-VHDL20_DWMG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3570
swis2-VHDL20_DWMG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4797
swis2-VHDL20_DWMG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:02 4925
swis2-VHDL20_DWMG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4783
swis2-VHDL20_DWMO_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3297
swis2-VHDL20_DWMO_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3630
swis2-VHDL20_DWMO_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:01 3714
swis2-VHDL20_DWMO_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4191
swis2-VHDL20_DWMO_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3224
swis2-VHDL20_DWMO_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3900
swis2-VHDL20_DWMO_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:02 3834
swis2-VHDL20_DWMO_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 3930
swis2-VHDL20_DWMP_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3333
swis2-VHDL20_DWMP_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3569
swis2-VHDL20_DWMP_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:01 3621
swis2-VHDL20_DWMP_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 4718
swis2-VHDL20_DWMP_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3618
swis2-VHDL20_DWMP_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4834
swis2-VHDL20_DWMP_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:06 4928
swis2-VHDL20_DWMP_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4886
swis2-VHDL20_DWPG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3255
swis2-VHDL20_DWPG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:08 3256
swis2-VHDL20_DWPG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:12 3162
swis2-VHDL20_DWPG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 3884
swis2-VHDL20_DWPG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 4249
swis2-VHDL20_DWPG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 3938
swis2-VHDL20_DWPG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:16 3935
swis2-VHDL20_DWPG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4029
swis2-VHDL20_DWPH_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3342
swis2-VHDL20_DWPH_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3283
swis2-VHDL20_DWPH_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:00:12 2945
swis2-VHDL20_DWPH_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:06 3619
swis2-VHDL20_DWPH_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:08 4127
swis2-VHDL20_DWPH_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4103
swis2-VHDL20_DWPH_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:00:16 4222
swis2-VHDL20_DWPH_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:06 4768
swis2-VHDL20_DWSG_231300-2601231300-dsw--0-ia5 23-Jan-2026 14:45:38 3250
swis2-VHDL20_DWSG_231800-2601231800-dsw--0-ia5 23-Jan-2026 19:45:06 3278
swis2-VHDL20_DWSG_240200-2601240200-dsw--0-ia5 24-Jan-2026 03:45:06 3530
swis2-VHDL20_DWSG_240400-2601240400-dsw--0-ia5 24-Jan-2026 06:15:07 3381
swis2-VHDL20_DWSG_240800-2601240800-dsw--0-ia5 24-Jan-2026 09:45:01 3840
swis2-VHDL20_DWSG_241300-2601241300-dsw--0-ia5 24-Jan-2026 14:45:06 3628
swis2-VHDL20_DWSG_241800-2601241800-dsw--0-ia5 24-Jan-2026 19:45:06 3672
swis2-VHDL20_DWSG_250200-2601250200-dsw--0-ia5 25-Jan-2026 03:45:24 4539
swis2-VHDL20_DWSG_250400-2601250400-dsw--0-ia5 25-Jan-2026 06:15:06 3946
swis2-VHDL20_DWSG_250800-2601250800-dsw--0-ia5 25-Jan-2026 09:45:02 4578
swis2-VHDL20_DWSG_250800_COR-2601250800-dsw--0-ia5 25-Jan-2026 09:38:50 4582
wst04-VHDL20_DWEG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:16 232196
wst04-VHDL20_DWEG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:17 233477
wst04-VHDL20_DWEG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:17 232899
wst04-VHDL20_DWEG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 229533
wst04-VHDL20_DWEG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:18 227002
wst04-VHDL20_DWEG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 228928
wst04-VHDL20_DWEG_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:26 228752
wst04-VHDL20_DWEG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:18 228134
wst04-VHDL20_DWEG_250800_COR-2601250800-omedes-..> 25-Jan-2026 09:59:08 227978
wst04-VHDL20_DWEH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 231836
wst04-VHDL20_DWEH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 232353
wst04-VHDL20_DWEH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:21 231857
wst04-VHDL20_DWEH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:16 226427
wst04-VHDL20_DWEH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 224061
wst04-VHDL20_DWEH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 226785
wst04-VHDL20_DWEH_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:18 226704
wst04-VHDL20_DWEH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 224982
wst04-VHDL20_DWEH_250800_COR-2601250800-omedes-..> 25-Jan-2026 09:58:56 224249
wst04-VHDL20_DWEI_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:16 330237
wst04-VHDL20_DWEI_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:17 330775
wst04-VHDL20_DWEI_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:25 330629
wst04-VHDL20_DWEI_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:16 323134
wst04-VHDL20_DWEI_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:18 322031
wst04-VHDL20_DWEI_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 323352
wst04-VHDL20_DWEI_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:26 323590
wst04-VHDL20_DWEI_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:16 314149
wst04-VHDL20_DWEI_250800_COR-2601250800-omedes-..> 25-Jan-2026 09:58:56 314003
wst04-VHDL20_DWHG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 310498
wst04-VHDL20_DWHG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 310741
wst04-VHDL20_DWHG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:12 310889
wst04-VHDL20_DWHG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 302713
wst04-VHDL20_DWHG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 299543
wst04-VHDL20_DWHG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 299699
wst04-VHDL20_DWHG_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:12 299646
wst04-VHDL20_DWHG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 300322
wst04-VHDL20_DWHH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 291366
wst04-VHDL20_DWHH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 291418
wst04-VHDL20_DWHH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:12 291502
wst04-VHDL20_DWHH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:12 292451
wst04-VHDL20_DWHH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:12 289969
wst04-VHDL20_DWHH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 290516
wst04-VHDL20_DWHH_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:12 290581
wst04-VHDL20_DWHH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:12 291602
wst04-VHDL20_DWLG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:32 308686
wst04-VHDL20_DWLG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:27 308878
wst04-VHDL20_DWLG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:43 308642
wst04-VHDL20_DWLG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:32 303981
wst04-VHDL20_DWLG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:27 304023
wst04-VHDL20_DWLG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:33 303974
wst04-VHDL20_DWLG_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:41 304275
wst04-VHDL20_DWLG_250400_COR-2601250400-omedes-..> 25-Jan-2026 06:14:37 304252
wst04-VHDL20_DWLG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 300482
wst04-VHDL20_DWLH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:26 297656
wst04-VHDL20_DWLH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:31 298015
wst04-VHDL20_DWLH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:43 298142
wst04-VHDL20_DWLH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:38 297934
wst04-VHDL20_DWLH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:30 297445
wst04-VHDL20_DWLH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:29 297926
wst04-VHDL20_DWLH_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:47 297656
wst04-VHDL20_DWLH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 295602
wst04-VHDL20_DWLI_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:32 315618
wst04-VHDL20_DWLI_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:31 315630
wst04-VHDL20_DWLI_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:47 315744
wst04-VHDL20_DWLI_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:36 301172
wst04-VHDL20_DWLI_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:27 300911
wst04-VHDL20_DWLI_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:31 301152
wst04-VHDL20_DWLI_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:43 301138
wst04-VHDL20_DWLI_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:32 297246
wst04-VHDL20_DWMG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:22 538532
wst04-VHDL20_DWMG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:21 537866
wst04-VHDL20_DWMG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:21 538222
wst04-VHDL20_DWMG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:22 535559
wst04-VHDL20_DWMG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:22 533750
wst04-VHDL20_DWMG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:29 535772
wst04-VHDL20_DWMG_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:22 535656
wst04-VHDL20_DWMG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 535723
wst04-VHDL20_DWMO_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:22 425035
wst04-VHDL20_DWMO_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:21 424401
wst04-VHDL20_DWMO_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:17 425550
wst04-VHDL20_DWMO_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:26 425662
wst04-VHDL20_DWMO_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:22 424454
wst04-VHDL20_DWMO_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 425026
wst04-VHDL20_DWMO_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:16 425473
wst04-VHDL20_DWMO_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 419678
wst04-VHDL20_DWMP_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:22 564137
wst04-VHDL20_DWMP_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:21 562418
wst04-VHDL20_DWMP_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:27 563702
wst04-VHDL20_DWMP_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:32 565530
wst04-VHDL20_DWMP_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:22 563553
wst04-VHDL20_DWMP_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:24 563350
wst04-VHDL20_DWMP_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:15:22 565378
wst04-VHDL20_DWMP_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:26 560045
wst04-VHDL20_DWPG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:32 302294
wst04-VHDL20_DWPG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:31 301870
wst04-VHDL20_DWPG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:33 302012
wst04-VHDL20_DWPG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:38 342621
wst04-VHDL20_DWPG_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:30 298105
wst04-VHDL20_DWPG_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:31 298473
wst04-VHDL20_DWPG_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:31 298069
wst04-VHDL20_DWPG_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:36 346209
wst04-VHDL20_DWPH_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:26 264378
wst04-VHDL20_DWPH_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:27 219311
wst04-VHDL20_DWPH_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:00:33 218981
wst04-VHDL20_DWPH_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:32 259886
wst04-VHDL20_DWPH_241800-2601241800-omedes--0.pdf 24-Jan-2026 19:45:27 261564
wst04-VHDL20_DWPH_250200-2601250200-omedes--0.pdf 25-Jan-2026 03:45:29 216522
wst04-VHDL20_DWPH_250400-2601250400-omedes--0.pdf 25-Jan-2026 06:00:31 216634
wst04-VHDL20_DWPH_250800-2601250800-omedes--0.pdf 25-Jan-2026 09:45:32 263045
wst04-VHDL20_DWSG_231300-2601231300-omedes--0.pdf 23-Jan-2026 14:45:38 337808
wst04-VHDL20_DWSG_231800-2601231800-omedes--0.pdf 23-Jan-2026 19:45:12 338335
wst04-VHDL20_DWSG_240200-2601240200-omedes--0.pdf 24-Jan-2026 03:45:12 338341
wst04-VHDL20_DWSG_240400-2601240400-omedes--0.pdf 24-Jan-2026 06:15:11 338331
wst04-VHDL20_DWSG_240800-2601240800-omedes--0.pdf 24-Jan-2026 09:45:10 341099
wst04-VHDL20_DWSG_241300-2601241300-omedes--0.pdf 24-Jan-2026 14:45:12 340730
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wst04-VHDL20_DWSG_250800_COR-2601250800-omedes-..> 25-Jan-2026 09:38:50 328663