Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Jun-2026 13:48:28 4894
FPDL13_DWMZ_180600 18-Jun-2026 12:40:56 6490
SXDL31_DWAV_171800 17-Jun-2026 16:33:25 5710
SXDL31_DWAV_180800 18-Jun-2026 10:24:35 14091
SXDL31_DWAV_181800 18-Jun-2026 16:43:20 15220
SXDL31_DWAV_190800 19-Jun-2026 09:40:55 15939
SXDL31_DWAV_LATEST 19-Jun-2026 09:40:55 15939
SXDL33_DWAV_180000 18-Jun-2026 10:51:52 20679
SXDL33_DWAV_190000 19-Jun-2026 09:39:29 11287
SXDL33_DWAV_LATEST 19-Jun-2026 09:39:29 11287
ber01-FWDL39_DWMS_171200-2606171200-dsw--0-ia5 17-Jun-2026 11:58:55 1460
ber01-FWDL39_DWMS_181200-2606181200-dsw--0-ia5 18-Jun-2026 09:48:23 1625
ber01-FWDL39_DWMS_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:25:51 1336
ber01-VHDL13_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3493
ber01-VHDL13_DWEG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:12 3431
ber01-VHDL13_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 4161
ber01-VHDL13_DWEH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:16 3906
ber01-VHDL13_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:28:16 3393
ber01-VHDL13_DWEI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:28:16 3477
ber01-VHDL13_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3038
ber01-VHDL13_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 10:54:52 3231
ber01-VHDL13_DWHG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3715
ber01-VHDL13_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3044
ber01-VHDL13_DWHH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3595
ber01-VHDL13_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2514
ber01-VHDL13_DWLG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2629
ber01-VHDL13_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2480
ber01-VHDL13_DWLH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2770
ber01-VHDL13_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2411
ber01-VHDL13_DWLI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2722
ber01-VHDL13_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3033
ber01-VHDL13_DWMO_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3467
ber01-VHDL13_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3367
ber01-VHDL13_DWMP_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3413
ber01-VHDL13_DWOG_171700-2606171700-dsw--0-ia5 17-Jun-2026 18:00:01 2767
ber01-VHDL13_DWOG_180300-2606180300-dsw--0-ia5 18-Jun-2026 03:01:30 3374
ber01-VHDL13_DWOG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3756
ber01-VHDL13_DWOG_181700-2606181700-dsw--0-ia5 18-Jun-2026 18:00:01 4526
ber01-VHDL13_DWOG_190300-2606190300-dsw--0-ia5 19-Jun-2026 03:00:01 4739
ber01-VHDL13_DWOG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 4679
ber01-VHDL13_DWON_171417-2606171417-dsw--0-ia5 17-Jun-2026 14:17:57 3495
ber01-VHDL13_DWON_171713-2606171713-dsw--0-ia5 17-Jun-2026 17:13:56 2814
ber01-VHDL13_DWON_171725-2606171725-dsw--0-ia5 17-Jun-2026 17:25:51 2814
ber01-VHDL13_DWON_172109-2606172109-dsw--0-ia5 17-Jun-2026 21:09:41 2845
ber01-VHDL13_DWON_172215-2606172215-dsw--0-ia5 17-Jun-2026 22:15:11 3118
ber01-VHDL13_DWON_180127-2606180127-dsw--0-ia5 18-Jun-2026 01:27:42 3118
ber01-VHDL13_DWON_180511-2606180511-dsw--0-ia5 18-Jun-2026 05:11:56 3126
ber01-VHDL13_DWON_180529-2606180529-dsw--0-ia5 18-Jun-2026 05:29:13 3274
ber01-VHDL13_DWON_180537-2606180537-dsw--0-ia5 18-Jun-2026 05:37:22 3939
ber01-VHDL13_DWON_180644-2606180644-dsw--0-ia5 18-Jun-2026 06:44:27 3982
ber01-VHDL13_DWON_181231-2606181231-dsw--0-ia5 18-Jun-2026 12:31:06 3958
ber01-VHDL13_DWON_181448-2606181448-dsw--0-ia5 18-Jun-2026 14:48:56 3661
ber01-VHDL13_DWON_181653-2606181653-dsw--0-ia5 18-Jun-2026 16:53:21 3579
ber01-VHDL13_DWON_181737-2606181737-dsw--0-ia5 18-Jun-2026 17:37:31 3579
ber01-VHDL13_DWON_182159-2606182159-dsw--0-ia5 18-Jun-2026 22:00:01 3512
ber01-VHDL13_DWON_190034-2606190034-dsw--0-ia5 19-Jun-2026 00:34:48 3759
ber01-VHDL13_DWON_190211-2606190211-dsw--0-ia5 19-Jun-2026 02:11:22 3759
ber01-VHDL13_DWON_190519-2606190519-dsw--0-ia5 19-Jun-2026 05:19:31 3686
ber01-VHDL13_DWON_190733-2606190733-dsw--0-ia5 19-Jun-2026 07:34:00 3661
ber01-VHDL13_DWON_190931-2606190931-dsw--0-ia5 19-Jun-2026 09:31:47 3512
ber01-VHDL13_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2391
ber01-VHDL13_DWPG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2812
ber01-VHDL13_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2532
ber01-VHDL13_DWPH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2759
ber01-VHDL13_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 3547
ber01-VHDL13_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 3906
ber01-VHDL13_DWSG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 3826
ber01-VHDL13_DWSG_190800_COR-2606190800-dsw--0-ia5 19-Jun-2026 05:24:56 3841
ber01-VHDL17_DWOG_181200-2606181200-dsw--0-ia5 18-Jun-2026 11:51:17 3712
ber01-VHDL17_DWOG_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:05:47 3322
swis2-VHDL20_DWEG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1927
swis2-VHDL20_DWEG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1621
swis2-VHDL20_DWEG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1614
swis2-VHDL20_DWEG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 2061
swis2-VHDL20_DWEG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 1927
swis2-VHDL20_DWEG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1507
swis2-VHDL20_DWEG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 2092
swis2-VHDL20_DWEG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2371
swis2-VHDL20_DWEH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 2224
swis2-VHDL20_DWEH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1905
swis2-VHDL20_DWEH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1905
swis2-VHDL20_DWEH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2581
swis2-VHDL20_DWEH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2513
swis2-VHDL20_DWEH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1985
swis2-VHDL20_DWEH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 2250
swis2-VHDL20_DWEH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2729
swis2-VHDL20_DWEI_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1932
swis2-VHDL20_DWEI_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1626
swis2-VHDL20_DWEI_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:01:19 1622
swis2-VHDL20_DWEI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 2017
swis2-VHDL20_DWEI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:07 2257
swis2-VHDL20_DWEI_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:01 1742
swis2-VHDL20_DWEI_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:01:16 1715
swis2-VHDL20_DWEI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 2365
swis2-VHDL20_DWHG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:45:06 1493
swis2-VHDL20_DWHG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:45:42 1247
swis2-VHDL20_DWHG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1255
swis2-VHDL20_DWHG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1686
swis2-VHDL20_DWHG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 11:05:21 1691
swis2-VHDL20_DWHG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1656
swis2-VHDL20_DWHG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:45:10 1961
swis2-VHDL20_DWHG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 2024
swis2-VHDL20_DWHG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:45:12 2149
swis2-VHDL20_DWHH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:45:06 1313
swis2-VHDL20_DWHH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:45:42 1092
swis2-VHDL20_DWHH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1252
swis2-VHDL20_DWHH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:45:17 1398
swis2-VHDL20_DWHH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:45:07 1606
swis2-VHDL20_DWHH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:45:10 1898
swis2-VHDL20_DWHH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 1935
swis2-VHDL20_DWHH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:45:12 2078
swis2-VHDL20_DWLG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1397
swis2-VHDL20_DWLG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1062
swis2-VHDL20_DWLG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1138
swis2-VHDL20_DWLG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1627
swis2-VHDL20_DWLG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1315
swis2-VHDL20_DWLG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1308
swis2-VHDL20_DWLG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1303
swis2-VHDL20_DWLG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1558
swis2-VHDL20_DWLH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1475
swis2-VHDL20_DWLH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1139
swis2-VHDL20_DWLH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1215
swis2-VHDL20_DWLH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1716
swis2-VHDL20_DWLH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1441
swis2-VHDL20_DWLH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1314
swis2-VHDL20_DWLH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1299
swis2-VHDL20_DWLH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1600
swis2-VHDL20_DWLI_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1402
swis2-VHDL20_DWLI_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1069
swis2-VHDL20_DWLI_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1145
swis2-VHDL20_DWLI_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1633
swis2-VHDL20_DWLI_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1405
swis2-VHDL20_DWLI_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1314
swis2-VHDL20_DWLI_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1293
swis2-VHDL20_DWLI_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1559
swis2-VHDL20_DWMO_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1324
swis2-VHDL20_DWMO_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:09 1098
swis2-VHDL20_DWMO_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:02 1235
swis2-VHDL20_DWMO_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:07 1416
swis2-VHDL20_DWMO_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1367
swis2-VHDL20_DWMO_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1419
swis2-VHDL20_DWMO_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:01 1427
swis2-VHDL20_DWMO_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1652
swis2-VHDL20_DWMP_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1408
swis2-VHDL20_DWMP_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:09 1056
swis2-VHDL20_DWMP_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:02 1368
swis2-VHDL20_DWMP_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1662
swis2-VHDL20_DWMP_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1603
swis2-VHDL20_DWMP_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:06 1472
swis2-VHDL20_DWMP_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:01 1464
swis2-VHDL20_DWMP_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1680
swis2-VHDL20_DWPG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1536
swis2-VHDL20_DWPG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1187
swis2-VHDL20_DWPG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1169
swis2-VHDL20_DWPG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1590
swis2-VHDL20_DWPG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1508
swis2-VHDL20_DWPG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1410
swis2-VHDL20_DWPG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1431
swis2-VHDL20_DWPG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1764
swis2-VHDL20_DWPH_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:31:01 1494
swis2-VHDL20_DWPH_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:23 1180
swis2-VHDL20_DWPH_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:12 1184
swis2-VHDL20_DWPH_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:21 1571
swis2-VHDL20_DWPH_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:31:00 1288
swis2-VHDL20_DWPH_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:20 1467
swis2-VHDL20_DWPH_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:15 1348
swis2-VHDL20_DWPH_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1447
swis2-VHDL20_DWSG_171800-2606171800-dsw--0-ia5 17-Jun-2026 18:30:08 1116
swis2-VHDL20_DWSG_180200-2606180200-dsw--0-ia5 18-Jun-2026 02:30:03 1156
swis2-VHDL20_DWSG_180400-2606180400-dsw--0-ia5 18-Jun-2026 05:00:16 1344
swis2-VHDL20_DWSG_180800-2606180800-dsw--0-ia5 18-Jun-2026 08:30:08 1561
swis2-VHDL20_DWSG_180800_COR-2606180800-dsw--0-ia5 18-Jun-2026 14:46:01 1831
swis2-VHDL20_DWSG_181800-2606181800-dsw--0-ia5 18-Jun-2026 18:30:03 1740
swis2-VHDL20_DWSG_190200-2606190200-dsw--0-ia5 19-Jun-2026 02:30:01 1527
swis2-VHDL20_DWSG_190400-2606190400-dsw--0-ia5 19-Jun-2026 05:00:17 1524
swis2-VHDL20_DWSG_190800-2606190800-dsw--0-ia5 19-Jun-2026 08:30:29 1890
swis2-VHDL20_DWSG_190800_COR-2606190800-dsw--0-ia5 19-Jun-2026 05:24:56 1905
wst04-VHDL20_DWEG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 246900
wst04-VHDL20_DWEG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 246459
wst04-VHDL20_DWEG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 246034
wst04-VHDL20_DWEG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246925
wst04-VHDL20_DWEG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249247
wst04-VHDL20_DWEG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 248752
wst04-VHDL20_DWEG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 249508
wst04-VHDL20_DWEG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 249956
wst04-VHDL20_DWEH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 244774
wst04-VHDL20_DWEH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 244967
wst04-VHDL20_DWEH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 244472
wst04-VHDL20_DWEH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 246072
wst04-VHDL20_DWEH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:12 249672
wst04-VHDL20_DWEH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 249798
wst04-VHDL20_DWEH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 249673
wst04-VHDL20_DWEH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 250386
wst04-VHDL20_DWEI_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 354331
wst04-VHDL20_DWEI_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 354462
wst04-VHDL20_DWEI_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 353953
wst04-VHDL20_DWEI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:12 354320
wst04-VHDL20_DWEI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 360512
wst04-VHDL20_DWEI_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 360619
wst04-VHDL20_DWEI_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 360310
wst04-VHDL20_DWEI_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 361027
wst04-VHDL20_DWHG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:45:17 349681
wst04-VHDL20_DWHG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:45:42 348764
wst04-VHDL20_DWHG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 348538
wst04-VHDL20_DWHG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 351740
wst04-VHDL20_DWHG_180800_COR-2606180800-omedes-..> 18-Jun-2026 11:07:07 363371
wst04-VHDL20_DWHG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 361512
wst04-VHDL20_DWHG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:45:14 363182
wst04-VHDL20_DWHG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 363215
wst04-VHDL20_DWHG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:45:12 364052
wst04-VHDL20_DWHH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:45:17 330835
wst04-VHDL20_DWHH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:45:42 330217
wst04-VHDL20_DWHH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 222334
wst04-VHDL20_DWHH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:45:17 331404
wst04-VHDL20_DWHH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:45:11 339012
wst04-VHDL20_DWHH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:45:14 340162
wst04-VHDL20_DWHH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 228387
wst04-VHDL20_DWHH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:45:12 341787
wst04-VHDL20_DWLG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 341579
wst04-VHDL20_DWLG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 341653
wst04-VHDL20_DWLG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 341306
wst04-VHDL20_DWLG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 342645
wst04-VHDL20_DWLG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348845
wst04-VHDL20_DWLG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 348841
wst04-VHDL20_DWLG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 348973
wst04-VHDL20_DWLG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 350185
wst04-VHDL20_DWLH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 340162
wst04-VHDL20_DWLH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 340257
wst04-VHDL20_DWLH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 339903
wst04-VHDL20_DWLH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 341229
wst04-VHDL20_DWLH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 348533
wst04-VHDL20_DWLH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 347587
wst04-VHDL20_DWLH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 347716
wst04-VHDL20_DWLH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 348956
wst04-VHDL20_DWLI_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 345243
wst04-VHDL20_DWLI_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:27 345370
wst04-VHDL20_DWLI_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:42 344983
wst04-VHDL20_DWLI_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 390905
wst04-VHDL20_DWLI_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:28 354450
wst04-VHDL20_DWLI_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 353539
wst04-VHDL20_DWLI_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:41 353653
wst04-VHDL20_DWLI_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 399449
wst04-VHDL20_DWMO_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:17 356000
wst04-VHDL20_DWMO_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:20 467596
wst04-VHDL20_DWMO_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 467607
wst04-VHDL20_DWMO_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:17 467840
wst04-VHDL20_DWMO_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 366447
wst04-VHDL20_DWMO_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 482435
wst04-VHDL20_DWMO_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 482327
wst04-VHDL20_DWMO_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 482491
wst04-VHDL20_DWMP_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:17 467440
wst04-VHDL20_DWMP_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:20 578377
wst04-VHDL20_DWMP_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:16 579190
wst04-VHDL20_DWMP_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:21 467930
wst04-VHDL20_DWMP_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 490164
wst04-VHDL20_DWMP_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:18 600461
wst04-VHDL20_DWMP_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:17 599678
wst04-VHDL20_DWMP_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 490297
wst04-VHDL20_DWPG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:29 345097
wst04-VHDL20_DWPG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 244194
wst04-VHDL20_DWPG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:32 344404
wst04-VHDL20_DWPG_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:47 390307
wst04-VHDL20_DWPG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 356284
wst04-VHDL20_DWPG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:25 247234
wst04-VHDL20_DWPG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:31 355761
wst04-VHDL20_DWPG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:53 401620
wst04-VHDL20_DWPH_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:31:22 239793
wst04-VHDL20_DWPH_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:23 239884
wst04-VHDL20_DWPH_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:32 239131
wst04-VHDL20_DWPH_180800-2606180800-omedes--0.pdf 18-Jun-2026 08:30:42 239610
wst04-VHDL20_DWPH_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:31:24 247781
wst04-VHDL20_DWPH_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:20 247665
wst04-VHDL20_DWPH_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:31 247815
wst04-VHDL20_DWPH_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:42 247908
wst04-VHDL20_DWSG_171800-2606171800-omedes--0.pdf 17-Jun-2026 18:30:13 351338
wst04-VHDL20_DWSG_180200-2606180200-omedes--0.pdf 18-Jun-2026 02:30:14 351346
wst04-VHDL20_DWSG_180400-2606180400-omedes--0.pdf 18-Jun-2026 05:00:12 351778
wst04-VHDL20_DWSG_180800-2606180800-omedes--0.pdf 18-Jun-2026 14:46:21 365010
wst04-VHDL20_DWSG_181800-2606181800-omedes--0.pdf 18-Jun-2026 18:30:16 364914
wst04-VHDL20_DWSG_190200-2606190200-omedes--0.pdf 19-Jun-2026 02:30:11 364114
wst04-VHDL20_DWSG_190400-2606190400-omedes--0.pdf 19-Jun-2026 05:00:11 364112
wst04-VHDL20_DWSG_190800-2606190800-omedes--0.pdf 19-Jun-2026 08:30:29 365377