Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Jun-2026 14:19:49 3430
FPDL13_DWMZ_240600 24-Jun-2026 09:39:15 2237
SXDL31_DWAV_230800 23-Jun-2026 07:23:35 6156
SXDL31_DWAV_231800 23-Jun-2026 16:12:47 2370
SXDL31_DWAV_240800 24-Jun-2026 07:43:54 10568
SXDL31_DWAV_241800 24-Jun-2026 16:34:49 7014
SXDL31_DWAV_LATEST 24-Jun-2026 16:34:49 7014
SXDL33_DWAV_230000 23-Jun-2026 10:49:59 16537
SXDL33_DWAV_240000 24-Jun-2026 09:36:43 11093
SXDL33_DWAV_LATEST 24-Jun-2026 09:36:43 11093
ber01-FWDL39_DWMS_231200-2606231200-dsw--0-ia5 23-Jun-2026 10:23:47 968
ber01-FWDL39_DWMS_241200-2606241200-dsw--0-ia5 24-Jun-2026 12:29:11 1761
ber01-FWDL39_DWMS_241200_COR-2606241200-dsw--0-ia5 24-Jun-2026 12:20:42 1765
ber01-VHDL13_DWEG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:28:17 2331
ber01-VHDL13_DWEG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:28:17 2497
ber01-VHDL13_DWEH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:28:11 2489
ber01-VHDL13_DWEH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:28:17 2559
ber01-VHDL13_DWEI_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:28:17 2285
ber01-VHDL13_DWEI_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:28:17 2617
ber01-VHDL13_DWHG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 2296
ber01-VHDL13_DWHG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2135
ber01-VHDL13_DWHH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 2251
ber01-VHDL13_DWHH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2370
ber01-VHDL13_DWLG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 1976
ber01-VHDL13_DWLG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 1828
ber01-VHDL13_DWLH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 2019
ber01-VHDL13_DWLH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 1883
ber01-VHDL13_DWLI_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 2066
ber01-VHDL13_DWLI_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 1966
ber01-VHDL13_DWMO_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 2358
ber01-VHDL13_DWMO_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2845
ber01-VHDL13_DWMP_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 2846
ber01-VHDL13_DWMP_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2820
ber01-VHDL13_DWMP_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 08:36:44 2923
ber01-VHDL13_DWOG_230300-2606230300-dsw--0-ia5 23-Jun-2026 03:00:02 3391
ber01-VHDL13_DWOG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 3465
ber01-VHDL13_DWOG_231700-2606231700-dsw--0-ia5 23-Jun-2026 18:00:03 2949
ber01-VHDL13_DWOG_240300-2606240300-dsw--0-ia5 24-Jun-2026 03:00:03 3255
ber01-VHDL13_DWOG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 3014
ber01-VHDL13_DWOG_241700-2606241700-dsw--0-ia5 24-Jun-2026 18:00:00 2956
ber01-VHDL13_DWON_230057-2606230057-dsw--0-ia5 23-Jun-2026 00:57:37 3245
ber01-VHDL13_DWON_230238-2606230238-dsw--0-ia5 23-Jun-2026 02:38:27 3245
ber01-VHDL13_DWON_230523-2606230523-dsw--0-ia5 23-Jun-2026 05:23:07 3235
ber01-VHDL13_DWON_230617-2606230617-dsw--0-ia5 23-Jun-2026 06:17:32 3274
ber01-VHDL13_DWON_230854-2606230854-dsw--0-ia5 23-Jun-2026 08:54:53 3274
ber01-VHDL13_DWON_231501-2606231501-dsw--0-ia5 23-Jun-2026 15:01:32 2995
ber01-VHDL13_DWON_231616-2606231616-dsw--0-ia5 23-Jun-2026 16:16:27 2619
ber01-VHDL13_DWON_231726-2606231726-dsw--0-ia5 23-Jun-2026 17:26:37 2619
ber01-VHDL13_DWON_240107-2606240107-dsw--0-ia5 24-Jun-2026 01:07:27 3259
ber01-VHDL13_DWON_240246-2606240246-dsw--0-ia5 24-Jun-2026 02:46:37 3206
ber01-VHDL13_DWON_240306-2606240306-dsw--0-ia5 24-Jun-2026 03:06:39 2992
ber01-VHDL13_DWON_240514-2606240514-dsw--0-ia5 24-Jun-2026 05:14:57 3258
ber01-VHDL13_DWON_240602-2606240602-dsw--0-ia5 24-Jun-2026 06:02:07 3191
ber01-VHDL13_DWON_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:00:57 3198
ber01-VHDL13_DWON_240941-2606240941-dsw--0-ia5 24-Jun-2026 09:41:25 3198
ber01-VHDL13_DWON_241442-2606241442-dsw--0-ia5 24-Jun-2026 14:42:59 3027
ber01-VHDL13_DWON_241656-2606241656-dsw--0-ia5 24-Jun-2026 16:56:17 2810
ber01-VHDL13_DWON_241852-2606241852-dsw--0-ia5 24-Jun-2026 18:52:32 2886
ber01-VHDL13_DWON_241900-2606241900-dsw--0-ia5 24-Jun-2026 19:00:52 2886
ber01-VHDL13_DWON_241901-2606241901-dsw--0-ia5 24-Jun-2026 19:01:21 2886
ber01-VHDL13_DWON_242144-2606242144-dsw--0-ia5 24-Jun-2026 21:45:03 2908
ber01-VHDL13_DWPG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 1993
ber01-VHDL13_DWPG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2222
ber01-VHDL13_DWPH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 2081
ber01-VHDL13_DWPH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 2111
ber01-VHDL13_DWSG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 3330
ber01-VHDL13_DWSG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 3082
ber01-VHDL13_DWSG_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 16:58:46 2898
ber01-VHDL17_DWOG_231200-2606231200-dsw--0-ia5 23-Jun-2026 10:48:41 3603
ber01-VHDL17_DWOG_241200-2606241200-dsw--0-ia5 24-Jun-2026 11:42:06 2953
swis2-VHDL20_DWEG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1018
swis2-VHDL20_DWEG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1018
swis2-VHDL20_DWEG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 1370
swis2-VHDL20_DWEG_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:02 1319
swis2-VHDL20_DWEG_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:02 668
swis2-VHDL20_DWEG_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:01:16 762
swis2-VHDL20_DWEG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 1174
swis2-VHDL20_DWEG_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 924
swis2-VHDL20_DWEH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1028
swis2-VHDL20_DWEH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1028
swis2-VHDL20_DWEH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 1471
swis2-VHDL20_DWEH_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:02 1329
swis2-VHDL20_DWEH_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:02 682
swis2-VHDL20_DWEH_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:01:16 777
swis2-VHDL20_DWEH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 1167
swis2-VHDL20_DWEH_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 1448
swis2-VHDL20_DWEI_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1003
swis2-VHDL20_DWEI_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1003
swis2-VHDL20_DWEI_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:11 1450
swis2-VHDL20_DWEI_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:02 1325
swis2-VHDL20_DWEI_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:02 690
swis2-VHDL20_DWEI_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:01:16 784
swis2-VHDL20_DWEI_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 1180
swis2-VHDL20_DWEI_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 1426
swis2-VHDL20_DWHG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:45:13 987
swis2-VHDL20_DWHG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 980
swis2-VHDL20_DWHG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:45:05 1044
swis2-VHDL20_DWHG_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:45:09 1118
swis2-VHDL20_DWHG_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:45:02 918
swis2-VHDL20_DWHG_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:16 919
swis2-VHDL20_DWHG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:45:05 1020
swis2-VHDL20_DWHG_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:45:07 1452
swis2-VHDL20_DWHH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:45:13 992
swis2-VHDL20_DWHH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 988
swis2-VHDL20_DWHH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:45:05 1080
swis2-VHDL20_DWHH_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:45:09 1130
swis2-VHDL20_DWHH_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:45:02 936
swis2-VHDL20_DWHH_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:16 936
swis2-VHDL20_DWHH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:45:05 1026
swis2-VHDL20_DWHH_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:45:07 1508
swis2-VHDL20_DWLG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 882
swis2-VHDL20_DWLG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 881
swis2-VHDL20_DWLG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:23 1014
swis2-VHDL20_DWLG_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:31:03 903
swis2-VHDL20_DWLG_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:24 785
swis2-VHDL20_DWLG_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:12 762
swis2-VHDL20_DWLG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:22 1156
swis2-VHDL20_DWLG_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:31:05 1161
swis2-VHDL20_DWLH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 886
swis2-VHDL20_DWLH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 908
swis2-VHDL20_DWLH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:23 1041
swis2-VHDL20_DWLH_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:31:03 928
swis2-VHDL20_DWLH_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:24 792
swis2-VHDL20_DWLH_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:12 769
swis2-VHDL20_DWLH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:22 1147
swis2-VHDL20_DWLH_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:31:05 1168
swis2-VHDL20_DWLI_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 917
swis2-VHDL20_DWLI_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 916
swis2-VHDL20_DWLI_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:23 1068
swis2-VHDL20_DWLI_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:31:03 923
swis2-VHDL20_DWLI_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:24 787
swis2-VHDL20_DWLI_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:12 764
swis2-VHDL20_DWLI_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:22 892
swis2-VHDL20_DWLI_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:31:05 1163
swis2-VHDL20_DWMO_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1452
swis2-VHDL20_DWMO_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:02 1426
swis2-VHDL20_DWMO_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 972
swis2-VHDL20_DWMO_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:02 1536
swis2-VHDL20_DWMO_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:10 1171
swis2-VHDL20_DWMO_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:02 1234
swis2-VHDL20_DWMO_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 1428
swis2-VHDL20_DWMO_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 1314
swis2-VHDL20_DWMP_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1328
swis2-VHDL20_DWMP_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:02 1293
swis2-VHDL20_DWMP_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 1380
swis2-VHDL20_DWMP_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:02 1608
swis2-VHDL20_DWMP_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:10 1207
swis2-VHDL20_DWMP_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:02 1269
swis2-VHDL20_DWMP_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:07 1549
swis2-VHDL20_DWMP_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 08:36:44 3199
swis2-VHDL20_DWMP_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 1397
swis2-VHDL20_DWPG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 898
swis2-VHDL20_DWPG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 923
swis2-VHDL20_DWPG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:23 1056
swis2-VHDL20_DWPG_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:31:03 1192
swis2-VHDL20_DWPG_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:24 1125
swis2-VHDL20_DWPG_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:12 1095
swis2-VHDL20_DWPG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:22 1245
swis2-VHDL20_DWPG_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:31:05 1181
swis2-VHDL20_DWPH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 827
swis2-VHDL20_DWPH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 892
swis2-VHDL20_DWPH_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:23 1039
swis2-VHDL20_DWPH_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:31:03 941
swis2-VHDL20_DWPH_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:24 874
swis2-VHDL20_DWPH_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:12 850
swis2-VHDL20_DWPH_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:22 1258
swis2-VHDL20_DWPH_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:31:05 1210
swis2-VHDL20_DWSG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1432
swis2-VHDL20_DWSG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 1429
swis2-VHDL20_DWSG_230800-2606230800-dsw--0-ia5 23-Jun-2026 08:30:01 1572
swis2-VHDL20_DWSG_231800-2606231800-dsw--0-ia5 23-Jun-2026 18:30:08 1175
swis2-VHDL20_DWSG_240200-2606240200-dsw--0-ia5 24-Jun-2026 02:30:02 970
swis2-VHDL20_DWSG_240400-2606240400-dsw--0-ia5 24-Jun-2026 05:00:16 1106
swis2-VHDL20_DWSG_240800-2606240800-dsw--0-ia5 24-Jun-2026 08:30:01 1371
swis2-VHDL20_DWSG_240800_COR-2606240800-dsw--0-ia5 24-Jun-2026 16:58:46 1603
swis2-VHDL20_DWSG_241800-2606241800-dsw--0-ia5 24-Jun-2026 18:30:02 1507
wst04-VHDL20_DWEG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 245146
wst04-VHDL20_DWEG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 244971
wst04-VHDL20_DWEG_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:11 246784
wst04-VHDL20_DWEG_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:11 241203
wst04-VHDL20_DWEG_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 238490
wst04-VHDL20_DWEG_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:12 238635
wst04-VHDL20_DWEG_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:12 240452
wst04-VHDL20_DWEG_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:14 236055
wst04-VHDL20_DWEH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 245701
wst04-VHDL20_DWEH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 245494
wst04-VHDL20_DWEH_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:11 247488
wst04-VHDL20_DWEH_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:11 244088
wst04-VHDL20_DWEH_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 241606
wst04-VHDL20_DWEH_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:12 242035
wst04-VHDL20_DWEH_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:12 243900
wst04-VHDL20_DWEH_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:14 238841
wst04-VHDL20_DWEI_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 350787
wst04-VHDL20_DWEI_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 350577
wst04-VHDL20_DWEI_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:16 352685
wst04-VHDL20_DWEI_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:20 345068
wst04-VHDL20_DWEI_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 342240
wst04-VHDL20_DWEI_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:12 342326
wst04-VHDL20_DWEI_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:20 344308
wst04-VHDL20_DWEI_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:16 337069
wst04-VHDL20_DWHG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:45:13 353402
wst04-VHDL20_DWHG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 353413
wst04-VHDL20_DWHG_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:45:24 353959
wst04-VHDL20_DWHG_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:45:11 351035
wst04-VHDL20_DWHG_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:45:12 349671
wst04-VHDL20_DWHG_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:16 349676
wst04-VHDL20_DWHG_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:45:14 351185
wst04-VHDL20_DWHG_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:45:21 343694
wst04-VHDL20_DWHH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:45:13 322416
wst04-VHDL20_DWHH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 218645
wst04-VHDL20_DWHH_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:45:24 321866
wst04-VHDL20_DWHH_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:45:11 332281
wst04-VHDL20_DWHH_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:45:12 331529
wst04-VHDL20_DWHH_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:16 225521
wst04-VHDL20_DWHH_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:45:14 332418
wst04-VHDL20_DWHH_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:45:21 328586
wst04-VHDL20_DWLG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 348240
wst04-VHDL20_DWLG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 347503
wst04-VHDL20_DWLG_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:42 347588
wst04-VHDL20_DWLG_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:31:22 340565
wst04-VHDL20_DWLG_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 340882
wst04-VHDL20_DWLG_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:42 340675
wst04-VHDL20_DWLG_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:43 342164
wst04-VHDL20_DWLG_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:31:21 332838
wst04-VHDL20_DWLH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:26 344859
wst04-VHDL20_DWLH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 344070
wst04-VHDL20_DWLH_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:42 344173
wst04-VHDL20_DWLH_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:31:22 346134
wst04-VHDL20_DWLH_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:27 345861
wst04-VHDL20_DWLH_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:42 345668
wst04-VHDL20_DWLH_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:43 347160
wst04-VHDL20_DWLH_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:31:21 334693
wst04-VHDL20_DWLI_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 352278
wst04-VHDL20_DWLI_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 351494
wst04-VHDL20_DWLI_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:46 396806
wst04-VHDL20_DWLI_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:31:22 339882
wst04-VHDL20_DWLI_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 339628
wst04-VHDL20_DWLI_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:42 339406
wst04-VHDL20_DWLI_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:43 384701
wst04-VHDL20_DWLI_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:31:29 339491
wst04-VHDL20_DWMO_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 479183
wst04-VHDL20_DWMO_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 479365
wst04-VHDL20_DWMO_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:16 477401
wst04-VHDL20_DWMO_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:20 354045
wst04-VHDL20_DWMO_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 461722
wst04-VHDL20_DWMO_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:16 461631
wst04-VHDL20_DWMO_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:22 461523
wst04-VHDL20_DWMO_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:16 346036
wst04-VHDL20_DWMP_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 576731
wst04-VHDL20_DWMP_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 576851
wst04-VHDL20_DWMP_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:23 470539
wst04-VHDL20_DWMP_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:20 471479
wst04-VHDL20_DWMP_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 576911
wst04-VHDL20_DWMP_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:16 576743
wst04-VHDL20_DWMP_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:22 471287
wst04-VHDL20_DWMP_240800_COR-2606240800-omedes-..> 24-Jun-2026 08:36:59 581275
wst04-VHDL20_DWMP_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:16 454493
wst04-VHDL20_DWPG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 246122
wst04-VHDL20_DWPG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:30 349809
wst04-VHDL20_DWPG_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:42 394445
wst04-VHDL20_DWPG_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:31:22 355515
wst04-VHDL20_DWPG_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 248508
wst04-VHDL20_DWPG_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:32 355094
wst04-VHDL20_DWPG_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:48 400367
wst04-VHDL20_DWPG_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:31:21 340426
wst04-VHDL20_DWPH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 239856
wst04-VHDL20_DWPH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:30 239260
wst04-VHDL20_DWPH_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:42 239607
wst04-VHDL20_DWPH_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:31:22 242058
wst04-VHDL20_DWPH_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 241963
wst04-VHDL20_DWPH_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:32 242260
wst04-VHDL20_DWPH_240800-2606240800-omedes--0.pdf 24-Jun-2026 08:30:43 242755
wst04-VHDL20_DWPH_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:31:21 239792
wst04-VHDL20_DWSG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 353553
wst04-VHDL20_DWSG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 353571
wst04-VHDL20_DWSG_230800-2606230800-omedes--0.pdf 23-Jun-2026 08:30:16 354447
wst04-VHDL20_DWSG_231800-2606231800-omedes--0.pdf 23-Jun-2026 18:30:20 345218
wst04-VHDL20_DWSG_240200-2606240200-omedes--0.pdf 24-Jun-2026 02:30:24 344641
wst04-VHDL20_DWSG_240400-2606240400-omedes--0.pdf 24-Jun-2026 05:00:12 345633
wst04-VHDL20_DWSG_240800-2606240800-omedes--0.pdf 24-Jun-2026 16:58:56 337864
wst04-VHDL20_DWSG_241800-2606241800-omedes--0.pdf 24-Jun-2026 18:30:11 337643