Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-Sep-2026 10:05:23 2415
FPDL13_DWMZ_030600 03-Sep-2026 10:33:09 2445
SXDL31_DWAV_011800 01-Sep-2026 16:44:03 9289
SXDL31_DWAV_020800 02-Sep-2026 07:29:05 8737
SXDL31_DWAV_021800 02-Sep-2026 16:47:02 8123
SXDL31_DWAV_030800 03-Sep-2026 07:55:18 8971
SXDL31_DWAV_LATEST 03-Sep-2026 07:55:18 8971
SXDL33_DWAV_020000 02-Sep-2026 10:03:59 11360
SXDL33_DWAV_030000 03-Sep-2026 11:04:33 13705
SXDL33_DWAV_LATEST 03-Sep-2026 11:04:33 13705
ber01-FWDL39_DWMS_021200-2609021200-dsw--0-ia5 02-Sep-2026 11:02:53 2246
ber01-FWDL39_DWMS_031200-2609031200-dsw--0-ia5 03-Sep-2026 11:54:28 1438
ber01-VHDL13_DWEG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:28:18 3036
ber01-VHDL13_DWEG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:28:18 3883
ber01-VHDL13_DWEH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:28:18 2768
ber01-VHDL13_DWEH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:28:18 3618
ber01-VHDL13_DWEI_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:28:18 2653
ber01-VHDL13_DWEI_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:28:18 3112
ber01-VHDL13_DWHG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:09 4298
ber01-VHDL13_DWHG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 4866
ber01-VHDL13_DWHH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:09 4040
ber01-VHDL13_DWHH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 4262
ber01-VHDL13_DWLG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2476
ber01-VHDL13_DWLG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 3675
ber01-VHDL13_DWLH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2910
ber01-VHDL13_DWLH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 3628
ber01-VHDL13_DWLI_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2378
ber01-VHDL13_DWLI_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 3104
ber01-VHDL13_DWLI_030800_COR-2609030800-dsw--0-ia5 03-Sep-2026 11:07:08 3224
ber01-VHDL13_DWMO_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 3064
ber01-VHDL13_DWMO_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:15 3406
ber01-VHDL13_DWMP_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2656
ber01-VHDL13_DWMP_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 3281
ber01-VHDL13_DWOG_011700-2609011700-dsw--0-ia5 01-Sep-2026 18:00:03 3967
ber01-VHDL13_DWOG_020300-2609020300-dsw--0-ia5 02-Sep-2026 03:00:08 3919
ber01-VHDL13_DWOG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 4389
ber01-VHDL13_DWOG_021700-2609021700-dsw--0-ia5 02-Sep-2026 18:00:09 3797
ber01-VHDL13_DWOG_030300-2609030300-dsw--0-ia5 03-Sep-2026 03:00:21 4170
ber01-VHDL13_DWOG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 4964
ber01-VHDL13_DWON_011707-2609011707-dsw--0-ia5 01-Sep-2026 17:07:59 3684
ber01-VHDL13_DWON_012131-2609012131-dsw--0-ia5 01-Sep-2026 21:31:37 3703
ber01-VHDL13_DWON_020132-2609020132-dsw--0-ia5 02-Sep-2026 01:32:37 3596
ber01-VHDL13_DWON_020241-2609020241-dsw--0-ia5 02-Sep-2026 02:41:48 3411
ber01-VHDL13_DWON_020445-2609020445-dsw--0-ia5 02-Sep-2026 04:46:13 3699
ber01-VHDL13_DWON_020530-2609020530-dsw--0-ia5 02-Sep-2026 05:31:04 3972
ber01-VHDL13_DWON_020554-2609020554-dsw--0-ia5 02-Sep-2026 05:54:23 3959
ber01-VHDL13_DWON_020630-2609020630-dsw--0-ia5 02-Sep-2026 06:30:59 3959
ber01-VHDL13_DWON_020758-2609020758-dsw--0-ia5 02-Sep-2026 07:58:43 3959
ber01-VHDL13_DWON_021522-2609021522-dsw--0-ia5 02-Sep-2026 15:22:39 3958
ber01-VHDL13_DWON_021649-2609021649-dsw--0-ia5 02-Sep-2026 16:49:18 3696
ber01-VHDL13_DWON_021658-2609021658-dsw--0-ia5 02-Sep-2026 16:58:58 3711
ber01-VHDL13_DWON_022142-2609022142-dsw--0-ia5 02-Sep-2026 21:42:14 3714
ber01-VHDL13_DWON_030125-2609030125-dsw--0-ia5 03-Sep-2026 01:25:28 3671
ber01-VHDL13_DWON_030225-2609030225-dsw--0-ia5 03-Sep-2026 02:25:58 3665
ber01-VHDL13_DWON_030529-2609030529-dsw--0-ia5 03-Sep-2026 05:29:43 3944
ber01-VHDL13_DWON_030549-2609030549-dsw--0-ia5 03-Sep-2026 05:49:46 3952
ber01-VHDL13_DWON_030815-2609030815-dsw--0-ia5 03-Sep-2026 08:15:54 4002
ber01-VHDL13_DWPG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2919
ber01-VHDL13_DWPG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 3238
ber01-VHDL13_DWPH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 3615
ber01-VHDL13_DWPH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 3221
ber01-VHDL13_DWSG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 2796
ber01-VHDL13_DWSG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 3613
ber01-VHDL17_DWOG_021200-2609021200-dsw--0-ia5 02-Sep-2026 11:38:42 4042
ber01-VHDL17_DWOG_031200-2609031200-dsw--0-ia5 03-Sep-2026 11:23:23 2746
swis2-VHDL20_DWEG_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:09 1465
swis2-VHDL20_DWEG_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:14 953
swis2-VHDL20_DWEG_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:01:29 916
swis2-VHDL20_DWEG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1283
swis2-VHDL20_DWEG_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:12 1884
swis2-VHDL20_DWEG_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1595
swis2-VHDL20_DWEG_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:01:19 1582
swis2-VHDL20_DWEG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 1952
swis2-VHDL20_DWEH_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:09 1410
swis2-VHDL20_DWEH_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:14 926
swis2-VHDL20_DWEH_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:01:29 881
swis2-VHDL20_DWEH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1211
swis2-VHDL20_DWEH_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:12 1819
swis2-VHDL20_DWEH_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1590
swis2-VHDL20_DWEH_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:01:19 1585
swis2-VHDL20_DWEH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 1916
swis2-VHDL20_DWEI_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:09 1186
swis2-VHDL20_DWEI_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:14 997
swis2-VHDL20_DWEI_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:01:29 883
swis2-VHDL20_DWEI_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1064
swis2-VHDL20_DWEI_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:12 1525
swis2-VHDL20_DWEI_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1280
swis2-VHDL20_DWEI_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:01:19 1269
swis2-VHDL20_DWEI_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:07 1477
swis2-VHDL20_DWHG_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:45:10 2023
swis2-VHDL20_DWHG_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:45:51 1635
swis2-VHDL20_DWHG_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:19 1632
swis2-VHDL20_DWHG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:45:09 2756
swis2-VHDL20_DWHG_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:45:18 2483
swis2-VHDL20_DWHG_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:45:36 2184
swis2-VHDL20_DWHG_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:19 2182
swis2-VHDL20_DWHG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:45:58 2910
swis2-VHDL20_DWHH_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:45:10 1969
swis2-VHDL20_DWHH_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:45:51 1508
swis2-VHDL20_DWHH_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:19 1508
swis2-VHDL20_DWHH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:45:09 2353
swis2-VHDL20_DWHH_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:45:18 2326
swis2-VHDL20_DWHH_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:45:36 2186
swis2-VHDL20_DWHH_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:19 2191
swis2-VHDL20_DWHH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:45:58 2478
swis2-VHDL20_DWLG_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:31:07 1029
swis2-VHDL20_DWLG_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:26 933
swis2-VHDL20_DWLG_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:13 854
swis2-VHDL20_DWLG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:31 1039
swis2-VHDL20_DWLG_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:31:10 1219
swis2-VHDL20_DWLG_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:26 1104
swis2-VHDL20_DWLG_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:13 1417
swis2-VHDL20_DWLG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:31 1773
swis2-VHDL20_DWLH_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:31:07 1156
swis2-VHDL20_DWLH_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:26 1027
swis2-VHDL20_DWLH_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:13 1033
swis2-VHDL20_DWLH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:31 1405
swis2-VHDL20_DWLH_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:31:10 1362
swis2-VHDL20_DWLH_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:26 1261
swis2-VHDL20_DWLH_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:13 1767
swis2-VHDL20_DWLH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:31 1874
swis2-VHDL20_DWLI_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:31:07 981
swis2-VHDL20_DWLI_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:26 936
swis2-VHDL20_DWLI_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:13 844
swis2-VHDL20_DWLI_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:31 956
swis2-VHDL20_DWLI_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:31:10 1103
swis2-VHDL20_DWLI_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:26 1015
swis2-VHDL20_DWLI_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:13 1381
swis2-VHDL20_DWLI_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:31 1555
swis2-VHDL20_DWLI_030800_COR-2609030800-dsw--0-ia5 03-Sep-2026 11:07:59 1675
swis2-VHDL20_DWMO_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:09 1074
swis2-VHDL20_DWMO_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:03 962
swis2-VHDL20_DWMO_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:03 963
swis2-VHDL20_DWMO_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1276
swis2-VHDL20_DWMO_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:12 1366
swis2-VHDL20_DWMO_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1114
swis2-VHDL20_DWMO_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:09 1370
swis2-VHDL20_DWMO_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 1632
swis2-VHDL20_DWMP_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:09 913
swis2-VHDL20_DWMP_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:03 962
swis2-VHDL20_DWMP_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:03 962
swis2-VHDL20_DWMP_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1252
swis2-VHDL20_DWMP_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:12 1508
swis2-VHDL20_DWMP_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1221
swis2-VHDL20_DWMP_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:09 1167
swis2-VHDL20_DWMP_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 1487
swis2-VHDL20_DWPG_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:31:07 1121
swis2-VHDL20_DWPG_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:26 995
swis2-VHDL20_DWPG_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:13 1160
swis2-VHDL20_DWPG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:31 1438
swis2-VHDL20_DWPG_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:31:10 1401
swis2-VHDL20_DWPG_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:26 1280
swis2-VHDL20_DWPG_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:13 1683
swis2-VHDL20_DWPG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:31 1873
swis2-VHDL20_DWPH_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:31:07 1323
swis2-VHDL20_DWPH_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:26 1216
swis2-VHDL20_DWPH_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:13 1495
swis2-VHDL20_DWPH_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:31 1734
swis2-VHDL20_DWPH_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:31:10 1494
swis2-VHDL20_DWPH_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:26 1293
swis2-VHDL20_DWPH_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:13 1507
swis2-VHDL20_DWPH_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:31 1763
swis2-VHDL20_DWSG_011800-2609011800-dsw--0-ia5 01-Sep-2026 18:30:03 1032
swis2-VHDL20_DWSG_020200-2609020200-dsw--0-ia5 02-Sep-2026 02:30:03 971
swis2-VHDL20_DWSG_020400-2609020400-dsw--0-ia5 02-Sep-2026 05:00:19 969
swis2-VHDL20_DWSG_020800-2609020800-dsw--0-ia5 02-Sep-2026 08:30:03 1126
swis2-VHDL20_DWSG_021800-2609021800-dsw--0-ia5 02-Sep-2026 18:30:04 1060
swis2-VHDL20_DWSG_030200-2609030200-dsw--0-ia5 03-Sep-2026 02:30:07 1027
swis2-VHDL20_DWSG_030400-2609030400-dsw--0-ia5 03-Sep-2026 05:00:19 1387
swis2-VHDL20_DWSG_030800-2609030800-dsw--0-ia5 03-Sep-2026 08:30:14 1503
wst04-VHDL20_DWEG_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:13 240897
wst04-VHDL20_DWEG_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:16 238828
wst04-VHDL20_DWEG_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:13 239775
wst04-VHDL20_DWEG_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:15 241223
wst04-VHDL20_DWEG_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:20 246710
wst04-VHDL20_DWEG_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:16 245370
wst04-VHDL20_DWEG_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:13 245429
wst04-VHDL20_DWEG_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:15 246632
wst04-VHDL20_DWEH_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:17 240582
wst04-VHDL20_DWEH_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:16 238835
wst04-VHDL20_DWEH_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:13 240005
wst04-VHDL20_DWEH_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:15 241496
wst04-VHDL20_DWEH_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:15 247952
wst04-VHDL20_DWEH_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:16 247217
wst04-VHDL20_DWEH_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:13 247256
wst04-VHDL20_DWEH_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:15 248462
wst04-VHDL20_DWEI_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:17 340640
wst04-VHDL20_DWEI_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:16 340284
wst04-VHDL20_DWEI_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:13 341109
wst04-VHDL20_DWEI_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:19 341514
wst04-VHDL20_DWEI_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:20 351130
wst04-VHDL20_DWEI_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:16 349167
wst04-VHDL20_DWEI_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:19 349601
wst04-VHDL20_DWEI_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:15 350828
wst04-VHDL20_DWHG_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:45:24 349185
wst04-VHDL20_DWHG_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:45:51 347043
wst04-VHDL20_DWHG_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:19 346835
wst04-VHDL20_DWHG_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:46:21 350849
wst04-VHDL20_DWHG_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:45:20 349647
wst04-VHDL20_DWHG_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:45:36 348254
wst04-VHDL20_DWHG_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:19 348735
wst04-VHDL20_DWHG_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:45:58 349656
wst04-VHDL20_DWHH_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:45:24 338564
wst04-VHDL20_DWHH_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:45:51 337226
wst04-VHDL20_DWHH_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:19 234849
wst04-VHDL20_DWHH_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:46:21 339177
wst04-VHDL20_DWHH_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:45:20 348238
wst04-VHDL20_DWHH_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:45:36 348061
wst04-VHDL20_DWHH_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:19 240077
wst04-VHDL20_DWHH_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:45:58 348158
wst04-VHDL20_DWLG_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:31:24 337795
wst04-VHDL20_DWLG_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:26 337501
wst04-VHDL20_DWLG_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:43 337273
wst04-VHDL20_DWLG_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:59 337637
wst04-VHDL20_DWLG_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:31:25 339270
wst04-VHDL20_DWLG_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:26 339172
wst04-VHDL20_DWLG_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:43 339051
wst04-VHDL20_DWLG_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:43 340667
wst04-VHDL20_DWLH_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:31:24 340511
wst04-VHDL20_DWLH_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:26 340134
wst04-VHDL20_DWLH_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:43 339995
wst04-VHDL20_DWLH_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:59 341596
wst04-VHDL20_DWLH_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:31:25 341629
wst04-VHDL20_DWLH_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:26 341539
wst04-VHDL20_DWLH_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:43 341536
wst04-VHDL20_DWLH_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:43 343035
wst04-VHDL20_DWLI_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:31:24 337177
wst04-VHDL20_DWLI_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:26 336895
wst04-VHDL20_DWLI_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:43 336621
wst04-VHDL20_DWLI_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:59 381531
wst04-VHDL20_DWLI_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:31:25 341825
wst04-VHDL20_DWLI_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:26 341740
wst04-VHDL20_DWLI_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:43 341645
wst04-VHDL20_DWLI_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:43 387730
wst04-VHDL20_DWMO_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:17 346946
wst04-VHDL20_DWMO_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:18 450431
wst04-VHDL20_DWMO_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:19 450306
wst04-VHDL20_DWMO_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:19 451043
wst04-VHDL20_DWMO_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:20 353506
wst04-VHDL20_DWMO_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:16 455811
wst04-VHDL20_DWMO_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:13 457092
wst04-VHDL20_DWMO_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:31 456954
wst04-VHDL20_DWMP_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:17 444466
wst04-VHDL20_DWMP_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:18 542995
wst04-VHDL20_DWMP_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:19 542907
wst04-VHDL20_DWMP_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:23 446643
wst04-VHDL20_DWMP_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:20 451298
wst04-VHDL20_DWMP_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:20 548325
wst04-VHDL20_DWMP_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:19 548470
wst04-VHDL20_DWMP_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:31 451274
wst04-VHDL20_DWPG_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:31:28 348381
wst04-VHDL20_DWPG_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:26 242522
wst04-VHDL20_DWPG_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:33 348030
wst04-VHDL20_DWPG_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:59 394266
wst04-VHDL20_DWPG_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:31:32 347345
wst04-VHDL20_DWPG_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:28 243740
wst04-VHDL20_DWPG_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:33 346934
wst04-VHDL20_DWPG_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:43 392534
wst04-VHDL20_DWPH_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:31:24 244176
wst04-VHDL20_DWPH_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:26 243743
wst04-VHDL20_DWPH_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:33 244790
wst04-VHDL20_DWPH_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:59 245050
wst04-VHDL20_DWPH_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:31:25 244502
wst04-VHDL20_DWPH_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:26 243809
wst04-VHDL20_DWPH_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:33 243749
wst04-VHDL20_DWPH_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:43 243913
wst04-VHDL20_DWSG_011800-2609011800-omedes--0.pdf 01-Sep-2026 18:30:13 341303
wst04-VHDL20_DWSG_020200-2609020200-omedes--0.pdf 02-Sep-2026 02:30:16 340865
wst04-VHDL20_DWSG_020400-2609020400-omedes--0.pdf 02-Sep-2026 05:00:13 340668
wst04-VHDL20_DWSG_020800-2609020800-omedes--0.pdf 02-Sep-2026 08:30:13 341673
wst04-VHDL20_DWSG_021800-2609021800-omedes--0.pdf 02-Sep-2026 18:30:15 350422
wst04-VHDL20_DWSG_030200-2609030200-omedes--0.pdf 03-Sep-2026 02:30:20 350283
wst04-VHDL20_DWSG_030400-2609030400-omedes--0.pdf 03-Sep-2026 05:00:13 352217
wst04-VHDL20_DWSG_030800-2609030800-omedes--0.pdf 03-Sep-2026 08:30:15 352465