Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_260600                                 26-Jun-2025 11:57:45                2752
FPDL13_DWMZ_270600                                 27-Jun-2025 12:30:51                3718
SXDL31_DWAV_261800                                 26-Jun-2025 16:07:04                9734
SXDL31_DWAV_270800                                 27-Jun-2025 07:13:59                6522
SXDL31_DWAV_271800                                 27-Jun-2025 15:57:50               11904
SXDL31_DWAV_280800                                 28-Jun-2025 06:41:48                6541
SXDL31_DWAV_LATEST                                 28-Jun-2025 06:41:48                6541
SXDL33_DWAV_260000                                 26-Jun-2025 09:57:44                7790
SXDL33_DWAV_270000                                 27-Jun-2025 10:21:25               11013
SXDL33_DWAV_LATEST                                 27-Jun-2025 10:21:25               11013
ber01-FWDL39_DWMS_261230-2506261230-dsw--0-ia5     26-Jun-2025 11:24:21                1747
ber01-FWDL39_DWMS_271230-2506271230-dsw--0-ia5     27-Jun-2025 11:42:12                1810
ber01-VHDL13_DWEH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:28:11                2285
ber01-VHDL13_DWEH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:28:06                2031
ber01-VHDL13_DWEH_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:58:06                2122
ber01-VHDL13_DWEH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:28:13                2126
ber01-VHDL13_DWEH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:28:11                1752
ber01-VHDL13_DWEH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:28:06                2207
ber01-VHDL13_DWEH_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:58:06                2116
ber01-VHDL13_DWEH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:28:12                2282
ber01-VHDL13_DWHG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:10                2295
ber01-VHDL13_DWHG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:07                2355
ber01-VHDL13_DWHG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:12                2318
ber01-VHDL13_DWHG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:08                2289
ber01-VHDL13_DWHG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:07                2035
ber01-VHDL13_DWHG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:07                2014
ber01-VHDL13_DWHG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:12                2014
ber01-VHDL13_DWHG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:09                2090
ber01-VHDL13_DWHH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:10                2347
ber01-VHDL13_DWHH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:07                2562
ber01-VHDL13_DWHH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:12                2601
ber01-VHDL13_DWHH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:08                2591
ber01-VHDL13_DWHH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:07                2282
ber01-VHDL13_DWHH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:07                2186
ber01-VHDL13_DWHH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:12                2187
ber01-VHDL13_DWHH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:09                2298
ber01-VHDL13_DWLG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                2424
ber01-VHDL13_DWLG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                1751
ber01-VHDL13_DWLG_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:59:56                2026
ber01-VHDL13_DWLG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2055
ber01-VHDL13_DWLG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1545
ber01-VHDL13_DWLG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:07                1724
ber01-VHDL13_DWLG_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:59:57                1737
ber01-VHDL13_DWLG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1733
ber01-VHDL13_DWLH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                2320
ber01-VHDL13_DWLH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                1813
ber01-VHDL13_DWLH_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:59:56                2091
ber01-VHDL13_DWLH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2094
ber01-VHDL13_DWLH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1628
ber01-VHDL13_DWLH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:07                1801
ber01-VHDL13_DWLH_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:59:57                1833
ber01-VHDL13_DWLH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1856
ber01-VHDL13_DWLI_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                1830
ber01-VHDL13_DWLI_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                1630
ber01-VHDL13_DWLI_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:59:56                1894
ber01-VHDL13_DWLI_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                1872
ber01-VHDL13_DWLI_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1525
ber01-VHDL13_DWLI_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:07                1659
ber01-VHDL13_DWLI_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:59:57                1671
ber01-VHDL13_DWLI_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1667
ber01-VHDL13_DWMG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                2362
ber01-VHDL13_DWMG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                2142
ber01-VHDL13_DWMG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2146
ber01-VHDL13_DWMG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2776
ber01-VHDL13_DWMG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1785
ber01-VHDL13_DWMG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                1933
ber01-VHDL13_DWMG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2049
ber01-VHDL13_DWMG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2028
ber01-VHDL13_DWMO_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                2254
ber01-VHDL13_DWMO_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                1917
ber01-VHDL13_DWMO_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                1914
ber01-VHDL13_DWMO_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2774
ber01-VHDL13_DWMO_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1742
ber01-VHDL13_DWMO_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                1970
ber01-VHDL13_DWMO_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                1991
ber01-VHDL13_DWMO_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2087
ber01-VHDL13_DWMP_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                2136
ber01-VHDL13_DWMP_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                2197
ber01-VHDL13_DWMP_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2199
ber01-VHDL13_DWMP_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2982
ber01-VHDL13_DWMP_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1928
ber01-VHDL13_DWMP_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                2072
ber01-VHDL13_DWMP_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2189
ber01-VHDL13_DWMP_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2199
ber01-VHDL13_DWOG_261700-2506261700-dsw--0-ia5     26-Jun-2025 18:00:01                3698
ber01-VHDL13_DWOG_270300-2506270300-dsw--0-ia5     27-Jun-2025 03:00:07                3523
ber01-VHDL13_DWOG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                3690
ber01-VHDL13_DWOG_271700-2506271700-dsw--0-ia5     27-Jun-2025 18:00:02                3121
ber01-VHDL13_DWOG_280300-2506280300-dsw--0-ia5     28-Jun-2025 03:00:08                3008
ber01-VHDL13_DWOG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                3231
ber01-VHDL13_DWOH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:28:11                2051
ber01-VHDL13_DWOH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:28:12                2009
ber01-VHDL13_DWOH_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:58:11                2132
ber01-VHDL13_DWOH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:28:13                2284
ber01-VHDL13_DWOH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:28:11                1901
ber01-VHDL13_DWOH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:28:06                2357
ber01-VHDL13_DWOH_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:58:12                2276
ber01-VHDL13_DWOH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:28:12                2380
ber01-VHDL13_DWOI_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:28:07                2165
ber01-VHDL13_DWOI_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:28:12                2072
ber01-VHDL13_DWOI_270400-2506270400-dsw--0-ia5     27-Jun-2025 04:58:11                2169
ber01-VHDL13_DWOI_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:28:07                2325
ber01-VHDL13_DWOI_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:28:07                1944
ber01-VHDL13_DWOI_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:28:12                2368
ber01-VHDL13_DWOI_280400-2506280400-dsw--0-ia5     28-Jun-2025 04:58:12                2284
ber01-VHDL13_DWOI_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:28:06                2370
ber01-VHDL13_DWON_261426-2506261426-dsw--0-ia5     26-Jun-2025 14:26:52                3659
ber01-VHDL13_DWON_261717-2506261717-dsw--0-ia5     26-Jun-2025 17:17:52                3174
ber01-VHDL13_DWON_262024-2506262024-dsw--0-ia5     26-Jun-2025 20:24:42                3088
ber01-VHDL13_DWON_270254-2506270254-dsw--0-ia5     27-Jun-2025 02:54:29                3250
ber01-VHDL13_DWON_270500-2506270500-dsw--0-ia5     27-Jun-2025 05:00:26                3056
ber01-VHDL13_DWON_270511-2506270511-dsw--0-ia5     27-Jun-2025 05:12:00                3231
ber01-VHDL13_DWON_270815-2506270815-dsw--0-ia5     27-Jun-2025 08:15:22                3199
ber01-VHDL13_DWON_271210-2506271210-dsw--0-ia5     27-Jun-2025 12:10:48                3766
ber01-VHDL13_DWON_271316-2506271316-dsw--0-ia5     27-Jun-2025 13:16:51                3568
ber01-VHDL13_DWON_271414-2506271414-dsw--0-ia5     27-Jun-2025 14:14:26                3473
ber01-VHDL13_DWON_271631-2506271631-dsw--0-ia5     27-Jun-2025 16:31:21                3081
ber01-VHDL13_DWON_280120-2506280120-dsw--0-ia5     28-Jun-2025 01:20:36                3066
ber01-VHDL13_DWON_280121-2506280121-dsw--0-ia5     28-Jun-2025 01:21:37                3066
ber01-VHDL13_DWON_280122-2506280122-dsw--0-ia5     28-Jun-2025 01:22:37                3066
ber01-VHDL13_DWON_280526-2506280526-dsw--0-ia5     28-Jun-2025 05:26:07                3674
ber01-VHDL13_DWON_280624-2506280624-dsw--0-ia5     28-Jun-2025 06:24:17                3674
ber01-VHDL13_DWON_280731-2506280731-dsw--0-ia5     28-Jun-2025 07:32:00                3674
ber01-VHDL13_DWON_280755-2506280755-dsw--0-ia5     28-Jun-2025 07:55:32                3674
ber01-VHDL13_DWON_280834-2506280834-dsw--0-ia5     28-Jun-2025 08:34:37                3674
ber01-VHDL13_DWPG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:10                2118
ber01-VHDL13_DWPG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                1817
ber01-VHDL13_DWPG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2094
ber01-VHDL13_DWPG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2087
ber01-VHDL13_DWPG_270800_COR-2506270800-dsw--0-ia5 27-Jun-2025 09:24:21                2087
ber01-VHDL13_DWPG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1676
ber01-VHDL13_DWPG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                1943
ber01-VHDL13_DWPG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                1909
ber01-VHDL13_DWPG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1880
ber01-VHDL13_DWPH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:10                2548
ber01-VHDL13_DWPH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:02                2199
ber01-VHDL13_DWPH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2556
ber01-VHDL13_DWPH_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:35:34                2744
ber01-VHDL13_DWPH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2692
ber01-VHDL13_DWPH_270800_COR-2506270800-dsw--0-ia5 27-Jun-2025 09:24:37                2538
ber01-VHDL13_DWPH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1852
ber01-VHDL13_DWPH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                2055
ber01-VHDL13_DWPH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2088
ber01-VHDL13_DWPH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2289
ber01-VHDL13_DWSG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                1724
ber01-VHDL13_DWSG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:30:07                1923
ber01-VHDL13_DWSG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:08                1966
ber01-VHDL13_DWSG_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:05:16                1970
ber01-VHDL13_DWSG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2038
ber01-VHDL13_DWSG_270800_COR-2506270800-dsw--0-ia5 27-Jun-2025 13:42:02                2239
ber01-VHDL13_DWSG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1587
ber01-VHDL13_DWSG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:30:01                2004
ber01-VHDL13_DWSG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2036
ber01-VHDL13_DWSG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2090
ber01-VHDL13_DWSN_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                1538
ber01-VHDL13_DWSN_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:08                1642
ber01-VHDL13_DWSN_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:05:16                1643
ber01-VHDL13_DWSN_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:08                1710
ber01-VHDL13_DWSN_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1307
ber01-VHDL13_DWSN_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                1527
ber01-VHDL13_DWSN_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1561
ber01-VHDL13_DWSO_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                1721
ber01-VHDL13_DWSO_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:08                1990
ber01-VHDL13_DWSO_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:05:16                1972
ber01-VHDL13_DWSO_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:01                2040
ber01-VHDL13_DWSO_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1606
ber01-VHDL13_DWSO_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                1999
ber01-VHDL13_DWSO_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                2048
ber01-VHDL13_DWSP_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:30:04                1647
ber01-VHDL13_DWSP_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:08                1934
ber01-VHDL13_DWSP_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:05:16                1899
ber01-VHDL13_DWSP_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:30:08                1967
ber01-VHDL13_DWSP_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:30:04                1543
ber01-VHDL13_DWSP_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                1851
ber01-VHDL13_DWSP_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:30:02                1873
ber01-VHDL17_DWOG_261200-2506261200-dsw--0-ia5     26-Jun-2025 10:55:32                2804
ber01-VHDL17_DWOG_271200-2506271200-dsw--0-ia5     27-Jun-2025 11:49:35                4139
swis2-VHDL20_DWEG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2236
swis2-VHDL20_DWEG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:01                2141
swis2-VHDL20_DWEG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:15:02                2340
swis2-VHDL20_DWEG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2463
swis2-VHDL20_DWEG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                2086
swis2-VHDL20_DWEG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2489
swis2-VHDL20_DWEG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:15:01                2484
swis2-VHDL20_DWEG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:07                2559
swis2-VHDL20_DWEH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:12                2485
swis2-VHDL20_DWEH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:09                2195
swis2-VHDL20_DWEH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:15:12                2300
swis2-VHDL20_DWEH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2304
swis2-VHDL20_DWEH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                1952
swis2-VHDL20_DWEH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2371
swis2-VHDL20_DWEH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:15:11                2294
swis2-VHDL20_DWEH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:07                2460
swis2-VHDL20_DWEI_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2350
swis2-VHDL20_DWEI_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:01                2205
swis2-VHDL20_DWEI_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:15:12                2354
swis2-VHDL20_DWEI_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2504
swis2-VHDL20_DWEI_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                2129
swis2-VHDL20_DWEI_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2501
swis2-VHDL20_DWEI_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:15:11                2469
swis2-VHDL20_DWEI_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:07                2549
swis2-VHDL20_DWHG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2478
swis2-VHDL20_DWHG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2541
swis2-VHDL20_DWHG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:12                2501
swis2-VHDL20_DWHG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2472
swis2-VHDL20_DWHG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                2218
swis2-VHDL20_DWHG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2200
swis2-VHDL20_DWHG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:12                2197
swis2-VHDL20_DWHG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2273
swis2-VHDL20_DWHH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2533
swis2-VHDL20_DWHH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2748
swis2-VHDL20_DWHH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:12                2787
swis2-VHDL20_DWHH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2777
swis2-VHDL20_DWHH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                2468
swis2-VHDL20_DWHH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2372
swis2-VHDL20_DWHH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:12                2373
swis2-VHDL20_DWHH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2484
swis2-VHDL20_DWLG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2645
swis2-VHDL20_DWLG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                1972
swis2-VHDL20_DWLG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:22                2247
swis2-VHDL20_DWLG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2285
swis2-VHDL20_DWLG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                1766
swis2-VHDL20_DWLG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                1945
swis2-VHDL20_DWLG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:22                1958
swis2-VHDL20_DWLG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                1957
swis2-VHDL20_DWLH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2541
swis2-VHDL20_DWLH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2034
swis2-VHDL20_DWLH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:22                2312
swis2-VHDL20_DWLH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2370
swis2-VHDL20_DWLH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                1849
swis2-VHDL20_DWLH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2022
swis2-VHDL20_DWLH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:22                2054
swis2-VHDL20_DWLH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2077
swis2-VHDL20_DWLI_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2051
swis2-VHDL20_DWLI_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                1851
swis2-VHDL20_DWLI_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:22                2112
swis2-VHDL20_DWLI_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2147
swis2-VHDL20_DWLI_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                1746
swis2-VHDL20_DWLI_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                1880
swis2-VHDL20_DWLI_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:22                1889
swis2-VHDL20_DWLI_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                1888
swis2-VHDL20_DWMG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2573
swis2-VHDL20_DWMG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:01                2353
swis2-VHDL20_DWMG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2357
swis2-VHDL20_DWMG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2988
swis2-VHDL20_DWMG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                1996
swis2-VHDL20_DWMG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2145
swis2-VHDL20_DWMG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2260
swis2-VHDL20_DWMG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2239
swis2-VHDL20_DWMO_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2466
swis2-VHDL20_DWMO_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:01                2132
swis2-VHDL20_DWMO_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2129
swis2-VHDL20_DWMO_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                2986
swis2-VHDL20_DWMO_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                1954
swis2-VHDL20_DWMO_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2185
swis2-VHDL20_DWMO_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2206
swis2-VHDL20_DWMO_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2299
swis2-VHDL20_DWMP_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                2349
swis2-VHDL20_DWMP_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:01                2409
swis2-VHDL20_DWMP_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:06                2411
swis2-VHDL20_DWMP_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:01                3194
swis2-VHDL20_DWMP_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:06                2132
swis2-VHDL20_DWMP_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2284
swis2-VHDL20_DWMP_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2401
swis2-VHDL20_DWMP_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2411
swis2-VHDL20_DWPG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:06                2315
swis2-VHDL20_DWPG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2014
swis2-VHDL20_DWPG_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2289
swis2-VHDL20_DWPG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2284
swis2-VHDL20_DWPG_270800_COR-2506270800-dsw--0-ia5 27-Jun-2025 09:24:51                2284
swis2-VHDL20_DWPG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                1873
swis2-VHDL20_DWPG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2140
swis2-VHDL20_DWPG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2104
swis2-VHDL20_DWPG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:07                2077
swis2-VHDL20_DWPH_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:06                2745
swis2-VHDL20_DWPH_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2396
swis2-VHDL20_DWPH_270400-2506270400-dsw--0-ia5     27-Jun-2025 05:00:02                2753
swis2-VHDL20_DWPH_270400_COR-2506270400-dsw--0-ia5 27-Jun-2025 06:35:51                2941
swis2-VHDL20_DWPH_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2889
swis2-VHDL20_DWPH_270800_COR-2506270800-dsw--0-ia5 27-Jun-2025 09:25:21                2735
swis2-VHDL20_DWPH_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                2049
swis2-VHDL20_DWPH_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2252
swis2-VHDL20_DWPH_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:00:06                2285
swis2-VHDL20_DWPH_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:07                2486
swis2-VHDL20_DWSG_261300-2506261300-dsw--0-ia5     26-Jun-2025 13:45:03                2970
swis2-VHDL20_DWSG_261800-2506261800-dsw--0-ia5     26-Jun-2025 18:45:02                1956
swis2-VHDL20_DWSG_270200-2506270200-dsw--0-ia5     27-Jun-2025 02:45:05                2179
swis2-VHDL20_DWSG_270400-2506270400-dsw--0-ia5     27-Jun-2025 06:05:16                2197
swis2-VHDL20_DWSG_270800-2506270800-dsw--0-ia5     27-Jun-2025 08:45:06                2268
swis2-VHDL20_DWSG_271300-2506271300-dsw--0-ia5     27-Jun-2025 13:45:04                2465
swis2-VHDL20_DWSG_271800-2506271800-dsw--0-ia5     27-Jun-2025 18:45:02                1819
swis2-VHDL20_DWSG_280200-2506280200-dsw--0-ia5     28-Jun-2025 02:45:08                2238
swis2-VHDL20_DWSG_280400-2506280400-dsw--0-ia5     28-Jun-2025 05:15:01                2267
swis2-VHDL20_DWSG_280800-2506280800-dsw--0-ia5     28-Jun-2025 08:45:01                2320
wst04-VHDL20_DWEG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:06              261680
wst04-VHDL20_DWEG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:09              261216
wst04-VHDL20_DWEG_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:15:06              261656
wst04-VHDL20_DWEG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:06              261892
wst04-VHDL20_DWEG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:12              261837
wst04-VHDL20_DWEG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:08              261642
wst04-VHDL20_DWEG_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:15:07              262152
wst04-VHDL20_DWEG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:07              262199
wst04-VHDL20_DWEH_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:12              259898
wst04-VHDL20_DWEH_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:10              260257
wst04-VHDL20_DWEH_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:15:06              260112
wst04-VHDL20_DWEH_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:06              260095
wst04-VHDL20_DWEH_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:12              259023
wst04-VHDL20_DWEH_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:08              260156
wst04-VHDL20_DWEH_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:15:07              259631
wst04-VHDL20_DWEH_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:07              259539
wst04-VHDL20_DWEI_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:16              364875
wst04-VHDL20_DWEI_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:12              365522
wst04-VHDL20_DWEI_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:15:12              364817
wst04-VHDL20_DWEI_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:12              365005
wst04-VHDL20_DWEI_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:12              368307
wst04-VHDL20_DWEI_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              369101
wst04-VHDL20_DWEI_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:15:11              368590
wst04-VHDL20_DWEI_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:11              368614
wst04-VHDL20_DWHG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:22              370285
wst04-VHDL20_DWHG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:22              370261
wst04-VHDL20_DWHG_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:06              369793
wst04-VHDL20_DWHG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:12              370860
wst04-VHDL20_DWHG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:22              364829
wst04-VHDL20_DWHG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              366220
wst04-VHDL20_DWHG_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:06              366232
wst04-VHDL20_DWHG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:17              366876
wst04-VHDL20_DWHH_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:16              356669
wst04-VHDL20_DWHH_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:22              357121
wst04-VHDL20_DWHH_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:06              357178
wst04-VHDL20_DWHH_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:12              357232
wst04-VHDL20_DWHH_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:16              351059
wst04-VHDL20_DWHH_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              351628
wst04-VHDL20_DWHH_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:06              351620
wst04-VHDL20_DWHH_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:17              352183
wst04-VHDL20_DWLG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:40:26              363841
wst04-VHDL20_DWLG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:40:30              362624
wst04-VHDL20_DWLG_270400-2506270400-omedes--0.pdf  27-Jun-2025 04:59:37              362327
wst04-VHDL20_DWLG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:40:27              362122
wst04-VHDL20_DWLG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:40:27              359205
wst04-VHDL20_DWLG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:40:37              359500
wst04-VHDL20_DWLG_280400-2506280400-omedes--0.pdf  28-Jun-2025 04:59:37              359112
wst04-VHDL20_DWLG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:40:26              359802
wst04-VHDL20_DWLH_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:40:16              368623
wst04-VHDL20_DWLH_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:40:17              368006
wst04-VHDL20_DWLH_270400-2506270400-omedes--0.pdf  27-Jun-2025 04:59:37              367682
wst04-VHDL20_DWLH_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:40:15              367469
wst04-VHDL20_DWLH_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:40:17              360648
wst04-VHDL20_DWLH_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:40:37              360961
wst04-VHDL20_DWLH_280400-2506280400-omedes--0.pdf  28-Jun-2025 04:59:37              360556
wst04-VHDL20_DWLH_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:40:18              361269
wst04-VHDL20_DWLI_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:40:36              359078
wst04-VHDL20_DWLI_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:40:36              359432
wst04-VHDL20_DWLI_270400-2506270400-omedes--0.pdf  27-Jun-2025 04:59:37              359164
wst04-VHDL20_DWLI_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:40:37              358971
wst04-VHDL20_DWLI_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:40:37              359338
wst04-VHDL20_DWLI_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:40:37              359561
wst04-VHDL20_DWLI_280400-2506280400-omedes--0.pdf  28-Jun-2025 04:59:37              359196
wst04-VHDL20_DWLI_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:40:36              359881
wst04-VHDL20_DWMG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:16              591121
wst04-VHDL20_DWMG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:22              592549
wst04-VHDL20_DWMG_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:12              591996
wst04-VHDL20_DWMG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:16              592257
wst04-VHDL20_DWMG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:16              593243
wst04-VHDL20_DWMG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              594396
wst04-VHDL20_DWMG_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:12              593894
wst04-VHDL20_DWMG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:17              593732
wst04-VHDL20_DWMO_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:12              475110
wst04-VHDL20_DWMO_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:12              475057
wst04-VHDL20_DWMO_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:12              475475
wst04-VHDL20_DWMO_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:16              475429
wst04-VHDL20_DWMO_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:16              477062
wst04-VHDL20_DWMO_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              477292
wst04-VHDL20_DWMO_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:12              478302
wst04-VHDL20_DWMO_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:11              477802
wst04-VHDL20_DWMP_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:16              599909
wst04-VHDL20_DWMP_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:22              600074
wst04-VHDL20_DWMP_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:12              600304
wst04-VHDL20_DWMP_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:16              601071
wst04-VHDL20_DWMP_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:16              597000
wst04-VHDL20_DWMP_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              597355
wst04-VHDL20_DWMP_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:12              598183
wst04-VHDL20_DWMP_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:11              597826
wst04-VHDL20_DWPG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:06              371833
wst04-VHDL20_DWPG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:12              371567
wst04-VHDL20_DWPG_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:08              372021
wst04-VHDL20_DWPG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:26              416167
wst04-VHDL20_DWPG_270800_COR-2506270800-omedes-..> 27-Jun-2025 09:25:11              416171
wst04-VHDL20_DWPG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:06              366851
wst04-VHDL20_DWPG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              367201
wst04-VHDL20_DWPG_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:06              366732
wst04-VHDL20_DWPG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:21              411466
wst04-VHDL20_DWPH_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:06              312337
wst04-VHDL20_DWPH_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:12              267459
wst04-VHDL20_DWPH_270400-2506270400-omedes--0.pdf  27-Jun-2025 05:00:08              267898
wst04-VHDL20_DWPH_270400_COR-2506270400-omedes-..> 27-Jun-2025 06:36:11              268815
wst04-VHDL20_DWPH_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:16              313035
wst04-VHDL20_DWPH_270800_COR-2506270800-omedes-..> 27-Jun-2025 09:25:43              312977
wst04-VHDL20_DWPH_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:06              303459
wst04-VHDL20_DWPH_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              259837
wst04-VHDL20_DWPH_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:00:06              259471
wst04-VHDL20_DWPH_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:17              304795
wst04-VHDL20_DWSG_261300-2506261300-omedes--0.pdf  26-Jun-2025 13:45:07              367394
wst04-VHDL20_DWSG_261800-2506261800-omedes--0.pdf  26-Jun-2025 18:45:12              365564
wst04-VHDL20_DWSG_270200-2506270200-omedes--0.pdf  27-Jun-2025 02:45:22              365981
wst04-VHDL20_DWSG_270400-2506270400-omedes--0.pdf  27-Jun-2025 06:05:16              365799
wst04-VHDL20_DWSG_270800-2506270800-omedes--0.pdf  27-Jun-2025 08:45:12              365900
wst04-VHDL20_DWSG_271300-2506271300-omedes--0.pdf  27-Jun-2025 13:45:08              370025
wst04-VHDL20_DWSG_271800-2506271800-omedes--0.pdf  27-Jun-2025 18:45:12              368946
wst04-VHDL20_DWSG_280200-2506280200-omedes--0.pdf  28-Jun-2025 02:45:37              369301
wst04-VHDL20_DWSG_280400-2506280400-omedes--0.pdf  28-Jun-2025 05:15:11              369085
wst04-VHDL20_DWSG_280800-2506280800-omedes--0.pdf  28-Jun-2025 08:45:11              369140