Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jun-2026 12:13:39 4018
FPDL13_DWMZ_200600 20-Jun-2026 14:12:50 3076
SXDL31_DWAV_191800 19-Jun-2026 16:37:38 13609
SXDL31_DWAV_200800 20-Jun-2026 08:12:40 14756
SXDL31_DWAV_201800 20-Jun-2026 16:29:04 5903
SXDL31_DWAV_210800 21-Jun-2026 08:13:45 9179
SXDL31_DWAV_LATEST 21-Jun-2026 08:13:45 9179
SXDL33_DWAV_200000 20-Jun-2026 09:30:58 9951
SXDL33_DWAV_LATEST 20-Jun-2026 09:30:58 9951
ber01-FWDL39_DWMS_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:25:51 1336
ber01-FWDL39_DWMS_201200-2606201200-dsw--0-ia5 20-Jun-2026 11:55:31 1171
ber01-FWDL39_DWMS_201200_COR-2606201200-dsw--0-ia5 20-Jun-2026 11:58:56 1166
ber01-VHDL13_DWEG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:28:54 4381
ber01-VHDL13_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3719
ber01-VHDL13_DWEH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:28:54 4394
ber01-VHDL13_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3725
ber01-VHDL13_DWEI_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:28:54 4193
ber01-VHDL13_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3430
ber01-VHDL13_DWHG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 3764
ber01-VHDL13_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3615
ber01-VHDL13_DWHH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2991
ber01-VHDL13_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2871
ber01-VHDL13_DWLG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2993
ber01-VHDL13_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2810
ber01-VHDL13_DWLH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2986
ber01-VHDL13_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2707
ber01-VHDL13_DWLI_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2818
ber01-VHDL13_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2760
ber01-VHDL13_DWMO_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 3396
ber01-VHDL13_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 3483
ber01-VHDL13_DWMP_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 3412
ber01-VHDL13_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL13_DWOG_191700-2606191700-dsw--0-ia5 19-Jun-2026 18:00:04 5005
ber01-VHDL13_DWOG_200300-2606200300-dsw--0-ia5 20-Jun-2026 03:00:02 4733
ber01-VHDL13_DWOG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 4757
ber01-VHDL13_DWOG_201700-2606201700-dsw--0-ia5 20-Jun-2026 18:00:01 4235
ber01-VHDL13_DWOG_210300-2606210300-dsw--0-ia5 21-Jun-2026 03:00:02 4349
ber01-VHDL13_DWOG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 4689
ber01-VHDL13_DWON_191416-2606191416-dsw--0-ia5 19-Jun-2026 14:16:07 3586
ber01-VHDL13_DWON_191701-2606191701-dsw--0-ia5 19-Jun-2026 17:01:11 4201
ber01-VHDL13_DWON_192159-2606192159-dsw--0-ia5 19-Jun-2026 21:59:52 4278
ber01-VHDL13_DWON_200137-2606200137-dsw--0-ia5 20-Jun-2026 01:37:31 3828
ber01-VHDL13_DWON_200156-2606200156-dsw--0-ia5 20-Jun-2026 01:56:27 3828
ber01-VHDL13_DWON_200339-2606200339-dsw--0-ia5 20-Jun-2026 03:39:08 3828
ber01-VHDL13_DWON_200529-2606200529-dsw--0-ia5 20-Jun-2026 05:29:41 3827
ber01-VHDL13_DWON_200612-2606200612-dsw--0-ia5 20-Jun-2026 06:12:27 4353
ber01-VHDL13_DWON_201200-2606201200-dsw--0-ia5 20-Jun-2026 12:00:12 4353
ber01-VHDL13_DWON_201216-2606201216-dsw--0-ia5 20-Jun-2026 12:16:46 4054
ber01-VHDL13_DWON_201504-2606201504-dsw--0-ia5 20-Jun-2026 15:04:11 3429
ber01-VHDL13_DWON_201720-2606201720-dsw--0-ia5 20-Jun-2026 17:20:26 3308
ber01-VHDL13_DWON_202127-2606202127-dsw--0-ia5 20-Jun-2026 21:27:53 3286
ber01-VHDL13_DWON_202344-2606202344-dsw--0-ia5 20-Jun-2026 23:44:12 3329
ber01-VHDL13_DWON_210128-2606210128-dsw--0-ia5 21-Jun-2026 01:28:56 3578
ber01-VHDL13_DWON_210249-2606210249-dsw--0-ia5 21-Jun-2026 02:50:29 3766
ber01-VHDL13_DWON_210530-2606210530-dsw--0-ia5 21-Jun-2026 05:30:07 3553
ber01-VHDL13_DWON_210629-2606210629-dsw--0-ia5 21-Jun-2026 06:29:27 4007
ber01-VHDL13_DWON_210721-2606210721-dsw--0-ia5 21-Jun-2026 07:21:22 4143
ber01-VHDL13_DWON_210722-2606210722-dsw--0-ia5 21-Jun-2026 07:22:51 4147
ber01-VHDL13_DWON_211000-2606211000-dsw--0-ia5 21-Jun-2026 10:00:52 3894
ber01-VHDL13_DWPG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 3214
ber01-VHDL13_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2496
ber01-VHDL13_DWPH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2788
ber01-VHDL13_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2126
ber01-VHDL13_DWSG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 3164
ber01-VHDL13_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL17_DWOG_191200-2606191200-dsw--0-ia5 19-Jun-2026 11:05:47 3322
ber01-VHDL17_DWOG_201200-2606201200-dsw--0-ia5 20-Jun-2026 10:58:02 2848
swis2-VHDL20_DWEG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2498
swis2-VHDL20_DWEG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1876
swis2-VHDL20_DWEG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2126
swis2-VHDL20_DWEG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2625
swis2-VHDL20_DWEG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2417
swis2-VHDL20_DWEG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1743
swis2-VHDL20_DWEG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1633
swis2-VHDL20_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1977
swis2-VHDL20_DWEH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2512
swis2-VHDL20_DWEH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1782
swis2-VHDL20_DWEH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2096
swis2-VHDL20_DWEH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2631
swis2-VHDL20_DWEH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2456
swis2-VHDL20_DWEH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1613
swis2-VHDL20_DWEH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1662
swis2-VHDL20_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2022
swis2-VHDL20_DWEI_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2510
swis2-VHDL20_DWEI_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1649
swis2-VHDL20_DWEI_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:01:17 2193
swis2-VHDL20_DWEI_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 2545
swis2-VHDL20_DWEI_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2312
swis2-VHDL20_DWEI_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1641
swis2-VHDL20_DWEI_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1595
swis2-VHDL20_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1884
swis2-VHDL20_DWHG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:45:07 1935
swis2-VHDL20_DWHG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:45:10 1743
swis2-VHDL20_DWHG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1740
swis2-VHDL20_DWHG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:45:43 1956
swis2-VHDL20_DWHG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:45:06 2117
swis2-VHDL20_DWHG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:45:08 1979
swis2-VHDL20_DWHG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1880
swis2-VHDL20_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 2030
swis2-VHDL20_DWHH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:45:07 1644
swis2-VHDL20_DWHH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:45:10 1550
swis2-VHDL20_DWHH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1550
swis2-VHDL20_DWHH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:45:43 1450
swis2-VHDL20_DWHH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:45:06 1526
swis2-VHDL20_DWHH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:45:08 1470
swis2-VHDL20_DWHH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1245
swis2-VHDL20_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 1419
swis2-VHDL20_DWLG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1912
swis2-VHDL20_DWLG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1490
swis2-VHDL20_DWLG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1448
swis2-VHDL20_DWLG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1714
swis2-VHDL20_DWLG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1337
swis2-VHDL20_DWLG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1341
swis2-VHDL20_DWLG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1372
swis2-VHDL20_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1578
swis2-VHDL20_DWLH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1953
swis2-VHDL20_DWLH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1750
swis2-VHDL20_DWLH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1442
swis2-VHDL20_DWLH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1693
swis2-VHDL20_DWLH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1290
swis2-VHDL20_DWLH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1145
swis2-VHDL20_DWLH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1488
swis2-VHDL20_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1612
swis2-VHDL20_DWLI_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1830
swis2-VHDL20_DWLI_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1597
swis2-VHDL20_DWLI_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1306
swis2-VHDL20_DWLI_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1533
swis2-VHDL20_DWLI_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1206
swis2-VHDL20_DWLI_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1395
swis2-VHDL20_DWLI_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1494
swis2-VHDL20_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1700
swis2-VHDL20_DWMO_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 1724
swis2-VHDL20_DWMO_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1460
swis2-VHDL20_DWMO_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:02 1448
swis2-VHDL20_DWMO_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1787
swis2-VHDL20_DWMO_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2012
swis2-VHDL20_DWMO_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:07 1577
swis2-VHDL20_DWMO_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:03 1626
swis2-VHDL20_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1806
swis2-VHDL20_DWMP_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 1670
swis2-VHDL20_DWMP_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1423
swis2-VHDL20_DWMP_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:02 1448
swis2-VHDL20_DWMP_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1786
swis2-VHDL20_DWMP_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 1898
swis2-VHDL20_DWMP_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:07 1506
swis2-VHDL20_DWMP_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:03 1511
swis2-VHDL20_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 1709
swis2-VHDL20_DWPG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1680
swis2-VHDL20_DWPG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1489
swis2-VHDL20_DWPG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1457
swis2-VHDL20_DWPG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1606
swis2-VHDL20_DWPG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1289
swis2-VHDL20_DWPG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1368
swis2-VHDL20_DWPG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1571
swis2-VHDL20_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1445
swis2-VHDL20_DWPH_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:31:05 1430
swis2-VHDL20_DWPH_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:23 1346
swis2-VHDL20_DWPH_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:12 1311
swis2-VHDL20_DWPH_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1409
swis2-VHDL20_DWPH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 861
swis2-VHDL20_DWPH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 842
swis2-VHDL20_DWPH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 931
swis2-VHDL20_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1049
swis2-VHDL20_DWSG_191800-2606191800-dsw--0-ia5 19-Jun-2026 18:30:02 2060
swis2-VHDL20_DWSG_200200-2606200200-dsw--0-ia5 20-Jun-2026 02:30:08 1328
swis2-VHDL20_DWSG_200400-2606200400-dsw--0-ia5 20-Jun-2026 05:00:16 1325
swis2-VHDL20_DWSG_200800-2606200800-dsw--0-ia5 20-Jun-2026 08:30:54 1592
swis2-VHDL20_DWSG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 1674
swis2-VHDL20_DWSG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1439
swis2-VHDL20_DWSG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1369
swis2-VHDL20_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1607
wst04-VHDL20_DWEG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 252051
wst04-VHDL20_DWEG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 250229
wst04-VHDL20_DWEG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 250055
wst04-VHDL20_DWEG_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 251322
wst04-VHDL20_DWEG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 252206
wst04-VHDL20_DWEG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 250231
wst04-VHDL20_DWEG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 249721
wst04-VHDL20_DWEG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 251328
wst04-VHDL20_DWEH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 246862
wst04-VHDL20_DWEH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 245556
wst04-VHDL20_DWEH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 245389
wst04-VHDL20_DWEH_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 246688
wst04-VHDL20_DWEH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 251789
wst04-VHDL20_DWEH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 250156
wst04-VHDL20_DWEH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 250338
wst04-VHDL20_DWEH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 251448
wst04-VHDL20_DWEI_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:13 363899
wst04-VHDL20_DWEI_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 362420
wst04-VHDL20_DWEI_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 362414
wst04-VHDL20_DWEI_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 363109
wst04-VHDL20_DWEI_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 364279
wst04-VHDL20_DWEI_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 362813
wst04-VHDL20_DWEI_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 362501
wst04-VHDL20_DWEI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 363969
wst04-VHDL20_DWHG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:45:18 356475
wst04-VHDL20_DWHG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:45:16 355913
wst04-VHDL20_DWHG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:16 355914
wst04-VHDL20_DWHG_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:45:30 357376
wst04-VHDL20_DWHG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:45:12 356361
wst04-VHDL20_DWHG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:46:02 356597
wst04-VHDL20_DWHG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 356296
wst04-VHDL20_DWHG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 357125
wst04-VHDL20_DWHH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:45:18 332569
wst04-VHDL20_DWHH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:45:16 332989
wst04-VHDL20_DWHH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:16 224791
wst04-VHDL20_DWHH_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:45:30 333152
wst04-VHDL20_DWHH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:45:12 328647
wst04-VHDL20_DWHH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:46:02 328879
wst04-VHDL20_DWHH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 220325
wst04-VHDL20_DWHH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 328334
wst04-VHDL20_DWLG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 393165
wst04-VHDL20_DWLG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:27 347610
wst04-VHDL20_DWLG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 346901
wst04-VHDL20_DWLG_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 347933
wst04-VHDL20_DWLG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 352773
wst04-VHDL20_DWLG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 353209
wst04-VHDL20_DWLG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 352497
wst04-VHDL20_DWLG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 353321
wst04-VHDL20_DWLH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 392141
wst04-VHDL20_DWLH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 347394
wst04-VHDL20_DWLH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 346199
wst04-VHDL20_DWLH_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 347238
wst04-VHDL20_DWLH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 343548
wst04-VHDL20_DWLH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 343838
wst04-VHDL20_DWLH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 343291
wst04-VHDL20_DWLH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 343371
wst04-VHDL20_DWLI_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:29 395503
wst04-VHDL20_DWLI_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 349928
wst04-VHDL20_DWLI_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:40 349436
wst04-VHDL20_DWLI_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 395069
wst04-VHDL20_DWLI_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 353474
wst04-VHDL20_DWLI_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:29 354099
wst04-VHDL20_DWLI_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 353355
wst04-VHDL20_DWLI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:50 398790
wst04-VHDL20_DWMO_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 371241
wst04-VHDL20_DWMO_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:19 483816
wst04-VHDL20_DWMO_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:18 483718
wst04-VHDL20_DWMO_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 484208
wst04-VHDL20_DWMO_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 378463
wst04-VHDL20_DWMO_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:17 494590
wst04-VHDL20_DWMO_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 494678
wst04-VHDL20_DWMO_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 493573
wst04-VHDL20_DWMP_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 484715
wst04-VHDL20_DWMP_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:19 595962
wst04-VHDL20_DWMP_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:18 596321
wst04-VHDL20_DWMP_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 484215
wst04-VHDL20_DWMP_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 504062
wst04-VHDL20_DWMP_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:17 615762
wst04-VHDL20_DWMP_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 616132
wst04-VHDL20_DWMP_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:21 503869
wst04-VHDL20_DWPG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 351741
wst04-VHDL20_DWPG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 246491
wst04-VHDL20_DWPG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:32 350885
wst04-VHDL20_DWPG_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 396259
wst04-VHDL20_DWPG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 350233
wst04-VHDL20_DWPG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 248418
wst04-VHDL20_DWPG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:31 350161
wst04-VHDL20_DWPG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 394534
wst04-VHDL20_DWPH_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:31:25 289943
wst04-VHDL20_DWPH_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:23 245471
wst04-VHDL20_DWPH_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:32 245316
wst04-VHDL20_DWPH_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 245354
wst04-VHDL20_DWPH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 240533
wst04-VHDL20_DWPH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 241001
wst04-VHDL20_DWPH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:31 240225
wst04-VHDL20_DWPH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 240225
wst04-VHDL20_DWSG_191800-2606191800-omedes--0.pdf 19-Jun-2026 18:30:18 366288
wst04-VHDL20_DWSG_200200-2606200200-omedes--0.pdf 20-Jun-2026 02:30:14 363164
wst04-VHDL20_DWSG_200400-2606200400-omedes--0.pdf 20-Jun-2026 05:00:12 362966
wst04-VHDL20_DWSG_200800-2606200800-omedes--0.pdf 20-Jun-2026 08:30:54 364177
wst04-VHDL20_DWSG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 362175
wst04-VHDL20_DWSG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:15 361029
wst04-VHDL20_DWSG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:11 360800
wst04-VHDL20_DWSG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 361943