Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_070600                                 07-Jun-2026 10:48:00                3731
FPDL13_DWMZ_080600                                 08-Jun-2026 12:24:19                3458
SXDL31_DWAV_070800                                 07-Jun-2026 07:18:39                7515
SXDL31_DWAV_071800                                 07-Jun-2026 16:04:09                8852
SXDL31_DWAV_080800                                 08-Jun-2026 07:56:44                8646
SXDL31_DWAV_081800                                 08-Jun-2026 16:45:11                9870
SXDL31_DWAV_LATEST                                 08-Jun-2026 16:45:11                9870
SXDL33_DWAV_070000                                 07-Jun-2026 09:42:45                9037
SXDL33_DWAV_080000                                 08-Jun-2026 10:26:28               21340
SXDL33_DWAV_LATEST                                 08-Jun-2026 10:26:28               21340
ber01-FWDL39_DWMS_071200-2606071200-dsw--0-ia5     07-Jun-2026 21:59:21                1281
ber01-FWDL39_DWMS_081200-2606081200-dsw--0-ia5     08-Jun-2026 11:59:03                1359
ber01-VHDL13_DWEG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:28:16                3066
ber01-VHDL13_DWEG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:28:17                2918
ber01-VHDL13_DWEH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:28:16                3181
ber01-VHDL13_DWEH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:28:21                2995
ber01-VHDL13_DWEI_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:28:22                2747
ber01-VHDL13_DWEI_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:28:17                2828
ber01-VHDL13_DWHG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:07                2999
ber01-VHDL13_DWHG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                3136
ber01-VHDL13_DWHH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:07                2913
ber01-VHDL13_DWHH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                3194
ber01-VHDL13_DWLG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                2532
ber01-VHDL13_DWLG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                2208
ber01-VHDL13_DWLH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                2679
ber01-VHDL13_DWLH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                2628
ber01-VHDL13_DWLI_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                2381
ber01-VHDL13_DWLI_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                2521
ber01-VHDL13_DWMO_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                3100
ber01-VHDL13_DWMO_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                2741
ber01-VHDL13_DWMP_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                3302
ber01-VHDL13_DWMP_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                3212
ber01-VHDL13_DWOG_070300-2606070300-dsw--0-ia5     07-Jun-2026 03:00:02                4013
ber01-VHDL13_DWOG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                3685
ber01-VHDL13_DWOG_071700-2606071700-dsw--0-ia5     07-Jun-2026 18:00:00                3625
ber01-VHDL13_DWOG_080300-2606080300-dsw--0-ia5     08-Jun-2026 03:00:01                3717
ber01-VHDL13_DWOG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                3610
ber01-VHDL13_DWOG_081700-2606081700-dsw--0-ia5     08-Jun-2026 18:00:07                3730
ber01-VHDL13_DWON_070256-2606070256-dsw--0-ia5     07-Jun-2026 02:56:36                4125
ber01-VHDL13_DWON_070525-2606070525-dsw--0-ia5     07-Jun-2026 05:26:00                3533
ber01-VHDL13_DWON_070617-2606070617-dsw--0-ia5     07-Jun-2026 06:17:41                3551
ber01-VHDL13_DWON_070751-2606070751-dsw--0-ia5     07-Jun-2026 07:51:41                3551
ber01-VHDL13_DWON_071433-2606071433-dsw--0-ia5     07-Jun-2026 14:33:48                3598
ber01-VHDL13_DWON_071645-2606071645-dsw--0-ia5     07-Jun-2026 16:45:40                3173
ber01-VHDL13_DWON_071935-2606071935-dsw--0-ia5     07-Jun-2026 19:35:42                3107
ber01-VHDL13_DWON_080235-2606080235-dsw--0-ia5     08-Jun-2026 02:36:01                3229
ber01-VHDL13_DWON_080520-2606080520-dsw--0-ia5     08-Jun-2026 05:20:48                3504
ber01-VHDL13_DWON_080600-2606080600-dsw--0-ia5     08-Jun-2026 06:00:22                3457
ber01-VHDL13_DWON_080744-2606080744-dsw--0-ia5     08-Jun-2026 07:44:16                3380
ber01-VHDL13_DWON_080814-2606080814-dsw--0-ia5     08-Jun-2026 08:14:46                3380
ber01-VHDL13_DWON_081450-2606081450-dsw--0-ia5     08-Jun-2026 14:50:54                3413
ber01-VHDL13_DWON_081727-2606081727-dsw--0-ia5     08-Jun-2026 17:27:42                2961
ber01-VHDL13_DWON_090025-2606090025-dsw--0-ia5     09-Jun-2026 00:25:06                3242
ber01-VHDL13_DWON_090125-2606090125-dsw--0-ia5     09-Jun-2026 01:25:27                3242
ber01-VHDL13_DWON_090239-2606090239-dsw--0-ia5     09-Jun-2026 02:39:41                3242
ber01-VHDL13_DWPG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                2750
ber01-VHDL13_DWPG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                2644
ber01-VHDL13_DWPH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                2834
ber01-VHDL13_DWPH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:01                2976
ber01-VHDL13_DWSG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                3189
ber01-VHDL13_DWSG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                2980
ber01-VHDL17_DWOG_071200-2606071200-dsw--0-ia5     07-Jun-2026 11:42:56                2294
ber01-VHDL17_DWOG_081200-2606081200-dsw--0-ia5     08-Jun-2026 12:03:57                3150
swis2-VHDL20_DWEG_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:01:23                1158
swis2-VHDL20_DWEG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1391
swis2-VHDL20_DWEG_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:06                1265
swis2-VHDL20_DWEG_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1290
swis2-VHDL20_DWEG_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:01:21                1167
swis2-VHDL20_DWEG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1290
swis2-VHDL20_DWEG_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1372
swis2-VHDL20_DWEG_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:06                1356
swis2-VHDL20_DWEH_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:01:23                1198
swis2-VHDL20_DWEH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1434
swis2-VHDL20_DWEH_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:06                1269
swis2-VHDL20_DWEH_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1322
swis2-VHDL20_DWEH_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:01:21                1199
swis2-VHDL20_DWEH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1327
swis2-VHDL20_DWEH_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1417
swis2-VHDL20_DWEH_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:06                1345
swis2-VHDL20_DWEI_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:01:23                1067
swis2-VHDL20_DWEI_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1245
swis2-VHDL20_DWEI_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:06                1147
swis2-VHDL20_DWEI_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1208
swis2-VHDL20_DWEI_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:01:21                1085
swis2-VHDL20_DWEI_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1219
swis2-VHDL20_DWEI_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1419
swis2-VHDL20_DWEI_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:06                1406
swis2-VHDL20_DWHG_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:17                1426
swis2-VHDL20_DWHG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:45:04                1802
swis2-VHDL20_DWHG_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:45:01                1528
swis2-VHDL20_DWHG_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:45:07                1399
swis2-VHDL20_DWHG_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:16                1396
swis2-VHDL20_DWHG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:45:02                1455
swis2-VHDL20_DWHG_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:45:01                1533
swis2-VHDL20_DWHG_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:45:13                1280
swis2-VHDL20_DWHH_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:17                1425
swis2-VHDL20_DWHH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:45:04                1734
swis2-VHDL20_DWHH_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:45:01                1318
swis2-VHDL20_DWHH_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:45:07                1303
swis2-VHDL20_DWHH_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:16                1187
swis2-VHDL20_DWHH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:45:02                1473
swis2-VHDL20_DWHH_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:45:01                1547
swis2-VHDL20_DWHH_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:45:13                1289
swis2-VHDL20_DWLG_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:11                1011
swis2-VHDL20_DWLG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:21                1137
swis2-VHDL20_DWLG_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:31:00                 939
swis2-VHDL20_DWLG_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:26                 868
swis2-VHDL20_DWLG_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:12                 801
swis2-VHDL20_DWLG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:27                 908
swis2-VHDL20_DWLG_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:31:05                 883
swis2-VHDL20_DWLG_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:21                 827
swis2-VHDL20_DWLH_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:11                 951
swis2-VHDL20_DWLH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:21                1126
swis2-VHDL20_DWLH_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:31:00                1021
swis2-VHDL20_DWLH_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:26                1258
swis2-VHDL20_DWLH_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:12                1176
swis2-VHDL20_DWLH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:27                1286
swis2-VHDL20_DWLH_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:31:05                1261
swis2-VHDL20_DWLH_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:21                1058
swis2-VHDL20_DWLI_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:11                 844
swis2-VHDL20_DWLI_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:21                 970
swis2-VHDL20_DWLI_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:31:00                 941
swis2-VHDL20_DWLI_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:26                 932
swis2-VHDL20_DWLI_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:12                1011
swis2-VHDL20_DWLI_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:27                1118
swis2-VHDL20_DWLI_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:31:05                1093
swis2-VHDL20_DWLI_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:21                 953
swis2-VHDL20_DWMO_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:02                1182
swis2-VHDL20_DWMO_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1667
swis2-VHDL20_DWMO_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:00                1172
swis2-VHDL20_DWMO_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1042
swis2-VHDL20_DWMO_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:02                1051
swis2-VHDL20_DWMO_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1172
swis2-VHDL20_DWMO_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1307
swis2-VHDL20_DWMO_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:04                1027
swis2-VHDL20_DWMP_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:02                1386
swis2-VHDL20_DWMP_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1808
swis2-VHDL20_DWMP_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:00                1596
swis2-VHDL20_DWMP_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1409
swis2-VHDL20_DWMP_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:02                1417
swis2-VHDL20_DWMP_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1673
swis2-VHDL20_DWMP_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1601
swis2-VHDL20_DWMP_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:04                1439
swis2-VHDL20_DWPG_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:11                1040
swis2-VHDL20_DWPG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:21                1201
swis2-VHDL20_DWPG_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:31:00                1029
swis2-VHDL20_DWPG_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:26                1192
swis2-VHDL20_DWPG_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:12                1089
swis2-VHDL20_DWPG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:27                1197
swis2-VHDL20_DWPG_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:31:05                1172
swis2-VHDL20_DWPG_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:21                1074
swis2-VHDL20_DWPH_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:11                1027
swis2-VHDL20_DWPH_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:21                1159
swis2-VHDL20_DWPH_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:31:00                 998
swis2-VHDL20_DWPH_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:26                1288
swis2-VHDL20_DWPH_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:12                1203
swis2-VHDL20_DWPH_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:27                1279
swis2-VHDL20_DWPH_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:31:05                1254
swis2-VHDL20_DWPH_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:21                1068
swis2-VHDL20_DWSG_070400-2606070400-dsw--0-ia5     07-Jun-2026 05:00:17                1322
swis2-VHDL20_DWSG_070800-2606070800-dsw--0-ia5     07-Jun-2026 08:30:02                1559
swis2-VHDL20_DWSG_071800-2606071800-dsw--0-ia5     07-Jun-2026 18:30:02                1561
swis2-VHDL20_DWSG_080200-2606080200-dsw--0-ia5     08-Jun-2026 02:30:03                1353
swis2-VHDL20_DWSG_080400-2606080400-dsw--0-ia5     08-Jun-2026 05:00:16                1216
swis2-VHDL20_DWSG_080800-2606080800-dsw--0-ia5     08-Jun-2026 08:30:09                1357
swis2-VHDL20_DWSG_081800-2606081800-dsw--0-ia5     08-Jun-2026 18:30:06                1399
swis2-VHDL20_DWSG_090200-2606090200-dsw--0-ia5     09-Jun-2026 02:30:04                1090
wst04-VHDL20_DWEG_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:11              234237
wst04-VHDL20_DWEG_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:11              235152
wst04-VHDL20_DWEG_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:16              235362
wst04-VHDL20_DWEG_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:12              233979
wst04-VHDL20_DWEG_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:12              234035
wst04-VHDL20_DWEG_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:11              234819
wst04-VHDL20_DWEG_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:13              239265
wst04-VHDL20_DWEG_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:11              238740
wst04-VHDL20_DWEH_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:11              234028
wst04-VHDL20_DWEH_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:11              234936
wst04-VHDL20_DWEH_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:12              232195
wst04-VHDL20_DWEH_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:12              231020
wst04-VHDL20_DWEH_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:12              231407
wst04-VHDL20_DWEH_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:11              232243
wst04-VHDL20_DWEH_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:13              237839
wst04-VHDL20_DWEH_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:11              237338
wst04-VHDL20_DWEI_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:17              333920
wst04-VHDL20_DWEI_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:11              334304
wst04-VHDL20_DWEI_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:16              334878
wst04-VHDL20_DWEI_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:12              334045
wst04-VHDL20_DWEI_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:12              334081
wst04-VHDL20_DWEI_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:11              334374
wst04-VHDL20_DWEI_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:17              340218
wst04-VHDL20_DWEI_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:17              340000
wst04-VHDL20_DWHG_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:17              338357
wst04-VHDL20_DWHG_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:45:11              340694
wst04-VHDL20_DWHG_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:45:13              345521
wst04-VHDL20_DWHG_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:45:28              343971
wst04-VHDL20_DWHG_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:16              343745
wst04-VHDL20_DWHG_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:45:12              344734
wst04-VHDL20_DWHG_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:45:12              348666
wst04-VHDL20_DWHG_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:45:13              347343
wst04-VHDL20_DWHH_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:17              230911
wst04-VHDL20_DWHH_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:45:11              330997
wst04-VHDL20_DWHH_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:45:13              339162
wst04-VHDL20_DWHH_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:45:28              338870
wst04-VHDL20_DWHH_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:22              232855
wst04-VHDL20_DWHH_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:45:12              339066
wst04-VHDL20_DWHH_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:45:12              335140
wst04-VHDL20_DWHH_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:45:13              334844
wst04-VHDL20_DWLG_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:41              329297
wst04-VHDL20_DWLG_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:41              329563
wst04-VHDL20_DWLG_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:31:21              328835
wst04-VHDL20_DWLG_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:26              328563
wst04-VHDL20_DWLG_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:40              328629
wst04-VHDL20_DWLG_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:47              328832
wst04-VHDL20_DWLG_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:31:25              328641
wst04-VHDL20_DWLG_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:21              327922
wst04-VHDL20_DWLH_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:41              331373
wst04-VHDL20_DWLH_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:48              332012
wst04-VHDL20_DWLH_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:31:27              325383
wst04-VHDL20_DWLH_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:26              325340
wst04-VHDL20_DWLH_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:40              325415
wst04-VHDL20_DWLH_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:42              325683
wst04-VHDL20_DWLH_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:31:20              336525
wst04-VHDL20_DWLH_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:21              335646
wst04-VHDL20_DWLI_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:41              330454
wst04-VHDL20_DWLI_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:41              375615
wst04-VHDL20_DWLI_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:31:21              327681
wst04-VHDL20_DWLI_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:26              327471
wst04-VHDL20_DWLI_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:40              327704
wst04-VHDL20_DWLI_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:42              372540
wst04-VHDL20_DWLI_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:31:20              330847
wst04-VHDL20_DWLI_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:26              330113
wst04-VHDL20_DWMO_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:17              442101
wst04-VHDL20_DWMO_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:21              442677
wst04-VHDL20_DWMO_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:16              345904
wst04-VHDL20_DWMO_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:19              445070
wst04-VHDL20_DWMO_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:18              444976
wst04-VHDL20_DWMO_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:17              444719
wst04-VHDL20_DWMO_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:17              346742
wst04-VHDL20_DWMO_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:11              451382
wst04-VHDL20_DWMP_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:17              557167
wst04-VHDL20_DWMP_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:21              449841
wst04-VHDL20_DWMP_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:21              451884
wst04-VHDL20_DWMP_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:19              554278
wst04-VHDL20_DWMP_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:18              554256
wst04-VHDL20_DWMP_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:23              451728
wst04-VHDL20_DWMP_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:17              456144
wst04-VHDL20_DWMP_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:17              561943
wst04-VHDL20_DWPG_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:31              333974
wst04-VHDL20_DWPG_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:41              378801
wst04-VHDL20_DWPG_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:31:21              331037
wst04-VHDL20_DWPG_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:26              234992
wst04-VHDL20_DWPG_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:32              331013
wst04-VHDL20_DWPG_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:47              375777
wst04-VHDL20_DWPG_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:31:25              334879
wst04-VHDL20_DWPG_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:21              237523
wst04-VHDL20_DWPH_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:31              239083
wst04-VHDL20_DWPH_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:41              239318
wst04-VHDL20_DWPH_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:31:21              238923
wst04-VHDL20_DWPH_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:26              238986
wst04-VHDL20_DWPH_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:32              238999
wst04-VHDL20_DWPH_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:42              239134
wst04-VHDL20_DWPH_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:31:20              242488
wst04-VHDL20_DWPH_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:21              241714
wst04-VHDL20_DWSG_070400-2606070400-omedes--0.pdf  07-Jun-2026 05:00:11              336658
wst04-VHDL20_DWSG_070800-2606070800-omedes--0.pdf  07-Jun-2026 08:30:17              337551
wst04-VHDL20_DWSG_071800-2606071800-omedes--0.pdf  07-Jun-2026 18:30:16              343313
wst04-VHDL20_DWSG_080200-2606080200-omedes--0.pdf  08-Jun-2026 02:30:12              342572
wst04-VHDL20_DWSG_080400-2606080400-omedes--0.pdf  08-Jun-2026 05:00:12              342035
wst04-VHDL20_DWSG_080800-2606080800-omedes--0.pdf  08-Jun-2026 08:30:17              343063
wst04-VHDL20_DWSG_081800-2606081800-omedes--0.pdf  08-Jun-2026 18:30:17              347060
wst04-VHDL20_DWSG_090200-2606090200-omedes--0.pdf  09-Jun-2026 02:30:11              347079