Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Nov-2025 14:22:09 4605
FPDL13_DWMZ_150600 15-Nov-2025 14:23:20 5352
SXDL31_DWAV_140800 14-Nov-2025 08:43:03 10677
SXDL31_DWAV_141800 14-Nov-2025 18:09:14 8802
SXDL31_DWAV_150800 15-Nov-2025 08:13:23 16928
SXDL31_DWAV_151800 15-Nov-2025 17:47:19 9497
SXDL31_DWAV_LATEST 15-Nov-2025 17:47:19 9497
SXDL33_DWAV_140000 14-Nov-2025 10:50:40 10956
SXDL33_DWAV_150000 15-Nov-2025 10:34:37 6268
SXDL33_DWAV_LATEST 15-Nov-2025 10:34:37 6268
ber01-FWDL39_DWMS_141230-2511141230-dsw--0-ia5 14-Nov-2025 12:11:47 2155
ber01-FWDL39_DWMS_151230-2511151230-dsw--0-ia5 15-Nov-2025 12:21:07 1157
ber01-VHDL13_DWEH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:28:11 2254
ber01-VHDL13_DWEH_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:58:18 2334
ber01-VHDL13_DWEH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:28:15 2334
ber01-VHDL13_DWEH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:28:12 2124
ber01-VHDL13_DWEH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:28:11 2504
ber01-VHDL13_DWEH_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:58:12 2486
ber01-VHDL13_DWEH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:28:17 2559
ber01-VHDL13_DWEH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:12 2483
ber01-VHDL13_DWHG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 3675
ber01-VHDL13_DWHG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:07 3674
ber01-VHDL13_DWHG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 3670
ber01-VHDL13_DWHG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:07 3299
ber01-VHDL13_DWHG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:06 3352
ber01-VHDL13_DWHG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:06 3112
ber01-VHDL13_DWHG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:07 3251
ber01-VHDL13_DWHG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2689
ber01-VHDL13_DWHH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 3402
ber01-VHDL13_DWHH_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:07 3402
ber01-VHDL13_DWHH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 3495
ber01-VHDL13_DWHH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:07 2987
ber01-VHDL13_DWHH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:06 3368
ber01-VHDL13_DWHH_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:06 3131
ber01-VHDL13_DWHH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:07 3251
ber01-VHDL13_DWHH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 3010
ber01-VHDL13_DWLG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:01 2445
ber01-VHDL13_DWLG_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:59:56 2485
ber01-VHDL13_DWLG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2431
ber01-VHDL13_DWLG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2126
ber01-VHDL13_DWLG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 2484
ber01-VHDL13_DWLG_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:59:56 2544
ber01-VHDL13_DWLG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 2616
ber01-VHDL13_DWLG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2470
ber01-VHDL13_DWLH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:01 2276
ber01-VHDL13_DWLH_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:59:56 2306
ber01-VHDL13_DWLH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2372
ber01-VHDL13_DWLH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2213
ber01-VHDL13_DWLH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 2542
ber01-VHDL13_DWLH_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:59:56 2443
ber01-VHDL13_DWLH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 2341
ber01-VHDL13_DWLH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2234
ber01-VHDL13_DWLI_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:01 2047
ber01-VHDL13_DWLI_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:59:56 2114
ber01-VHDL13_DWLI_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2181
ber01-VHDL13_DWLI_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 1897
ber01-VHDL13_DWLI_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 2284
ber01-VHDL13_DWLI_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:59:56 2386
ber01-VHDL13_DWLI_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 2351
ber01-VHDL13_DWLI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2175
ber01-VHDL13_DWMG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 4186
ber01-VHDL13_DWMG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:01 4186
ber01-VHDL13_DWMG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 3141
ber01-VHDL13_DWMG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2788
ber01-VHDL13_DWMG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 4883
ber01-VHDL13_DWMG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:01 4823
ber01-VHDL13_DWMG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 4097
ber01-VHDL13_DWMG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2866
ber01-VHDL13_DWMO_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 3699
ber01-VHDL13_DWMO_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:01 3660
ber01-VHDL13_DWMO_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2679
ber01-VHDL13_DWMO_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2460
ber01-VHDL13_DWMO_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 4110
ber01-VHDL13_DWMO_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:01 3974
ber01-VHDL13_DWMO_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 3662
ber01-VHDL13_DWMO_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2505
ber01-VHDL13_DWMP_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 4385
ber01-VHDL13_DWMP_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:01 4385
ber01-VHDL13_DWMP_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 3270
ber01-VHDL13_DWMP_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2974
ber01-VHDL13_DWMP_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 4786
ber01-VHDL13_DWMP_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:01 4673
ber01-VHDL13_DWMP_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 4009
ber01-VHDL13_DWMP_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 3137
ber01-VHDL13_DWOG_140300-2511140300-dsw--0-ia5 14-Nov-2025 04:00:01 4686
ber01-VHDL13_DWOG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 4724
ber01-VHDL13_DWOG_141700-2511141700-dsw--0-ia5 14-Nov-2025 19:00:03 4096
ber01-VHDL13_DWOG_141700_COR-2511141700-dsw--0-ia5 14-Nov-2025 19:20:36 4271
ber01-VHDL13_DWOG_150300-2511150300-dsw--0-ia5 15-Nov-2025 04:00:06 4234
ber01-VHDL13_DWOG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 4172
ber01-VHDL13_DWOG_151700-2511151700-dsw--0-ia5 15-Nov-2025 19:00:02 3638
ber01-VHDL13_DWOH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:28:11 2198
ber01-VHDL13_DWOH_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:58:11 2267
ber01-VHDL13_DWOH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:28:15 2047
ber01-VHDL13_DWOH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:28:16 2273
ber01-VHDL13_DWOH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:28:17 2325
ber01-VHDL13_DWOH_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:58:16 2386
ber01-VHDL13_DWOH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:28:17 2513
ber01-VHDL13_DWOH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:12 2469
ber01-VHDL13_DWOI_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:28:17 2292
ber01-VHDL13_DWOI_140400-2511140400-dsw--0-ia5 14-Nov-2025 05:58:18 2354
ber01-VHDL13_DWOI_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:28:11 2168
ber01-VHDL13_DWOI_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:28:12 2587
ber01-VHDL13_DWOI_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:28:11 2579
ber01-VHDL13_DWOI_150400-2511150400-dsw--0-ia5 15-Nov-2025 05:58:16 2552
ber01-VHDL13_DWOI_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:28:13 2656
ber01-VHDL13_DWOI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:28:16 2483
ber01-VHDL13_DWON_140358-2511140358-dsw--0-ia5 14-Nov-2025 03:58:21 3958
ber01-VHDL13_DWON_140630-2511140630-dsw--0-ia5 14-Nov-2025 06:30:09 4409
ber01-VHDL13_DWON_140728-2511140728-dsw--0-ia5 14-Nov-2025 07:28:32 4503
ber01-VHDL13_DWON_140915-2511140915-dsw--0-ia5 14-Nov-2025 09:15:52 4503
ber01-VHDL13_DWON_141513-2511141513-dsw--0-ia5 14-Nov-2025 15:14:01 3889
ber01-VHDL13_DWON_141824-2511141824-dsw--0-ia5 14-Nov-2025 18:24:17 4055
ber01-VHDL13_DWON_141920-2511141920-dsw--0-ia5 14-Nov-2025 19:20:28 4055
ber01-VHDL13_DWON_142336-2511142336-dsw--0-ia5 14-Nov-2025 23:36:16 3903
ber01-VHDL13_DWON_150350-2511150350-dsw--0-ia5 15-Nov-2025 03:51:04 3903
ber01-VHDL13_DWON_150626-2511150626-dsw--0-ia5 15-Nov-2025 06:26:22 4422
ber01-VHDL13_DWON_150639-2511150639-dsw--0-ia5 15-Nov-2025 06:39:11 4547
ber01-VHDL13_DWON_150911-2511150911-dsw--0-ia5 15-Nov-2025 09:11:07 4547
ber01-VHDL13_DWON_151207-2511151207-dsw--0-ia5 15-Nov-2025 12:07:27 4547
ber01-VHDL13_DWON_151531-2511151531-dsw--0-ia5 15-Nov-2025 15:31:35 4420
ber01-VHDL13_DWON_151840-2511151840-dsw--0-ia5 15-Nov-2025 18:40:27 3615
ber01-VHDL13_DWPG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:01 2269
ber01-VHDL13_DWPG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:01 2223
ber01-VHDL13_DWPG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2191
ber01-VHDL13_DWPG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 1784
ber01-VHDL13_DWPG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 2199
ber01-VHDL13_DWPG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:01 2255
ber01-VHDL13_DWPG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:07 2244
ber01-VHDL13_DWPG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2076
ber01-VHDL13_DWPH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:01 2497
ber01-VHDL13_DWPH_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:01 2479
ber01-VHDL13_DWPH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 2436
ber01-VHDL13_DWPH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2232
ber01-VHDL13_DWPH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 2678
ber01-VHDL13_DWPH_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:01 2701
ber01-VHDL13_DWPH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:07 2714
ber01-VHDL13_DWPH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:06 2261
ber01-VHDL13_DWSG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:30:07 3005
ber01-VHDL13_DWSG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:07 3302
ber01-VHDL13_DWSG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:30:06 3401
ber01-VHDL13_DWSG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:30:02 2825
ber01-VHDL13_DWSG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:30:02 3498
ber01-VHDL13_DWSG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:06 2910
ber01-VHDL13_DWSG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:30:02 2911
ber01-VHDL13_DWSG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:30:02 2625
ber01-VHDL17_DWOG_141200-2511141200-dsw--0-ia5 14-Nov-2025 12:33:12 3381
ber01-VHDL17_DWOG_151200-2511151200-dsw--0-ia5 15-Nov-2025 12:32:23 3310
swis2-VHDL20_DWEG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:07 2474
swis2-VHDL20_DWEG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:15:07 2587
swis2-VHDL20_DWEG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:06 2522
swis2-VHDL20_DWEG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:01 2599
swis2-VHDL20_DWEG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:08 2601
swis2-VHDL20_DWEG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:15:06 2706
swis2-VHDL20_DWEG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:06 3158
swis2-VHDL20_DWEG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:02 2795
swis2-VHDL20_DWEH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:07 2575
swis2-VHDL20_DWEH_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:15:07 2666
swis2-VHDL20_DWEH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:06 2834
swis2-VHDL20_DWEH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:01 2478
swis2-VHDL20_DWEH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:08 2825
swis2-VHDL20_DWEH_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:15:06 2818
swis2-VHDL20_DWEH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:06 3215
swis2-VHDL20_DWEH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:03 2837
swis2-VHDL20_DWEI_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:07 2584
swis2-VHDL20_DWEI_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:15:07 2705
swis2-VHDL20_DWEI_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:06 2690
swis2-VHDL20_DWEI_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:01 2938
swis2-VHDL20_DWEI_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:08 2871
swis2-VHDL20_DWEI_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:15:06 2903
swis2-VHDL20_DWEI_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:06 3335
swis2-VHDL20_DWEI_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:02 2834
swis2-VHDL20_DWHG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:02 3861
swis2-VHDL20_DWHG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:07 3857
swis2-VHDL20_DWHG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:01 4206
swis2-VHDL20_DWHG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:04 3482
swis2-VHDL20_DWHG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:02 3538
swis2-VHDL20_DWHG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:06 3295
swis2-VHDL20_DWHG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:06 3832
swis2-VHDL20_DWHG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:07 2872
swis2-VHDL20_DWHH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:02 3588
swis2-VHDL20_DWHH_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:07 3588
swis2-VHDL20_DWHH_140800-2511140800-dsw--0-ia5 14-Nov-2025 10:36:56 4099
swis2-VHDL20_DWHH_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:04 3173
swis2-VHDL20_DWHH_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:02 3554
swis2-VHDL20_DWHH_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:06 3317
swis2-VHDL20_DWHH_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:06 3854
swis2-VHDL20_DWHH_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:07 3196
swis2-VHDL20_DWLG_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:02 2815
swis2-VHDL20_DWLG_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:26 2852
swis2-VHDL20_DWLG_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:01 2948
swis2-VHDL20_DWLG_141800-2511141800-dsw--0-ia5 14-Nov-2025 19:45:01 2493
swis2-VHDL20_DWLG_150200-2511150200-dsw--0-ia5 15-Nov-2025 03:45:02 2854
swis2-VHDL20_DWLG_150400-2511150400-dsw--0-ia5 15-Nov-2025 06:00:21 2912
swis2-VHDL20_DWLG_150800-2511150800-dsw--0-ia5 15-Nov-2025 09:45:02 3122
swis2-VHDL20_DWLG_151800-2511151800-dsw--0-ia5 15-Nov-2025 19:45:02 2838
swis2-VHDL20_DWLH_140200-2511140200-dsw--0-ia5 14-Nov-2025 03:45:02 2653
swis2-VHDL20_DWLH_140400-2511140400-dsw--0-ia5 14-Nov-2025 06:00:26 2680
swis2-VHDL20_DWLH_140800-2511140800-dsw--0-ia5 14-Nov-2025 09:45:01 2900
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wst04-VHDL20_DWEH_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:20 228313
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wst04-VHDL20_DWEI_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:20 324663
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wst04-VHDL20_DWHH_140400-2511140400-omedes--0.pdf 14-Nov-2025 06:00:11 334602
wst04-VHDL20_DWHH_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:17 334120
wst04-VHDL20_DWHH_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:12 334566
wst04-VHDL20_DWHH_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:00:11 334063
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wst04-VHDL20_DWLG_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:40:32 310189
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wst04-VHDL20_DWLH_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:40:21 313483
wst04-VHDL20_DWLH_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:40:22 313653
wst04-VHDL20_DWLH_150400-2511150400-omedes--0.pdf 15-Nov-2025 05:59:42 313543
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wst04-VHDL20_DWLH_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:40:21 309270
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wst04-VHDL20_DWLI_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:40:41 308221
wst04-VHDL20_DWLI_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:40:42 308017
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wst04-VHDL20_DWMG_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:16 526722
wst04-VHDL20_DWMG_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:15:16 526640
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wst04-VHDL20_DWMO_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:21 426341
wst04-VHDL20_DWMO_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:12 429629
wst04-VHDL20_DWMO_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:15:16 429997
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wst04-VHDL20_DWMP_140400-2511140400-omedes--0.pdf 14-Nov-2025 06:15:23 535240
wst04-VHDL20_DWMP_140800-2511140800-omedes--0.pdf 14-Nov-2025 09:45:16 538007
wst04-VHDL20_DWMP_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:21 537261
wst04-VHDL20_DWMP_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:20 537716
wst04-VHDL20_DWMP_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:15:16 539544
wst04-VHDL20_DWMP_150800-2511150800-omedes--0.pdf 15-Nov-2025 09:45:26 547169
wst04-VHDL20_DWMP_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:45:21 544781
wst04-VHDL20_DWPG_140200-2511140200-omedes--0.pdf 14-Nov-2025 03:45:17 313062
wst04-VHDL20_DWPG_140400-2511140400-omedes--0.pdf 14-Nov-2025 06:00:11 313025
wst04-VHDL20_DWPG_140800-2511140800-omedes--0.pdf 14-Nov-2025 09:45:12 365480
wst04-VHDL20_DWPG_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:11 320595
wst04-VHDL20_DWPG_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:16 321444
wst04-VHDL20_DWPG_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:00:11 321206
wst04-VHDL20_DWPG_150800-2511150800-omedes--0.pdf 15-Nov-2025 09:45:12 363239
wst04-VHDL20_DWPG_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:45:11 318811
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wst04-VHDL20_DWPH_140400-2511140400-omedes--0.pdf 14-Nov-2025 06:00:11 228884
wst04-VHDL20_DWPH_140800-2511140800-omedes--0.pdf 14-Nov-2025 09:45:12 282562
wst04-VHDL20_DWPH_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:11 282422
wst04-VHDL20_DWPH_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:16 237910
wst04-VHDL20_DWPH_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:00:11 237992
wst04-VHDL20_DWPH_150800-2511150800-omedes--0.pdf 15-Nov-2025 09:45:12 275064
wst04-VHDL20_DWPH_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:45:11 274392
wst04-VHDL20_DWSG_140200-2511140200-omedes--0.pdf 14-Nov-2025 03:45:11 346552
wst04-VHDL20_DWSG_140400-2511140400-omedes--0.pdf 14-Nov-2025 06:15:13 347081
wst04-VHDL20_DWSG_140800-2511140800-omedes--0.pdf 14-Nov-2025 09:45:16 349729
wst04-VHDL20_DWSG_141300-2511141300-omedes--0.pdf 14-Nov-2025 14:45:14 326942
wst04-VHDL20_DWSG_141800-2511141800-omedes--0.pdf 14-Nov-2025 19:45:11 326016
wst04-VHDL20_DWSG_150200-2511150200-omedes--0.pdf 15-Nov-2025 03:45:12 327165
wst04-VHDL20_DWSG_150400-2511150400-omedes--0.pdf 15-Nov-2025 06:15:11 326407
wst04-VHDL20_DWSG_150800-2511150800-omedes--0.pdf 15-Nov-2025 09:45:12 324657
wst04-VHDL20_DWSG_151300-2511151300-omedes--0.pdf 15-Nov-2025 14:45:12 324792
wst04-VHDL20_DWSG_151800-2511151800-omedes--0.pdf 15-Nov-2025 19:45:11 324381