Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_200600 20-Dec-2024 14:27 4115
FPDL13_DWMZ_210600 21-Dec-2024 12:38 3437
SXDL31_DWAV_191800 19-Dec-2024 18:01 5744
SXDL31_DWAV_200800 20-Dec-2024 09:10 10104
SXDL31_DWAV_201800 20-Dec-2024 17:43 9209
SXDL31_DWAV_210800 21-Dec-2024 09:33 10957
SXDL31_DWAV_LATEST 21-Dec-2024 09:33 10957
SXDL33_DWAV_200000 20-Dec-2024 11:17 10931
SXDL33_DWAV_210000 21-Dec-2024 11:36 9771
SXDL33_DWAV_LATEST 21-Dec-2024 11:36 9771
ber01-FWDL39_DWMS_201230-2412201230-dsw--0-ia5 20-Dec-2024 13:03 1618
ber01-FWDL39_DWMS_211230-2412211230-dsw--0-ia5 21-Dec-2024 13:12 1810
ber01-VHDL13_DWEH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:28 3612
ber01-VHDL13_DWEH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:28 3662
ber01-VHDL13_DWEH_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:58 3905
ber01-VHDL13_DWEH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:28 3864
ber01-VHDL13_DWEH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:28 4213
ber01-VHDL13_DWEH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:28 3788
ber01-VHDL13_DWEH_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:58 4138
ber01-VHDL13_DWEH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:28 4227
ber01-VHDL13_DWHG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3353
ber01-VHDL13_DWHG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3600
ber01-VHDL13_DWHG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3571
ber01-VHDL13_DWHG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3615
ber01-VHDL13_DWHG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3699
ber01-VHDL13_DWHG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3755
ber01-VHDL13_DWHG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3758
ber01-VHDL13_DWHG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3995
ber01-VHDL13_DWHH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2741
ber01-VHDL13_DWHH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 2934
ber01-VHDL13_DWHH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2831
ber01-VHDL13_DWHH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 2926
ber01-VHDL13_DWHH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2929
ber01-VHDL13_DWHH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3095
ber01-VHDL13_DWHH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3095
ber01-VHDL13_DWHH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3383
ber01-VHDL13_DWLG_191733-2412191733-dsw--0-ia5 19-Dec-2024 17:33 2862
ber01-VHDL13_DWLG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2657
ber01-VHDL13_DWLG_191833-2412191833-dsw--0-ia5 19-Dec-2024 18:33 2663
ber01-VHDL13_DWLG_192033-2412192033-dsw--0-ia5 19-Dec-2024 20:33 2663
ber01-VHDL13_DWLG_192133-2412192133-dsw--0-ia5 19-Dec-2024 21:33 2663
ber01-VHDL13_DWLG_200133-2412200133-dsw--0-ia5 20-Dec-2024 01:33 2871
ber01-VHDL13_DWLG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3208
ber01-VHDL13_DWLG_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:59 3143
ber01-VHDL13_DWLG_200633-2412200633-dsw--0-ia5 20-Dec-2024 06:33 3149
ber01-VHDL13_DWLG_200733-2412200733-dsw--0-ia5 20-Dec-2024 07:33 3149
ber01-VHDL13_DWLG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3427
ber01-VHDL13_DWLG_200833-2412200833-dsw--0-ia5 20-Dec-2024 08:33 3149
ber01-VHDL13_DWLG_201033-2412201033-dsw--0-ia5 20-Dec-2024 10:33 3436
ber01-VHDL13_DWLG_201133-2412201133-dsw--0-ia5 20-Dec-2024 11:33 3436
ber01-VHDL13_DWLG_201233-2412201233-dsw--0-ia5 20-Dec-2024 12:33 3436
ber01-VHDL13_DWLG_201433-2412201433-dsw--0-ia5 20-Dec-2024 14:33 2928
ber01-VHDL13_DWLG_201533-2412201533-dsw--0-ia5 20-Dec-2024 15:33 2928
ber01-VHDL13_DWLG_201633-2412201633-dsw--0-ia5 20-Dec-2024 16:33 2928
ber01-VHDL13_DWLG_201733-2412201733-dsw--0-ia5 20-Dec-2024 17:33 2928
ber01-VHDL13_DWLG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2671
ber01-VHDL13_DWLG_201833-2412201833-dsw--0-ia5 20-Dec-2024 18:33 2928
ber01-VHDL13_DWLG_202033-2412202033-dsw--0-ia5 20-Dec-2024 20:33 2677
ber01-VHDL13_DWLG_202133-2412202133-dsw--0-ia5 20-Dec-2024 21:33 2677
ber01-VHDL13_DWLG_210133-2412210133-dsw--0-ia5 21-Dec-2024 01:33 2709
ber01-VHDL13_DWLG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3198
ber01-VHDL13_DWLG_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:59 3312
ber01-VHDL13_DWLG_210633-2412210633-dsw--0-ia5 21-Dec-2024 06:33 3318
ber01-VHDL13_DWLG_210733-2412210733-dsw--0-ia5 21-Dec-2024 07:33 3317
ber01-VHDL13_DWLG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3306
ber01-VHDL13_DWLG_210833-2412210833-dsw--0-ia5 21-Dec-2024 08:33 3315
ber01-VHDL13_DWLG_211033-2412211033-dsw--0-ia5 21-Dec-2024 10:33 3346
ber01-VHDL13_DWLG_211133-2412211133-dsw--0-ia5 21-Dec-2024 11:33 3346
ber01-VHDL13_DWLG_211233-2412211233-dsw--0-ia5 21-Dec-2024 12:33 3238
ber01-VHDL13_DWLG_211433-2412211433-dsw--0-ia5 21-Dec-2024 14:33 3212
ber01-VHDL13_DWLG_211533-2412211533-dsw--0-ia5 21-Dec-2024 15:33 3212
ber01-VHDL13_DWLG_211633-2412211633-dsw--0-ia5 21-Dec-2024 16:33 3212
ber01-VHDL13_DWLH_191733-2412191733-dsw--0-ia5 19-Dec-2024 17:33 2495
ber01-VHDL13_DWLH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2927
ber01-VHDL13_DWLH_191833-2412191833-dsw--0-ia5 19-Dec-2024 18:33 2936
ber01-VHDL13_DWLH_192033-2412192033-dsw--0-ia5 19-Dec-2024 20:33 2936
ber01-VHDL13_DWLH_192133-2412192133-dsw--0-ia5 19-Dec-2024 21:33 2936
ber01-VHDL13_DWLH_200133-2412200133-dsw--0-ia5 20-Dec-2024 01:33 3135
ber01-VHDL13_DWLH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3349
ber01-VHDL13_DWLH_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:59 3331
ber01-VHDL13_DWLH_200633-2412200633-dsw--0-ia5 20-Dec-2024 06:33 3340
ber01-VHDL13_DWLH_200733-2412200733-dsw--0-ia5 20-Dec-2024 07:33 3340
ber01-VHDL13_DWLH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3670
ber01-VHDL13_DWLH_200833-2412200833-dsw--0-ia5 20-Dec-2024 08:33 3340
ber01-VHDL13_DWLH_201033-2412201033-dsw--0-ia5 20-Dec-2024 10:33 3679
ber01-VHDL13_DWLH_201133-2412201133-dsw--0-ia5 20-Dec-2024 11:33 3679
ber01-VHDL13_DWLH_201233-2412201233-dsw--0-ia5 20-Dec-2024 12:33 3679
ber01-VHDL13_DWLH_201433-2412201433-dsw--0-ia5 20-Dec-2024 14:33 3135
ber01-VHDL13_DWLH_201533-2412201533-dsw--0-ia5 20-Dec-2024 15:33 3135
ber01-VHDL13_DWLH_201633-2412201633-dsw--0-ia5 20-Dec-2024 16:33 3135
ber01-VHDL13_DWLH_201733-2412201733-dsw--0-ia5 20-Dec-2024 17:33 3135
ber01-VHDL13_DWLH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2767
ber01-VHDL13_DWLH_201833-2412201833-dsw--0-ia5 20-Dec-2024 18:33 3135
ber01-VHDL13_DWLH_202033-2412202033-dsw--0-ia5 20-Dec-2024 20:33 2776
ber01-VHDL13_DWLH_202133-2412202133-dsw--0-ia5 20-Dec-2024 21:33 2776
ber01-VHDL13_DWLH_210133-2412210133-dsw--0-ia5 21-Dec-2024 01:33 2690
ber01-VHDL13_DWLH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 2678
ber01-VHDL13_DWLH_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:59 2805
ber01-VHDL13_DWLH_210633-2412210633-dsw--0-ia5 21-Dec-2024 06:33 2814
ber01-VHDL13_DWLH_210733-2412210733-dsw--0-ia5 21-Dec-2024 07:33 3005
ber01-VHDL13_DWLH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 2996
ber01-VHDL13_DWLH_210833-2412210833-dsw--0-ia5 21-Dec-2024 08:33 3005
ber01-VHDL13_DWLH_211033-2412211033-dsw--0-ia5 21-Dec-2024 10:33 3028
ber01-VHDL13_DWLH_211133-2412211133-dsw--0-ia5 21-Dec-2024 11:33 3028
ber01-VHDL13_DWLH_211233-2412211233-dsw--0-ia5 21-Dec-2024 12:33 3024
ber01-VHDL13_DWLH_211433-2412211433-dsw--0-ia5 21-Dec-2024 14:33 2897
ber01-VHDL13_DWLH_211533-2412211533-dsw--0-ia5 21-Dec-2024 15:33 2897
ber01-VHDL13_DWLH_211633-2412211633-dsw--0-ia5 21-Dec-2024 16:33 2897
ber01-VHDL13_DWLI_191733-2412191733-dsw--0-ia5 19-Dec-2024 17:33 2613
ber01-VHDL13_DWLI_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2673
ber01-VHDL13_DWLI_191833-2412191833-dsw--0-ia5 19-Dec-2024 18:33 2679
ber01-VHDL13_DWLI_192033-2412192033-dsw--0-ia5 19-Dec-2024 20:33 2679
ber01-VHDL13_DWLI_192133-2412192133-dsw--0-ia5 19-Dec-2024 21:33 2679
ber01-VHDL13_DWLI_200133-2412200133-dsw--0-ia5 20-Dec-2024 01:33 2855
ber01-VHDL13_DWLI_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 2985
ber01-VHDL13_DWLI_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:59 3029
ber01-VHDL13_DWLI_200633-2412200633-dsw--0-ia5 20-Dec-2024 06:33 3032
ber01-VHDL13_DWLI_200733-2412200733-dsw--0-ia5 20-Dec-2024 07:33 3032
ber01-VHDL13_DWLI_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3321
ber01-VHDL13_DWLI_200833-2412200833-dsw--0-ia5 20-Dec-2024 08:33 3032
ber01-VHDL13_DWLI_201033-2412201033-dsw--0-ia5 20-Dec-2024 10:33 3327
ber01-VHDL13_DWLI_201133-2412201133-dsw--0-ia5 20-Dec-2024 11:33 3327
ber01-VHDL13_DWLI_201233-2412201233-dsw--0-ia5 20-Dec-2024 12:33 3327
ber01-VHDL13_DWLI_201433-2412201433-dsw--0-ia5 20-Dec-2024 14:33 2945
ber01-VHDL13_DWLI_201533-2412201533-dsw--0-ia5 20-Dec-2024 15:33 2945
ber01-VHDL13_DWLI_201633-2412201633-dsw--0-ia5 20-Dec-2024 16:33 2945
ber01-VHDL13_DWLI_201733-2412201733-dsw--0-ia5 20-Dec-2024 17:33 2945
ber01-VHDL13_DWLI_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2843
ber01-VHDL13_DWLI_201833-2412201833-dsw--0-ia5 20-Dec-2024 18:33 2945
ber01-VHDL13_DWLI_202033-2412202033-dsw--0-ia5 20-Dec-2024 20:33 2849
ber01-VHDL13_DWLI_202133-2412202133-dsw--0-ia5 20-Dec-2024 21:33 2849
ber01-VHDL13_DWLI_210133-2412210133-dsw--0-ia5 21-Dec-2024 01:33 2834
ber01-VHDL13_DWLI_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3044
ber01-VHDL13_DWLI_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:59 3198
ber01-VHDL13_DWLI_210633-2412210633-dsw--0-ia5 21-Dec-2024 06:33 3201
ber01-VHDL13_DWLI_210733-2412210733-dsw--0-ia5 21-Dec-2024 07:33 3445
ber01-VHDL13_DWLI_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3437
ber01-VHDL13_DWLI_210833-2412210833-dsw--0-ia5 21-Dec-2024 08:33 3443
ber01-VHDL13_DWLI_211033-2412211033-dsw--0-ia5 21-Dec-2024 10:33 3430
ber01-VHDL13_DWLI_211133-2412211133-dsw--0-ia5 21-Dec-2024 11:33 3430
ber01-VHDL13_DWLI_211233-2412211233-dsw--0-ia5 21-Dec-2024 12:33 3390
ber01-VHDL13_DWLI_211433-2412211433-dsw--0-ia5 21-Dec-2024 14:33 3261
ber01-VHDL13_DWLI_211533-2412211533-dsw--0-ia5 21-Dec-2024 15:33 3261
ber01-VHDL13_DWLI_211633-2412211633-dsw--0-ia5 21-Dec-2024 16:33 3261
ber01-VHDL13_DWMG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3536
ber01-VHDL13_DWMG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3596
ber01-VHDL13_DWMG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3351
ber01-VHDL13_DWMG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3527
ber01-VHDL13_DWMG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3554
ber01-VHDL13_DWMG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3904
ber01-VHDL13_DWMG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3906
ber01-VHDL13_DWMG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 4097
ber01-VHDL13_DWMO_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3107
ber01-VHDL13_DWMO_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3256
ber01-VHDL13_DWMO_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3210
ber01-VHDL13_DWMO_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3238
ber01-VHDL13_DWMO_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3046
ber01-VHDL13_DWMO_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3339
ber01-VHDL13_DWMO_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3316
ber01-VHDL13_DWMO_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3344
ber01-VHDL13_DWMP_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3563
ber01-VHDL13_DWMP_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3603
ber01-VHDL13_DWMP_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3558
ber01-VHDL13_DWMP_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3558
ber01-VHDL13_DWMP_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3590
ber01-VHDL13_DWMP_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3835
ber01-VHDL13_DWMP_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3622
ber01-VHDL13_DWMP_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3622
ber01-VHDL13_DWOG_191700-2412191700-dsw--0-ia5 19-Dec-2024 19:00 4766
ber01-VHDL13_DWOG_200300-2412200300-dsw--0-ia5 20-Dec-2024 04:00 5715
ber01-VHDL13_DWOG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 5541
ber01-VHDL13_DWOG_201700-2412201700-dsw--0-ia5 20-Dec-2024 19:00 4868
ber01-VHDL13_DWOG_210300-2412210300-dsw--0-ia5 21-Dec-2024 04:00 6590
ber01-VHDL13_DWOG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 6432
ber01-VHDL13_DWOH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:28 3285
ber01-VHDL13_DWOH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:28 3464
ber01-VHDL13_DWOH_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:58 3831
ber01-VHDL13_DWOH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:28 3749
ber01-VHDL13_DWOH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:28 3941
ber01-VHDL13_DWOH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:28 3639
ber01-VHDL13_DWOH_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:58 3879
ber01-VHDL13_DWOH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:28 3912
ber01-VHDL13_DWOI_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:28 3226
ber01-VHDL13_DWOI_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:28 3317
ber01-VHDL13_DWOI_200400-2412200400-dsw--0-ia5 20-Dec-2024 05:58 3809
ber01-VHDL13_DWOI_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:28 3770
ber01-VHDL13_DWOI_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:28 4050
ber01-VHDL13_DWOI_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:28 3630
ber01-VHDL13_DWOI_210400-2412210400-dsw--0-ia5 21-Dec-2024 05:58 3735
ber01-VHDL13_DWOI_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:28 3792
ber01-VHDL13_DWON_191830-2412191830-dsw--0-ia5 19-Dec-2024 18:30 3274
ber01-VHDL13_DWON_191943-2412191943-dsw--0-ia5 19-Dec-2024 19:43 3520
ber01-VHDL13_DWON_192213-2412192213-dsw--0-ia5 19-Dec-2024 22:13 3551
ber01-VHDL13_DWON_192344-2412192344-dsw--0-ia5 19-Dec-2024 23:45 4257
ber01-VHDL13_DWON_200003-2412200003-dsw--0-ia5 20-Dec-2024 00:03 4257
ber01-VHDL13_DWON_200152-2412200152-dsw--0-ia5 20-Dec-2024 01:52 4198
ber01-VHDL13_DWON_200341-2412200341-dsw--0-ia5 20-Dec-2024 03:41 4198
ber01-VHDL13_DWON_200618-2412200618-dsw--0-ia5 20-Dec-2024 06:18 3868
ber01-VHDL13_DWON_200627-2412200627-dsw--0-ia5 20-Dec-2024 06:27 4323
ber01-VHDL13_DWON_200638-2412200638-dsw--0-ia5 20-Dec-2024 06:38 4430
ber01-VHDL13_DWON_200906-2412200906-dsw--0-ia5 20-Dec-2024 09:07 4436
ber01-VHDL13_DWON_201012-2412201012-dsw--0-ia5 20-Dec-2024 10:12 4436
ber01-VHDL13_DWON_201450-2412201450-dsw--0-ia5 20-Dec-2024 14:50 4173
ber01-VHDL13_DWON_201514-2412201514-dsw--0-ia5 20-Dec-2024 15:14 4119
ber01-VHDL13_DWON_201814-2412201814-dsw--0-ia5 20-Dec-2024 18:14 3682
ber01-VHDL13_DWON_201952-2412201952-dsw--0-ia5 20-Dec-2024 19:52 4027
ber01-VHDL13_DWON_202033-2412202033-dsw--0-ia5 20-Dec-2024 20:33 4422
ber01-VHDL13_DWON_202230-2412202230-dsw--0-ia5 20-Dec-2024 22:30 4406
ber01-VHDL13_DWON_202344-2412202344-dsw--0-ia5 20-Dec-2024 23:44 5204
ber01-VHDL13_DWON_210008-2412210008-dsw--0-ia5 21-Dec-2024 00:08 5204
ber01-VHDL13_DWON_210146-2412210146-dsw--0-ia5 21-Dec-2024 01:46 5218
ber01-VHDL13_DWON_210340-2412210340-dsw--0-ia5 21-Dec-2024 03:41 5217
ber01-VHDL13_DWON_210629-2412210629-dsw--0-ia5 21-Dec-2024 06:29 4243
ber01-VHDL13_DWON_210635-2412210635-dsw--0-ia5 21-Dec-2024 06:35 4305
ber01-VHDL13_DWON_210636-2412210636-dsw--0-ia5 21-Dec-2024 06:36 4329
ber01-VHDL13_DWON_210727-2412210727-dsw--0-ia5 21-Dec-2024 07:27 5089
ber01-VHDL13_DWON_210736-2412210736-dsw--0-ia5 21-Dec-2024 07:36 5089
ber01-VHDL13_DWON_210858-2412210858-dsw--0-ia5 21-Dec-2024 08:58 5089
ber01-VHDL13_DWON_211105-2412211105-dsw--0-ia5 21-Dec-2024 11:05 5089
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ber01-VHDL13_DWPG_191730-2412191730-dsw--0-ia5 19-Dec-2024 17:30 2693
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ber01-VHDL13_DWPG_192130-2412192130-dsw--0-ia5 19-Dec-2024 21:30 1906
ber01-VHDL13_DWPG_200130-2412200130-dsw--0-ia5 20-Dec-2024 01:30 1876
ber01-VHDL13_DWPG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 2106
ber01-VHDL13_DWPG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2152
ber01-VHDL13_DWPG_200730-2412200730-dsw--0-ia5 20-Dec-2024 07:30 2150
ber01-VHDL13_DWPG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 2100
ber01-VHDL13_DWPG_200830-2412200830-dsw--0-ia5 20-Dec-2024 08:30 2150
ber01-VHDL13_DWPG_201030-2412201030-dsw--0-ia5 20-Dec-2024 10:30 2099
ber01-VHDL13_DWPG_201130-2412201130-dsw--0-ia5 20-Dec-2024 11:30 2099
ber01-VHDL13_DWPG_201230-2412201230-dsw--0-ia5 20-Dec-2024 12:30 2099
ber01-VHDL13_DWPG_201330-2412201330-dsw--0-ia5 20-Dec-2024 13:30 2099
ber01-VHDL13_DWPG_201430-2412201430-dsw--0-ia5 20-Dec-2024 14:30 2099
ber01-VHDL13_DWPG_201530-2412201530-dsw--0-ia5 20-Dec-2024 15:30 2099
ber01-VHDL13_DWPG_201630-2412201630-dsw--0-ia5 20-Dec-2024 16:30 2099
ber01-VHDL13_DWPG_201730-2412201730-dsw--0-ia5 20-Dec-2024 17:30 2099
ber01-VHDL13_DWPG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 1830
ber01-VHDL13_DWPG_201830-2412201830-dsw--0-ia5 20-Dec-2024 18:30 2099
ber01-VHDL13_DWPG_202030-2412202030-dsw--0-ia5 20-Dec-2024 20:30 1829
ber01-VHDL13_DWPG_202130-2412202130-dsw--0-ia5 20-Dec-2024 21:30 1829
ber01-VHDL13_DWPG_210130-2412210130-dsw--0-ia5 21-Dec-2024 01:30 1838
ber01-VHDL13_DWPG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 1792
ber01-VHDL13_DWPG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 1918
ber01-VHDL13_DWPG_210730-2412210730-dsw--0-ia5 21-Dec-2024 07:30 2146
ber01-VHDL13_DWPG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 2147
ber01-VHDL13_DWPG_210830-2412210830-dsw--0-ia5 21-Dec-2024 08:30 2146
ber01-VHDL13_DWPG_211030-2412211030-dsw--0-ia5 21-Dec-2024 10:30 2146
ber01-VHDL13_DWPG_211130-2412211130-dsw--0-ia5 21-Dec-2024 11:30 2146
ber01-VHDL13_DWPG_211230-2412211230-dsw--0-ia5 21-Dec-2024 12:30 2146
ber01-VHDL13_DWPG_211330-2412211330-dsw--0-ia5 21-Dec-2024 13:30 2094
ber01-VHDL13_DWPG_211430-2412211430-dsw--0-ia5 21-Dec-2024 14:30 2096
ber01-VHDL13_DWPG_211530-2412211530-dsw--0-ia5 21-Dec-2024 15:30 2096
ber01-VHDL13_DWPG_211630-2412211630-dsw--0-ia5 21-Dec-2024 16:30 2096
ber01-VHDL13_DWPH_191730-2412191730-dsw--0-ia5 19-Dec-2024 17:30 3455
ber01-VHDL13_DWPH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2778
ber01-VHDL13_DWPH_191830-2412191830-dsw--0-ia5 19-Dec-2024 18:30 3455
ber01-VHDL13_DWPH_192030-2412192030-dsw--0-ia5 19-Dec-2024 20:30 2778
ber01-VHDL13_DWPH_192130-2412192130-dsw--0-ia5 19-Dec-2024 21:30 2778
ber01-VHDL13_DWPH_200130-2412200130-dsw--0-ia5 20-Dec-2024 01:30 2691
ber01-VHDL13_DWPH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 2903
ber01-VHDL13_DWPH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2645
ber01-VHDL13_DWPH_200730-2412200730-dsw--0-ia5 20-Dec-2024 07:30 2645
ber01-VHDL13_DWPH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 2561
ber01-VHDL13_DWPH_200830-2412200830-dsw--0-ia5 20-Dec-2024 08:30 2645
ber01-VHDL13_DWPH_201030-2412201030-dsw--0-ia5 20-Dec-2024 10:30 2561
ber01-VHDL13_DWPH_201130-2412201130-dsw--0-ia5 20-Dec-2024 11:30 2561
ber01-VHDL13_DWPH_201230-2412201230-dsw--0-ia5 20-Dec-2024 12:30 2561
ber01-VHDL13_DWPH_201330-2412201330-dsw--0-ia5 20-Dec-2024 13:30 2561
ber01-VHDL13_DWPH_201430-2412201430-dsw--0-ia5 20-Dec-2024 14:30 2561
ber01-VHDL13_DWPH_201530-2412201530-dsw--0-ia5 20-Dec-2024 15:30 2561
ber01-VHDL13_DWPH_201630-2412201630-dsw--0-ia5 20-Dec-2024 16:30 2561
ber01-VHDL13_DWPH_201730-2412201730-dsw--0-ia5 20-Dec-2024 17:30 2561
ber01-VHDL13_DWPH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2123
ber01-VHDL13_DWPH_201830-2412201830-dsw--0-ia5 20-Dec-2024 18:30 2561
ber01-VHDL13_DWPH_202030-2412202030-dsw--0-ia5 20-Dec-2024 20:30 2123
ber01-VHDL13_DWPH_202130-2412202130-dsw--0-ia5 20-Dec-2024 21:30 2123
ber01-VHDL13_DWPH_210130-2412210130-dsw--0-ia5 21-Dec-2024 01:30 2000
ber01-VHDL13_DWPH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 1993
ber01-VHDL13_DWPH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 2476
ber01-VHDL13_DWPH_210730-2412210730-dsw--0-ia5 21-Dec-2024 07:30 2771
ber01-VHDL13_DWPH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 2771
ber01-VHDL13_DWPH_210830-2412210830-dsw--0-ia5 21-Dec-2024 08:30 2771
ber01-VHDL13_DWPH_211030-2412211030-dsw--0-ia5 21-Dec-2024 10:30 2771
ber01-VHDL13_DWPH_211130-2412211130-dsw--0-ia5 21-Dec-2024 11:30 2771
ber01-VHDL13_DWPH_211230-2412211230-dsw--0-ia5 21-Dec-2024 12:30 2771
ber01-VHDL13_DWPH_211330-2412211330-dsw--0-ia5 21-Dec-2024 13:30 2700
ber01-VHDL13_DWPH_211430-2412211430-dsw--0-ia5 21-Dec-2024 14:30 2702
ber01-VHDL13_DWPH_211530-2412211530-dsw--0-ia5 21-Dec-2024 15:30 2702
ber01-VHDL13_DWPH_211630-2412211630-dsw--0-ia5 21-Dec-2024 16:30 2702
ber01-VHDL13_DWSG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3809
ber01-VHDL13_DWSG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:30 3880
ber01-VHDL13_DWSG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3791
ber01-VHDL13_DWSG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3874
ber01-VHDL13_DWSG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3852
ber01-VHDL13_DWSG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:30 3885
ber01-VHDL13_DWSG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 4242
ber01-VHDL13_DWSG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 4841
ber01-VHDL13_DWSN_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 2510
ber01-VHDL13_DWSN_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2729
ber01-VHDL13_DWSN_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 2704
ber01-VHDL13_DWSN_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2566
ber01-VHDL13_DWSN_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 2910
ber01-VHDL13_DWSN_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 3259
ber01-VHDL13_DWSO_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3706
ber01-VHDL13_DWSO_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3812
ber01-VHDL13_DWSO_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3854
ber01-VHDL13_DWSO_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 3806
ber01-VHDL13_DWSO_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 4191
ber01-VHDL13_DWSO_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 4751
ber01-VHDL13_DWSP_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:30 3952
ber01-VHDL13_DWSP_191800_COR-2412191800-dsw--0-ia5 19-Dec-2024 19:37 3201
ber01-VHDL13_DWSP_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3122
ber01-VHDL13_DWSP_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:30 3127
ber01-VHDL13_DWSP_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:30 2858
ber01-VHDL13_DWSP_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3513
ber01-VHDL13_DWSP_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:30 4035
ber01-VHDL17_DWOG_201200-2412201200-dsw--0-ia5 20-Dec-2024 13:00 3405
ber01-VHDL17_DWOG_211200-2412211200-dsw--0-ia5 21-Dec-2024 12:27 4136
swis2-VHDL20_DWEG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3786
swis2-VHDL20_DWEG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3935
swis2-VHDL20_DWEG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 4320
swis2-VHDL20_DWEG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4553
swis2-VHDL20_DWEG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4436
swis2-VHDL20_DWEG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4039
swis2-VHDL20_DWEG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4334
swis2-VHDL20_DWEG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4739
swis2-VHDL20_DWEH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 4141
swis2-VHDL20_DWEH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 4161
swis2-VHDL20_DWEH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 4402
swis2-VHDL20_DWEH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4672
swis2-VHDL20_DWEH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4738
swis2-VHDL20_DWEH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4088
swis2-VHDL20_DWEH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4605
swis2-VHDL20_DWEH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 5078
swis2-VHDL20_DWEI_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3780
swis2-VHDL20_DWEI_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3834
swis2-VHDL20_DWEI_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 4323
swis2-VHDL20_DWEI_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4600
swis2-VHDL20_DWEI_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4564
swis2-VHDL20_DWEI_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3898
swis2-VHDL20_DWEI_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4221
swis2-VHDL20_DWEI_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4666
swis2-VHDL20_DWHG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3765
swis2-VHDL20_DWHG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 4012
swis2-VHDL20_DWHG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3978
swis2-VHDL20_DWHG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4318
swis2-VHDL20_DWHG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4262
swis2-VHDL20_DWHG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4318
swis2-VHDL20_DWHG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 4234
swis2-VHDL20_DWHG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4710
swis2-VHDL20_DWHH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3102
swis2-VHDL20_DWHH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3295
swis2-VHDL20_DWHH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3192
swis2-VHDL20_DWHH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 3467
swis2-VHDL20_DWHH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 3290
swis2-VHDL20_DWHH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3456
swis2-VHDL20_DWHH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3464
swis2-VHDL20_DWHH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 3928
swis2-VHDL20_DWLG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3073
swis2-VHDL20_DWLG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3627
swis2-VHDL20_DWLG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3555
swis2-VHDL20_DWLG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4023
swis2-VHDL20_DWLG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 3083
swis2-VHDL20_DWLG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3613
swis2-VHDL20_DWLG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3714
swis2-VHDL20_DWLG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4057
swis2-VHDL20_DWLH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3350
swis2-VHDL20_DWLH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3775
swis2-VHDL20_DWLH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3763
swis2-VHDL20_DWLH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4254
swis2-VHDL20_DWLH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 3199
swis2-VHDL20_DWLH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3113
swis2-VHDL20_DWLH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3178
swis2-VHDL20_DWLH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 3621
swis2-VHDL20_DWLI_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3092
swis2-VHDL20_DWLI_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3407
swis2-VHDL20_DWLI_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 3453
swis2-VHDL20_DWLI_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 3895
swis2-VHDL20_DWLI_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 3270
swis2-VHDL20_DWLI_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3474
swis2-VHDL20_DWLI_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 3563
swis2-VHDL20_DWLI_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4020
swis2-VHDL20_DWMG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3955
swis2-VHDL20_DWMG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 4020
swis2-VHDL20_DWMG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 3837
swis2-VHDL20_DWMG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4253
swis2-VHDL20_DWMG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4037
swis2-VHDL20_DWMG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4489
swis2-VHDL20_DWMG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4448
swis2-VHDL20_DWMG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 5190
swis2-VHDL20_DWMO_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3529
swis2-VHDL20_DWMO_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3684
swis2-VHDL20_DWMO_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 3702
swis2-VHDL20_DWMO_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4010
swis2-VHDL20_DWMO_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 3532
swis2-VHDL20_DWMO_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 3969
swis2-VHDL20_DWMO_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 3862
swis2-VHDL20_DWMO_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4191
swis2-VHDL20_DWMP_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3976
swis2-VHDL20_DWMP_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 4032
swis2-VHDL20_DWMP_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 4090
swis2-VHDL20_DWMP_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4099
swis2-VHDL20_DWMP_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4136
swis2-VHDL20_DWMP_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4263
swis2-VHDL20_DWMP_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4167
swis2-VHDL20_DWMP_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 4617
swis2-VHDL20_DWPG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 2369
swis2-VHDL20_DWPG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 2438
swis2-VHDL20_DWPG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2481
swis2-VHDL20_DWPG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 2562
swis2-VHDL20_DWPG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 2292
swis2-VHDL20_DWPG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 2124
swis2-VHDL20_DWPG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 2247
swis2-VHDL20_DWPG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 2608
swis2-VHDL20_DWPH_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 3240
swis2-VHDL20_DWPH_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 3234
swis2-VHDL20_DWPH_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:00 2976
swis2-VHDL20_DWPH_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 3023
swis2-VHDL20_DWPH_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 2585
swis2-VHDL20_DWPH_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 2324
swis2-VHDL20_DWPH_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:00 2807
swis2-VHDL20_DWPH_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 3232
swis2-VHDL20_DWSG_191800-2412191800-dsw--0-ia5 19-Dec-2024 19:45 4232
swis2-VHDL20_DWSG_200200-2412200200-dsw--0-ia5 20-Dec-2024 03:45 4294
swis2-VHDL20_DWSG_200400-2412200400-dsw--0-ia5 20-Dec-2024 06:15 4255
swis2-VHDL20_DWSG_200800-2412200800-dsw--0-ia5 20-Dec-2024 09:45 4525
swis2-VHDL20_DWSG_201800-2412201800-dsw--0-ia5 20-Dec-2024 19:45 4312
swis2-VHDL20_DWSG_210200-2412210200-dsw--0-ia5 21-Dec-2024 03:45 4336
swis2-VHDL20_DWSG_210400-2412210400-dsw--0-ia5 21-Dec-2024 06:15 4700
swis2-VHDL20_DWSG_210800-2412210800-dsw--0-ia5 21-Dec-2024 09:45 5439
wst04-VHDL20_DWEG_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 257148
wst04-VHDL20_DWEG_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 257472
wst04-VHDL20_DWEG_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 257087
wst04-VHDL20_DWEG_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 255528
wst04-VHDL20_DWEG_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 254817
wst04-VHDL20_DWEG_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 254824
wst04-VHDL20_DWEG_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 255151
wst04-VHDL20_DWEG_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 254022
wst04-VHDL20_DWEH_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 255565
wst04-VHDL20_DWEH_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 255947
wst04-VHDL20_DWEH_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 255087
wst04-VHDL20_DWEH_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 256093
wst04-VHDL20_DWEH_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 255957
wst04-VHDL20_DWEH_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 255643
wst04-VHDL20_DWEH_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 256080
wst04-VHDL20_DWEH_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 260174
wst04-VHDL20_DWEI_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 353118
wst04-VHDL20_DWEI_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 352989
wst04-VHDL20_DWEI_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 353280
wst04-VHDL20_DWEI_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 343162
wst04-VHDL20_DWEI_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 343146
wst04-VHDL20_DWEI_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 342536
wst04-VHDL20_DWEI_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 343167
wst04-VHDL20_DWEI_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 344356
wst04-VHDL20_DWHG_191800-2412191800-oflxs888--0..> 19-Dec-2024 19:45 342866
wst04-VHDL20_DWHG_200200-2412200200-oflxs888--0..> 20-Dec-2024 03:45 343655
wst04-VHDL20_DWHG_200400-2412200400-oflxs888--0..> 20-Dec-2024 06:00 343647
wst04-VHDL20_DWHG_200800-2412200800-oflxs888--0..> 20-Dec-2024 09:45 342685
wst04-VHDL20_DWHG_201800-2412201800-oflxs888--0..> 20-Dec-2024 19:45 340592
wst04-VHDL20_DWHG_210200-2412210200-oflxs888--0..> 21-Dec-2024 03:45 340775
wst04-VHDL20_DWHG_210400-2412210400-oflxs888--0..> 21-Dec-2024 06:00 340837
wst04-VHDL20_DWHG_210800-2412210800-oflxs888--0..> 21-Dec-2024 09:45 340714
wst04-VHDL20_DWHH_191800-2412191800-oflxs888--0..> 19-Dec-2024 19:45 329478
wst04-VHDL20_DWHH_200200-2412200200-oflxs888--0..> 20-Dec-2024 03:45 329733
wst04-VHDL20_DWHH_200400-2412200400-oflxs888--0..> 20-Dec-2024 06:00 329678
wst04-VHDL20_DWHH_200800-2412200800-oflxs888--0..> 20-Dec-2024 09:45 332324
wst04-VHDL20_DWHH_201800-2412201800-oflxs888--0..> 20-Dec-2024 19:45 331796
wst04-VHDL20_DWHH_210200-2412210200-oflxs888--0..> 21-Dec-2024 03:45 332532
wst04-VHDL20_DWHH_210400-2412210400-oflxs888--0..> 21-Dec-2024 06:00 332638
wst04-VHDL20_DWHH_210800-2412210800-oflxs888--0..> 21-Dec-2024 09:45 328937
wst04-VHDL20_DWLG_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:40 337322
wst04-VHDL20_DWLG_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:41 338455
wst04-VHDL20_DWLG_200400-2412200400-omedes--0.pdf 20-Dec-2024 05:59 337816
wst04-VHDL20_DWLG_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:40 332514
wst04-VHDL20_DWLG_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:40 331235
wst04-VHDL20_DWLG_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:42 331855
wst04-VHDL20_DWLG_210400-2412210400-omedes--0.pdf 21-Dec-2024 05:59 331827
wst04-VHDL20_DWLG_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:40 334683
wst04-VHDL20_DWLH_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:40 335604
wst04-VHDL20_DWLH_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:41 335550
wst04-VHDL20_DWLH_200400-2412200400-omedes--0.pdf 20-Dec-2024 05:59 334815
wst04-VHDL20_DWLH_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:40 329068
wst04-VHDL20_DWLH_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:40 328038
wst04-VHDL20_DWLH_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:41 328150
wst04-VHDL20_DWLH_210400-2412210400-omedes--0.pdf 21-Dec-2024 05:59 328181
wst04-VHDL20_DWLH_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:40 331063
wst04-VHDL20_DWLI_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:40 331056
wst04-VHDL20_DWLI_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:41 331091
wst04-VHDL20_DWLI_200400-2412200400-omedes--0.pdf 20-Dec-2024 05:59 331984
wst04-VHDL20_DWLI_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:40 333749
wst04-VHDL20_DWLI_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:40 332419
wst04-VHDL20_DWLI_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:42 332876
wst04-VHDL20_DWLI_210400-2412210400-omedes--0.pdf 21-Dec-2024 05:59 332894
wst04-VHDL20_DWLI_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:40 332922
wst04-VHDL20_DWMG_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 535936
wst04-VHDL20_DWMG_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 536556
wst04-VHDL20_DWMG_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 536367
wst04-VHDL20_DWMG_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 542119
wst04-VHDL20_DWMG_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 541465
wst04-VHDL20_DWMG_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 540961
wst04-VHDL20_DWMG_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 540582
wst04-VHDL20_DWMG_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 547202
wst04-VHDL20_DWMO_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 431620
wst04-VHDL20_DWMO_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 431266
wst04-VHDL20_DWMO_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 431818
wst04-VHDL20_DWMO_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 433695
wst04-VHDL20_DWMO_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 432292
wst04-VHDL20_DWMO_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 432872
wst04-VHDL20_DWMO_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 433338
wst04-VHDL20_DWMO_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 438648
wst04-VHDL20_DWMP_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 562797
wst04-VHDL20_DWMP_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 562189
wst04-VHDL20_DWMP_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 563384
wst04-VHDL20_DWMP_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 558557
wst04-VHDL20_DWMP_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 557563
wst04-VHDL20_DWMP_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 556094
wst04-VHDL20_DWMP_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 557242
wst04-VHDL20_DWMP_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 566831
wst04-VHDL20_DWPG_191800-2412191800-oflxs892--0..> 19-Dec-2024 19:45 331048
wst04-VHDL20_DWPG_200200-2412200200-oflxs892--0..> 20-Dec-2024 03:45 330869
wst04-VHDL20_DWPG_200400-2412200400-oflxs892--0..> 20-Dec-2024 06:00 330419
wst04-VHDL20_DWPG_200800-2412200800-oflxs892--0..> 20-Dec-2024 09:45 371365
wst04-VHDL20_DWPG_201800-2412201800-oflxs892--0..> 20-Dec-2024 19:45 326601
wst04-VHDL20_DWPG_210200-2412210200-oflxs892--0..> 21-Dec-2024 03:45 326545
wst04-VHDL20_DWPG_210400-2412210400-oflxs892--0..> 21-Dec-2024 06:00 327317
wst04-VHDL20_DWPG_210800-2412210800-oflxs892--0..> 21-Dec-2024 09:45 377097
wst04-VHDL20_DWPH_191800-2412191800-oflxs892--0..> 19-Dec-2024 19:45 294498
wst04-VHDL20_DWPH_200200-2412200200-oflxs892--0..> 20-Dec-2024 03:45 249713
wst04-VHDL20_DWPH_200400-2412200400-oflxs892--0..> 20-Dec-2024 06:00 249010
wst04-VHDL20_DWPH_200800-2412200800-oflxs892--0..> 20-Dec-2024 09:45 293335
wst04-VHDL20_DWPH_210200-2412210200-oflxs892--0..> 21-Dec-2024 03:45 247969
wst04-VHDL20_DWPH_210400-2412210400-oflxs892--0..> 21-Dec-2024 06:00 247784
wst04-VHDL20_DWPH_210800-2412210800-oflxs892--0..> 21-Dec-2024 09:45 290228
wst04-VHDL20_DWSG_191800-2412191800-omedes--0.pdf 19-Dec-2024 19:45 347016
wst04-VHDL20_DWSG_200200-2412200200-omedes--0.pdf 20-Dec-2024 03:45 346319
wst04-VHDL20_DWSG_200400-2412200400-omedes--0.pdf 20-Dec-2024 06:15 347204
wst04-VHDL20_DWSG_200800-2412200800-omedes--0.pdf 20-Dec-2024 09:45 346750
wst04-VHDL20_DWSG_201800-2412201800-omedes--0.pdf 20-Dec-2024 19:45 346312
wst04-VHDL20_DWSG_210200-2412210200-omedes--0.pdf 21-Dec-2024 03:45 347097
wst04-VHDL20_DWSG_210400-2412210400-omedes--0.pdf 21-Dec-2024 06:15 347136
wst04-VHDL20_DWSG_210800-2412210800-omedes--0.pdf 21-Dec-2024 09:45 351037