Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_300600                                 30-Aug-2026 11:27:40                4230
FPDL13_DWMZ_310600                                 31-Aug-2026 14:05:48                4050
SXDL31_DWAV_300800                                 30-Aug-2026 07:53:50               10242
SXDL31_DWAV_301800                                 30-Aug-2026 16:49:19                7992
SXDL31_DWAV_310800                                 31-Aug-2026 07:25:14                8174
SXDL31_DWAV_311800                                 31-Aug-2026 16:39:49                6667
SXDL31_DWAV_LATEST                                 31-Aug-2026 16:39:49                6667
SXDL33_DWAV_300000                                 30-Aug-2026 10:25:30               10690
SXDL33_DWAV_310000                                 31-Aug-2026 10:29:02               17117
SXDL33_DWAV_LATEST                                 31-Aug-2026 10:29:02               17117
ber01-FWDL39_DWMS_301200-2608301200-dsw--0-ia5     30-Aug-2026 10:50:28                1456
ber01-FWDL39_DWMS_311200-2608311200-dsw--0-ia5     31-Aug-2026 10:52:08                1502
ber01-VHDL13_DWEG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:28:14                2878
ber01-VHDL13_DWEG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:28:18                2788
ber01-VHDL13_DWEH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:28:18                2954
ber01-VHDL13_DWEH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:28:18                2641
ber01-VHDL13_DWEI_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:28:18                2834
ber01-VHDL13_DWEI_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:28:14                2851
ber01-VHDL13_DWHG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                4120
ber01-VHDL13_DWHG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:09                3803
ber01-VHDL13_DWHH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                4197
ber01-VHDL13_DWHH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:09                3431
ber01-VHDL13_DWLG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                2726
ber01-VHDL13_DWLG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                2833
ber01-VHDL13_DWLH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                3045
ber01-VHDL13_DWLH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                3186
ber01-VHDL13_DWLI_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                2704
ber01-VHDL13_DWLI_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                2733
ber01-VHDL13_DWMO_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                3318
ber01-VHDL13_DWMO_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                2939
ber01-VHDL13_DWMP_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                3099
ber01-VHDL13_DWMP_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                2887
ber01-VHDL13_DWOG_300300-2608300300-dsw--0-ia5     30-Aug-2026 03:00:04                4685
ber01-VHDL13_DWOG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                4146
ber01-VHDL13_DWOG_301700-2608301700-dsw--0-ia5     30-Aug-2026 18:00:09                3982
ber01-VHDL13_DWOG_310300-2608310300-dsw--0-ia5     31-Aug-2026 03:00:08                4256
ber01-VHDL13_DWOG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                4147
ber01-VHDL13_DWOG_311700-2608311700-dsw--0-ia5     31-Aug-2026 18:00:06                3596
ber01-VHDL13_DWON_300015-2608300015-dsw--0-ia5     30-Aug-2026 00:15:14                4125
ber01-VHDL13_DWON_300100-2608300100-dsw--0-ia5     30-Aug-2026 01:00:30                4125
ber01-VHDL13_DWON_300233-2608300233-dsw--0-ia5     30-Aug-2026 02:34:06                4125
ber01-VHDL13_DWON_300522-2608300522-dsw--0-ia5     30-Aug-2026 05:22:25                3606
ber01-VHDL13_DWON_300602-2608300602-dsw--0-ia5     30-Aug-2026 06:02:29                3606
ber01-VHDL13_DWON_300603-2608300603-dsw--0-ia5     30-Aug-2026 06:03:43                3606
ber01-VHDL13_DWON_301327-2608301327-dsw--0-ia5     30-Aug-2026 13:28:01                3462
ber01-VHDL13_DWON_301412-2608301412-dsw--0-ia5     30-Aug-2026 14:12:14                3456
ber01-VHDL13_DWON_301658-2608301658-dsw--0-ia5     30-Aug-2026 16:58:38                3196
ber01-VHDL13_DWON_301733-2608301733-dsw--0-ia5     30-Aug-2026 17:34:13                3196
ber01-VHDL13_DWON_310259-2608310259-dsw--0-ia5     31-Aug-2026 03:00:00                3242
ber01-VHDL13_DWON_310525-2608310525-dsw--0-ia5     31-Aug-2026 05:25:50                3637
ber01-VHDL13_DWON_310604-2608310604-dsw--0-ia5     31-Aug-2026 06:04:44                3698
ber01-VHDL13_DWON_310814-2608310814-dsw--0-ia5     31-Aug-2026 08:14:22                3686
ber01-VHDL13_DWON_311455-2608311455-dsw--0-ia5     31-Aug-2026 14:55:34                3667
ber01-VHDL13_DWON_311722-2608311722-dsw--0-ia5     31-Aug-2026 17:22:55                3063
ber01-VHDL13_DWON_312019-2608312019-dsw--0-ia5     31-Aug-2026 20:19:23                3102
ber01-VHDL13_DWPG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                2601
ber01-VHDL13_DWPG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                2736
ber01-VHDL13_DWPH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                2904
ber01-VHDL13_DWPH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                3044
ber01-VHDL13_DWSG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                3255
ber01-VHDL13_DWSG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:09                2567
ber01-VHDL17_DWOG_301200-2608301200-dsw--0-ia5     30-Aug-2026 11:49:58                4086
ber01-VHDL17_DWOG_311200-2608311200-dsw--0-ia5     31-Aug-2026 11:04:09                4262
swis2-VHDL20_DWEG_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:03                1346
swis2-VHDL20_DWEG_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:01:14                1350
swis2-VHDL20_DWEG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                1463
swis2-VHDL20_DWEG_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:05                1378
swis2-VHDL20_DWEG_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:07                1147
swis2-VHDL20_DWEG_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:01:18                1063
swis2-VHDL20_DWEG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                1182
swis2-VHDL20_DWEG_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:03                1150
swis2-VHDL20_DWEH_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:03                1427
swis2-VHDL20_DWEH_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:01:14                1332
swis2-VHDL20_DWEH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                1434
swis2-VHDL20_DWEH_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:05                1350
swis2-VHDL20_DWEH_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:07                1162
swis2-VHDL20_DWEH_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:01:18                1078
swis2-VHDL20_DWEH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                1191
swis2-VHDL20_DWEH_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:03                 934
swis2-VHDL20_DWEI_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:03                1307
swis2-VHDL20_DWEI_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:01:14                1311
swis2-VHDL20_DWEI_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                1398
swis2-VHDL20_DWEI_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:05                1392
swis2-VHDL20_DWEI_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:07                1170
swis2-VHDL20_DWEI_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:01:18                1086
swis2-VHDL20_DWEI_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                1205
swis2-VHDL20_DWEI_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:03                 914
swis2-VHDL20_DWHG_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:45:49                2283
swis2-VHDL20_DWHG_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                2294
swis2-VHDL20_DWHG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:45:45                2315
swis2-VHDL20_DWHG_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:45:07                1919
swis2-VHDL20_DWHG_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:45:30                1727
swis2-VHDL20_DWHG_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:18                1724
swis2-VHDL20_DWHG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:45:43                1913
swis2-VHDL20_DWHG_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:45:13                1727
swis2-VHDL20_DWHH_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:45:49                2332
swis2-VHDL20_DWHH_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                2348
swis2-VHDL20_DWHH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:45:45                2352
swis2-VHDL20_DWHH_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:45:07                2035
swis2-VHDL20_DWHH_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:45:30                1712
swis2-VHDL20_DWHH_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:18                1710
swis2-VHDL20_DWHH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:45:43                1974
swis2-VHDL20_DWHH_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:45:13                1762
swis2-VHDL20_DWLG_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:29                1148
swis2-VHDL20_DWLG_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1109
swis2-VHDL20_DWLG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1235
swis2-VHDL20_DWLG_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:31:13                1475
swis2-VHDL20_DWLG_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:32                1386
swis2-VHDL20_DWLG_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:14                1398
swis2-VHDL20_DWLG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:23                1331
swis2-VHDL20_DWLG_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:31:15                1515
swis2-VHDL20_DWLH_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:29                1419
swis2-VHDL20_DWLH_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1243
swis2-VHDL20_DWLH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1448
swis2-VHDL20_DWLH_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:31:13                1745
swis2-VHDL20_DWLH_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:32                1610
swis2-VHDL20_DWLH_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:14                1470
swis2-VHDL20_DWLH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:23                1642
swis2-VHDL20_DWLH_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:31:15                1691
swis2-VHDL20_DWLI_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:29                1166
swis2-VHDL20_DWLI_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1082
swis2-VHDL20_DWLI_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1208
swis2-VHDL20_DWLI_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:31:13                1423
swis2-VHDL20_DWLI_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:32                1375
swis2-VHDL20_DWLI_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:14                1309
swis2-VHDL20_DWLI_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:23                1349
swis2-VHDL20_DWLI_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:31:15                1354
swis2-VHDL20_DWMO_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:06                1350
swis2-VHDL20_DWMO_300200_COR-2608300200-dsw--0-ia5 30-Aug-2026 03:04:48                3093
swis2-VHDL20_DWMO_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:04                1408
swis2-VHDL20_DWMO_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1639
swis2-VHDL20_DWMO_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:24                1508
swis2-VHDL20_DWMO_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:16                1491
swis2-VHDL20_DWMO_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:04                1492
swis2-VHDL20_DWMO_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                1357
swis2-VHDL20_DWMO_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:03                1304
swis2-VHDL20_DWMP_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:06                1139
swis2-VHDL20_DWMP_300200_COR-2608300200-dsw--0-ia5 30-Aug-2026 03:05:02                3119
swis2-VHDL20_DWMP_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:04                1185
swis2-VHDL20_DWMP_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1411
swis2-VHDL20_DWMP_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:24                1740
swis2-VHDL20_DWMP_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:16                1551
swis2-VHDL20_DWMP_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:04                1551
swis2-VHDL20_DWMP_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:03                1352
swis2-VHDL20_DWMP_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:03                1424
swis2-VHDL20_DWPG_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:29                1195
swis2-VHDL20_DWPG_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1044
swis2-VHDL20_DWPG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1170
swis2-VHDL20_DWPG_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:31:13                1493
swis2-VHDL20_DWPG_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:32                1444
swis2-VHDL20_DWPG_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:14                1288
swis2-VHDL20_DWPG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:23                1430
swis2-VHDL20_DWPG_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:31:15                1448
swis2-VHDL20_DWPH_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:29                1338
swis2-VHDL20_DWPH_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1120
swis2-VHDL20_DWPH_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:20                1321
swis2-VHDL20_DWPH_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:31:13                1654
swis2-VHDL20_DWPH_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:32                1460
swis2-VHDL20_DWPH_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:14                1294
swis2-VHDL20_DWPH_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:23                1595
swis2-VHDL20_DWPH_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:31:15                1739
swis2-VHDL20_DWSG_300200-2608300200-dsw--0-ia5     30-Aug-2026 02:30:06                1344
swis2-VHDL20_DWSG_300200_COR-2608300200-dsw--0-ia5 30-Aug-2026 03:05:37                1397
swis2-VHDL20_DWSG_300400-2608300400-dsw--0-ia5     30-Aug-2026 05:00:18                1414
swis2-VHDL20_DWSG_300800-2608300800-dsw--0-ia5     30-Aug-2026 08:30:12                1455
swis2-VHDL20_DWSG_301800-2608301800-dsw--0-ia5     30-Aug-2026 18:30:05                1413
swis2-VHDL20_DWSG_310200-2608310200-dsw--0-ia5     31-Aug-2026 02:30:16                1422
swis2-VHDL20_DWSG_310400-2608310400-dsw--0-ia5     31-Aug-2026 05:00:20                1155
swis2-VHDL20_DWSG_310800-2608310800-dsw--0-ia5     31-Aug-2026 08:30:09                1214
swis2-VHDL20_DWSG_311800-2608311800-dsw--0-ia5     31-Aug-2026 18:30:11                1249
wst04-VHDL20_DWEG_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:27              242670
wst04-VHDL20_DWEG_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:14              242689
wst04-VHDL20_DWEG_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:20              243402
wst04-VHDL20_DWEG_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              242302
wst04-VHDL20_DWEG_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:24              241570
wst04-VHDL20_DWEG_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:14              240959
wst04-VHDL20_DWEG_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:13              241714
wst04-VHDL20_DWEG_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:19              243657
wst04-VHDL20_DWEH_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:27              239044
wst04-VHDL20_DWEH_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:14              239000
wst04-VHDL20_DWEH_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:20              239694
wst04-VHDL20_DWEH_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              238337
wst04-VHDL20_DWEH_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:24              238184
wst04-VHDL20_DWEH_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:14              237571
wst04-VHDL20_DWEH_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:13              238387
wst04-VHDL20_DWEH_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:13              237283
wst04-VHDL20_DWEI_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:27              346698
wst04-VHDL20_DWEI_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:18              346645
wst04-VHDL20_DWEI_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:20              347515
wst04-VHDL20_DWEI_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              345435
wst04-VHDL20_DWEI_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:23              345252
wst04-VHDL20_DWEI_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:14              344619
wst04-VHDL20_DWEI_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:19              344865
wst04-VHDL20_DWEI_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:19              342492
wst04-VHDL20_DWHG_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:45:49              347296
wst04-VHDL20_DWHG_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:18              347120
wst04-VHDL20_DWHG_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:45:45              348448
wst04-VHDL20_DWHG_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:45:15              348188
wst04-VHDL20_DWHG_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:45:30              347200
wst04-VHDL20_DWHG_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:18              346939
wst04-VHDL20_DWHG_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:45:43              349028
wst04-VHDL20_DWHG_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:45:24              342887
wst04-VHDL20_DWHH_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:45:49              338994
wst04-VHDL20_DWHH_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:18              237270
wst04-VHDL20_DWHH_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:45:45              339911
wst04-VHDL20_DWHH_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:45:15              341768
wst04-VHDL20_DWHH_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:45:30              340714
wst04-VHDL20_DWHH_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:18              239126
wst04-VHDL20_DWHH_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:45:43              342040
wst04-VHDL20_DWHH_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:45:24              341000
wst04-VHDL20_DWLG_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:29              335672
wst04-VHDL20_DWLG_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:44              335378
wst04-VHDL20_DWLG_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:57              335608
wst04-VHDL20_DWLG_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:31:28              335510
wst04-VHDL20_DWLG_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:38              335750
wst04-VHDL20_DWLG_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:44              335483
wst04-VHDL20_DWLG_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:43              335654
wst04-VHDL20_DWLG_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:31:22              336418
wst04-VHDL20_DWLH_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:29              328600
wst04-VHDL20_DWLH_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:44              328183
wst04-VHDL20_DWLH_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:45              328489
wst04-VHDL20_DWLH_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:31:28              335346
wst04-VHDL20_DWLH_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:32              335171
wst04-VHDL20_DWLH_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:44              334903
wst04-VHDL20_DWLH_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:43              335989
wst04-VHDL20_DWLH_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:31:22              338415
wst04-VHDL20_DWLI_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:29              334608
wst04-VHDL20_DWLI_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:44              334242
wst04-VHDL20_DWLI_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:45              379077
wst04-VHDL20_DWLI_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:31:28              340889
wst04-VHDL20_DWLI_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:32              341181
wst04-VHDL20_DWLI_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:44              340753
wst04-VHDL20_DWLI_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:43              385543
wst04-VHDL20_DWLI_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:31:28              344845
wst04-VHDL20_DWMO_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:27              450723
wst04-VHDL20_DWMO_300200_COR-2608300200-omedes-..> 30-Aug-2026 03:05:02              453603
wst04-VHDL20_DWMO_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:14              451291
wst04-VHDL20_DWMO_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:20              451558
wst04-VHDL20_DWMO_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              351980
wst04-VHDL20_DWMO_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:23              454359
wst04-VHDL20_DWMO_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:20              454571
wst04-VHDL20_DWMO_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:19              452256
wst04-VHDL20_DWMO_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:19              347701
wst04-VHDL20_DWMP_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:27              563522
wst04-VHDL20_DWMP_300200_COR-2608300200-omedes-..> 30-Aug-2026 03:05:07              566657
wst04-VHDL20_DWMP_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:18              564142
wst04-VHDL20_DWMP_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:28              460120
wst04-VHDL20_DWMP_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              465184
wst04-VHDL20_DWMP_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:23              573508
wst04-VHDL20_DWMP_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:20              573683
wst04-VHDL20_DWMP_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:23              464702
wst04-VHDL20_DWMP_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:19              459293
wst04-VHDL20_DWPG_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:29              239734
wst04-VHDL20_DWPG_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:34              339709
wst04-VHDL20_DWPG_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:45              384473
wst04-VHDL20_DWPG_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:31:36              347291
wst04-VHDL20_DWPG_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:32              244284
wst04-VHDL20_DWPG_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:34              347722
wst04-VHDL20_DWPG_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:49              393319
wst04-VHDL20_DWPG_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:31:22              339597
wst04-VHDL20_DWPH_300200-2608300200-omedes--0.pdf  30-Aug-2026 02:30:29              240487
wst04-VHDL20_DWPH_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:34              239658
wst04-VHDL20_DWPH_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:45              240315
wst04-VHDL20_DWPH_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:31:28              243811
wst04-VHDL20_DWPH_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:32              243091
wst04-VHDL20_DWPH_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:34              242972
wst04-VHDL20_DWPH_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:43              243928
wst04-VHDL20_DWPH_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:31:22              241767
wst04-VHDL20_DWSG_300200-2608300200-omedes--0.pdf  30-Aug-2026 03:05:40              344053
wst04-VHDL20_DWSG_300400-2608300400-omedes--0.pdf  30-Aug-2026 05:00:14              344096
wst04-VHDL20_DWSG_300800-2608300800-omedes--0.pdf  30-Aug-2026 08:30:20              344226
wst04-VHDL20_DWSG_301800-2608301800-omedes--0.pdf  30-Aug-2026 18:30:24              344647
wst04-VHDL20_DWSG_310200-2608310200-omedes--0.pdf  31-Aug-2026 02:30:23              345872
wst04-VHDL20_DWSG_310400-2608310400-omedes--0.pdf  31-Aug-2026 05:00:14              344750
wst04-VHDL20_DWSG_310800-2608310800-omedes--0.pdf  31-Aug-2026 08:30:13              344934
wst04-VHDL20_DWSG_311800-2608311800-omedes--0.pdf  31-Aug-2026 18:30:13              341863