Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Jul-2026 12:52:15 5827
FPDL13_DWMZ_240600 24-Jul-2026 13:33:17 5380
SXDL31_DWAV_230800 23-Jul-2026 07:49:10 11206
SXDL31_DWAV_231800 23-Jul-2026 16:50:04 6255
SXDL31_DWAV_240800 24-Jul-2026 07:02:55 14784
SXDL31_DWAV_241800 24-Jul-2026 15:50:44 10063
SXDL31_DWAV_LATEST 24-Jul-2026 15:50:44 10063
SXDL33_DWAV_230000 23-Jul-2026 10:41:39 5974
SXDL33_DWAV_240000 24-Jul-2026 09:46:55 8795
SXDL33_DWAV_LATEST 24-Jul-2026 09:46:55 8795
ber01-FWDL39_DWMS_231200-2607231200-dsw--0-ia5 23-Jul-2026 11:09:12 2007
ber01-FWDL39_DWMS_241200-2607241200-dsw--0-ia5 24-Jul-2026 11:57:01 2068
ber01-VHDL13_DWEG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:28:12 2526
ber01-VHDL13_DWEG_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03 2359
ber01-VHDL13_DWEG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:28:17 2506
ber01-VHDL13_DWEH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:28:16 2716
ber01-VHDL13_DWEH_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03 2514
ber01-VHDL13_DWEH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:28:17 2672
ber01-VHDL13_DWEI_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:28:16 2342
ber01-VHDL13_DWEI_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03 2258
ber01-VHDL13_DWEI_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:28:17 2458
ber01-VHDL13_DWHG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:14 3055
ber01-VHDL13_DWHG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 3124
ber01-VHDL13_DWHH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:14 2870
ber01-VHDL13_DWHH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2902
ber01-VHDL13_DWLG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2800
ber01-VHDL13_DWLG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2418
ber01-VHDL13_DWLH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2545
ber01-VHDL13_DWLH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2449
ber01-VHDL13_DWLI_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2407
ber01-VHDL13_DWLI_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2468
ber01-VHDL13_DWMO_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2309
ber01-VHDL13_DWMO_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2493
ber01-VHDL13_DWMP_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2940
ber01-VHDL13_DWMP_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 08:49:08 2948
ber01-VHDL13_DWMP_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 3215
ber01-VHDL13_DWOG_230300-2607230300-dsw--0-ia5 23-Jul-2026 03:00:03 3714
ber01-VHDL13_DWOG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 3169
ber01-VHDL13_DWOG_231700-2607231700-dsw--0-ia5 23-Jul-2026 18:00:03 2891
ber01-VHDL13_DWOG_240300-2607240300-dsw--0-ia5 24-Jul-2026 03:00:01 3024
ber01-VHDL13_DWOG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 3022
ber01-VHDL13_DWOG_241700-2607241700-dsw--0-ia5 24-Jul-2026 18:00:00 3284
ber01-VHDL13_DWON_222019-2607222019-dsw--0-ia5 22-Jul-2026 20:19:36 3643
ber01-VHDL13_DWON_230011-2607230011-dsw--0-ia5 23-Jul-2026 00:11:41 3815
ber01-VHDL13_DWON_230330-2607230330-dsw--0-ia5 23-Jul-2026 03:30:38 3815
ber01-VHDL13_DWON_230356-2607230356-dsw--0-ia5 23-Jul-2026 03:56:56 3815
ber01-VHDL13_DWON_230522-2607230522-dsw--0-ia5 23-Jul-2026 05:22:17 3801
ber01-VHDL13_DWON_230618-2607230618-dsw--0-ia5 23-Jul-2026 06:18:11 3714
ber01-VHDL13_DWON_231427-2607231427-dsw--0-ia5 23-Jul-2026 14:27:17 3363
ber01-VHDL13_DWON_231728-2607231728-dsw--0-ia5 23-Jul-2026 17:28:06 3022
ber01-VHDL13_DWON_240129-2607240129-dsw--0-ia5 24-Jul-2026 01:29:11 3199
ber01-VHDL13_DWON_240526-2607240526-dsw--0-ia5 24-Jul-2026 05:26:38 3486
ber01-VHDL13_DWON_240739-2607240739-dsw--0-ia5 24-Jul-2026 07:39:21 3486
ber01-VHDL13_DWON_241437-2607241437-dsw--0-ia5 24-Jul-2026 14:38:05 3478
ber01-VHDL13_DWON_241628-2607241628-dsw--0-ia5 24-Jul-2026 16:28:51 3290
ber01-VHDL13_DWON_241631-2607241631-dsw--0-ia5 24-Jul-2026 16:32:10 3226
ber01-VHDL13_DWPG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2945
ber01-VHDL13_DWPG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2631
ber01-VHDL13_DWPH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2969
ber01-VHDL13_DWPH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 2637
ber01-VHDL13_DWSG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 2651
ber01-VHDL13_DWSG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 3049
ber01-VHDL17_DWOG_231200-2607231200-dsw--0-ia5 23-Jul-2026 11:45:36 3539
ber01-VHDL17_DWOG_241200-2607241200-dsw--0-ia5 24-Jul-2026 10:50:42 3901
swis2-VHDL20_DWEG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 799
swis2-VHDL20_DWEG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 795
swis2-VHDL20_DWEG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 979
swis2-VHDL20_DWEG_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57 1116
swis2-VHDL20_DWEG_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1132
swis2-VHDL20_DWEG_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 787
swis2-VHDL20_DWEG_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:01:17 787
swis2-VHDL20_DWEG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1109
swis2-VHDL20_DWEG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1132
swis2-VHDL20_DWEH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 817
swis2-VHDL20_DWEH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 819
swis2-VHDL20_DWEH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 1028
swis2-VHDL20_DWEH_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57 1045
swis2-VHDL20_DWEH_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1079
swis2-VHDL20_DWEH_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 803
swis2-VHDL20_DWEH_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:01:17 803
swis2-VHDL20_DWEH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1097
swis2-VHDL20_DWEH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1165
swis2-VHDL20_DWEI_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 821
swis2-VHDL20_DWEI_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 817
swis2-VHDL20_DWEI_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 997
swis2-VHDL20_DWEI_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57 1068
swis2-VHDL20_DWEI_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1084
swis2-VHDL20_DWEI_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 809
swis2-VHDL20_DWEI_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:01:17 809
swis2-VHDL20_DWEI_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1061
swis2-VHDL20_DWEI_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1163
swis2-VHDL20_DWHG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:45:32 1258
swis2-VHDL20_DWHG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 1080
swis2-VHDL20_DWHG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:45:07 1130
swis2-VHDL20_DWHG_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:45:04 1118
swis2-VHDL20_DWHG_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:45:04 993
swis2-VHDL20_DWHG_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 990
swis2-VHDL20_DWHG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:45:11 1160
swis2-VHDL20_DWHG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:45:04 1400
swis2-VHDL20_DWHH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:45:32 1551
swis2-VHDL20_DWHH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 1214
swis2-VHDL20_DWHH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:45:07 1159
swis2-VHDL20_DWHH_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:45:04 1126
swis2-VHDL20_DWHH_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:45:04 996
swis2-VHDL20_DWHH_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 996
swis2-VHDL20_DWHH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:45:11 1162
swis2-VHDL20_DWHH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:45:04 1419
swis2-VHDL20_DWLG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 1048
swis2-VHDL20_DWLG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1197
swis2-VHDL20_DWLG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:23 1504
swis2-VHDL20_DWLG_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:31:05 915
swis2-VHDL20_DWLG_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:21 752
swis2-VHDL20_DWLG_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 818
swis2-VHDL20_DWLG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:21 1228
swis2-VHDL20_DWLG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1120
swis2-VHDL20_DWLH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 842
swis2-VHDL20_DWLH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1016
swis2-VHDL20_DWLH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:23 1143
swis2-VHDL20_DWLH_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:31:05 997
swis2-VHDL20_DWLH_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:21 809
swis2-VHDL20_DWLH_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 824
swis2-VHDL20_DWLH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:21 1285
swis2-VHDL20_DWLH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1490
swis2-VHDL20_DWLI_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 837
swis2-VHDL20_DWLI_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1036
swis2-VHDL20_DWLI_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:23 1163
swis2-VHDL20_DWLI_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:31:05 1017
swis2-VHDL20_DWLI_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:21 829
swis2-VHDL20_DWLI_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 821
swis2-VHDL20_DWLI_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:21 1260
swis2-VHDL20_DWLI_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1051
swis2-VHDL20_DWMO_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 922
swis2-VHDL20_DWMO_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:02 923
swis2-VHDL20_DWMO_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 1059
swis2-VHDL20_DWMO_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1285
swis2-VHDL20_DWMO_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 858
swis2-VHDL20_DWMO_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:03 859
swis2-VHDL20_DWMO_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1178
swis2-VHDL20_DWMO_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1499
swis2-VHDL20_DWMP_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 919
swis2-VHDL20_DWMP_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:02 915
swis2-VHDL20_DWMP_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 1422
swis2-VHDL20_DWMP_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1541
swis2-VHDL20_DWMP_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 1070
swis2-VHDL20_DWMP_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:03 1069
swis2-VHDL20_DWMP_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1721
swis2-VHDL20_DWMP_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1586
swis2-VHDL20_DWPG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 1053
swis2-VHDL20_DWPG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1250
swis2-VHDL20_DWPG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:23 1508
swis2-VHDL20_DWPG_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:31:05 934
swis2-VHDL20_DWPG_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:21 764
swis2-VHDL20_DWPG_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 850
swis2-VHDL20_DWPG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:21 1132
swis2-VHDL20_DWPG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1296
swis2-VHDL20_DWPH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 955
swis2-VHDL20_DWPH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1063
swis2-VHDL20_DWPH_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:23 1334
swis2-VHDL20_DWPH_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:31:05 1018
swis2-VHDL20_DWPH_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:21 768
swis2-VHDL20_DWPH_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 860
swis2-VHDL20_DWPH_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:21 1162
swis2-VHDL20_DWPH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1411
swis2-VHDL20_DWSG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 879
swis2-VHDL20_DWSG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 876
swis2-VHDL20_DWSG_230800-2607230800-dsw--0-ia5 23-Jul-2026 08:30:06 993
swis2-VHDL20_DWSG_231800-2607231800-dsw--0-ia5 23-Jul-2026 18:30:11 1676
swis2-VHDL20_DWSG_240200-2607240200-dsw--0-ia5 24-Jul-2026 02:30:03 1212
swis2-VHDL20_DWSG_240400-2607240400-dsw--0-ia5 24-Jul-2026 05:00:17 1224
swis2-VHDL20_DWSG_240800-2607240800-dsw--0-ia5 24-Jul-2026 08:30:07 1617
swis2-VHDL20_DWSG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:03 1659
wst04-VHDL20_DWEG_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 238328
wst04-VHDL20_DWEG_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 237386
wst04-VHDL20_DWEG_230800-2607230800-omedes--0.pdf 23-Jul-2026 08:30:14 238576
wst04-VHDL20_DWEG_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06 238644
wst04-VHDL20_DWEG_231800-2607231800-omedes--0.pdf 23-Jul-2026 18:30:11 238890
wst04-VHDL20_DWEG_240200-2607240200-omedes--0.pdf 24-Jul-2026 02:30:19 237287
wst04-VHDL20_DWEG_240400-2607240400-omedes--0.pdf 24-Jul-2026 05:00:13 237344
wst04-VHDL20_DWEG_240800-2607240800-omedes--0.pdf 24-Jul-2026 08:30:14 238662
wst04-VHDL20_DWEG_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:21 239456
wst04-VHDL20_DWEH_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 235110
wst04-VHDL20_DWEH_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 234146
wst04-VHDL20_DWEH_230800-2607230800-omedes--0.pdf 23-Jul-2026 08:30:14 235414
wst04-VHDL20_DWEH_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06 235919
wst04-VHDL20_DWEH_231800-2607231800-omedes--0.pdf 23-Jul-2026 18:30:11 235570
wst04-VHDL20_DWEH_240200-2607240200-omedes--0.pdf 24-Jul-2026 02:30:19 234327
wst04-VHDL20_DWEH_240400-2607240400-omedes--0.pdf 24-Jul-2026 05:00:13 234698
wst04-VHDL20_DWEH_240800-2607240800-omedes--0.pdf 24-Jul-2026 08:30:14 235986
wst04-VHDL20_DWEH_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:21 238485
wst04-VHDL20_DWEI_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 337802
wst04-VHDL20_DWEI_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 336813
wst04-VHDL20_DWEI_230800-2607230800-omedes--0.pdf 23-Jul-2026 08:30:23 337503
wst04-VHDL20_DWEI_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06 342105
wst04-VHDL20_DWEI_231800-2607231800-omedes--0.pdf 23-Jul-2026 18:30:17 342308
wst04-VHDL20_DWEI_240200-2607240200-omedes--0.pdf 24-Jul-2026 02:30:19 341355
wst04-VHDL20_DWEI_240400-2607240400-omedes--0.pdf 24-Jul-2026 05:00:13 341364
wst04-VHDL20_DWEI_240800-2607240800-omedes--0.pdf 24-Jul-2026 08:30:21 342088
wst04-VHDL20_DWEI_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:11 341316
wst04-VHDL20_DWHG_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:45:32 341583
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