Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Sep-2026 12:20:24 4106
SXDL31_DWAV_131800 13-Sep-2026 17:09:24 3769
SXDL31_DWAV_140800 14-Sep-2026 08:28:24 12072
SXDL31_DWAV_141800 14-Sep-2026 16:55:19 10876
SXDL31_DWAV_150800 15-Sep-2026 07:58:28 9655
SXDL31_DWAV_LATEST 15-Sep-2026 07:58:28 9655
SXDL33_DWAV_140000 14-Sep-2026 09:43:03 13602
SXDL33_DWAV_150000 15-Sep-2026 10:09:29 6331
SXDL33_DWAV_LATEST 15-Sep-2026 10:09:29 6331
ber01-FWDL39_DWMS_141200-2609141200-dsw--0-ia5 14-Sep-2026 11:45:40 1558
ber01-VHDL13_DWEG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:12 2811
ber01-VHDL13_DWEG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:28:18 3001
ber01-VHDL13_DWEH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:18 3001
ber01-VHDL13_DWEH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:28:18 3151
ber01-VHDL13_DWEI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:18 2723
ber01-VHDL13_DWEI_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:28:18 2721
ber01-VHDL13_DWHG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3338
ber01-VHDL13_DWHG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 3767
ber01-VHDL13_DWHH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3246
ber01-VHDL13_DWHH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:09 3595
ber01-VHDL13_DWLG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2278
ber01-VHDL13_DWLG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 2449
ber01-VHDL13_DWLH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2282
ber01-VHDL13_DWLH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 3088
ber01-VHDL13_DWLI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2313
ber01-VHDL13_DWLI_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 2399
ber01-VHDL13_DWMO_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 3072
ber01-VHDL13_DWMO_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 3261
ber01-VHDL13_DWMP_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2861
ber01-VHDL13_DWMP_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 4063
ber01-VHDL13_DWOG_131700-2609131700-dsw--0-ia5 13-Sep-2026 18:00:05 3536
ber01-VHDL13_DWOG_140300-2609140300-dsw--0-ia5 14-Sep-2026 03:02:48 4054
ber01-VHDL13_DWOG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3657
ber01-VHDL13_DWOG_141700-2609141700-dsw--0-ia5 14-Sep-2026 18:00:04 3851
ber01-VHDL13_DWOG_150300-2609150300-dsw--0-ia5 15-Sep-2026 03:00:46 4216
ber01-VHDL13_DWOG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 4095
ber01-VHDL13_DWON_131502-2609131502-dsw--0-ia5 13-Sep-2026 15:02:19 3316
ber01-VHDL13_DWON_131632-2609131632-dsw--0-ia5 13-Sep-2026 16:32:24 3316
ber01-VHDL13_DWON_131821-2609131821-dsw--0-ia5 13-Sep-2026 18:21:48 3617
ber01-VHDL13_DWON_132117-2609132117-dsw--0-ia5 13-Sep-2026 21:17:24 3595
ber01-VHDL13_DWON_140005-2609140005-dsw--0-ia5 14-Sep-2026 00:05:14 4272
ber01-VHDL13_DWON_140133-2609140133-dsw--0-ia5 14-Sep-2026 01:33:34 4248
ber01-VHDL13_DWON_140246-2609140246-dsw--0-ia5 14-Sep-2026 02:49:01 4248
ber01-VHDL13_DWON_140529-2609140529-dsw--0-ia5 14-Sep-2026 05:29:54 4152
ber01-VHDL13_DWON_140601-2609140601-dsw--0-ia5 14-Sep-2026 06:01:49 4204
ber01-VHDL13_DWON_141117-2609141117-dsw--0-ia5 14-Sep-2026 11:18:03 4084
ber01-VHDL13_DWON_141445-2609141445-dsw--0-ia5 14-Sep-2026 14:47:13 3959
ber01-VHDL13_DWON_141713-2609141713-dsw--0-ia5 14-Sep-2026 17:13:34 3746
ber01-VHDL13_DWON_141838-2609141838-dsw--0-ia5 14-Sep-2026 18:38:34 3893
ber01-VHDL13_DWON_142129-2609142129-dsw--0-ia5 14-Sep-2026 21:29:33 3879
ber01-VHDL13_DWON_150001-2609150001-dsw--0-ia5 15-Sep-2026 00:01:49 4338
ber01-VHDL13_DWON_150244-2609150244-dsw--0-ia5 15-Sep-2026 02:45:10 4332
ber01-VHDL13_DWON_150523-2609150523-dsw--0-ia5 15-Sep-2026 05:23:53 4811
ber01-VHDL13_DWON_150625-2609150625-dsw--0-ia5 15-Sep-2026 06:25:39 4751
ber01-VHDL13_DWON_150924-2609150924-dsw--0-ia5 15-Sep-2026 09:24:38 4751
ber01-VHDL13_DWPG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2134
ber01-VHDL13_DWPG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 3096
ber01-VHDL13_DWPH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2229
ber01-VHDL13_DWPH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 2979
ber01-VHDL13_DWSG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2958
ber01-VHDL13_DWSG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 3092
ber01-VHDL17_DWOG_131200-2609131200-dsw--0-ia5 13-Sep-2026 11:38:04 2843
ber01-VHDL17_DWOG_141200-2609141200-dsw--0-ia5 14-Sep-2026 11:23:43 3294
ber01-VHDL17_DWOG_151200-2609151200-dsw--0-ia5 15-Sep-2026 10:46:53 2284
swis2-VHDL20_DWEG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1405
swis2-VHDL20_DWEG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1074
swis2-VHDL20_DWEG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1064
swis2-VHDL20_DWEG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1413
swis2-VHDL20_DWEG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1547
swis2-VHDL20_DWEG_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1395
swis2-VHDL20_DWEG_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:01:19 1426
swis2-VHDL20_DWEG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 1421
swis2-VHDL20_DWEH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1459
swis2-VHDL20_DWEH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1135
swis2-VHDL20_DWEH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1121
swis2-VHDL20_DWEH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1461
swis2-VHDL20_DWEH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 1613
swis2-VHDL20_DWEH_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1429
swis2-VHDL20_DWEH_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:01:19 1461
swis2-VHDL20_DWEH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:09 1452
swis2-VHDL20_DWEI_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1428
swis2-VHDL20_DWEI_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1098
swis2-VHDL20_DWEI_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1088
swis2-VHDL20_DWEI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1434
swis2-VHDL20_DWEI_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1329
swis2-VHDL20_DWEI_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1194
swis2-VHDL20_DWEI_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:01:19 1233
swis2-VHDL20_DWEI_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 1229
swis2-VHDL20_DWHG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:45:09 1609
swis2-VHDL20_DWHG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:46:16 1432
swis2-VHDL20_DWHG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1419
swis2-VHDL20_DWHG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:45:33 1677
swis2-VHDL20_DWHG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:45:11 1795
swis2-VHDL20_DWHG_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:45:10 1536
swis2-VHDL20_DWHG_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:18 1533
swis2-VHDL20_DWHG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:45:29 1914
swis2-VHDL20_DWHH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:45:09 1607
swis2-VHDL20_DWHH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:46:16 1358
swis2-VHDL20_DWHH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1330
swis2-VHDL20_DWHH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:45:33 1569
swis2-VHDL20_DWHH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:45:11 1689
swis2-VHDL20_DWHH_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:45:10 1428
swis2-VHDL20_DWHH_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:18 1428
swis2-VHDL20_DWHH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:45:29 1840
swis2-VHDL20_DWLG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 947
swis2-VHDL20_DWLG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 821
swis2-VHDL20_DWLG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 769
swis2-VHDL20_DWLG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 877
swis2-VHDL20_DWLG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1082
swis2-VHDL20_DWLG_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:23 986
swis2-VHDL20_DWLG_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 981
swis2-VHDL20_DWLG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:31 1203
swis2-VHDL20_DWLH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 949
swis2-VHDL20_DWLH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 813
swis2-VHDL20_DWLH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 761
swis2-VHDL20_DWLH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 901
swis2-VHDL20_DWLH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1070
swis2-VHDL20_DWLH_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:23 1158
swis2-VHDL20_DWLH_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 1391
swis2-VHDL20_DWLH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:31 1636
swis2-VHDL20_DWLI_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 930
swis2-VHDL20_DWLI_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 806
swis2-VHDL20_DWLI_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 754
swis2-VHDL20_DWLI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 894
swis2-VHDL20_DWLI_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1064
swis2-VHDL20_DWLI_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:23 1152
swis2-VHDL20_DWLI_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 963
swis2-VHDL20_DWLI_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:31 1093
swis2-VHDL20_DWMO_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1259
swis2-VHDL20_DWMO_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 945
swis2-VHDL20_DWMO_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:03 947
swis2-VHDL20_DWMO_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1281
swis2-VHDL20_DWMO_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 1599
swis2-VHDL20_DWMO_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1413
swis2-VHDL20_DWMO_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:08 1389
swis2-VHDL20_DWMO_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 1369
swis2-VHDL20_DWMP_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1477
swis2-VHDL20_DWMP_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 970
swis2-VHDL20_DWMP_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:03 947
swis2-VHDL20_DWMP_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1253
swis2-VHDL20_DWMP_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 2156
swis2-VHDL20_DWMP_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1948
swis2-VHDL20_DWMP_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:08 1920
swis2-VHDL20_DWMP_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 2048
swis2-VHDL20_DWPG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 960
swis2-VHDL20_DWPG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 821
swis2-VHDL20_DWPG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 769
swis2-VHDL20_DWPG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 911
swis2-VHDL20_DWPG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1095
swis2-VHDL20_DWPG_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:23 1192
swis2-VHDL20_DWPG_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 1463
swis2-VHDL20_DWPG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:31 1629
swis2-VHDL20_DWPH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 962
swis2-VHDL20_DWPH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 824
swis2-VHDL20_DWPH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 772
swis2-VHDL20_DWPH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 914
swis2-VHDL20_DWPH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1083
swis2-VHDL20_DWPH_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:23 1091
swis2-VHDL20_DWPH_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 1325
swis2-VHDL20_DWPH_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:31 1515
swis2-VHDL20_DWSG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1183
swis2-VHDL20_DWSG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 851
swis2-VHDL20_DWSG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1147
swis2-VHDL20_DWSG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1421
swis2-VHDL20_DWSG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1564
swis2-VHDL20_DWSG_150200-2609150200-dsw--0-ia5 15-Sep-2026 02:30:12 1435
swis2-VHDL20_DWSG_150400-2609150400-dsw--0-ia5 15-Sep-2026 05:00:14 1442
swis2-VHDL20_DWSG_150800-2609150800-dsw--0-ia5 15-Sep-2026 08:30:11 1363
wst04-VHDL20_DWEG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:12 250951
wst04-VHDL20_DWEG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 249885
wst04-VHDL20_DWEG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 249904
wst04-VHDL20_DWEG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 250897
wst04-VHDL20_DWEG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:23 242247
wst04-VHDL20_DWEG_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:21 241455
wst04-VHDL20_DWEG_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:14 241453
wst04-VHDL20_DWEG_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:24 242068
wst04-VHDL20_DWEH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:12 247475
wst04-VHDL20_DWEH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 246706
wst04-VHDL20_DWEH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 246942
wst04-VHDL20_DWEH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 247976
wst04-VHDL20_DWEH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 237987
wst04-VHDL20_DWEH_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:21 237415
wst04-VHDL20_DWEH_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:18 237697
wst04-VHDL20_DWEH_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:24 238328
wst04-VHDL20_DWEI_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 357411
wst04-VHDL20_DWEI_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 356219
wst04-VHDL20_DWEI_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 356204
wst04-VHDL20_DWEI_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 357362
wst04-VHDL20_DWEI_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 344414
wst04-VHDL20_DWEI_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 344181
wst04-VHDL20_DWEI_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:14 344133
wst04-VHDL20_DWEI_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:24 344253
wst04-VHDL20_DWHG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:45:14 343271
wst04-VHDL20_DWHG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:46:16 342451
wst04-VHDL20_DWHG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 342904
wst04-VHDL20_DWHG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:45:33 343826
wst04-VHDL20_DWHG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:45:13 344221
wst04-VHDL20_DWHG_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:46:32 342843
wst04-VHDL20_DWHG_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:18 342626
wst04-VHDL20_DWHG_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:45:29 344799
wst04-VHDL20_DWHH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:45:14 338246
wst04-VHDL20_DWHH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:46:16 337679
wst04-VHDL20_DWHH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 237384
wst04-VHDL20_DWHH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:45:33 338346
wst04-VHDL20_DWHH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:45:13 341964
wst04-VHDL20_DWHH_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:46:32 340824
wst04-VHDL20_DWHH_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:24 238502
wst04-VHDL20_DWHH_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:45:29 342079
wst04-VHDL20_DWLG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 340063
wst04-VHDL20_DWLG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 340364
wst04-VHDL20_DWLG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 339862
wst04-VHDL20_DWLG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 339950
wst04-VHDL20_DWLG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 335626
wst04-VHDL20_DWLG_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 335489
wst04-VHDL20_DWLG_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:43 334864
wst04-VHDL20_DWLG_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:48 335073
wst04-VHDL20_DWLH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 336821
wst04-VHDL20_DWLH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 337110
wst04-VHDL20_DWLH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 336591
wst04-VHDL20_DWLH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 336740
wst04-VHDL20_DWLH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 336752
wst04-VHDL20_DWLH_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:44 337156
wst04-VHDL20_DWLH_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:43 336784
wst04-VHDL20_DWLH_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:51 337160
wst04-VHDL20_DWLI_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 343444
wst04-VHDL20_DWLI_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 343740
wst04-VHDL20_DWLI_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 343205
wst04-VHDL20_DWLI_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 387933
wst04-VHDL20_DWLI_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 331972
wst04-VHDL20_DWLI_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 332232
wst04-VHDL20_DWLI_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:43 331237
wst04-VHDL20_DWLI_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:48 375908
wst04-VHDL20_DWMO_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 363945
wst04-VHDL20_DWMO_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:19 470546
wst04-VHDL20_DWMO_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 470225
wst04-VHDL20_DWMO_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 471216
wst04-VHDL20_DWMO_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 351005
wst04-VHDL20_DWMO_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:21 457156
wst04-VHDL20_DWMO_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:14 456982
wst04-VHDL20_DWMO_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:24 456823
wst04-VHDL20_DWMP_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 479901
wst04-VHDL20_DWMP_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:19 586000
wst04-VHDL20_DWMP_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 585293
wst04-VHDL20_DWMP_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 477807
wst04-VHDL20_DWMP_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 472503
wst04-VHDL20_DWMP_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 579693
wst04-VHDL20_DWMP_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:18 579860
wst04-VHDL20_DWMP_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:31 473008
wst04-VHDL20_DWPG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:29 345868
wst04-VHDL20_DWPG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 243175
wst04-VHDL20_DWPG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:33 345675
wst04-VHDL20_DWPG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 390367
wst04-VHDL20_DWPG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 334278
wst04-VHDL20_DWPG_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 238018
wst04-VHDL20_DWPG_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:32 334637
wst04-VHDL20_DWPG_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:48 379451
wst04-VHDL20_DWPH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 242742
wst04-VHDL20_DWPH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 243027
wst04-VHDL20_DWPH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:33 242533
wst04-VHDL20_DWPH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 242624
wst04-VHDL20_DWPH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 242965
wst04-VHDL20_DWPH_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:23 242718
wst04-VHDL20_DWPH_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:32 242342
wst04-VHDL20_DWPH_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:48 242787
wst04-VHDL20_DWSG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 356387
wst04-VHDL20_DWSG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 355425
wst04-VHDL20_DWSG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 355742
wst04-VHDL20_DWSG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 358310
wst04-VHDL20_DWSG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:23 343185
wst04-VHDL20_DWSG_150200-2609150200-omedes--0.pdf 15-Sep-2026 02:30:21 341935
wst04-VHDL20_DWSG_150400-2609150400-omedes--0.pdf 15-Sep-2026 05:00:14 341995
wst04-VHDL20_DWSG_150800-2609150800-omedes--0.pdf 15-Sep-2026 08:30:11 341948