Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Mar-2026 13:55:53 5005
FPDL13_DWMZ_280600 28-Feb-2026 13:30:40 8518
SXDL31_DWAV_010800 01-Mar-2026 07:55:39 6416
SXDL31_DWAV_011800 01-Mar-2026 17:23:35 3783
SXDL31_DWAV_280800 28-Feb-2026 08:53:09 7922
SXDL31_DWAV_281800 28-Feb-2026 18:11:58 4583
SXDL31_DWAV_LATEST 01-Mar-2026 17:23:35 3783
SXDL33_DWAV_010000 01-Mar-2026 11:01:49 7444
SXDL33_DWAV_280000 28-Feb-2026 10:27:19 6914
SXDL33_DWAV_LATEST 01-Mar-2026 11:01:49 7444
ber01-FWDL39_DWMS_011230-2603011230-dsw--0-ia5 01-Mar-2026 12:23:17 1420
ber01-FWDL39_DWMS_281230-2602281230-dsw--0-ia5 28-Feb-2026 12:52:31 2061
ber01-VHDL13_DWEH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:28:11 2322
ber01-VHDL13_DWEH_010400-2603010400-dsw--0-ia5 01-Mar-2026 05:58:16 2337
ber01-VHDL13_DWEH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:28:17 2438
ber01-VHDL13_DWEH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:28:17 2281
ber01-VHDL13_DWEH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:11 3182
ber01-VHDL13_DWEH_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:17 3051
ber01-VHDL13_DWEH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:17 3042
ber01-VHDL13_DWEH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:28:17 2471
ber01-VHDL13_DWHG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:11 2564
ber01-VHDL13_DWHG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2567
ber01-VHDL13_DWHG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2599
ber01-VHDL13_DWHG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 2316
ber01-VHDL13_DWHG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2945
ber01-VHDL13_DWHG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2949
ber01-VHDL13_DWHG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 3033
ber01-VHDL13_DWHG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:10 2612
ber01-VHDL13_DWHH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:11 2458
ber01-VHDL13_DWHH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2294
ber01-VHDL13_DWHH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2425
ber01-VHDL13_DWHH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 2189
ber01-VHDL13_DWHH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2718
ber01-VHDL13_DWHH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2732
ber01-VHDL13_DWHH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2492
ber01-VHDL13_DWHH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:10 2298
ber01-VHDL13_DWLG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 1831
ber01-VHDL13_DWLG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 1683
ber01-VHDL13_DWLG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 1663
ber01-VHDL13_DWLG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 1544
ber01-VHDL13_DWLG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2036
ber01-VHDL13_DWLG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 1994
ber01-VHDL13_DWLG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2051
ber01-VHDL13_DWLG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 1719
ber01-VHDL13_DWLH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2183
ber01-VHDL13_DWLH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 2037
ber01-VHDL13_DWLH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 1980
ber01-VHDL13_DWLH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 1846
ber01-VHDL13_DWLH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2296
ber01-VHDL13_DWLH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 2335
ber01-VHDL13_DWLH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2337
ber01-VHDL13_DWLH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 2077
ber01-VHDL13_DWLI_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 1869
ber01-VHDL13_DWLI_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 1626
ber01-VHDL13_DWLI_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 1602
ber01-VHDL13_DWLI_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 1557
ber01-VHDL13_DWLI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 1999
ber01-VHDL13_DWLI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 2049
ber01-VHDL13_DWLI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2051
ber01-VHDL13_DWLI_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 1739
ber01-VHDL13_DWMG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2451
ber01-VHDL13_DWMG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 2406
ber01-VHDL13_DWMG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2314
ber01-VHDL13_DWMG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:05 2258
ber01-VHDL13_DWMG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2418
ber01-VHDL13_DWMG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2405
ber01-VHDL13_DWMG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2563
ber01-VHDL13_DWMG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 2427
ber01-VHDL13_DWMO_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2455
ber01-VHDL13_DWMO_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 2441
ber01-VHDL13_DWMO_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2358
ber01-VHDL13_DWMO_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:05 2197
ber01-VHDL13_DWMO_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2520
ber01-VHDL13_DWMO_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2515
ber01-VHDL13_DWMO_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2709
ber01-VHDL13_DWMO_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 2465
ber01-VHDL13_DWMP_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2447
ber01-VHDL13_DWMP_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 2465
ber01-VHDL13_DWMP_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2376
ber01-VHDL13_DWMP_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:05 2181
ber01-VHDL13_DWMP_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2047
ber01-VHDL13_DWMP_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:03 2035
ber01-VHDL13_DWMP_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:05 2258
ber01-VHDL13_DWMP_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 1884
ber01-VHDL13_DWOG_010300-2603010300-dsw--0-ia5 01-Mar-2026 04:00:07 3587
ber01-VHDL13_DWOG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 3355
ber01-VHDL13_DWOG_011700-2603011700-dsw--0-ia5 01-Mar-2026 19:00:06 3115
ber01-VHDL13_DWOG_280300-2602280300-dsw--0-ia5 28-Feb-2026 04:00:06 3612
ber01-VHDL13_DWOG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 3335
ber01-VHDL13_DWOG_281700-2602281700-dsw--0-ia5 28-Feb-2026 19:00:07 3473
ber01-VHDL13_DWOH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:28:11 2416
ber01-VHDL13_DWOH_010400-2603010400-dsw--0-ia5 01-Mar-2026 05:58:12 2453
ber01-VHDL13_DWOH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:28:17 2313
ber01-VHDL13_DWOH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:28:17 2206
ber01-VHDL13_DWOH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:11 2788
ber01-VHDL13_DWOH_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:11 2735
ber01-VHDL13_DWOH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:17 2788
ber01-VHDL13_DWOH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:28:17 2420
ber01-VHDL13_DWOI_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:28:15 2509
ber01-VHDL13_DWOI_010400-2603010400-dsw--0-ia5 01-Mar-2026 05:58:16 2485
ber01-VHDL13_DWOI_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:28:11 2339
ber01-VHDL13_DWOI_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:28:13 2251
ber01-VHDL13_DWOI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:28:17 2905
ber01-VHDL13_DWOI_280400-2602280400-dsw--0-ia5 28-Feb-2026 05:58:17 2849
ber01-VHDL13_DWOI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:28:13 3000
ber01-VHDL13_DWOI_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:28:17 2545
ber01-VHDL13_DWON_010228-2603010228-dsw--0-ia5 01-Mar-2026 02:28:42 2993
ber01-VHDL13_DWON_010615-2603010615-dsw--0-ia5 01-Mar-2026 06:15:16 3118
ber01-VHDL13_DWON_010627-2603010627-dsw--0-ia5 01-Mar-2026 06:27:47 3607
ber01-VHDL13_DWON_010701-2603010701-dsw--0-ia5 01-Mar-2026 07:01:17 3709
ber01-VHDL13_DWON_010750-2603010750-dsw--0-ia5 01-Mar-2026 07:50:21 3637
ber01-VHDL13_DWON_010902-2603010902-dsw--0-ia5 01-Mar-2026 09:02:16 3637
ber01-VHDL13_DWON_011104-2603011104-dsw--0-ia5 01-Mar-2026 11:04:17 3603
ber01-VHDL13_DWON_011313-2603011313-dsw--0-ia5 01-Mar-2026 13:13:52 3604
ber01-VHDL13_DWON_011549-2603011549-dsw--0-ia5 01-Mar-2026 15:49:10 3040
ber01-VHDL13_DWON_011729-2603011729-dsw--0-ia5 01-Mar-2026 17:29:31 3008
ber01-VHDL13_DWON_272338-2602272338-dsw--0-ia5 27-Feb-2026 23:39:01 3398
ber01-VHDL13_DWON_280153-2602280153-dsw--0-ia5 28-Feb-2026 01:53:06 3398
ber01-VHDL13_DWON_280353-2602280353-dsw--0-ia5 28-Feb-2026 03:53:22 3398
ber01-VHDL13_DWON_280629-2602280629-dsw--0-ia5 28-Feb-2026 06:29:17 3162
ber01-VHDL13_DWON_280725-2602280725-dsw--0-ia5 28-Feb-2026 07:25:26 2888
ber01-VHDL13_DWON_280942-2602280942-dsw--0-ia5 28-Feb-2026 09:42:31 2888
ber01-VHDL13_DWON_281539-2602281539-dsw--0-ia5 28-Feb-2026 15:40:06 2652
ber01-VHDL13_DWON_281541-2602281541-dsw--0-ia5 28-Feb-2026 15:41:47 2652
ber01-VHDL13_DWON_281833-2602281833-dsw--0-ia5 28-Feb-2026 18:33:11 3007
ber01-VHDL13_DWPG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 1910
ber01-VHDL13_DWPG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 1811
ber01-VHDL13_DWPG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 1953
ber01-VHDL13_DWPG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 1727
ber01-VHDL13_DWPG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 1885
ber01-VHDL13_DWPG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:01 1901
ber01-VHDL13_DWPG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 1888
ber01-VHDL13_DWPG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 1717
ber01-VHDL13_DWPH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2182
ber01-VHDL13_DWPH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:02 1929
ber01-VHDL13_DWPH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 1731
ber01-VHDL13_DWPH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:10 1577
ber01-VHDL13_DWPH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2090
ber01-VHDL13_DWPH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2115
ber01-VHDL13_DWPH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2085
ber01-VHDL13_DWPH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 2016
ber01-VHDL13_DWSG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:30:05 2223
ber01-VHDL13_DWSG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:06 2774
ber01-VHDL13_DWSG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:30:09 2652
ber01-VHDL13_DWSG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:30:05 2172
ber01-VHDL13_DWSG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:30:07 2165
ber01-VHDL13_DWSG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2345
ber01-VHDL13_DWSG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:30:01 2323
ber01-VHDL13_DWSG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:30:04 2095
ber01-VHDL17_DWOG_011200-2603011200-dsw--0-ia5 01-Mar-2026 12:50:53 2525
ber01-VHDL17_DWOG_281200-2602281200-dsw--0-ia5 28-Feb-2026 12:20:27 1713
swis2-VHDL20_DWEG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2693
swis2-VHDL20_DWEG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:06 2773
swis2-VHDL20_DWEG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2790
swis2-VHDL20_DWEG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2532
swis2-VHDL20_DWEG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3065
swis2-VHDL20_DWEG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3162
swis2-VHDL20_DWEG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3371
swis2-VHDL20_DWEG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:06 2854
swis2-VHDL20_DWEH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2644
swis2-VHDL20_DWEH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:06 2672
swis2-VHDL20_DWEH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2940
swis2-VHDL20_DWEH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2634
swis2-VHDL20_DWEH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3504
swis2-VHDL20_DWEH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3387
swis2-VHDL20_DWEH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3543
swis2-VHDL20_DWEH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:06 2826
swis2-VHDL20_DWEI_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2805
swis2-VHDL20_DWEI_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:06 2836
swis2-VHDL20_DWEI_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2863
swis2-VHDL20_DWEI_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2602
swis2-VHDL20_DWEI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 3198
swis2-VHDL20_DWEI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 3310
swis2-VHDL20_DWEI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3633
swis2-VHDL20_DWEI_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:06 3007
swis2-VHDL20_DWHG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2750
swis2-VHDL20_DWHG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2750
swis2-VHDL20_DWHG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 3127
swis2-VHDL20_DWHG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2499
swis2-VHDL20_DWHG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 3131
swis2-VHDL20_DWHG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 3132
swis2-VHDL20_DWHG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3572
swis2-VHDL20_DWHG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2795
swis2-VHDL20_DWHH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2644
swis2-VHDL20_DWHH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2480
swis2-VHDL20_DWHH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2964
swis2-VHDL20_DWHH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2375
swis2-VHDL20_DWHH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2904
swis2-VHDL20_DWHH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:07 2918
swis2-VHDL20_DWHH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3040
swis2-VHDL20_DWHH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2484
swis2-VHDL20_DWLG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2173
swis2-VHDL20_DWLG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2028
swis2-VHDL20_DWLG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2155
swis2-VHDL20_DWLG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:06 1889
swis2-VHDL20_DWLG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2378
swis2-VHDL20_DWLG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2336
swis2-VHDL20_DWLG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2542
swis2-VHDL20_DWLG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2061
swis2-VHDL20_DWLH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2532
swis2-VHDL20_DWLH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2388
swis2-VHDL20_DWLH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2482
swis2-VHDL20_DWLH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:06 2197
swis2-VHDL20_DWLH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2645
swis2-VHDL20_DWLH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2684
swis2-VHDL20_DWLH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2838
swis2-VHDL20_DWLH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2426
swis2-VHDL20_DWLI_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2213
swis2-VHDL20_DWLI_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 1973
swis2-VHDL20_DWLI_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2095
swis2-VHDL20_DWLI_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:06 1904
swis2-VHDL20_DWLI_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2343
swis2-VHDL20_DWLI_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2393
swis2-VHDL20_DWLI_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2543
swis2-VHDL20_DWLI_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2083
swis2-VHDL20_DWMG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2788
swis2-VHDL20_DWMG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:02 2838
swis2-VHDL20_DWMG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:06 2957
swis2-VHDL20_DWMG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2743
swis2-VHDL20_DWMG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2814
swis2-VHDL20_DWMG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2776
swis2-VHDL20_DWMG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3153
swis2-VHDL20_DWMG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2798
swis2-VHDL20_DWMO_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2830
swis2-VHDL20_DWMO_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:02 2877
swis2-VHDL20_DWMO_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:06 3012
swis2-VHDL20_DWMO_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2655
swis2-VHDL20_DWMO_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2895
swis2-VHDL20_DWMO_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2889
swis2-VHDL20_DWMO_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 3307
swis2-VHDL20_DWMO_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2840
swis2-VHDL20_DWMP_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2821
swis2-VHDL20_DWMP_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:02 2897
swis2-VHDL20_DWMP_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:06 3028
swis2-VHDL20_DWMP_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2795
swis2-VHDL20_DWMP_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2470
swis2-VHDL20_DWMP_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:02 2405
swis2-VHDL20_DWMP_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:06 2853
swis2-VHDL20_DWMP_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2332
swis2-VHDL20_DWPG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2239
swis2-VHDL20_DWPG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2137
swis2-VHDL20_DWPG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2413
swis2-VHDL20_DWPG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:06 2187
swis2-VHDL20_DWPG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2214
swis2-VHDL20_DWPG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2227
swis2-VHDL20_DWPG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2347
swis2-VHDL20_DWPG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2176
swis2-VHDL20_DWPH_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2510
swis2-VHDL20_DWPH_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:00:12 2257
swis2-VHDL20_DWPH_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 2191
swis2-VHDL20_DWPH_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:06 2037
swis2-VHDL20_DWPH_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:07 2418
swis2-VHDL20_DWPH_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:00:11 2443
swis2-VHDL20_DWPH_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2544
swis2-VHDL20_DWPH_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2475
swis2-VHDL20_DWSG_010200-2603010200-dsw--0-ia5 01-Mar-2026 03:45:06 2568
swis2-VHDL20_DWSG_010400-2603010400-dsw--0-ia5 01-Mar-2026 06:15:02 3172
swis2-VHDL20_DWSG_010800-2603010800-dsw--0-ia5 01-Mar-2026 09:45:02 3218
swis2-VHDL20_DWSG_011300-2603011300-dsw--0-ia5 01-Mar-2026 14:45:04 3012
swis2-VHDL20_DWSG_011800-2603011800-dsw--0-ia5 01-Mar-2026 19:45:04 2582
swis2-VHDL20_DWSG_280200-2602280200-dsw--0-ia5 28-Feb-2026 03:45:01 2510
swis2-VHDL20_DWSG_280400-2602280400-dsw--0-ia5 28-Feb-2026 06:15:05 2698
swis2-VHDL20_DWSG_280800-2602280800-dsw--0-ia5 28-Feb-2026 09:45:02 2882
swis2-VHDL20_DWSG_281300-2602281300-dsw--0-ia5 28-Feb-2026 14:45:06 2748
swis2-VHDL20_DWSG_281800-2602281800-dsw--0-ia5 28-Feb-2026 19:45:02 2450
wst04-VHDL20_DWEG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:16 241340
wst04-VHDL20_DWEG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:16 240866
wst04-VHDL20_DWEG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:16 242425
wst04-VHDL20_DWEG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:12 241549
wst04-VHDL20_DWEG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 247335
wst04-VHDL20_DWEG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 246682
wst04-VHDL20_DWEG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 243329
wst04-VHDL20_DWEG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:12 241562
wst04-VHDL20_DWEH_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:16 244463
wst04-VHDL20_DWEH_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:22 244301
wst04-VHDL20_DWEH_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:12 240645
wst04-VHDL20_DWEH_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:12 240156
wst04-VHDL20_DWEH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 250729
wst04-VHDL20_DWEH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:27 250354
wst04-VHDL20_DWEH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 246687
wst04-VHDL20_DWEH_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:12 244427
wst04-VHDL20_DWEI_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:16 347310
wst04-VHDL20_DWEI_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:26 347603
wst04-VHDL20_DWEI_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:16 348200
wst04-VHDL20_DWEI_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:16 347321
wst04-VHDL20_DWEI_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:13 354501
wst04-VHDL20_DWEI_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 354308
wst04-VHDL20_DWEI_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:16 349394
wst04-VHDL20_DWEI_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:16 347679
wst04-VHDL20_DWHG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:22 349404
wst04-VHDL20_DWHG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:12 349615
wst04-VHDL20_DWHG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:22 344610
wst04-VHDL20_DWHG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:22 343216
wst04-VHDL20_DWHG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 354339
wst04-VHDL20_DWHG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:11 354409
wst04-VHDL20_DWHG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 351205
wst04-VHDL20_DWHG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:22 349604
wst04-VHDL20_DWHH_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:22 330410
wst04-VHDL20_DWHH_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:12 330397
wst04-VHDL20_DWHH_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:22 328755
wst04-VHDL20_DWHH_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:22 328065
wst04-VHDL20_DWHH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 331822
wst04-VHDL20_DWHH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:11 331944
wst04-VHDL20_DWHH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 330716
wst04-VHDL20_DWHH_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:22 329779
wst04-VHDL20_DWLG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:26 332962
wst04-VHDL20_DWLG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:42 332422
wst04-VHDL20_DWLG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:32 327783
wst04-VHDL20_DWLG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:26 327154
wst04-VHDL20_DWLG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 340425
wst04-VHDL20_DWLG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 341375
wst04-VHDL20_DWLG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 334346
wst04-VHDL20_DWLG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:26 332588
wst04-VHDL20_DWLH_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:26 338283
wst04-VHDL20_DWLH_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:42 337870
wst04-VHDL20_DWLH_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:36 335368
wst04-VHDL20_DWLH_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:20 334240
wst04-VHDL20_DWLH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 346306
wst04-VHDL20_DWLH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 347355
wst04-VHDL20_DWLH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 339165
wst04-VHDL20_DWLH_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:26 337876
wst04-VHDL20_DWLI_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:26 340839
wst04-VHDL20_DWLI_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:42 340284
wst04-VHDL20_DWLI_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:36 340182
wst04-VHDL20_DWLI_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:26 339583
wst04-VHDL20_DWLI_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 339530
wst04-VHDL20_DWLI_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:41 340631
wst04-VHDL20_DWLI_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 342134
wst04-VHDL20_DWLI_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:22 340516
wst04-VHDL20_DWMG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:12 559492
wst04-VHDL20_DWMG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:28 559257
wst04-VHDL20_DWMG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:26 559228
wst04-VHDL20_DWMG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:16 559333
wst04-VHDL20_DWMG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:17 575655
wst04-VHDL20_DWMG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 575574
wst04-VHDL20_DWMG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:26 559988
wst04-VHDL20_DWMG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:16 559257
wst04-VHDL20_DWMO_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:12 461041
wst04-VHDL20_DWMO_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:22 461434
wst04-VHDL20_DWMO_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:26 460589
wst04-VHDL20_DWMO_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:16 459591
wst04-VHDL20_DWMO_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:17 475695
wst04-VHDL20_DWMO_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:17 476242
wst04-VHDL20_DWMO_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:22 461726
wst04-VHDL20_DWMO_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:16 460929
wst04-VHDL20_DWMP_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:12 556221
wst04-VHDL20_DWMP_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:22 556961
wst04-VHDL20_DWMP_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:26 551353
wst04-VHDL20_DWMP_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:16 551363
wst04-VHDL20_DWMP_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 560839
wst04-VHDL20_DWMP_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:23 561656
wst04-VHDL20_DWMP_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:22 556874
wst04-VHDL20_DWMP_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:16 556041
wst04-VHDL20_DWPG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:26 347175
wst04-VHDL20_DWPG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:30 346712
wst04-VHDL20_DWPG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:32 384511
wst04-VHDL20_DWPG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:26 339752
wst04-VHDL20_DWPG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:28 352156
wst04-VHDL20_DWPG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:31 353065
wst04-VHDL20_DWPG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:36 392219
wst04-VHDL20_DWPG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:26 347221
wst04-VHDL20_DWPH_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:22 247349
wst04-VHDL20_DWPH_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:00:30 246474
wst04-VHDL20_DWPH_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:32 289455
wst04-VHDL20_DWPH_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:20 289230
wst04-VHDL20_DWPH_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:21 245841
wst04-VHDL20_DWPH_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:00:31 246399
wst04-VHDL20_DWPH_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:32 292242
wst04-VHDL20_DWPH_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:22 291924
wst04-VHDL20_DWSG_010200-2603010200-omedes--0.pdf 01-Mar-2026 03:45:22 357436
wst04-VHDL20_DWSG_010400-2603010400-omedes--0.pdf 01-Mar-2026 06:15:12 357136
wst04-VHDL20_DWSG_010800-2603010800-omedes--0.pdf 01-Mar-2026 09:45:12 350773
wst04-VHDL20_DWSG_011300-2603011300-omedes--0.pdf 01-Mar-2026 14:45:12 351491
wst04-VHDL20_DWSG_011800-2603011800-omedes--0.pdf 01-Mar-2026 19:45:12 350281
wst04-VHDL20_DWSG_280200-2602280200-omedes--0.pdf 28-Feb-2026 03:45:11 355227
wst04-VHDL20_DWSG_280400-2602280400-omedes--0.pdf 28-Feb-2026 06:15:17 356284
wst04-VHDL20_DWSG_280800-2602280800-omedes--0.pdf 28-Feb-2026 09:45:12 358120
wst04-VHDL20_DWSG_281300-2602281300-omedes--0.pdf 28-Feb-2026 14:45:12 357205
wst04-VHDL20_DWSG_281800-2602281800-omedes--0.pdf 28-Feb-2026 19:45:12 357117