Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Mar-2026 14:45:27 5333
FPDL13_DWMZ_140600 14-Mar-2026 11:56:35 2692
SXDL31_DWAV_130800 13-Mar-2026 08:41:05 9569
SXDL31_DWAV_131800 13-Mar-2026 17:46:01 7016
SXDL31_DWAV_140800 14-Mar-2026 08:52:01 8044
SXDL31_DWAV_141800 14-Mar-2026 17:29:39 7365
SXDL31_DWAV_LATEST 14-Mar-2026 17:29:39 7365
SXDL33_DWAV_130000 13-Mar-2026 10:59:19 9076
SXDL33_DWAV_140000 14-Mar-2026 10:27:35 5585
SXDL33_DWAV_LATEST 14-Mar-2026 10:27:35 5585
ber01-FWDL39_DWMS_131230-2603131230-dsw--0-ia5 13-Mar-2026 13:00:47 2650
ber01-FWDL39_DWMS_141230-2603141230-dsw--0-ia5 14-Mar-2026 12:52:23 1814
ber01-VHDL13_DWEH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:16 2904
ber01-VHDL13_DWEH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 3142
ber01-VHDL13_DWEH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:17 3397
ber01-VHDL13_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 3160
ber01-VHDL13_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:16 3115
ber01-VHDL13_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 3274
ber01-VHDL13_DWEH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:17 3256
ber01-VHDL13_DWEH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:17 3821
ber01-VHDL13_DWEH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:16 3679
ber01-VHDL13_DWEH_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:17 3136
ber01-VHDL13_DWHG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 4173
ber01-VHDL13_DWHG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:46:07 4125
ber01-VHDL13_DWHG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:07 3509
ber01-VHDL13_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2869
ber01-VHDL13_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 2940
ber01-VHDL13_DWHG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2956
ber01-VHDL13_DWHG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2706
ber01-VHDL13_DWHG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 3565
ber01-VHDL13_DWHG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3565
ber01-VHDL13_DWHH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 2946
ber01-VHDL13_DWHH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:46:27 2903
ber01-VHDL13_DWHH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:07 2406
ber01-VHDL13_DWHH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2202
ber01-VHDL13_DWHH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:06 2236
ber01-VHDL13_DWHH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2273
ber01-VHDL13_DWHH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2301
ber01-VHDL13_DWHH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2804
ber01-VHDL13_DWHH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2804
ber01-VHDL13_DWLG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2762
ber01-VHDL13_DWLG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2244
ber01-VHDL13_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2420
ber01-VHDL13_DWLG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2287
ber01-VHDL13_DWLG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2223
ber01-VHDL13_DWLG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1952
ber01-VHDL13_DWLG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2158
ber01-VHDL13_DWLG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2923
ber01-VHDL13_DWLH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 3618
ber01-VHDL13_DWLH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2503
ber01-VHDL13_DWLH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2577
ber01-VHDL13_DWLH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2474
ber01-VHDL13_DWLH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2474
ber01-VHDL13_DWLH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2018
ber01-VHDL13_DWLH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2638
ber01-VHDL13_DWLH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2923
ber01-VHDL13_DWLI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 3322
ber01-VHDL13_DWLI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2378
ber01-VHDL13_DWLI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2493
ber01-VHDL13_DWLI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2319
ber01-VHDL13_DWLI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2308
ber01-VHDL13_DWLI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2058
ber01-VHDL13_DWLI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2621
ber01-VHDL13_DWLI_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2862
ber01-VHDL13_DWMG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3609
ber01-VHDL13_DWMG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:36:28 3615
ber01-VHDL13_DWMG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3536
ber01-VHDL13_DWMG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3524
ber01-VHDL13_DWMG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3370
ber01-VHDL13_DWMG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 3370
ber01-VHDL13_DWMG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 3034
ber01-VHDL13_DWMG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2861
ber01-VHDL13_DWMG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2826
ber01-VHDL13_DWMO_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 2876
ber01-VHDL13_DWMO_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 2672
ber01-VHDL13_DWMO_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2937
ber01-VHDL13_DWMO_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2937
ber01-VHDL13_DWMO_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2861
ber01-VHDL13_DWMO_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2662
ber01-VHDL13_DWMO_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2580
ber01-VHDL13_DWMO_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2839
ber01-VHDL13_DWMP_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3184
ber01-VHDL13_DWMP_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3606
ber01-VHDL13_DWMP_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3613
ber01-VHDL13_DWMP_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3593
ber01-VHDL13_DWMP_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 3240
ber01-VHDL13_DWMP_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2865
ber01-VHDL13_DWMP_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2837
ber01-VHDL13_DWMP_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2799
ber01-VHDL13_DWOG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 4453
ber01-VHDL13_DWOG_131700-2603131700-dsw--0-ia5 13-Mar-2026 19:00:03 5200
ber01-VHDL13_DWOG_140300-2603140300-dsw--0-ia5 14-Mar-2026 04:00:05 4603
ber01-VHDL13_DWOG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 4336
ber01-VHDL13_DWOG_141700-2603141700-dsw--0-ia5 14-Mar-2026 19:00:02 4064
ber01-VHDL13_DWOG_150300-2603150300-dsw--0-ia5 15-Mar-2026 04:00:06 4315
ber01-VHDL13_DWOH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:16 2816
ber01-VHDL13_DWOH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 2879
ber01-VHDL13_DWOH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:11 3017
ber01-VHDL13_DWOH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2819
ber01-VHDL13_DWOH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:21 2676
ber01-VHDL13_DWOH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:13 2501
ber01-VHDL13_DWOH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:17 3396
ber01-VHDL13_DWOH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:12 3340
ber01-VHDL13_DWOH_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:11 3064
ber01-VHDL13_DWOI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:28:12 2668
ber01-VHDL13_DWOI_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:17 2721
ber01-VHDL13_DWOI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:28:11 3243
ber01-VHDL13_DWOI_131800_COR-2603131800-dsw--0-ia5 13-Mar-2026 19:31:15 2973
ber01-VHDL13_DWOI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2824
ber01-VHDL13_DWOI_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 2723
ber01-VHDL13_DWOI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:13 2597
ber01-VHDL13_DWOI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:11 3558
ber01-VHDL13_DWOI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:12 3354
ber01-VHDL13_DWOI_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:17 3062
ber01-VHDL13_DWON_130845-2603130845-dsw--0-ia5 13-Mar-2026 08:45:53 4725
ber01-VHDL13_DWON_130918-2603130918-dsw--0-ia5 13-Mar-2026 09:18:23 4725
ber01-VHDL13_DWON_131015-2603131015-dsw--0-ia5 13-Mar-2026 10:16:00 4725
ber01-VHDL13_DWON_131558-2603131558-dsw--0-ia5 13-Mar-2026 15:59:02 4223
ber01-VHDL13_DWON_131756-2603131756-dsw--0-ia5 13-Mar-2026 17:56:46 4223
ber01-VHDL13_DWON_140240-2603140240-dsw--0-ia5 14-Mar-2026 02:40:14 3438
ber01-VHDL13_DWON_140613-2603140613-dsw--0-ia5 14-Mar-2026 06:13:53 4314
ber01-VHDL13_DWON_140655-2603140655-dsw--0-ia5 14-Mar-2026 06:55:27 4314
ber01-VHDL13_DWON_140848-2603140848-dsw--0-ia5 14-Mar-2026 08:48:16 4192
ber01-VHDL13_DWON_140953-2603140953-dsw--0-ia5 14-Mar-2026 09:53:16 4192
ber01-VHDL13_DWON_141554-2603141554-dsw--0-ia5 14-Mar-2026 15:54:31 3733
ber01-VHDL13_DWON_141802-2603141802-dsw--0-ia5 14-Mar-2026 18:02:21 3496
ber01-VHDL13_DWON_150131-2603150131-dsw--0-ia5 15-Mar-2026 01:31:59 4068
ber01-VHDL13_DWON_150341-2603150341-dsw--0-ia5 15-Mar-2026 03:41:36 4068
ber01-VHDL13_DWON_150621-2603150621-dsw--0-ia5 15-Mar-2026 06:21:27 3742
ber01-VHDL13_DWPG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2663
ber01-VHDL13_DWPG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 1980
ber01-VHDL13_DWPG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:15 2173
ber01-VHDL13_DWPG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2129
ber01-VHDL13_DWPG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2128
ber01-VHDL13_DWPG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1599
ber01-VHDL13_DWPG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 1946
ber01-VHDL13_DWPG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 1835
ber01-VHDL13_DWPH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:00 2587
ber01-VHDL13_DWPH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 1885
ber01-VHDL13_DWPH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2130
ber01-VHDL13_DWPH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2125
ber01-VHDL13_DWPH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2125
ber01-VHDL13_DWPH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1642
ber01-VHDL13_DWPH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 1924
ber01-VHDL13_DWPH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 1832
ber01-VHDL13_DWSG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:30:07 3432
ber01-VHDL13_DWSG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:30:03 3356
ber01-VHDL13_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3628
ber01-VHDL13_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3780
ber01-VHDL13_DWSG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:02 3466
ber01-VHDL13_DWSG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 3094
ber01-VHDL13_DWSG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 3532
ber01-VHDL13_DWSG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3619
ber01-VHDL17_DWOG_131200-2603131200-dsw--0-ia5 13-Mar-2026 12:31:33 3012
ber01-VHDL17_DWOG_141200-2603141200-dsw--0-ia5 14-Mar-2026 12:14:36 2747
swis2-VHDL20_DWEG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3572
swis2-VHDL20_DWEG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3576
swis2-VHDL20_DWEG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3448
swis2-VHDL20_DWEG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3184
swis2-VHDL20_DWEG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3109
swis2-VHDL20_DWEG_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3113
swis2-VHDL20_DWEG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3214
swis2-VHDL20_DWEG_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:03:36 4211
swis2-VHDL20_DWEG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3817
swis2-VHDL20_DWEG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3711
swis2-VHDL20_DWEG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3498
swis2-VHDL20_DWEH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3837
swis2-VHDL20_DWEH_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3841
swis2-VHDL20_DWEH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3854
swis2-VHDL20_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3568
swis2-VHDL20_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3701
swis2-VHDL20_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3705
swis2-VHDL20_DWEH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 4035
swis2-VHDL20_DWEH_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:03:52 4646
swis2-VHDL20_DWEH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 4364
swis2-VHDL20_DWEH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 4189
swis2-VHDL20_DWEH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3593
swis2-VHDL20_DWEI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3424
swis2-VHDL20_DWEI_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:32:05 3428
swis2-VHDL20_DWEI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3409
swis2-VHDL20_DWEI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3205
swis2-VHDL20_DWEI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3166
swis2-VHDL20_DWEI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3170
swis2-VHDL20_DWEI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3416
swis2-VHDL20_DWEI_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:04:02 4454
swis2-VHDL20_DWEI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:06 4088
swis2-VHDL20_DWEI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3825
swis2-VHDL20_DWEI_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3517
swis2-VHDL20_DWHG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:06 4951
swis2-VHDL20_DWHG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3692
swis2-VHDL20_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:07 3055
swis2-VHDL20_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3123
swis2-VHDL20_DWHG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3637
swis2-VHDL20_DWHG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2889
swis2-VHDL20_DWHG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3751
swis2-VHDL20_DWHG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3748
swis2-VHDL20_DWHH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:06 3548
swis2-VHDL20_DWHH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 2592
swis2-VHDL20_DWHH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:07 2388
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swis2-VHDL20_DWHH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 2990
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swis2-VHDL20_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2762
swis2-VHDL20_DWLG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2676
swis2-VHDL20_DWLG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2809
swis2-VHDL20_DWLG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2334
swis2-VHDL20_DWLG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 2540
swis2-VHDL20_DWLG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 3308
swis2-VHDL20_DWLH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4297
swis2-VHDL20_DWLH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2899
swis2-VHDL20_DWLH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2926
swis2-VHDL20_DWLH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2884
swis2-VHDL20_DWLH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3089
swis2-VHDL20_DWLH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2428
swis2-VHDL20_DWLH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3048
swis2-VHDL20_DWLH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 3315
swis2-VHDL20_DWLI_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3959
swis2-VHDL20_DWLI_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2722
swis2-VHDL20_DWLI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2837
swis2-VHDL20_DWLI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2728
swis2-VHDL20_DWLI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2920
swis2-VHDL20_DWLI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2467
swis2-VHDL20_DWLI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3030
swis2-VHDL20_DWLI_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 3252
swis2-VHDL20_DWMG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4249
swis2-VHDL20_DWMG_130800_COR-2603130800-dsw--0-ia5 13-Mar-2026 09:36:28 4253
swis2-VHDL20_DWMG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3906
swis2-VHDL20_DWMG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3895
swis2-VHDL20_DWMG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3843
swis2-VHDL20_DWMG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:02 4132
swis2-VHDL20_DWMG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3508
swis2-VHDL20_DWMG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3335
swis2-VHDL20_DWMG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3324
swis2-VHDL20_DWMO_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3480
swis2-VHDL20_DWMO_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3046
swis2-VHDL20_DWMO_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3314
swis2-VHDL20_DWMO_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3418
swis2-VHDL20_DWMO_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:02 3549
swis2-VHDL20_DWMO_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3088
swis2-VHDL20_DWMO_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3009
swis2-VHDL20_DWMO_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3316
swis2-VHDL20_DWMP_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3809
swis2-VHDL20_DWMP_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:06 3965
swis2-VHDL20_DWMP_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3986
swis2-VHDL20_DWMP_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3814
swis2-VHDL20_DWMP_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:02 3988
swis2-VHDL20_DWMP_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3305
swis2-VHDL20_DWMP_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3304
swis2-VHDL20_DWMP_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3288
swis2-VHDL20_DWPG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3122
swis2-VHDL20_DWPG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2439
swis2-VHDL20_DWPG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2502
swis2-VHDL20_DWPG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2455
swis2-VHDL20_DWPG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2586
swis2-VHDL20_DWPG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2057
swis2-VHDL20_DWPG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 2275
swis2-VHDL20_DWPG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 2160
swis2-VHDL20_DWPH_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 3046
swis2-VHDL20_DWPH_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 2344
swis2-VHDL20_DWPH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2458
swis2-VHDL20_DWPH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:11 2453
swis2-VHDL20_DWPH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2583
swis2-VHDL20_DWPH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2100
swis2-VHDL20_DWPH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 2252
swis2-VHDL20_DWPH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 2159
swis2-VHDL20_DWSG_130800-2603130800-dsw--0-ia5 13-Mar-2026 09:45:02 4043
swis2-VHDL20_DWSG_131300-2603131300-dsw--0-ia5 13-Mar-2026 14:45:15 3875
swis2-VHDL20_DWSG_131800-2603131800-dsw--0-ia5 13-Mar-2026 19:45:01 3771
swis2-VHDL20_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 4036
swis2-VHDL20_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 4215
swis2-VHDL20_DWSG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:02 4112
swis2-VHDL20_DWSG_141300-2603141300-dsw--0-ia5 14-Mar-2026 14:45:07 3947
swis2-VHDL20_DWSG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3531
swis2-VHDL20_DWSG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3962
swis2-VHDL20_DWSG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3996
wst04-VHDL20_DWEG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 251854
wst04-VHDL20_DWEG_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 249769
wst04-VHDL20_DWEG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 251996
wst04-VHDL20_DWEG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:15 251482
wst04-VHDL20_DWEG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:11 250097
wst04-VHDL20_DWEG_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250097
wst04-VHDL20_DWEG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:12 250633
wst04-VHDL20_DWEG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:12 249403
wst04-VHDL20_DWEG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:11 250547
wst04-VHDL20_DWEG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:21 250342
wst04-VHDL20_DWEH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 251054
wst04-VHDL20_DWEH_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 246217
wst04-VHDL20_DWEH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 251362
wst04-VHDL20_DWEH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 251353
wst04-VHDL20_DWEH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:17 250927
wst04-VHDL20_DWEH_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250927
wst04-VHDL20_DWEH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:17 251316
wst04-VHDL20_DWEH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:12 250986
wst04-VHDL20_DWEH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 251607
wst04-VHDL20_DWEH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 250682
wst04-VHDL20_DWEI_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:16 358015
wst04-VHDL20_DWEI_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:32:20 353808
wst04-VHDL20_DWEI_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:13 358758
wst04-VHDL20_DWEI_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:15 358136
wst04-VHDL20_DWEI_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:23 357689
wst04-VHDL20_DWEI_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 357689
wst04-VHDL20_DWEI_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:17 354880
wst04-VHDL20_DWEI_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 354102
wst04-VHDL20_DWEI_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:11 354568
wst04-VHDL20_DWEI_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:27 354837
wst04-VHDL20_DWHG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:22 362723
wst04-VHDL20_DWHG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 360336
wst04-VHDL20_DWHG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 359687
wst04-VHDL20_DWHG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 359933
wst04-VHDL20_DWHG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:27 360249
wst04-VHDL20_DWHG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 358907
wst04-VHDL20_DWHG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 359590
wst04-VHDL20_DWHG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:12 359391
wst04-VHDL20_DWHH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:26 342789
wst04-VHDL20_DWHH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 342313
wst04-VHDL20_DWHH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:17 341715
wst04-VHDL20_DWHH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 341468
wst04-VHDL20_DWHH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:27 328678
wst04-VHDL20_DWHH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 328309
wst04-VHDL20_DWHH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 328771
wst04-VHDL20_DWHH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:16 328747
wst04-VHDL20_DWLG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 343454
wst04-VHDL20_DWLG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 343725
wst04-VHDL20_DWLG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 343715
wst04-VHDL20_DWLG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 343606
wst04-VHDL20_DWLG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 346218
wst04-VHDL20_DWLG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 344886
wst04-VHDL20_DWLG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:26 344989
wst04-VHDL20_DWLG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 346016
wst04-VHDL20_DWLH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 346845
wst04-VHDL20_DWLH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:25 345679
wst04-VHDL20_DWLH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 345560
wst04-VHDL20_DWLH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 345973
wst04-VHDL20_DWLH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 346592
wst04-VHDL20_DWLH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:26 344903
wst04-VHDL20_DWLH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 345425
wst04-VHDL20_DWLH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 345835
wst04-VHDL20_DWLI_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 350246
wst04-VHDL20_DWLI_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 348956
wst04-VHDL20_DWLI_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 348976
wst04-VHDL20_DWLI_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 349147
wst04-VHDL20_DWLI_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 345467
wst04-VHDL20_DWLI_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 344131
wst04-VHDL20_DWLI_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 345062
wst04-VHDL20_DWLI_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 345441
wst04-VHDL20_DWMG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:28 567123
wst04-VHDL20_DWMG_130800_COR-2603130800-omedes-..> 13-Mar-2026 09:36:32 567123
wst04-VHDL20_DWMG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 565205
wst04-VHDL20_DWMG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:17 566325
wst04-VHDL20_DWMG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 566048
wst04-VHDL20_DWMG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:21 568166
wst04-VHDL20_DWMG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 567541
wst04-VHDL20_DWMG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 567865
wst04-VHDL20_DWMG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:21 567800
wst04-VHDL20_DWMO_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:22 463482
wst04-VHDL20_DWMO_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 462449
wst04-VHDL20_DWMO_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 463827
wst04-VHDL20_DWMO_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:11 464361
wst04-VHDL20_DWMO_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:12 462597
wst04-VHDL20_DWMO_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 462282
wst04-VHDL20_DWMO_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 462517
wst04-VHDL20_DWMO_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 463634
wst04-VHDL20_DWMP_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:28 565667
wst04-VHDL20_DWMP_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:17 564506
wst04-VHDL20_DWMP_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 564188
wst04-VHDL20_DWMP_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 565258
wst04-VHDL20_DWMP_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:21 561156
wst04-VHDL20_DWMP_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 560495
wst04-VHDL20_DWMP_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 559824
wst04-VHDL20_DWMP_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 560825
wst04-VHDL20_DWPG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:32 398505
wst04-VHDL20_DWPG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:25 353541
wst04-VHDL20_DWPG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 353093
wst04-VHDL20_DWPG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 353564
wst04-VHDL20_DWPG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 404545
wst04-VHDL20_DWPG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:26 358558
wst04-VHDL20_DWPG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:26 358799
wst04-VHDL20_DWPG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:32 358735
wst04-VHDL20_DWPH_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:26 296035
wst04-VHDL20_DWPH_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:21 295384
wst04-VHDL20_DWPH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 250352
wst04-VHDL20_DWPH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 250897
wst04-VHDL20_DWPH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:25 295412
wst04-VHDL20_DWPH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 293995
wst04-VHDL20_DWPH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 249383
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wst04-VHDL20_DWSG_130800-2603130800-omedes--0.pdf 13-Mar-2026 09:45:12 361042
wst04-VHDL20_DWSG_131300-2603131300-omedes--0.pdf 13-Mar-2026 14:45:15 361229
wst04-VHDL20_DWSG_131800-2603131800-omedes--0.pdf 13-Mar-2026 19:45:11 361045
wst04-VHDL20_DWSG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 361932
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