Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_100600 10-Jan-2026 13:22:39 3927
FPDL13_DWMZ_110600 11-Jan-2026 15:06:48 3372
SXDL31_DWAV_100800 10-Jan-2026 09:29:23 10405
SXDL31_DWAV_101800 10-Jan-2026 18:12:49 7477
SXDL31_DWAV_110800 11-Jan-2026 09:07:24 10743
SXDL31_DWAV_111800 11-Jan-2026 17:57:43 9990
SXDL31_DWAV_LATEST 11-Jan-2026 17:57:43 9990
SXDL33_DWAV_100000 10-Jan-2026 10:33:21 6268
SXDL33_DWAV_110000 11-Jan-2026 11:05:29 9006
SXDL33_DWAV_LATEST 11-Jan-2026 11:05:29 9006
ber01-FWDL39_DWMS_101230-2601101230-dsw--0-ia5 10-Jan-2026 12:25:28 1416
ber01-FWDL39_DWMS_111230-2601111230-dsw--0-ia5 11-Jan-2026 12:23:15 1670
ber01-VHDL13_DWEH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:11 4058
ber01-VHDL13_DWEH_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:12 3971
ber01-VHDL13_DWEH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:16 3894
ber01-VHDL13_DWEH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:16 3872
ber01-VHDL13_DWEH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:11 4188
ber01-VHDL13_DWEH_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:11 4148
ber01-VHDL13_DWEH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:17 4064
ber01-VHDL13_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 4021
ber01-VHDL13_DWHG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 4915
ber01-VHDL13_DWHG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4575
ber01-VHDL13_DWHG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4561
ber01-VHDL13_DWHG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:06 3416
ber01-VHDL13_DWHG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:06 4173
ber01-VHDL13_DWHG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4173
ber01-VHDL13_DWHG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3986
ber01-VHDL13_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4635
ber01-VHDL13_DWHH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 4282
ber01-VHDL13_DWHH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4005
ber01-VHDL13_DWHH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4326
ber01-VHDL13_DWHH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:06 3494
ber01-VHDL13_DWHH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:06 3912
ber01-VHDL13_DWHH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 3894
ber01-VHDL13_DWHH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3805
ber01-VHDL13_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4090
ber01-VHDL13_DWLG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 3262
ber01-VHDL13_DWLG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3301
ber01-VHDL13_DWLG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3399
ber01-VHDL13_DWLG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2654
ber01-VHDL13_DWLG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3041
ber01-VHDL13_DWLG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2946
ber01-VHDL13_DWLG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3124
ber01-VHDL13_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2815
ber01-VHDL13_DWLH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2879
ber01-VHDL13_DWLH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3050
ber01-VHDL13_DWLH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 2934
ber01-VHDL13_DWLH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2539
ber01-VHDL13_DWLH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2842
ber01-VHDL13_DWLH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2942
ber01-VHDL13_DWLH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3080
ber01-VHDL13_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2928
ber01-VHDL13_DWLI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2924
ber01-VHDL13_DWLI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3008
ber01-VHDL13_DWLI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3100
ber01-VHDL13_DWLI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2486
ber01-VHDL13_DWLI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2745
ber01-VHDL13_DWLI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2833
ber01-VHDL13_DWLI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 2942
ber01-VHDL13_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2798
ber01-VHDL13_DWMG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3879
ber01-VHDL13_DWMG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3882
ber01-VHDL13_DWMG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4073
ber01-VHDL13_DWMG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 3181
ber01-VHDL13_DWMG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3650
ber01-VHDL13_DWMG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3627
ber01-VHDL13_DWMG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3640
ber01-VHDL13_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3285
ber01-VHDL13_DWMO_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3365
ber01-VHDL13_DWMO_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3357
ber01-VHDL13_DWMO_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 3685
ber01-VHDL13_DWMO_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2982
ber01-VHDL13_DWMO_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3355
ber01-VHDL13_DWMO_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3365
ber01-VHDL13_DWMO_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3563
ber01-VHDL13_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3292
ber01-VHDL13_DWMP_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3947
ber01-VHDL13_DWMP_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3939
ber01-VHDL13_DWMP_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 3891
ber01-VHDL13_DWMP_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 3294
ber01-VHDL13_DWMP_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3924
ber01-VHDL13_DWMP_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3916
ber01-VHDL13_DWMP_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3985
ber01-VHDL13_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3551
ber01-VHDL13_DWOG_100300-2601100300-dsw--0-ia5 10-Jan-2026 04:00:07 7013
ber01-VHDL13_DWOG_100800-2601100800-dsw--0-ia5 10-Jan-2026 10:05:36 6159
ber01-VHDL13_DWOG_101700-2601101700-dsw--0-ia5 10-Jan-2026 19:00:01 5061
ber01-VHDL13_DWOG_110300-2601110300-dsw--0-ia5 11-Jan-2026 04:00:01 5455
ber01-VHDL13_DWOG_110800-2601110800-dsw--0-ia5 11-Jan-2026 10:16:42 5616
ber01-VHDL13_DWOG_110800_COR-2601110800-dsw--0-ia5 11-Jan-2026 15:00:00 5620
ber01-VHDL13_DWOG_111700-2601111700-dsw--0-ia5 11-Jan-2026 19:00:01 5442
ber01-VHDL13_DWOH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:17 3741
ber01-VHDL13_DWOH_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:17 3710
ber01-VHDL13_DWOH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:18 3841
ber01-VHDL13_DWOH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:16 3424
ber01-VHDL13_DWOH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:11 3728
ber01-VHDL13_DWOH_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:16 3689
ber01-VHDL13_DWOH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:17 3528
ber01-VHDL13_DWOH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 3596
ber01-VHDL13_DWOI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:11 3653
ber01-VHDL13_DWOI_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:17 3621
ber01-VHDL13_DWOI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:12 3660
ber01-VHDL13_DWOI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:11 3175
ber01-VHDL13_DWOI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:17 3456
ber01-VHDL13_DWOI_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:16 3412
ber01-VHDL13_DWOI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:11 3304
ber01-VHDL13_DWOI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:11 3118
ber01-VHDL13_DWON_100147-2601100147-dsw--0-ia5 10-Jan-2026 01:47:22 5043
ber01-VHDL13_DWON_100331-2601100331-dsw--0-ia5 10-Jan-2026 03:31:06 5043
ber01-VHDL13_DWON_100342-2601100342-dsw--0-ia5 10-Jan-2026 03:42:31 5043
ber01-VHDL13_DWON_100349-2601100349-dsw--0-ia5 10-Jan-2026 03:49:27 4916
ber01-VHDL13_DWON_100620-2601100620-dsw--0-ia5 10-Jan-2026 06:20:11 4595
ber01-VHDL13_DWON_100622-2601100622-dsw--0-ia5 10-Jan-2026 06:22:31 4595
ber01-VHDL13_DWON_100704-2601100704-dsw--0-ia5 10-Jan-2026 07:04:52 4595
ber01-VHDL13_DWON_100840-2601100840-dsw--0-ia5 10-Jan-2026 08:40:44 4595
ber01-VHDL13_DWON_100929-2601100929-dsw--0-ia5 10-Jan-2026 09:29:08 4595
ber01-VHDL13_DWON_101005-2601101005-dsw--0-ia5 10-Jan-2026 10:05:12 4709
ber01-VHDL13_DWON_101551-2601101551-dsw--0-ia5 10-Jan-2026 15:51:17 3655
ber01-VHDL13_DWON_101818-2601101818-dsw--0-ia5 10-Jan-2026 18:18:21 3664
ber01-VHDL13_DWON_102334-2601102334-dsw--0-ia5 10-Jan-2026 23:34:47 4042
ber01-VHDL13_DWON_110154-2601110154-dsw--0-ia5 11-Jan-2026 01:54:56 4016
ber01-VHDL13_DWON_110357-2601110357-dsw--0-ia5 11-Jan-2026 03:57:31 4016
ber01-VHDL13_DWON_110421-2601110421-dsw--0-ia5 11-Jan-2026 04:21:27 4016
ber01-VHDL13_DWON_110626-2601110626-dsw--0-ia5 11-Jan-2026 06:26:52 4411
ber01-VHDL13_DWON_110709-2601110709-dsw--0-ia5 11-Jan-2026 07:09:07 4405
ber01-VHDL13_DWON_110852-2601110852-dsw--0-ia5 11-Jan-2026 08:52:59 4375
ber01-VHDL13_DWON_111016-2601111016-dsw--0-ia5 11-Jan-2026 10:16:12 4375
ber01-VHDL13_DWON_111021-2601111021-dsw--0-ia5 11-Jan-2026 10:21:11 4375
ber01-VHDL13_DWON_111459-2601111459-dsw--0-ia5 11-Jan-2026 14:59:22 4375
ber01-VHDL13_DWON_111557-2601111557-dsw--0-ia5 11-Jan-2026 15:57:32 3780
ber01-VHDL13_DWON_111852-2601111852-dsw--0-ia5 11-Jan-2026 18:52:26 3768
ber01-VHDL13_DWON_112238-2601112238-dsw--0-ia5 11-Jan-2026 22:38:31 3859
ber01-VHDL13_DWON_112357-2601112357-dsw--0-ia5 11-Jan-2026 23:57:46 3615
ber01-VHDL13_DWPG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2621
ber01-VHDL13_DWPG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 2811
ber01-VHDL13_DWPG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 2725
ber01-VHDL13_DWPG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 1929
ber01-VHDL13_DWPG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2491
ber01-VHDL13_DWPG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2569
ber01-VHDL13_DWPG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 2948
ber01-VHDL13_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2546
ber01-VHDL13_DWPH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2904
ber01-VHDL13_DWPH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3077
ber01-VHDL13_DWPH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3330
ber01-VHDL13_DWPH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2275
ber01-VHDL13_DWPH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2617
ber01-VHDL13_DWPH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2807
ber01-VHDL13_DWPH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3015
ber01-VHDL13_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2466
ber01-VHDL13_DWSG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:03 4824
ber01-VHDL13_DWSG_100200_COR-2601100200-dsw--0-ia5 10-Jan-2026 03:34:48 4659
ber01-VHDL13_DWSG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4399
ber01-VHDL13_DWSG_100400_COR-2601100400-dsw--0-ia5 10-Jan-2026 07:24:00 4408
ber01-VHDL13_DWSG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 4481
ber01-VHDL13_DWSG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:03 3422
ber01-VHDL13_DWSG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3954
ber01-VHDL13_DWSG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 3963
ber01-VHDL13_DWSG_110400_COR-2601110400-dsw--0-ia5 11-Jan-2026 06:32:22 4274
ber01-VHDL13_DWSG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 4256
ber01-VHDL13_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 4093
ber01-VHDL17_DWOG_101200-2601101200-dsw--0-ia5 10-Jan-2026 12:33:01 2641
ber01-VHDL17_DWOG_111200-2601111200-dsw--0-ia5 11-Jan-2026 12:36:29 3302
swis2-VHDL20_DWEG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4299
swis2-VHDL20_DWEG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4099
swis2-VHDL20_DWEG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4674
swis2-VHDL20_DWEG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 3819
swis2-VHDL20_DWEG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4073
swis2-VHDL20_DWEG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:07 4298
swis2-VHDL20_DWEG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4363
swis2-VHDL20_DWEG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4211
swis2-VHDL20_DWEH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4594
swis2-VHDL20_DWEH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4372
swis2-VHDL20_DWEH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4736
swis2-VHDL20_DWEH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 4295
swis2-VHDL20_DWEH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4578
swis2-VHDL20_DWEH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:07 4753
swis2-VHDL20_DWEH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4903
swis2-VHDL20_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4647
swis2-VHDL20_DWEI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4246
swis2-VHDL20_DWEI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4041
swis2-VHDL20_DWEI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4523
swis2-VHDL20_DWEI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 3595
swis2-VHDL20_DWEI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 3817
swis2-VHDL20_DWEI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:06 4035
swis2-VHDL20_DWEI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4101
swis2-VHDL20_DWEI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3741
swis2-VHDL20_DWHG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 5101
swis2-VHDL20_DWHG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:11 4758
swis2-VHDL20_DWHG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 5365
swis2-VHDL20_DWHG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3599
swis2-VHDL20_DWHG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4359
swis2-VHDL20_DWHG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4356
swis2-VHDL20_DWHG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4705
swis2-VHDL20_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4818
swis2-VHDL20_DWHH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 4468
swis2-VHDL20_DWHH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:11 4191
swis2-VHDL20_DWHH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 5058
swis2-VHDL20_DWHH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3680
swis2-VHDL20_DWHH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4098
swis2-VHDL20_DWHH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4080
swis2-VHDL20_DWHH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4524
swis2-VHDL20_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4276
swis2-VHDL20_DWLG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3677
swis2-VHDL20_DWLG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3705
swis2-VHDL20_DWLG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3955
swis2-VHDL20_DWLG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3052
swis2-VHDL20_DWLG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3444
swis2-VHDL20_DWLG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3367
swis2-VHDL20_DWLG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3723
swis2-VHDL20_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3230
swis2-VHDL20_DWLH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3297
swis2-VHDL20_DWLH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3462
swis2-VHDL20_DWLH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3502
swis2-VHDL20_DWLH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2918
swis2-VHDL20_DWLH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3221
swis2-VHDL20_DWLH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3354
swis2-VHDL20_DWLH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3667
swis2-VHDL20_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3334
swis2-VHDL20_DWLI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3337
swis2-VHDL20_DWLI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3416
swis2-VHDL20_DWLI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3659
swis2-VHDL20_DWLI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2860
swis2-VHDL20_DWLI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3119
swis2-VHDL20_DWLI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3240
swis2-VHDL20_DWLI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3515
swis2-VHDL20_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3199
swis2-VHDL20_DWMG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4374
swis2-VHDL20_DWMG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4295
swis2-VHDL20_DWMG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4800
swis2-VHDL20_DWMG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3594
swis2-VHDL20_DWMG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 4132
swis2-VHDL20_DWMG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4212
swis2-VHDL20_DWMG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4517
swis2-VHDL20_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3870
swis2-VHDL20_DWMO_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 3814
swis2-VHDL20_DWMO_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 3775
swis2-VHDL20_DWMO_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4466
swis2-VHDL20_DWMO_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3441
swis2-VHDL20_DWMO_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3782
swis2-VHDL20_DWMO_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 3961
swis2-VHDL20_DWMO_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4455
swis2-VHDL20_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3888
swis2-VHDL20_DWMP_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4442
swis2-VHDL20_DWMP_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4352
swis2-VHDL20_DWMP_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4632
swis2-VHDL20_DWMP_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3671
swis2-VHDL20_DWMP_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 4410
swis2-VHDL20_DWMP_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4498
swis2-VHDL20_DWMP_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4865
swis2-VHDL20_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4114
swis2-VHDL20_DWPG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 2992
swis2-VHDL20_DWPG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3173
swis2-VHDL20_DWPG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3229
swis2-VHDL20_DWPG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2433
swis2-VHDL20_DWPG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 2856
swis2-VHDL20_DWPG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 2904
swis2-VHDL20_DWPG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3498
swis2-VHDL20_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3096
swis2-VHDL20_DWPH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3269
swis2-VHDL20_DWPH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3441
swis2-VHDL20_DWPH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3834
swis2-VHDL20_DWPH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2779
swis2-VHDL20_DWPH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 2981
swis2-VHDL20_DWPH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3144
swis2-VHDL20_DWPH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3564
swis2-VHDL20_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3015
swis2-VHDL20_DWSG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 5161
swis2-VHDL20_DWSG_100200_COR-2601100200-dsw--0-ia5 10-Jan-2026 03:34:48 4893
swis2-VHDL20_DWSG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4809
swis2-VHDL20_DWSG_100400_COR-2601100400-dsw--0-ia5 10-Jan-2026 07:24:00 4818
swis2-VHDL20_DWSG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:06 5141
swis2-VHDL20_DWSG_101300-2601101300-dsw--0-ia5 10-Jan-2026 14:45:06 4879
swis2-VHDL20_DWSG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3857
swis2-VHDL20_DWSG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4406
swis2-VHDL20_DWSG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4494
swis2-VHDL20_DWSG_110400_COR-2601110400-dsw--0-ia5 11-Jan-2026 06:32:22 4805
swis2-VHDL20_DWSG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4988
swis2-VHDL20_DWSG_111300-2601111300-dsw--0-ia5 11-Jan-2026 14:45:08 4799
swis2-VHDL20_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:03 4619
wst04-VHDL20_DWEG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 234886
wst04-VHDL20_DWEG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 234415
wst04-VHDL20_DWEG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 234049
wst04-VHDL20_DWEG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 232805
wst04-VHDL20_DWEG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 233369
wst04-VHDL20_DWEG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:27 233147
wst04-VHDL20_DWEG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 231495
wst04-VHDL20_DWEG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 230426
wst04-VHDL20_DWEH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 230857
wst04-VHDL20_DWEH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 230353
wst04-VHDL20_DWEH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 228779
wst04-VHDL20_DWEH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 228447
wst04-VHDL20_DWEH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 228847
wst04-VHDL20_DWEH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 228623
wst04-VHDL20_DWEH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 234078
wst04-VHDL20_DWEH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 233710
wst04-VHDL20_DWEI_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 324144
wst04-VHDL20_DWEI_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:27 323949
wst04-VHDL20_DWEI_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 322239
wst04-VHDL20_DWEI_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 322287
wst04-VHDL20_DWEI_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 322255
wst04-VHDL20_DWEI_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:27 322491
wst04-VHDL20_DWEI_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:22 319515
wst04-VHDL20_DWEI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 318758
wst04-VHDL20_DWHG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 313346
wst04-VHDL20_DWHG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:11 313049
wst04-VHDL20_DWHG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:18 313535
wst04-VHDL20_DWHG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 309701
wst04-VHDL20_DWHG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 310535
wst04-VHDL20_DWHG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:11 310432
wst04-VHDL20_DWHG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:22 309864
wst04-VHDL20_DWHG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 309251
wst04-VHDL20_DWHH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 300348
wst04-VHDL20_DWHH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:11 299518
wst04-VHDL20_DWHH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:18 302188
wst04-VHDL20_DWHH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 299180
wst04-VHDL20_DWHH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 299903
wst04-VHDL20_DWHH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:16 299891
wst04-VHDL20_DWHH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:16 302176
wst04-VHDL20_DWHH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 301685
wst04-VHDL20_DWLG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 319200
wst04-VHDL20_DWLG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 319196
wst04-VHDL20_DWLG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 313984
wst04-VHDL20_DWLG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 312505
wst04-VHDL20_DWLG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 313798
wst04-VHDL20_DWLG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 313096
wst04-VHDL20_DWLG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 306851
wst04-VHDL20_DWLG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 304475
wst04-VHDL20_DWLH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 311090
wst04-VHDL20_DWLH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 311212
wst04-VHDL20_DWLH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 307534
wst04-VHDL20_DWLH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 306720
wst04-VHDL20_DWLH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 307399
wst04-VHDL20_DWLH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 307333
wst04-VHDL20_DWLH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 305479
wst04-VHDL20_DWLH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 303368
wst04-VHDL20_DWLI_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 313589
wst04-VHDL20_DWLI_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 313680
wst04-VHDL20_DWLI_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 312949
wst04-VHDL20_DWLI_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:27 312141
wst04-VHDL20_DWLI_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:26 312852
wst04-VHDL20_DWLI_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 312755
wst04-VHDL20_DWLI_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 309359
wst04-VHDL20_DWLI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 307672
wst04-VHDL20_DWMG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 533949
wst04-VHDL20_DWMG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:16 533907
wst04-VHDL20_DWMG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:16 526739
wst04-VHDL20_DWMG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 525401
wst04-VHDL20_DWMG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 525892
wst04-VHDL20_DWMG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 525787
wst04-VHDL20_DWMG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 518963
wst04-VHDL20_DWMG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 516689
wst04-VHDL20_DWMO_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 428776
wst04-VHDL20_DWMO_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:16 429363
wst04-VHDL20_DWMO_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:12 424233
wst04-VHDL20_DWMO_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 423169
wst04-VHDL20_DWMO_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 422964
wst04-VHDL20_DWMO_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:17 423582
wst04-VHDL20_DWMO_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 419572
wst04-VHDL20_DWMO_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 418583
wst04-VHDL20_DWMP_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:22 549202
wst04-VHDL20_DWMP_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 550958
wst04-VHDL20_DWMP_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:16 542391
wst04-VHDL20_DWMP_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 541322
wst04-VHDL20_DWMP_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 540687
wst04-VHDL20_DWMP_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 542545
wst04-VHDL20_DWMP_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:16 545590
wst04-VHDL20_DWMP_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 543939
wst04-VHDL20_DWPG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:22 310976
wst04-VHDL20_DWPG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:32 310897
wst04-VHDL20_DWPG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:26 351951
wst04-VHDL20_DWPG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 306891
wst04-VHDL20_DWPG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:26 307412
wst04-VHDL20_DWPG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:33 306917
wst04-VHDL20_DWPG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 352543
wst04-VHDL20_DWPG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 306905
wst04-VHDL20_DWPH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:22 223035
wst04-VHDL20_DWPH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:32 222343
wst04-VHDL20_DWPH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:26 269037
wst04-VHDL20_DWPH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 267787
wst04-VHDL20_DWPH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 223526
wst04-VHDL20_DWPH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:33 224243
wst04-VHDL20_DWPH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 270398
wst04-VHDL20_DWPH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 267645
wst04-VHDL20_DWSG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 339878
wst04-VHDL20_DWSG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:16 339947
wst04-VHDL20_DWSG_100400_COR-2601100400-omedes-..> 10-Jan-2026 07:24:12 339904
wst04-VHDL20_DWSG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:12 340187
wst04-VHDL20_DWSG_101300-2601101300-omedes--0.pdf 10-Jan-2026 14:45:22 339571
wst04-VHDL20_DWSG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 338801
wst04-VHDL20_DWSG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 339840
wst04-VHDL20_DWSG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:17 339967
wst04-VHDL20_DWSG_110400_COR-2601110400-omedes-..> 11-Jan-2026 06:32:25 341560
wst04-VHDL20_DWSG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 338675
wst04-VHDL20_DWSG_111300-2601111300-omedes--0.pdf 11-Jan-2026 14:45:11 338677
wst04-VHDL20_DWSG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 337722