Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_070600                                 07-Aug-2025 12:43:53                3771
FPDL13_DWMZ_080600                                 08-Aug-2025 12:41:39                5202
SXDL31_DWAV_061800                                 06-Aug-2025 16:15:45                6564
SXDL31_DWAV_070800                                 07-Aug-2025 06:40:38               13153
SXDL31_DWAV_071800                                 07-Aug-2025 16:35:53                4385
SXDL31_DWAV_080800                                 08-Aug-2025 06:38:48               12968
SXDL31_DWAV_LATEST                                 08-Aug-2025 06:38:48               12968
SXDL33_DWAV_070000                                 07-Aug-2025 10:23:44               10999
SXDL33_DWAV_080000                                 08-Aug-2025 09:05:16                5926
SXDL33_DWAV_LATEST                                 08-Aug-2025 09:05:16                5926
ber01-FWDL39_DWMS_071230-2508071230-dsw--0-ia5     07-Aug-2025 11:16:57                 806
ber01-FWDL39_DWMS_081230-2508081230-dsw--0-ia5     08-Aug-2025 11:11:17                 824
ber01-VHDL13_DWEH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:28:11                1914
ber01-VHDL13_DWEH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:28:12                2087
ber01-VHDL13_DWEH_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:58:06                2383
ber01-VHDL13_DWEH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:28:12                2358
ber01-VHDL13_DWEH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:28:11                2091
ber01-VHDL13_DWEH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:28:11                2261
ber01-VHDL13_DWEH_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:58:06                2085
ber01-VHDL13_DWEH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:28:12                2027
ber01-VHDL13_DWHG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:09                2212
ber01-VHDL13_DWHG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                2218
ber01-VHDL13_DWHG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:11                2188
ber01-VHDL13_DWHG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:07                2178
ber01-VHDL13_DWHG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:06                2028
ber01-VHDL13_DWHG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                2275
ber01-VHDL13_DWHG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                2275
ber01-VHDL13_DWHG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:08                2375
ber01-VHDL13_DWHH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:10                2407
ber01-VHDL13_DWHH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                2402
ber01-VHDL13_DWHH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:11                2370
ber01-VHDL13_DWHH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:07                2502
ber01-VHDL13_DWHH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:06                2288
ber01-VHDL13_DWHH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                2691
ber01-VHDL13_DWHH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                2691
ber01-VHDL13_DWHH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:08                2564
ber01-VHDL13_DWLG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1633
ber01-VHDL13_DWLG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1825
ber01-VHDL13_DWLG_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:59:57                1900
ber01-VHDL13_DWLG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1904
ber01-VHDL13_DWLG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1509
ber01-VHDL13_DWLG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1579
ber01-VHDL13_DWLG_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:59:56                1510
ber01-VHDL13_DWLG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1507
ber01-VHDL13_DWLH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1664
ber01-VHDL13_DWLH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1835
ber01-VHDL13_DWLH_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:59:57                1823
ber01-VHDL13_DWLH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1848
ber01-VHDL13_DWLH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1575
ber01-VHDL13_DWLH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1625
ber01-VHDL13_DWLH_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:59:56                1533
ber01-VHDL13_DWLH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1533
ber01-VHDL13_DWLI_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1622
ber01-VHDL13_DWLI_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1857
ber01-VHDL13_DWLI_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:59:57                1889
ber01-VHDL13_DWLI_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1889
ber01-VHDL13_DWLI_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1482
ber01-VHDL13_DWLI_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1572
ber01-VHDL13_DWLI_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:59:56                1506
ber01-VHDL13_DWLI_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1503
ber01-VHDL13_DWMG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1869
ber01-VHDL13_DWMG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1780
ber01-VHDL13_DWMG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                1791
ber01-VHDL13_DWMG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1779
ber01-VHDL13_DWMG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1653
ber01-VHDL13_DWMG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1633
ber01-VHDL13_DWMG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                1633
ber01-VHDL13_DWMG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1558
ber01-VHDL13_DWMG_080800_COR-2508080800-dsw--0-ia5 08-Aug-2025 11:47:11                1620
ber01-VHDL13_DWMO_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1897
ber01-VHDL13_DWMO_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1850
ber01-VHDL13_DWMO_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                1849
ber01-VHDL13_DWMO_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1849
ber01-VHDL13_DWMO_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1720
ber01-VHDL13_DWMO_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1698
ber01-VHDL13_DWMO_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                1698
ber01-VHDL13_DWMO_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1684
ber01-VHDL13_DWMP_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1945
ber01-VHDL13_DWMP_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:07                1910
ber01-VHDL13_DWMP_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                1909
ber01-VHDL13_DWMP_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1909
ber01-VHDL13_DWMP_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1699
ber01-VHDL13_DWMP_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:06                1808
ber01-VHDL13_DWMP_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                1808
ber01-VHDL13_DWMP_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1675
ber01-VHDL13_DWOG_061700-2508061700-dsw--0-ia5     06-Aug-2025 18:00:06                3061
ber01-VHDL13_DWOG_070300-2508070300-dsw--0-ia5     07-Aug-2025 03:00:04                2877
ber01-VHDL13_DWOG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                2996
ber01-VHDL13_DWOG_071700-2508071700-dsw--0-ia5     07-Aug-2025 18:00:02                2739
ber01-VHDL13_DWOG_071700_COR-2508071700-dsw--0-ia5 07-Aug-2025 14:48:58                2929
ber01-VHDL13_DWOG_080300-2508080300-dsw--0-ia5     08-Aug-2025 03:00:12                2852
ber01-VHDL13_DWOG_080800-2508080800-dsw--0-ia5     08-Aug-2025 11:19:56                3036
ber01-VHDL13_DWOH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:28:11                1917
ber01-VHDL13_DWOH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:28:06                1999
ber01-VHDL13_DWOH_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:58:12                2193
ber01-VHDL13_DWOH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:28:07                2207
ber01-VHDL13_DWOH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:28:11                2015
ber01-VHDL13_DWOH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:28:07                2138
ber01-VHDL13_DWOH_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:58:12                1960
ber01-VHDL13_DWOH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:28:12                1950
ber01-VHDL13_DWOI_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:28:07                1832
ber01-VHDL13_DWOI_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:28:12                1988
ber01-VHDL13_DWOI_070400-2508070400-dsw--0-ia5     07-Aug-2025 04:58:12                2170
ber01-VHDL13_DWOI_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:28:07                2215
ber01-VHDL13_DWOI_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:28:07                2052
ber01-VHDL13_DWOI_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:28:11                2105
ber01-VHDL13_DWOI_080400-2508080400-dsw--0-ia5     08-Aug-2025 04:58:12                2104
ber01-VHDL13_DWOI_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:28:06                2122
ber01-VHDL13_DWON_061639-2508061639-dsw--0-ia5     06-Aug-2025 16:39:11                3356
ber01-VHDL13_DWON_061904-2508061904-dsw--0-ia5     06-Aug-2025 19:04:46                3387
ber01-VHDL13_DWON_061933-2508061933-dsw--0-ia5     06-Aug-2025 19:33:17                2941
ber01-VHDL13_DWON_070011-2508070011-dsw--0-ia5     07-Aug-2025 00:11:37                2978
ber01-VHDL13_DWON_070012_COR-2508070012-dsw--0-ia5 07-Aug-2025 00:13:11                2982
ber01-VHDL13_DWON_070127-2508070127-dsw--0-ia5     07-Aug-2025 01:27:51                2978
ber01-VHDL13_DWON_070246-2508070246-dsw--0-ia5     07-Aug-2025 02:46:50                2978
ber01-VHDL13_DWON_070530-2508070530-dsw--0-ia5     07-Aug-2025 05:30:20                3190
ber01-VHDL13_DWON_070621-2508070621-dsw--0-ia5     07-Aug-2025 06:21:51                3262
ber01-VHDL13_DWON_071448-2508071448-dsw--0-ia5     07-Aug-2025 14:48:58                3356
ber01-VHDL13_DWON_071708-2508071708-dsw--0-ia5     07-Aug-2025 17:08:11                2993
ber01-VHDL13_DWON_080108-2508080108-dsw--0-ia5     08-Aug-2025 01:08:57                2975
ber01-VHDL13_DWON_080230-2508080230-dsw--0-ia5     08-Aug-2025 02:30:48                2975
ber01-VHDL13_DWON_080530-2508080530-dsw--0-ia5     08-Aug-2025 05:30:33                3114
ber01-VHDL13_DWON_080604-2508080604-dsw--0-ia5     08-Aug-2025 06:04:42                3219
ber01-VHDL13_DWON_080638-2508080638-dsw--0-ia5     08-Aug-2025 06:39:02                3229
ber01-VHDL13_DWON_081107-2508081107-dsw--0-ia5     08-Aug-2025 11:07:46                3150
ber01-VHDL13_DWON_081416-2508081416-dsw--0-ia5     08-Aug-2025 14:16:17                3266
ber01-VHDL13_DWPG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1625
ber01-VHDL13_DWPG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:01                1731
ber01-VHDL13_DWPG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:01                1722
ber01-VHDL13_DWPG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1727
ber01-VHDL13_DWPG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1470
ber01-VHDL13_DWPG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:02                1533
ber01-VHDL13_DWPG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                1520
ber01-VHDL13_DWPG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1519
ber01-VHDL13_DWPH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:01                1780
ber01-VHDL13_DWPH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:01                1848
ber01-VHDL13_DWPH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:01                1806
ber01-VHDL13_DWPH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1811
ber01-VHDL13_DWPH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:02                1695
ber01-VHDL13_DWPH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:02                1765
ber01-VHDL13_DWPH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                1739
ber01-VHDL13_DWPH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1739
ber01-VHDL13_DWSG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:30:09                1375
ber01-VHDL13_DWSG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:30:01                1584
ber01-VHDL13_DWSG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                1594
ber01-VHDL13_DWSG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:30:03                1594
ber01-VHDL13_DWSG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:30:06                1513
ber01-VHDL13_DWSG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:30:02                1649
ber01-VHDL13_DWSG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                1643
ber01-VHDL13_DWSG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:30:02                1644
ber01-VHDL13_DWSG_080800_COR-2508080800-dsw--0-ia5 08-Aug-2025 12:11:56                1684
ber01-VHDL17_DWOG_071200-2508071200-dsw--0-ia5     07-Aug-2025 11:10:21                2779
ber01-VHDL17_DWOG_081200-2508081200-dsw--0-ia5     08-Aug-2025 11:15:11                2644
swis2-VHDL20_DWEG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:06                2102
swis2-VHDL20_DWEG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2131
swis2-VHDL20_DWEG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:15:07                2401
swis2-VHDL20_DWEG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2386
swis2-VHDL20_DWEG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:07                2200
swis2-VHDL20_DWEG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                2270
swis2-VHDL20_DWEG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:15:02                2168
swis2-VHDL20_DWEG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                2129
swis2-VHDL20_DWEH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:12                2117
swis2-VHDL20_DWEH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2251
swis2-VHDL20_DWEH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:15:11                2561
swis2-VHDL20_DWEH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2536
swis2-VHDL20_DWEH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:11                2291
swis2-VHDL20_DWEH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:14                2425
swis2-VHDL20_DWEH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:15:12                2263
swis2-VHDL20_DWEH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:12                2205
swis2-VHDL20_DWEI_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:06                2017
swis2-VHDL20_DWEI_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2121
swis2-VHDL20_DWEI_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:15:11                2355
swis2-VHDL20_DWEI_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2394
swis2-VHDL20_DWEI_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:07                2237
swis2-VHDL20_DWEI_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                2238
swis2-VHDL20_DWEI_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:15:12                2289
swis2-VHDL20_DWEI_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                2301
swis2-VHDL20_DWHG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                2395
swis2-VHDL20_DWHG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2404
swis2-VHDL20_DWHG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:11                2371
swis2-VHDL20_DWHG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2361
swis2-VHDL20_DWHG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:07                2211
swis2-VHDL20_DWHG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                2461
swis2-VHDL20_DWHG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                2458
swis2-VHDL20_DWHG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                2558
swis2-VHDL20_DWHH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                2593
swis2-VHDL20_DWHH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2588
swis2-VHDL20_DWHH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:11                2556
swis2-VHDL20_DWHH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2688
swis2-VHDL20_DWHH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:07                2474
swis2-VHDL20_DWHH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                2877
swis2-VHDL20_DWHH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                2877
swis2-VHDL20_DWHH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                2750
swis2-VHDL20_DWLG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                1854
swis2-VHDL20_DWLG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2046
swis2-VHDL20_DWLG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:27                2121
swis2-VHDL20_DWLG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2128
swis2-VHDL20_DWLG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1730
swis2-VHDL20_DWLG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1800
swis2-VHDL20_DWLG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:27                1731
swis2-VHDL20_DWLG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1731
swis2-VHDL20_DWLH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                1885
swis2-VHDL20_DWLH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2056
swis2-VHDL20_DWLH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:27                2044
swis2-VHDL20_DWLH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2069
swis2-VHDL20_DWLH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1796
swis2-VHDL20_DWLH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1846
swis2-VHDL20_DWLH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:27                1754
swis2-VHDL20_DWLH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1754
swis2-VHDL20_DWLI_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                1843
swis2-VHDL20_DWLI_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2078
swis2-VHDL20_DWLI_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:27                2107
swis2-VHDL20_DWLI_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2110
swis2-VHDL20_DWLI_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1703
swis2-VHDL20_DWLI_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1793
swis2-VHDL20_DWLI_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:27                1724
swis2-VHDL20_DWLI_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1724
swis2-VHDL20_DWMG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                2080
swis2-VHDL20_DWMG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                1994
swis2-VHDL20_DWMG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                2002
swis2-VHDL20_DWMG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                1990
swis2-VHDL20_DWMG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1864
swis2-VHDL20_DWMG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1908
swis2-VHDL20_DWMG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                1843
swis2-VHDL20_DWMG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:12                1769
swis2-VHDL20_DWMO_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                2109
swis2-VHDL20_DWMO_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2065
swis2-VHDL20_DWMO_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                2064
swis2-VHDL20_DWMO_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2061
swis2-VHDL20_DWMO_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1932
swis2-VHDL20_DWMO_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1913
swis2-VHDL20_DWMO_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                1913
swis2-VHDL20_DWMO_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:12                1896
swis2-VHDL20_DWMP_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                2151
swis2-VHDL20_DWMP_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2122
swis2-VHDL20_DWMP_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:07                2121
swis2-VHDL20_DWMP_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2121
swis2-VHDL20_DWMP_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1905
swis2-VHDL20_DWMP_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                2020
swis2-VHDL20_DWMP_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                2020
swis2-VHDL20_DWMP_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:12                1887
swis2-VHDL20_DWPG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                1822
swis2-VHDL20_DWPG_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                1928
swis2-VHDL20_DWPG_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:01                1917
swis2-VHDL20_DWPG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                1924
swis2-VHDL20_DWPG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1667
swis2-VHDL20_DWPG_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1730
swis2-VHDL20_DWPG_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:07                1715
swis2-VHDL20_DWPG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1716
swis2-VHDL20_DWPH_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:02                1977
swis2-VHDL20_DWPH_070200-2508070200-dsw--0-ia5     07-Aug-2025 02:45:07                2045
swis2-VHDL20_DWPH_070400-2508070400-dsw--0-ia5     07-Aug-2025 05:00:01                2003
swis2-VHDL20_DWPH_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                2008
swis2-VHDL20_DWPH_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1892
swis2-VHDL20_DWPH_080200-2508080200-dsw--0-ia5     08-Aug-2025 02:45:11                1962
swis2-VHDL20_DWPH_080400-2508080400-dsw--0-ia5     08-Aug-2025 05:00:08                1936
swis2-VHDL20_DWPH_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1936
swis2-VHDL20_DWSG_061800-2508061800-dsw--0-ia5     06-Aug-2025 18:45:06                1607
swis2-VHDL20_DWSG_070800-2508070800-dsw--0-ia5     07-Aug-2025 08:45:11                1825
swis2-VHDL20_DWSG_071300-2508071300-dsw--0-ia5     07-Aug-2025 13:45:02                1804
swis2-VHDL20_DWSG_071800-2508071800-dsw--0-ia5     07-Aug-2025 18:45:01                1745
swis2-VHDL20_DWSG_080800-2508080800-dsw--0-ia5     08-Aug-2025 08:45:02                1874
swis2-VHDL20_DWSG_081300-2508081300-dsw--0-ia5     08-Aug-2025 13:45:04                1910
wst04-VHDL20_DWEG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:16              259687
wst04-VHDL20_DWEG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              259593
wst04-VHDL20_DWEG_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:15:11              260063
wst04-VHDL20_DWEG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:24              259868
wst04-VHDL20_DWEG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:17              263578
wst04-VHDL20_DWEG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:17              264328
wst04-VHDL20_DWEG_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:15:06              264144
wst04-VHDL20_DWEG_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:12              263959
wst04-VHDL20_DWEH_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:16              261360
wst04-VHDL20_DWEH_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              261501
wst04-VHDL20_DWEH_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:15:11              261949
wst04-VHDL20_DWEH_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:16              261414
wst04-VHDL20_DWEH_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:17              266843
wst04-VHDL20_DWEH_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:17              267586
wst04-VHDL20_DWEH_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:15:12              267283
wst04-VHDL20_DWEH_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:12              267258
wst04-VHDL20_DWEI_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:22              364858
wst04-VHDL20_DWEI_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              365356
wst04-VHDL20_DWEI_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:15:07              365250
wst04-VHDL20_DWEI_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:24              364760
wst04-VHDL20_DWEI_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:17              366755
wst04-VHDL20_DWEI_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:17              368878
wst04-VHDL20_DWEI_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:15:12              367310
wst04-VHDL20_DWEI_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:18              367318
wst04-VHDL20_DWHG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:12              366152
wst04-VHDL20_DWHG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              365574
wst04-VHDL20_DWHG_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:07              365604
wst04-VHDL20_DWHG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:12              366968
wst04-VHDL20_DWHG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:21              368268
wst04-VHDL20_DWHG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              369260
wst04-VHDL20_DWHG_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:08              369274
wst04-VHDL20_DWHG_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:12              369605
wst04-VHDL20_DWHH_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:18              356910
wst04-VHDL20_DWHH_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              357177
wst04-VHDL20_DWHH_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:07              357184
wst04-VHDL20_DWHH_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:11              357267
wst04-VHDL20_DWHH_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:17              352102
wst04-VHDL20_DWHH_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              353063
wst04-VHDL20_DWHH_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:08              353058
wst04-VHDL20_DWHH_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:12              352621
wst04-VHDL20_DWLG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:40:27              356643
wst04-VHDL20_DWLG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:40:29              356765
wst04-VHDL20_DWLG_070400-2508070400-omedes--0.pdf  07-Aug-2025 04:59:37              356697
wst04-VHDL20_DWLG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:40:26              356384
wst04-VHDL20_DWLG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:40:26              356239
wst04-VHDL20_DWLG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:40:27              356338
wst04-VHDL20_DWLG_080400-2508080400-omedes--0.pdf  08-Aug-2025 04:59:36              356116
wst04-VHDL20_DWLG_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:40:27              356128
wst04-VHDL20_DWLH_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:40:17              365585
wst04-VHDL20_DWLH_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:40:29              365746
wst04-VHDL20_DWLH_070400-2508070400-omedes--0.pdf  07-Aug-2025 04:59:37              365602
wst04-VHDL20_DWLH_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:40:16              365581
wst04-VHDL20_DWLH_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:40:16              363463
wst04-VHDL20_DWLH_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:40:17              364012
wst04-VHDL20_DWLH_080400-2508080400-omedes--0.pdf  08-Aug-2025 04:59:36              363703
wst04-VHDL20_DWLH_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:40:16              363714
wst04-VHDL20_DWLI_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:40:37              357569
wst04-VHDL20_DWLI_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:40:53              358091
wst04-VHDL20_DWLI_070400-2508070400-omedes--0.pdf  07-Aug-2025 04:59:37              358004
wst04-VHDL20_DWLI_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:40:36              358025
wst04-VHDL20_DWLI_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:40:37              363048
wst04-VHDL20_DWLI_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:40:37              363179
wst04-VHDL20_DWLI_080400-2508080400-omedes--0.pdf  08-Aug-2025 04:59:36              362902
wst04-VHDL20_DWLI_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:40:35              362914
wst04-VHDL20_DWMG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:12              575230
wst04-VHDL20_DWMG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              575832
wst04-VHDL20_DWMG_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:11              575231
wst04-VHDL20_DWMG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:16              575192
wst04-VHDL20_DWMG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:11              575006
wst04-VHDL20_DWMG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:17              576355
wst04-VHDL20_DWMG_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:12              575520
wst04-VHDL20_DWMG_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:24              575431
wst04-VHDL20_DWMO_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:06              468874
wst04-VHDL20_DWMO_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              468427
wst04-VHDL20_DWMO_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:11              468850
wst04-VHDL20_DWMO_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:11              468411
wst04-VHDL20_DWMO_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:11              467193
wst04-VHDL20_DWMO_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              467684
wst04-VHDL20_DWMO_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:12              468112
wst04-VHDL20_DWMO_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:18              467661
wst04-VHDL20_DWMP_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:12              589179
wst04-VHDL20_DWMP_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              588941
wst04-VHDL20_DWMP_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:11              589166
wst04-VHDL20_DWMP_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:16              589166
wst04-VHDL20_DWMP_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:11              582329
wst04-VHDL20_DWMP_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:17              582593
wst04-VHDL20_DWMP_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:12              582825
wst04-VHDL20_DWMP_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:18              582734
wst04-VHDL20_DWPG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:06              373056
wst04-VHDL20_DWPG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:07              374375
wst04-VHDL20_DWPG_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:07              374028
wst04-VHDL20_DWPG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:11              418634
wst04-VHDL20_DWPG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:07              361846
wst04-VHDL20_DWPG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              362293
wst04-VHDL20_DWPG_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:08              361996
wst04-VHDL20_DWPG_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:18              406582
wst04-VHDL20_DWPH_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:06              307262
wst04-VHDL20_DWPH_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:07              263429
wst04-VHDL20_DWPH_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:00:07              263582
wst04-VHDL20_DWPH_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:11              308195
wst04-VHDL20_DWPH_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:07              311825
wst04-VHDL20_DWPH_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              267554
wst04-VHDL20_DWPH_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:00:07              267270
wst04-VHDL20_DWPH_080800-2508080800-omedes--0.pdf  08-Aug-2025 08:45:12              311853
wst04-VHDL20_DWSG_061800-2508061800-omedes--0.pdf  06-Aug-2025 18:45:12              369765
wst04-VHDL20_DWSG_070200-2508070200-omedes--0.pdf  07-Aug-2025 02:45:22              371417
wst04-VHDL20_DWSG_070400-2508070400-omedes--0.pdf  07-Aug-2025 05:15:07              371550
wst04-VHDL20_DWSG_070800-2508070800-omedes--0.pdf  07-Aug-2025 08:45:11              371564
wst04-VHDL20_DWSG_071300-2508071300-omedes--0.pdf  07-Aug-2025 13:45:06              368340
wst04-VHDL20_DWSG_071800-2508071800-omedes--0.pdf  07-Aug-2025 18:45:07              368703
wst04-VHDL20_DWSG_080200-2508080200-omedes--0.pdf  08-Aug-2025 02:45:11              368481
wst04-VHDL20_DWSG_080400-2508080400-omedes--0.pdf  08-Aug-2025 05:15:06              368533
wst04-VHDL20_DWSG_080800-2508080800-omedes--0.pdf  08-Aug-2025 12:11:56              379584
wst04-VHDL20_DWSG_081300-2508081300-omedes--0.pdf  08-Aug-2025 13:45:06              379562