Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Feb-2026 12:01:19 7447
FPDL13_DWMZ_230600 23-Feb-2026 15:35:52 4915
SXDL31_DWAV_220800 22-Feb-2026 08:26:15 10907
SXDL31_DWAV_221800 22-Feb-2026 17:44:44 8445
SXDL31_DWAV_230800 23-Feb-2026 08:17:48 7812
SXDL31_DWAV_231800 23-Feb-2026 17:51:39 7166
SXDL31_DWAV_LATEST 23-Feb-2026 17:51:39 7166
SXDL33_DWAV_220000 22-Feb-2026 11:20:20 9521
SXDL33_DWAV_230000 23-Feb-2026 10:05:40 9480
SXDL33_DWAV_LATEST 23-Feb-2026 10:05:40 9480
ber01-FWDL39_DWMS_221230-2602221230-dsw--0-ia5 22-Feb-2026 12:30:56 1717
ber01-FWDL39_DWMS_221230_COR-2602221230-dsw--0-ia5 22-Feb-2026 13:17:07 1721
ber01-FWDL39_DWMS_231230-2602231230-dsw--0-ia5 23-Feb-2026 13:28:26 2092
ber01-VHDL13_DWEH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:10 2715
ber01-VHDL13_DWEH_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2699
ber01-VHDL13_DWEH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:16 3091
ber01-VHDL13_DWEH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:18 2705
ber01-VHDL13_DWEH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:28:12 2535
ber01-VHDL13_DWEH_230400-2602230400-dsw--0-ia5 23-Feb-2026 05:58:12 2503
ber01-VHDL13_DWEH_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:22 2507
ber01-VHDL13_DWEH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:28:17 2532
ber01-VHDL13_DWEH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:17 2219
ber01-VHDL13_DWHG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 3392
ber01-VHDL13_DWHG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3403
ber01-VHDL13_DWHG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:15 3722
ber01-VHDL13_DWHG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3088
ber01-VHDL13_DWHG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:11 3415
ber01-VHDL13_DWHG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:07 3300
ber01-VHDL13_DWHG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3321
ber01-VHDL13_DWHG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:09 2439
ber01-VHDL13_DWHH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 2727
ber01-VHDL13_DWHH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 2599
ber01-VHDL13_DWHH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2612
ber01-VHDL13_DWHH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2212
ber01-VHDL13_DWHH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:11 2758
ber01-VHDL13_DWHH_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:07 2966
ber01-VHDL13_DWHH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3091
ber01-VHDL13_DWHH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:09 2557
ber01-VHDL13_DWLG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2661
ber01-VHDL13_DWLG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2651
ber01-VHDL13_DWLG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3177
ber01-VHDL13_DWLG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3194
ber01-VHDL13_DWLG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3416
ber01-VHDL13_DWLG_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 3279
ber01-VHDL13_DWLG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3379
ber01-VHDL13_DWLG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2499
ber01-VHDL13_DWLH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2718
ber01-VHDL13_DWLH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2708
ber01-VHDL13_DWLH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3182
ber01-VHDL13_DWLH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3035
ber01-VHDL13_DWLH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3207
ber01-VHDL13_DWLH_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 3030
ber01-VHDL13_DWLH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3135
ber01-VHDL13_DWLH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2392
ber01-VHDL13_DWLI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2434
ber01-VHDL13_DWLI_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2424
ber01-VHDL13_DWLI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2880
ber01-VHDL13_DWLI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2755
ber01-VHDL13_DWLI_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 2890
ber01-VHDL13_DWLI_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 2845
ber01-VHDL13_DWLI_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 2878
ber01-VHDL13_DWLI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2317
ber01-VHDL13_DWMG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3155
ber01-VHDL13_DWMG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 3153
ber01-VHDL13_DWMG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3317
ber01-VHDL13_DWMG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 3065
ber01-VHDL13_DWMG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3686
ber01-VHDL13_DWMG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:03 3629
ber01-VHDL13_DWMG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3867
ber01-VHDL13_DWMG_230800_COR-2602230800-dsw--0-ia5 23-Feb-2026 09:35:44 3871
ber01-VHDL13_DWMG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 3184
ber01-VHDL13_DWMO_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3005
ber01-VHDL13_DWMO_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2897
ber01-VHDL13_DWMO_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3156
ber01-VHDL13_DWMO_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2741
ber01-VHDL13_DWMO_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3006
ber01-VHDL13_DWMO_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:03 3008
ber01-VHDL13_DWMO_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3038
ber01-VHDL13_DWMO_230800_COR-2602230800-dsw--0-ia5 23-Feb-2026 10:11:07 3042
ber01-VHDL13_DWMO_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2347
ber01-VHDL13_DWMP_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 3377
ber01-VHDL13_DWMP_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 3390
ber01-VHDL13_DWMP_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3506
ber01-VHDL13_DWMP_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:06 3231
ber01-VHDL13_DWMP_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3671
ber01-VHDL13_DWMP_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:03 3673
ber01-VHDL13_DWMP_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3698
ber01-VHDL13_DWMP_230800_COR-2602230800-dsw--0-ia5 23-Feb-2026 09:59:58 3702
ber01-VHDL13_DWMP_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2945
ber01-VHDL13_DWOG_220300-2602220300-dsw--0-ia5 22-Feb-2026 04:00:01 3559
ber01-VHDL13_DWOG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:01 3932
ber01-VHDL13_DWOG_221700-2602221700-dsw--0-ia5 22-Feb-2026 19:00:06 3858
ber01-VHDL13_DWOG_230300-2602230300-dsw--0-ia5 23-Feb-2026 04:00:07 4534
ber01-VHDL13_DWOG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 4567
ber01-VHDL13_DWOG_231700-2602231700-dsw--0-ia5 23-Feb-2026 19:00:04 4490
ber01-VHDL13_DWOH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:16 2423
ber01-VHDL13_DWOH_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2393
ber01-VHDL13_DWOH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:16 2845
ber01-VHDL13_DWOH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:18 2647
ber01-VHDL13_DWOH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:28:12 2506
ber01-VHDL13_DWOH_230400-2602230400-dsw--0-ia5 23-Feb-2026 05:58:16 2739
ber01-VHDL13_DWOH_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:22 2743
ber01-VHDL13_DWOH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:28:17 2233
ber01-VHDL13_DWOH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:17 2146
ber01-VHDL13_DWOI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:28:16 2420
ber01-VHDL13_DWOI_220400-2602220400-dsw--0-ia5 22-Feb-2026 05:58:17 2415
ber01-VHDL13_DWOI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:28:12 2643
ber01-VHDL13_DWOI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:28:12 2591
ber01-VHDL13_DWOI_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:28:16 2316
ber01-VHDL13_DWOI_230400-2602230400-dsw--0-ia5 23-Feb-2026 05:58:16 2265
ber01-VHDL13_DWOI_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:22 2269
ber01-VHDL13_DWOI_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:28:17 2293
ber01-VHDL13_DWOI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:28:11 1945
ber01-VHDL13_DWON_220100-2602220100-dsw--0-ia5 22-Feb-2026 01:00:10 3355
ber01-VHDL13_DWON_220341-2602220341-dsw--0-ia5 22-Feb-2026 03:41:37 3355
ber01-VHDL13_DWON_220628-2602220628-dsw--0-ia5 22-Feb-2026 06:28:51 3165
ber01-VHDL13_DWON_220703-2602220703-dsw--0-ia5 22-Feb-2026 07:03:46 3405
ber01-VHDL13_DWON_220853-2602220853-dsw--0-ia5 22-Feb-2026 08:53:54 3405
ber01-VHDL13_DWON_220925-2602220925-dsw--0-ia5 22-Feb-2026 09:25:26 3405
ber01-VHDL13_DWON_221549-2602221549-dsw--0-ia5 22-Feb-2026 15:49:37 2967
ber01-VHDL13_DWON_221759-2602221759-dsw--0-ia5 22-Feb-2026 17:59:07 3081
ber01-VHDL13_DWON_222336-2602222336-dsw--0-ia5 22-Feb-2026 23:36:37 3299
ber01-VHDL13_DWON_230327-2602230327-dsw--0-ia5 23-Feb-2026 03:27:21 3207
ber01-VHDL13_DWON_230339-2602230339-dsw--0-ia5 23-Feb-2026 03:39:51 3207
ber01-VHDL13_DWON_230629-2602230629-dsw--0-ia5 23-Feb-2026 06:29:17 3624
ber01-VHDL13_DWON_230658-2602230658-dsw--0-ia5 23-Feb-2026 06:58:17 3619
ber01-VHDL13_DWON_230913-2602230913-dsw--0-ia5 23-Feb-2026 09:14:02 3722
ber01-VHDL13_DWON_231542-2602231542-dsw--0-ia5 23-Feb-2026 15:42:41 3819
ber01-VHDL13_DWON_231558-2602231558-dsw--0-ia5 23-Feb-2026 15:58:42 3819
ber01-VHDL13_DWON_231801-2602231801-dsw--0-ia5 23-Feb-2026 18:01:41 3396
ber01-VHDL13_DWON_232028-2602232028-dsw--0-ia5 23-Feb-2026 20:28:11 3396
ber01-VHDL13_DWPG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 1971
ber01-VHDL13_DWPG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 1987
ber01-VHDL13_DWPG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:15 2646
ber01-VHDL13_DWPG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2619
ber01-VHDL13_DWPG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 2688
ber01-VHDL13_DWPG_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 2757
ber01-VHDL13_DWPG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 2798
ber01-VHDL13_DWPG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2080
ber01-VHDL13_DWPH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:05 2121
ber01-VHDL13_DWPH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:01 2177
ber01-VHDL13_DWPH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 2722
ber01-VHDL13_DWPH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:05 2632
ber01-VHDL13_DWPH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 2618
ber01-VHDL13_DWPH_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 2518
ber01-VHDL13_DWPH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 2518
ber01-VHDL13_DWPH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 1899
ber01-VHDL13_DWSG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:30:10 3595
ber01-VHDL13_DWSG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3520
ber01-VHDL13_DWSG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:30:14 3768
ber01-VHDL13_DWSG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:30:06 2985
ber01-VHDL13_DWSG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:30:05 3373
ber01-VHDL13_DWSG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:07 3381
ber01-VHDL13_DWSG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:30:09 3382
ber01-VHDL13_DWSG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:30:02 2657
ber01-VHDL17_DWOG_221200-2602221200-dsw--0-ia5 22-Feb-2026 12:59:06 3052
ber01-VHDL17_DWOG_231200-2602231200-dsw--0-ia5 23-Feb-2026 12:11:57 3629
swis2-VHDL20_DWEG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 2702
swis2-VHDL20_DWEG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 2715
swis2-VHDL20_DWEG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3326
swis2-VHDL20_DWEG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 2974
swis2-VHDL20_DWEG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 2784
swis2-VHDL20_DWEG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 3063
swis2-VHDL20_DWEG_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:06 3067
swis2-VHDL20_DWEG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 2713
swis2-VHDL20_DWEG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2476
swis2-VHDL20_DWEH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 3039
swis2-VHDL20_DWEH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 3036
swis2-VHDL20_DWEH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3597
swis2-VHDL20_DWEH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3060
swis2-VHDL20_DWEH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 2858
swis2-VHDL20_DWEH_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 2842
swis2-VHDL20_DWEH_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:06 2846
swis2-VHDL20_DWEH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 3037
swis2-VHDL20_DWEH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2578
swis2-VHDL20_DWEI_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:07 2715
swis2-VHDL20_DWEI_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:06 2768
swis2-VHDL20_DWEI_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3171
swis2-VHDL20_DWEI_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 2944
swis2-VHDL20_DWEI_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 2611
swis2-VHDL20_DWEI_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 2620
swis2-VHDL20_DWEI_230400_COR-2602230400-dsw--0-ia5 23-Feb-2026 07:55:06 2624
swis2-VHDL20_DWEI_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 2820
swis2-VHDL20_DWEI_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2300
swis2-VHDL20_DWHG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 3578
swis2-VHDL20_DWHG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 3586
swis2-VHDL20_DWHG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 4256
swis2-VHDL20_DWHG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:06 3271
swis2-VHDL20_DWHG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 3601
swis2-VHDL20_DWHG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:07 3483
swis2-VHDL20_DWHG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 3857
swis2-VHDL20_DWHG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:06 2622
swis2-VHDL20_DWHH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 2913
swis2-VHDL20_DWHH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:07 2785
swis2-VHDL20_DWHH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3154
swis2-VHDL20_DWHH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:06 2398
swis2-VHDL20_DWHH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 2944
swis2-VHDL20_DWHH_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:00:07 3152
swis2-VHDL20_DWHH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 3634
swis2-VHDL20_DWHH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:06 2743
swis2-VHDL20_DWLG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 3003
swis2-VHDL20_DWLG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 2992
swis2-VHDL20_DWLG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3755
swis2-VHDL20_DWLG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3535
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swis2-VHDL20_DWMG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:04 3847
swis2-VHDL20_DWMG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3434
swis2-VHDL20_DWMG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 4041
swis2-VHDL20_DWMG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 4133
swis2-VHDL20_DWMG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 4614
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swis2-VHDL20_DWMO_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:01 3272
swis2-VHDL20_DWMO_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:04 3699
swis2-VHDL20_DWMO_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3116
swis2-VHDL20_DWMO_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 3379
swis2-VHDL20_DWMO_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 3385
swis2-VHDL20_DWMO_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 3652
swis2-VHDL20_DWMO_230800_COR-2602230800-dsw--0-ia5 23-Feb-2026 10:11:07 3656
swis2-VHDL20_DWMO_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2724
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swis2-VHDL20_DWMP_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:04 4042
swis2-VHDL20_DWMP_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3586
swis2-VHDL20_DWMP_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 4043
swis2-VHDL20_DWMP_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 4177
swis2-VHDL20_DWMP_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:06 4451
swis2-VHDL20_DWMP_230800_COR-2602230800-dsw--0-ia5 23-Feb-2026 09:59:58 4455
swis2-VHDL20_DWMP_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 3434
swis2-VHDL20_DWPG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 2300
swis2-VHDL20_DWPG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 2312
swis2-VHDL20_DWPG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3105
swis2-VHDL20_DWPG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3078
swis2-VHDL20_DWPG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:06 3016
swis2-VHDL20_DWPG_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 3084
swis2-VHDL20_DWPG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:02 3299
swis2-VHDL20_DWPG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2581
swis2-VHDL20_DWPH_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:01 2450
swis2-VHDL20_DWPH_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:00:11 2504
swis2-VHDL20_DWPH_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:07 3181
swis2-VHDL20_DWPH_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3091
swis2-VHDL20_DWPH_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:06 2945
swis2-VHDL20_DWPH_230400-2602230400-dsw--0-ia5 23-Feb-2026 07:18:55 2847
swis2-VHDL20_DWPH_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:02 2979
swis2-VHDL20_DWPH_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 2360
swis2-VHDL20_DWSG_220200-2602220200-dsw--0-ia5 22-Feb-2026 03:45:03 3942
swis2-VHDL20_DWSG_220400-2602220400-dsw--0-ia5 22-Feb-2026 06:15:01 3874
swis2-VHDL20_DWSG_220800-2602220800-dsw--0-ia5 22-Feb-2026 09:45:04 4270
swis2-VHDL20_DWSG_221300-2602221300-dsw--0-ia5 22-Feb-2026 14:45:10 4085
swis2-VHDL20_DWSG_221800-2602221800-dsw--0-ia5 22-Feb-2026 19:45:01 3341
swis2-VHDL20_DWSG_230200-2602230200-dsw--0-ia5 23-Feb-2026 03:45:02 3718
swis2-VHDL20_DWSG_230400-2602230400-dsw--0-ia5 23-Feb-2026 06:15:01 3737
swis2-VHDL20_DWSG_230800-2602230800-dsw--0-ia5 23-Feb-2026 09:45:02 3886
swis2-VHDL20_DWSG_231300-2602231300-dsw--0-ia5 23-Feb-2026 14:45:07 3450
swis2-VHDL20_DWSG_231800-2602231800-dsw--0-ia5 23-Feb-2026 19:45:01 3015
wst04-VHDL20_DWEG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:17 246731
wst04-VHDL20_DWEG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:16 245730
wst04-VHDL20_DWEG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:12 250368
wst04-VHDL20_DWEG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:12 248413
wst04-VHDL20_DWEG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:22 248961
wst04-VHDL20_DWEG_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:17 248781
wst04-VHDL20_DWEG_230400_COR-2602230400-omedes-..> 23-Feb-2026 07:55:26 248781
wst04-VHDL20_DWEG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:20 247756
wst04-VHDL20_DWEG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 247279
wst04-VHDL20_DWEH_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:17 237994
wst04-VHDL20_DWEH_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:16 237049
wst04-VHDL20_DWEH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:17 241704
wst04-VHDL20_DWEH_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:12 239817
wst04-VHDL20_DWEH_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:22 240246
wst04-VHDL20_DWEH_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:17 239785
wst04-VHDL20_DWEH_230400_COR-2602230400-omedes-..> 23-Feb-2026 07:55:26 239785
wst04-VHDL20_DWEH_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:16 242091
wst04-VHDL20_DWEH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 240254
wst04-VHDL20_DWEI_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:21 347600
wst04-VHDL20_DWEI_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:26 347035
wst04-VHDL20_DWEI_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:21 355044
wst04-VHDL20_DWEI_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:16 354238
wst04-VHDL20_DWEI_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:22 354318
wst04-VHDL20_DWEI_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:17 353775
wst04-VHDL20_DWEI_230400_COR-2602230400-omedes-..> 23-Feb-2026 07:55:32 353775
wst04-VHDL20_DWEI_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:20 353896
wst04-VHDL20_DWEI_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 353459
wst04-VHDL20_DWHG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:21 344767
wst04-VHDL20_DWHG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:11 344667
wst04-VHDL20_DWHG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:27 348748
wst04-VHDL20_DWHG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:22 345829
wst04-VHDL20_DWHG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:16 346043
wst04-VHDL20_DWHG_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:00:13 345537
wst04-VHDL20_DWHG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:26 344955
wst04-VHDL20_DWHG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 342878
wst04-VHDL20_DWHH_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:21 328795
wst04-VHDL20_DWHH_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:11 328407
wst04-VHDL20_DWHH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:27 327988
wst04-VHDL20_DWHH_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:22 326083
wst04-VHDL20_DWHH_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:12 327081
wst04-VHDL20_DWHH_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:00:13 327486
wst04-VHDL20_DWHH_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:26 328174
wst04-VHDL20_DWHH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 327023
wst04-VHDL20_DWLG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 333330
wst04-VHDL20_DWLG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:41 333322
wst04-VHDL20_DWLG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 342513
wst04-VHDL20_DWLG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:26 342068
wst04-VHDL20_DWLG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:26 342474
wst04-VHDL20_DWLG_230400-2602230400-omedes--0.pdf 23-Feb-2026 07:19:52 342077
wst04-VHDL20_DWLG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:32 351674
wst04-VHDL20_DWLG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 350582
wst04-VHDL20_DWLH_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 334384
wst04-VHDL20_DWLH_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:41 334349
wst04-VHDL20_DWLH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 341107
wst04-VHDL20_DWLH_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:22 340129
wst04-VHDL20_DWLH_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:26 340438
wst04-VHDL20_DWLH_230400-2602230400-omedes--0.pdf 23-Feb-2026 07:19:46 339760
wst04-VHDL20_DWLH_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:32 344997
wst04-VHDL20_DWLH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 344069
wst04-VHDL20_DWLI_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 343260
wst04-VHDL20_DWLI_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:41 343241
wst04-VHDL20_DWLI_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 344642
wst04-VHDL20_DWLI_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:26 344489
wst04-VHDL20_DWLI_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:26 344759
wst04-VHDL20_DWLI_230400-2602230400-omedes--0.pdf 23-Feb-2026 07:19:52 344134
wst04-VHDL20_DWLI_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:32 344974
wst04-VHDL20_DWLI_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 344033
wst04-VHDL20_DWMG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 566763
wst04-VHDL20_DWMG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:26 566365
wst04-VHDL20_DWMG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:27 582490
wst04-VHDL20_DWMG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:16 581769
wst04-VHDL20_DWMG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:16 582803
wst04-VHDL20_DWMG_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:22 582850
wst04-VHDL20_DWMG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:16 592248
wst04-VHDL20_DWMG_230800_COR-2602230800-omedes-..> 23-Feb-2026 09:35:52 592248
wst04-VHDL20_DWMG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 589176
wst04-VHDL20_DWMO_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 459208
wst04-VHDL20_DWMO_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:16 459156
wst04-VHDL20_DWMO_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:21 464997
wst04-VHDL20_DWMO_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:16 463948
wst04-VHDL20_DWMO_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:12 464139
wst04-VHDL20_DWMO_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:22 464714
wst04-VHDL20_DWMO_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:12 475351
wst04-VHDL20_DWMO_230800_COR-2602230800-omedes-..> 23-Feb-2026 10:11:17 475351
wst04-VHDL20_DWMO_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 472439
wst04-VHDL20_DWMP_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:11 571452
wst04-VHDL20_DWMP_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:22 572256
wst04-VHDL20_DWMP_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:27 587346
wst04-VHDL20_DWMP_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:16 586467
wst04-VHDL20_DWMP_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:16 586384
wst04-VHDL20_DWMP_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:22 587518
wst04-VHDL20_DWMP_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:16 594682
wst04-VHDL20_DWMP_230800_COR-2602230800-omedes-..> 23-Feb-2026 10:00:07 594682
wst04-VHDL20_DWMP_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:16 591824
wst04-VHDL20_DWPG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:27 343528
wst04-VHDL20_DWPG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:31 343536
wst04-VHDL20_DWPG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:37 399239
wst04-VHDL20_DWPG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:26 354577
wst04-VHDL20_DWPG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:26 354194
wst04-VHDL20_DWPG_230400-2602230400-omedes--0.pdf 23-Feb-2026 07:19:46 354598
wst04-VHDL20_DWPG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:36 402235
wst04-VHDL20_DWPG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:26 356368
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wst04-VHDL20_DWPH_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:00:31 242176
wst04-VHDL20_DWPH_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:31 292295
wst04-VHDL20_DWPH_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:22 292324
wst04-VHDL20_DWPH_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:22 246656
wst04-VHDL20_DWPH_230400-2602230400-omedes--0.pdf 23-Feb-2026 07:19:46 246639
wst04-VHDL20_DWPH_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:32 286568
wst04-VHDL20_DWPH_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:22 285202
wst04-VHDL20_DWSG_220200-2602220200-omedes--0.pdf 22-Feb-2026 03:45:17 360131
wst04-VHDL20_DWSG_220400-2602220400-omedes--0.pdf 22-Feb-2026 06:15:16 360230
wst04-VHDL20_DWSG_220800-2602220800-omedes--0.pdf 22-Feb-2026 09:45:12 359429
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wst04-VHDL20_DWSG_221800-2602221800-omedes--0.pdf 22-Feb-2026 19:45:12 358394
wst04-VHDL20_DWSG_230200-2602230200-omedes--0.pdf 23-Feb-2026 03:45:12 358749
wst04-VHDL20_DWSG_230400-2602230400-omedes--0.pdf 23-Feb-2026 06:15:11 358566
wst04-VHDL20_DWSG_230800-2602230800-omedes--0.pdf 23-Feb-2026 09:45:12 362709
wst04-VHDL20_DWSG_231300-2602231300-omedes--0.pdf 23-Feb-2026 14:45:11 361794
wst04-VHDL20_DWSG_231800-2602231800-omedes--0.pdf 23-Feb-2026 19:45:12 361158