Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Aug-2026 14:13:04 5380
FPDL13_DWMZ_140600 14-Aug-2026 13:01:44 4026
SXDL31_DWAV_130800 13-Aug-2026 07:13:24 6136
SXDL31_DWAV_131800 13-Aug-2026 16:31:58 4765
SXDL31_DWAV_140800 14-Aug-2026 08:46:44 12818
SXDL31_DWAV_141800 14-Aug-2026 17:34:28 8122
SXDL31_DWAV_LATEST 14-Aug-2026 17:34:28 8122
SXDL33_DWAV_130000 13-Aug-2026 10:03:29 8167
SXDL33_DWAV_140000 14-Aug-2026 09:52:20 6120
SXDL33_DWAV_LATEST 14-Aug-2026 09:52:20 6120
ber01-FWDL39_DWMS_131200-2608131200-dsw--0-ia5 13-Aug-2026 11:49:29 1560
ber01-FWDL39_DWMS_141200-2608141200-dsw--0-ia5 14-Aug-2026 11:39:21 1879
ber01-VHDL13_DWEG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2824
ber01-VHDL13_DWEG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:14 3600
ber01-VHDL13_DWEH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2675
ber01-VHDL13_DWEH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:14 3370
ber01-VHDL13_DWEI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2722
ber01-VHDL13_DWEI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:18 3300
ber01-VHDL13_DWHG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 3573
ber01-VHDL13_DWHG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3754
ber01-VHDL13_DWHH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 3033
ber01-VHDL13_DWHH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3458
ber01-VHDL13_DWLG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2647
ber01-VHDL13_DWLG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2438
ber01-VHDL13_DWLH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2597
ber01-VHDL13_DWLH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2633
ber01-VHDL13_DWLI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2474
ber01-VHDL13_DWLI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2503
ber01-VHDL13_DWMO_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2573
ber01-VHDL13_DWMO_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2944
ber01-VHDL13_DWMP_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2348
ber01-VHDL13_DWMP_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2747
ber01-VHDL13_DWMP_140800_COR-2608140800-dsw--0-ia5 14-Aug-2026 08:39:45 2741
ber01-VHDL13_DWOG_130300-2608130300-dsw--0-ia5 13-Aug-2026 03:00:07 2921
ber01-VHDL13_DWOG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2826
ber01-VHDL13_DWOG_131700-2608131700-dsw--0-ia5 13-Aug-2026 18:00:10 2692
ber01-VHDL13_DWOG_140300-2608140300-dsw--0-ia5 14-Aug-2026 03:00:28 3119
ber01-VHDL13_DWOG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3571
ber01-VHDL13_DWOG_141700-2608141700-dsw--0-ia5 14-Aug-2026 18:00:08 3511
ber01-VHDL13_DWON_130001-2608130001-dsw--0-ia5 13-Aug-2026 00:01:47 3108
ber01-VHDL13_DWON_130134-2608130134-dsw--0-ia5 13-Aug-2026 01:35:12 3084
ber01-VHDL13_DWON_130248-2608130248-dsw--0-ia5 13-Aug-2026 02:48:45 3088
ber01-VHDL13_DWON_130525-2608130525-dsw--0-ia5 13-Aug-2026 05:25:33 3118
ber01-VHDL13_DWON_130609-2608130609-dsw--0-ia5 13-Aug-2026 06:09:19 3241
ber01-VHDL13_DWON_130817-2608130817-dsw--0-ia5 13-Aug-2026 08:17:59 3241
ber01-VHDL13_DWON_131439-2608131439-dsw--0-ia5 13-Aug-2026 14:40:50 3228
ber01-VHDL13_DWON_131440-2608131440-dsw--0-ia5 13-Aug-2026 14:40:54 3228
ber01-VHDL13_DWON_131722-2608131722-dsw--0-ia5 13-Aug-2026 17:22:38 3017
ber01-VHDL13_DWON_140058-2608140058-dsw--0-ia5 14-Aug-2026 00:58:58 3458
ber01-VHDL13_DWON_140238-2608140238-dsw--0-ia5 14-Aug-2026 02:38:38 3547
ber01-VHDL13_DWON_140529-2608140529-dsw--0-ia5 14-Aug-2026 05:29:50 3552
ber01-VHDL13_DWON_140601-2608140601-dsw--0-ia5 14-Aug-2026 06:01:34 3637
ber01-VHDL13_DWON_140641-2608140641-dsw--0-ia5 14-Aug-2026 06:41:29 3631
ber01-VHDL13_DWON_141458-2608141458-dsw--0-ia5 14-Aug-2026 14:58:38 3736
ber01-VHDL13_DWON_141505-2608141505-dsw--0-ia5 14-Aug-2026 15:05:34 3736
ber01-VHDL13_DWON_141746-2608141746-dsw--0-ia5 14-Aug-2026 17:46:28 3427
ber01-VHDL13_DWON_141940-2608141940-dsw--0-ia5 14-Aug-2026 19:40:25 3384
ber01-VHDL13_DWPG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2485
ber01-VHDL13_DWPG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2463
ber01-VHDL13_DWPH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2528
ber01-VHDL13_DWPH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2435
ber01-VHDL13_DWSG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 2263
ber01-VHDL13_DWSG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3371
ber01-VHDL17_DWOG_131200-2608131200-dsw--0-ia5 13-Aug-2026 11:40:37 2518
ber01-VHDL17_DWOG_141200-2608141200-dsw--0-ia5 14-Aug-2026 11:01:12 2867
swis2-VHDL20_DWEG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 793
swis2-VHDL20_DWEG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:15 786
swis2-VHDL20_DWEG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1251
swis2-VHDL20_DWEG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1506
swis2-VHDL20_DWEG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1422
swis2-VHDL20_DWEG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1428
swis2-VHDL20_DWEG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1661
swis2-VHDL20_DWEG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2123
swis2-VHDL20_DWEH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 807
swis2-VHDL20_DWEH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:19 798
swis2-VHDL20_DWEH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1144
swis2-VHDL20_DWEH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1548
swis2-VHDL20_DWEH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1489
swis2-VHDL20_DWEH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1489
swis2-VHDL20_DWEH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1600
swis2-VHDL20_DWEH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2033
swis2-VHDL20_DWEI_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 813
swis2-VHDL20_DWEI_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:19 806
swis2-VHDL20_DWEI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1274
swis2-VHDL20_DWEI_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1536
swis2-VHDL20_DWEI_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1446
swis2-VHDL20_DWEI_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1449
swis2-VHDL20_DWEI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1607
swis2-VHDL20_DWEI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2081
swis2-VHDL20_DWHG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:46:57 974
swis2-VHDL20_DWHG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 971
swis2-VHDL20_DWHG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:45:09 1166
swis2-VHDL20_DWHG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:45:05 1247
swis2-VHDL20_DWHG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:45:18 1221
swis2-VHDL20_DWHG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1247
swis2-VHDL20_DWHG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:45:06 1520
swis2-VHDL20_DWHG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 2144
swis2-VHDL20_DWHH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:46:57 976
swis2-VHDL20_DWHH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 976
swis2-VHDL20_DWHH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:45:09 1045
swis2-VHDL20_DWHH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:45:05 1129
swis2-VHDL20_DWHH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:45:18 1055
swis2-VHDL20_DWHH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1309
swis2-VHDL20_DWHH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:45:06 1352
swis2-VHDL20_DWHH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 1658
swis2-VHDL20_DWLG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1028
swis2-VHDL20_DWLG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1098
swis2-VHDL20_DWLG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1209
swis2-VHDL20_DWLG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1182
swis2-VHDL20_DWLG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1072
swis2-VHDL20_DWLG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1157
swis2-VHDL20_DWLG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1255
swis2-VHDL20_DWLG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1345
swis2-VHDL20_DWLH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1032
swis2-VHDL20_DWLH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1102
swis2-VHDL20_DWLH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1349
swis2-VHDL20_DWLH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1186
swis2-VHDL20_DWLH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1076
swis2-VHDL20_DWLH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1186
swis2-VHDL20_DWLH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1284
swis2-VHDL20_DWLH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1249
swis2-VHDL20_DWLI_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1009
swis2-VHDL20_DWLI_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1103
swis2-VHDL20_DWLI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1255
swis2-VHDL20_DWLI_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1184
swis2-VHDL20_DWLI_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1074
swis2-VHDL20_DWLI_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1184
swis2-VHDL20_DWLI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1282
swis2-VHDL20_DWLI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1405
swis2-VHDL20_DWMO_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 848
swis2-VHDL20_DWMO_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:07 856
swis2-VHDL20_DWMO_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1195
swis2-VHDL20_DWMO_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1152
swis2-VHDL20_DWMO_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 973
swis2-VHDL20_DWMO_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:08 981
swis2-VHDL20_DWMO_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1418
swis2-VHDL20_DWMO_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1691
swis2-VHDL20_DWMP_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 840
swis2-VHDL20_DWMP_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:07 847
swis2-VHDL20_DWMP_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1359
swis2-VHDL20_DWMP_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1442
swis2-VHDL20_DWMP_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1140
swis2-VHDL20_DWMP_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:08 1147
swis2-VHDL20_DWMP_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1503
swis2-VHDL20_DWMP_140800_COR-2608140800-dsw--0-ia5 14-Aug-2026 08:39:45 3002
swis2-VHDL20_DWMP_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1739
swis2-VHDL20_DWPG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1033
swis2-VHDL20_DWPG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1110
swis2-VHDL20_DWPG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1338
swis2-VHDL20_DWPG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1200
swis2-VHDL20_DWPG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1090
swis2-VHDL20_DWPG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1195
swis2-VHDL20_DWPG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1293
swis2-VHDL20_DWPG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1254
swis2-VHDL20_DWPH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 787
swis2-VHDL20_DWPH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 858
swis2-VHDL20_DWPH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1085
swis2-VHDL20_DWPH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 950
swis2-VHDL20_DWPH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 840
swis2-VHDL20_DWPH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 950
swis2-VHDL20_DWPH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1048
swis2-VHDL20_DWPH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1012
swis2-VHDL20_DWSG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 744
swis2-VHDL20_DWSG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 750
swis2-VHDL20_DWSG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 1214
swis2-VHDL20_DWSG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1405
swis2-VHDL20_DWSG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1122
swis2-VHDL20_DWSG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1345
swis2-VHDL20_DWSG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1697
swis2-VHDL20_DWSG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:07 1692
swis2-VHDL20_DWSG_141800_COR-2608141800-dsw--0-ia5 14-Aug-2026 18:33:52 1603
wst04-VHDL20_DWEG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 232751
wst04-VHDL20_DWEG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 232784
wst04-VHDL20_DWEG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 234668
wst04-VHDL20_DWEG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 243995
wst04-VHDL20_DWEG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 243239
wst04-VHDL20_DWEG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 243317
wst04-VHDL20_DWEG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:15 243952
wst04-VHDL20_DWEG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 246884
wst04-VHDL20_DWEH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 233153
wst04-VHDL20_DWEH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 233143
wst04-VHDL20_DWEH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 234893
wst04-VHDL20_DWEH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 237584
wst04-VHDL20_DWEH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 237085
wst04-VHDL20_DWEH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 237413
wst04-VHDL20_DWEH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 238161
wst04-VHDL20_DWEH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 244007
wst04-VHDL20_DWEI_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 332135
wst04-VHDL20_DWEI_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 332169
wst04-VHDL20_DWEI_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 333533
wst04-VHDL20_DWEI_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 348283
wst04-VHDL20_DWEI_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 347322
wst04-VHDL20_DWEI_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 347341
wst04-VHDL20_DWEI_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 348242
wst04-VHDL20_DWEI_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 354251
wst04-VHDL20_DWHG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:46:57 334424
wst04-VHDL20_DWHG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 334210
wst04-VHDL20_DWHG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:45:22 335372
wst04-VHDL20_DWHG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:45:15 348667
wst04-VHDL20_DWHG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:45:18 348585
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wst04-VHDL20_DWHG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:45:31 349746
wst04-VHDL20_DWHG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:45:21 342679
wst04-VHDL20_DWHH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:46:57 329008
wst04-VHDL20_DWHH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 227528
wst04-VHDL20_DWHH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:45:22 329280
wst04-VHDL20_DWHH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:45:15 331779
wst04-VHDL20_DWHH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:45:18 331707
wst04-VHDL20_DWHH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 232110
wst04-VHDL20_DWHH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:45:31 332912
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wst04-VHDL20_DWLH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:31:06 333025
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wst04-VHDL20_DWLH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 340589
wst04-VHDL20_DWLH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:44 340766
wst04-VHDL20_DWLH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 340986
wst04-VHDL20_DWLH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 349467
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wst04-VHDL20_DWLI_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:43 328329
wst04-VHDL20_DWLI_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 373366
wst04-VHDL20_DWLI_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 337800
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wst04-VHDL20_DWLI_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:44 337880
wst04-VHDL20_DWLI_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 382702
wst04-VHDL20_DWLI_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 342331
wst04-VHDL20_DWMO_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 440803
wst04-VHDL20_DWMO_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 441008
wst04-VHDL20_DWMO_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 441165
wst04-VHDL20_DWMO_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 351553
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wst04-VHDL20_DWMO_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:19 357510
wst04-VHDL20_DWMP_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 554632
wst04-VHDL20_DWMP_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 554909
wst04-VHDL20_DWMP_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 453443
wst04-VHDL20_DWMP_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 468688
wst04-VHDL20_DWMP_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:20 571391
wst04-VHDL20_DWMP_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 571357
wst04-VHDL20_DWMP_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 469112
wst04-VHDL20_DWMP_140800_COR-2608140800-omedes-..> 14-Aug-2026 08:39:54 576059
wst04-VHDL20_DWMP_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 472433
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wst04-VHDL20_DWPG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:33 335430
wst04-VHDL20_DWPG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 380728
wst04-VHDL20_DWPG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 342177
wst04-VHDL20_DWPG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 239877
wst04-VHDL20_DWPG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:34 342305
wst04-VHDL20_DWPG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:53 387062
wst04-VHDL20_DWPG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:33 347981
wst04-VHDL20_DWPH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 235579
wst04-VHDL20_DWPH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:33 235042
wst04-VHDL20_DWPH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 235495
wst04-VHDL20_DWPH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 239603
wst04-VHDL20_DWPH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 239575
wst04-VHDL20_DWPH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:34 239793
wst04-VHDL20_DWPH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 239945
wst04-VHDL20_DWPH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 241229
wst04-VHDL20_DWSG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 343015
wst04-VHDL20_DWSG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 343119
wst04-VHDL20_DWSG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 343691
wst04-VHDL20_DWSG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 354185
wst04-VHDL20_DWSG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 354097
wst04-VHDL20_DWSG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 354471
wst04-VHDL20_DWSG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 355813
wst04-VHDL20_DWSG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:33:54 355200