Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Jan-2026 11:36:37 3017
FPDL13_DWMZ_150600 15-Jan-2026 13:47:54 7753
SXDL31_DWAV_140800 14-Jan-2026 08:08:35 7241
SXDL31_DWAV_141800 14-Jan-2026 17:10:09 9414
SXDL31_DWAV_150800 15-Jan-2026 09:00:51 12772
SXDL31_DWAV_151800 15-Jan-2026 16:42:54 11067
SXDL31_DWAV_LATEST 15-Jan-2026 16:42:54 11067
SXDL33_DWAV_140000 14-Jan-2026 09:55:49 7633
SXDL33_DWAV_150000 15-Jan-2026 09:27:35 7611
SXDL33_DWAV_LATEST 15-Jan-2026 09:27:35 7611
ber01-FWDL39_DWMS_141230-2601141230-dsw--0-ia5 14-Jan-2026 12:02:51 1474
ber01-FWDL39_DWMS_151230-2601151230-dsw--0-ia5 15-Jan-2026 12:30:08 1540
ber01-VHDL13_DWEH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:11 2121
ber01-VHDL13_DWEH_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:12 2187
ber01-VHDL13_DWEH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:18 2075
ber01-VHDL13_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 2305
ber01-VHDL13_DWEH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:14 2429
ber01-VHDL13_DWEH_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:11 2474
ber01-VHDL13_DWEH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:13 2685
ber01-VHDL13_DWEH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:17 2812
ber01-VHDL13_DWHG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 2977
ber01-VHDL13_DWHG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2977
ber01-VHDL13_DWHG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:10 3082
ber01-VHDL13_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 3017
ber01-VHDL13_DWHG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 3132
ber01-VHDL13_DWHG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 3043
ber01-VHDL13_DWHG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 3362
ber01-VHDL13_DWHG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:08 3131
ber01-VHDL13_DWHH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 2494
ber01-VHDL13_DWHH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2494
ber01-VHDL13_DWHH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:10 2590
ber01-VHDL13_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 2563
ber01-VHDL13_DWHH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2544
ber01-VHDL13_DWHH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2476
ber01-VHDL13_DWHH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 2606
ber01-VHDL13_DWHH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:08 2506
ber01-VHDL13_DWLG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2684
ber01-VHDL13_DWLG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2599
ber01-VHDL13_DWLG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2817
ber01-VHDL13_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2581
ber01-VHDL13_DWLG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2988
ber01-VHDL13_DWLG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2988
ber01-VHDL13_DWLG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2941
ber01-VHDL13_DWLG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2780
ber01-VHDL13_DWLH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2732
ber01-VHDL13_DWLH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2507
ber01-VHDL13_DWLH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2664
ber01-VHDL13_DWLH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2843
ber01-VHDL13_DWLH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2872
ber01-VHDL13_DWLH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2906
ber01-VHDL13_DWLH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2508
ber01-VHDL13_DWLH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2331
ber01-VHDL13_DWLI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2261
ber01-VHDL13_DWLI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2174
ber01-VHDL13_DWLI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2263
ber01-VHDL13_DWLI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2393
ber01-VHDL13_DWLI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2544
ber01-VHDL13_DWLI_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2506
ber01-VHDL13_DWLI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2490
ber01-VHDL13_DWLI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2271
ber01-VHDL13_DWMG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3660
ber01-VHDL13_DWMG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3612
ber01-VHDL13_DWMG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3526
ber01-VHDL13_DWMG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 3175
ber01-VHDL13_DWMG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3527
ber01-VHDL13_DWMG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3529
ber01-VHDL13_DWMG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3470
ber01-VHDL13_DWMG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2994
ber01-VHDL13_DWMO_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3645
ber01-VHDL13_DWMO_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3579
ber01-VHDL13_DWMO_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3240
ber01-VHDL13_DWMO_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2966
ber01-VHDL13_DWMO_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3205
ber01-VHDL13_DWMO_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3223
ber01-VHDL13_DWMO_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3270
ber01-VHDL13_DWMO_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2943
ber01-VHDL13_DWMP_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3693
ber01-VHDL13_DWMP_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3679
ber01-VHDL13_DWMP_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3509
ber01-VHDL13_DWMP_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2945
ber01-VHDL13_DWMP_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3403
ber01-VHDL13_DWMP_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3458
ber01-VHDL13_DWMP_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3260
ber01-VHDL13_DWMP_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 3141
ber01-VHDL13_DWOG_140300-2601140300-dsw--0-ia5 14-Jan-2026 04:00:02 3963
ber01-VHDL13_DWOG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3762
ber01-VHDL13_DWOG_141700-2601141700-dsw--0-ia5 14-Jan-2026 19:00:04 3307
ber01-VHDL13_DWOG_150300-2601150300-dsw--0-ia5 15-Jan-2026 04:00:10 4062
ber01-VHDL13_DWOG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 4317
ber01-VHDL13_DWOG_151700-2601151700-dsw--0-ia5 15-Jan-2026 19:00:06 3933
ber01-VHDL13_DWOH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:11 2013
ber01-VHDL13_DWOH_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:12 2198
ber01-VHDL13_DWOH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:13 1955
ber01-VHDL13_DWOH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 1954
ber01-VHDL13_DWOH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:14 2229
ber01-VHDL13_DWOH_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:11 2169
ber01-VHDL13_DWOH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:17 2527
ber01-VHDL13_DWOH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:11 2845
ber01-VHDL13_DWOI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:17 1985
ber01-VHDL13_DWOI_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:16 2037
ber01-VHDL13_DWOI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:13 1986
ber01-VHDL13_DWOI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:12 1989
ber01-VHDL13_DWOI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:16 2146
ber01-VHDL13_DWOI_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:16 2164
ber01-VHDL13_DWOI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:13 2167
ber01-VHDL13_DWOI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:11 2305
ber01-VHDL13_DWON_140017-2601140017-dsw--0-ia5 14-Jan-2026 00:17:21 3618
ber01-VHDL13_DWON_140208-2601140208-dsw--0-ia5 14-Jan-2026 02:08:41 3618
ber01-VHDL13_DWON_140425-2601140425-dsw--0-ia5 14-Jan-2026 04:25:22 3459
ber01-VHDL13_DWON_140554-2601140554-dsw--0-ia5 14-Jan-2026 05:54:06 3459
ber01-VHDL13_DWON_140642-2601140642-dsw--0-ia5 14-Jan-2026 06:42:47 3459
ber01-VHDL13_DWON_140708-2601140708-dsw--0-ia5 14-Jan-2026 07:08:22 3668
ber01-VHDL13_DWON_140850-2601140850-dsw--0-ia5 14-Jan-2026 08:50:36 3668
ber01-VHDL13_DWON_141152-2601141152-dsw--0-ia5 14-Jan-2026 11:52:46 3668
ber01-VHDL13_DWON_141227-2601141227-dsw--0-ia5 14-Jan-2026 12:27:41 3848
ber01-VHDL13_DWON_141409-2601141409-dsw--0-ia5 14-Jan-2026 14:09:37 3898
ber01-VHDL13_DWON_141534-2601141534-dsw--0-ia5 14-Jan-2026 15:34:12 3898
ber01-VHDL13_DWON_141729-2601141729-dsw--0-ia5 14-Jan-2026 17:29:56 3225
ber01-VHDL13_DWON_141737-2601141737-dsw--0-ia5 14-Jan-2026 17:37:40 3225
ber01-VHDL13_DWON_141823-2601141823-dsw--0-ia5 14-Jan-2026 18:23:42 3225
ber01-VHDL13_DWON_141947-2601141947-dsw--0-ia5 14-Jan-2026 19:47:51 3209
ber01-VHDL13_DWON_142000-2601142000-dsw--0-ia5 14-Jan-2026 20:00:36 3209
ber01-VHDL13_DWON_150013-2601150013-dsw--0-ia5 15-Jan-2026 00:13:32 3258
ber01-VHDL13_DWON_150353-2601150353-dsw--0-ia5 15-Jan-2026 03:53:57 3258
ber01-VHDL13_DWON_150621-2601150621-dsw--0-ia5 15-Jan-2026 06:21:17 3664
ber01-VHDL13_DWON_150751-2601150751-dsw--0-ia5 15-Jan-2026 07:51:07 4193
ber01-VHDL13_DWON_150957-2601150957-dsw--0-ia5 15-Jan-2026 09:57:11 4178
ber01-VHDL13_DWON_151245-2601151245-dsw--0-ia5 15-Jan-2026 12:45:43 4181
ber01-VHDL13_DWON_151548-2601151548-dsw--0-ia5 15-Jan-2026 15:48:07 3597
ber01-VHDL13_DWON_151734-2601151734-dsw--0-ia5 15-Jan-2026 17:34:22 3542
ber01-VHDL13_DWPG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2507
ber01-VHDL13_DWPG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2321
ber01-VHDL13_DWPG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2268
ber01-VHDL13_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2116
ber01-VHDL13_DWPG_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:11 2339
ber01-VHDL13_DWPG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2529
ber01-VHDL13_DWPG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2620
ber01-VHDL13_DWPG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2237
ber01-VHDL13_DWPG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 1959
ber01-VHDL13_DWPH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2386
ber01-VHDL13_DWPH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2195
ber01-VHDL13_DWPH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2224
ber01-VHDL13_DWPH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2054
ber01-VHDL13_DWPH_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:27 2194
ber01-VHDL13_DWPH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2348
ber01-VHDL13_DWPH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2434
ber01-VHDL13_DWPH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2251
ber01-VHDL13_DWPH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2029
ber01-VHDL13_DWSG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 3147
ber01-VHDL13_DWSG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3035
ber01-VHDL13_DWSG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3102
ber01-VHDL13_DWSG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2586
ber01-VHDL13_DWSG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3252
ber01-VHDL13_DWSG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2947
ber01-VHDL13_DWSG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 2673
ber01-VHDL13_DWSG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2283
ber01-VHDL17_DWOG_141200-2601141200-dsw--0-ia5 14-Jan-2026 11:26:47 2379
ber01-VHDL17_DWOG_151200-2601151200-dsw--0-ia5 15-Jan-2026 11:48:57 2200
swis2-VHDL20_DWEG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2462
swis2-VHDL20_DWEG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2522
swis2-VHDL20_DWEG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2438
swis2-VHDL20_DWEG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2284
swis2-VHDL20_DWEG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2509
swis2-VHDL20_DWEG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2493
swis2-VHDL20_DWEG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3104
swis2-VHDL20_DWEG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3175
swis2-VHDL20_DWEH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2444
swis2-VHDL20_DWEH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2523
swis2-VHDL20_DWEH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2583
swis2-VHDL20_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2666
swis2-VHDL20_DWEH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2754
swis2-VHDL20_DWEH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2810
swis2-VHDL20_DWEH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3331
swis2-VHDL20_DWEH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3170
swis2-VHDL20_DWEI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2278
swis2-VHDL20_DWEI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2392
swis2-VHDL20_DWEI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2516
swis2-VHDL20_DWEI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2344
swis2-VHDL20_DWEI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2439
swis2-VHDL20_DWEI_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2519
swis2-VHDL20_DWEI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 2801
swis2-VHDL20_DWEI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 2660
swis2-VHDL20_DWHG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3163
swis2-VHDL20_DWHG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3160
swis2-VHDL20_DWHG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3732
swis2-VHDL20_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 3200
swis2-VHDL20_DWHG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 3318
swis2-VHDL20_DWHG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 3226
swis2-VHDL20_DWHG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:19 4039
swis2-VHDL20_DWHG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3314
swis2-VHDL20_DWHH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2680
swis2-VHDL20_DWHH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2680
swis2-VHDL20_DWHH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3218
swis2-VHDL20_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2749
swis2-VHDL20_DWHH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2730
swis2-VHDL20_DWHH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2662
swis2-VHDL20_DWHH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3231
swis2-VHDL20_DWHH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 2692
swis2-VHDL20_DWLG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3095
swis2-VHDL20_DWLG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3074
swis2-VHDL20_DWLG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 3469
swis2-VHDL20_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3056
swis2-VHDL20_DWLG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3466
swis2-VHDL20_DWLG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 3389
swis2-VHDL20_DWLG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3502
swis2-VHDL20_DWLG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 3178
swis2-VHDL20_DWLH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3116
swis2-VHDL20_DWLH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2921
swis2-VHDL20_DWLH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3261
swis2-VHDL20_DWLH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3257
swis2-VHDL20_DWLH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3289
swis2-VHDL20_DWLH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 3316
swis2-VHDL20_DWLH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3065
swis2-VHDL20_DWLH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2727
swis2-VHDL20_DWLI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2651
swis2-VHDL20_DWLI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2916
swis2-VHDL20_DWLI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2870
swis2-VHDL20_DWLI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 2888
swis2-VHDL20_DWLI_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 2910
swis2-VHDL20_DWLI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:19 3044
swis2-VHDL20_DWLI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2672
swis2-VHDL20_DWMG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 4209
swis2-VHDL20_DWMG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4184
swis2-VHDL20_DWMG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 4390
swis2-VHDL20_DWMG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3827
swis2-VHDL20_DWMG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 4176
swis2-VHDL20_DWMG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:03 3952
swis2-VHDL20_DWMG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 4102
swis2-VHDL20_DWMG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 3416
swis2-VHDL20_DWMO_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:08 4195
swis2-VHDL20_DWMO_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4147
swis2-VHDL20_DWMO_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 4099
swis2-VHDL20_DWMO_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3604
swis2-VHDL20_DWMO_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3781
swis2-VHDL20_DWMO_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:03 3650
swis2-VHDL20_DWMO_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3915
swis2-VHDL20_DWMO_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 3369
swis2-VHDL20_DWMP_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 4105
swis2-VHDL20_DWMP_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4101
swis2-VHDL20_DWMP_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 4349
swis2-VHDL20_DWMP_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3538
swis2-VHDL20_DWMP_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3962
swis2-VHDL20_DWMP_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:03 3881
swis2-VHDL20_DWMP_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3903
swis2-VHDL20_DWMP_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 3553
swis2-VHDL20_DWPG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2959
swis2-VHDL20_DWPG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2767
swis2-VHDL20_DWPG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2847
swis2-VHDL20_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2695
swis2-VHDL20_DWPG_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:16:01 3038
swis2-VHDL20_DWPG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3030
swis2-VHDL20_DWPG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 2998
swis2-VHDL20_DWPG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:19 2841
swis2-VHDL20_DWPG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2563
swis2-VHDL20_DWPH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2810
swis2-VHDL20_DWPH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2577
swis2-VHDL20_DWPH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2737
swis2-VHDL20_DWPH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2567
swis2-VHDL20_DWPH_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:16:11 2881
swis2-VHDL20_DWPH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 2733
swis2-VHDL20_DWPH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 2910
swis2-VHDL20_DWPH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:19 2981
swis2-VHDL20_DWPH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2758
swis2-VHDL20_DWSG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3583
swis2-VHDL20_DWSG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:02 3532
swis2-VHDL20_DWSG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3822
swis2-VHDL20_DWSG_141300-2601141300-dsw--0-ia5 14-Jan-2026 14:45:10 3549
swis2-VHDL20_DWSG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3114
swis2-VHDL20_DWSG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 3765
swis2-VHDL20_DWSG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:03 3397
swis2-VHDL20_DWSG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3303
swis2-VHDL20_DWSG_151300-2601151300-dsw--0-ia5 15-Jan-2026 14:45:06 2956
swis2-VHDL20_DWSG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2694
wst04-VHDL20_DWEG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 228205
wst04-VHDL20_DWEG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 227922
wst04-VHDL20_DWEG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 227413
wst04-VHDL20_DWEG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 226572
wst04-VHDL20_DWEG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 227348
wst04-VHDL20_DWEG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 226584
wst04-VHDL20_DWEG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 224658
wst04-VHDL20_DWEG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 226122
wst04-VHDL20_DWEH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 228491
wst04-VHDL20_DWEH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 228134
wst04-VHDL20_DWEH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 228617
wst04-VHDL20_DWEH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 228699
wst04-VHDL20_DWEH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 229759
wst04-VHDL20_DWEH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 229805
wst04-VHDL20_DWEH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 224229
wst04-VHDL20_DWEH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 226944
wst04-VHDL20_DWEI_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 318217
wst04-VHDL20_DWEI_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 318320
wst04-VHDL20_DWEI_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 321697
wst04-VHDL20_DWEI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 321181
wst04-VHDL20_DWEI_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 321324
wst04-VHDL20_DWEI_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:27 321190
wst04-VHDL20_DWEI_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 225492
wst04-VHDL20_DWEI_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 317007
wst04-VHDL20_DWHG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 317945
wst04-VHDL20_DWHG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:11 318152
wst04-VHDL20_DWHG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 318148
wst04-VHDL20_DWHG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 316370
wst04-VHDL20_DWHG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 316813
wst04-VHDL20_DWHG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:11 316711
wst04-VHDL20_DWHG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 308706
wst04-VHDL20_DWHG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 305193
wst04-VHDL20_DWHH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 305631
wst04-VHDL20_DWHH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:11 305565
wst04-VHDL20_DWHH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 301975
wst04-VHDL20_DWHH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 301223
wst04-VHDL20_DWHH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 301402
wst04-VHDL20_DWHH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:11 301141
wst04-VHDL20_DWHH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 307816
wst04-VHDL20_DWHH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 291192
wst04-VHDL20_DWLG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 300165
wst04-VHDL20_DWLG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 299983
wst04-VHDL20_DWLG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 301545
wst04-VHDL20_DWLG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 300079
wst04-VHDL20_DWLG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 300434
wst04-VHDL20_DWLG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 299820
wst04-VHDL20_DWLG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 298912
wst04-VHDL20_DWLG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 296856
wst04-VHDL20_DWLH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:27 312575
wst04-VHDL20_DWLH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 311841
wst04-VHDL20_DWLH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 320973
wst04-VHDL20_DWLH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 320411
wst04-VHDL20_DWLH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:26 321317
wst04-VHDL20_DWLH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 320741
wst04-VHDL20_DWLH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 297823
wst04-VHDL20_DWLH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 301383
wst04-VHDL20_DWLI_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:27 307495
wst04-VHDL20_DWLI_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 307331
wst04-VHDL20_DWLI_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 310760
wst04-VHDL20_DWLI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 310272
wst04-VHDL20_DWLI_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 311048
wst04-VHDL20_DWLI_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 310511
wst04-VHDL20_DWLI_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 298041
wst04-VHDL20_DWLI_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 306582
wst04-VHDL20_DWMG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 519569
wst04-VHDL20_DWMG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 520372
wst04-VHDL20_DWMG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 520406
wst04-VHDL20_DWMG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 518542
wst04-VHDL20_DWMG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 519093
wst04-VHDL20_DWMG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 518869
wst04-VHDL20_DWMG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 395613
wst04-VHDL20_DWMG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 523747
wst04-VHDL20_DWMO_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 415424
wst04-VHDL20_DWMO_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 415906
wst04-VHDL20_DWMO_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 421846
wst04-VHDL20_DWMO_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 419975
wst04-VHDL20_DWMO_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 420201
wst04-VHDL20_DWMO_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:17 420624
wst04-VHDL20_DWMO_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 313398
wst04-VHDL20_DWMO_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 418581
wst04-VHDL20_DWMP_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 544033
wst04-VHDL20_DWMP_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 545243
wst04-VHDL20_DWMP_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 544751
wst04-VHDL20_DWMP_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:22 542122
wst04-VHDL20_DWMP_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 541524
wst04-VHDL20_DWMP_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 542580
wst04-VHDL20_DWMP_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 395214
wst04-VHDL20_DWMP_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 553238
wst04-VHDL20_DWPG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 320823
wst04-VHDL20_DWPG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:31 320579
wst04-VHDL20_DWPG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 363439
wst04-VHDL20_DWPG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 317641
wst04-VHDL20_DWPG_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:14:47 317768
wst04-VHDL20_DWPG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:26 318244
wst04-VHDL20_DWPG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:31 317346
wst04-VHDL20_DWPG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 350658
wst04-VHDL20_DWPG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:26 296687
wst04-VHDL20_DWPH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 225831
wst04-VHDL20_DWPH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:31 225602
wst04-VHDL20_DWPH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 270201
wst04-VHDL20_DWPH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 269755
wst04-VHDL20_DWPH_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:15:01 269520
wst04-VHDL20_DWPH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 225443
wst04-VHDL20_DWPH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:31 224465
wst04-VHDL20_DWPH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 267420
wst04-VHDL20_DWPH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 268262
wst04-VHDL20_DWSG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 325999
wst04-VHDL20_DWSG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:13 326460
wst04-VHDL20_DWSG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 331518
wst04-VHDL20_DWSG_141300-2601141300-omedes--0.pdf 14-Jan-2026 14:45:16 331244
wst04-VHDL20_DWSG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 330822
wst04-VHDL20_DWSG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 331677
wst04-VHDL20_DWSG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:17 331470
wst04-VHDL20_DWSG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 309057
wst04-VHDL20_DWSG_151300-2601151300-omedes--0.pdf 15-Jan-2026 14:45:16 307894
wst04-VHDL20_DWSG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 331221