Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-May-2026 11:19:49 3105
SXDL31_DWAV_041800 04-May-2026 16:03:43 9769
SXDL31_DWAV_050800 05-May-2026 07:35:19 7712
SXDL31_DWAV_051800 05-May-2026 16:41:14 9293
SXDL31_DWAV_060800 06-May-2026 07:34:03 10603
SXDL31_DWAV_LATEST 06-May-2026 07:34:03 10603
SXDL33_DWAV_051014 05-May-2026 10:14:43 8270
SXDL33_DWAV_060000 06-May-2026 10:05:43 8825
SXDL33_DWAV_LATEST 06-May-2026 10:05:43 8825
ber01-FWDL39_DWMS_051230-2605051230-dsw--0-ia5 05-May-2026 11:12:07 1481
ber01-FWDL39_DWMS_061230-2605061230-dsw--0-ia5 06-May-2026 11:34:20 1559
ber01-VHDL13_DWEG_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:22 3660
ber01-VHDL13_DWEG_060800-2605060800-dsw--0-ia5 06-May-2026 08:28:17 2985
ber01-VHDL13_DWEH_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:22 3732
ber01-VHDL13_DWEH_060800-2605060800-dsw--0-ia5 06-May-2026 08:28:17 2946
ber01-VHDL13_DWEI_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:26 3454
ber01-VHDL13_DWEI_060800-2605060800-dsw--0-ia5 06-May-2026 08:28:17 2927
ber01-VHDL13_DWHG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 4085
ber01-VHDL13_DWHG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 3538
ber01-VHDL13_DWHH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3160
ber01-VHDL13_DWHH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 3253
ber01-VHDL13_DWLG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2680
ber01-VHDL13_DWLG_050800_COR-2605050800-dsw--0-ia5 05-May-2026 18:57:27 2880
ber01-VHDL13_DWLG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 3334
ber01-VHDL13_DWLH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3069
ber01-VHDL13_DWLH_050800_COR-2605050800-dsw--0-ia5 05-May-2026 19:11:07 2960
ber01-VHDL13_DWLH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 3679
ber01-VHDL13_DWLI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2873
ber01-VHDL13_DWLI_050800_COR-2605050800-dsw--0-ia5 05-May-2026 19:10:51 2825
ber01-VHDL13_DWLI_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 3100
ber01-VHDL13_DWMO_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3492
ber01-VHDL13_DWMO_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 3324
ber01-VHDL13_DWMP_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3563
ber01-VHDL13_DWMP_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 3945
ber01-VHDL13_DWOG_041700-2605041700-dsw--0-ia5 04-May-2026 18:00:07 4747
ber01-VHDL13_DWOG_050300-2605050300-dsw--0-ia5 05-May-2026 03:00:15 5053
ber01-VHDL13_DWOG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 4581
ber01-VHDL13_DWOG_051700-2605051700-dsw--0-ia5 05-May-2026 18:00:06 3881
ber01-VHDL13_DWOG_060300-2605060300-dsw--0-ia5 06-May-2026 03:00:08 4609
ber01-VHDL13_DWOG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 4445
ber01-VHDL13_DWOG_060800_COR-2605060800-dsw--0-ia5 06-May-2026 10:35:57 4842
ber01-VHDL13_DWON_041416-2605041416-dsw--0-ia5 04-May-2026 14:16:11 4398
ber01-VHDL13_DWON_041657-2605041657-dsw--0-ia5 04-May-2026 16:57:21 4242
ber01-VHDL13_DWON_041845-2605041845-dsw--0-ia5 04-May-2026 18:46:01 4494
ber01-VHDL13_DWON_042132-2605042132-dsw--0-ia5 04-May-2026 21:32:37 4538
ber01-VHDL13_DWON_050010-2605050010-dsw--0-ia5 05-May-2026 00:10:22 5024
ber01-VHDL13_DWON_050145-2605050145-dsw--0-ia5 05-May-2026 01:45:56 4954
ber01-VHDL13_DWON_050257-2605050257-dsw--0-ia5 05-May-2026 02:57:17 4954
ber01-VHDL13_DWON_050303-2605050303-dsw--0-ia5 05-May-2026 03:03:08 4954
ber01-VHDL13_DWON_050518-2605050518-dsw--0-ia5 05-May-2026 05:18:21 5331
ber01-VHDL13_DWON_050546-2605050546-dsw--0-ia5 05-May-2026 05:46:51 5331
ber01-VHDL13_DWON_050743-2605050743-dsw--0-ia5 05-May-2026 07:43:52 5039
ber01-VHDL13_DWON_050847-2605050847-dsw--0-ia5 05-May-2026 08:47:40 4957
ber01-VHDL13_DWON_051456-2605051456-dsw--0-ia5 05-May-2026 14:56:56 4264
ber01-VHDL13_DWON_051718-2605051718-dsw--0-ia5 05-May-2026 17:18:41 3854
ber01-VHDL13_DWON_051851-2605051851-dsw--0-ia5 05-May-2026 18:51:52 3904
ber01-VHDL13_DWON_052135-2605052135-dsw--0-ia5 05-May-2026 21:35:55 3936
ber01-VHDL13_DWON_060140-2605060140-dsw--0-ia5 06-May-2026 01:40:12 4277
ber01-VHDL13_DWON_060243-2605060243-dsw--0-ia5 06-May-2026 02:43:45 4277
ber01-VHDL13_DWON_060529-2605060529-dsw--0-ia5 06-May-2026 05:29:17 4293
ber01-VHDL13_DWON_060616-2605060616-dsw--0-ia5 06-May-2026 06:16:22 4131
ber01-VHDL13_DWON_061035-2605061035-dsw--0-ia5 06-May-2026 10:35:36 4425
ber01-VHDL13_DWPG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3458
ber01-VHDL13_DWPG_050800_COR-2605050800-dsw--0-ia5 05-May-2026 18:56:31 3172
ber01-VHDL13_DWPG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 3264
ber01-VHDL13_DWPH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2667
ber01-VHDL13_DWPH_050800_COR-2605050800-dsw--0-ia5 05-May-2026 18:56:51 2482
ber01-VHDL13_DWPH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 2617
ber01-VHDL13_DWSG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3010
ber01-VHDL13_DWSG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 3267
ber01-VHDL17_DWOG_051200-2605051200-dsw--0-ia5 05-May-2026 11:06:21 3058
ber01-VHDL17_DWOG_061200-2605061200-dsw--0-ia5 06-May-2026 11:05:23 2736
swis2-VHDL20_DWEG_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1966
swis2-VHDL20_DWEG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1926
swis2-VHDL20_DWEG_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 2009
swis2-VHDL20_DWEG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 2218
swis2-VHDL20_DWEG_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:07 2303
swis2-VHDL20_DWEG_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:01 1287
swis2-VHDL20_DWEG_060400-2605060400-dsw--0-ia5 06-May-2026 05:01:07 1246
swis2-VHDL20_DWEG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 1476
swis2-VHDL20_DWEH_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 2244
swis2-VHDL20_DWEH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1903
swis2-VHDL20_DWEH_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 1796
swis2-VHDL20_DWEH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 2005
swis2-VHDL20_DWEH_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:07 2028
swis2-VHDL20_DWEH_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:01 1418
swis2-VHDL20_DWEH_060400-2605060400-dsw--0-ia5 06-May-2026 05:01:07 1215
swis2-VHDL20_DWEH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 1438
swis2-VHDL20_DWEI_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1665
swis2-VHDL20_DWEI_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1679
swis2-VHDL20_DWEI_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 1781
swis2-VHDL20_DWEI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 1991
swis2-VHDL20_DWEI_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:07 1863
swis2-VHDL20_DWEI_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:01 1305
swis2-VHDL20_DWEI_060400-2605060400-dsw--0-ia5 06-May-2026 05:01:07 1248
swis2-VHDL20_DWEI_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 1470
swis2-VHDL20_DWHG_041800-2605041800-dsw--0-ia5 04-May-2026 18:45:04 2247
swis2-VHDL20_DWHG_050200-2605050200-dsw--0-ia5 05-May-2026 02:45:07 2028
swis2-VHDL20_DWHG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 2025
swis2-VHDL20_DWHG_050800-2605050800-dsw--0-ia5 05-May-2026 08:45:08 2274
swis2-VHDL20_DWHG_051800-2605051800-dsw--0-ia5 05-May-2026 18:45:03 2069
swis2-VHDL20_DWHG_060200-2605060200-dsw--0-ia5 06-May-2026 02:45:20 2366
swis2-VHDL20_DWHG_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:06 2330
swis2-VHDL20_DWHG_060800-2605060800-dsw--0-ia5 06-May-2026 08:45:07 2038
swis2-VHDL20_DWHH_041800-2605041800-dsw--0-ia5 04-May-2026 18:45:04 1178
swis2-VHDL20_DWHH_050200-2605050200-dsw--0-ia5 05-May-2026 02:45:07 1127
swis2-VHDL20_DWHH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1127
swis2-VHDL20_DWHH_050800-2605050800-dsw--0-ia5 05-May-2026 08:45:08 1349
swis2-VHDL20_DWHH_051800-2605051800-dsw--0-ia5 05-May-2026 18:45:03 1335
swis2-VHDL20_DWHH_060200-2605060200-dsw--0-ia5 06-May-2026 02:45:20 1313
swis2-VHDL20_DWHH_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:06 1320
swis2-VHDL20_DWHH_060800-2605060800-dsw--0-ia5 06-May-2026 08:45:07 1570
swis2-VHDL20_DWLG_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1510
swis2-VHDL20_DWLG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1221
swis2-VHDL20_DWLG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1254
swis2-VHDL20_DWLG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1570
swis2-VHDL20_DWLG_051800-2605051800-dsw--0-ia5 05-May-2026 18:31:03 1795
swis2-VHDL20_DWLG_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:22 1053
swis2-VHDL20_DWLG_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 1299
swis2-VHDL20_DWLG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:23 1793
swis2-VHDL20_DWLH_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1576
swis2-VHDL20_DWLH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1227
swis2-VHDL20_DWLH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1260
swis2-VHDL20_DWLH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1650
swis2-VHDL20_DWLH_051800-2605051800-dsw--0-ia5 05-May-2026 18:31:03 1499
swis2-VHDL20_DWLH_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:22 1402
swis2-VHDL20_DWLH_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 1522
swis2-VHDL20_DWLH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:23 1777
swis2-VHDL20_DWLI_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1532
swis2-VHDL20_DWLI_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1223
swis2-VHDL20_DWLI_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1412
swis2-VHDL20_DWLI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1733
swis2-VHDL20_DWLI_051800-2605051800-dsw--0-ia5 05-May-2026 18:31:03 1696
swis2-VHDL20_DWLI_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:22 1066
swis2-VHDL20_DWLI_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 1344
swis2-VHDL20_DWLI_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:23 1656
swis2-VHDL20_DWMO_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1328
swis2-VHDL20_DWMO_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1331
swis2-VHDL20_DWMO_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1287
swis2-VHDL20_DWMO_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1465
swis2-VHDL20_DWMO_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:04 1573
swis2-VHDL20_DWMO_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:01 1343
swis2-VHDL20_DWMO_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:02 1228
swis2-VHDL20_DWMO_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 1664
swis2-VHDL20_DWMP_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1706
swis2-VHDL20_DWMP_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1199
swis2-VHDL20_DWMP_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1151
swis2-VHDL20_DWMP_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1646
swis2-VHDL20_DWMP_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:04 1810
swis2-VHDL20_DWMP_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:01 1457
swis2-VHDL20_DWMP_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:02 1620
swis2-VHDL20_DWMP_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:07 2025
swis2-VHDL20_DWPG_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1684
swis2-VHDL20_DWPG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1231
swis2-VHDL20_DWPG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1228
swis2-VHDL20_DWPG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1562
swis2-VHDL20_DWPG_051800-2605051800-dsw--0-ia5 05-May-2026 18:31:03 1506
swis2-VHDL20_DWPG_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:22 1388
swis2-VHDL20_DWPG_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 942
swis2-VHDL20_DWPG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:23 1247
swis2-VHDL20_DWPH_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 968
swis2-VHDL20_DWPH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 903
swis2-VHDL20_DWPH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 878
swis2-VHDL20_DWPH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 968
swis2-VHDL20_DWPH_051800-2605051800-dsw--0-ia5 05-May-2026 18:31:03 848
swis2-VHDL20_DWPH_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:22 776
swis2-VHDL20_DWPH_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 791
swis2-VHDL20_DWPH_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:23 1021
swis2-VHDL20_DWSG_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1625
swis2-VHDL20_DWSG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:06 1490
swis2-VHDL20_DWSG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:21 1388
swis2-VHDL20_DWSG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1226
swis2-VHDL20_DWSG_051800-2605051800-dsw--0-ia5 05-May-2026 18:30:04 1608
swis2-VHDL20_DWSG_060200-2605060200-dsw--0-ia5 06-May-2026 02:30:07 1231
swis2-VHDL20_DWSG_060400-2605060400-dsw--0-ia5 06-May-2026 05:00:12 1129
swis2-VHDL20_DWSG_060800-2605060800-dsw--0-ia5 06-May-2026 08:30:03 1450
wst04-VHDL20_DWEG_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:22 244126
wst04-VHDL20_DWEG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:13 243194
wst04-VHDL20_DWEG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:13 243427
wst04-VHDL20_DWEG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:11 244490
wst04-VHDL20_DWEG_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:11 245451
wst04-VHDL20_DWEG_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:11 242915
wst04-VHDL20_DWEG_060400-2605060400-omedes--0.pdf 06-May-2026 05:43:30 242540
wst04-VHDL20_DWEG_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:12 243477
wst04-VHDL20_DWEH_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:18 244654
wst04-VHDL20_DWEH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:18 244192
wst04-VHDL20_DWEH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:17 243789
wst04-VHDL20_DWEH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:11 244871
wst04-VHDL20_DWEH_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:11 241174
wst04-VHDL20_DWEH_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:11 240276
wst04-VHDL20_DWEH_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:12 240081
wst04-VHDL20_DWEH_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:12 241046
wst04-VHDL20_DWEI_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:28 346586
wst04-VHDL20_DWEI_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:18 346919
wst04-VHDL20_DWEI_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:17 346495
wst04-VHDL20_DWEI_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:17 346845
wst04-VHDL20_DWEI_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:17 348222
wst04-VHDL20_DWEI_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:16 347509
wst04-VHDL20_DWEI_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:12 347090
wst04-VHDL20_DWEI_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:17 348239
wst04-VHDL20_DWHG_041800-2605041800-omedes--0.pdf 04-May-2026 18:45:12 351034
wst04-VHDL20_DWHG_050200-2605050200-omedes--0.pdf 05-May-2026 02:45:32 350509
wst04-VHDL20_DWHG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 350492
wst04-VHDL20_DWHG_050800-2605050800-omedes--0.pdf 05-May-2026 08:45:18 352198
wst04-VHDL20_DWHG_051800-2605051800-omedes--0.pdf 05-May-2026 18:45:13 353822
wst04-VHDL20_DWHG_060200-2605060200-omedes--0.pdf 06-May-2026 02:45:20 353881
wst04-VHDL20_DWHG_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:12 353830
wst04-VHDL20_DWHG_060800-2605060800-omedes--0.pdf 06-May-2026 08:45:17 353540
wst04-VHDL20_DWHH_041800-2605041800-omedes--0.pdf 04-May-2026 18:45:12 321790
wst04-VHDL20_DWHH_050200-2605050200-omedes--0.pdf 05-May-2026 02:45:32 321788
wst04-VHDL20_DWHH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 219659
wst04-VHDL20_DWHH_050800-2605050800-omedes--0.pdf 05-May-2026 08:45:18 322722
wst04-VHDL20_DWHH_051800-2605051800-omedes--0.pdf 05-May-2026 18:45:13 328098
wst04-VHDL20_DWHH_060200-2605060200-omedes--0.pdf 06-May-2026 02:45:20 328143
wst04-VHDL20_DWHH_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:12 223654
wst04-VHDL20_DWHH_060800-2605060800-omedes--0.pdf 06-May-2026 08:45:17 329216
wst04-VHDL20_DWLG_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:33 344822
wst04-VHDL20_DWLG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:27 344754
wst04-VHDL20_DWLG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:41 344500
wst04-VHDL20_DWLG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:51 345949
wst04-VHDL20_DWLG_050800_COR-2605050800-omedes-..> 05-May-2026 12:42:46 348815
wst04-VHDL20_DWLG_051800-2605051800-omedes--0.pdf 05-May-2026 18:31:20 348686
wst04-VHDL20_DWLG_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:26 346617
wst04-VHDL20_DWLG_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:42 347231
wst04-VHDL20_DWLG_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:42 348404
wst04-VHDL20_DWLH_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:24 352427
wst04-VHDL20_DWLH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 352076
wst04-VHDL20_DWLH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:47 351544
wst04-VHDL20_DWLH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:46 353200
wst04-VHDL20_DWLH_050800_COR-2605050800-omedes-..> 05-May-2026 12:41:31 348879
wst04-VHDL20_DWLH_051800-2605051800-omedes--0.pdf 05-May-2026 18:31:25 347609
wst04-VHDL20_DWLH_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:22 347429
wst04-VHDL20_DWLH_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:42 347345
wst04-VHDL20_DWLH_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:42 348439
wst04-VHDL20_DWLI_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:29 348819
wst04-VHDL20_DWLI_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 348687
wst04-VHDL20_DWLI_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:41 348912
wst04-VHDL20_DWLI_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:41 395003
wst04-VHDL20_DWLI_050800_COR-2605050800-omedes-..> 05-May-2026 12:43:10 394090
wst04-VHDL20_DWLI_051800-2605051800-omedes--0.pdf 05-May-2026 18:31:20 348457
wst04-VHDL20_DWLI_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:22 346609
wst04-VHDL20_DWLI_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:42 347203
wst04-VHDL20_DWLI_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:42 392841
wst04-VHDL20_DWMO_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:22 354458
wst04-VHDL20_DWMO_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:22 466024
wst04-VHDL20_DWMO_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:21 466186
wst04-VHDL20_DWMO_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:26 467004
wst04-VHDL20_DWMO_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:17 361750
wst04-VHDL20_DWMO_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:14 469886
wst04-VHDL20_DWMO_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:16 470034
wst04-VHDL20_DWMO_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:17 470695
wst04-VHDL20_DWMP_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:28 474927
wst04-VHDL20_DWMP_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:22 578608
wst04-VHDL20_DWMP_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:21 578506
wst04-VHDL20_DWMP_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:33 475199
wst04-VHDL20_DWMP_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:17 469825
wst04-VHDL20_DWMP_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:20 573901
wst04-VHDL20_DWMP_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:16 574266
wst04-VHDL20_DWMP_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:23 470159
wst04-VHDL20_DWPG_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:29 354021
wst04-VHDL20_DWPG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 244697
wst04-VHDL20_DWPG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:31 352977
wst04-VHDL20_DWPG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:46 398505
wst04-VHDL20_DWPG_050800_COR-2605050800-omedes-..> 05-May-2026 12:42:11 395588
wst04-VHDL20_DWPG_051800-2605051800-omedes--0.pdf 05-May-2026 18:31:20 350999
wst04-VHDL20_DWPG_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:22 245540
wst04-VHDL20_DWPG_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:32 350679
wst04-VHDL20_DWPG_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:48 395569
wst04-VHDL20_DWPH_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:24 243625
wst04-VHDL20_DWPH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:27 243879
wst04-VHDL20_DWPH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:31 243453
wst04-VHDL20_DWPH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:41 243395
wst04-VHDL20_DWPH_051800-2605051800-omedes--0.pdf 05-May-2026 18:31:20 240312
wst04-VHDL20_DWPH_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:22 240515
wst04-VHDL20_DWPH_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:32 240372
wst04-VHDL20_DWPH_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:42 241082
wst04-VHDL20_DWSG_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:18 353266
wst04-VHDL20_DWSG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:11 352729
wst04-VHDL20_DWSG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 352017
wst04-VHDL20_DWSG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:26 351552
wst04-VHDL20_DWSG_051800-2605051800-omedes--0.pdf 05-May-2026 18:30:11 355780
wst04-VHDL20_DWSG_060200-2605060200-omedes--0.pdf 06-May-2026 02:30:11 353980
wst04-VHDL20_DWSG_060400-2605060400-omedes--0.pdf 06-May-2026 05:00:12 354295
wst04-VHDL20_DWSG_060800-2605060800-omedes--0.pdf 06-May-2026 08:30:17 355816