Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Aug-2026 13:01:44 4026
FPDL13_DWMZ_150600 15-Aug-2026 11:47:04 3663
SXDL31_DWAV_140800 14-Aug-2026 08:46:44 12818
SXDL31_DWAV_141800 14-Aug-2026 17:34:28 8122
SXDL31_DWAV_150800 15-Aug-2026 07:42:21 8267
SXDL31_DWAV_151800 15-Aug-2026 17:22:00 5750
SXDL31_DWAV_LATEST 15-Aug-2026 17:22:00 5750
SXDL33_DWAV_140000 14-Aug-2026 09:52:20 6120
SXDL33_DWAV_150000 15-Aug-2026 09:42:41 10767
SXDL33_DWAV_LATEST 15-Aug-2026 09:42:41 10767
ber01-FWDL39_DWMS_141200-2608141200-dsw--0-ia5 14-Aug-2026 11:39:21 1879
ber01-FWDL39_DWMS_151200-2608151200-dsw--0-ia5 15-Aug-2026 11:37:32 1128
ber01-VHDL13_DWEG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:14 3600
ber01-VHDL13_DWEG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:18 3934
ber01-VHDL13_DWEH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:14 3370
ber01-VHDL13_DWEH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:18 3728
ber01-VHDL13_DWEI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:28:18 3300
ber01-VHDL13_DWEI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:14 3752
ber01-VHDL13_DWHG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3754
ber01-VHDL13_DWHG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 4133
ber01-VHDL13_DWHG_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:37:52 4124
ber01-VHDL13_DWHH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3458
ber01-VHDL13_DWHH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3211
ber01-VHDL13_DWHH_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:38:04 3215
ber01-VHDL13_DWLG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2438
ber01-VHDL13_DWLG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3139
ber01-VHDL13_DWLH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2633
ber01-VHDL13_DWLH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3309
ber01-VHDL13_DWLI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2503
ber01-VHDL13_DWLI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3602
ber01-VHDL13_DWMO_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2944
ber01-VHDL13_DWMO_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3501
ber01-VHDL13_DWMP_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2747
ber01-VHDL13_DWMP_140800_COR-2608140800-dsw--0-ia5 14-Aug-2026 08:39:45 2741
ber01-VHDL13_DWMP_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3467
ber01-VHDL13_DWOG_140300-2608140300-dsw--0-ia5 14-Aug-2026 03:00:28 3119
ber01-VHDL13_DWOG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3571
ber01-VHDL13_DWOG_141700-2608141700-dsw--0-ia5 14-Aug-2026 18:00:08 3511
ber01-VHDL13_DWOG_150300-2608150300-dsw--0-ia5 15-Aug-2026 03:00:09 4126
ber01-VHDL13_DWOG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 4183
ber01-VHDL13_DWOG_151700-2608151700-dsw--0-ia5 15-Aug-2026 18:00:06 3818
ber01-VHDL13_DWON_140058-2608140058-dsw--0-ia5 14-Aug-2026 00:58:58 3458
ber01-VHDL13_DWON_140238-2608140238-dsw--0-ia5 14-Aug-2026 02:38:38 3547
ber01-VHDL13_DWON_140529-2608140529-dsw--0-ia5 14-Aug-2026 05:29:50 3552
ber01-VHDL13_DWON_140601-2608140601-dsw--0-ia5 14-Aug-2026 06:01:34 3637
ber01-VHDL13_DWON_140641-2608140641-dsw--0-ia5 14-Aug-2026 06:41:29 3631
ber01-VHDL13_DWON_141458-2608141458-dsw--0-ia5 14-Aug-2026 14:58:38 3736
ber01-VHDL13_DWON_141505-2608141505-dsw--0-ia5 14-Aug-2026 15:05:34 3736
ber01-VHDL13_DWON_141746-2608141746-dsw--0-ia5 14-Aug-2026 17:46:28 3427
ber01-VHDL13_DWON_141940-2608141940-dsw--0-ia5 14-Aug-2026 19:40:25 3384
ber01-VHDL13_DWON_150135-2608150135-dsw--0-ia5 15-Aug-2026 01:35:11 3376
ber01-VHDL13_DWON_150147-2608150147-dsw--0-ia5 15-Aug-2026 01:47:20 3376
ber01-VHDL13_DWON_150347-2608150347-dsw--0-ia5 15-Aug-2026 03:47:08 3376
ber01-VHDL13_DWON_150508-2608150508-dsw--0-ia5 15-Aug-2026 05:08:34 3677
ber01-VHDL13_DWON_150607-2608150607-dsw--0-ia5 15-Aug-2026 06:07:54 3677
ber01-VHDL13_DWON_150821-2608150821-dsw--0-ia5 15-Aug-2026 08:21:14 3677
ber01-VHDL13_DWON_151438-2608151438-dsw--0-ia5 15-Aug-2026 14:38:59 3039
ber01-VHDL13_DWON_151739-2608151739-dsw--0-ia5 15-Aug-2026 17:40:00 2919
ber01-VHDL13_DWON_152156-2608152156-dsw--0-ia5 15-Aug-2026 21:56:34 2924
ber01-VHDL13_DWPG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2463
ber01-VHDL13_DWPG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3467
ber01-VHDL13_DWPH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 2435
ber01-VHDL13_DWPH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3030
ber01-VHDL13_DWSG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 3371
ber01-VHDL13_DWSG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3556
ber01-VHDL17_DWOG_141200-2608141200-dsw--0-ia5 14-Aug-2026 11:01:12 2867
ber01-VHDL17_DWOG_151200-2608151200-dsw--0-ia5 15-Aug-2026 11:02:58 2605
swis2-VHDL20_DWEG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1422
swis2-VHDL20_DWEG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1428
swis2-VHDL20_DWEG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1661
swis2-VHDL20_DWEG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2123
swis2-VHDL20_DWEG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1930
swis2-VHDL20_DWEG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1946
swis2-VHDL20_DWEG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 2039
swis2-VHDL20_DWEG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 2072
swis2-VHDL20_DWEG_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1742
swis2-VHDL20_DWEH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1489
swis2-VHDL20_DWEH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1489
swis2-VHDL20_DWEH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1600
swis2-VHDL20_DWEH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2033
swis2-VHDL20_DWEH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1653
swis2-VHDL20_DWEH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1701
swis2-VHDL20_DWEH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 1819
swis2-VHDL20_DWEH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1858
swis2-VHDL20_DWEH_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1289
swis2-VHDL20_DWEI_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1446
swis2-VHDL20_DWEI_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:01:20 1449
swis2-VHDL20_DWEI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1607
swis2-VHDL20_DWEI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2081
swis2-VHDL20_DWEI_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1894
swis2-VHDL20_DWEI_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1913
swis2-VHDL20_DWEI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 2031
swis2-VHDL20_DWEI_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 2056
swis2-VHDL20_DWEI_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1744
swis2-VHDL20_DWHG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:45:18 1221
swis2-VHDL20_DWHG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1247
swis2-VHDL20_DWHG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:45:06 1520
swis2-VHDL20_DWHG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 2144
swis2-VHDL20_DWHG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:47:07 2066
swis2-VHDL20_DWHG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 2051
swis2-VHDL20_DWHG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:45:45 2236
swis2-VHDL20_DWHG_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:38:51 2240
swis2-VHDL20_DWHG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:45:11 1444
swis2-VHDL20_DWHH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:45:18 1055
swis2-VHDL20_DWHH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1309
swis2-VHDL20_DWHH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:45:06 1352
swis2-VHDL20_DWHH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 1658
swis2-VHDL20_DWHH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:47:07 1463
swis2-VHDL20_DWHH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 1449
swis2-VHDL20_DWHH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:45:45 1727
swis2-VHDL20_DWHH_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:39:32 1731
swis2-VHDL20_DWHH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:45:11 1376
swis2-VHDL20_DWLG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1072
swis2-VHDL20_DWLG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1157
swis2-VHDL20_DWLG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1255
swis2-VHDL20_DWLG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1345
swis2-VHDL20_DWLG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1589
swis2-VHDL20_DWLG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1495
swis2-VHDL20_DWLG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1588
swis2-VHDL20_DWLG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1416
swis2-VHDL20_DWLH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1076
swis2-VHDL20_DWLH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1186
swis2-VHDL20_DWLH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1284
swis2-VHDL20_DWLH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1249
swis2-VHDL20_DWLH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1551
swis2-VHDL20_DWLH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1522
swis2-VHDL20_DWLH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1593
swis2-VHDL20_DWLH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1407
swis2-VHDL20_DWLI_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1074
swis2-VHDL20_DWLI_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1184
swis2-VHDL20_DWLI_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1282
swis2-VHDL20_DWLI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1405
swis2-VHDL20_DWLI_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1742
swis2-VHDL20_DWLI_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1723
swis2-VHDL20_DWLI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1814
swis2-VHDL20_DWLI_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1427
swis2-VHDL20_DWMO_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 973
swis2-VHDL20_DWMO_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:08 981
swis2-VHDL20_DWMO_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1418
swis2-VHDL20_DWMO_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1691
swis2-VHDL20_DWMO_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1609
swis2-VHDL20_DWMO_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:08 1632
swis2-VHDL20_DWMO_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1844
swis2-VHDL20_DWMO_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1731
swis2-VHDL20_DWMP_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1140
swis2-VHDL20_DWMP_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:08 1147
swis2-VHDL20_DWMP_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1503
swis2-VHDL20_DWMP_140800_COR-2608140800-dsw--0-ia5 14-Aug-2026 08:39:45 3002
swis2-VHDL20_DWMP_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1739
swis2-VHDL20_DWMP_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1675
swis2-VHDL20_DWMP_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:08 1697
swis2-VHDL20_DWMP_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1818
swis2-VHDL20_DWMP_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1719
swis2-VHDL20_DWPG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 1090
swis2-VHDL20_DWPG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 1195
swis2-VHDL20_DWPG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1293
swis2-VHDL20_DWPG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1254
swis2-VHDL20_DWPG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1505
swis2-VHDL20_DWPG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1580
swis2-VHDL20_DWPG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1667
swis2-VHDL20_DWPG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1345
swis2-VHDL20_DWPH_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:24 840
swis2-VHDL20_DWPH_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:14 950
swis2-VHDL20_DWPH_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:30 1048
swis2-VHDL20_DWPH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1012
swis2-VHDL20_DWPH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1256
swis2-VHDL20_DWPH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1262
swis2-VHDL20_DWPH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1366
swis2-VHDL20_DWPH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 959
swis2-VHDL20_DWSG_140200-2608140200-dsw--0-ia5 14-Aug-2026 02:30:14 1122
swis2-VHDL20_DWSG_140400-2608140400-dsw--0-ia5 14-Aug-2026 05:00:18 1345
swis2-VHDL20_DWSG_140800-2608140800-dsw--0-ia5 14-Aug-2026 08:30:15 1697
swis2-VHDL20_DWSG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:07 1692
swis2-VHDL20_DWSG_141800_COR-2608141800-dsw--0-ia5 14-Aug-2026 18:33:52 1603
swis2-VHDL20_DWSG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1501
swis2-VHDL20_DWSG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 1499
swis2-VHDL20_DWSG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1712
swis2-VHDL20_DWSG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1771
wst04-VHDL20_DWEG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 243239
wst04-VHDL20_DWEG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 243317
wst04-VHDL20_DWEG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:15 243952
wst04-VHDL20_DWEG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 246884
wst04-VHDL20_DWEG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 245951
wst04-VHDL20_DWEG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 245925
wst04-VHDL20_DWEG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:12 246735
wst04-VHDL20_DWEG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 243201
wst04-VHDL20_DWEG_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 242911
wst04-VHDL20_DWEH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 237085
wst04-VHDL20_DWEH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 237413
wst04-VHDL20_DWEH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 238161
wst04-VHDL20_DWEH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 244007
wst04-VHDL20_DWEH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 243238
wst04-VHDL20_DWEH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 243481
wst04-VHDL20_DWEH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:12 244284
wst04-VHDL20_DWEH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 242463
wst04-VHDL20_DWEH_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 241165
wst04-VHDL20_DWEI_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 347322
wst04-VHDL20_DWEI_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 347341
wst04-VHDL20_DWEI_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 348242
wst04-VHDL20_DWEI_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 354251
wst04-VHDL20_DWEI_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 353874
wst04-VHDL20_DWEI_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 353849
wst04-VHDL20_DWEI_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:18 354115
wst04-VHDL20_DWEI_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 350082
wst04-VHDL20_DWEI_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 349875
wst04-VHDL20_DWHG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:45:18 348585
wst04-VHDL20_DWHG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 348616
wst04-VHDL20_DWHG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:45:31 349746
wst04-VHDL20_DWHG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:45:21 342679
wst04-VHDL20_DWHG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:47:07 341821
wst04-VHDL20_DWHG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 341599
wst04-VHDL20_DWHG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:45:45 343437
wst04-VHDL20_DWHG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:45:21 350781
wst04-VHDL20_DWHH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:45:18 331707
wst04-VHDL20_DWHH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 232110
wst04-VHDL20_DWHH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:45:31 332912
wst04-VHDL20_DWHH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:45:21 334647
wst04-VHDL20_DWHH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:47:07 334506
wst04-VHDL20_DWHH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 232685
wst04-VHDL20_DWHH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:45:45 335912
wst04-VHDL20_DWHH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:45:21 335431
wst04-VHDL20_DWLG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 333614
wst04-VHDL20_DWLG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:44 333760
wst04-VHDL20_DWLG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 333989
wst04-VHDL20_DWLG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 342772
wst04-VHDL20_DWLG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 343836
wst04-VHDL20_DWLG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:44 343308
wst04-VHDL20_DWLG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 344272
wst04-VHDL20_DWLG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 339393
wst04-VHDL20_DWLH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 340589
wst04-VHDL20_DWLH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:44 340766
wst04-VHDL20_DWLH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 340986
wst04-VHDL20_DWLH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 349467
wst04-VHDL20_DWLH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 349873
wst04-VHDL20_DWLH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:44 349918
wst04-VHDL20_DWLH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 350870
wst04-VHDL20_DWLH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 347829
wst04-VHDL20_DWLI_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 337721
wst04-VHDL20_DWLI_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:44 337880
wst04-VHDL20_DWLI_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 382702
wst04-VHDL20_DWLI_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 342331
wst04-VHDL20_DWLI_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 343414
wst04-VHDL20_DWLI_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:44 343698
wst04-VHDL20_DWLI_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 388550
wst04-VHDL20_DWLI_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 340885
wst04-VHDL20_DWMO_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:20 457010
wst04-VHDL20_DWMO_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 456888
wst04-VHDL20_DWMO_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 458018
wst04-VHDL20_DWMO_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:19 357510
wst04-VHDL20_DWMO_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 464658
wst04-VHDL20_DWMO_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 464767
wst04-VHDL20_DWMO_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:18 464786
wst04-VHDL20_DWMO_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 354194
wst04-VHDL20_DWMP_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:20 571391
wst04-VHDL20_DWMP_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:18 571357
wst04-VHDL20_DWMP_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 469112
wst04-VHDL20_DWMP_140800_COR-2608140800-omedes-..> 14-Aug-2026 08:39:54 576059
wst04-VHDL20_DWMP_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 472433
wst04-VHDL20_DWMP_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 580939
wst04-VHDL20_DWMP_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 581284
wst04-VHDL20_DWMP_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:24 472434
wst04-VHDL20_DWMP_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 471257
wst04-VHDL20_DWPG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 239877
wst04-VHDL20_DWPG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:34 342305
wst04-VHDL20_DWPG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:53 387062
wst04-VHDL20_DWPG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:33 347981
wst04-VHDL20_DWPG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 244242
wst04-VHDL20_DWPG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:32 349704
wst04-VHDL20_DWPG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:48 394476
wst04-VHDL20_DWPG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 354743
wst04-VHDL20_DWPH_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:24 239575
wst04-VHDL20_DWPH_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:34 239793
wst04-VHDL20_DWPH_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:43 239945
wst04-VHDL20_DWPH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 241229
wst04-VHDL20_DWPH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 242307
wst04-VHDL20_DWPH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:32 242435
wst04-VHDL20_DWPH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 242548
wst04-VHDL20_DWPH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 283561
wst04-VHDL20_DWSG_140200-2608140200-omedes--0.pdf 14-Aug-2026 02:30:16 354097
wst04-VHDL20_DWSG_140400-2608140400-omedes--0.pdf 14-Aug-2026 05:00:14 354471
wst04-VHDL20_DWSG_140800-2608140800-omedes--0.pdf 14-Aug-2026 08:30:20 355813
wst04-VHDL20_DWSG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:33:54 355200
wst04-VHDL20_DWSG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 355223
wst04-VHDL20_DWSG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 354784
wst04-VHDL20_DWSG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:18 356040
wst04-VHDL20_DWSG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 353821