Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_090600 09-Nov-2026 14:32:06 3308
FPDL13_DWMZ_100600 10-Nov-2026 14:55:59 4395
SXDL31_DWAV_090810 09-Nov-2026 08:51:42 11093
SXDL31_DWAV_091810 09-Nov-2026 17:58:10 10230
SXDL31_DWAV_100810 10-Nov-2026 09:24:39 13180
SXDL31_DWAV_101810 10-Nov-2026 15:59:01 12347
SXDL31_DWAV_LATEST 10-Nov-2026 15:59:01 12347
SXDL33_DWAV_090000 09-Nov-2026 11:05:25 11352
SXDL33_DWAV_100000 10-Nov-2026 11:28:35 10981
SXDL33_DWAV_LATEST 10-Nov-2026 11:28:35 10981
ber01-FWDL39_DWMS_091200-2611091200-dsw--0-ia5 09-Nov-2026 12:14:03 1498
ber01-FWDL39_DWMS_101200-2611101200-dsw--0-ia5 10-Nov-2026 11:41:26 1268
ber01-VHDL13_DWEG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 3465
ber01-VHDL13_DWEG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:15 3107
ber01-VHDL13_DWEH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 3666
ber01-VHDL13_DWEH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:15 2903
ber01-VHDL13_DWEI_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 2668
ber01-VHDL13_DWEI_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:20 2454
ber01-VHDL13_DWHG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 3424
ber01-VHDL13_DWHG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 3448
ber01-VHDL13_DWHH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 2969
ber01-VHDL13_DWHH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 3617
ber01-VHDL13_DWLG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 2933
ber01-VHDL13_DWLG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 2976
ber01-VHDL13_DWLH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 2266
ber01-VHDL13_DWLH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 2518
ber01-VHDL13_DWLI_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 2572
ber01-VHDL13_DWLI_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 2772
ber01-VHDL13_DWMO_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 2700
ber01-VHDL13_DWMO_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:05 2751
ber01-VHDL13_DWMP_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 3237
ber01-VHDL13_DWMP_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:05 2913
ber01-VHDL13_DWOG_090300-2611090300-dsw--0-ia5 09-Nov-2026 04:00:07 4541
ber01-VHDL13_DWOG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 4690
ber01-VHDL13_DWOG_091700-2611091700-dsw--0-ia5 09-Nov-2026 19:00:08 4043
ber01-VHDL13_DWOG_100300-2611100300-dsw--0-ia5 10-Nov-2026 04:00:05 5232
ber01-VHDL13_DWOG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 4859
ber01-VHDL13_DWOG_100800_COR-2611100800-dsw--0-ia5 10-Nov-2026 13:17:05 4547
ber01-VHDL13_DWOG_101700-2611101700-dsw--0-ia5 10-Nov-2026 19:00:07 4395
ber01-VHDL13_DWON_082339-2611082339-dsw--0-ia5 08-Nov-2026 23:40:16 3499
ber01-VHDL13_DWON_090129-2611090129-dsw--0-ia5 09-Nov-2026 01:29:19 3499
ber01-VHDL13_DWON_090359-2611090359-dsw--0-ia5 09-Nov-2026 03:59:59 3728
ber01-VHDL13_DWON_090625-2611090625-dsw--0-ia5 09-Nov-2026 06:25:49 4369
ber01-VHDL13_DWON_090715-2611090715-dsw--0-ia5 09-Nov-2026 07:15:30 4558
ber01-VHDL13_DWON_090900-2611090900-dsw--0-ia5 09-Nov-2026 09:01:06 4416
ber01-VHDL13_DWON_090941-2611090941-dsw--0-ia5 09-Nov-2026 09:42:05 4416
ber01-VHDL13_DWON_091313-2611091313-dsw--0-ia5 09-Nov-2026 13:13:49 4550
ber01-VHDL13_DWON_091533-2611091533-dsw--0-ia5 09-Nov-2026 15:33:40 4460
ber01-VHDL13_DWON_091547-2611091547-dsw--0-ia5 09-Nov-2026 15:47:39 4460
ber01-VHDL13_DWON_091759-2611091759-dsw--0-ia5 09-Nov-2026 17:59:35 3894
ber01-VHDL13_DWON_091941-2611091941-dsw--0-ia5 09-Nov-2026 19:41:48 4598
ber01-VHDL13_DWON_092222-2611092222-dsw--0-ia5 09-Nov-2026 22:22:25 4600
ber01-VHDL13_DWON_100004-2611100004-dsw--0-ia5 10-Nov-2026 00:04:22 5222
ber01-VHDL13_DWON_100137-2611100137-dsw--0-ia5 10-Nov-2026 01:37:46 5152
ber01-VHDL13_DWON_100348-2611100348-dsw--0-ia5 10-Nov-2026 03:48:28 5024
ber01-VHDL13_DWON_100630-2611100630-dsw--0-ia5 10-Nov-2026 06:30:34 4995
ber01-VHDL13_DWON_100727-2611100727-dsw--0-ia5 10-Nov-2026 07:27:54 4652
ber01-VHDL13_DWON_101009-2611101009-dsw--0-ia5 10-Nov-2026 10:09:17 4652
ber01-VHDL13_DWON_101316-2611101316-dsw--0-ia5 10-Nov-2026 13:16:49 4421
ber01-VHDL13_DWON_101534-2611101534-dsw--0-ia5 10-Nov-2026 15:35:03 4067
ber01-VHDL13_DWON_101649-2611101649-dsw--0-ia5 10-Nov-2026 16:49:34 4067
ber01-VHDL13_DWON_101948-2611101948-dsw--0-ia5 10-Nov-2026 19:48:58 4504
ber01-VHDL13_DWPG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 2630
ber01-VHDL13_DWPG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 2473
ber01-VHDL13_DWPH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:02 2248
ber01-VHDL13_DWPH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:03 2879
ber01-VHDL13_DWSG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 3316
ber01-VHDL13_DWSG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:07 3640
ber01-VHDL17_DWOG_091200-2611091200-dsw--0-ia5 09-Nov-2026 12:45:43 4000
ber01-VHDL17_DWOG_101200-2611101200-dsw--0-ia5 10-Nov-2026 11:51:58 2704
swis2-VHDL20_DWEG_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1408
swis2-VHDL20_DWEG_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:01:05 1658
swis2-VHDL20_DWEG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 2188
swis2-VHDL20_DWEG_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:18 1956
swis2-VHDL20_DWEG_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:10 1760
swis2-VHDL20_DWEG_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:01:12 1673
swis2-VHDL20_DWEG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:07 1776
swis2-VHDL20_DWEG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1992
swis2-VHDL20_DWEH_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1294
swis2-VHDL20_DWEH_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:01:05 2036
swis2-VHDL20_DWEH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 2489
swis2-VHDL20_DWEH_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:18 2319
swis2-VHDL20_DWEH_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:10 1241
swis2-VHDL20_DWEH_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:01:12 1679
swis2-VHDL20_DWEH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 1636
swis2-VHDL20_DWEH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1863
swis2-VHDL20_DWEI_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1471
swis2-VHDL20_DWEI_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:01:05 1654
swis2-VHDL20_DWEI_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 1796
swis2-VHDL20_DWEI_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:18 1604
swis2-VHDL20_DWEI_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:10 1547
swis2-VHDL20_DWEI_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:01:12 1481
swis2-VHDL20_DWEI_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 1521
swis2-VHDL20_DWEI_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1883
swis2-VHDL20_DWHG_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:14 1704
swis2-VHDL20_DWHG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 2186
swis2-VHDL20_DWHG_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:45:08 2296
swis2-VHDL20_DWHG_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:15 1685
swis2-VHDL20_DWHG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 2421
swis2-VHDL20_DWHG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:45:08 2595
swis2-VHDL20_DWHH_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:45:15 1293
swis2-VHDL20_DWHH_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:14 1296
swis2-VHDL20_DWHH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1771
swis2-VHDL20_DWHH_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:45:08 1952
swis2-VHDL20_DWHH_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:45:18 1424
swis2-VHDL20_DWHH_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:15 1535
swis2-VHDL20_DWHH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:09 2492
swis2-VHDL20_DWHH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:45:08 2367
swis2-VHDL20_DWLG_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:33 1172
swis2-VHDL20_DWLG_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:18 1286
swis2-VHDL20_DWLG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1676
swis2-VHDL20_DWLG_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:31:16 1705
swis2-VHDL20_DWLG_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:25 1580
swis2-VHDL20_DWLG_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:14 1402
swis2-VHDL20_DWLG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:28 1731
swis2-VHDL20_DWLG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1846
swis2-VHDL20_DWLG_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:05:32 2183
swis2-VHDL20_DWLH_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:33 1132
swis2-VHDL20_DWLH_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:18 1195
swis2-VHDL20_DWLH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1358
swis2-VHDL20_DWLH_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:31:16 1309
swis2-VHDL20_DWLH_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:25 1141
swis2-VHDL20_DWLH_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:14 1086
swis2-VHDL20_DWLH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:28 1376
swis2-VHDL20_DWLH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1604
swis2-VHDL20_DWLH_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:05:08 1934
swis2-VHDL20_DWLI_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:33 1138
swis2-VHDL20_DWLI_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:18 1235
swis2-VHDL20_DWLI_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1470
swis2-VHDL20_DWLI_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:31:16 1355
swis2-VHDL20_DWLI_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:25 1253
swis2-VHDL20_DWLI_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:14 1267
swis2-VHDL20_DWLI_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:28 1606
swis2-VHDL20_DWLI_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1614
swis2-VHDL20_DWLI_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:06:33 1916
swis2-VHDL20_DWMO_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1507
swis2-VHDL20_DWMO_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:08 1475
swis2-VHDL20_DWMO_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 1632
swis2-VHDL20_DWMO_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:18 1535
swis2-VHDL20_DWMO_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:03 1467
swis2-VHDL20_DWMO_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:04 1475
swis2-VHDL20_DWMO_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:05 2011
swis2-VHDL20_DWMO_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1303
swis2-VHDL20_DWMP_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1980
swis2-VHDL20_DWMP_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:08 1927
swis2-VHDL20_DWMP_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 2165
swis2-VHDL20_DWMP_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:19 1846
swis2-VHDL20_DWMP_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:03 1618
swis2-VHDL20_DWMP_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:04 1629
swis2-VHDL20_DWMP_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:05 1959
swis2-VHDL20_DWMP_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1693
swis2-VHDL20_DWPG_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:33 1298
swis2-VHDL20_DWPG_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:18 1398
swis2-VHDL20_DWPG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1814
swis2-VHDL20_DWPG_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:31:16 1675
swis2-VHDL20_DWPG_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:25 1534
swis2-VHDL20_DWPG_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:15 1218
swis2-VHDL20_DWPG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:28 1475
swis2-VHDL20_DWPG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1501
swis2-VHDL20_DWPH_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:33 1324
swis2-VHDL20_DWPH_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:18 1375
swis2-VHDL20_DWPH_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:22 1512
swis2-VHDL20_DWPH_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:31:16 1506
swis2-VHDL20_DWPH_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:25 1296
swis2-VHDL20_DWPH_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:14 1256
swis2-VHDL20_DWPH_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:28 1535
swis2-VHDL20_DWPH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1587
swis2-VHDL20_DWSG_090200-2611090200-dsw--0-ia5 09-Nov-2026 03:30:05 1328
swis2-VHDL20_DWSG_090400-2611090400-dsw--0-ia5 09-Nov-2026 06:00:14 1535
swis2-VHDL20_DWSG_090800-2611090800-dsw--0-ia5 09-Nov-2026 09:30:04 1923
swis2-VHDL20_DWSG_091800-2611091800-dsw--0-ia5 09-Nov-2026 19:30:19 1841
swis2-VHDL20_DWSG_100200-2611100200-dsw--0-ia5 10-Nov-2026 03:30:03 1597
swis2-VHDL20_DWSG_100400-2611100400-dsw--0-ia5 10-Nov-2026 06:00:14 1715
swis2-VHDL20_DWSG_100800-2611100800-dsw--0-ia5 10-Nov-2026 09:30:07 2116
swis2-VHDL20_DWSG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:10 1534
wst04-VHDL20_DWEG_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:33 230294
wst04-VHDL20_DWEG_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:14 229770
wst04-VHDL20_DWEG_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:22 232655
wst04-VHDL20_DWEG_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:30:23 230610
wst04-VHDL20_DWEG_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:23 230746
wst04-VHDL20_DWEG_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:14 230013
wst04-VHDL20_DWEG_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:20 231417
wst04-VHDL20_DWEG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 236898
wst04-VHDL20_DWEH_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:25 230399
wst04-VHDL20_DWEH_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:14 230322
wst04-VHDL20_DWEH_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:22 230880
wst04-VHDL20_DWEH_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:30:19 227711
wst04-VHDL20_DWEH_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:23 228811
wst04-VHDL20_DWEH_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:15 228516
wst04-VHDL20_DWEH_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:20 229011
wst04-VHDL20_DWEH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:25 232975
wst04-VHDL20_DWEI_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:33 327121
wst04-VHDL20_DWEI_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:14 326832
wst04-VHDL20_DWEI_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:22 330956
wst04-VHDL20_DWEI_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:30:23 329753
wst04-VHDL20_DWEI_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:23 329040
wst04-VHDL20_DWEI_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:14 329199
wst04-VHDL20_DWEI_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:20 329684
wst04-VHDL20_DWEI_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:25 334389
wst04-VHDL20_DWHG_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:45:18 323960
wst04-VHDL20_DWHG_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:18 323027
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wst04-VHDL20_DWHG_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:45:18 322283
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wst04-VHDL20_DWHG_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:34 324261
wst04-VHDL20_DWHG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:45:13 325757
wst04-VHDL20_DWHH_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:45:18 314565
wst04-VHDL20_DWHH_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:24 221158
wst04-VHDL20_DWHH_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:50 313133
wst04-VHDL20_DWHH_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:45:13 314047
wst04-VHDL20_DWHH_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:45:18 311428
wst04-VHDL20_DWHH_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:23 220468
wst04-VHDL20_DWHH_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:34 314294
wst04-VHDL20_DWHH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:45:13 314248
wst04-VHDL20_DWLG_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:35 318019
wst04-VHDL20_DWLG_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:44 317975
wst04-VHDL20_DWLG_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:53 324424
wst04-VHDL20_DWLG_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:31:32 325135
wst04-VHDL20_DWLG_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:29 324011
wst04-VHDL20_DWLG_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:43 324092
wst04-VHDL20_DWLG_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:49 324775
wst04-VHDL20_DWLG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:37 321457
wst04-VHDL20_DWLG_101800_COR-2611101800-omedes-..> 10-Nov-2026 20:58:54 321896
wst04-VHDL20_DWLH_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:33 323632
wst04-VHDL20_DWLH_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:44 323517
wst04-VHDL20_DWLH_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:53 323985
wst04-VHDL20_DWLH_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:31:22 324306
wst04-VHDL20_DWLH_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:25 322597
wst04-VHDL20_DWLH_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:43 322678
wst04-VHDL20_DWLH_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:49 324090
wst04-VHDL20_DWLH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 316317
wst04-VHDL20_DWLH_101800_COR-2611101800-omedes-..> 10-Nov-2026 20:57:45 316506
wst04-VHDL20_DWLI_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:35 326876
wst04-VHDL20_DWLI_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:44 326874
wst04-VHDL20_DWLI_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:53 371999
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wst04-VHDL20_DWLI_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:25 325993
wst04-VHDL20_DWLI_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:43 326100
wst04-VHDL20_DWLI_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:59 371930
wst04-VHDL20_DWLI_101800-2611101800-omedes--0.pdf 10-Nov-2026 20:59:35 316548
wst04-VHDL20_DWMO_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:25 435082
wst04-VHDL20_DWMO_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:18 435315
wst04-VHDL20_DWMO_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:22 436502
wst04-VHDL20_DWMO_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:30:23 435470
wst04-VHDL20_DWMO_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:14 435997
wst04-VHDL20_DWMO_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:19 436242
wst04-VHDL20_DWMO_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:28 435926
wst04-VHDL20_DWMO_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:14 441780
wst04-VHDL20_DWMP_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:25 539562
wst04-VHDL20_DWMP_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:18 539654
wst04-VHDL20_DWMP_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:40 551725
wst04-VHDL20_DWMP_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:30:23 549048
wst04-VHDL20_DWMP_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:14 549110
wst04-VHDL20_DWMP_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:19 548821
wst04-VHDL20_DWMP_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:28 549744
wst04-VHDL20_DWMP_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 557505
wst04-VHDL20_DWPG_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:33 230488
wst04-VHDL20_DWPG_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:34 322724
wst04-VHDL20_DWPG_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:53 366047
wst04-VHDL20_DWPG_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:31:22 321762
wst04-VHDL20_DWPG_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:29 229431
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wst04-VHDL20_DWPG_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:49 365735
wst04-VHDL20_DWPG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 319306
wst04-VHDL20_DWPH_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:33 228172
wst04-VHDL20_DWPH_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:34 228095
wst04-VHDL20_DWPH_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:53 226316
wst04-VHDL20_DWPH_091800-2611091800-omedes--0.pdf 09-Nov-2026 19:31:22 226660
wst04-VHDL20_DWPH_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:25 225552
wst04-VHDL20_DWPH_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:33 226326
wst04-VHDL20_DWPH_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:49 226908
wst04-VHDL20_DWPH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 231519
wst04-VHDL20_DWSG_090200-2611090200-omedes--0.pdf 09-Nov-2026 03:30:25 339960
wst04-VHDL20_DWSG_090400-2611090400-omedes--0.pdf 09-Nov-2026 06:00:14 340495
wst04-VHDL20_DWSG_090800-2611090800-omedes--0.pdf 09-Nov-2026 09:30:22 338695
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wst04-VHDL20_DWSG_100200-2611100200-omedes--0.pdf 10-Nov-2026 03:30:14 337686
wst04-VHDL20_DWSG_100400-2611100400-omedes--0.pdf 10-Nov-2026 06:00:19 338565
wst04-VHDL20_DWSG_100800-2611100800-omedes--0.pdf 10-Nov-2026 09:30:15 339182
wst04-VHDL20_DWSG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 342559