Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Jan-2026 15:00:16 7018
FPDL13_DWMZ_230600 23-Jan-2026 13:03:30 4946
SXDL31_DWAV_211800 21-Jan-2026 16:50:20 11073
SXDL31_DWAV_220800 22-Jan-2026 09:14:09 9707
SXDL31_DWAV_221800 22-Jan-2026 16:47:03 11662
SXDL31_DWAV_230800 23-Jan-2026 08:26:25 8596
SXDL31_DWAV_LATEST 23-Jan-2026 08:26:25 8596
SXDL33_DWAV_220000 22-Jan-2026 11:38:24 9090
SXDL33_DWAV_230000 23-Jan-2026 10:31:59 8506
SXDL33_DWAV_LATEST 23-Jan-2026 10:31:59 8506
ber01-FWDL39_DWMS_221230-2601221230-dsw--0-ia5 22-Jan-2026 12:42:06 1757
ber01-FWDL39_DWMS_231230-2601231230-dsw--0-ia5 23-Jan-2026 11:59:31 1712
ber01-VHDL13_DWEH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:28:17 3030
ber01-VHDL13_DWEH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:28:16 3335
ber01-VHDL13_DWEH_220400-2601220400-dsw--0-ia5 22-Jan-2026 05:58:16 3324
ber01-VHDL13_DWEH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:28:17 3068
ber01-VHDL13_DWEH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:28:17 3002
ber01-VHDL13_DWEH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:28:31 3138
ber01-VHDL13_DWEH_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:16 2991
ber01-VHDL13_DWEH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:21 3467
ber01-VHDL13_DWHG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 3900
ber01-VHDL13_DWHG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 4328
ber01-VHDL13_DWHG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 4355
ber01-VHDL13_DWHG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 4788
ber01-VHDL13_DWHG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 4303
ber01-VHDL13_DWHG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 4349
ber01-VHDL13_DWHG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:01:51 4278
ber01-VHDL13_DWHG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 5154
ber01-VHDL13_DWHG_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:35:16 5101
ber01-VHDL13_DWHH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 3629
ber01-VHDL13_DWHH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 4041
ber01-VHDL13_DWHH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 4058
ber01-VHDL13_DWHH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 4166
ber01-VHDL13_DWHH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 3441
ber01-VHDL13_DWHH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 3301
ber01-VHDL13_DWHH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3293
ber01-VHDL13_DWHH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3595
ber01-VHDL13_DWHH_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:37:59 3608
ber01-VHDL13_DWLG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 2394
ber01-VHDL13_DWLG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 2219
ber01-VHDL13_DWLG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 2111
ber01-VHDL13_DWLG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 2148
ber01-VHDL13_DWLG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 1871
ber01-VHDL13_DWLG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 1910
ber01-VHDL13_DWLG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2193
ber01-VHDL13_DWLG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2614
ber01-VHDL13_DWLH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 1834
ber01-VHDL13_DWLH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 2061
ber01-VHDL13_DWLH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 2024
ber01-VHDL13_DWLH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 2017
ber01-VHDL13_DWLH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 1738
ber01-VHDL13_DWLH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 1835
ber01-VHDL13_DWLH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 1922
ber01-VHDL13_DWLH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2354
ber01-VHDL13_DWLI_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 1712
ber01-VHDL13_DWLI_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 1935
ber01-VHDL13_DWLI_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 1956
ber01-VHDL13_DWLI_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 2023
ber01-VHDL13_DWLI_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 1774
ber01-VHDL13_DWLI_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 1952
ber01-VHDL13_DWLI_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2299
ber01-VHDL13_DWLI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2611
ber01-VHDL13_DWMG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 2810
ber01-VHDL13_DWMG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:01 3096
ber01-VHDL13_DWMG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:08 3107
ber01-VHDL13_DWMG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 3026
ber01-VHDL13_DWMG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:02 2687
ber01-VHDL13_DWMG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:02 2862
ber01-VHDL13_DWMG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:01 2862
ber01-VHDL13_DWMG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3210
ber01-VHDL13_DWMO_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 3012
ber01-VHDL13_DWMO_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 3359
ber01-VHDL13_DWMO_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 3359
ber01-VHDL13_DWMO_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:09 3388
ber01-VHDL13_DWMO_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:02 2918
ber01-VHDL13_DWMO_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:02 3114
ber01-VHDL13_DWMO_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3114
ber01-VHDL13_DWMO_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 3109
ber01-VHDL13_DWMP_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 2917
ber01-VHDL13_DWMP_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:01 3150
ber01-VHDL13_DWMP_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:08 3150
ber01-VHDL13_DWMP_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 3078
ber01-VHDL13_DWMP_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:02 2632
ber01-VHDL13_DWMP_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:02 2909
ber01-VHDL13_DWMP_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:01 2909
ber01-VHDL13_DWMP_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2994
ber01-VHDL13_DWOG_211700-2601211700-dsw--0-ia5 21-Jan-2026 19:00:06 4804
ber01-VHDL13_DWOG_220300-2601220300-dsw--0-ia5 22-Jan-2026 04:00:01 4493
ber01-VHDL13_DWOG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 4681
ber01-VHDL13_DWOG_220800_COR-2601220800-dsw--0-ia5 22-Jan-2026 10:02:56 4532
ber01-VHDL13_DWOG_221700-2601221700-dsw--0-ia5 22-Jan-2026 19:00:02 4406
ber01-VHDL13_DWOG_230300-2601230300-dsw--0-ia5 23-Jan-2026 04:00:01 5345
ber01-VHDL13_DWOG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:01 5181
ber01-VHDL13_DWOH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:28:21 3011
ber01-VHDL13_DWOH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:28:16 2989
ber01-VHDL13_DWOH_220400-2601220400-dsw--0-ia5 22-Jan-2026 05:58:16 3009
ber01-VHDL13_DWOH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:28:21 2700
ber01-VHDL13_DWOH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:28:23 2570
ber01-VHDL13_DWOH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:28:29 2598
ber01-VHDL13_DWOH_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:16 2722
ber01-VHDL13_DWOH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:17 2856
ber01-VHDL13_DWOI_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:28:17 2735
ber01-VHDL13_DWOI_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:28:16 3037
ber01-VHDL13_DWOI_220400-2601220400-dsw--0-ia5 22-Jan-2026 05:58:22 2968
ber01-VHDL13_DWOI_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:28:11 2711
ber01-VHDL13_DWOI_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:28:17 2668
ber01-VHDL13_DWOI_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:28:31 2603
ber01-VHDL13_DWOI_230400-2601230400-dsw--0-ia5 23-Jan-2026 05:58:22 2659
ber01-VHDL13_DWOI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:28:17 2777
ber01-VHDL13_DWOI_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 12:02:51 2844
ber01-VHDL13_DWON_211513-2601211513-dsw--0-ia5 21-Jan-2026 15:13:21 4144
ber01-VHDL13_DWON_211734-2601211734-dsw--0-ia5 21-Jan-2026 17:35:04 4148
ber01-VHDL13_DWON_220010-2601220010-dsw--0-ia5 22-Jan-2026 00:11:03 4635
ber01-VHDL13_DWON_220200-2601220200-dsw--0-ia5 22-Jan-2026 02:00:45 4648
ber01-VHDL13_DWON_220434-2601220434-dsw--0-ia5 22-Jan-2026 04:34:07 4648
ber01-VHDL13_DWON_220621-2601220621-dsw--0-ia5 22-Jan-2026 06:21:33 4327
ber01-VHDL13_DWON_220650-2601220650-dsw--0-ia5 22-Jan-2026 06:50:17 4328
ber01-VHDL13_DWON_220925-2601220925-dsw--0-ia5 22-Jan-2026 09:25:17 4328
ber01-VHDL13_DWON_220930-2601220930-dsw--0-ia5 22-Jan-2026 09:30:42 4328
ber01-VHDL13_DWON_221001-2601221001-dsw--0-ia5 22-Jan-2026 10:01:22 4328
ber01-VHDL13_DWON_221545-2601221545-dsw--0-ia5 22-Jan-2026 15:45:44 3532
ber01-VHDL13_DWON_221732-2601221732-dsw--0-ia5 22-Jan-2026 17:32:47 3806
ber01-VHDL13_DWON_230353-2601230353-dsw--0-ia5 23-Jan-2026 03:53:07 3863
ber01-VHDL13_DWON_230602-2601230602-dsw--0-ia5 23-Jan-2026 06:02:32 3958
ber01-VHDL13_DWON_230709-2601230709-dsw--0-ia5 23-Jan-2026 07:10:08 3958
ber01-VHDL13_DWON_231229-2601231229-dsw--0-ia5 23-Jan-2026 12:30:02 4133
ber01-VHDL13_DWON_231421-2601231421-dsw--0-ia5 23-Jan-2026 14:21:47 3581
ber01-VHDL13_DWPG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 1682
ber01-VHDL13_DWPG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 1906
ber01-VHDL13_DWPG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 1887
ber01-VHDL13_DWPG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 1821
ber01-VHDL13_DWPG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 1758
ber01-VHDL13_DWPG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 1877
ber01-VHDL13_DWPG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 1929
ber01-VHDL13_DWPG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2637
ber01-VHDL13_DWPH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 3311
ber01-VHDL13_DWPH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:09 3376
ber01-VHDL13_DWPH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 3316
ber01-VHDL13_DWPH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 2682
ber01-VHDL13_DWPH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:10 2328
ber01-VHDL13_DWPH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:16 2412
ber01-VHDL13_DWPH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2444
ber01-VHDL13_DWPH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:08 2902
ber01-VHDL13_DWSG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:30:10 3392
ber01-VHDL13_DWSG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:30:01 3315
ber01-VHDL13_DWSG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:08 3386
ber01-VHDL13_DWSG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:30:08 3336
ber01-VHDL13_DWSG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:30:02 2793
ber01-VHDL13_DWSG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:30:02 3272
ber01-VHDL13_DWSG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 2972
ber01-VHDL13_DWSG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:30:01 2721
ber01-VHDL17_DWOG_221200-2601221200-dsw--0-ia5 22-Jan-2026 12:35:17 3527
ber01-VHDL17_DWOG_231200-2601231200-dsw--0-ia5 23-Jan-2026 12:17:47 2715
swis2-VHDL20_DWEG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3385
swis2-VHDL20_DWEG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3389
swis2-VHDL20_DWEG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:06 3422
swis2-VHDL20_DWEG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 3422
swis2-VHDL20_DWEG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:08 3050
swis2-VHDL20_DWEG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:08 2994
swis2-VHDL20_DWEG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3128
swis2-VHDL20_DWEG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3550
swis2-VHDL20_DWEH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3496
swis2-VHDL20_DWEH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3765
swis2-VHDL20_DWEH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:06 3777
swis2-VHDL20_DWEH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 3862
swis2-VHDL20_DWEH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:08 3635
swis2-VHDL20_DWEH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:08 3696
swis2-VHDL20_DWEH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3455
swis2-VHDL20_DWEH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 4160
swis2-VHDL20_DWEI_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3135
swis2-VHDL20_DWEI_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3438
swis2-VHDL20_DWEI_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:06 3358
swis2-VHDL20_DWEI_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 3435
swis2-VHDL20_DWEI_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:08 3241
swis2-VHDL20_DWEI_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 3090
swis2-VHDL20_DWEI_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:06 3113
swis2-VHDL20_DWEI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3552
swis2-VHDL20_DWEI_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 12:04:12 3619
swis2-VHDL20_DWHG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 4083
swis2-VHDL20_DWHG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:04 4514
swis2-VHDL20_DWHG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 4538
swis2-VHDL20_DWHG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 5655
swis2-VHDL20_DWHG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:04 4486
swis2-VHDL20_DWHG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 4535
swis2-VHDL20_DWHG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 4532
swis2-VHDL20_DWHG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 6208
swis2-VHDL20_DWHG_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:38:38 6152
swis2-VHDL20_DWHH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3815
swis2-VHDL20_DWHH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:04 4227
swis2-VHDL20_DWHH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:06 4244
swis2-VHDL20_DWHH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 4823
swis2-VHDL20_DWHH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:04 3627
swis2-VHDL20_DWHH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 3487
swis2-VHDL20_DWHH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:07 3479
swis2-VHDL20_DWHH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 4286
swis2-VHDL20_DWHH_230800_COR-2601230800-dsw--0-ia5 23-Jan-2026 11:39:12 4296
swis2-VHDL20_DWLG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 2803
swis2-VHDL20_DWLG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 2562
swis2-VHDL20_DWLG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:12 2512
swis2-VHDL20_DWLG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 2694
swis2-VHDL20_DWLG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 2272
swis2-VHDL20_DWLG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 2292
swis2-VHDL20_DWLG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2534
swis2-VHDL20_DWLG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:05 3147
swis2-VHDL20_DWLH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 2250
swis2-VHDL20_DWLH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 2410
swis2-VHDL20_DWLH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:12 2431
swis2-VHDL20_DWLH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 2573
swis2-VHDL20_DWLH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 2145
swis2-VHDL20_DWLH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 2225
swis2-VHDL20_DWLH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2270
swis2-VHDL20_DWLH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:05 2898
swis2-VHDL20_DWLI_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 2123
swis2-VHDL20_DWLI_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 2280
swis2-VHDL20_DWLI_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:12 2358
swis2-VHDL20_DWLI_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 2568
swis2-VHDL20_DWLI_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 2176
swis2-VHDL20_DWLI_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 2336
swis2-VHDL20_DWLI_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2641
swis2-VHDL20_DWLI_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3143
swis2-VHDL20_DWMG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3244
swis2-VHDL20_DWMG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3525
swis2-VHDL20_DWMG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:02 3534
swis2-VHDL20_DWMG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 3798
swis2-VHDL20_DWMG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 3246
swis2-VHDL20_DWMG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:08 3418
swis2-VHDL20_DWMG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:01 3288
swis2-VHDL20_DWMG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3985
swis2-VHDL20_DWMO_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3453
swis2-VHDL20_DWMO_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3794
swis2-VHDL20_DWMO_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:02 3790
swis2-VHDL20_DWMO_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 4149
swis2-VHDL20_DWMO_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 3482
swis2-VHDL20_DWMO_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 3673
swis2-VHDL20_DWMO_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:01 3545
swis2-VHDL20_DWMO_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3886
swis2-VHDL20_DWMP_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3336
swis2-VHDL20_DWMP_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3584
swis2-VHDL20_DWMP_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:06 3575
swis2-VHDL20_DWMP_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 3726
swis2-VHDL20_DWMP_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 3058
swis2-VHDL20_DWMP_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 3337
swis2-VHDL20_DWMP_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:01 3334
swis2-VHDL20_DWMP_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3767
swis2-VHDL20_DWPG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 2138
swis2-VHDL20_DWPG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 2235
swis2-VHDL20_DWPG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:12 2210
swis2-VHDL20_DWPG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 2277
swis2-VHDL20_DWPG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 2214
swis2-VHDL20_DWPG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 2203
swis2-VHDL20_DWPG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2255
swis2-VHDL20_DWPG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3417
swis2-VHDL20_DWPH_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:06 3874
swis2-VHDL20_DWPH_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:06 3811
swis2-VHDL20_DWPH_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:00:12 3641
swis2-VHDL20_DWPH_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:02 3138
swis2-VHDL20_DWPH_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 2784
swis2-VHDL20_DWPH_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:06 2737
swis2-VHDL20_DWPH_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:00:17 2772
swis2-VHDL20_DWPH_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:07 3682
swis2-VHDL20_DWSG_211800-2601211800-dsw--0-ia5 21-Jan-2026 19:45:04 3764
swis2-VHDL20_DWSG_220200-2601220200-dsw--0-ia5 22-Jan-2026 03:45:04 3716
swis2-VHDL20_DWSG_220400-2601220400-dsw--0-ia5 22-Jan-2026 06:15:06 4016
swis2-VHDL20_DWSG_220800-2601220800-dsw--0-ia5 22-Jan-2026 09:45:06 4166
swis2-VHDL20_DWSG_221300-2601221300-dsw--0-ia5 22-Jan-2026 14:45:09 3959
swis2-VHDL20_DWSG_221800-2601221800-dsw--0-ia5 22-Jan-2026 19:45:06 3204
swis2-VHDL20_DWSG_230200-2601230200-dsw--0-ia5 23-Jan-2026 03:45:01 3766
swis2-VHDL20_DWSG_230400-2601230400-dsw--0-ia5 23-Jan-2026 06:15:01 3498
swis2-VHDL20_DWSG_230800-2601230800-dsw--0-ia5 23-Jan-2026 09:45:01 3448
swis2-VHDL20_DWSG_231300-2601231300-dsw--0-ia5 23-Jan-2026 14:45:38 3250
wst04-VHDL20_DWEG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:22 226885
wst04-VHDL20_DWEG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:12 227451
wst04-VHDL20_DWEG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:18 226989
wst04-VHDL20_DWEG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:16 231822
wst04-VHDL20_DWEG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:17 229966
wst04-VHDL20_DWEG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:28 230625
wst04-VHDL20_DWEG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:27 230266
wst04-VHDL20_DWEG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 233760
wst04-VHDL20_DWEH_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:16 224278
wst04-VHDL20_DWEH_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:16 226098
wst04-VHDL20_DWEH_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:28 225851
wst04-VHDL20_DWEH_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:16 233507
wst04-VHDL20_DWEH_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:13 232949
wst04-VHDL20_DWEH_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:16 234258
wst04-VHDL20_DWEH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:23 233488
wst04-VHDL20_DWEH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 232809
wst04-VHDL20_DWEI_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:22 317607
wst04-VHDL20_DWEI_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:16 318007
wst04-VHDL20_DWEI_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:28 318153
wst04-VHDL20_DWEI_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:12 328774
wst04-VHDL20_DWEI_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:17 328159
wst04-VHDL20_DWEI_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:22 328612
wst04-VHDL20_DWEI_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:27 328645
wst04-VHDL20_DWEI_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:17 331122
wst04-VHDL20_DWHG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:12 299945
wst04-VHDL20_DWHG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:12 300830
wst04-VHDL20_DWHG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:12 300825
wst04-VHDL20_DWHG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:12 308491
wst04-VHDL20_DWHG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:13 306498
wst04-VHDL20_DWHG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:12 306664
wst04-VHDL20_DWHG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:11 307385
wst04-VHDL20_DWHG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:13 312001
wst04-VHDL20_DWHG_230800_COR-2601230800-omedes-..> 23-Jan-2026 11:32:32 311944
wst04-VHDL20_DWHH_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:12 292973
wst04-VHDL20_DWHH_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:12 293413
wst04-VHDL20_DWHH_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:12 293382
wst04-VHDL20_DWHH_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:12 294502
wst04-VHDL20_DWHH_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:13 292867
wst04-VHDL20_DWHH_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:12 292465
wst04-VHDL20_DWHH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:11 292511
wst04-VHDL20_DWHH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:13 292687
wst04-VHDL20_DWHH_230800_COR-2601230800-omedes-..> 23-Jan-2026 11:34:43 292658
wst04-VHDL20_DWLG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:32 303212
wst04-VHDL20_DWLG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:31 302658
wst04-VHDL20_DWLG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:41 303330
wst04-VHDL20_DWLG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:42 302428
wst04-VHDL20_DWLG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:32 301455
wst04-VHDL20_DWLG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:32 301554
wst04-VHDL20_DWLG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:43 300930
wst04-VHDL20_DWLG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:41 309382
wst04-VHDL20_DWLH_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:26 297558
wst04-VHDL20_DWLH_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:31 297748
wst04-VHDL20_DWLH_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:41 298504
wst04-VHDL20_DWLH_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:36 304133
wst04-VHDL20_DWLH_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:32 303068
wst04-VHDL20_DWLH_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:26 303511
wst04-VHDL20_DWLH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:41 302445
wst04-VHDL20_DWLH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:37 298390
wst04-VHDL20_DWLI_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:32 306357
wst04-VHDL20_DWLI_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:27 306525
wst04-VHDL20_DWLI_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:47 307291
wst04-VHDL20_DWLI_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:32 315929
wst04-VHDL20_DWLI_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:28 314846
wst04-VHDL20_DWLI_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:32 315193
wst04-VHDL20_DWLI_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:47 314062
wst04-VHDL20_DWLI_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:41 316825
wst04-VHDL20_DWMG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:16 519321
wst04-VHDL20_DWMG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:21 519855
wst04-VHDL20_DWMG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:22 520514
wst04-VHDL20_DWMG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:26 537975
wst04-VHDL20_DWMG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:21 536774
wst04-VHDL20_DWMG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:16 536921
wst04-VHDL20_DWMG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:17 536702
wst04-VHDL20_DWMG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:27 539717
wst04-VHDL20_DWMO_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:12 412057
wst04-VHDL20_DWMO_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:21 412999
wst04-VHDL20_DWMO_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:16 413472
wst04-VHDL20_DWMO_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:26 426504
wst04-VHDL20_DWMO_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:17 425649
wst04-VHDL20_DWMO_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:12 425591
wst04-VHDL20_DWMO_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:17 426093
wst04-VHDL20_DWMO_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:27 426280
wst04-VHDL20_DWMP_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:22 542080
wst04-VHDL20_DWMP_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:21 541434
wst04-VHDL20_DWMP_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:22 542497
wst04-VHDL20_DWMP_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:26 563429
wst04-VHDL20_DWMP_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:21 562002
wst04-VHDL20_DWMP_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:22 560742
wst04-VHDL20_DWMP_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:21 561756
wst04-VHDL20_DWMP_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:31 565021
wst04-VHDL20_DWPG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:32 297594
wst04-VHDL20_DWPG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:31 297426
wst04-VHDL20_DWPG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:32 297713
wst04-VHDL20_DWPG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:36 351371
wst04-VHDL20_DWPG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:32 306051
wst04-VHDL20_DWPG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:32 306059
wst04-VHDL20_DWPG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:31 305601
wst04-VHDL20_DWPG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:37 347102
wst04-VHDL20_DWPH_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:26 265063
wst04-VHDL20_DWPH_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:27 219934
wst04-VHDL20_DWPH_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:00:32 219106
wst04-VHDL20_DWPH_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:32 264982
wst04-VHDL20_DWPH_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:28 263792
wst04-VHDL20_DWPH_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:26 219434
wst04-VHDL20_DWPH_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:00:31 219131
wst04-VHDL20_DWPH_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:31 265287
wst04-VHDL20_DWSG_211800-2601211800-omedes--0.pdf 21-Jan-2026 19:45:12 330268
wst04-VHDL20_DWSG_220200-2601220200-omedes--0.pdf 22-Jan-2026 03:45:12 330420
wst04-VHDL20_DWSG_220400-2601220400-omedes--0.pdf 22-Jan-2026 06:15:16 331644
wst04-VHDL20_DWSG_220800-2601220800-omedes--0.pdf 22-Jan-2026 09:45:12 345982
wst04-VHDL20_DWSG_221300-2601221300-omedes--0.pdf 22-Jan-2026 14:45:11 345543
wst04-VHDL20_DWSG_221800-2601221800-omedes--0.pdf 22-Jan-2026 19:45:13 345408
wst04-VHDL20_DWSG_230200-2601230200-omedes--0.pdf 23-Jan-2026 03:45:12 345836
wst04-VHDL20_DWSG_230400-2601230400-omedes--0.pdf 23-Jan-2026 06:15:11 344988
wst04-VHDL20_DWSG_230800-2601230800-omedes--0.pdf 23-Jan-2026 09:45:11 337623
wst04-VHDL20_DWSG_231300-2601231300-omedes--0.pdf 23-Jan-2026 14:45:38 337808