Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Apr-2026 13:26:39 14738
FPDL13_DWMZ_060600 06-Apr-2026 12:49:00 2833
SXDL31_DWAV_051800 05-Apr-2026 16:56:03 8977
SXDL31_DWAV_060800 06-Apr-2026 06:41:54 6608
SXDL31_DWAV_061800 06-Apr-2026 15:45:00 8282
SXDL31_DWAV_070800 07-Apr-2026 07:18:29 9040
SXDL31_DWAV_LATEST 07-Apr-2026 07:18:29 9040
SXDL33_DWAV_050000 05-Apr-2026 09:44:10 9979
SXDL33_DWAV_060000 06-Apr-2026 09:20:59 8035
SXDL33_DWAV_LATEST 06-Apr-2026 09:20:59 8035
ber01-FWDL39_DWMS_051230-2604051230-dsw--0-ia5 05-Apr-2026 10:52:31 2156
ber01-FWDL39_DWMS_061230-2604061230-dsw--0-ia5 06-Apr-2026 12:04:31 1749
ber01-VHDL13_DWEH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:13 1899
ber01-VHDL13_DWEH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:11 2235
ber01-VHDL13_DWEH_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:11 2352
ber01-VHDL13_DWEH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:17 2335
ber01-VHDL13_DWEH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:28:12 2129
ber01-VHDL13_DWEH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:28:16 2500
ber01-VHDL13_DWEH_070400-2604070400-dsw--0-ia5 07-Apr-2026 04:58:17 2384
ber01-VHDL13_DWEH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:17 2275
ber01-VHDL13_DWHG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 3280
ber01-VHDL13_DWHG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2936
ber01-VHDL13_DWHG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3026
ber01-VHDL13_DWHG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2947
ber01-VHDL13_DWHG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:08 2502
ber01-VHDL13_DWHG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:07 2764
ber01-VHDL13_DWHG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:13 2738
ber01-VHDL13_DWHG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2358
ber01-VHDL13_DWHH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 3455
ber01-VHDL13_DWHH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 3075
ber01-VHDL13_DWHH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3089
ber01-VHDL13_DWHH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2914
ber01-VHDL13_DWHH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:08 2324
ber01-VHDL13_DWHH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:07 2533
ber01-VHDL13_DWHH_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:13 2541
ber01-VHDL13_DWHH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2445
ber01-VHDL13_DWLG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2333
ber01-VHDL13_DWLG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2513
ber01-VHDL13_DWLG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2583
ber01-VHDL13_DWLG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2339
ber01-VHDL13_DWLG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 1925
ber01-VHDL13_DWLG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2047
ber01-VHDL13_DWLG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:01 2251
ber01-VHDL13_DWLG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2182
ber01-VHDL13_DWLH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2381
ber01-VHDL13_DWLH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2583
ber01-VHDL13_DWLH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2562
ber01-VHDL13_DWLH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2464
ber01-VHDL13_DWLH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 1837
ber01-VHDL13_DWLH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 1931
ber01-VHDL13_DWLH_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:01 2067
ber01-VHDL13_DWLH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2017
ber01-VHDL13_DWLI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 1881
ber01-VHDL13_DWLI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 1979
ber01-VHDL13_DWLI_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 1840
ber01-VHDL13_DWLI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 1908
ber01-VHDL13_DWLI_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 1676
ber01-VHDL13_DWLI_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 1815
ber01-VHDL13_DWLI_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:01 1917
ber01-VHDL13_DWLI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 1902
ber01-VHDL13_DWMG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2861
ber01-VHDL13_DWMG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2490
ber01-VHDL13_DWMG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2557
ber01-VHDL13_DWMG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2621
ber01-VHDL13_DWMG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 2443
ber01-VHDL13_DWMG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2364
ber01-VHDL13_DWMG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:07 2242
ber01-VHDL13_DWMG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2159
ber01-VHDL13_DWMO_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2166
ber01-VHDL13_DWMO_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2131
ber01-VHDL13_DWMO_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2151
ber01-VHDL13_DWMO_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2360
ber01-VHDL13_DWMO_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 2070
ber01-VHDL13_DWMO_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2232
ber01-VHDL13_DWMO_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:07 2240
ber01-VHDL13_DWMO_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2381
ber01-VHDL13_DWMP_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2983
ber01-VHDL13_DWMP_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2662
ber01-VHDL13_DWMP_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2731
ber01-VHDL13_DWMP_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2683
ber01-VHDL13_DWMP_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 2414
ber01-VHDL13_DWMP_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2423
ber01-VHDL13_DWMP_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:07 2383
ber01-VHDL13_DWMP_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2329
ber01-VHDL13_DWOG_051700-2604051700-dsw--0-ia5 05-Apr-2026 18:00:02 3876
ber01-VHDL13_DWOG_060300-2604060300-dsw--0-ia5 06-Apr-2026 03:00:02 3712
ber01-VHDL13_DWOG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 3714
ber01-VHDL13_DWOG_061700-2604061700-dsw--0-ia5 06-Apr-2026 18:00:02 3339
ber01-VHDL13_DWOG_061700_COR-2604061700-dsw--0-ia5 06-Apr-2026 21:24:13 3451
ber01-VHDL13_DWOG_070300-2604070300-dsw--0-ia5 07-Apr-2026 03:00:02 3620
ber01-VHDL13_DWOG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 3308
ber01-VHDL13_DWOH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1823
ber01-VHDL13_DWOH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:11 2103
ber01-VHDL13_DWOH_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:17 2190
ber01-VHDL13_DWOH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:11 2193
ber01-VHDL13_DWOH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:28:17 2008
ber01-VHDL13_DWOH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:28:12 2345
ber01-VHDL13_DWOH_070400-2604070400-dsw--0-ia5 07-Apr-2026 04:58:11 2284
ber01-VHDL13_DWOH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:17 2254
ber01-VHDL13_DWOI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1685
ber01-VHDL13_DWOI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:17 1975
ber01-VHDL13_DWOI_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:11 2153
ber01-VHDL13_DWOI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:17 2139
ber01-VHDL13_DWOI_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:28:17 1984
ber01-VHDL13_DWOI_061800_COR-2604061800-dsw--0-ia5 06-Apr-2026 19:30:21 2027
ber01-VHDL13_DWOI_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:28:12 2320
ber01-VHDL13_DWOI_070400-2604070400-dsw--0-ia5 07-Apr-2026 04:58:11 2200
ber01-VHDL13_DWOI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:28:11 2196
ber01-VHDL13_DWON_051500-2604051500-dsw--0-ia5 05-Apr-2026 15:00:46 3326
ber01-VHDL13_DWON_051736-2604051736-dsw--0-ia5 05-Apr-2026 17:36:31 3219
ber01-VHDL13_DWON_060053-2604060053-dsw--0-ia5 06-Apr-2026 00:53:47 3740
ber01-VHDL13_DWON_060234-2604060234-dsw--0-ia5 06-Apr-2026 02:34:37 3810
ber01-VHDL13_DWON_060235-2604060235-dsw--0-ia5 06-Apr-2026 02:36:09 3810
ber01-VHDL13_DWON_060521-2604060521-dsw--0-ia5 06-Apr-2026 05:21:27 3545
ber01-VHDL13_DWON_060604-2604060604-dsw--0-ia5 06-Apr-2026 06:04:07 3622
ber01-VHDL13_DWON_060734-2604060734-dsw--0-ia5 06-Apr-2026 07:34:38 3702
ber01-VHDL13_DWON_060928-2604060928-dsw--0-ia5 06-Apr-2026 09:28:57 3702
ber01-VHDL13_DWON_061333-2604061333-dsw--0-ia5 06-Apr-2026 13:33:15 3335
ber01-VHDL13_DWON_061423-2604061423-dsw--0-ia5 06-Apr-2026 14:23:32 3335
ber01-VHDL13_DWON_061630-2604061630-dsw--0-ia5 06-Apr-2026 16:30:52 3233
ber01-VHDL13_DWON_061632-2604061632-dsw--0-ia5 06-Apr-2026 16:32:26 3233
ber01-VHDL13_DWON_061705-2604061705-dsw--0-ia5 06-Apr-2026 17:06:03 3233
ber01-VHDL13_DWON_062123-2604062123-dsw--0-ia5 06-Apr-2026 21:23:41 3417
ber01-VHDL13_DWON_070144-2604070144-dsw--0-ia5 07-Apr-2026 01:44:51 3853
ber01-VHDL13_DWON_070203-2604070203-dsw--0-ia5 07-Apr-2026 02:03:21 3675
ber01-VHDL13_DWON_070521-2604070521-dsw--0-ia5 07-Apr-2026 05:21:57 3605
ber01-VHDL13_DWON_070605-2604070605-dsw--0-ia5 07-Apr-2026 06:05:52 3672
ber01-VHDL13_DWON_070821-2604070821-dsw--0-ia5 07-Apr-2026 08:21:22 3672
ber01-VHDL13_DWPG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2261
ber01-VHDL13_DWPG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2526
ber01-VHDL13_DWPG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2587
ber01-VHDL13_DWPG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2534
ber01-VHDL13_DWPG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 1969
ber01-VHDL13_DWPG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2010
ber01-VHDL13_DWPG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:01 1932
ber01-VHDL13_DWPG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 1971
ber01-VHDL13_DWPH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 3191
ber01-VHDL13_DWPH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 3168
ber01-VHDL13_DWPH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2955
ber01-VHDL13_DWPH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2974
ber01-VHDL13_DWPH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 2267
ber01-VHDL13_DWPH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2223
ber01-VHDL13_DWPH_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:01 2232
ber01-VHDL13_DWPH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:01 2153
ber01-VHDL13_DWSG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2344
ber01-VHDL13_DWSG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2230
ber01-VHDL13_DWSG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:17 2283
ber01-VHDL13_DWSG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2138
ber01-VHDL13_DWSG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:30:05 1874
ber01-VHDL13_DWSG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:30:03 2060
ber01-VHDL13_DWSG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:17 2024
ber01-VHDL13_DWSG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:30:07 2025
ber01-VHDL17_DWOG_051200-2604051200-dsw--0-ia5 05-Apr-2026 10:49:37 3098
ber01-VHDL17_DWOG_061200-2604061200-dsw--0-ia5 06-Apr-2026 11:10:26 3054
swis2-VHDL20_DWEG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2353
swis2-VHDL20_DWEG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2586
swis2-VHDL20_DWEG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2511
swis2-VHDL20_DWEG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 2670
swis2-VHDL20_DWEG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2335
swis2-VHDL20_DWEG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:37 2625
swis2-VHDL20_DWEG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:15:02 2602
swis2-VHDL20_DWEG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2733
swis2-VHDL20_DWEH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2456
swis2-VHDL20_DWEH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2763
swis2-VHDL20_DWEH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2685
swis2-VHDL20_DWEH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:12 2837
swis2-VHDL20_DWEH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2485
swis2-VHDL20_DWEH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:36 2825
swis2-VHDL20_DWEH_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:15:02 2714
swis2-VHDL20_DWEH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2779
swis2-VHDL20_DWEI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2240
swis2-VHDL20_DWEI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2475
swis2-VHDL20_DWEI_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2505
swis2-VHDL20_DWEI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 2663
swis2-VHDL20_DWEI_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2336
swis2-VHDL20_DWEI_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:36 2615
swis2-VHDL20_DWEI_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:15:02 2549
swis2-VHDL20_DWEI_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2722
swis2-VHDL20_DWHG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 3463
swis2-VHDL20_DWHG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 3122
swis2-VHDL20_DWHG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3209
swis2-VHDL20_DWHG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 3510
swis2-VHDL20_DWHG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2685
swis2-VHDL20_DWHG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:37 2950
swis2-VHDL20_DWHG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:13 2921
swis2-VHDL20_DWHG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:06 2890
swis2-VHDL20_DWHH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 3641
swis2-VHDL20_DWHH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 3261
swis2-VHDL20_DWHH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3275
swis2-VHDL20_DWHH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 3485
swis2-VHDL20_DWHH_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2510
swis2-VHDL20_DWHH_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:37 2719
swis2-VHDL20_DWHH_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:13 2727
swis2-VHDL20_DWHH_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:06 2986
swis2-VHDL20_DWLG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2678
swis2-VHDL20_DWLG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2858
swis2-VHDL20_DWLG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:15 2926
swis2-VHDL20_DWLG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:12 2829
swis2-VHDL20_DWLG_061800-2604061800-dsw--0-ia5 06-Apr-2026 18:45:01 2268
swis2-VHDL20_DWLG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:36 2390
swis2-VHDL20_DWLG_070400-2604070400-dsw--0-ia5 07-Apr-2026 05:00:11 2594
swis2-VHDL20_DWLG_070800-2604070800-dsw--0-ia5 07-Apr-2026 08:45:01 2674
swis2-VHDL20_DWLH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2733
swis2-VHDL20_DWLH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2935
swis2-VHDL20_DWLH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:15 2912
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swis2-VHDL20_DWMP_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:36 2796
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swis2-VHDL20_DWSG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 2576
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swis2-VHDL20_DWSG_070200-2604070200-dsw--0-ia5 07-Apr-2026 02:45:36 2406
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wst04-VHDL20_DWEG_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 245384
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wst04-VHDL20_DWEH_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:37 243616
wst04-VHDL20_DWEH_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:15:12 242389
wst04-VHDL20_DWEH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 242680
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wst04-VHDL20_DWEI_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 346506
wst04-VHDL20_DWEI_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 346732
wst04-VHDL20_DWEI_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:18 347182
wst04-VHDL20_DWEI_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:12 347867
wst04-VHDL20_DWEI_061800_COR-2604061800-omedes-..> 06-Apr-2026 19:31:51 347913
wst04-VHDL20_DWEI_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 348573
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wst04-VHDL20_DWHG_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 355862
wst04-VHDL20_DWHG_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:13 355929
wst04-VHDL20_DWHG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 356730
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wst04-VHDL20_DWHH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 328734
wst04-VHDL20_DWHH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:11 328803
wst04-VHDL20_DWHH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:18 329935
wst04-VHDL20_DWHH_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:22 321481
wst04-VHDL20_DWHH_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:37 322131
wst04-VHDL20_DWHH_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:13 322090
wst04-VHDL20_DWHH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:16 322812
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wst04-VHDL20_DWLG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 339684
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wst04-VHDL20_DWLH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 334967
wst04-VHDL20_DWLH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 334635
wst04-VHDL20_DWLH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 335211
wst04-VHDL20_DWLH_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:26 332834
wst04-VHDL20_DWLH_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:37 332895
wst04-VHDL20_DWLH_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:41 331965
wst04-VHDL20_DWLH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 332302
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wst04-VHDL20_DWLI_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 334788
wst04-VHDL20_DWLI_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 334711
wst04-VHDL20_DWLI_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:31 335322
wst04-VHDL20_DWLI_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:26 334803
wst04-VHDL20_DWLI_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 334672
wst04-VHDL20_DWLI_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:41 334150
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wst04-VHDL20_DWMG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 564519
wst04-VHDL20_DWMG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:22 564713
wst04-VHDL20_DWMG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 564625
wst04-VHDL20_DWMG_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:16 559513
wst04-VHDL20_DWMG_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 559773
wst04-VHDL20_DWMG_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:15:16 559311
wst04-VHDL20_DWMG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:16 559955
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wst04-VHDL20_DWMO_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 461661
wst04-VHDL20_DWMO_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 462787
wst04-VHDL20_DWMO_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 463305
wst04-VHDL20_DWMO_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:16 448923
wst04-VHDL20_DWMO_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 449854
wst04-VHDL20_DWMO_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:15:16 450120
wst04-VHDL20_DWMO_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 451037
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wst04-VHDL20_DWMP_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 563193
wst04-VHDL20_DWMP_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 563846
wst04-VHDL20_DWMP_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 564188
wst04-VHDL20_DWMP_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:16 571592
wst04-VHDL20_DWMP_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:37 571401
wst04-VHDL20_DWMP_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:15:22 571915
wst04-VHDL20_DWMP_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 572410
wst04-VHDL20_DWPG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:26 335464
wst04-VHDL20_DWPG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 336190
wst04-VHDL20_DWPG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:31 335856
wst04-VHDL20_DWPG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:31 381426
wst04-VHDL20_DWPG_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:22 341216
wst04-VHDL20_DWPG_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 340921
wst04-VHDL20_DWPG_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:31 340544
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wst04-VHDL20_DWPH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 241096
wst04-VHDL20_DWPH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:31 240950
wst04-VHDL20_DWPH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 285922
wst04-VHDL20_DWPH_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:22 283763
wst04-VHDL20_DWPH_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:36 238711
wst04-VHDL20_DWPH_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:00:31 238939
wst04-VHDL20_DWPH_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:28 283826
wst04-VHDL20_DWSG_051300-2604051300-omedes--0.pdf 05-Apr-2026 13:45:12 354478
wst04-VHDL20_DWSG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:12 353999
wst04-VHDL20_DWSG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 354460
wst04-VHDL20_DWSG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:12 354767
wst04-VHDL20_DWSG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 354412
wst04-VHDL20_DWSG_061300-2604061300-omedes--0.pdf 06-Apr-2026 13:45:12 352952
wst04-VHDL20_DWSG_061800-2604061800-omedes--0.pdf 06-Apr-2026 18:45:12 352845
wst04-VHDL20_DWSG_070200-2604070200-omedes--0.pdf 07-Apr-2026 02:45:37 353681
wst04-VHDL20_DWSG_070400-2604070400-omedes--0.pdf 07-Apr-2026 05:15:12 353609
wst04-VHDL20_DWSG_070800-2604070800-omedes--0.pdf 07-Apr-2026 08:45:12 353530