Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_200600 20-Aug-2026 13:43:20 4379
FPDL13_DWMZ_210600 21-Aug-2026 13:04:34 3947
FPDL13_DWMZ_220600 22-Aug-2026 10:17:29 3483
SXDL31_DWAV_201800 20-Aug-2026 16:55:29 5210
SXDL31_DWAV_210800 21-Aug-2026 08:02:45 12154
SXDL31_DWAV_211800 21-Aug-2026 17:00:29 8467
SXDL31_DWAV_220800 22-Aug-2026 06:59:48 6837
SXDL31_DWAV_LATEST 22-Aug-2026 06:59:48 6837
SXDL33_DWAV_200000 20-Aug-2026 11:30:39 16387
SXDL33_DWAV_210000 21-Aug-2026 10:01:53 5457
SXDL33_DWAV_220000 22-Aug-2026 09:27:29 7174
SXDL33_DWAV_LATEST 22-Aug-2026 09:27:29 7174
ber01-FWDL39_DWMS_201200-2608201200-dsw--0-ia5 20-Aug-2026 12:24:03 1994
ber01-FWDL39_DWMS_211200-2608211200-dsw--0-ia5 21-Aug-2026 12:12:44 1708
ber01-VHDL13_DWEG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:28:17 3667
ber01-VHDL13_DWEG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 2926
ber01-VHDL13_DWEH_200800_COR-2608200800-dsw--0-ia5 20-Aug-2026 19:22:03 3078
ber01-VHDL13_DWEH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:28:17 3721
ber01-VHDL13_DWEH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 3039
ber01-VHDL13_DWEI_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:28:17 3580
ber01-VHDL13_DWEI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:28:18 2817
ber01-VHDL13_DWHG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:17 3645
ber01-VHDL13_DWHG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 3592
ber01-VHDL13_DWHH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:17 3022
ber01-VHDL13_DWHH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 3301
ber01-VHDL13_DWLG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 3080
ber01-VHDL13_DWLG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2393
ber01-VHDL13_DWLH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 2748
ber01-VHDL13_DWLH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2321
ber01-VHDL13_DWLI_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 2675
ber01-VHDL13_DWLI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2391
ber01-VHDL13_DWMO_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 3993
ber01-VHDL13_DWMO_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 2853
ber01-VHDL13_DWMP_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 4392
ber01-VHDL13_DWMP_210800_COR-2608210800-dsw--0-ia5 21-Aug-2026 08:45:24 4349
ber01-VHDL13_DWMP_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 2989
ber01-VHDL13_DWOG_201700-2608201700-dsw--0-ia5 20-Aug-2026 18:00:06 5032
ber01-VHDL13_DWOG_210300-2608210300-dsw--0-ia5 21-Aug-2026 03:00:03 5875
ber01-VHDL13_DWOG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 5093
ber01-VHDL13_DWOG_211700-2608211700-dsw--0-ia5 21-Aug-2026 18:00:04 3789
ber01-VHDL13_DWOG_220300-2608220300-dsw--0-ia5 22-Aug-2026 03:00:25 3670
ber01-VHDL13_DWOG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 3466
ber01-VHDL13_DWON_201452-2608201452-dsw--0-ia5 20-Aug-2026 14:53:20 4444
ber01-VHDL13_DWON_201705-2608201705-dsw--0-ia5 20-Aug-2026 17:05:49 4444
ber01-VHDL13_DWON_201915-2608201915-dsw--0-ia5 20-Aug-2026 19:15:34 4134
ber01-VHDL13_DWON_202153-2608202153-dsw--0-ia5 20-Aug-2026 21:53:29 4370
ber01-VHDL13_DWON_210006-2608210006-dsw--0-ia5 21-Aug-2026 00:06:49 5048
ber01-VHDL13_DWON_210152-2608210152-dsw--0-ia5 21-Aug-2026 01:52:08 4851
ber01-VHDL13_DWON_210247-2608210247-dsw--0-ia5 21-Aug-2026 02:47:36 4851
ber01-VHDL13_DWON_210259-2608210259-dsw--0-ia5 21-Aug-2026 02:59:14 4911
ber01-VHDL13_DWON_210530-2608210530-dsw--0-ia5 21-Aug-2026 05:30:56 4782
ber01-VHDL13_DWON_210611-2608210611-dsw--0-ia5 21-Aug-2026 06:11:13 4157
ber01-VHDL13_DWON_211021-2608211021-dsw--0-ia5 21-Aug-2026 10:21:53 4157
ber01-VHDL13_DWON_211502-2608211502-dsw--0-ia5 21-Aug-2026 15:02:25 3888
ber01-VHDL13_DWON_211705-2608211705-dsw--0-ia5 21-Aug-2026 17:05:48 3035
ber01-VHDL13_DWON_211718-2608211718-dsw--0-ia5 21-Aug-2026 17:18:53 3035
ber01-VHDL13_DWON_212050-2608212050-dsw--0-ia5 21-Aug-2026 20:50:51 3006
ber01-VHDL13_DWON_220131-2608220131-dsw--0-ia5 22-Aug-2026 01:32:14 2770
ber01-VHDL13_DWON_220234-2608220234-dsw--0-ia5 22-Aug-2026 02:35:11 2889
ber01-VHDL13_DWON_220446-2608220446-dsw--0-ia5 22-Aug-2026 04:46:18 3348
ber01-VHDL13_DWON_220526-2608220526-dsw--0-ia5 22-Aug-2026 05:26:23 3348
ber01-VHDL13_DWON_220552-2608220552-dsw--0-ia5 22-Aug-2026 05:52:53 3348
ber01-VHDL13_DWPG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 3139
ber01-VHDL13_DWPG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1953
ber01-VHDL13_DWPH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 3180
ber01-VHDL13_DWPH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2953
ber01-VHDL13_DWSG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:17 3955
ber01-VHDL13_DWSG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 2884
ber01-VHDL17_DWOG_201200-2608201200-dsw--0-ia5 20-Aug-2026 12:09:43 3025
ber01-VHDL17_DWOG_211200-2608211200-dsw--0-ia5 21-Aug-2026 11:56:39 2843
swis2-VHDL20_DWEG_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 1466
swis2-VHDL20_DWEG_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 1273
swis2-VHDL20_DWEG_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:01:13 1428
swis2-VHDL20_DWEG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 1916
swis2-VHDL20_DWEG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1729
swis2-VHDL20_DWEG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1524
swis2-VHDL20_DWEG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1225
swis2-VHDL20_DWEG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1287
swis2-VHDL20_DWEH_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 1427
swis2-VHDL20_DWEH_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 1238
swis2-VHDL20_DWEH_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:01:13 1407
swis2-VHDL20_DWEH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 1924
swis2-VHDL20_DWEH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1807
swis2-VHDL20_DWEH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1521
swis2-VHDL20_DWEH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1100
swis2-VHDL20_DWEH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1267
swis2-VHDL20_DWEI_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 1414
swis2-VHDL20_DWEI_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 1221
swis2-VHDL20_DWEI_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:01:13 1381
swis2-VHDL20_DWEI_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 1932
swis2-VHDL20_DWEI_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1785
swis2-VHDL20_DWEI_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1592
swis2-VHDL20_DWEI_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:01:15 1247
swis2-VHDL20_DWEI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1292
swis2-VHDL20_DWHG_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:45:15 1804
swis2-VHDL20_DWHG_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:45:40 1665
swis2-VHDL20_DWHG_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1698
swis2-VHDL20_DWHG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:45:24 1698
swis2-VHDL20_DWHG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:46:05 1387
swis2-VHDL20_DWHG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:45:24 1533
swis2-VHDL20_DWHG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1530
swis2-VHDL20_DWHG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:45:29 1726
swis2-VHDL20_DWHH_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:45:15 1558
swis2-VHDL20_DWHH_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:45:40 1469
swis2-VHDL20_DWHH_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1424
swis2-VHDL20_DWHH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:45:24 1590
swis2-VHDL20_DWHH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:46:04 1207
swis2-VHDL20_DWHH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:45:24 1450
swis2-VHDL20_DWHH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1450
swis2-VHDL20_DWHH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:45:29 1577
swis2-VHDL20_DWLG_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:31:16 1568
swis2-VHDL20_DWLG_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:30 1476
swis2-VHDL20_DWLG_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1464
swis2-VHDL20_DWLG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:27 1587
swis2-VHDL20_DWLG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1517
swis2-VHDL20_DWLG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1186
swis2-VHDL20_DWLG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1011
swis2-VHDL20_DWLG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1133
swis2-VHDL20_DWLH_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:31:16 1415
swis2-VHDL20_DWLH_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:30 1192
swis2-VHDL20_DWLH_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1246
swis2-VHDL20_DWLH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:27 1384
swis2-VHDL20_DWLH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1396
swis2-VHDL20_DWLH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1133
swis2-VHDL20_DWLH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1039
swis2-VHDL20_DWLH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 993
swis2-VHDL20_DWLI_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:31:16 1392
swis2-VHDL20_DWLI_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:30 1203
swis2-VHDL20_DWLI_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1257
swis2-VHDL20_DWLI_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:27 1341
swis2-VHDL20_DWLI_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1356
swis2-VHDL20_DWLI_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1322
swis2-VHDL20_DWLI_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1119
swis2-VHDL20_DWLI_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1098
swis2-VHDL20_DWMO_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 2335
swis2-VHDL20_DWMO_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 2341
swis2-VHDL20_DWMO_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:03 2342
swis2-VHDL20_DWMO_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 2363
swis2-VHDL20_DWMO_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1788
swis2-VHDL20_DWMO_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1203
swis2-VHDL20_DWMO_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:08 1220
swis2-VHDL20_DWMO_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1363
swis2-VHDL20_DWMP_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 2611
swis2-VHDL20_DWMP_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 2287
swis2-VHDL20_DWMP_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:03 2287
swis2-VHDL20_DWMP_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:10 2263
swis2-VHDL20_DWMP_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1740
swis2-VHDL20_DWMP_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1130
swis2-VHDL20_DWMP_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:08 1143
swis2-VHDL20_DWMP_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:12 1398
swis2-VHDL20_DWPG_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:31:16 1441
swis2-VHDL20_DWPG_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:30 1536
swis2-VHDL20_DWPG_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1555
swis2-VHDL20_DWPG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:27 1743
swis2-VHDL20_DWPG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1769
swis2-VHDL20_DWPG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1118
swis2-VHDL20_DWPG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 896
swis2-VHDL20_DWPG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 971
swis2-VHDL20_DWPH_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:31:16 1489
swis2-VHDL20_DWPH_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:30 1185
swis2-VHDL20_DWPH_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1239
swis2-VHDL20_DWPH_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:27 1716
swis2-VHDL20_DWPH_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:31:12 1816
swis2-VHDL20_DWPH_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1588
swis2-VHDL20_DWPH_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:13 1437
swis2-VHDL20_DWPH_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1531
swis2-VHDL20_DWSG_201800-2608201800-dsw--0-ia5 20-Aug-2026 18:30:16 1514
swis2-VHDL20_DWSG_210200-2608210200-dsw--0-ia5 21-Aug-2026 02:30:19 1958
swis2-VHDL20_DWSG_210400-2608210400-dsw--0-ia5 21-Aug-2026 05:00:19 1977
swis2-VHDL20_DWSG_210800-2608210800-dsw--0-ia5 21-Aug-2026 08:30:17 2148
swis2-VHDL20_DWSG_211800-2608211800-dsw--0-ia5 21-Aug-2026 18:30:04 1544
swis2-VHDL20_DWSG_220200-2608220200-dsw--0-ia5 22-Aug-2026 02:30:31 1137
swis2-VHDL20_DWSG_220400-2608220400-dsw--0-ia5 22-Aug-2026 05:00:19 1124
swis2-VHDL20_DWSG_220400_COR-2608220400-dsw--0-ia5 22-Aug-2026 05:00:49 1123
swis2-VHDL20_DWSG_220800-2608220800-dsw--0-ia5 22-Aug-2026 08:30:20 1275
wst04-VHDL20_DWEG_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:16 241588
wst04-VHDL20_DWEG_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 240717
wst04-VHDL20_DWEG_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:13 240555
wst04-VHDL20_DWEG_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:17 242401
wst04-VHDL20_DWEG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:25 245506
wst04-VHDL20_DWEG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 245469
wst04-VHDL20_DWEG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 243730
wst04-VHDL20_DWEG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 244437
wst04-VHDL20_DWEH_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:16 239989
wst04-VHDL20_DWEH_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 239708
wst04-VHDL20_DWEH_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:13 239530
wst04-VHDL20_DWEH_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:17 241450
wst04-VHDL20_DWEH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:25 243822
wst04-VHDL20_DWEH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 244290
wst04-VHDL20_DWEH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 242907
wst04-VHDL20_DWEH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 243708
wst04-VHDL20_DWEI_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:26 350721
wst04-VHDL20_DWEI_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 349671
wst04-VHDL20_DWEI_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:19 349523
wst04-VHDL20_DWEI_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:17 351614
wst04-VHDL20_DWEI_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 351534
wst04-VHDL20_DWEI_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 352244
wst04-VHDL20_DWEI_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:13 349910
wst04-VHDL20_DWEI_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 350840
wst04-VHDL20_DWHG_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:45:26 345750
wst04-VHDL20_DWHG_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:45:40 345008
wst04-VHDL20_DWHG_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:19 344968
wst04-VHDL20_DWHG_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:45:24 346919
wst04-VHDL20_DWHG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:46:05 348794
wst04-VHDL20_DWHG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:45:24 348340
wst04-VHDL20_DWHG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 348145
wst04-VHDL20_DWHG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:45:29 350253
wst04-VHDL20_DWHH_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:45:26 336818
wst04-VHDL20_DWHH_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:45:40 336461
wst04-VHDL20_DWHH_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:19 234342
wst04-VHDL20_DWHH_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:45:24 338576
wst04-VHDL20_DWHH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:46:05 333773
wst04-VHDL20_DWHH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:45:24 334725
wst04-VHDL20_DWHH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 229677
wst04-VHDL20_DWHH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:45:29 335341
wst04-VHDL20_DWLG_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:31:40 343705
wst04-VHDL20_DWLG_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:30 342884
wst04-VHDL20_DWLG_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:43 342743
wst04-VHDL20_DWLG_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:43 343019
wst04-VHDL20_DWLG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 346799
wst04-VHDL20_DWLG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 346245
wst04-VHDL20_DWLG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 345953
wst04-VHDL20_DWLG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 346142
wst04-VHDL20_DWLH_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:31:40 337882
wst04-VHDL20_DWLH_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:30 336978
wst04-VHDL20_DWLH_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:43 336809
wst04-VHDL20_DWLH_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:57 337059
wst04-VHDL20_DWLH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 348324
wst04-VHDL20_DWLH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 347484
wst04-VHDL20_DWLH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 347183
wst04-VHDL20_DWLH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:52 346799
wst04-VHDL20_DWLI_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:31:40 338214
wst04-VHDL20_DWLI_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:30 337662
wst04-VHDL20_DWLI_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:43 337510
wst04-VHDL20_DWLI_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:43 382281
wst04-VHDL20_DWLI_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 344353
wst04-VHDL20_DWLI_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 344195
wst04-VHDL20_DWLI_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:43 343876
wst04-VHDL20_DWLI_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 387818
wst04-VHDL20_DWMO_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:26 356898
wst04-VHDL20_DWMO_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 464325
wst04-VHDL20_DWMO_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:19 464515
wst04-VHDL20_DWMO_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:17 465062
wst04-VHDL20_DWMO_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 361526
wst04-VHDL20_DWMO_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 469206
wst04-VHDL20_DWMO_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 469156
wst04-VHDL20_DWMO_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 469774
wst04-VHDL20_DWMP_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:26 474334
wst04-VHDL20_DWMP_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 579566
wst04-VHDL20_DWMP_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:19 579745
wst04-VHDL20_DWMP_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:27 473781
wst04-VHDL20_DWMP_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 474947
wst04-VHDL20_DWMP_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 581434
wst04-VHDL20_DWMP_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:19 580787
wst04-VHDL20_DWMP_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:29 474091
wst04-VHDL20_DWPG_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:31:40 340669
wst04-VHDL20_DWPG_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:30 238206
wst04-VHDL20_DWPG_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:33 340732
wst04-VHDL20_DWPG_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:43 386440
wst04-VHDL20_DWPG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 350535
wst04-VHDL20_DWPG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 243344
wst04-VHDL20_DWPG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:33 347757
wst04-VHDL20_DWPG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 392477
wst04-VHDL20_DWPH_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:31:40 244616
wst04-VHDL20_DWPH_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:30 243273
wst04-VHDL20_DWPH_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:33 243652
wst04-VHDL20_DWPH_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:43 244532
wst04-VHDL20_DWPH_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:31:31 250117
wst04-VHDL20_DWPH_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 249839
wst04-VHDL20_DWPH_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:33 249641
wst04-VHDL20_DWPH_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:43 249733
wst04-VHDL20_DWSG_201800-2608201800-omedes--0.pdf 20-Aug-2026 18:30:16 353369
wst04-VHDL20_DWSG_210200-2608210200-omedes--0.pdf 21-Aug-2026 02:30:28 355089
wst04-VHDL20_DWSG_210400-2608210400-omedes--0.pdf 21-Aug-2026 05:00:13 355034
wst04-VHDL20_DWSG_210800-2608210800-omedes--0.pdf 21-Aug-2026 08:30:17 355268
wst04-VHDL20_DWSG_211800-2608211800-omedes--0.pdf 21-Aug-2026 18:30:29 353092
wst04-VHDL20_DWSG_220200-2608220200-omedes--0.pdf 22-Aug-2026 02:30:31 351262
wst04-VHDL20_DWSG_220400-2608220400-omedes--0.pdf 22-Aug-2026 05:00:59 351539
wst04-VHDL20_DWSG_220800-2608220800-omedes--0.pdf 22-Aug-2026 08:30:20 351630