Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_280600 28-Jun-2026 14:16:59 8000
FPDL13_DWMZ_290600 29-Jun-2026 14:05:33 6917
SXDL31_DWAV_280800 28-Jun-2026 08:11:43 15233
SXDL31_DWAV_281800 28-Jun-2026 16:07:14 3274
SXDL31_DWAV_290800 29-Jun-2026 07:38:48 12485
SXDL31_DWAV_291800 29-Jun-2026 16:42:55 5469
SXDL31_DWAV_LATEST 29-Jun-2026 16:42:55 5469
SXDL33_DWAV_280000 28-Jun-2026 09:20:59 10623
SXDL33_DWAV_290000 29-Jun-2026 09:19:00 12039
SXDL33_DWAV_LATEST 29-Jun-2026 09:19:00 12039
ber01-FWDL39_DWMS_281200-2606281200-dsw--0-ia5 28-Jun-2026 11:55:37 1660
ber01-FWDL39_DWMS_291200-2606291200-dsw--0-ia5 29-Jun-2026 11:41:03 2341
ber01-VHDL13_DWEG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:28:16 3451
ber01-VHDL13_DWEG_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 18:13:46 3501
ber01-VHDL13_DWEG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 3680
ber01-VHDL13_DWEH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:28:12 3238
ber01-VHDL13_DWEH_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 18:20:17 3346
ber01-VHDL13_DWEH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 2905
ber01-VHDL13_DWEI_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:28:16 3464
ber01-VHDL13_DWEI_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 18:14:27 3501
ber01-VHDL13_DWEI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 3558
ber01-VHDL13_DWHG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3580
ber01-VHDL13_DWHG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3859
ber01-VHDL13_DWHH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3028
ber01-VHDL13_DWHH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3286
ber01-VHDL13_DWLG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3251
ber01-VHDL13_DWLG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 2965
ber01-VHDL13_DWLH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3318
ber01-VHDL13_DWLH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 2951
ber01-VHDL13_DWLI_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3265
ber01-VHDL13_DWLI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 3017
ber01-VHDL13_DWMO_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 4074
ber01-VHDL13_DWMO_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3636
ber01-VHDL13_DWMO_290800_COR-2606290800-dsw--0-ia5 29-Jun-2026 13:01:41 3614
ber01-VHDL13_DWMP_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 4016
ber01-VHDL13_DWMP_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3525
ber01-VHDL13_DWOG_280300-2606280300-dsw--0-ia5 28-Jun-2026 03:00:01 5547
ber01-VHDL13_DWOG_280300_COR-2606280300-dsw--0-ia5 28-Jun-2026 03:02:22 5082
ber01-VHDL13_DWOG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 4978
ber01-VHDL13_DWOG_281700-2606281700-dsw--0-ia5 28-Jun-2026 18:00:06 4282
ber01-VHDL13_DWOG_290300-2606290300-dsw--0-ia5 29-Jun-2026 03:00:06 3831
ber01-VHDL13_DWOG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 5269
ber01-VHDL13_DWOG_291700-2606291700-dsw--0-ia5 29-Jun-2026 18:00:06 4349
ber01-VHDL13_DWON_280301-2606280301-dsw--0-ia5 28-Jun-2026 03:01:51 4040
ber01-VHDL13_DWON_280521-2606280521-dsw--0-ia5 28-Jun-2026 05:21:37 3639
ber01-VHDL13_DWON_280644-2606280644-dsw--0-ia5 28-Jun-2026 06:45:08 4241
ber01-VHDL13_DWON_281317-2606281317-dsw--0-ia5 28-Jun-2026 13:17:21 4066
ber01-VHDL13_DWON_281453-2606281453-dsw--0-ia5 28-Jun-2026 14:53:17 3706
ber01-VHDL13_DWON_281713-2606281713-dsw--0-ia5 28-Jun-2026 17:13:28 3342
ber01-VHDL13_DWON_290125-2606290125-dsw--0-ia5 29-Jun-2026 01:26:03 3481
ber01-VHDL13_DWON_290236-2606290236-dsw--0-ia5 29-Jun-2026 02:36:07 3481
ber01-VHDL13_DWON_290529-2606290529-dsw--0-ia5 29-Jun-2026 05:29:46 3640
ber01-VHDL13_DWON_290629-2606290629-dsw--0-ia5 29-Jun-2026 06:29:56 3843
ber01-VHDL13_DWON_290826-2606290826-dsw--0-ia5 29-Jun-2026 08:27:02 3820
ber01-VHDL13_DWON_290955-2606290955-dsw--0-ia5 29-Jun-2026 09:55:06 3822
ber01-VHDL13_DWON_291500-2606291500-dsw--0-ia5 29-Jun-2026 15:00:42 3902
ber01-VHDL13_DWON_291759-2606291759-dsw--0-ia5 29-Jun-2026 17:59:21 3269
ber01-VHDL13_DWPG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3198
ber01-VHDL13_DWPG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 3520
ber01-VHDL13_DWPH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 3126
ber01-VHDL13_DWPH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3141
ber01-VHDL13_DWSG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 4386
ber01-VHDL13_DWSG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3730
ber01-VHDL17_DWOG_281200-2606281200-dsw--0-ia5 28-Jun-2026 11:10:07 2597
ber01-VHDL17_DWOG_291200-2606291200-dsw--0-ia5 29-Jun-2026 11:32:16 3021
swis2-VHDL20_DWEG_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 1512
swis2-VHDL20_DWEG_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:01:18 1503
swis2-VHDL20_DWEG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 1711
swis2-VHDL20_DWEG_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 13:37:02 1651
swis2-VHDL20_DWEG_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:01 2009
swis2-VHDL20_DWEG_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:01 1567
swis2-VHDL20_DWEG_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:01:22 1627
swis2-VHDL20_DWEG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1984
swis2-VHDL20_DWEG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1755
swis2-VHDL20_DWEH_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 1493
swis2-VHDL20_DWEH_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:01:18 1305
swis2-VHDL20_DWEH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 1598
swis2-VHDL20_DWEH_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 13:37:02 1555
swis2-VHDL20_DWEH_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:01 1948
swis2-VHDL20_DWEH_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:01 1787
swis2-VHDL20_DWEH_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:01:22 1671
swis2-VHDL20_DWEH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1558
swis2-VHDL20_DWEH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1715
swis2-VHDL20_DWEI_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 1785
swis2-VHDL20_DWEI_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:01:18 1610
swis2-VHDL20_DWEI_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 1808
swis2-VHDL20_DWEI_280800_COR-2606280800-dsw--0-ia5 28-Jun-2026 13:50:07 1753
swis2-VHDL20_DWEI_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:01 2080
swis2-VHDL20_DWEI_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:01 1600
swis2-VHDL20_DWEI_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:01:22 1601
swis2-VHDL20_DWEI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1963
swis2-VHDL20_DWEI_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1551
swis2-VHDL20_DWHG_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:45:07 1818
swis2-VHDL20_DWHG_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:16 1692
swis2-VHDL20_DWHG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:45:03 1952
swis2-VHDL20_DWHG_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:45:02 2025
swis2-VHDL20_DWHG_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:45:01 1691
swis2-VHDL20_DWHG_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:16 1809
swis2-VHDL20_DWHG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:45:01 2032
swis2-VHDL20_DWHG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:45:15 2012
swis2-VHDL20_DWHH_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:45:07 1853
swis2-VHDL20_DWHH_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:16 1675
swis2-VHDL20_DWHH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:45:03 1605
swis2-VHDL20_DWHH_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:45:02 1548
swis2-VHDL20_DWHH_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:45:01 1619
swis2-VHDL20_DWHH_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:16 1615
swis2-VHDL20_DWHH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:45:01 1663
swis2-VHDL20_DWHH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:45:15 2064
swis2-VHDL20_DWLG_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:22 1652
swis2-VHDL20_DWLG_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:12 1506
swis2-VHDL20_DWLG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:27 2021
swis2-VHDL20_DWLG_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:31:01 1939
swis2-VHDL20_DWLG_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:21 1797
swis2-VHDL20_DWLG_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:12 1797
swis2-VHDL20_DWLG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1519
swis2-VHDL20_DWLG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1110
swis2-VHDL20_DWLH_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:22 1670
swis2-VHDL20_DWLH_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:12 1513
swis2-VHDL20_DWLH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:27 2041
swis2-VHDL20_DWLH_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:31:01 2009
swis2-VHDL20_DWLH_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:21 1974
swis2-VHDL20_DWLH_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:12 1974
swis2-VHDL20_DWLH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1503
swis2-VHDL20_DWLH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1056
swis2-VHDL20_DWLI_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:22 1671
swis2-VHDL20_DWLI_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:12 1508
swis2-VHDL20_DWLI_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:27 2024
swis2-VHDL20_DWLI_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:31:01 1970
swis2-VHDL20_DWLI_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:21 1805
swis2-VHDL20_DWLI_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:12 1805
swis2-VHDL20_DWLI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1559
swis2-VHDL20_DWLI_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1048
swis2-VHDL20_DWMO_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 1564
swis2-VHDL20_DWMO_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:02 1719
swis2-VHDL20_DWMO_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 2444
swis2-VHDL20_DWMO_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:01 2331
swis2-VHDL20_DWMO_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:05 1379
swis2-VHDL20_DWMO_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:06 1380
swis2-VHDL20_DWMO_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 2018
swis2-VHDL20_DWMO_290800_COR-2606290800-dsw--0-ia5 29-Jun-2026 13:01:41 3334
swis2-VHDL20_DWMO_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:07 1955
swis2-VHDL20_DWMP_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 1574
swis2-VHDL20_DWMP_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:02 1730
swis2-VHDL20_DWMP_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 2597
swis2-VHDL20_DWMP_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:01 2486
swis2-VHDL20_DWMP_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:05 1503
swis2-VHDL20_DWMP_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:06 1503
swis2-VHDL20_DWMP_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 2067
swis2-VHDL20_DWMP_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:07 2448
swis2-VHDL20_DWPG_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:22 1629
swis2-VHDL20_DWPG_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:12 1523
swis2-VHDL20_DWPG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:27 2051
swis2-VHDL20_DWPG_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:31:01 2005
swis2-VHDL20_DWPG_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:21 2017
swis2-VHDL20_DWPG_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:12 2017
swis2-VHDL20_DWPG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 2274
swis2-VHDL20_DWPG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1125
swis2-VHDL20_DWPH_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:22 1560
swis2-VHDL20_DWPH_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:12 1525
swis2-VHDL20_DWPH_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:27 1825
swis2-VHDL20_DWPH_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:31:01 1900
swis2-VHDL20_DWPH_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:21 1813
swis2-VHDL20_DWPH_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:12 1813
swis2-VHDL20_DWPH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1829
swis2-VHDL20_DWPH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1059
swis2-VHDL20_DWSG_280200-2606280200-dsw--0-ia5 28-Jun-2026 02:30:05 2124
swis2-VHDL20_DWSG_280400-2606280400-dsw--0-ia5 28-Jun-2026 05:00:16 2286
swis2-VHDL20_DWSG_280400_COR-2606280400-dsw--0-ia5 28-Jun-2026 05:31:29 2100
swis2-VHDL20_DWSG_280800-2606280800-dsw--0-ia5 28-Jun-2026 08:30:20 2443
swis2-VHDL20_DWSG_281800-2606281800-dsw--0-ia5 28-Jun-2026 18:30:07 2184
swis2-VHDL20_DWSG_290200-2606290200-dsw--0-ia5 29-Jun-2026 02:30:01 1521
swis2-VHDL20_DWSG_290400-2606290400-dsw--0-ia5 29-Jun-2026 05:00:16 1580
swis2-VHDL20_DWSG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1819
swis2-VHDL20_DWSG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1939
swis2-VHDL20_DWSG_291800_COR-2606291800-dsw--0-ia5 29-Jun-2026 22:02:12 2103
wst04-VHDL20_DWEG_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:12 246344
wst04-VHDL20_DWEG_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:12 246564
wst04-VHDL20_DWEG_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:20 247309
wst04-VHDL20_DWEG_280800_COR-2606280800-omedes-..> 28-Jun-2026 13:37:24 242564
wst04-VHDL20_DWEG_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:11 242874
wst04-VHDL20_DWEG_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:14 241766
wst04-VHDL20_DWEG_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:12 241820
wst04-VHDL20_DWEG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:12 242210
wst04-VHDL20_DWEG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:11 243440
wst04-VHDL20_DWEH_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:12 241831
wst04-VHDL20_DWEH_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:12 242175
wst04-VHDL20_DWEH_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:20 242865
wst04-VHDL20_DWEH_280800_COR-2606280800-omedes-..> 28-Jun-2026 13:37:24 242057
wst04-VHDL20_DWEH_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:11 241913
wst04-VHDL20_DWEH_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:14 241188
wst04-VHDL20_DWEH_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:12 241465
wst04-VHDL20_DWEH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:12 241322
wst04-VHDL20_DWEH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:11 236256
wst04-VHDL20_DWEI_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:12 349749
wst04-VHDL20_DWEI_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:12 349389
wst04-VHDL20_DWEI_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:20 349610
wst04-VHDL20_DWEI_280800_COR-2606280800-omedes-..> 28-Jun-2026 13:37:24 349405
wst04-VHDL20_DWEI_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:17 350256
wst04-VHDL20_DWEI_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:14 349155
wst04-VHDL20_DWEI_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:16 349157
wst04-VHDL20_DWEI_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:16 348759
wst04-VHDL20_DWEI_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 348527
wst04-VHDL20_DWHG_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:45:11 353258
wst04-VHDL20_DWHG_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:16 352756
wst04-VHDL20_DWHG_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:45:13 354841
wst04-VHDL20_DWHG_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:45:12 357088
wst04-VHDL20_DWHG_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:45:12 355934
wst04-VHDL20_DWHG_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:16 356580
wst04-VHDL20_DWHG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:45:12 357215
wst04-VHDL20_DWHG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:45:15 351060
wst04-VHDL20_DWHH_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:45:11 337701
wst04-VHDL20_DWHH_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:16 233039
wst04-VHDL20_DWHH_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:45:13 337067
wst04-VHDL20_DWHH_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:45:12 337733
wst04-VHDL20_DWHH_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:45:12 337870
wst04-VHDL20_DWHH_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:12 231397
wst04-VHDL20_DWHH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:45:12 337518
wst04-VHDL20_DWHH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:45:15 337688
wst04-VHDL20_DWLG_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:22 336734
wst04-VHDL20_DWLG_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:42 336037
wst04-VHDL20_DWLG_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:47 337073
wst04-VHDL20_DWLG_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:31:22 333530
wst04-VHDL20_DWLG_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:27 333727
wst04-VHDL20_DWLG_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:40 333768
wst04-VHDL20_DWLG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 332290
wst04-VHDL20_DWLG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 337195
wst04-VHDL20_DWLH_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:22 343025
wst04-VHDL20_DWLH_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:42 342235
wst04-VHDL20_DWLH_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:47 343317
wst04-VHDL20_DWLH_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:31:26 341130
wst04-VHDL20_DWLH_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:21 341583
wst04-VHDL20_DWLH_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:40 341624
wst04-VHDL20_DWLH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 340093
wst04-VHDL20_DWLH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:32 347567
wst04-VHDL20_DWLI_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:30 340199
wst04-VHDL20_DWLI_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:42 339466
wst04-VHDL20_DWLI_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:47 385090
wst04-VHDL20_DWLI_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:31:22 334507
wst04-VHDL20_DWLI_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:21 334935
wst04-VHDL20_DWLI_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:40 334955
wst04-VHDL20_DWLI_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 378145
wst04-VHDL20_DWLI_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 341984
wst04-VHDL20_DWMO_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:16 460195
wst04-VHDL20_DWMO_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:18 460510
wst04-VHDL20_DWMO_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:20 461223
wst04-VHDL20_DWMO_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:17 350400
wst04-VHDL20_DWMO_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:17 452824
wst04-VHDL20_DWMO_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:16 452899
wst04-VHDL20_DWMO_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:18 454477
wst04-VHDL20_DWMO_290800_COR-2606290800-omedes-..> 29-Jun-2026 13:01:53 470101
wst04-VHDL20_DWMO_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 360446
wst04-VHDL20_DWMP_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:16 567328
wst04-VHDL20_DWMP_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:18 567635
wst04-VHDL20_DWMP_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:22 461908
wst04-VHDL20_DWMP_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:17 477224
wst04-VHDL20_DWMP_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:17 585701
wst04-VHDL20_DWMP_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:16 585902
wst04-VHDL20_DWMP_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:22 478253
wst04-VHDL20_DWMP_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 488397
wst04-VHDL20_DWPG_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:22 241292
wst04-VHDL20_DWPG_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:32 342679
wst04-VHDL20_DWPG_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:47 387520
wst04-VHDL20_DWPG_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:31:22 342790
wst04-VHDL20_DWPG_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:21 242331
wst04-VHDL20_DWPG_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:31 343370
wst04-VHDL20_DWPG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:47 388124
wst04-VHDL20_DWPG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 341892
wst04-VHDL20_DWPH_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:22 241220
wst04-VHDL20_DWPH_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:00:32 240937
wst04-VHDL20_DWPH_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:47 241100
wst04-VHDL20_DWPH_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:31:22 242694
wst04-VHDL20_DWPH_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:21 242303
wst04-VHDL20_DWPH_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:31 242374
wst04-VHDL20_DWPH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 242353
wst04-VHDL20_DWPH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 247159
wst04-VHDL20_DWSG_280200-2606280200-omedes--0.pdf 28-Jun-2026 02:30:12 346817
wst04-VHDL20_DWSG_280400-2606280400-omedes--0.pdf 28-Jun-2026 05:31:29 348038
wst04-VHDL20_DWSG_280800-2606280800-omedes--0.pdf 28-Jun-2026 08:30:20 346370
wst04-VHDL20_DWSG_281800-2606281800-omedes--0.pdf 28-Jun-2026 18:30:17 353361
wst04-VHDL20_DWSG_290200-2606290200-omedes--0.pdf 29-Jun-2026 02:30:14 351978
wst04-VHDL20_DWSG_290400-2606290400-omedes--0.pdf 29-Jun-2026 05:00:12 352001
wst04-VHDL20_DWSG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:16 353177
wst04-VHDL20_DWSG_291800-2606291800-omedes--0.pdf 29-Jun-2026 22:02:22 357847