Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_160600 16-Jan-2026 14:03:34 8327
FPDL13_DWMZ_170600 17-Jan-2026 11:03:48 3675
SXDL31_DWAV_161800 16-Jan-2026 15:01:26 7333
SXDL31_DWAV_170800 17-Jan-2026 09:52:55 11986
SXDL31_DWAV_171800 17-Jan-2026 17:13:13 6369
SXDL31_DWAV_180800 18-Jan-2026 10:31:18 10271
SXDL31_DWAV_LATEST 18-Jan-2026 10:31:18 10271
SXDL33_DWAV_170000 17-Jan-2026 11:07:21 8527
SXDL33_DWAV_180000 18-Jan-2026 11:27:40 7373
SXDL33_DWAV_LATEST 18-Jan-2026 11:27:40 7373
ber01-FWDL39_DWMS_161230-2601161230-dsw--0-ia5 16-Jan-2026 13:02:07 944
ber01-FWDL39_DWMS_171230-2601171230-dsw--0-ia5 17-Jan-2026 12:38:05 1728
ber01-VHDL13_DWEH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:28:16 3252
ber01-VHDL13_DWEH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:28:12 3093
ber01-VHDL13_DWEH_170400-2601170400-dsw--0-ia5 17-Jan-2026 05:58:16 3290
ber01-VHDL13_DWEH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:28:17 2776
ber01-VHDL13_DWEH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:17 2814
ber01-VHDL13_DWEH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 3122
ber01-VHDL13_DWEH_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:12 3052
ber01-VHDL13_DWEH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2741
ber01-VHDL13_DWHG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:07 3037
ber01-VHDL13_DWHG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:10 3113
ber01-VHDL13_DWHG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:07 3113
ber01-VHDL13_DWHG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 3113
ber01-VHDL13_DWHG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2877
ber01-VHDL13_DWHG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:09 2903
ber01-VHDL13_DWHG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2784
ber01-VHDL13_DWHG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:11 2578
ber01-VHDL13_DWHG_180800_COR-2601180800-dsw--0-ia5 18-Jan-2026 09:40:27 2582
ber01-VHDL13_DWHH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:07 2649
ber01-VHDL13_DWHH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:10 2738
ber01-VHDL13_DWHH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:07 2741
ber01-VHDL13_DWHH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 2346
ber01-VHDL13_DWHH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2229
ber01-VHDL13_DWHH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:09 2530
ber01-VHDL13_DWHH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2530
ber01-VHDL13_DWHH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:11 2406
ber01-VHDL13_DWHH_180800_COR-2601180800-dsw--0-ia5 18-Jan-2026 09:40:57 2410
ber01-VHDL13_DWLG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 2599
ber01-VHDL13_DWLG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 2771
ber01-VHDL13_DWLG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 2742
ber01-VHDL13_DWLG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 2994
ber01-VHDL13_DWLG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 3129
ber01-VHDL13_DWLG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3163
ber01-VHDL13_DWLG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3244
ber01-VHDL13_DWLG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3231
ber01-VHDL13_DWLH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 1802
ber01-VHDL13_DWLH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 1800
ber01-VHDL13_DWLH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 1795
ber01-VHDL13_DWLH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 1847
ber01-VHDL13_DWLH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2011
ber01-VHDL13_DWLH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 1944
ber01-VHDL13_DWLH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2053
ber01-VHDL13_DWLH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1803
ber01-VHDL13_DWLI_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 1699
ber01-VHDL13_DWLI_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 1779
ber01-VHDL13_DWLI_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 1654
ber01-VHDL13_DWLI_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 1743
ber01-VHDL13_DWLI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 1807
ber01-VHDL13_DWLI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 1827
ber01-VHDL13_DWLI_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 1860
ber01-VHDL13_DWLI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1773
ber01-VHDL13_DWMG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 2414
ber01-VHDL13_DWMG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 2955
ber01-VHDL13_DWMG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 3043
ber01-VHDL13_DWMG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 3433
ber01-VHDL13_DWMG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2987
ber01-VHDL13_DWMG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3420
ber01-VHDL13_DWMG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3421
ber01-VHDL13_DWMG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3293
ber01-VHDL13_DWMO_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 2276
ber01-VHDL13_DWMO_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 2892
ber01-VHDL13_DWMO_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 2686
ber01-VHDL13_DWMO_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 2949
ber01-VHDL13_DWMO_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2583
ber01-VHDL13_DWMO_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2978
ber01-VHDL13_DWMO_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2960
ber01-VHDL13_DWMO_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 2657
ber01-VHDL13_DWMP_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 2682
ber01-VHDL13_DWMP_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 3245
ber01-VHDL13_DWMP_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 3238
ber01-VHDL13_DWMP_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 3544
ber01-VHDL13_DWMP_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 3132
ber01-VHDL13_DWMP_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 3558
ber01-VHDL13_DWMP_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 3612
ber01-VHDL13_DWMP_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 3444
ber01-VHDL13_DWOG_160800-2601160800-dsw--0-ia5 16-Jan-2026 15:44:56 4337
ber01-VHDL13_DWOG_161700-2601161700-dsw--0-ia5 16-Jan-2026 19:00:02 4321
ber01-VHDL13_DWOG_170300-2601170300-dsw--0-ia5 17-Jan-2026 04:00:04 4543
ber01-VHDL13_DWOG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 4240
ber01-VHDL13_DWOG_171700-2601171700-dsw--0-ia5 17-Jan-2026 19:00:07 3874
ber01-VHDL13_DWOG_180300-2601180300-dsw--0-ia5 18-Jan-2026 04:00:02 4415
ber01-VHDL13_DWOG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 4154
ber01-VHDL13_DWOH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:28:16 2696
ber01-VHDL13_DWOH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:28:12 2721
ber01-VHDL13_DWOH_170400-2601170400-dsw--0-ia5 17-Jan-2026 05:58:12 2934
ber01-VHDL13_DWOH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:28:17 2827
ber01-VHDL13_DWOH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:11 2713
ber01-VHDL13_DWOH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 2938
ber01-VHDL13_DWOH_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:12 2755
ber01-VHDL13_DWOH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2474
ber01-VHDL13_DWOI_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:28:12 2754
ber01-VHDL13_DWOI_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:28:12 2679
ber01-VHDL13_DWOI_170400-2601170400-dsw--0-ia5 17-Jan-2026 05:58:12 2863
ber01-VHDL13_DWOI_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:28:11 2884
ber01-VHDL13_DWOI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:28:11 2910
ber01-VHDL13_DWOI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:28:11 3140
ber01-VHDL13_DWOI_180400-2601180400-dsw--0-ia5 18-Jan-2026 05:58:16 3027
ber01-VHDL13_DWOI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:28:16 2770
ber01-VHDL13_DWON_161422-2601161422-dsw--0-ia5 16-Jan-2026 14:23:01 4286
ber01-VHDL13_DWON_161544-2601161544-dsw--0-ia5 16-Jan-2026 15:44:26 3414
ber01-VHDL13_DWON_161819-2601161819-dsw--0-ia5 16-Jan-2026 18:19:52 3531
ber01-VHDL13_DWON_170149-2601170149-dsw--0-ia5 17-Jan-2026 01:49:17 4351
ber01-VHDL13_DWON_170342-2601170342-dsw--0-ia5 17-Jan-2026 03:42:47 3888
ber01-VHDL13_DWON_170611-2601170611-dsw--0-ia5 17-Jan-2026 06:11:01 3465
ber01-VHDL13_DWON_170656-2601170656-dsw--0-ia5 17-Jan-2026 06:56:36 3722
ber01-VHDL13_DWON_170920-2601170920-dsw--0-ia5 17-Jan-2026 09:20:58 3644
ber01-VHDL13_DWON_171000-2601171000-dsw--0-ia5 17-Jan-2026 10:00:47 3644
ber01-VHDL13_DWON_171555-2601171555-dsw--0-ia5 17-Jan-2026 15:55:28 3105
ber01-VHDL13_DWON_171729-2601171729-dsw--0-ia5 17-Jan-2026 17:29:42 3093
ber01-VHDL13_DWON_180330-2601180330-dsw--0-ia5 18-Jan-2026 03:30:09 3558
ber01-VHDL13_DWON_180617-2601180617-dsw--0-ia5 18-Jan-2026 06:17:56 3606
ber01-VHDL13_DWON_180715-2601180715-dsw--0-ia5 18-Jan-2026 07:15:31 3630
ber01-VHDL13_DWPG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 1806
ber01-VHDL13_DWPG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 1915
ber01-VHDL13_DWPG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 2018
ber01-VHDL13_DWPG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 1874
ber01-VHDL13_DWPG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2159
ber01-VHDL13_DWPG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2119
ber01-VHDL13_DWPG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2280
ber01-VHDL13_DWPG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1922
ber01-VHDL13_DWPH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 1833
ber01-VHDL13_DWPH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 2024
ber01-VHDL13_DWPH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:01 1825
ber01-VHDL13_DWPH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 1834
ber01-VHDL13_DWPH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2068
ber01-VHDL13_DWPH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2130
ber01-VHDL13_DWPH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:01 2412
ber01-VHDL13_DWPH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 1950
ber01-VHDL13_DWSG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:30:02 2404
ber01-VHDL13_DWSG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:30:03 2747
ber01-VHDL13_DWSG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:07 2735
ber01-VHDL13_DWSG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:30:13 2497
ber01-VHDL13_DWSG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:30:09 2120
ber01-VHDL13_DWSG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:30:03 2896
ber01-VHDL13_DWSG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:07 2664
ber01-VHDL13_DWSG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:30:05 2637
ber01-VHDL17_DWOG_161200-2601161200-dsw--0-ia5 16-Jan-2026 12:06:03 2356
ber01-VHDL17_DWOG_171200-2601171200-dsw--0-ia5 17-Jan-2026 12:34:58 3134
swis2-VHDL20_DWEG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 3120
swis2-VHDL20_DWEG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 3094
swis2-VHDL20_DWEG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:07 3345
swis2-VHDL20_DWEG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:02 3419
swis2-VHDL20_DWEG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3121
swis2-VHDL20_DWEG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3296
swis2-VHDL20_DWEG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3110
swis2-VHDL20_DWEG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3021
swis2-VHDL20_DWEH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 3751
swis2-VHDL20_DWEH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 3558
swis2-VHDL20_DWEH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:07 3675
swis2-VHDL20_DWEH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:02 3416
swis2-VHDL20_DWEH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3237
swis2-VHDL20_DWEH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3512
swis2-VHDL20_DWEH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3455
swis2-VHDL20_DWEH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3385
swis2-VHDL20_DWEI_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 3213
swis2-VHDL20_DWEI_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 3078
swis2-VHDL20_DWEI_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:07 3250
swis2-VHDL20_DWEI_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:02 3477
swis2-VHDL20_DWEI_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3297
swis2-VHDL20_DWEI_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3468
swis2-VHDL20_DWEI_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3413
swis2-VHDL20_DWEI_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:07 3364
swis2-VHDL20_DWHG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 3220
swis2-VHDL20_DWHG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 3299
swis2-VHDL20_DWHG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:07 3296
swis2-VHDL20_DWHG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 3756
swis2-VHDL20_DWHG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:06 3060
swis2-VHDL20_DWHG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3089
swis2-VHDL20_DWHG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2967
swis2-VHDL20_DWHG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3226
swis2-VHDL20_DWHH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 2835
swis2-VHDL20_DWHH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 2924
swis2-VHDL20_DWHH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:07 2927
swis2-VHDL20_DWHH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 2908
swis2-VHDL20_DWHH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:06 2415
swis2-VHDL20_DWHH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2716
swis2-VHDL20_DWHH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2716
swis2-VHDL20_DWHH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3065
swis2-VHDL20_DWLG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 2989
swis2-VHDL20_DWLG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 3164
swis2-VHDL20_DWLG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:11 3135
swis2-VHDL20_DWLG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 3546
swis2-VHDL20_DWLG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3519
swis2-VHDL20_DWLG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3556
swis2-VHDL20_DWLG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 3599
swis2-VHDL20_DWLG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3774
swis2-VHDL20_DWLH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 2197
swis2-VHDL20_DWLH_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 2198
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swis2-VHDL20_DWLH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 2410
swis2-VHDL20_DWLH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2408
swis2-VHDL20_DWLH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2344
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swis2-VHDL20_DWMG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:01 3432
swis2-VHDL20_DWMG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 4075
swis2-VHDL20_DWMG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3415
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swis2-VHDL20_DWMG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3840
swis2-VHDL20_DWMG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3965
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swis2-VHDL20_DWMO_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 3601
swis2-VHDL20_DWMO_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3015
swis2-VHDL20_DWMO_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3404
swis2-VHDL20_DWMO_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3383
swis2-VHDL20_DWMO_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3303
swis2-VHDL20_DWMP_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 3103
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swis2-VHDL20_DWMP_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:01 3627
swis2-VHDL20_DWMP_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 4192
swis2-VHDL20_DWMP_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 3556
swis2-VHDL20_DWMP_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:09 3982
swis2-VHDL20_DWMP_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 4030
swis2-VHDL20_DWMP_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 4105
swis2-VHDL20_DWPG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 2349
swis2-VHDL20_DWPG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:03 2296
swis2-VHDL20_DWPG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:11 2401
swis2-VHDL20_DWPG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 2407
swis2-VHDL20_DWPG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2692
swis2-VHDL20_DWPG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2505
swis2-VHDL20_DWPG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2623
swis2-VHDL20_DWPG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 2443
swis2-VHDL20_DWPH_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:06 2376
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swis2-VHDL20_DWPH_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:00:11 2210
swis2-VHDL20_DWPH_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:06 2366
swis2-VHDL20_DWPH_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2600
swis2-VHDL20_DWPH_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 2515
swis2-VHDL20_DWPH_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:00:12 2756
swis2-VHDL20_DWPH_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 2470
swis2-VHDL20_DWSG_161300-2601161300-dsw--0-ia5 16-Jan-2026 14:45:03 3278
swis2-VHDL20_DWSG_161800-2601161800-dsw--0-ia5 16-Jan-2026 19:45:01 2871
swis2-VHDL20_DWSG_170200-2601170200-dsw--0-ia5 17-Jan-2026 03:45:07 3147
swis2-VHDL20_DWSG_170400-2601170400-dsw--0-ia5 17-Jan-2026 06:15:07 3144
swis2-VHDL20_DWSG_170800-2601170800-dsw--0-ia5 17-Jan-2026 09:45:02 3103
swis2-VHDL20_DWSG_171300-2601171300-dsw--0-ia5 17-Jan-2026 14:45:09 2935
swis2-VHDL20_DWSG_171800-2601171800-dsw--0-ia5 17-Jan-2026 19:45:04 2531
swis2-VHDL20_DWSG_180200-2601180200-dsw--0-ia5 18-Jan-2026 03:45:04 3298
swis2-VHDL20_DWSG_180400-2601180400-dsw--0-ia5 18-Jan-2026 06:15:07 3072
swis2-VHDL20_DWSG_180800-2601180800-dsw--0-ia5 18-Jan-2026 09:45:03 3250
wst04-VHDL20_DWEG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:12 225648
wst04-VHDL20_DWEG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 226581
wst04-VHDL20_DWEG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:21 226677
wst04-VHDL20_DWEG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:22 228734
wst04-VHDL20_DWEG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 226789
wst04-VHDL20_DWEG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 227664
wst04-VHDL20_DWEG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:21 226667
wst04-VHDL20_DWEG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:21 228389
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wst04-VHDL20_DWEH_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 225393
wst04-VHDL20_DWEH_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:21 225124
wst04-VHDL20_DWEH_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:26 227181
wst04-VHDL20_DWEH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 225895
wst04-VHDL20_DWEH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 227353
wst04-VHDL20_DWEH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 226876
wst04-VHDL20_DWEH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:21 229329
wst04-VHDL20_DWEI_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:12 317092
wst04-VHDL20_DWEI_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 316579
wst04-VHDL20_DWEI_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:27 316685
wst04-VHDL20_DWEI_170800-2601170800-omedes--0.pdf 17-Jan-2026 10:01:01 318952
wst04-VHDL20_DWEI_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 318100
wst04-VHDL20_DWEI_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 318416
wst04-VHDL20_DWEI_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:11 318191
wst04-VHDL20_DWEI_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:27 323817
wst04-VHDL20_DWHG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:22 303379
wst04-VHDL20_DWHG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 303661
wst04-VHDL20_DWHG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:11 303788
wst04-VHDL20_DWHG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:22 314549
wst04-VHDL20_DWHG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 313204
wst04-VHDL20_DWHG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 312959
wst04-VHDL20_DWHG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:12 312643
wst04-VHDL20_DWHG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 311906
wst04-VHDL20_DWHH_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:16 291542
wst04-VHDL20_DWHH_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 291746
wst04-VHDL20_DWHH_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:11 291912
wst04-VHDL20_DWHH_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:16 293698
wst04-VHDL20_DWHH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 292938
wst04-VHDL20_DWHH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 293642
wst04-VHDL20_DWHH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:12 293500
wst04-VHDL20_DWHH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:11 295486
wst04-VHDL20_DWLG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:22 300713
wst04-VHDL20_DWLG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:22 301412
wst04-VHDL20_DWLG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:41 301319
wst04-VHDL20_DWLG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:26 302296
wst04-VHDL20_DWLG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:46:02 301794
wst04-VHDL20_DWLG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 301884
wst04-VHDL20_DWLG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 301965
wst04-VHDL20_DWLG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 305286
wst04-VHDL20_DWLH_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:22 300152
wst04-VHDL20_DWLH_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:26 301045
wst04-VHDL20_DWLH_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:41 300559
wst04-VHDL20_DWLH_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:26 309983
wst04-VHDL20_DWLH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 309466
wst04-VHDL20_DWLH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 309491
wst04-VHDL20_DWLH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 309537
wst04-VHDL20_DWLH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 309287
wst04-VHDL20_DWLI_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:26 307027
wst04-VHDL20_DWLI_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:22 308009
wst04-VHDL20_DWLI_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:41 307326
wst04-VHDL20_DWLI_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:32 309465
wst04-VHDL20_DWLI_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 308978
wst04-VHDL20_DWLI_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 309079
wst04-VHDL20_DWLI_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:41 309043
wst04-VHDL20_DWLI_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 317179
wst04-VHDL20_DWMG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:16 523657
wst04-VHDL20_DWMG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 524951
wst04-VHDL20_DWMG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:21 524485
wst04-VHDL20_DWMG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:16 525492
wst04-VHDL20_DWMG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 523530
wst04-VHDL20_DWMG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 525430
wst04-VHDL20_DWMG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 524956
wst04-VHDL20_DWMG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:23 538966
wst04-VHDL20_DWMO_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:16 416817
wst04-VHDL20_DWMO_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 417562
wst04-VHDL20_DWMO_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:17 417311
wst04-VHDL20_DWMO_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:12 424742
wst04-VHDL20_DWMO_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 422767
wst04-VHDL20_DWMO_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 423798
wst04-VHDL20_DWMO_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 424218
wst04-VHDL20_DWMO_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 433711
wst04-VHDL20_DWMP_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:16 545997
wst04-VHDL20_DWMP_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:22 545741
wst04-VHDL20_DWMP_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:21 546542
wst04-VHDL20_DWMP_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:16 555153
wst04-VHDL20_DWMP_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:16 552893
wst04-VHDL20_DWMP_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:17 552739
wst04-VHDL20_DWMP_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:17 553667
wst04-VHDL20_DWMP_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:17 560290
wst04-VHDL20_DWPG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:26 300607
wst04-VHDL20_DWPG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:26 301195
wst04-VHDL20_DWPG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:31 300844
wst04-VHDL20_DWPG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:26 349573
wst04-VHDL20_DWPG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:46:02 305189
wst04-VHDL20_DWPG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:25 304683
wst04-VHDL20_DWPG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:31 305166
wst04-VHDL20_DWPG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:31 352372
wst04-VHDL20_DWPH_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:22 265935
wst04-VHDL20_DWPH_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:22 221451
wst04-VHDL20_DWPH_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:00:31 221292
wst04-VHDL20_DWPH_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:26 266867
wst04-VHDL20_DWPH_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:22 266579
wst04-VHDL20_DWPH_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:21 222068
wst04-VHDL20_DWPH_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:00:31 222385
wst04-VHDL20_DWPH_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:27 267149
wst04-VHDL20_DWSG_161300-2601161300-omedes--0.pdf 16-Jan-2026 14:45:11 335757
wst04-VHDL20_DWSG_161800-2601161800-omedes--0.pdf 16-Jan-2026 19:45:12 334553
wst04-VHDL20_DWSG_170200-2601170200-omedes--0.pdf 17-Jan-2026 03:45:20 334885
wst04-VHDL20_DWSG_170400-2601170400-omedes--0.pdf 17-Jan-2026 06:15:17 335472
wst04-VHDL20_DWSG_170800-2601170800-omedes--0.pdf 17-Jan-2026 09:45:12 340843
wst04-VHDL20_DWSG_171300-2601171300-omedes--0.pdf 17-Jan-2026 14:45:12 340651
wst04-VHDL20_DWSG_171800-2601171800-omedes--0.pdf 17-Jan-2026 19:45:12 339884
wst04-VHDL20_DWSG_180200-2601180200-omedes--0.pdf 18-Jan-2026 03:45:13 340562
wst04-VHDL20_DWSG_180400-2601180400-omedes--0.pdf 18-Jan-2026 06:15:11 340211
wst04-VHDL20_DWSG_180800-2601180800-omedes--0.pdf 18-Jan-2026 09:45:11 338948