Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Sep-2026 11:46:30 4007
FPDL13_DWMZ_230600 23-Sep-2026 13:51:54 2996
SXDL31_DWAV_220800 22-Sep-2026 07:17:25 11017
SXDL31_DWAV_221800 22-Sep-2026 15:21:44 6553
SXDL31_DWAV_230800 23-Sep-2026 07:30:36 6674
SXDL31_DWAV_231800 23-Sep-2026 18:37:30 4215
SXDL31_DWAV_LATEST 23-Sep-2026 18:37:30 4215
SXDL33_DWAV_220000 22-Sep-2026 09:40:00 4885
SXDL33_DWAV_230000 23-Sep-2026 09:33:14 9800
SXDL33_DWAV_LATEST 23-Sep-2026 09:33:14 9800
ber01-FWDL39_DWMS_221200-2609221200-dsw--0-ia5 22-Sep-2026 11:23:18 1522
ber01-FWDL39_DWMS_231200-2609231200-dsw--0-ia5 23-Sep-2026 11:19:29 2366
ber01-VHDL13_DWEG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:28:18 2910
ber01-VHDL13_DWEG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2931
ber01-VHDL13_DWEH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:28:18 3106
ber01-VHDL13_DWEH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2902
ber01-VHDL13_DWEI_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:28:14 2623
ber01-VHDL13_DWEI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:28:17 2619
ber01-VHDL13_DWHG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 2890
ber01-VHDL13_DWHG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3276
ber01-VHDL13_DWHH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 2764
ber01-VHDL13_DWHH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3234
ber01-VHDL13_DWLG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2117
ber01-VHDL13_DWLG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2568
ber01-VHDL13_DWLH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2330
ber01-VHDL13_DWLH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2534
ber01-VHDL13_DWLI_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2217
ber01-VHDL13_DWLI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2164
ber01-VHDL13_DWMO_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 2661
ber01-VHDL13_DWMO_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3363
ber01-VHDL13_DWMP_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:14 2760
ber01-VHDL13_DWMP_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 3342
ber01-VHDL13_DWOG_220300-2609220300-dsw--0-ia5 22-Sep-2026 03:00:20 3497
ber01-VHDL13_DWOG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 3802
ber01-VHDL13_DWOG_221700-2609221700-dsw--0-ia5 22-Sep-2026 18:00:04 4161
ber01-VHDL13_DWOG_230300-2609230300-dsw--0-ia5 23-Sep-2026 03:00:36 4597
ber01-VHDL13_DWOG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 4281
ber01-VHDL13_DWOG_231700-2609231700-dsw--0-ia5 23-Sep-2026 18:00:03 3771
ber01-VHDL13_DWON_212223-2609212223-dsw--0-ia5 21-Sep-2026 22:24:03 4161
ber01-VHDL13_DWON_220056-2609220056-dsw--0-ia5 22-Sep-2026 00:56:58 4161
ber01-VHDL13_DWON_220232-2609220232-dsw--0-ia5 22-Sep-2026 02:32:16 4161
ber01-VHDL13_DWON_220509-2609220509-dsw--0-ia5 22-Sep-2026 05:09:33 3940
ber01-VHDL13_DWON_220551-2609220551-dsw--0-ia5 22-Sep-2026 05:51:53 3940
ber01-VHDL13_DWON_220754-2609220754-dsw--0-ia5 22-Sep-2026 07:55:13 3940
ber01-VHDL13_DWON_221452-2609221452-dsw--0-ia5 22-Sep-2026 14:54:05 3731
ber01-VHDL13_DWON_221531-2609221531-dsw--0-ia5 22-Sep-2026 15:31:55 3731
ber01-VHDL13_DWON_221634-2609221634-dsw--0-ia5 22-Sep-2026 16:34:40 3731
ber01-VHDL13_DWON_221715-2609221715-dsw--0-ia5 22-Sep-2026 17:15:08 3731
ber01-VHDL13_DWON_230017-2609230017-dsw--0-ia5 23-Sep-2026 00:17:29 4559
ber01-VHDL13_DWON_230105-2609230105-dsw--0-ia5 23-Sep-2026 01:06:06 4559
ber01-VHDL13_DWON_230348-2609230348-dsw--0-ia5 23-Sep-2026 03:48:23 4559
ber01-VHDL13_DWON_230529-2609230529-dsw--0-ia5 23-Sep-2026 05:29:51 4169
ber01-VHDL13_DWON_230556-2609230556-dsw--0-ia5 23-Sep-2026 05:56:28 4165
ber01-VHDL13_DWON_230629-2609230629-dsw--0-ia5 23-Sep-2026 06:29:54 4165
ber01-VHDL13_DWON_230630-2609230630-dsw--0-ia5 23-Sep-2026 06:30:14 4165
ber01-VHDL13_DWON_230758-2609230758-dsw--0-ia5 23-Sep-2026 07:58:29 4215
ber01-VHDL13_DWON_230808-2609230808-dsw--0-ia5 23-Sep-2026 08:08:48 4215
ber01-VHDL13_DWON_231432-2609231432-dsw--0-ia5 23-Sep-2026 14:33:18 4273
ber01-VHDL13_DWON_231456-2609231456-dsw--0-ia5 23-Sep-2026 14:58:02 4273
ber01-VHDL13_DWON_231729-2609231729-dsw--0-ia5 23-Sep-2026 17:30:09 3422
ber01-VHDL13_DWON_231838-2609231838-dsw--0-ia5 23-Sep-2026 18:38:36 3409
ber01-VHDL13_DWPG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2162
ber01-VHDL13_DWPG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2083
ber01-VHDL13_DWPH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2346
ber01-VHDL13_DWPH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 2713
ber01-VHDL13_DWSG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 2394
ber01-VHDL13_DWSG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 2266
ber01-VHDL17_DWOG_221200-2609221200-dsw--0-ia5 22-Sep-2026 11:13:13 2948
ber01-VHDL17_DWOG_231200-2609231200-dsw--0-ia5 23-Sep-2026 11:41:04 3707
swis2-VHDL20_DWEG_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:05 1346
swis2-VHDL20_DWEG_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:01:18 1182
swis2-VHDL20_DWEG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 1403
swis2-VHDL20_DWEG_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1496
swis2-VHDL20_DWEG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 1073
swis2-VHDL20_DWEG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 1057
swis2-VHDL20_DWEG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1279
swis2-VHDL20_DWEG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:03 1210
swis2-VHDL20_DWEH_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:05 1324
swis2-VHDL20_DWEH_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:01:18 1194
swis2-VHDL20_DWEH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 1430
swis2-VHDL20_DWEH_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1489
swis2-VHDL20_DWEH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 1321
swis2-VHDL20_DWEH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 1305
swis2-VHDL20_DWEH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1251
swis2-VHDL20_DWEH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1242
swis2-VHDL20_DWEI_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:05 943
swis2-VHDL20_DWEI_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:01:18 921
swis2-VHDL20_DWEI_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:14 1137
swis2-VHDL20_DWEI_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1148
swis2-VHDL20_DWEI_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:09 882
swis2-VHDL20_DWEI_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:01:13 882
swis2-VHDL20_DWEI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:03 1090
swis2-VHDL20_DWEI_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:03 1027
swis2-VHDL20_DWHG_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:45:54 1371
swis2-VHDL20_DWHG_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:09 1355
swis2-VHDL20_DWHG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:46:04 1428
swis2-VHDL20_DWHG_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:45:15 1482
swis2-VHDL20_DWHG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:48:13 1399
swis2-VHDL20_DWHG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:10 1307
swis2-VHDL20_DWHG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:45:54 1547
swis2-VHDL20_DWHG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:45:19 1645
swis2-VHDL20_DWHH_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:45:54 1492
swis2-VHDL20_DWHH_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:09 1404
swis2-VHDL20_DWHH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:46:04 1480
swis2-VHDL20_DWHH_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:45:15 1540
swis2-VHDL20_DWHH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:48:13 1567
swis2-VHDL20_DWHH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1449
swis2-VHDL20_DWHH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:45:54 1766
swis2-VHDL20_DWHH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:45:19 1902
swis2-VHDL20_DWLG_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:25 783
swis2-VHDL20_DWLG_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 771
swis2-VHDL20_DWLG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:33 888
swis2-VHDL20_DWLG_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:31:14 1081
swis2-VHDL20_DWLG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1133
swis2-VHDL20_DWLG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1104
swis2-VHDL20_DWLG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1214
swis2-VHDL20_DWLG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1091
swis2-VHDL20_DWLH_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:25 940
swis2-VHDL20_DWLH_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 923
swis2-VHDL20_DWLH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:33 1040
swis2-VHDL20_DWLH_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:31:14 1234
swis2-VHDL20_DWLH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1264
swis2-VHDL20_DWLH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1200
swis2-VHDL20_DWLH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1310
swis2-VHDL20_DWLH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1141
swis2-VHDL20_DWLI_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:25 886
swis2-VHDL20_DWLI_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 881
swis2-VHDL20_DWLI_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:33 998
swis2-VHDL20_DWLI_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:31:14 1190
swis2-VHDL20_DWLI_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1255
swis2-VHDL20_DWLI_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 848
swis2-VHDL20_DWLI_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 958
swis2-VHDL20_DWLI_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 898
swis2-VHDL20_DWMO_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:09 1120
swis2-VHDL20_DWMO_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:03 938
swis2-VHDL20_DWMO_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 1197
swis2-VHDL20_DWMO_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1322
swis2-VHDL20_DWMO_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 1168
swis2-VHDL20_DWMO_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:03 1249
swis2-VHDL20_DWMO_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 1598
swis2-VHDL20_DWMO_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1466
swis2-VHDL20_DWMP_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:09 1085
swis2-VHDL20_DWMP_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:03 918
swis2-VHDL20_DWMP_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:13 1205
swis2-VHDL20_DWMP_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1353
swis2-VHDL20_DWMP_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 1414
swis2-VHDL20_DWMP_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:03 1494
swis2-VHDL20_DWMP_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 1596
swis2-VHDL20_DWMP_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1735
swis2-VHDL20_DWPG_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:25 830
swis2-VHDL20_DWPG_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 787
swis2-VHDL20_DWPG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:33 904
swis2-VHDL20_DWPG_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:31:14 996
swis2-VHDL20_DWPG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 973
swis2-VHDL20_DWPG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 891
swis2-VHDL20_DWPG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1005
swis2-VHDL20_DWPG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1039
swis2-VHDL20_DWPH_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:25 959
swis2-VHDL20_DWPH_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 939
swis2-VHDL20_DWPH_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:33 1056
swis2-VHDL20_DWPH_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:31:14 1089
swis2-VHDL20_DWPH_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:34 1213
swis2-VHDL20_DWPH_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1103
swis2-VHDL20_DWPH_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:26 1213
swis2-VHDL20_DWPH_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:31:26 1153
swis2-VHDL20_DWSG_220200-2609220200-dsw--0-ia5 22-Sep-2026 02:30:03 950
swis2-VHDL20_DWSG_220400-2609220400-dsw--0-ia5 22-Sep-2026 05:00:13 994
swis2-VHDL20_DWSG_220800-2609220800-dsw--0-ia5 22-Sep-2026 08:30:02 1049
swis2-VHDL20_DWSG_221800-2609221800-dsw--0-ia5 22-Sep-2026 18:30:04 1137
swis2-VHDL20_DWSG_230200-2609230200-dsw--0-ia5 23-Sep-2026 02:30:03 934
swis2-VHDL20_DWSG_230400-2609230400-dsw--0-ia5 23-Sep-2026 05:00:14 1086
swis2-VHDL20_DWSG_230800-2609230800-dsw--0-ia5 23-Sep-2026 08:30:09 977
swis2-VHDL20_DWSG_231800-2609231800-dsw--0-ia5 23-Sep-2026 18:30:09 1246
wst04-VHDL20_DWEG_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:15 241978
wst04-VHDL20_DWEG_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 241683
wst04-VHDL20_DWEG_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:13 242581
wst04-VHDL20_DWEG_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:20 243346
wst04-VHDL20_DWEG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 241557
wst04-VHDL20_DWEG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 241394
wst04-VHDL20_DWEG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 242227
wst04-VHDL20_DWEG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 242877
wst04-VHDL20_DWEH_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:15 235103
wst04-VHDL20_DWEH_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 235139
wst04-VHDL20_DWEH_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:13 236098
wst04-VHDL20_DWEH_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:14 236259
wst04-VHDL20_DWEH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 235573
wst04-VHDL20_DWEH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 235401
wst04-VHDL20_DWEH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 235710
wst04-VHDL20_DWEH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:13 235291
wst04-VHDL20_DWEI_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:15 347016
wst04-VHDL20_DWEI_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:19 346738
wst04-VHDL20_DWEI_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:14 347673
wst04-VHDL20_DWEI_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:20 347423
wst04-VHDL20_DWEI_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:13 346755
wst04-VHDL20_DWEI_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:20 346519
wst04-VHDL20_DWEI_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 346697
wst04-VHDL20_DWEI_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 347158
wst04-VHDL20_DWHG_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:45:54 348594
wst04-VHDL20_DWHG_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 348864
wst04-VHDL20_DWHG_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:46:04 350645
wst04-VHDL20_DWHG_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:45:15 349168
wst04-VHDL20_DWHG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:48:14 349085
wst04-VHDL20_DWHG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 348689
wst04-VHDL20_DWHG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:45:54 350442
wst04-VHDL20_DWHG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:45:19 349964
wst04-VHDL20_DWHH_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:45:54 334933
wst04-VHDL20_DWHH_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 230763
wst04-VHDL20_DWHH_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:46:04 335802
wst04-VHDL20_DWHH_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:45:15 335751
wst04-VHDL20_DWHH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:48:13 335480
wst04-VHDL20_DWHH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 230956
wst04-VHDL20_DWHH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:45:54 336318
wst04-VHDL20_DWHH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:45:19 336288
wst04-VHDL20_DWLG_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:38 332985
wst04-VHDL20_DWLG_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:44 333432
wst04-VHDL20_DWLG_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:50 333557
wst04-VHDL20_DWLG_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:31:24 334088
wst04-VHDL20_DWLG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 333983
wst04-VHDL20_DWLG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 333781
wst04-VHDL20_DWLG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 333954
wst04-VHDL20_DWLG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 334185
wst04-VHDL20_DWLH_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 338070
wst04-VHDL20_DWLH_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:44 338504
wst04-VHDL20_DWLH_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:50 338744
wst04-VHDL20_DWLH_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:31:24 338188
wst04-VHDL20_DWLH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 337832
wst04-VHDL20_DWLH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 337841
wst04-VHDL20_DWLH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 338036
wst04-VHDL20_DWLH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 338171
wst04-VHDL20_DWLI_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 338290
wst04-VHDL20_DWLI_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:44 338726
wst04-VHDL20_DWLI_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:50 383393
wst04-VHDL20_DWLI_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:31:24 339361
wst04-VHDL20_DWLI_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 339265
wst04-VHDL20_DWLI_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:43 338244
wst04-VHDL20_DWLI_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 383053
wst04-VHDL20_DWLI_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 338729
wst04-VHDL20_DWMO_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:15 455353
wst04-VHDL20_DWMO_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 455357
wst04-VHDL20_DWMO_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:33 455399
wst04-VHDL20_DWMO_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:18 354804
wst04-VHDL20_DWMO_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:17 456039
wst04-VHDL20_DWMO_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 456301
wst04-VHDL20_DWMO_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 456861
wst04-VHDL20_DWMO_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 354421
wst04-VHDL20_DWMP_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 561725
wst04-VHDL20_DWMP_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:19 561835
wst04-VHDL20_DWMP_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:33 460700
wst04-VHDL20_DWMP_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:18 461718
wst04-VHDL20_DWMP_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:17 563512
wst04-VHDL20_DWMP_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:20 563777
wst04-VHDL20_DWMP_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 461555
wst04-VHDL20_DWMP_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:19 461462
wst04-VHDL20_DWPG_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 244488
wst04-VHDL20_DWPG_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:34 348497
wst04-VHDL20_DWPG_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:52 393104
wst04-VHDL20_DWPG_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:31:30 347999
wst04-VHDL20_DWPG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:34 244085
wst04-VHDL20_DWPG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:34 347730
wst04-VHDL20_DWPG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:53 392322
wst04-VHDL20_DWPG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 348567
wst04-VHDL20_DWPH_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 244369
wst04-VHDL20_DWPH_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:34 244852
wst04-VHDL20_DWPH_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:50 244980
wst04-VHDL20_DWPH_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:31:24 243879
wst04-VHDL20_DWPH_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:23 243788
wst04-VHDL20_DWPH_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:34 243560
wst04-VHDL20_DWPH_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:51 243671
wst04-VHDL20_DWPH_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:31:28 243501
wst04-VHDL20_DWSG_220200-2609220200-omedes--0.pdf 22-Sep-2026 02:30:25 346679
wst04-VHDL20_DWSG_220400-2609220400-omedes--0.pdf 22-Sep-2026 05:00:13 347956
wst04-VHDL20_DWSG_220800-2609220800-omedes--0.pdf 22-Sep-2026 08:30:33 348091
wst04-VHDL20_DWSG_221800-2609221800-omedes--0.pdf 22-Sep-2026 18:30:14 347995
wst04-VHDL20_DWSG_230200-2609230200-omedes--0.pdf 23-Sep-2026 02:30:15 347625
wst04-VHDL20_DWSG_230400-2609230400-omedes--0.pdf 23-Sep-2026 05:00:14 347599
wst04-VHDL20_DWSG_230800-2609230800-omedes--0.pdf 23-Sep-2026 08:30:26 346540
wst04-VHDL20_DWSG_231800-2609231800-omedes--0.pdf 23-Sep-2026 18:30:13 347477