Index of /weather/text_forecasts/txt/
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FPDL13_DWMZ_100600 10-Jul-2026 14:11:19 4131
FPDL13_DWMZ_110600 11-Jul-2026 10:57:49 2967
SXDL31_DWAV_100800 10-Jul-2026 07:44:32 10139
SXDL31_DWAV_101800 10-Jul-2026 16:12:34 4208
SXDL31_DWAV_110800 11-Jul-2026 07:07:19 6415
SXDL31_DWAV_111800 11-Jul-2026 16:03:14 5170
SXDL31_DWAV_LATEST 11-Jul-2026 16:03:14 5170
SXDL33_DWAV_100000 10-Jul-2026 09:50:10 6024
SXDL33_DWAV_110000 11-Jul-2026 10:20:08 7020
SXDL33_DWAV_LATEST 11-Jul-2026 10:20:08 7020
ber01-FWDL39_DWMS_101200-2607101200-dsw--0-ia5 10-Jul-2026 11:28:38 1450
ber01-FWDL39_DWMS_111200-2607111200-dsw--0-ia5 11-Jul-2026 11:58:41 1172
ber01-VHDL13_DWEG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:12 2073
ber01-VHDL13_DWEG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2114
ber01-VHDL13_DWEH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:16 2072
ber01-VHDL13_DWEH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2105
ber01-VHDL13_DWEI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:28:16 1906
ber01-VHDL13_DWEI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2061
ber01-VHDL13_DWHG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2726
ber01-VHDL13_DWHG_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:44:03 2695
ber01-VHDL13_DWHG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2694
ber01-VHDL13_DWHH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2646
ber01-VHDL13_DWHH_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:44:52 2650
ber01-VHDL13_DWHH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2833
ber01-VHDL13_DWLG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2023
ber01-VHDL13_DWLG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2003
ber01-VHDL13_DWLH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1903
ber01-VHDL13_DWLH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1871
ber01-VHDL13_DWLI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1873
ber01-VHDL13_DWLI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1753
ber01-VHDL13_DWMO_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2104
ber01-VHDL13_DWMO_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:42 2118
ber01-VHDL13_DWMO_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:14 2580
ber01-VHDL13_DWMP_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2092
ber01-VHDL13_DWMP_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:52 2098
ber01-VHDL13_DWMP_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2339
ber01-VHDL13_DWOG_100300-2607100300-dsw--0-ia5 10-Jul-2026 03:00:02 2569
ber01-VHDL13_DWOG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 2497
ber01-VHDL13_DWOG_101700-2607101700-dsw--0-ia5 10-Jul-2026 18:00:01 2345
ber01-VHDL13_DWOG_110300-2607110300-dsw--0-ia5 11-Jul-2026 03:00:00 3384
ber01-VHDL13_DWOG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2885
ber01-VHDL13_DWOG_111700-2607111700-dsw--0-ia5 11-Jul-2026 18:00:01 2394
ber01-VHDL13_DWON_100017-2607100017-dsw--0-ia5 10-Jul-2026 00:17:57 2615
ber01-VHDL13_DWON_100215-2607100215-dsw--0-ia5 10-Jul-2026 02:15:21 2615
ber01-VHDL13_DWON_100530-2607100530-dsw--0-ia5 10-Jul-2026 05:30:12 3065
ber01-VHDL13_DWON_100627-2607100627-dsw--0-ia5 10-Jul-2026 06:27:51 3065
ber01-VHDL13_DWON_101140-2607101140-dsw--0-ia5 10-Jul-2026 11:40:16 3065
ber01-VHDL13_DWON_101505-2607101505-dsw--0-ia5 10-Jul-2026 15:05:32 2784
ber01-VHDL13_DWON_101629-2607101629-dsw--0-ia5 10-Jul-2026 16:29:52 2861
ber01-VHDL13_DWON_101632-2607101632-dsw--0-ia5 10-Jul-2026 16:32:11 2857
ber01-VHDL13_DWON_101819-2607101819-dsw--0-ia5 10-Jul-2026 18:20:01 3369
ber01-VHDL13_DWON_102143-2607102143-dsw--0-ia5 10-Jul-2026 21:43:41 3362
ber01-VHDL13_DWON_110006-2607110006-dsw--0-ia5 11-Jul-2026 00:06:31 3846
ber01-VHDL13_DWON_110150-2607110150-dsw--0-ia5 11-Jul-2026 01:50:57 4028
ber01-VHDL13_DWON_110244-2607110244-dsw--0-ia5 11-Jul-2026 02:44:56 4028
ber01-VHDL13_DWON_110512-2607110512-dsw--0-ia5 11-Jul-2026 05:12:11 3949
ber01-VHDL13_DWON_110609-2607110609-dsw--0-ia5 11-Jul-2026 06:09:17 3625
ber01-VHDL13_DWON_110751-2607110751-dsw--0-ia5 11-Jul-2026 07:51:52 3480
ber01-VHDL13_DWON_111458-2607111458-dsw--0-ia5 11-Jul-2026 14:58:19 3104
ber01-VHDL13_DWON_111500-2607111500-dsw--0-ia5 11-Jul-2026 15:00:50 3104
ber01-VHDL13_DWON_111701-2607111701-dsw--0-ia5 11-Jul-2026 17:01:52 2832
ber01-VHDL13_DWON_111913-2607111913-dsw--0-ia5 11-Jul-2026 19:13:17 3744
ber01-VHDL13_DWPG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2005
ber01-VHDL13_DWPG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2265
ber01-VHDL13_DWPH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1969
ber01-VHDL13_DWPH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1998
ber01-VHDL13_DWSG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 2561
ber01-VHDL13_DWSG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2604
ber01-VHDL13_DWSG_110800_COR-2607110800-dsw--0-ia5 11-Jul-2026 14:54:06 2904
ber01-VHDL17_DWOG_101200-2607101200-dsw--0-ia5 10-Jul-2026 11:22:02 3022
ber01-VHDL17_DWOG_111200-2607111200-dsw--0-ia5 11-Jul-2026 11:55:52 2815
swis2-VHDL20_DWEG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 737
swis2-VHDL20_DWEG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 724
swis2-VHDL20_DWEG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 888
swis2-VHDL20_DWEG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 923
swis2-VHDL20_DWEG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 743
swis2-VHDL20_DWEG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:16 743
swis2-VHDL20_DWEG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 913
swis2-VHDL20_DWEG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 958
swis2-VHDL20_DWEH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 770
swis2-VHDL20_DWEH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 757
swis2-VHDL20_DWEH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 915
swis2-VHDL20_DWEH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 949
swis2-VHDL20_DWEH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 757
swis2-VHDL20_DWEH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:22 757
swis2-VHDL20_DWEH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 921
swis2-VHDL20_DWEH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1112
swis2-VHDL20_DWEI_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 759
swis2-VHDL20_DWEI_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:01:21 746
swis2-VHDL20_DWEI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 910
swis2-VHDL20_DWEI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 945
swis2-VHDL20_DWEI_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 765
swis2-VHDL20_DWEI_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:22 765
swis2-VHDL20_DWEI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 935
swis2-VHDL20_DWEI_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1118
swis2-VHDL20_DWHG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:45:13 931
swis2-VHDL20_DWHG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 928
swis2-VHDL20_DWHG_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:45:28 1013
swis2-VHDL20_DWHG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 966
swis2-VHDL20_DWHG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:45:47 968
swis2-VHDL20_DWHG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 965
swis2-VHDL20_DWHG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:45:06 1047
swis2-VHDL20_DWHG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:45:44 1572
swis2-VHDL20_DWHH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:45:13 934
swis2-VHDL20_DWHH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 934
swis2-VHDL20_DWHH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:45:28 1038
swis2-VHDL20_DWHH_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 08:45:31 1042
swis2-VHDL20_DWHH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 972
swis2-VHDL20_DWHH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:45:47 959
swis2-VHDL20_DWHH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 959
swis2-VHDL20_DWHH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:45:06 1021
swis2-VHDL20_DWHH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:45:44 1595
swis2-VHDL20_DWLG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 760
swis2-VHDL20_DWLG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 745
swis2-VHDL20_DWLG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 825
swis2-VHDL20_DWLG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 825
swis2-VHDL20_DWLG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 740
swis2-VHDL20_DWLG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:10 759
swis2-VHDL20_DWLG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 836
swis2-VHDL20_DWLG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1084
swis2-VHDL20_DWLH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 769
swis2-VHDL20_DWLH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 754
swis2-VHDL20_DWLH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 834
swis2-VHDL20_DWLH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 834
swis2-VHDL20_DWLH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 749
swis2-VHDL20_DWLH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 768
swis2-VHDL20_DWLH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 845
swis2-VHDL20_DWLH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1093
swis2-VHDL20_DWLI_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 762
swis2-VHDL20_DWLI_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 747
swis2-VHDL20_DWLI_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 827
swis2-VHDL20_DWLI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 827
swis2-VHDL20_DWLI_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 742
swis2-VHDL20_DWLI_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 761
swis2-VHDL20_DWLI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 838
swis2-VHDL20_DWLI_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1086
swis2-VHDL20_DWMO_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 740
swis2-VHDL20_DWMO_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:01 741
swis2-VHDL20_DWMO_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 855
swis2-VHDL20_DWMO_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:42 2773
swis2-VHDL20_DWMO_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 905
swis2-VHDL20_DWMO_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 800
swis2-VHDL20_DWMO_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:02 812
swis2-VHDL20_DWMO_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:14 973
swis2-VHDL20_DWMO_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1124
swis2-VHDL20_DWMP_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 741
swis2-VHDL20_DWMP_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:01 741
swis2-VHDL20_DWMP_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:16 854
swis2-VHDL20_DWMP_100800_COR-2607100800-dsw--0-ia5 10-Jul-2026 09:13:52 2783
swis2-VHDL20_DWMP_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 877
swis2-VHDL20_DWMP_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 800
swis2-VHDL20_DWMP_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:02 808
swis2-VHDL20_DWMP_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 957
swis2-VHDL20_DWMP_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1180
swis2-VHDL20_DWPG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 778
swis2-VHDL20_DWPG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 763
swis2-VHDL20_DWPG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 843
swis2-VHDL20_DWPG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 843
swis2-VHDL20_DWPG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 758
swis2-VHDL20_DWPG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 1033
swis2-VHDL20_DWPG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 1246
swis2-VHDL20_DWPG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1244
swis2-VHDL20_DWPH_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:21 778
swis2-VHDL20_DWPH_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:11 763
swis2-VHDL20_DWPH_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:21 840
swis2-VHDL20_DWPH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 840
swis2-VHDL20_DWPH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 758
swis2-VHDL20_DWPH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:10 777
swis2-VHDL20_DWPH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 943
swis2-VHDL20_DWPH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1191
swis2-VHDL20_DWSG_100200-2607100200-dsw--0-ia5 10-Jul-2026 02:30:06 751
swis2-VHDL20_DWSG_100400-2607100400-dsw--0-ia5 10-Jul-2026 05:00:17 909
swis2-VHDL20_DWSG_100800-2607100800-dsw--0-ia5 10-Jul-2026 08:30:04 1106
swis2-VHDL20_DWSG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 850
swis2-VHDL20_DWSG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:06 814
swis2-VHDL20_DWSG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 811
swis2-VHDL20_DWSG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 907
swis2-VHDL20_DWSG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1235
wst04-VHDL20_DWEG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 234130
wst04-VHDL20_DWEG_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 233977
wst04-VHDL20_DWEG_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 234756
wst04-VHDL20_DWEG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:13 236532
wst04-VHDL20_DWEG_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 235385
wst04-VHDL20_DWEG_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 235040
wst04-VHDL20_DWEG_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:13 235971
wst04-VHDL20_DWEG_111800-2607111800-omedes--0.pdf 11-Jul-2026 18:30:49 237239
wst04-VHDL20_DWEH_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 236790
wst04-VHDL20_DWEH_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 236916
wst04-VHDL20_DWEH_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 237713
wst04-VHDL20_DWEH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 238400
wst04-VHDL20_DWEH_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 237615
wst04-VHDL20_DWEH_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 237482
wst04-VHDL20_DWEH_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:14 238388
wst04-VHDL20_DWEH_111800-2607111800-omedes--0.pdf 11-Jul-2026 18:30:49 235008
wst04-VHDL20_DWEI_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:30:11 337898
wst04-VHDL20_DWEI_100400-2607100400-omedes--0.pdf 10-Jul-2026 05:00:11 337749
wst04-VHDL20_DWEI_100800-2607100800-omedes--0.pdf 10-Jul-2026 08:30:16 338003
wst04-VHDL20_DWEI_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 335245
wst04-VHDL20_DWEI_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 334696
wst04-VHDL20_DWEI_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 334280
wst04-VHDL20_DWEI_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:16 334682
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wst04-VHDL20_DWHG_100200-2607100200-omedes--0.pdf 10-Jul-2026 02:45:13 346356
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