Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Aug-2026 10:17:29 3483
FPDL13_DWMZ_230600 23-Aug-2026 11:30:08 6653
SXDL31_DWAV_221800 22-Aug-2026 16:42:34 5571
SXDL31_DWAV_230800 23-Aug-2026 07:11:18 6834
SXDL31_DWAV_231800 23-Aug-2026 15:32:39 5097
SXDL31_DWAV_LATEST 23-Aug-2026 15:32:39 5097
SXDL33_DWAV_220000 22-Aug-2026 09:27:29 7174
SXDL33_DWAV_230000 23-Aug-2026 10:08:24 7782
SXDL33_DWAV_LATEST 23-Aug-2026 10:08:24 7782
ber01-FWDL39_DWMS_221200-2608221200-dsw--0-ia5 22-Aug-2026 11:54:01 1539
ber01-FWDL39_DWMS_231200-2608231200-dsw--0-ia5 23-Aug-2026 10:49:39 1282
ber01-VHDL13_DWEG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:13 2738
ber01-VHDL13_DWEG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3141
ber01-VHDL13_DWEH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:19 2826
ber01-VHDL13_DWEH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3113
ber01-VHDL13_DWEI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:28:19 2868
ber01-VHDL13_DWEI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:28:19 3452
ber01-VHDL13_DWHG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3009
ber01-VHDL13_DWHG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2718
ber01-VHDL13_DWHH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3234
ber01-VHDL13_DWHH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2668
ber01-VHDL13_DWLG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1968
ber01-VHDL13_DWLG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2212
ber01-VHDL13_DWLH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2100
ber01-VHDL13_DWLH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2348
ber01-VHDL13_DWLI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1951
ber01-VHDL13_DWLI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2497
ber01-VHDL13_DWMO_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2626
ber01-VHDL13_DWMO_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2985
ber01-VHDL13_DWMP_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2571
ber01-VHDL13_DWMP_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2842
ber01-VHDL13_DWOG_221700-2608221700-dsw--0-ia5 22-Aug-2026 18:00:04 3566
ber01-VHDL13_DWOG_230300-2608230300-dsw--0-ia5 23-Aug-2026 03:00:07 3581
ber01-VHDL13_DWOG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3677
ber01-VHDL13_DWOG_231700-2608231700-dsw--0-ia5 23-Aug-2026 18:00:07 3391
ber01-VHDL13_DWOG_240300-2608240300-dsw--0-ia5 24-Aug-2026 03:00:09 2855
ber01-VHDL13_DWOG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 2993
ber01-VHDL13_DWON_221232-2608221232-dsw--0-ia5 22-Aug-2026 12:32:14 3170
ber01-VHDL13_DWON_221346-2608221346-dsw--0-ia5 22-Aug-2026 13:46:49 3170
ber01-VHDL13_DWON_221425-2608221425-dsw--0-ia5 22-Aug-2026 14:25:19 3170
ber01-VHDL13_DWON_221653-2608221653-dsw--0-ia5 22-Aug-2026 16:53:24 3068
ber01-VHDL13_DWON_221935-2608221935-dsw--0-ia5 22-Aug-2026 19:35:43 3068
ber01-VHDL13_DWON_222031-2608222031-dsw--0-ia5 22-Aug-2026 20:31:49 3063
ber01-VHDL13_DWON_230129-2608230129-dsw--0-ia5 23-Aug-2026 01:29:28 2977
ber01-VHDL13_DWON_230215-2608230215-dsw--0-ia5 23-Aug-2026 02:15:54 2967
ber01-VHDL13_DWON_230329-2608230329-dsw--0-ia5 23-Aug-2026 03:29:33 2983
ber01-VHDL13_DWON_230513-2608230513-dsw--0-ia5 23-Aug-2026 05:13:54 3068
ber01-VHDL13_DWON_230914-2608230914-dsw--0-ia5 23-Aug-2026 09:14:48 3022
ber01-VHDL13_DWON_231245-2608231245-dsw--0-ia5 23-Aug-2026 12:46:08 2789
ber01-VHDL13_DWON_231805-2608231805-dsw--0-ia5 23-Aug-2026 18:05:40 2687
ber01-VHDL13_DWON_240107-2608240107-dsw--0-ia5 24-Aug-2026 01:07:38 2881
ber01-VHDL13_DWON_240245-2608240245-dsw--0-ia5 24-Aug-2026 02:45:36 2866
ber01-VHDL13_DWON_240530-2608240530-dsw--0-ia5 24-Aug-2026 05:30:15 2866
ber01-VHDL13_DWON_240634-2608240634-dsw--0-ia5 24-Aug-2026 06:34:55 3098
ber01-VHDL13_DWPG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 2189
ber01-VHDL13_DWPG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2595
ber01-VHDL13_DWPH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 3196
ber01-VHDL13_DWPH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 2885
ber01-VHDL13_DWSG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:10 2551
ber01-VHDL13_DWSG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 3169
ber01-VHDL17_DWOG_221200-2608221200-dsw--0-ia5 22-Aug-2026 10:47:13 2915
ber01-VHDL17_DWOG_231200-2608231200-dsw--0-ia5 23-Aug-2026 11:43:09 2501
swis2-VHDL20_DWEG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1083
swis2-VHDL20_DWEG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 911
swis2-VHDL20_DWEG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 877
swis2-VHDL20_DWEG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1000
swis2-VHDL20_DWEG_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:13 1600
swis2-VHDL20_DWEG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1117
swis2-VHDL20_DWEG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1115
swis2-VHDL20_DWEG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1458
swis2-VHDL20_DWEH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1182
swis2-VHDL20_DWEH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 924
swis2-VHDL20_DWEH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 891
swis2-VHDL20_DWEH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1107
swis2-VHDL20_DWEH_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:13 1617
swis2-VHDL20_DWEH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1122
swis2-VHDL20_DWEH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1120
swis2-VHDL20_DWEH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1457
swis2-VHDL20_DWEI_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1286
swis2-VHDL20_DWEI_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:18 1171
swis2-VHDL20_DWEI_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:01:14 1078
swis2-VHDL20_DWEI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1362
swis2-VHDL20_DWEI_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:13 1844
swis2-VHDL20_DWEI_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1357
swis2-VHDL20_DWEI_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:01:23 1355
swis2-VHDL20_DWEI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1699
swis2-VHDL20_DWHG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:45:18 1226
swis2-VHDL20_DWHG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:46:07 1013
swis2-VHDL20_DWHG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 1013
swis2-VHDL20_DWHG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:46:52 1163
swis2-VHDL20_DWHG_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:45:07 1027
swis2-VHDL20_DWHG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:45:24 898
swis2-VHDL20_DWHG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:19 895
swis2-VHDL20_DWHG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:45:30 1034
swis2-VHDL20_DWHH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:45:18 1329
swis2-VHDL20_DWHH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:46:07 1258
swis2-VHDL20_DWHH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 1261
swis2-VHDL20_DWHH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:46:52 1411
swis2-VHDL20_DWHH_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:45:07 1003
swis2-VHDL20_DWHH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:45:24 900
swis2-VHDL20_DWHH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:19 900
swis2-VHDL20_DWHH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:45:30 958
swis2-VHDL20_DWLG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 984
swis2-VHDL20_DWLG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 853
swis2-VHDL20_DWLG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 766
swis2-VHDL20_DWLG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 876
swis2-VHDL20_DWLG_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:31:11 900
swis2-VHDL20_DWLG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 749
swis2-VHDL20_DWLG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 744
swis2-VHDL20_DWLG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 915
swis2-VHDL20_DWLH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 929
swis2-VHDL20_DWLH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 834
swis2-VHDL20_DWLH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 772
swis2-VHDL20_DWLH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 882
swis2-VHDL20_DWLH_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:31:11 903
swis2-VHDL20_DWLH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 756
swis2-VHDL20_DWLH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 751
swis2-VHDL20_DWLH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1037
swis2-VHDL20_DWLI_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 950
swis2-VHDL20_DWLI_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 894
swis2-VHDL20_DWLI_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 768
swis2-VHDL20_DWLI_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 860
swis2-VHDL20_DWLI_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:31:11 902
swis2-VHDL20_DWLI_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 751
swis2-VHDL20_DWLI_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 814
swis2-VHDL20_DWLI_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1242
swis2-VHDL20_DWMO_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1194
swis2-VHDL20_DWMO_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 949
swis2-VHDL20_DWMO_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:03 984
swis2-VHDL20_DWMO_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1191
swis2-VHDL20_DWMO_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:13 1100
swis2-VHDL20_DWMO_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1445
swis2-VHDL20_DWMO_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:05 1345
swis2-VHDL20_DWMO_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1424
swis2-VHDL20_DWMP_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1242
swis2-VHDL20_DWMP_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 997
swis2-VHDL20_DWMP_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:03 1127
swis2-VHDL20_DWMP_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:12 1236
swis2-VHDL20_DWMP_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:13 1279
swis2-VHDL20_DWMP_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:10 1328
swis2-VHDL20_DWMP_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:05 1227
swis2-VHDL20_DWMP_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:18 1520
swis2-VHDL20_DWPG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 965
swis2-VHDL20_DWPG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 865
swis2-VHDL20_DWPG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 833
swis2-VHDL20_DWPG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 924
swis2-VHDL20_DWPG_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:31:11 876
swis2-VHDL20_DWPG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 792
swis2-VHDL20_DWPG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 878
swis2-VHDL20_DWPG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1000
swis2-VHDL20_DWPH_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:31:32 1676
swis2-VHDL20_DWPH_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:25 1469
swis2-VHDL20_DWPH_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:14 1455
swis2-VHDL20_DWPH_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:26 1547
swis2-VHDL20_DWPH_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:31:11 1246
swis2-VHDL20_DWPH_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:27 881
swis2-VHDL20_DWPH_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:13 897
swis2-VHDL20_DWPH_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:23 1025
swis2-VHDL20_DWSG_221800-2608221800-dsw--0-ia5 22-Aug-2026 18:30:07 1135
swis2-VHDL20_DWSG_230200-2608230200-dsw--0-ia5 23-Aug-2026 02:30:09 976
swis2-VHDL20_DWSG_230400-2608230400-dsw--0-ia5 23-Aug-2026 05:00:18 996
swis2-VHDL20_DWSG_230800-2608230800-dsw--0-ia5 23-Aug-2026 08:30:10 1256
swis2-VHDL20_DWSG_231800-2608231800-dsw--0-ia5 23-Aug-2026 18:30:11 1392
swis2-VHDL20_DWSG_240200-2608240200-dsw--0-ia5 24-Aug-2026 02:30:16 1351
swis2-VHDL20_DWSG_240400-2608240400-dsw--0-ia5 24-Aug-2026 05:00:23 1210
swis2-VHDL20_DWSG_240800-2608240800-dsw--0-ia5 24-Aug-2026 08:30:19 1403
wst04-VHDL20_DWEG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 244240
wst04-VHDL20_DWEG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 243110
wst04-VHDL20_DWEG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 242980
wst04-VHDL20_DWEG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:12 243972
wst04-VHDL20_DWEG_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:28 245524
wst04-VHDL20_DWEG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 244196
wst04-VHDL20_DWEG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:13 244402
wst04-VHDL20_DWEG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 245290
wst04-VHDL20_DWEH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 236854
wst04-VHDL20_DWEH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 236290
wst04-VHDL20_DWEH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 236080
wst04-VHDL20_DWEH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:12 237218
wst04-VHDL20_DWEH_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:28 242404
wst04-VHDL20_DWEH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 241352
wst04-VHDL20_DWEH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:13 241811
wst04-VHDL20_DWEH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 242732
wst04-VHDL20_DWEI_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 354576
wst04-VHDL20_DWEI_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 354504
wst04-VHDL20_DWEI_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 354513
wst04-VHDL20_DWEI_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 355642
wst04-VHDL20_DWEI_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:28 357099
wst04-VHDL20_DWEI_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 355645
wst04-VHDL20_DWEI_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 355778
wst04-VHDL20_DWEI_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 356819
wst04-VHDL20_DWHG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:45:33 344643
wst04-VHDL20_DWHG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:46:07 343672
wst04-VHDL20_DWHG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 343459
wst04-VHDL20_DWHG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:46:52 344888
wst04-VHDL20_DWHG_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:45:26 344143
wst04-VHDL20_DWHG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:45:24 343826
wst04-VHDL20_DWHG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 343816
wst04-VHDL20_DWHG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:45:30 345223
wst04-VHDL20_DWHH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:45:33 334485
wst04-VHDL20_DWHH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:46:07 334128
wst04-VHDL20_DWHH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 232090
wst04-VHDL20_DWHH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:46:52 334549
wst04-VHDL20_DWHH_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:45:26 338816
wst04-VHDL20_DWHH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:45:24 338709
wst04-VHDL20_DWHH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 232374
wst04-VHDL20_DWHH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:45:30 339431
wst04-VHDL20_DWLG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 337587
wst04-VHDL20_DWLG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 382162
wst04-VHDL20_DWLG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 336309
wst04-VHDL20_DWLG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 336365
wst04-VHDL20_DWLG_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:31:32 333570
wst04-VHDL20_DWLG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 333583
wst04-VHDL20_DWLG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 332857
wst04-VHDL20_DWLG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 333377
wst04-VHDL20_DWLH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 336921
wst04-VHDL20_DWLH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 380514
wst04-VHDL20_DWLH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 335183
wst04-VHDL20_DWLH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 335245
wst04-VHDL20_DWLH_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:31:32 337456
wst04-VHDL20_DWLH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 337454
wst04-VHDL20_DWLH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 336724
wst04-VHDL20_DWLH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 337561
wst04-VHDL20_DWLI_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 339289
wst04-VHDL20_DWLI_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 383934
wst04-VHDL20_DWLI_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:42 337851
wst04-VHDL20_DWLI_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:48 382915
wst04-VHDL20_DWLI_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:31:32 339130
wst04-VHDL20_DWLI_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 339169
wst04-VHDL20_DWLI_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:43 338623
wst04-VHDL20_DWLI_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 384114
wst04-VHDL20_DWMO_220800-2608220800-omedes--0.pdf 22-Aug-2026 11:10:49 455075
wst04-VHDL20_DWMO_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 346913
wst04-VHDL20_DWMO_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 453181
wst04-VHDL20_DWMO_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 453212
wst04-VHDL20_DWMO_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 453017
wst04-VHDL20_DWMO_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:13 353343
wst04-VHDL20_DWMO_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 462232
wst04-VHDL20_DWMO_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:13 461831
wst04-VHDL20_DWMO_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 460666
wst04-VHDL20_DWMP_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 456088
wst04-VHDL20_DWMP_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 560459
wst04-VHDL20_DWMP_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:18 560706
wst04-VHDL20_DWMP_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 455806
wst04-VHDL20_DWMP_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:28 461819
wst04-VHDL20_DWMP_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 571962
wst04-VHDL20_DWMP_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:19 571617
wst04-VHDL20_DWMP_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 461098
wst04-VHDL20_DWPG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 346271
wst04-VHDL20_DWPG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 242206
wst04-VHDL20_DWPG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:34 344919
wst04-VHDL20_DWPG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 389481
wst04-VHDL20_DWPG_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:31:32 340771
wst04-VHDL20_DWPG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 238744
wst04-VHDL20_DWPG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:33 340734
wst04-VHDL20_DWPG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 385341
wst04-VHDL20_DWPH_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:31:35 245633
wst04-VHDL20_DWPH_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:25 290149
wst04-VHDL20_DWPH_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:34 245378
wst04-VHDL20_DWPH_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:46 245491
wst04-VHDL20_DWPH_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:31:32 246635
wst04-VHDL20_DWPH_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:27 245488
wst04-VHDL20_DWPH_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:33 244796
wst04-VHDL20_DWPH_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:52 245265
wst04-VHDL20_DWSG_221800-2608221800-omedes--0.pdf 22-Aug-2026 18:30:26 353696
wst04-VHDL20_DWSG_230200-2608230200-omedes--0.pdf 23-Aug-2026 02:30:23 352737
wst04-VHDL20_DWSG_230400-2608230400-omedes--0.pdf 23-Aug-2026 05:00:14 352548
wst04-VHDL20_DWSG_230800-2608230800-omedes--0.pdf 23-Aug-2026 08:30:26 353155
wst04-VHDL20_DWSG_231800-2608231800-omedes--0.pdf 23-Aug-2026 18:30:13 351570
wst04-VHDL20_DWSG_240200-2608240200-omedes--0.pdf 24-Aug-2026 02:30:19 351469
wst04-VHDL20_DWSG_240400-2608240400-omedes--0.pdf 24-Aug-2026 05:00:15 351233
wst04-VHDL20_DWSG_240800-2608240800-omedes--0.pdf 24-Aug-2026 08:30:19 351470