Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Aug-2026 14:30:14 3857
FPDL13_DWMZ_050600 05-Aug-2026 14:00:30 9424
SXDL31_DWAV_040800 04-Aug-2026 08:14:04 9592
SXDL31_DWAV_041800 04-Aug-2026 16:15:49 7881
SXDL31_DWAV_050800 05-Aug-2026 07:28:34 9523
SXDL31_DWAV_051800 05-Aug-2026 17:00:09 10503
SXDL31_DWAV_LATEST 05-Aug-2026 17:00:09 10503
SXDL33_DWAV_040000 04-Aug-2026 10:18:04 14152
SXDL33_DWAV_050000 05-Aug-2026 09:49:20 5880
SXDL33_DWAV_LATEST 05-Aug-2026 09:49:20 5880
ber01-FWDL39_DWMS_041200-2608041200-dsw--0-ia5 04-Aug-2026 11:21:17 1368
ber01-FWDL39_DWMS_051200-2608051200-dsw--0-ia5 05-Aug-2026 11:21:01 1264
ber01-VHDL13_DWEG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:12 3172
ber01-VHDL13_DWEG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:28:17 2999
ber01-VHDL13_DWEH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:16 3227
ber01-VHDL13_DWEH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:28:17 2800
ber01-VHDL13_DWEI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:22 2919
ber01-VHDL13_DWEI_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:28:17 2541
ber01-VHDL13_DWHG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3584
ber01-VHDL13_DWHG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:13 3659
ber01-VHDL13_DWHH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 4020
ber01-VHDL13_DWHH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:13 3671
ber01-VHDL13_DWLG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3103
ber01-VHDL13_DWLG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3108
ber01-VHDL13_DWLG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:47 2994
ber01-VHDL13_DWLH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3132
ber01-VHDL13_DWLH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3058
ber01-VHDL13_DWLH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:37 2973
ber01-VHDL13_DWLI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3091
ber01-VHDL13_DWLI_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 2715
ber01-VHDL13_DWLI_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:57 2580
ber01-VHDL13_DWMO_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3447
ber01-VHDL13_DWMO_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3123
ber01-VHDL13_DWMP_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3768
ber01-VHDL13_DWMP_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3577
ber01-VHDL13_DWOG_040300-2608040300-dsw--0-ia5 04-Aug-2026 03:00:06 3644
ber01-VHDL13_DWOG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3675
ber01-VHDL13_DWOG_041700-2608041700-dsw--0-ia5 04-Aug-2026 18:00:01 5156
ber01-VHDL13_DWOG_041700_COR-2608041700-dsw--0-ia5 04-Aug-2026 17:23:57 5160
ber01-VHDL13_DWOG_050300-2608050300-dsw--0-ia5 05-Aug-2026 03:00:08 4197
ber01-VHDL13_DWOG_050300_COR-2608050300-dsw--0-ia5 05-Aug-2026 03:40:18 4467
ber01-VHDL13_DWOG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 4618
ber01-VHDL13_DWOG_051700-2608051700-dsw--0-ia5 05-Aug-2026 18:00:03 4302
ber01-VHDL13_DWON_040012-2608040012-dsw--0-ia5 04-Aug-2026 00:12:07 3157
ber01-VHDL13_DWON_040252-2608040252-dsw--0-ia5 04-Aug-2026 02:52:31 3157
ber01-VHDL13_DWON_040529-2608040529-dsw--0-ia5 04-Aug-2026 05:29:36 3473
ber01-VHDL13_DWON_040629-2608040629-dsw--0-ia5 04-Aug-2026 06:29:27 3490
ber01-VHDL13_DWON_040722-2608040722-dsw--0-ia5 04-Aug-2026 07:22:06 3490
ber01-VHDL13_DWON_041520-2608041520-dsw--0-ia5 04-Aug-2026 15:20:41 3648
ber01-VHDL13_DWON_041723-2608041723-dsw--0-ia5 04-Aug-2026 17:23:31 4010
ber01-VHDL13_DWON_050124-2608050124-dsw--0-ia5 05-Aug-2026 01:24:51 3282
ber01-VHDL13_DWON_050249-2608050249-dsw--0-ia5 05-Aug-2026 02:49:36 3414
ber01-VHDL13_DWON_050339-2608050339-dsw--0-ia5 05-Aug-2026 03:39:43 3414
ber01-VHDL13_DWON_050529-2608050529-dsw--0-ia5 05-Aug-2026 05:29:57 4076
ber01-VHDL13_DWON_050607-2608050607-dsw--0-ia5 05-Aug-2026 06:07:32 4242
ber01-VHDL13_DWON_050736-2608050736-dsw--0-ia5 05-Aug-2026 07:36:33 4385
ber01-VHDL13_DWON_051456-2608051456-dsw--0-ia5 05-Aug-2026 14:56:45 4242
ber01-VHDL13_DWON_051733-2608051733-dsw--0-ia5 05-Aug-2026 17:33:34 3344
ber01-VHDL13_DWON_052224-2608052224-dsw--0-ia5 05-Aug-2026 22:24:31 2973
ber01-VHDL13_DWPG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3252
ber01-VHDL13_DWPG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3120
ber01-VHDL13_DWPG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:07 3206
ber01-VHDL13_DWPH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3272
ber01-VHDL13_DWPH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 3846
ber01-VHDL13_DWPH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:21 3696
ber01-VHDL13_DWSG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3496
ber01-VHDL13_DWSG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 2915
ber01-VHDL17_DWOG_041200-2608041200-dsw--0-ia5 04-Aug-2026 10:49:42 3444
ber01-VHDL17_DWOG_051200-2608051200-dsw--0-ia5 05-Aug-2026 10:47:32 1806
swis2-VHDL20_DWEG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1550
swis2-VHDL20_DWEG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1641
swis2-VHDL20_DWEG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1695
swis2-VHDL20_DWEG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2140
swis2-VHDL20_DWEG_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:07 1393
swis2-VHDL20_DWEG_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:55:26 1412
swis2-VHDL20_DWEG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1524
swis2-VHDL20_DWEG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1040
swis2-VHDL20_DWEH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1542
swis2-VHDL20_DWEH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1650
swis2-VHDL20_DWEH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1842
swis2-VHDL20_DWEH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2172
swis2-VHDL20_DWEH_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:07 1417
swis2-VHDL20_DWEH_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:55:26 1437
swis2-VHDL20_DWEH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1540
swis2-VHDL20_DWEH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1258
swis2-VHDL20_DWEI_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1459
swis2-VHDL20_DWEI_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1402
swis2-VHDL20_DWEI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1525
swis2-VHDL20_DWEI_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2084
swis2-VHDL20_DWEI_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:07 1415
swis2-VHDL20_DWEI_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:55:26 1195
swis2-VHDL20_DWEI_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1283
swis2-VHDL20_DWEI_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1060
swis2-VHDL20_DWHG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:45:23 2297
swis2-VHDL20_DWHG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:23 2141
swis2-VHDL20_DWHG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:45:19 2105
swis2-VHDL20_DWHG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:45:06 2190
swis2-VHDL20_DWHG_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:45:06 2111
swis2-VHDL20_DWHG_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:16 2030
swis2-VHDL20_DWHG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:45:03 1987
swis2-VHDL20_DWHG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:45:01 1585
swis2-VHDL20_DWHH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:45:23 2204
swis2-VHDL20_DWHH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:23 2204
swis2-VHDL20_DWHH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:45:19 2318
swis2-VHDL20_DWHH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:45:07 2238
swis2-VHDL20_DWHH_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:45:06 2111
swis2-VHDL20_DWHH_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:16 2035
swis2-VHDL20_DWHH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:45:03 2026
swis2-VHDL20_DWHH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:45:01 1584
swis2-VHDL20_DWLG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1227
swis2-VHDL20_DWLG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1410
swis2-VHDL20_DWLG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1506
swis2-VHDL20_DWLG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1442
swis2-VHDL20_DWLG_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:33 1103
swis2-VHDL20_DWLG_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:12 1180
swis2-VHDL20_DWLG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:28 1625
swis2-VHDL20_DWLG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:37 1611
swis2-VHDL20_DWLG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1343
swis2-VHDL20_DWLH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1238
swis2-VHDL20_DWLH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1401
swis2-VHDL20_DWLH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1570
swis2-VHDL20_DWLH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1373
swis2-VHDL20_DWLH_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:33 1211
swis2-VHDL20_DWLH_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:12 1191
swis2-VHDL20_DWLH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:28 1631
swis2-VHDL20_DWLH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:27 1543
swis2-VHDL20_DWLH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1176
swis2-VHDL20_DWLI_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1227
swis2-VHDL20_DWLI_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:13 1396
swis2-VHDL20_DWLI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1567
swis2-VHDL20_DWLI_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1353
swis2-VHDL20_DWLI_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:33 1206
swis2-VHDL20_DWLI_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:12 1166
swis2-VHDL20_DWLI_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:28 1300
swis2-VHDL20_DWLI_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:57 1312
swis2-VHDL20_DWLI_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 995
swis2-VHDL20_DWMO_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:12 1673
swis2-VHDL20_DWMO_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:01 1685
swis2-VHDL20_DWMO_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 2029
swis2-VHDL20_DWMO_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1624
swis2-VHDL20_DWMO_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:07 1336
swis2-VHDL20_DWMO_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:02 1360
swis2-VHDL20_DWMO_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1630
swis2-VHDL20_DWMO_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:09 1594
swis2-VHDL20_DWMP_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:12 1705
swis2-VHDL20_DWMP_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:01 1716
swis2-VHDL20_DWMP_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 2093
swis2-VHDL20_DWMP_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1899
swis2-VHDL20_DWMP_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:07 1692
swis2-VHDL20_DWMP_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:02 1715
swis2-VHDL20_DWMP_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1951
swis2-VHDL20_DWMP_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:09 1924
swis2-VHDL20_DWPG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1318
swis2-VHDL20_DWPG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1506
swis2-VHDL20_DWPG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1632
swis2-VHDL20_DWPG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1407
swis2-VHDL20_DWPG_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:33 1222
swis2-VHDL20_DWPG_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:12 1263
swis2-VHDL20_DWPG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:28 1650
swis2-VHDL20_DWPG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:01 1724
swis2-VHDL20_DWPG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1411
swis2-VHDL20_DWPH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1428
swis2-VHDL20_DWPH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1444
swis2-VHDL20_DWPH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1618
swis2-VHDL20_DWPH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1481
swis2-VHDL20_DWPH_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:33 1447
swis2-VHDL20_DWPH_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:12 1488
swis2-VHDL20_DWPH_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:28 1951
swis2-VHDL20_DWPH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:16 1796
swis2-VHDL20_DWPH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1642
swis2-VHDL20_DWSG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1503
swis2-VHDL20_DWSG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:21 1410
swis2-VHDL20_DWSG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1714
swis2-VHDL20_DWSG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1426
swis2-VHDL20_DWSG_050200-2608050200-dsw--0-ia5 05-Aug-2026 02:30:01 1365
swis2-VHDL20_DWSG_050400-2608050400-dsw--0-ia5 05-Aug-2026 05:00:16 1358
swis2-VHDL20_DWSG_050800-2608050800-dsw--0-ia5 05-Aug-2026 08:30:02 1411
swis2-VHDL20_DWSG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1335
wst04-VHDL20_DWEG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 242756
wst04-VHDL20_DWEG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 243167
wst04-VHDL20_DWEG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:14 243394
wst04-VHDL20_DWEG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 247698
wst04-VHDL20_DWEG_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:11 245168
wst04-VHDL20_DWEG_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:12 245066
wst04-VHDL20_DWEG_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:13 245841
wst04-VHDL20_DWEG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 239458
wst04-VHDL20_DWEH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 240487
wst04-VHDL20_DWEH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 240570
wst04-VHDL20_DWEH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:14 241424
wst04-VHDL20_DWEH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 240676
wst04-VHDL20_DWEH_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:11 238873
wst04-VHDL20_DWEH_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:12 239010
wst04-VHDL20_DWEH_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:13 239820
wst04-VHDL20_DWEH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:23 237871
wst04-VHDL20_DWEI_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 350734
wst04-VHDL20_DWEI_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:23 350408
wst04-VHDL20_DWEI_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:18 351207
wst04-VHDL20_DWEI_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 352318
wst04-VHDL20_DWEI_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 350157
wst04-VHDL20_DWEI_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:12 349415
wst04-VHDL20_DWEI_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:20 350352
wst04-VHDL20_DWEI_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 343600
wst04-VHDL20_DWHG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:45:22 353238
wst04-VHDL20_DWHG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 352784
wst04-VHDL20_DWHG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:45:19 353994
wst04-VHDL20_DWHG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:45:14 348453
wst04-VHDL20_DWHG_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:45:12 347331
wst04-VHDL20_DWHG_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:16 347050
wst04-VHDL20_DWHG_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:45:15 347783
wst04-VHDL20_DWHG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:45:12 342574
wst04-VHDL20_DWHH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:45:22 342228
wst04-VHDL20_DWHH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:23 235344
wst04-VHDL20_DWHH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:45:19 343118
wst04-VHDL20_DWHH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:45:14 342735
wst04-VHDL20_DWHH_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:45:12 342136
wst04-VHDL20_DWHH_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:16 234457
wst04-VHDL20_DWHH_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:45:15 341497
wst04-VHDL20_DWHH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:45:12 329731
wst04-VHDL20_DWLG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:32 341963
wst04-VHDL20_DWLG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:41 342126
wst04-VHDL20_DWLG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:47 342339
wst04-VHDL20_DWLG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 345752
wst04-VHDL20_DWLG_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 345331
wst04-VHDL20_DWLG_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:42 345415
wst04-VHDL20_DWLG_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:43 347697
wst04-VHDL20_DWLG_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:21 345616
wst04-VHDL20_DWLG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 343527
wst04-VHDL20_DWLH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 344347
wst04-VHDL20_DWLH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:47 344519
wst04-VHDL20_DWLH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:51 344806
wst04-VHDL20_DWLH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 344326
wst04-VHDL20_DWLH_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 343401
wst04-VHDL20_DWLH_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:42 343440
wst04-VHDL20_DWLH_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:43 345747
wst04-VHDL20_DWLH_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:01 345003
wst04-VHDL20_DWLH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 344072
wst04-VHDL20_DWLI_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 344113
wst04-VHDL20_DWLI_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:41 344257
wst04-VHDL20_DWLI_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:47 389130
wst04-VHDL20_DWLI_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 341343
wst04-VHDL20_DWLI_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:33 340494
wst04-VHDL20_DWLI_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:42 340474
wst04-VHDL20_DWLI_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:46 385521
wst04-VHDL20_DWLI_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:47 383027
wst04-VHDL20_DWLI_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 336629
wst04-VHDL20_DWMO_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:12 472025
wst04-VHDL20_DWMO_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:11 472216
wst04-VHDL20_DWMO_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 472025
wst04-VHDL20_DWMO_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 363603
wst04-VHDL20_DWMO_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:11 476207
wst04-VHDL20_DWMO_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:18 476395
wst04-VHDL20_DWMO_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:20 476915
wst04-VHDL20_DWMO_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 364442
wst04-VHDL20_DWMP_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 601503
wst04-VHDL20_DWMP_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:27 601691
wst04-VHDL20_DWMP_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 487246
wst04-VHDL20_DWMP_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 496110
wst04-VHDL20_DWMP_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 608221
wst04-VHDL20_DWMP_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:18 608452
wst04-VHDL20_DWMP_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:20 495895
wst04-VHDL20_DWMP_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 501794
wst04-VHDL20_DWPG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 245464
wst04-VHDL20_DWPG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:31 351498
wst04-VHDL20_DWPG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:42 397037
wst04-VHDL20_DWPG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 345767
wst04-VHDL20_DWPG_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 242448
wst04-VHDL20_DWPG_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:32 344959
wst04-VHDL20_DWPG_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:43 391737
wst04-VHDL20_DWPG_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:21:27 385912
wst04-VHDL20_DWPG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 339944
wst04-VHDL20_DWPH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 246055
wst04-VHDL20_DWPH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:31 246158
wst04-VHDL20_DWPH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:42 246310
wst04-VHDL20_DWPH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 246422
wst04-VHDL20_DWPH_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:20 246319
wst04-VHDL20_DWPH_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:32 246408
wst04-VHDL20_DWPH_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:43 247265
wst04-VHDL20_DWPH_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:21:45 242230
wst04-VHDL20_DWPH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 242271
wst04-VHDL20_DWSG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:12 365748
wst04-VHDL20_DWSG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:13 365897
wst04-VHDL20_DWSG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 367889
wst04-VHDL20_DWSG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 361535
wst04-VHDL20_DWSG_050200-2608050200-omedes--0.pdf 05-Aug-2026 02:30:11 361188
wst04-VHDL20_DWSG_050400-2608050400-omedes--0.pdf 05-Aug-2026 05:00:12 360452
wst04-VHDL20_DWSG_050800-2608050800-omedes--0.pdf 05-Aug-2026 08:30:13 360864
wst04-VHDL20_DWSG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 353465