Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Apr-2026 12:32:14 3694
FPDL13_DWMZ_020600 02-Apr-2026 11:02:54 2468
SXDL31_DWAV_010800 01-Apr-2026 07:20:20 6839
SXDL31_DWAV_011800 01-Apr-2026 16:35:16 6418
SXDL31_DWAV_020800 02-Apr-2026 07:26:15 6567
SXDL31_DWAV_021800 02-Apr-2026 16:34:00 6157
SXDL31_DWAV_LATEST 02-Apr-2026 16:34:00 6157
SXDL33_DWAV_010000 01-Apr-2026 09:46:49 8420
SXDL33_DWAV_020000 02-Apr-2026 09:51:02 9767
SXDL33_DWAV_LATEST 02-Apr-2026 09:51:02 9767
ber01-FWDL39_DWMS_011230-2604011230-dsw--0-ia5 01-Apr-2026 12:06:16 1636
ber01-FWDL39_DWMS_021230-2604021230-dsw--0-ia5 02-Apr-2026 11:03:27 1122
ber01-VHDL13_DWEH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3181
ber01-VHDL13_DWEH_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:17 2976
ber01-VHDL13_DWEH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:17 2710
ber01-VHDL13_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2644
ber01-VHDL13_DWEH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:11 2977
ber01-VHDL13_DWEH_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:12 3001
ber01-VHDL13_DWEH_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:44:57 2806
ber01-VHDL13_DWEH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:17 2745
ber01-VHDL13_DWHG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 2670
ber01-VHDL13_DWHG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2662
ber01-VHDL13_DWHG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2664
ber01-VHDL13_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 3001
ber01-VHDL13_DWHG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:06 3315
ber01-VHDL13_DWHG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3131
ber01-VHDL13_DWHG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 3185
ber01-VHDL13_DWHG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2792
ber01-VHDL13_DWHH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 2315
ber01-VHDL13_DWHH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2318
ber01-VHDL13_DWHH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2815
ber01-VHDL13_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 2997
ber01-VHDL13_DWHH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:06 3201
ber01-VHDL13_DWHH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3210
ber01-VHDL13_DWHH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 3348
ber01-VHDL13_DWHH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2779
ber01-VHDL13_DWLG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2574
ber01-VHDL13_DWLG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2699
ber01-VHDL13_DWLG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2649
ber01-VHDL13_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2403
ber01-VHDL13_DWLG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2688
ber01-VHDL13_DWLG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2807
ber01-VHDL13_DWLG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2954
ber01-VHDL13_DWLG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 3306
ber01-VHDL13_DWLH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2366
ber01-VHDL13_DWLH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2401
ber01-VHDL13_DWLH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2660
ber01-VHDL13_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2332
ber01-VHDL13_DWLH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2452
ber01-VHDL13_DWLH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2502
ber01-VHDL13_DWLH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2807
ber01-VHDL13_DWLH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 3474
ber01-VHDL13_DWLI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2503
ber01-VHDL13_DWLI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2537
ber01-VHDL13_DWLI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2496
ber01-VHDL13_DWLI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2264
ber01-VHDL13_DWLI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2509
ber01-VHDL13_DWLI_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2560
ber01-VHDL13_DWLI_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2580
ber01-VHDL13_DWLI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2905
ber01-VHDL13_DWMG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 3361
ber01-VHDL13_DWMG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 3201
ber01-VHDL13_DWMG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2821
ber01-VHDL13_DWMG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWMG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2833
ber01-VHDL13_DWMG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2905
ber01-VHDL13_DWMG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2671
ber01-VHDL13_DWMG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2559
ber01-VHDL13_DWMO_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2843
ber01-VHDL13_DWMO_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 2773
ber01-VHDL13_DWMO_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2332
ber01-VHDL13_DWMO_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2143
ber01-VHDL13_DWMO_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2553
ber01-VHDL13_DWMO_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2665
ber01-VHDL13_DWMO_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2424
ber01-VHDL13_DWMO_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2334
ber01-VHDL13_DWMP_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 3266
ber01-VHDL13_DWMP_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 3251
ber01-VHDL13_DWMP_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2998
ber01-VHDL13_DWMP_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2615
ber01-VHDL13_DWMP_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2795
ber01-VHDL13_DWMP_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2806
ber01-VHDL13_DWMP_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2633
ber01-VHDL13_DWMP_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2478
ber01-VHDL13_DWOG_010300-2604010300-dsw--0-ia5 01-Apr-2026 03:00:15 3398
ber01-VHDL13_DWOG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 3994
ber01-VHDL13_DWOG_011700-2604011700-dsw--0-ia5 01-Apr-2026 18:00:01 3033
ber01-VHDL13_DWOG_020300-2604020300-dsw--0-ia5 02-Apr-2026 03:00:08 4040
ber01-VHDL13_DWOG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:01 4052
ber01-VHDL13_DWOG_021700-2604021700-dsw--0-ia5 02-Apr-2026 18:00:01 3575
ber01-VHDL13_DWOH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3036
ber01-VHDL13_DWOH_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:11 2824
ber01-VHDL13_DWOH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:17 2716
ber01-VHDL13_DWOH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2529
ber01-VHDL13_DWOH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:11 2915
ber01-VHDL13_DWOH_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:16 2762
ber01-VHDL13_DWOH_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:45:22 2591
ber01-VHDL13_DWOH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:11 2476
ber01-VHDL13_DWOI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3081
ber01-VHDL13_DWOI_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:17 2697
ber01-VHDL13_DWOI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:11 2702
ber01-VHDL13_DWOI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:12 2578
ber01-VHDL13_DWOI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:17 2758
ber01-VHDL13_DWOI_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:16 2613
ber01-VHDL13_DWOI_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:45:42 2390
ber01-VHDL13_DWOI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:11 2329
ber01-VHDL13_DWON_010143-2604010143-dsw--0-ia5 01-Apr-2026 01:43:51 3368
ber01-VHDL13_DWON_010530-2604010530-dsw--0-ia5 01-Apr-2026 05:30:27 3613
ber01-VHDL13_DWON_010606-2604010606-dsw--0-ia5 01-Apr-2026 06:06:21 3714
ber01-VHDL13_DWON_010704-2604010704-dsw--0-ia5 01-Apr-2026 07:04:33 4163
ber01-VHDL13_DWON_010931-2604010931-dsw--0-ia5 01-Apr-2026 09:31:31 3920
ber01-VHDL13_DWON_011455-2604011455-dsw--0-ia5 01-Apr-2026 14:55:07 3631
ber01-VHDL13_DWON_011727-2604011727-dsw--0-ia5 01-Apr-2026 17:28:01 3214
ber01-VHDL13_DWON_012126-2604012126-dsw--0-ia5 01-Apr-2026 21:26:51 3172
ber01-VHDL13_DWON_020154-2604020154-dsw--0-ia5 02-Apr-2026 01:54:27 3491
ber01-VHDL13_DWON_020246-2604020246-dsw--0-ia5 02-Apr-2026 02:46:46 3627
ber01-VHDL13_DWON_020248-2604020248-dsw--0-ia5 02-Apr-2026 02:48:11 3627
ber01-VHDL13_DWON_020513-2604020513-dsw--0-ia5 02-Apr-2026 05:13:57 4064
ber01-VHDL13_DWON_020631-2604020631-dsw--0-ia5 02-Apr-2026 06:31:31 4064
ber01-VHDL13_DWON_020823-2604020823-dsw--0-ia5 02-Apr-2026 08:23:26 4062
ber01-VHDL13_DWON_020921-2604020921-dsw--0-ia5 02-Apr-2026 09:21:42 4115
ber01-VHDL13_DWON_021433-2604021433-dsw--0-ia5 02-Apr-2026 14:33:52 4025
ber01-VHDL13_DWON_021712-2604021712-dsw--0-ia5 02-Apr-2026 17:12:42 3527
ber01-VHDL13_DWON_022041-2604022041-dsw--0-ia5 02-Apr-2026 20:41:31 3523
ber01-VHDL13_DWPG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2252
ber01-VHDL13_DWPG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2714
ber01-VHDL13_DWPG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2743
ber01-VHDL13_DWPG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2475
ber01-VHDL13_DWPG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2588
ber01-VHDL13_DWPG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2549
ber01-VHDL13_DWPG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2607
ber01-VHDL13_DWPG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2294
ber01-VHDL13_DWPH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2483
ber01-VHDL13_DWPH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2801
ber01-VHDL13_DWPH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2685
ber01-VHDL13_DWPH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWPH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2477
ber01-VHDL13_DWPH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2486
ber01-VHDL13_DWPH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2639
ber01-VHDL13_DWPH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2267
ber01-VHDL13_DWSG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 3121
ber01-VHDL13_DWSG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 3225
ber01-VHDL13_DWSG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2890
ber01-VHDL13_DWSG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2396
ber01-VHDL13_DWSG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2829
ber01-VHDL13_DWSG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:17 2630
ber01-VHDL13_DWSG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:01 2612
ber01-VHDL13_DWSG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:02 2518
ber01-VHDL17_DWOG_011200-2604011200-dsw--0-ia5 01-Apr-2026 11:03:56 3234
ber01-VHDL17_DWOG_021200-2604021200-dsw--0-ia5 02-Apr-2026 11:45:32 3094
swis2-VHDL20_DWEG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3516
swis2-VHDL20_DWEG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3284
swis2-VHDL20_DWEG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3331
swis2-VHDL20_DWEG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2995
swis2-VHDL20_DWEG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3334
swis2-VHDL20_DWEG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:01 3080
swis2-VHDL20_DWEG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3067
swis2-VHDL20_DWEG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2800
swis2-VHDL20_DWEH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3704
swis2-VHDL20_DWEH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3448
swis2-VHDL20_DWEH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3350
swis2-VHDL20_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3141
swis2-VHDL20_DWEH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3441
swis2-VHDL20_DWEH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:07 3489
swis2-VHDL20_DWEH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3465
swis2-VHDL20_DWEH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 3255
swis2-VHDL20_DWEI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3573
swis2-VHDL20_DWEI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3188
swis2-VHDL20_DWEI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3364
swis2-VHDL20_DWEI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3069
swis2-VHDL20_DWEI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3190
swis2-VHDL20_DWEI_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:07 2962
swis2-VHDL20_DWEI_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 2913
swis2-VHDL20_DWEI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2678
swis2-VHDL20_DWHG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2856
swis2-VHDL20_DWHG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 2845
swis2-VHDL20_DWHG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3282
swis2-VHDL20_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3184
swis2-VHDL20_DWHG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3501
swis2-VHDL20_DWHG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3314
swis2-VHDL20_DWHG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3779
swis2-VHDL20_DWHG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2975
swis2-VHDL20_DWHH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2501
swis2-VHDL20_DWHH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 2504
swis2-VHDL20_DWHH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3431
swis2-VHDL20_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3183
swis2-VHDL20_DWHH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3387
swis2-VHDL20_DWHH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3396
swis2-VHDL20_DWHH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:06 3888
swis2-VHDL20_DWHH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2965
swis2-VHDL20_DWLG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2997
swis2-VHDL20_DWLG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3069
swis2-VHDL20_DWLG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3249
swis2-VHDL20_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2773
swis2-VHDL20_DWLG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3058
swis2-VHDL20_DWLG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3232
swis2-VHDL20_DWLG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3524
swis2-VHDL20_DWLG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 3731
swis2-VHDL20_DWLH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2789
swis2-VHDL20_DWLH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2779
swis2-VHDL20_DWLH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3263
swis2-VHDL20_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2710
swis2-VHDL20_DWLH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2830
swis2-VHDL20_DWLH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 2923
swis2-VHDL20_DWLH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3377
swis2-VHDL20_DWLH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 3895
swis2-VHDL20_DWLI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2938
swis2-VHDL20_DWLI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2910
swis2-VHDL20_DWLI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3100
swis2-VHDL20_DWLI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2637
swis2-VHDL20_DWLI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2882
swis2-VHDL20_DWLI_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 2995
swis2-VHDL20_DWLI_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3165
swis2-VHDL20_DWLI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 3340
swis2-VHDL20_DWMG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3875
swis2-VHDL20_DWMG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3637
swis2-VHDL20_DWMG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3488
swis2-VHDL20_DWMG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2818
swis2-VHDL20_DWMG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3273
swis2-VHDL20_DWMG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:01 3409
swis2-VHDL20_DWMG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3333
swis2-VHDL20_DWMG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 3062
swis2-VHDL20_DWMO_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3329
swis2-VHDL20_DWMO_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3209
swis2-VHDL20_DWMO_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 2930
swis2-VHDL20_DWMO_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2579
swis2-VHDL20_DWMO_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2988
swis2-VHDL20_DWMO_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:01 3039
swis2-VHDL20_DWMO_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:06 2960
swis2-VHDL20_DWMO_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2707
swis2-VHDL20_DWMP_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3781
swis2-VHDL20_DWMP_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3692
swis2-VHDL20_DWMP_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3676
swis2-VHDL20_DWMP_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3032
swis2-VHDL20_DWMP_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3238
swis2-VHDL20_DWMP_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:01 3312
swis2-VHDL20_DWMP_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3303
swis2-VHDL20_DWMP_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 3007
swis2-VHDL20_DWPG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2637
swis2-VHDL20_DWPG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3060
swis2-VHDL20_DWPG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3222
swis2-VHDL20_DWPG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2970
swis2-VHDL20_DWPG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2953
swis2-VHDL20_DWPG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 2875
swis2-VHDL20_DWPG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3067
swis2-VHDL20_DWPG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 2754
swis2-VHDL20_DWPH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2867
swis2-VHDL20_DWPH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3149
swis2-VHDL20_DWPH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3164
swis2-VHDL20_DWPH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2879
swis2-VHDL20_DWPH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2841
swis2-VHDL20_DWPH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 2814
swis2-VHDL20_DWPH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3099
swis2-VHDL20_DWPH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 2727
swis2-VHDL20_DWSG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3661
swis2-VHDL20_DWSG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3659
swis2-VHDL20_DWSG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3469
swis2-VHDL20_DWSG_011300-2604011300-dsw--0-ia5 01-Apr-2026 13:45:02 3096
swis2-VHDL20_DWSG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:06 2828
swis2-VHDL20_DWSG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:06 3249
swis2-VHDL20_DWSG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:03 3064
swis2-VHDL20_DWSG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:06 3112
swis2-VHDL20_DWSG_021300-2604021300-dsw--0-ia5 02-Apr-2026 13:45:02 3111
swis2-VHDL20_DWSG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2873
wst04-VHDL20_DWEG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 243461
wst04-VHDL20_DWEG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 242617
wst04-VHDL20_DWEG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 243351
wst04-VHDL20_DWEG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 238984
wst04-VHDL20_DWEG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:13 240024
wst04-VHDL20_DWEG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:11 239644
wst04-VHDL20_DWEG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 240250
wst04-VHDL20_DWEG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:12 242444
wst04-VHDL20_DWEH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 240618
wst04-VHDL20_DWEH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 239965
wst04-VHDL20_DWEH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 239578
wst04-VHDL20_DWEH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 235894
wst04-VHDL20_DWEH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:13 237309
wst04-VHDL20_DWEH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:11 237251
wst04-VHDL20_DWEH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 236707
wst04-VHDL20_DWEH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:12 238195
wst04-VHDL20_DWEI_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 343856
wst04-VHDL20_DWEI_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 343369
wst04-VHDL20_DWEI_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:16 343411
wst04-VHDL20_DWEI_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 337285
wst04-VHDL20_DWEI_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 337701
wst04-VHDL20_DWEI_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 337444
wst04-VHDL20_DWEI_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 337455
wst04-VHDL20_DWEI_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:12 343326
wst04-VHDL20_DWHG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 339593
wst04-VHDL20_DWHG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:12 339567
wst04-VHDL20_DWHG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 340706
wst04-VHDL20_DWHG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 334524
wst04-VHDL20_DWHG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 335422
wst04-VHDL20_DWHG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:11 335284
wst04-VHDL20_DWHG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:16 336057
wst04-VHDL20_DWHG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 337903
wst04-VHDL20_DWHH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 322171
wst04-VHDL20_DWHH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:12 322294
wst04-VHDL20_DWHH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 323395
wst04-VHDL20_DWHH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 320385
wst04-VHDL20_DWHH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:13 321486
wst04-VHDL20_DWHH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:11 321472
wst04-VHDL20_DWHH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 321127
wst04-VHDL20_DWHH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 324622
wst04-VHDL20_DWLG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 325455
wst04-VHDL20_DWLG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 325522
wst04-VHDL20_DWLG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 326458
wst04-VHDL20_DWLG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 327924
wst04-VHDL20_DWLG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 327988
wst04-VHDL20_DWLG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 327958
wst04-VHDL20_DWLG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:30 328725
wst04-VHDL20_DWLG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:26 329139
wst04-VHDL20_DWLH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 337473
wst04-VHDL20_DWLH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 338292
wst04-VHDL20_DWLH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 339093
wst04-VHDL20_DWLH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 328382
wst04-VHDL20_DWLH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 328091
wst04-VHDL20_DWLH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 328280
wst04-VHDL20_DWLH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:30 328808
wst04-VHDL20_DWLH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 329303
wst04-VHDL20_DWLI_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 329820
wst04-VHDL20_DWLI_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 329855
wst04-VHDL20_DWLI_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 330118
wst04-VHDL20_DWLI_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:26 329236
wst04-VHDL20_DWLI_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 329782
wst04-VHDL20_DWLI_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 329338
wst04-VHDL20_DWLI_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 329529
wst04-VHDL20_DWLI_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:26 331323
wst04-VHDL20_DWMG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 536688
wst04-VHDL20_DWMG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 536521
wst04-VHDL20_DWMG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 536763
wst04-VHDL20_DWMG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 541181
wst04-VHDL20_DWMG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 541314
wst04-VHDL20_DWMG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 541311
wst04-VHDL20_DWMG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 541675
wst04-VHDL20_DWMG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 546455
wst04-VHDL20_DWMO_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 441033
wst04-VHDL20_DWMO_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 441319
wst04-VHDL20_DWMO_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 440737
wst04-VHDL20_DWMO_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 439947
wst04-VHDL20_DWMO_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 440966
wst04-VHDL20_DWMO_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 441853
wst04-VHDL20_DWMO_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 441736
wst04-VHDL20_DWMO_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 448753
wst04-VHDL20_DWMP_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 533174
wst04-VHDL20_DWMP_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:22 534294
wst04-VHDL20_DWMP_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 534220
wst04-VHDL20_DWMP_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 540426
wst04-VHDL20_DWMP_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 539981
wst04-VHDL20_DWMP_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:21 540991
wst04-VHDL20_DWMP_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 541423
wst04-VHDL20_DWMP_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 538034
wst04-VHDL20_DWPG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 348727
wst04-VHDL20_DWPG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:32 349082
wst04-VHDL20_DWPG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 394157
wst04-VHDL20_DWPG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:26 332658
wst04-VHDL20_DWPG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 331945
wst04-VHDL20_DWPG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:31 331629
wst04-VHDL20_DWPG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 376786
wst04-VHDL20_DWPG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 339368
wst04-VHDL20_DWPH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 241638
wst04-VHDL20_DWPH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:32 242601
wst04-VHDL20_DWPH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 287403
wst04-VHDL20_DWPH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 282558
wst04-VHDL20_DWPH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 237161
wst04-VHDL20_DWPH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:31 237059
wst04-VHDL20_DWPH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 282382
wst04-VHDL20_DWPH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 283126
wst04-VHDL20_DWSG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 343158
wst04-VHDL20_DWSG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 342839
wst04-VHDL20_DWSG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 342499
wst04-VHDL20_DWSG_011300-2604011300-omedes--0.pdf 01-Apr-2026 13:45:12 341028
wst04-VHDL20_DWSG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 341744
wst04-VHDL20_DWSG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 342439
wst04-VHDL20_DWSG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:11 342348
wst04-VHDL20_DWSG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 342277
wst04-VHDL20_DWSG_021300-2604021300-omedes--0.pdf 02-Apr-2026 13:45:12 348566
wst04-VHDL20_DWSG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:12 347807