Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Sep-2026 11:15:44 3796
SXDL31_DWAV_031800 03-Sep-2026 17:23:08 8006
SXDL31_DWAV_040800 04-Sep-2026 07:43:27 13426
SXDL31_DWAV_041800 04-Sep-2026 16:25:44 7487
SXDL31_DWAV_050800 05-Sep-2026 07:20:44 7213
SXDL31_DWAV_LATEST 05-Sep-2026 07:20:44 7213
SXDL33_DWAV_040000 04-Sep-2026 09:48:59 10162
SXDL33_DWAV_050000 05-Sep-2026 09:27:23 8257
SXDL33_DWAV_LATEST 05-Sep-2026 09:27:23 8257
ber01-FWDL39_DWMS_041200-2609041200-dsw--0-ia5 04-Sep-2026 10:05:24 1225
ber01-FWDL39_DWMS_051200-2609051200-dsw--0-ia5 05-Sep-2026 12:02:04 1317
ber01-VHDL13_DWEG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:28:19 3813
ber01-VHDL13_DWEG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3202
ber01-VHDL13_DWEH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:28:19 3616
ber01-VHDL13_DWEH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3141
ber01-VHDL13_DWEI_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:28:19 3322
ber01-VHDL13_DWEI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3008
ber01-VHDL13_DWHG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:17 4256
ber01-VHDL13_DWHG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 3532
ber01-VHDL13_DWHH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:17 4181
ber01-VHDL13_DWHH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 3607
ber01-VHDL13_DWLG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:07 3378
ber01-VHDL13_DWLG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2777
ber01-VHDL13_DWLH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:07 3486
ber01-VHDL13_DWLH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3258
ber01-VHDL13_DWLI_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:07 3025
ber01-VHDL13_DWLI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2539
ber01-VHDL13_DWMO_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 3609
ber01-VHDL13_DWMO_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2765
ber01-VHDL13_DWMP_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 3345
ber01-VHDL13_DWMP_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2969
ber01-VHDL13_DWOG_031700-2609031700-dsw--0-ia5 03-Sep-2026 18:00:05 4665
ber01-VHDL13_DWOG_040300-2609040300-dsw--0-ia5 04-Sep-2026 03:01:06 5151
ber01-VHDL13_DWOG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:17 5151
ber01-VHDL13_DWOG_041700-2609041700-dsw--0-ia5 04-Sep-2026 18:00:04 5510
ber01-VHDL13_DWOG_041700_COR-2609041700-dsw--0-ia5 04-Sep-2026 18:01:00 4587
ber01-VHDL13_DWOG_050300-2609050300-dsw--0-ia5 05-Sep-2026 03:01:13 4591
ber01-VHDL13_DWOG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 4230
ber01-VHDL13_DWON_031443-2609031443-dsw--0-ia5 03-Sep-2026 14:43:57 3858
ber01-VHDL13_DWON_031721-2609031721-dsw--0-ia5 03-Sep-2026 17:21:13 3712
ber01-VHDL13_DWON_032256-2609032256-dsw--0-ia5 03-Sep-2026 22:56:43 3640
ber01-VHDL13_DWON_032257-2609032257-dsw--0-ia5 03-Sep-2026 22:57:09 3640
ber01-VHDL13_DWON_032347-2609032347-dsw--0-ia5 03-Sep-2026 23:47:45 3640
ber01-VHDL13_DWON_040003-2609040003-dsw--0-ia5 04-Sep-2026 00:03:18 3741
ber01-VHDL13_DWON_040226-2609040226-dsw--0-ia5 04-Sep-2026 02:26:44 3741
ber01-VHDL13_DWON_040459-2609040459-dsw--0-ia5 04-Sep-2026 04:59:24 4379
ber01-VHDL13_DWON_040609-2609040609-dsw--0-ia5 04-Sep-2026 06:09:58 4379
ber01-VHDL13_DWON_041156-2609041156-dsw--0-ia5 04-Sep-2026 11:56:57 4379
ber01-VHDL13_DWON_041239-2609041239-dsw--0-ia5 04-Sep-2026 12:40:15 4038
ber01-VHDL13_DWON_041407-2609041407-dsw--0-ia5 04-Sep-2026 14:07:59 4038
ber01-VHDL13_DWON_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:00:38 4026
ber01-VHDL13_DWON_050116-2609050116-dsw--0-ia5 05-Sep-2026 01:16:37 4023
ber01-VHDL13_DWON_050244-2609050244-dsw--0-ia5 05-Sep-2026 02:46:58 4023
ber01-VHDL13_DWON_050529-2609050529-dsw--0-ia5 05-Sep-2026 05:29:23 4295
ber01-VHDL13_DWON_050552-2609050552-dsw--0-ia5 05-Sep-2026 05:52:33 4038
ber01-VHDL13_DWON_050807-2609050807-dsw--0-ia5 05-Sep-2026 08:07:33 4024
ber01-VHDL13_DWPG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:07 3090
ber01-VHDL13_DWPG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2971
ber01-VHDL13_DWPH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:07 3603
ber01-VHDL13_DWPH_040800_COR-2609040800-dsw--0-ia5 04-Sep-2026 12:04:03 4107
ber01-VHDL13_DWPH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3475
ber01-VHDL13_DWSG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 3453
ber01-VHDL13_DWSG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3147
ber01-VHDL17_DWOG_041200-2609041200-dsw--0-ia5 04-Sep-2026 11:52:50 3956
ber01-VHDL17_DWOG_051200-2609051200-dsw--0-ia5 05-Sep-2026 10:48:08 3038
swis2-VHDL20_DWEG_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1744
swis2-VHDL20_DWEG_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1473
swis2-VHDL20_DWEG_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:01:18 1573
swis2-VHDL20_DWEG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1833
swis2-VHDL20_DWEG_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1935
swis2-VHDL20_DWEG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 951
swis2-VHDL20_DWEG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 957
swis2-VHDL20_DWEG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1240
swis2-VHDL20_DWEH_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1816
swis2-VHDL20_DWEH_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1476
swis2-VHDL20_DWEH_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:01:18 1585
swis2-VHDL20_DWEH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1831
swis2-VHDL20_DWEH_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1682
swis2-VHDL20_DWEH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1019
swis2-VHDL20_DWEH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 1028
swis2-VHDL20_DWEH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1311
swis2-VHDL20_DWEI_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1472
swis2-VHDL20_DWEI_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1096
swis2-VHDL20_DWEI_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:01:18 1096
swis2-VHDL20_DWEI_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1687
swis2-VHDL20_DWEI_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1946
swis2-VHDL20_DWEI_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 965
swis2-VHDL20_DWEI_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 971
swis2-VHDL20_DWEI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1257
swis2-VHDL20_DWHG_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:45:05 2630
swis2-VHDL20_DWHG_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:45:26 2120
swis2-VHDL20_DWHG_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:18 2117
swis2-VHDL20_DWHG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:45:16 2290
swis2-VHDL20_DWHG_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:45:22 2800
swis2-VHDL20_DWHG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:46:58 1674
swis2-VHDL20_DWHG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1709
swis2-VHDL20_DWHG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:45:33 1846
swis2-VHDL20_DWHH_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:45:05 2141
swis2-VHDL20_DWHH_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:45:26 2258
swis2-VHDL20_DWHH_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:18 2258
swis2-VHDL20_DWHH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:45:16 2364
swis2-VHDL20_DWHH_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:45:22 2173
swis2-VHDL20_DWHH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:46:58 1690
swis2-VHDL20_DWHH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1711
swis2-VHDL20_DWHH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:45:33 1984
swis2-VHDL20_DWLG_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:31:04 1484
swis2-VHDL20_DWLG_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:33 1422
swis2-VHDL20_DWLG_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:14 1418
swis2-VHDL20_DWLG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:39 1593
swis2-VHDL20_DWLG_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:31:05 1110
swis2-VHDL20_DWLG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 892
swis2-VHDL20_DWLG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1096
swis2-VHDL20_DWLG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1329
swis2-VHDL20_DWLH_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:31:04 1591
swis2-VHDL20_DWLH_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:33 1531
swis2-VHDL20_DWLH_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:14 1621
swis2-VHDL20_DWLH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:39 1762
swis2-VHDL20_DWLH_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:31:05 1219
swis2-VHDL20_DWLH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1124
swis2-VHDL20_DWLH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1319
swis2-VHDL20_DWLH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1660
swis2-VHDL20_DWLI_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:31:04 1483
swis2-VHDL20_DWLI_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:33 1421
swis2-VHDL20_DWLI_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:14 1417
swis2-VHDL20_DWLI_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:39 1510
swis2-VHDL20_DWLI_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:31:05 1122
swis2-VHDL20_DWLI_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 911
swis2-VHDL20_DWLI_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 964
swis2-VHDL20_DWLI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1204
swis2-VHDL20_DWMO_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1760
swis2-VHDL20_DWMO_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1354
swis2-VHDL20_DWMO_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:08 1415
swis2-VHDL20_DWMO_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1858
swis2-VHDL20_DWMO_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1862
swis2-VHDL20_DWMO_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1356
swis2-VHDL20_DWMO_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:03 1204
swis2-VHDL20_DWMO_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1379
swis2-VHDL20_DWMP_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1593
swis2-VHDL20_DWMP_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1238
swis2-VHDL20_DWMP_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:08 1471
swis2-VHDL20_DWMP_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1631
swis2-VHDL20_DWMP_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1683
swis2-VHDL20_DWMP_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1453
swis2-VHDL20_DWMP_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:03 1401
swis2-VHDL20_DWMP_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1274
swis2-VHDL20_DWPG_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:31:04 1573
swis2-VHDL20_DWPG_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:33 1523
swis2-VHDL20_DWPG_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:14 1580
swis2-VHDL20_DWPG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:39 1749
swis2-VHDL20_DWPG_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:31:05 1608
swis2-VHDL20_DWPG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1180
swis2-VHDL20_DWPG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1294
swis2-VHDL20_DWPG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1591
swis2-VHDL20_DWPH_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:31:04 1474
swis2-VHDL20_DWPH_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:33 1439
swis2-VHDL20_DWPH_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:14 1449
swis2-VHDL20_DWPH_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:39 2000
swis2-VHDL20_DWPH_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:31:05 1821
swis2-VHDL20_DWPH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1531
swis2-VHDL20_DWPH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1681
swis2-VHDL20_DWPH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 2001
swis2-VHDL20_DWSG_031800-2609031800-dsw--0-ia5 03-Sep-2026 18:30:19 1569
swis2-VHDL20_DWSG_040200-2609040200-dsw--0-ia5 04-Sep-2026 02:30:04 1368
swis2-VHDL20_DWSG_040400-2609040400-dsw--0-ia5 04-Sep-2026 05:00:18 1602
swis2-VHDL20_DWSG_040800-2609040800-dsw--0-ia5 04-Sep-2026 08:30:05 1661
swis2-VHDL20_DWSG_041800-2609041800-dsw--0-ia5 04-Sep-2026 18:30:04 1665
swis2-VHDL20_DWSG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1156
swis2-VHDL20_DWSG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1129
swis2-VHDL20_DWSG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1376
wst04-VHDL20_DWEG_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:19 245919
wst04-VHDL20_DWEG_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:13 245021
wst04-VHDL20_DWEG_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:14 245095
wst04-VHDL20_DWEG_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 245817
wst04-VHDL20_DWEG_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 243510
wst04-VHDL20_DWEG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 241043
wst04-VHDL20_DWEG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 240599
wst04-VHDL20_DWEG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:14 241896
wst04-VHDL20_DWEH_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:19 243555
wst04-VHDL20_DWEH_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:13 243020
wst04-VHDL20_DWEH_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:14 243070
wst04-VHDL20_DWEH_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 243870
wst04-VHDL20_DWEH_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 244786
wst04-VHDL20_DWEH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 243178
wst04-VHDL20_DWEH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 242961
wst04-VHDL20_DWEH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:14 244295
wst04-VHDL20_DWEI_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:19 350824
wst04-VHDL20_DWEI_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:29 349866
wst04-VHDL20_DWEI_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:14 349846
wst04-VHDL20_DWEI_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 351760
wst04-VHDL20_DWEI_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 348625
wst04-VHDL20_DWEI_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 346146
wst04-VHDL20_DWEI_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 345627
wst04-VHDL20_DWEI_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 346412
wst04-VHDL20_DWHG_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:45:14 348859
wst04-VHDL20_DWHG_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:45:26 347558
wst04-VHDL20_DWHG_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:18 347580
wst04-VHDL20_DWHG_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:45:36 348558
wst04-VHDL20_DWHG_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:45:22 347223
wst04-VHDL20_DWHG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:46:58 345471
wst04-VHDL20_DWHG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 345263
wst04-VHDL20_DWHG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:45:33 346306
wst04-VHDL20_DWHH_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:45:14 340704
wst04-VHDL20_DWHH_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:45:26 340081
wst04-VHDL20_DWHH_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:18 235530
wst04-VHDL20_DWHH_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:45:36 340073
wst04-VHDL20_DWHH_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:45:22 340904
wst04-VHDL20_DWHH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:46:58 339358
wst04-VHDL20_DWHH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 232468
wst04-VHDL20_DWHH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:45:33 339565
wst04-VHDL20_DWLG_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:31:26 338530
wst04-VHDL20_DWLG_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:33 338274
wst04-VHDL20_DWLG_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:42 338566
wst04-VHDL20_DWLG_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:52 339101
wst04-VHDL20_DWLG_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:31:50 339195
wst04-VHDL20_DWLG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 338812
wst04-VHDL20_DWLG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 338815
wst04-VHDL20_DWLG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 339600
wst04-VHDL20_DWLH_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:31:26 342131
wst04-VHDL20_DWLH_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:33 341160
wst04-VHDL20_DWLH_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:42 341488
wst04-VHDL20_DWLH_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:52 342467
wst04-VHDL20_DWLH_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:31:24 346611
wst04-VHDL20_DWLH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:40 346929
wst04-VHDL20_DWLH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 346889
wst04-VHDL20_DWLH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 348026
wst04-VHDL20_DWLI_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:31:26 343601
wst04-VHDL20_DWLI_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:33 343343
wst04-VHDL20_DWLI_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:42 343625
wst04-VHDL20_DWLI_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:31:02 388406
wst04-VHDL20_DWLI_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:31:24 343605
wst04-VHDL20_DWLI_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 343224
wst04-VHDL20_DWLI_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 343062
wst04-VHDL20_DWLI_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 388489
wst04-VHDL20_DWMO_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:19 358925
wst04-VHDL20_DWMO_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:13 462718
wst04-VHDL20_DWMO_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:18 462551
wst04-VHDL20_DWMO_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 462633
wst04-VHDL20_DWMO_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 355734
wst04-VHDL20_DWMO_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 460477
wst04-VHDL20_DWMO_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 459772
wst04-VHDL20_DWMO_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 459316
wst04-VHDL20_DWMP_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:39 459432
wst04-VHDL20_DWMP_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:29 561609
wst04-VHDL20_DWMP_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:18 562616
wst04-VHDL20_DWMP_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 459837
wst04-VHDL20_DWMP_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 461148
wst04-VHDL20_DWMP_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 564528
wst04-VHDL20_DWMP_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 564927
wst04-VHDL20_DWMP_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 460275
wst04-VHDL20_DWPG_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:31:26 346702
wst04-VHDL20_DWPG_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:33 243474
wst04-VHDL20_DWPG_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:32 346094
wst04-VHDL20_DWPG_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:52 391587
wst04-VHDL20_DWPG_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:31:24 350805
wst04-VHDL20_DWPG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 247443
wst04-VHDL20_DWPG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:33 349466
wst04-VHDL20_DWPG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:58 395118
wst04-VHDL20_DWPH_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:31:26 244334
wst04-VHDL20_DWPH_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:33 244000
wst04-VHDL20_DWPH_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:32 244330
wst04-VHDL20_DWPH_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:52 245483
wst04-VHDL20_DWPH_040800_COR-2609040800-omedes-..> 04-Sep-2026 12:04:29 250442
wst04-VHDL20_DWPH_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:31:24 249404
wst04-VHDL20_DWPH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 249024
wst04-VHDL20_DWPH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:33 248991
wst04-VHDL20_DWPH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 249316
wst04-VHDL20_DWSG_031800-2609031800-omedes--0.pdf 03-Sep-2026 18:30:19 350518
wst04-VHDL20_DWSG_040200-2609040200-omedes--0.pdf 04-Sep-2026 02:30:13 349122
wst04-VHDL20_DWSG_040400-2609040400-omedes--0.pdf 04-Sep-2026 05:00:14 349629
wst04-VHDL20_DWSG_040800-2609040800-omedes--0.pdf 04-Sep-2026 08:30:19 350715
wst04-VHDL20_DWSG_041800-2609041800-omedes--0.pdf 04-Sep-2026 18:30:20 351289
wst04-VHDL20_DWSG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 349091
wst04-VHDL20_DWSG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 349446
wst04-VHDL20_DWSG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 349617