Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Aug-2026 14:00:30 9424
FPDL13_DWMZ_060600 06-Aug-2026 14:02:23 4687
FPDL13_DWMZ_070600 07-Aug-2026 12:59:24 9546
SXDL31_DWAV_051800 05-Aug-2026 17:00:09 10503
SXDL31_DWAV_060800 06-Aug-2026 06:49:19 13593
SXDL31_DWAV_061800 06-Aug-2026 17:21:40 4784
SXDL31_DWAV_070800 07-Aug-2026 06:44:14 5800
SXDL31_DWAV_LATEST 07-Aug-2026 06:44:14 5800
SXDL33_DWAV_060000 06-Aug-2026 09:45:51 5835
SXDL33_DWAV_070000 07-Aug-2026 10:39:32 7075
SXDL33_DWAV_LATEST 07-Aug-2026 10:39:32 7075
ber01-FWDL39_DWMS_061200-2608061200-dsw--0-ia5 06-Aug-2026 10:03:47 1727
ber01-FWDL39_DWMS_071200-2608071200-dsw--0-ia5 07-Aug-2026 11:10:22 1688
ber01-VHDL13_DWEG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2249
ber01-VHDL13_DWEG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:16 2355
ber01-VHDL13_DWEH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2290
ber01-VHDL13_DWEH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:16 2292
ber01-VHDL13_DWEI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2101
ber01-VHDL13_DWEI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:11 2152
ber01-VHDL13_DWHG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2809
ber01-VHDL13_DWHG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2674
ber01-VHDL13_DWHH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2895
ber01-VHDL13_DWHH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2542
ber01-VHDL13_DWLG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:47 2994
ber01-VHDL13_DWLG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2469
ber01-VHDL13_DWLG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2180
ber01-VHDL13_DWLH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:37 2973
ber01-VHDL13_DWLH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2183
ber01-VHDL13_DWLH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2406
ber01-VHDL13_DWLI_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:20:57 2580
ber01-VHDL13_DWLI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2107
ber01-VHDL13_DWLI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2253
ber01-VHDL13_DWMO_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 2689
ber01-VHDL13_DWMO_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2426
ber01-VHDL13_DWMP_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 3429
ber01-VHDL13_DWMP_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2962
ber01-VHDL13_DWOG_051700-2608051700-dsw--0-ia5 05-Aug-2026 18:00:03 4302
ber01-VHDL13_DWOG_060300-2608060300-dsw--0-ia5 06-Aug-2026 03:00:15 3634
ber01-VHDL13_DWOG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 3682
ber01-VHDL13_DWOG_061700-2608061700-dsw--0-ia5 06-Aug-2026 18:00:06 3437
ber01-VHDL13_DWOG_070300-2608070300-dsw--0-ia5 07-Aug-2026 03:00:02 2965
ber01-VHDL13_DWOG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2831
ber01-VHDL13_DWON_051456-2608051456-dsw--0-ia5 05-Aug-2026 14:56:45 4242
ber01-VHDL13_DWON_051733-2608051733-dsw--0-ia5 05-Aug-2026 17:33:34 3344
ber01-VHDL13_DWON_052224-2608052224-dsw--0-ia5 05-Aug-2026 22:24:31 2973
ber01-VHDL13_DWON_060129-2608060129-dsw--0-ia5 06-Aug-2026 01:29:41 2973
ber01-VHDL13_DWON_060211-2608060211-dsw--0-ia5 06-Aug-2026 02:11:56 2853
ber01-VHDL13_DWON_060529-2608060529-dsw--0-ia5 06-Aug-2026 05:29:12 2786
ber01-VHDL13_DWON_060610-2608060610-dsw--0-ia5 06-Aug-2026 06:10:07 3035
ber01-VHDL13_DWON_060721-2608060721-dsw--0-ia5 06-Aug-2026 07:21:21 3035
ber01-VHDL13_DWON_060812-2608060812-dsw--0-ia5 06-Aug-2026 08:12:41 3035
ber01-VHDL13_DWON_061445-2608061445-dsw--0-ia5 06-Aug-2026 14:45:17 2673
ber01-VHDL13_DWON_061729-2608061729-dsw--0-ia5 06-Aug-2026 17:29:22 2417
ber01-VHDL13_DWON_070105-2608070105-dsw--0-ia5 07-Aug-2026 01:05:22 2944
ber01-VHDL13_DWON_070233-2608070233-dsw--0-ia5 07-Aug-2026 02:34:03 2944
ber01-VHDL13_DWON_070526-2608070526-dsw--0-ia5 07-Aug-2026 05:26:17 2762
ber01-VHDL13_DWON_070550-2608070550-dsw--0-ia5 07-Aug-2026 05:50:46 2808
ber01-VHDL13_DWON_070746-2608070746-dsw--0-ia5 07-Aug-2026 07:46:21 2870
ber01-VHDL13_DWPG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2255
ber01-VHDL13_DWPG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2502
ber01-VHDL13_DWPH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2734
ber01-VHDL13_DWPH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2996
ber01-VHDL13_DWSG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 2642
ber01-VHDL13_DWSG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2163
ber01-VHDL17_DWOG_061200-2608061200-dsw--0-ia5 06-Aug-2026 11:47:01 2621
ber01-VHDL17_DWOG_071200-2608071200-dsw--0-ia5 07-Aug-2026 11:58:06 2841
swis2-VHDL20_DWEG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1040
swis2-VHDL20_DWEG_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 732
swis2-VHDL20_DWEG_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:01:17 732
swis2-VHDL20_DWEG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 926
swis2-VHDL20_DWEG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1177
swis2-VHDL20_DWEG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 733
swis2-VHDL20_DWEG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 763
swis2-VHDL20_DWEG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 999
swis2-VHDL20_DWEH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1258
swis2-VHDL20_DWEH_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 992
swis2-VHDL20_DWEH_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:01:17 992
swis2-VHDL20_DWEH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1171
swis2-VHDL20_DWEH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1007
swis2-VHDL20_DWEH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 751
swis2-VHDL20_DWEH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 771
swis2-VHDL20_DWEH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 978
swis2-VHDL20_DWEI_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1060
swis2-VHDL20_DWEI_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 754
swis2-VHDL20_DWEI_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:01:21 754
swis2-VHDL20_DWEI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 949
swis2-VHDL20_DWEI_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1072
swis2-VHDL20_DWEI_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 755
swis2-VHDL20_DWEI_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 755
swis2-VHDL20_DWEI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 924
swis2-VHDL20_DWHG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:45:01 1585
swis2-VHDL20_DWHG_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:45:20 1252
swis2-VHDL20_DWHG_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:16 1249
swis2-VHDL20_DWHG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:45:34 1425
swis2-VHDL20_DWHG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:45:05 1520
swis2-VHDL20_DWHG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:45:56 1139
swis2-VHDL20_DWHG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 1160
swis2-VHDL20_DWHG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:55:45 1282
swis2-VHDL20_DWHH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:45:01 1584
swis2-VHDL20_DWHH_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:45:20 1370
swis2-VHDL20_DWHH_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:16 1370
swis2-VHDL20_DWHH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:45:34 1604
swis2-VHDL20_DWHH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:45:05 1698
swis2-VHDL20_DWHH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:45:56 1310
swis2-VHDL20_DWHH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 1343
swis2-VHDL20_DWHH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:55:45 1292
swis2-VHDL20_DWLG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:37 1611
swis2-VHDL20_DWLG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1343
swis2-VHDL20_DWLG_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:23 986
swis2-VHDL20_DWLG_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:12 959
swis2-VHDL20_DWLG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1139
swis2-VHDL20_DWLG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 958
swis2-VHDL20_DWLG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 773
swis2-VHDL20_DWLG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 851
swis2-VHDL20_DWLG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 998
swis2-VHDL20_DWLH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:27 1543
swis2-VHDL20_DWLH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1176
swis2-VHDL20_DWLH_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:23 758
swis2-VHDL20_DWLH_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:12 737
swis2-VHDL20_DWLH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 920
swis2-VHDL20_DWLH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 933
swis2-VHDL20_DWLH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 753
swis2-VHDL20_DWLH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 858
swis2-VHDL20_DWLH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1003
swis2-VHDL20_DWLI_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:57 1312
swis2-VHDL20_DWLI_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 995
swis2-VHDL20_DWLI_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:23 753
swis2-VHDL20_DWLI_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:12 732
swis2-VHDL20_DWLI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 912
swis2-VHDL20_DWLI_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 925
swis2-VHDL20_DWLI_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 740
swis2-VHDL20_DWLI_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 854
swis2-VHDL20_DWLI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1004
swis2-VHDL20_DWMO_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:09 1594
swis2-VHDL20_DWMO_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 1058
swis2-VHDL20_DWMO_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:02 1031
swis2-VHDL20_DWMO_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1288
swis2-VHDL20_DWMO_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1133
swis2-VHDL20_DWMO_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:02 839
swis2-VHDL20_DWMO_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:02 840
swis2-VHDL20_DWMO_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 1029
swis2-VHDL20_DWMP_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:09 1924
swis2-VHDL20_DWMP_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 1449
swis2-VHDL20_DWMP_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:02 1397
swis2-VHDL20_DWMP_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1768
swis2-VHDL20_DWMP_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1684
swis2-VHDL20_DWMP_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:02 1163
swis2-VHDL20_DWMP_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:02 1163
swis2-VHDL20_DWMP_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 1520
swis2-VHDL20_DWPG_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:01 1724
swis2-VHDL20_DWPG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1411
swis2-VHDL20_DWPG_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:23 769
swis2-VHDL20_DWPG_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:12 847
swis2-VHDL20_DWPG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1030
swis2-VHDL20_DWPG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 961
swis2-VHDL20_DWPG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 773
swis2-VHDL20_DWPG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 854
swis2-VHDL20_DWPG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1018
swis2-VHDL20_DWPH_050800_COR-2608050800-dsw--0-ia5 05-Aug-2026 13:23:16 1796
swis2-VHDL20_DWPH_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:31:00 1642
swis2-VHDL20_DWPH_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:23 994
swis2-VHDL20_DWPH_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:12 953
swis2-VHDL20_DWPH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1136
swis2-VHDL20_DWPH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 1014
swis2-VHDL20_DWPH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 903
swis2-VHDL20_DWPH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 977
swis2-VHDL20_DWPH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1205
swis2-VHDL20_DWSG_051800-2608051800-dsw--0-ia5 05-Aug-2026 18:30:01 1335
swis2-VHDL20_DWSG_060200-2608060200-dsw--0-ia5 06-Aug-2026 02:30:01 1020
swis2-VHDL20_DWSG_060400-2608060400-dsw--0-ia5 06-Aug-2026 05:00:16 1072
swis2-VHDL20_DWSG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1226
swis2-VHDL20_DWSG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:10 1205
swis2-VHDL20_DWSG_061800_COR-2608061800-dsw--0-ia5 06-Aug-2026 19:36:21 1412
swis2-VHDL20_DWSG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 791
swis2-VHDL20_DWSG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 663
swis2-VHDL20_DWSG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 915
wst04-VHDL20_DWEG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 239458
wst04-VHDL20_DWEG_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 237893
wst04-VHDL20_DWEG_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:12 237762
wst04-VHDL20_DWEG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 238843
wst04-VHDL20_DWEG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 239358
wst04-VHDL20_DWEG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 237266
wst04-VHDL20_DWEG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 237156
wst04-VHDL20_DWEG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 238379
wst04-VHDL20_DWEH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:23 237871
wst04-VHDL20_DWEH_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 236502
wst04-VHDL20_DWEH_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:12 236611
wst04-VHDL20_DWEH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 237867
wst04-VHDL20_DWEH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 236361
wst04-VHDL20_DWEH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 235399
wst04-VHDL20_DWEH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 235532
wst04-VHDL20_DWEH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 236761
wst04-VHDL20_DWEI_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 343600
wst04-VHDL20_DWEI_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 342593
wst04-VHDL20_DWEI_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:12 342416
wst04-VHDL20_DWEI_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 342947
wst04-VHDL20_DWEI_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:19 343713
wst04-VHDL20_DWEI_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 342886
wst04-VHDL20_DWEI_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 342719
wst04-VHDL20_DWEI_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 343320
wst04-VHDL20_DWHG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:45:12 342574
wst04-VHDL20_DWHG_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:45:20 341375
wst04-VHDL20_DWHG_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:16 341160
wst04-VHDL20_DWHG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:45:34 342815
wst04-VHDL20_DWHG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:45:11 334442
wst04-VHDL20_DWHG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:45:56 332845
wst04-VHDL20_DWHG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 333117
wst04-VHDL20_DWHG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:55:45 333658
wst04-VHDL20_DWHH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:45:12 329731
wst04-VHDL20_DWHH_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:45:20 329500
wst04-VHDL20_DWHH_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:16 227025
wst04-VHDL20_DWHH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:45:34 329921
wst04-VHDL20_DWHH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:45:11 322409
wst04-VHDL20_DWHH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:45:56 321244
wst04-VHDL20_DWHH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 226804
wst04-VHDL20_DWHH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:55:45 321101
wst04-VHDL20_DWLG_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:21 345616
wst04-VHDL20_DWLG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 343527
wst04-VHDL20_DWLG_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:23 343286
wst04-VHDL20_DWLG_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:40 342841
wst04-VHDL20_DWLG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 343244
wst04-VHDL20_DWLG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 330830
wst04-VHDL20_DWLG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330080
wst04-VHDL20_DWLG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:40 329875
wst04-VHDL20_DWLG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 330161
wst04-VHDL20_DWLH_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:01 345003
wst04-VHDL20_DWLH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 344072
wst04-VHDL20_DWLH_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:23 343462
wst04-VHDL20_DWLH_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:40 342752
wst04-VHDL20_DWLH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:55 343354
wst04-VHDL20_DWLH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 331042
wst04-VHDL20_DWLH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330047
wst04-VHDL20_DWLH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:40 329819
wst04-VHDL20_DWLH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 330123
wst04-VHDL20_DWLI_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:22:47 383027
wst04-VHDL20_DWLI_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 336629
wst04-VHDL20_DWLI_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:23 336929
wst04-VHDL20_DWLI_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:40 336204
wst04-VHDL20_DWLI_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 381344
wst04-VHDL20_DWLI_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 331439
wst04-VHDL20_DWLI_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330958
wst04-VHDL20_DWLI_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:42 330242
wst04-VHDL20_DWLI_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 375187
wst04-VHDL20_DWMO_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 364442
wst04-VHDL20_DWMO_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 477738
wst04-VHDL20_DWMO_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:16 477842
wst04-VHDL20_DWMO_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 478040
wst04-VHDL20_DWMO_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 342472
wst04-VHDL20_DWMO_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 460003
wst04-VHDL20_DWMO_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 459880
wst04-VHDL20_DWMO_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 460180
wst04-VHDL20_DWMP_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 501794
wst04-VHDL20_DWMP_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 618290
wst04-VHDL20_DWMP_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:16 616556
wst04-VHDL20_DWMP_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:28 500099
wst04-VHDL20_DWMP_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:19 483076
wst04-VHDL20_DWMP_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 597752
wst04-VHDL20_DWMP_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 597578
wst04-VHDL20_DWMP_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:25 483157
wst04-VHDL20_DWPG_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:21:27 385912
wst04-VHDL20_DWPG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 339944
wst04-VHDL20_DWPG_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:23 238861
wst04-VHDL20_DWPG_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:32 338001
wst04-VHDL20_DWPG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 382822
wst04-VHDL20_DWPG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 334807
wst04-VHDL20_DWPG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:26 235524
wst04-VHDL20_DWPG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:32 334112
wst04-VHDL20_DWPG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 378986
wst04-VHDL20_DWPH_050800_COR-2608050800-omedes-..> 05-Aug-2026 13:21:45 242230
wst04-VHDL20_DWPH_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:31:21 242271
wst04-VHDL20_DWPH_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:23 240837
wst04-VHDL20_DWPH_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:32 240228
wst04-VHDL20_DWPH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 240963
wst04-VHDL20_DWPH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 236847
wst04-VHDL20_DWPH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 235785
wst04-VHDL20_DWPH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:32 235264
wst04-VHDL20_DWPH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 235999
wst04-VHDL20_DWSG_051800-2608051800-omedes--0.pdf 05-Aug-2026 18:30:16 353465
wst04-VHDL20_DWSG_060200-2608060200-omedes--0.pdf 06-Aug-2026 02:30:17 352799
wst04-VHDL20_DWSG_060400-2608060400-omedes--0.pdf 06-Aug-2026 05:00:12 353013
wst04-VHDL20_DWSG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:10 353299
wst04-VHDL20_DWSG_061800-2608061800-omedes--0.pdf 06-Aug-2026 19:36:30 348211
wst04-VHDL20_DWSG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 346162
wst04-VHDL20_DWSG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 345800
wst04-VHDL20_DWSG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 346574