Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Jan-2026 15:06:48 3372
FPDL13_DWMZ_120600 12-Jan-2026 14:08:44 2637
SXDL31_DWAV_101800 10-Jan-2026 18:12:49 7477
SXDL31_DWAV_110800 11-Jan-2026 09:07:24 10743
SXDL31_DWAV_111800 11-Jan-2026 17:57:43 9990
SXDL31_DWAV_120800 12-Jan-2026 10:14:58 8522
SXDL31_DWAV_LATEST 12-Jan-2026 10:14:58 8522
SXDL33_DWAV_110000 11-Jan-2026 11:05:29 9006
SXDL33_DWAV_120000 12-Jan-2026 11:27:29 6347
SXDL33_DWAV_LATEST 12-Jan-2026 11:27:29 6347
ber01-FWDL39_DWMS_111230-2601111230-dsw--0-ia5 11-Jan-2026 12:23:15 1670
ber01-FWDL39_DWMS_121230-2601121230-dsw--0-ia5 12-Jan-2026 12:29:01 2010
ber01-VHDL13_DWEH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:16 3872
ber01-VHDL13_DWEH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:11 4188
ber01-VHDL13_DWEH_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:11 4148
ber01-VHDL13_DWEH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:17 4064
ber01-VHDL13_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 4021
ber01-VHDL13_DWEH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3924
ber01-VHDL13_DWEH_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:12 3684
ber01-VHDL13_DWEH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:16 2912
ber01-VHDL13_DWHG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:06 3416
ber01-VHDL13_DWHG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:06 4173
ber01-VHDL13_DWHG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4173
ber01-VHDL13_DWHG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3986
ber01-VHDL13_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4635
ber01-VHDL13_DWHG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4318
ber01-VHDL13_DWHG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4000
ber01-VHDL13_DWHG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3712
ber01-VHDL13_DWHH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:06 3494
ber01-VHDL13_DWHH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:06 3912
ber01-VHDL13_DWHH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 3894
ber01-VHDL13_DWHH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3805
ber01-VHDL13_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4090
ber01-VHDL13_DWHH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4174
ber01-VHDL13_DWHH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3974
ber01-VHDL13_DWHH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3936
ber01-VHDL13_DWLG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2654
ber01-VHDL13_DWLG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3041
ber01-VHDL13_DWLG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2946
ber01-VHDL13_DWLG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3124
ber01-VHDL13_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2815
ber01-VHDL13_DWLG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3383
ber01-VHDL13_DWLG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3296
ber01-VHDL13_DWLG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3258
ber01-VHDL13_DWLH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2539
ber01-VHDL13_DWLH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2842
ber01-VHDL13_DWLH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2942
ber01-VHDL13_DWLH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3080
ber01-VHDL13_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2928
ber01-VHDL13_DWLH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3293
ber01-VHDL13_DWLH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3217
ber01-VHDL13_DWLH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3078
ber01-VHDL13_DWLI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2486
ber01-VHDL13_DWLI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2745
ber01-VHDL13_DWLI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2833
ber01-VHDL13_DWLI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 2942
ber01-VHDL13_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2798
ber01-VHDL13_DWLI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3044
ber01-VHDL13_DWLI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 2928
ber01-VHDL13_DWLI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2921
ber01-VHDL13_DWMG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 3181
ber01-VHDL13_DWMG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3650
ber01-VHDL13_DWMG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3627
ber01-VHDL13_DWMG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3640
ber01-VHDL13_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3285
ber01-VHDL13_DWMG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3400
ber01-VHDL13_DWMG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3400
ber01-VHDL13_DWMG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 4048
ber01-VHDL13_DWMO_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2982
ber01-VHDL13_DWMO_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3355
ber01-VHDL13_DWMO_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3365
ber01-VHDL13_DWMO_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3563
ber01-VHDL13_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3292
ber01-VHDL13_DWMO_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3530
ber01-VHDL13_DWMO_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3530
ber01-VHDL13_DWMO_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 3718
ber01-VHDL13_DWMP_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 3294
ber01-VHDL13_DWMP_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3924
ber01-VHDL13_DWMP_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 3916
ber01-VHDL13_DWMP_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3985
ber01-VHDL13_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3551
ber01-VHDL13_DWMP_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3723
ber01-VHDL13_DWMP_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3723
ber01-VHDL13_DWMP_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 4178
ber01-VHDL13_DWOG_101700-2601101700-dsw--0-ia5 10-Jan-2026 19:00:01 5061
ber01-VHDL13_DWOG_110300-2601110300-dsw--0-ia5 11-Jan-2026 04:00:01 5455
ber01-VHDL13_DWOG_110800-2601110800-dsw--0-ia5 11-Jan-2026 10:16:42 5616
ber01-VHDL13_DWOG_110800_COR-2601110800-dsw--0-ia5 11-Jan-2026 15:00:00 5620
ber01-VHDL13_DWOG_111700-2601111700-dsw--0-ia5 11-Jan-2026 19:00:01 5442
ber01-VHDL13_DWOG_120300-2601120300-dsw--0-ia5 12-Jan-2026 04:00:04 5098
ber01-VHDL13_DWOG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 5559
ber01-VHDL13_DWOH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:16 3424
ber01-VHDL13_DWOH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:11 3728
ber01-VHDL13_DWOH_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:16 3689
ber01-VHDL13_DWOH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:17 3528
ber01-VHDL13_DWOH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 3596
ber01-VHDL13_DWOH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3406
ber01-VHDL13_DWOH_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:12 3327
ber01-VHDL13_DWOH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:16 2957
ber01-VHDL13_DWOI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:28:11 3175
ber01-VHDL13_DWOI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:28:17 3456
ber01-VHDL13_DWOI_110400-2601110400-dsw--0-ia5 11-Jan-2026 05:58:16 3412
ber01-VHDL13_DWOI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:28:11 3304
ber01-VHDL13_DWOI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:11 3118
ber01-VHDL13_DWOI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3062
ber01-VHDL13_DWOI_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:16 2981
ber01-VHDL13_DWOI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:12 2590
ber01-VHDL13_DWON_101551-2601101551-dsw--0-ia5 10-Jan-2026 15:51:17 3655
ber01-VHDL13_DWON_101818-2601101818-dsw--0-ia5 10-Jan-2026 18:18:21 3664
ber01-VHDL13_DWON_102334-2601102334-dsw--0-ia5 10-Jan-2026 23:34:47 4042
ber01-VHDL13_DWON_110154-2601110154-dsw--0-ia5 11-Jan-2026 01:54:56 4016
ber01-VHDL13_DWON_110357-2601110357-dsw--0-ia5 11-Jan-2026 03:57:31 4016
ber01-VHDL13_DWON_110421-2601110421-dsw--0-ia5 11-Jan-2026 04:21:27 4016
ber01-VHDL13_DWON_110626-2601110626-dsw--0-ia5 11-Jan-2026 06:26:52 4411
ber01-VHDL13_DWON_110709-2601110709-dsw--0-ia5 11-Jan-2026 07:09:07 4405
ber01-VHDL13_DWON_110852-2601110852-dsw--0-ia5 11-Jan-2026 08:52:59 4375
ber01-VHDL13_DWON_111016-2601111016-dsw--0-ia5 11-Jan-2026 10:16:12 4375
ber01-VHDL13_DWON_111021-2601111021-dsw--0-ia5 11-Jan-2026 10:21:11 4375
ber01-VHDL13_DWON_111459-2601111459-dsw--0-ia5 11-Jan-2026 14:59:22 4375
ber01-VHDL13_DWON_111557-2601111557-dsw--0-ia5 11-Jan-2026 15:57:32 3780
ber01-VHDL13_DWON_111852-2601111852-dsw--0-ia5 11-Jan-2026 18:52:26 3768
ber01-VHDL13_DWON_112238-2601112238-dsw--0-ia5 11-Jan-2026 22:38:31 3859
ber01-VHDL13_DWON_112357-2601112357-dsw--0-ia5 11-Jan-2026 23:57:46 3615
ber01-VHDL13_DWON_120620-2601120620-dsw--0-ia5 12-Jan-2026 06:20:47 3583
ber01-VHDL13_DWON_120718-2601120718-dsw--0-ia5 12-Jan-2026 07:18:37 3712
ber01-VHDL13_DWON_120911-2601120911-dsw--0-ia5 12-Jan-2026 09:11:57 3712
ber01-VHDL13_DWPG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 1929
ber01-VHDL13_DWPG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2491
ber01-VHDL13_DWPG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2569
ber01-VHDL13_DWPG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 2948
ber01-VHDL13_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2546
ber01-VHDL13_DWPG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 2789
ber01-VHDL13_DWPG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3101
ber01-VHDL13_DWPG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2964
ber01-VHDL13_DWPG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:25:46 3121
ber01-VHDL13_DWPH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:01 2275
ber01-VHDL13_DWPH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 2617
ber01-VHDL13_DWPH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:02 2807
ber01-VHDL13_DWPH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 3015
ber01-VHDL13_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2466
ber01-VHDL13_DWPH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 2709
ber01-VHDL13_DWPH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3056
ber01-VHDL13_DWPH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2919
ber01-VHDL13_DWPH_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:26:31 3165
ber01-VHDL13_DWSG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:30:03 3422
ber01-VHDL13_DWSG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:30:01 3954
ber01-VHDL13_DWSG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 3963
ber01-VHDL13_DWSG_110400_COR-2601110400-dsw--0-ia5 11-Jan-2026 06:32:22 4274
ber01-VHDL13_DWSG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:30:05 4256
ber01-VHDL13_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 4093
ber01-VHDL13_DWSG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4102
ber01-VHDL13_DWSG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4160
ber01-VHDL13_DWSG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 3731
ber01-VHDL13_DWSG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 12:21:21 3230
ber01-VHDL17_DWOG_111200-2601111200-dsw--0-ia5 11-Jan-2026 12:36:29 3302
ber01-VHDL17_DWOG_121200-2601121200-dsw--0-ia5 12-Jan-2026 12:23:26 2344
swis2-VHDL20_DWEG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 3819
swis2-VHDL20_DWEG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4073
swis2-VHDL20_DWEG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:07 4298
swis2-VHDL20_DWEG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4363
swis2-VHDL20_DWEG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4211
swis2-VHDL20_DWEG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3951
swis2-VHDL20_DWEG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3733
swis2-VHDL20_DWEG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3521
swis2-VHDL20_DWEH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 4295
swis2-VHDL20_DWEH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4578
swis2-VHDL20_DWEH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:07 4753
swis2-VHDL20_DWEH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4903
swis2-VHDL20_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4647
swis2-VHDL20_DWEH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 4414
swis2-VHDL20_DWEH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4082
swis2-VHDL20_DWEH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3480
swis2-VHDL20_DWEI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:06 3595
swis2-VHDL20_DWEI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 3817
swis2-VHDL20_DWEI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:06 4035
swis2-VHDL20_DWEI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4101
swis2-VHDL20_DWEI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3741
swis2-VHDL20_DWEI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3525
swis2-VHDL20_DWEI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3335
swis2-VHDL20_DWEI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3117
swis2-VHDL20_DWHG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3599
swis2-VHDL20_DWHG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4359
swis2-VHDL20_DWHG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4356
swis2-VHDL20_DWHG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4705
swis2-VHDL20_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4818
swis2-VHDL20_DWHG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4504
swis2-VHDL20_DWHG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4183
swis2-VHDL20_DWHG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4248
swis2-VHDL20_DWHH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3680
swis2-VHDL20_DWHH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4098
swis2-VHDL20_DWHH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:07 4080
swis2-VHDL20_DWHH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4524
swis2-VHDL20_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4276
swis2-VHDL20_DWHH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4360
swis2-VHDL20_DWHH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4160
swis2-VHDL20_DWHH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 4479
swis2-VHDL20_DWLG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3052
swis2-VHDL20_DWLG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3444
swis2-VHDL20_DWLG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3367
swis2-VHDL20_DWLG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3723
swis2-VHDL20_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3230
swis2-VHDL20_DWLG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3885
swis2-VHDL20_DWLG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3774
swis2-VHDL20_DWLG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3868
swis2-VHDL20_DWLH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2918
swis2-VHDL20_DWLH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3221
swis2-VHDL20_DWLH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3354
swis2-VHDL20_DWLH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3667
swis2-VHDL20_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3334
swis2-VHDL20_DWLH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3808
swis2-VHDL20_DWLH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3726
swis2-VHDL20_DWLH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3723
swis2-VHDL20_DWLI_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2860
swis2-VHDL20_DWLI_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3119
swis2-VHDL20_DWLI_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3240
swis2-VHDL20_DWLI_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3515
swis2-VHDL20_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3199
swis2-VHDL20_DWLI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3554
swis2-VHDL20_DWLI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3408
swis2-VHDL20_DWLI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3532
swis2-VHDL20_DWMG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3594
swis2-VHDL20_DWMG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 4132
swis2-VHDL20_DWMG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4212
swis2-VHDL20_DWMG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4517
swis2-VHDL20_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3870
swis2-VHDL20_DWMG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 3982
swis2-VHDL20_DWMG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3911
swis2-VHDL20_DWMG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4828
swis2-VHDL20_DWMO_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3441
swis2-VHDL20_DWMO_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 3782
swis2-VHDL20_DWMO_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 3961
swis2-VHDL20_DWMO_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4455
swis2-VHDL20_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3888
swis2-VHDL20_DWMO_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4118
swis2-VHDL20_DWMO_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4048
swis2-VHDL20_DWMO_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4525
swis2-VHDL20_DWMP_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3671
swis2-VHDL20_DWMP_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 4410
swis2-VHDL20_DWMP_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4498
swis2-VHDL20_DWMP_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4865
swis2-VHDL20_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4114
swis2-VHDL20_DWMP_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4312
swis2-VHDL20_DWMP_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4236
swis2-VHDL20_DWMP_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 5165
swis2-VHDL20_DWPG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2433
swis2-VHDL20_DWPG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 2856
swis2-VHDL20_DWPG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 2904
swis2-VHDL20_DWPG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3498
swis2-VHDL20_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3096
swis2-VHDL20_DWPG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3127
swis2-VHDL20_DWPG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3666
swis2-VHDL20_DWPG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3718
swis2-VHDL20_DWPG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:31:22 3875
swis2-VHDL20_DWPH_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 2779
swis2-VHDL20_DWPH_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:01 2981
swis2-VHDL20_DWPH_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:00:11 3144
swis2-VHDL20_DWPH_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 3564
swis2-VHDL20_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3015
swis2-VHDL20_DWPH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3046
swis2-VHDL20_DWPH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3617
swis2-VHDL20_DWPH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3644
swis2-VHDL20_DWPH_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:31:50 3890
swis2-VHDL20_DWSG_101800-2601101800-dsw--0-ia5 10-Jan-2026 19:45:02 3857
swis2-VHDL20_DWSG_110200-2601110200-dsw--0-ia5 11-Jan-2026 03:45:07 4406
swis2-VHDL20_DWSG_110400-2601110400-dsw--0-ia5 11-Jan-2026 06:15:01 4494
swis2-VHDL20_DWSG_110400_COR-2601110400-dsw--0-ia5 11-Jan-2026 06:32:22 4805
swis2-VHDL20_DWSG_110800-2601110800-dsw--0-ia5 11-Jan-2026 09:45:02 4988
swis2-VHDL20_DWSG_111300-2601111300-dsw--0-ia5 11-Jan-2026 14:45:08 4799
swis2-VHDL20_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:03 4619
swis2-VHDL20_DWSG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 4618
swis2-VHDL20_DWSG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:02 4561
swis2-VHDL20_DWSG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4330
swis2-VHDL20_DWSG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 12:21:21 3811
swis2-VHDL20_DWSG_121300-2601121300-dsw--0-ia5 12-Jan-2026 14:45:09 3689
wst04-VHDL20_DWEG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 232805
wst04-VHDL20_DWEG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 233369
wst04-VHDL20_DWEG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:27 233147
wst04-VHDL20_DWEG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 231495
wst04-VHDL20_DWEG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 230426
wst04-VHDL20_DWEG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 231007
wst04-VHDL20_DWEG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:26 230571
wst04-VHDL20_DWEG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 240378
wst04-VHDL20_DWEH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 228447
wst04-VHDL20_DWEH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 228847
wst04-VHDL20_DWEH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 228623
wst04-VHDL20_DWEH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 234078
wst04-VHDL20_DWEH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 233710
wst04-VHDL20_DWEH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 233772
wst04-VHDL20_DWEH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 232437
wst04-VHDL20_DWEH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 232516
wst04-VHDL20_DWEI_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 322287
wst04-VHDL20_DWEI_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 322255
wst04-VHDL20_DWEI_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:27 322491
wst04-VHDL20_DWEI_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:22 319515
wst04-VHDL20_DWEI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 318758
wst04-VHDL20_DWEI_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 318680
wst04-VHDL20_DWEI_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:26 317981
wst04-VHDL20_DWEI_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 334392
wst04-VHDL20_DWHG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 309701
wst04-VHDL20_DWHG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 310535
wst04-VHDL20_DWHG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:11 310432
wst04-VHDL20_DWHG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:22 309864
wst04-VHDL20_DWHG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 309251
wst04-VHDL20_DWHG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 309134
wst04-VHDL20_DWHG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:11 308103
wst04-VHDL20_DWHG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 314108
wst04-VHDL20_DWHH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 299180
wst04-VHDL20_DWHH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:11 299903
wst04-VHDL20_DWHH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:16 299891
wst04-VHDL20_DWHH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:16 302176
wst04-VHDL20_DWHH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 301685
wst04-VHDL20_DWHH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 301620
wst04-VHDL20_DWHH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:11 301445
wst04-VHDL20_DWHH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 307493
wst04-VHDL20_DWLG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 312505
wst04-VHDL20_DWLG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 313798
wst04-VHDL20_DWLG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 313096
wst04-VHDL20_DWLG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 306851
wst04-VHDL20_DWLG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 304475
wst04-VHDL20_DWLG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 305713
wst04-VHDL20_DWLG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 305574
wst04-VHDL20_DWLG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:36 310289
wst04-VHDL20_DWLH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 306720
wst04-VHDL20_DWLH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 307399
wst04-VHDL20_DWLH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 307333
wst04-VHDL20_DWLH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 305479
wst04-VHDL20_DWLH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 303368
wst04-VHDL20_DWLH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 304046
wst04-VHDL20_DWLH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 303919
wst04-VHDL20_DWLH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:32 311581
wst04-VHDL20_DWLI_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:27 312141
wst04-VHDL20_DWLI_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:26 312852
wst04-VHDL20_DWLI_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:41 312755
wst04-VHDL20_DWLI_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 309359
wst04-VHDL20_DWLI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 307672
wst04-VHDL20_DWLI_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 307919
wst04-VHDL20_DWLI_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 307709
wst04-VHDL20_DWLI_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:32 318897
wst04-VHDL20_DWMG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 525401
wst04-VHDL20_DWMG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 525892
wst04-VHDL20_DWMG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 525787
wst04-VHDL20_DWMG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 518963
wst04-VHDL20_DWMG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 516689
wst04-VHDL20_DWMG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 516640
wst04-VHDL20_DWMG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 516563
wst04-VHDL20_DWMG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 522652
wst04-VHDL20_DWMO_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:17 423169
wst04-VHDL20_DWMO_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 422964
wst04-VHDL20_DWMO_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:17 423582
wst04-VHDL20_DWMO_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 419572
wst04-VHDL20_DWMO_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 418583
wst04-VHDL20_DWMO_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:17 418508
wst04-VHDL20_DWMO_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:16 418906
wst04-VHDL20_DWMO_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:12 421098
wst04-VHDL20_DWMP_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 541322
wst04-VHDL20_DWMP_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 540687
wst04-VHDL20_DWMP_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:21 542545
wst04-VHDL20_DWMP_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:16 545590
wst04-VHDL20_DWMP_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 543939
wst04-VHDL20_DWMP_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:17 541939
wst04-VHDL20_DWMP_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 543723
wst04-VHDL20_DWMP_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 558286
wst04-VHDL20_DWPG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 306891
wst04-VHDL20_DWPG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:26 307412
wst04-VHDL20_DWPG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:33 306917
wst04-VHDL20_DWPG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:32 352543
wst04-VHDL20_DWPG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 306905
wst04-VHDL20_DWPG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 306879
wst04-VHDL20_DWPG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:31 307095
wst04-VHDL20_DWPG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:26 356558
wst04-VHDL20_DWPG_120800_COR-2601120800-omedes-..> 12-Jan-2026 14:30:45 356673
wst04-VHDL20_DWPH_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:21 267787
wst04-VHDL20_DWPH_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:22 223526
wst04-VHDL20_DWPH_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:00:33 224243
wst04-VHDL20_DWPH_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:26 270398
wst04-VHDL20_DWPH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 267645
wst04-VHDL20_DWPH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 222938
wst04-VHDL20_DWPH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:31 223309
wst04-VHDL20_DWPH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:26 268248
wst04-VHDL20_DWPH_120800_COR-2601120800-omedes-..> 12-Jan-2026 14:29:22 268528
wst04-VHDL20_DWSG_101800-2601101800-omedes--0.pdf 10-Jan-2026 19:45:11 338801
wst04-VHDL20_DWSG_110200-2601110200-omedes--0.pdf 11-Jan-2026 03:45:16 339840
wst04-VHDL20_DWSG_110400-2601110400-omedes--0.pdf 11-Jan-2026 06:15:17 339967
wst04-VHDL20_DWSG_110400_COR-2601110400-omedes-..> 11-Jan-2026 06:32:25 341560
wst04-VHDL20_DWSG_110800-2601110800-omedes--0.pdf 11-Jan-2026 09:45:12 338675
wst04-VHDL20_DWSG_111300-2601111300-omedes--0.pdf 11-Jan-2026 14:45:11 338677
wst04-VHDL20_DWSG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 337722
wst04-VHDL20_DWSG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 337465
wst04-VHDL20_DWSG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:16 337463
wst04-VHDL20_DWSG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:12 344350
wst04-VHDL20_DWSG_120800_COR-2601120800-omedes-..> 12-Jan-2026 12:21:31 342980
wst04-VHDL20_DWSG_121300-2601121300-omedes--0.pdf 12-Jan-2026 14:45:16 342939