Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Sep-2026 10:25:40 3344
FPDL13_DWMZ_280600 28-Sep-2026 12:51:39 2857
SXDL31_DWAV_270800 27-Sep-2026 07:39:55 7714
SXDL31_DWAV_271800 27-Sep-2026 15:27:00 2617
SXDL31_DWAV_280800 28-Sep-2026 07:21:30 12182
SXDL31_DWAV_281800 28-Sep-2026 17:40:50 5358
SXDL31_DWAV_LATEST 28-Sep-2026 17:40:50 5358
SXDL33_DWAV_270000 27-Sep-2026 10:10:30 12261
SXDL33_DWAV_280000 28-Sep-2026 09:39:59 6236
SXDL33_DWAV_LATEST 28-Sep-2026 09:39:59 6236
ber01-FWDL39_DWMS_271200-2609271200-dsw--0-ia5 27-Sep-2026 11:12:18 1457
ber01-FWDL39_DWMS_271200_COR-2609271200-dsw--0-ia5 27-Sep-2026 12:32:24 1447
ber01-FWDL39_DWMS_281200-2609281200-dsw--0-ia5 28-Sep-2026 12:29:14 1258
ber01-VHDL13_DWEG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:28:19 2339
ber01-VHDL13_DWEG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:28:19 2366
ber01-VHDL13_DWEH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:28:19 2454
ber01-VHDL13_DWEH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:28:19 2696
ber01-VHDL13_DWEI_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:28:13 2345
ber01-VHDL13_DWEI_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:28:19 2384
ber01-VHDL13_DWHG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 2564
ber01-VHDL13_DWHG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2887
ber01-VHDL13_DWHH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 2674
ber01-VHDL13_DWHH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2672
ber01-VHDL13_DWLG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 2552
ber01-VHDL13_DWLG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2418
ber01-VHDL13_DWLH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 2032
ber01-VHDL13_DWLH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2081
ber01-VHDL13_DWLI_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 2202
ber01-VHDL13_DWLI_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2007
ber01-VHDL13_DWMO_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 2609
ber01-VHDL13_DWMO_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2598
ber01-VHDL13_DWMP_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 2555
ber01-VHDL13_DWMP_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2523
ber01-VHDL13_DWOG_261700-2609261700-dsw--0-ia5 26-Sep-2026 18:00:04 2730
ber01-VHDL13_DWOG_261700_COR-2609261700-dsw--0-ia5 26-Sep-2026 19:48:53 2847
ber01-VHDL13_DWOG_270300-2609270300-dsw--0-ia5 27-Sep-2026 03:01:16 3066
ber01-VHDL13_DWOG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 3135
ber01-VHDL13_DWOG_271700-2609271700-dsw--0-ia5 27-Sep-2026 18:00:04 2973
ber01-VHDL13_DWOG_280300-2609280300-dsw--0-ia5 28-Sep-2026 03:00:12 3162
ber01-VHDL13_DWOG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 3367
ber01-VHDL13_DWON_261914-2609261914-dsw--0-ia5 26-Sep-2026 19:14:49 3177
ber01-VHDL13_DWON_261947-2609261947-dsw--0-ia5 26-Sep-2026 19:48:20 3211
ber01-VHDL13_DWON_261948-2609261948-dsw--0-ia5 26-Sep-2026 19:48:37 3211
ber01-VHDL13_DWON_270006-2609270006-dsw--0-ia5 27-Sep-2026 00:06:39 3004
ber01-VHDL13_DWON_270221-2609270221-dsw--0-ia5 27-Sep-2026 02:22:03 3004
ber01-VHDL13_DWON_270250-2609270250-dsw--0-ia5 27-Sep-2026 02:51:30 3004
ber01-VHDL13_DWON_270508-2609270508-dsw--0-ia5 27-Sep-2026 05:08:13 3488
ber01-VHDL13_DWON_270613-2609270613-dsw--0-ia5 27-Sep-2026 06:14:04 3616
ber01-VHDL13_DWON_270816-2609270816-dsw--0-ia5 27-Sep-2026 08:16:29 3514
ber01-VHDL13_DWON_271438-2609271438-dsw--0-ia5 27-Sep-2026 14:39:01 3166
ber01-VHDL13_DWON_271623-2609271623-dsw--0-ia5 27-Sep-2026 16:23:17 3166
ber01-VHDL13_DWON_271747-2609271747-dsw--0-ia5 27-Sep-2026 17:47:47 3166
ber01-VHDL13_DWON_280033-2609280033-dsw--0-ia5 28-Sep-2026 00:34:13 3729
ber01-VHDL13_DWON_280524-2609280524-dsw--0-ia5 28-Sep-2026 05:24:28 3729
ber01-VHDL13_DWON_280605-2609280605-dsw--0-ia5 28-Sep-2026 06:05:23 3911
ber01-VHDL13_DWON_280731-2609280731-dsw--0-ia5 28-Sep-2026 07:32:06 3911
ber01-VHDL13_DWON_281442-2609281442-dsw--0-ia5 28-Sep-2026 14:43:25 3385
ber01-VHDL13_DWPG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 1711
ber01-VHDL13_DWPG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 1788
ber01-VHDL13_DWPH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 1940
ber01-VHDL13_DWPH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2144
ber01-VHDL13_DWSG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 2513
ber01-VHDL13_DWSG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 2521
ber01-VHDL17_DWOG_271200-2609271200-dsw--0-ia5 27-Sep-2026 12:00:33 2838
ber01-VHDL17_DWOG_281200-2609281200-dsw--0-ia5 28-Sep-2026 10:55:59 2893
swis2-VHDL20_DWEG_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 875
swis2-VHDL20_DWEG_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 739
swis2-VHDL20_DWEG_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:01:28 738
swis2-VHDL20_DWEG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 813
swis2-VHDL20_DWEG_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:04 908
swis2-VHDL20_DWEG_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 793
swis2-VHDL20_DWEG_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:01:18 793
swis2-VHDL20_DWEG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 950
swis2-VHDL20_DWEH_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 1071
swis2-VHDL20_DWEH_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 753
swis2-VHDL20_DWEH_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:01:28 752
swis2-VHDL20_DWEH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 807
swis2-VHDL20_DWEH_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:04 1210
swis2-VHDL20_DWEH_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 807
swis2-VHDL20_DWEH_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:01:18 807
swis2-VHDL20_DWEH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 1066
swis2-VHDL20_DWEI_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 1067
swis2-VHDL20_DWEI_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 761
swis2-VHDL20_DWEI_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:01:28 760
swis2-VHDL20_DWEI_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 818
swis2-VHDL20_DWEI_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:04 1205
swis2-VHDL20_DWEI_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 815
swis2-VHDL20_DWEI_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:01:18 815
swis2-VHDL20_DWEI_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 1080
swis2-VHDL20_DWHG_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:45:21 1084
swis2-VHDL20_DWHG_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:45:55 962
swis2-VHDL20_DWHG_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 959
swis2-VHDL20_DWHG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:45:57 1100
swis2-VHDL20_DWHG_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:45:11 1303
swis2-VHDL20_DWHG_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:45:28 1206
swis2-VHDL20_DWHG_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:18 1195
swis2-VHDL20_DWHG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:45:49 1408
swis2-VHDL20_DWHH_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:45:21 1043
swis2-VHDL20_DWHH_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:45:55 956
swis2-VHDL20_DWHH_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 956
swis2-VHDL20_DWHH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:45:57 1095
swis2-VHDL20_DWHH_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:45:11 1287
swis2-VHDL20_DWHH_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:45:28 1133
swis2-VHDL20_DWHH_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:18 1125
swis2-VHDL20_DWHH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:45:49 1264
swis2-VHDL20_DWLG_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:31:13 885
swis2-VHDL20_DWLG_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:38 763
swis2-VHDL20_DWLG_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 898
swis2-VHDL20_DWLG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:30 1067
swis2-VHDL20_DWLG_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:31:14 988
swis2-VHDL20_DWLG_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:25 791
swis2-VHDL20_DWLG_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:14 844
swis2-VHDL20_DWLG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:32 1013
swis2-VHDL20_DWLH_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:31:13 891
swis2-VHDL20_DWLH_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:38 769
swis2-VHDL20_DWLH_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 865
swis2-VHDL20_DWLH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:30 937
swis2-VHDL20_DWLH_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:31:14 928
swis2-VHDL20_DWLH_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:25 707
swis2-VHDL20_DWLH_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:14 744
swis2-VHDL20_DWLH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:32 816
swis2-VHDL20_DWLI_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:31:13 869
swis2-VHDL20_DWLI_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:38 748
swis2-VHDL20_DWLI_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 905
swis2-VHDL20_DWLI_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:30 976
swis2-VHDL20_DWLI_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:31:14 898
swis2-VHDL20_DWLI_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:25 702
swis2-VHDL20_DWLI_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:14 740
swis2-VHDL20_DWLI_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:32 811
swis2-VHDL20_DWMO_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 1153
swis2-VHDL20_DWMO_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 942
swis2-VHDL20_DWMO_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:04 950
swis2-VHDL20_DWMO_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 1184
swis2-VHDL20_DWMO_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:04 1262
swis2-VHDL20_DWMO_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 838
swis2-VHDL20_DWMO_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:04 781
swis2-VHDL20_DWMO_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 923
swis2-VHDL20_DWMP_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 1261
swis2-VHDL20_DWMP_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 928
swis2-VHDL20_DWMP_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:04 935
swis2-VHDL20_DWMP_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:11 1312
swis2-VHDL20_DWMP_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:04 1446
swis2-VHDL20_DWMP_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 837
swis2-VHDL20_DWMP_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:04 779
swis2-VHDL20_DWMP_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 1025
swis2-VHDL20_DWPG_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:31:13 1038
swis2-VHDL20_DWPG_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:38 875
swis2-VHDL20_DWPG_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 846
swis2-VHDL20_DWPG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:30 771
swis2-VHDL20_DWPG_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:31:14 804
swis2-VHDL20_DWPG_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:25 717
swis2-VHDL20_DWPG_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:14 755
swis2-VHDL20_DWPG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:32 826
swis2-VHDL20_DWPH_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:31:13 984
swis2-VHDL20_DWPH_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:38 817
swis2-VHDL20_DWPH_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 788
swis2-VHDL20_DWPH_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:30 774
swis2-VHDL20_DWPH_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:31:14 807
swis2-VHDL20_DWPH_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:25 692
swis2-VHDL20_DWPH_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:14 757
swis2-VHDL20_DWPH_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:32 829
swis2-VHDL20_DWSG_261800-2609261800-dsw--0-ia5 26-Sep-2026 18:30:09 999
swis2-VHDL20_DWSG_270200-2609270200-dsw--0-ia5 27-Sep-2026 02:30:04 910
swis2-VHDL20_DWSG_270400-2609270400-dsw--0-ia5 27-Sep-2026 05:00:18 901
swis2-VHDL20_DWSG_270800-2609270800-dsw--0-ia5 27-Sep-2026 08:30:06 995
swis2-VHDL20_DWSG_271800-2609271800-dsw--0-ia5 27-Sep-2026 18:30:13 1065
swis2-VHDL20_DWSG_280200-2609280200-dsw--0-ia5 28-Sep-2026 02:30:03 771
swis2-VHDL20_DWSG_280400-2609280400-dsw--0-ia5 28-Sep-2026 05:00:18 801
swis2-VHDL20_DWSG_280800-2609280800-dsw--0-ia5 28-Sep-2026 08:30:12 884
wst04-VHDL20_DWEG_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 241218
wst04-VHDL20_DWEG_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:14 239826
wst04-VHDL20_DWEG_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:14 239642
wst04-VHDL20_DWEG_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:17 240362
wst04-VHDL20_DWEG_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:15 241234
wst04-VHDL20_DWEG_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:15 239801
wst04-VHDL20_DWEG_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:14 239615
wst04-VHDL20_DWEG_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:32 240426
wst04-VHDL20_DWEH_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 235217
wst04-VHDL20_DWEH_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:14 233015
wst04-VHDL20_DWEH_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:14 233075
wst04-VHDL20_DWEH_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:17 233791
wst04-VHDL20_DWEH_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:15 235526
wst04-VHDL20_DWEH_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:15 233014
wst04-VHDL20_DWEH_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:14 233086
wst04-VHDL20_DWEH_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:12 234817
wst04-VHDL20_DWEI_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 347992
wst04-VHDL20_DWEI_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:14 346136
wst04-VHDL20_DWEI_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:18 345895
wst04-VHDL20_DWEI_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:20 346024
wst04-VHDL20_DWEI_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:34 348259
wst04-VHDL20_DWEI_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:19 346128
wst04-VHDL20_DWEI_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:14 345887
wst04-VHDL20_DWEI_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:32 347067
wst04-VHDL20_DWHG_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:45:21 347943
wst04-VHDL20_DWHG_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:45:55 347318
wst04-VHDL20_DWHG_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:18 347114
wst04-VHDL20_DWHG_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:45:57 348525
wst04-VHDL20_DWHG_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:45:13 347908
wst04-VHDL20_DWHG_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:45:28 347807
wst04-VHDL20_DWHG_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:18 347612
wst04-VHDL20_DWHG_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:45:49 349863
wst04-VHDL20_DWHH_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:45:21 333864
wst04-VHDL20_DWHH_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:45:55 333008
wst04-VHDL20_DWHH_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:18 228881
wst04-VHDL20_DWHH_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:45:57 333648
wst04-VHDL20_DWHH_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:45:13 333827
wst04-VHDL20_DWHH_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:45:28 333434
wst04-VHDL20_DWHH_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:18 229310
wst04-VHDL20_DWHH_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:45:49 334102
wst04-VHDL20_DWLG_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:31:29 333609
wst04-VHDL20_DWLG_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:38 333188
wst04-VHDL20_DWLG_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:44 334677
wst04-VHDL20_DWLG_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:56 334937
wst04-VHDL20_DWLG_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:31:24 334387
wst04-VHDL20_DWLG_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:25 333491
wst04-VHDL20_DWLG_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:44 333411
wst04-VHDL20_DWLG_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:52 334203
wst04-VHDL20_DWLH_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:31:23 337628
wst04-VHDL20_DWLH_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:38 337238
wst04-VHDL20_DWLH_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:44 337629
wst04-VHDL20_DWLH_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:56 338253
wst04-VHDL20_DWLH_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:31:28 337794
wst04-VHDL20_DWLH_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:25 337150
wst04-VHDL20_DWLH_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:44 337019
wst04-VHDL20_DWLH_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:52 337063
wst04-VHDL20_DWLI_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:31:23 339142
wst04-VHDL20_DWLI_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:38 338742
wst04-VHDL20_DWLI_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:44 339757
wst04-VHDL20_DWLI_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:56 384522
wst04-VHDL20_DWLI_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:31:24 338850
wst04-VHDL20_DWLI_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:25 338245
wst04-VHDL20_DWLI_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:44 338071
wst04-VHDL20_DWLI_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:52 382708
wst04-VHDL20_DWMO_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 353491
wst04-VHDL20_DWMO_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:28 455106
wst04-VHDL20_DWMO_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:14 455002
wst04-VHDL20_DWMO_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:20 455449
wst04-VHDL20_DWMO_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:34 353957
wst04-VHDL20_DWMO_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:15 455214
wst04-VHDL20_DWMO_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:14 455440
wst04-VHDL20_DWMO_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:32 455480
wst04-VHDL20_DWMP_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 460503
wst04-VHDL20_DWMP_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:28 561624
wst04-VHDL20_DWMP_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:18 561435
wst04-VHDL20_DWMP_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:30 460724
wst04-VHDL20_DWMP_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:34 460907
wst04-VHDL20_DWMP_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:19 561579
wst04-VHDL20_DWMP_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:18 561910
wst04-VHDL20_DWMP_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:32 461228
wst04-VHDL20_DWPG_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:31:23 347931
wst04-VHDL20_DWPG_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:38 243948
wst04-VHDL20_DWPG_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:34 347810
wst04-VHDL20_DWPG_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:56 392806
wst04-VHDL20_DWPG_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:31:24 347829
wst04-VHDL20_DWPG_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:27 244023
wst04-VHDL20_DWPG_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:32 347512
wst04-VHDL20_DWPG_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:31:01 392066
wst04-VHDL20_DWPH_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:31:23 242796
wst04-VHDL20_DWPH_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:38 242392
wst04-VHDL20_DWPH_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:34 242706
wst04-VHDL20_DWPH_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:56 243100
wst04-VHDL20_DWPH_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:31:24 242700
wst04-VHDL20_DWPH_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:25 242450
wst04-VHDL20_DWPH_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:32 242404
wst04-VHDL20_DWPH_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:52 242355
wst04-VHDL20_DWSG_261800-2609261800-omedes--0.pdf 26-Sep-2026 18:30:21 347438
wst04-VHDL20_DWSG_270200-2609270200-omedes--0.pdf 27-Sep-2026 02:30:14 347141
wst04-VHDL20_DWSG_270400-2609270400-omedes--0.pdf 27-Sep-2026 05:00:14 346929
wst04-VHDL20_DWSG_270800-2609270800-omedes--0.pdf 27-Sep-2026 08:30:20 347110
wst04-VHDL20_DWSG_271800-2609271800-omedes--0.pdf 27-Sep-2026 18:30:34 347888
wst04-VHDL20_DWSG_280200-2609280200-omedes--0.pdf 28-Sep-2026 02:30:15 347093
wst04-VHDL20_DWSG_280400-2609280400-omedes--0.pdf 28-Sep-2026 05:00:18 346651
wst04-VHDL20_DWSG_280800-2609280800-omedes--0.pdf 28-Sep-2026 08:30:32 347488