Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Jul-2026 10:57:49 2967
FPDL13_DWMZ_120600 12-Jul-2026 12:28:20 17491
SXDL31_DWAV_110800 11-Jul-2026 07:07:19 6415
SXDL31_DWAV_111800 11-Jul-2026 16:03:14 5170
SXDL31_DWAV_120800 12-Jul-2026 07:11:05 9143
SXDL31_DWAV_121800 12-Jul-2026 15:45:51 6741
SXDL31_DWAV_LATEST 12-Jul-2026 15:45:51 6741
SXDL33_DWAV_110000 11-Jul-2026 10:20:08 7020
SXDL33_DWAV_120000 12-Jul-2026 09:59:45 8275
SXDL33_DWAV_LATEST 12-Jul-2026 09:59:45 8275
ber01-FWDL39_DWMS_111200-2607111200-dsw--0-ia5 11-Jul-2026 11:58:41 1172
ber01-FWDL39_DWMS_121200-2607121200-dsw--0-ia5 12-Jul-2026 11:31:51 1224
ber01-VHDL13_DWEG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2114
ber01-VHDL13_DWEG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:17 2682
ber01-VHDL13_DWEH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2105
ber01-VHDL13_DWEH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:11 2469
ber01-VHDL13_DWEI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:28:17 2061
ber01-VHDL13_DWEI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:17 2481
ber01-VHDL13_DWHG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2694
ber01-VHDL13_DWHG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3348
ber01-VHDL13_DWHH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2833
ber01-VHDL13_DWHH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 3321
ber01-VHDL13_DWLG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2003
ber01-VHDL13_DWLG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2172
ber01-VHDL13_DWLH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1871
ber01-VHDL13_DWLH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2215
ber01-VHDL13_DWLI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1753
ber01-VHDL13_DWLI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2068
ber01-VHDL13_DWMO_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:14 2580
ber01-VHDL13_DWMO_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 2575
ber01-VHDL13_DWMP_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 2339
ber01-VHDL13_DWMP_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2631
ber01-VHDL13_DWOG_101700-2607101700-dsw--0-ia5 10-Jul-2026 18:00:01 2345
ber01-VHDL13_DWOG_110300-2607110300-dsw--0-ia5 11-Jul-2026 03:00:00 3384
ber01-VHDL13_DWOG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2885
ber01-VHDL13_DWOG_111700-2607111700-dsw--0-ia5 11-Jul-2026 18:00:01 2394
ber01-VHDL13_DWOG_120300-2607120300-dsw--0-ia5 12-Jul-2026 03:00:23 3914
ber01-VHDL13_DWOG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3910
ber01-VHDL13_DWON_101819-2607101819-dsw--0-ia5 10-Jul-2026 18:20:01 3369
ber01-VHDL13_DWON_102143-2607102143-dsw--0-ia5 10-Jul-2026 21:43:41 3362
ber01-VHDL13_DWON_110006-2607110006-dsw--0-ia5 11-Jul-2026 00:06:31 3846
ber01-VHDL13_DWON_110150-2607110150-dsw--0-ia5 11-Jul-2026 01:50:57 4028
ber01-VHDL13_DWON_110244-2607110244-dsw--0-ia5 11-Jul-2026 02:44:56 4028
ber01-VHDL13_DWON_110512-2607110512-dsw--0-ia5 11-Jul-2026 05:12:11 3949
ber01-VHDL13_DWON_110609-2607110609-dsw--0-ia5 11-Jul-2026 06:09:17 3625
ber01-VHDL13_DWON_110751-2607110751-dsw--0-ia5 11-Jul-2026 07:51:52 3480
ber01-VHDL13_DWON_111458-2607111458-dsw--0-ia5 11-Jul-2026 14:58:19 3104
ber01-VHDL13_DWON_111500-2607111500-dsw--0-ia5 11-Jul-2026 15:00:50 3104
ber01-VHDL13_DWON_111701-2607111701-dsw--0-ia5 11-Jul-2026 17:01:52 2832
ber01-VHDL13_DWON_111913-2607111913-dsw--0-ia5 11-Jul-2026 19:13:17 3744
ber01-VHDL13_DWON_112153-2607112153-dsw--0-ia5 11-Jul-2026 21:54:02 3740
ber01-VHDL13_DWON_112329-2607112329-dsw--0-ia5 11-Jul-2026 23:29:51 4171
ber01-VHDL13_DWON_120000-2607120000-dsw--0-ia5 12-Jul-2026 00:00:23 4171
ber01-VHDL13_DWON_120135-2607120135-dsw--0-ia5 12-Jul-2026 01:35:27 4135
ber01-VHDL13_DWON_120235-2607120235-dsw--0-ia5 12-Jul-2026 02:36:11 4135
ber01-VHDL13_DWON_120520-2607120520-dsw--0-ia5 12-Jul-2026 05:20:51 4351
ber01-VHDL13_DWON_120620-2607120620-dsw--0-ia5 12-Jul-2026 06:20:18 4351
ber01-VHDL13_DWON_120808-2607120808-dsw--0-ia5 12-Jul-2026 08:08:32 4351
ber01-VHDL13_DWON_120852-2607120852-dsw--0-ia5 12-Jul-2026 08:52:32 4351
ber01-VHDL13_DWON_121457-2607121457-dsw--0-ia5 12-Jul-2026 14:57:06 3528
ber01-VHDL13_DWON_121721-2607121721-dsw--0-ia5 12-Jul-2026 17:21:26 3229
ber01-VHDL13_DWPG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2265
ber01-VHDL13_DWPG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2304
ber01-VHDL13_DWPH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 1998
ber01-VHDL13_DWPH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2433
ber01-VHDL13_DWSG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 2604
ber01-VHDL13_DWSG_110800_COR-2607110800-dsw--0-ia5 11-Jul-2026 14:54:06 2904
ber01-VHDL13_DWSG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3172
ber01-VHDL17_DWOG_111200-2607111200-dsw--0-ia5 11-Jul-2026 11:55:52 2815
ber01-VHDL17_DWOG_121200-2607121200-dsw--0-ia5 12-Jul-2026 11:43:22 3183
swis2-VHDL20_DWEG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 923
swis2-VHDL20_DWEG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 743
swis2-VHDL20_DWEG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:16 743
swis2-VHDL20_DWEG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 913
swis2-VHDL20_DWEG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 958
swis2-VHDL20_DWEG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1005
swis2-VHDL20_DWEG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 1009
swis2-VHDL20_DWEG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1272
swis2-VHDL20_DWEH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 949
swis2-VHDL20_DWEH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 757
swis2-VHDL20_DWEH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:22 757
swis2-VHDL20_DWEH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 921
swis2-VHDL20_DWEH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1112
swis2-VHDL20_DWEH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 923
swis2-VHDL20_DWEH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 911
swis2-VHDL20_DWEH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1172
swis2-VHDL20_DWEI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:08 945
swis2-VHDL20_DWEI_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 765
swis2-VHDL20_DWEI_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:01:22 765
swis2-VHDL20_DWEI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 935
swis2-VHDL20_DWEI_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1118
swis2-VHDL20_DWEI_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 969
swis2-VHDL20_DWEI_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 1100
swis2-VHDL20_DWEI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1242
swis2-VHDL20_DWHG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 966
swis2-VHDL20_DWHG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:45:47 968
swis2-VHDL20_DWHG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 965
swis2-VHDL20_DWHG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:45:06 1047
swis2-VHDL20_DWHG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:45:44 1572
swis2-VHDL20_DWHG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:45:40 1398
swis2-VHDL20_DWHG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1395
swis2-VHDL20_DWHG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:45:01 1719
swis2-VHDL20_DWHH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:45:06 972
swis2-VHDL20_DWHH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:45:47 959
swis2-VHDL20_DWHH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 959
swis2-VHDL20_DWHH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:45:06 1021
swis2-VHDL20_DWHH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:45:44 1595
swis2-VHDL20_DWHH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:45:40 1504
swis2-VHDL20_DWHH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1504
swis2-VHDL20_DWHH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:45:01 1580
swis2-VHDL20_DWLG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 825
swis2-VHDL20_DWLG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 740
swis2-VHDL20_DWLG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:10 759
swis2-VHDL20_DWLG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 836
swis2-VHDL20_DWLG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1084
swis2-VHDL20_DWLG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1019
swis2-VHDL20_DWLG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1009
swis2-VHDL20_DWLG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1319
swis2-VHDL20_DWLH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 834
swis2-VHDL20_DWLH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 749
swis2-VHDL20_DWLH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 768
swis2-VHDL20_DWLH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 845
swis2-VHDL20_DWLH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1093
swis2-VHDL20_DWLH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1028
swis2-VHDL20_DWLH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1133
swis2-VHDL20_DWLH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1471
swis2-VHDL20_DWLI_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 827
swis2-VHDL20_DWLI_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 742
swis2-VHDL20_DWLI_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 761
swis2-VHDL20_DWLI_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 838
swis2-VHDL20_DWLI_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1086
swis2-VHDL20_DWLI_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1021
swis2-VHDL20_DWLI_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1011
swis2-VHDL20_DWLI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1321
swis2-VHDL20_DWMO_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 905
swis2-VHDL20_DWMO_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 800
swis2-VHDL20_DWMO_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:02 812
swis2-VHDL20_DWMO_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:14 973
swis2-VHDL20_DWMO_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1124
swis2-VHDL20_DWMO_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 832
swis2-VHDL20_DWMO_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:02 833
swis2-VHDL20_DWMO_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 993
swis2-VHDL20_DWMP_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 877
swis2-VHDL20_DWMP_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:02 800
swis2-VHDL20_DWMP_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:02 808
swis2-VHDL20_DWMP_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:13 957
swis2-VHDL20_DWMP_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1180
swis2-VHDL20_DWMP_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1023
swis2-VHDL20_DWMP_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:02 1025
swis2-VHDL20_DWMP_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1212
swis2-VHDL20_DWPG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 843
swis2-VHDL20_DWPG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 758
swis2-VHDL20_DWPG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:12 1033
swis2-VHDL20_DWPG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 1246
swis2-VHDL20_DWPG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1244
swis2-VHDL20_DWPG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1145
swis2-VHDL20_DWPG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1148
swis2-VHDL20_DWPG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1410
swis2-VHDL20_DWPH_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:31:01 840
swis2-VHDL20_DWPH_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:22 758
swis2-VHDL20_DWPH_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:10 777
swis2-VHDL20_DWPH_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:22 943
swis2-VHDL20_DWPH_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:31:01 1191
swis2-VHDL20_DWPH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1318
swis2-VHDL20_DWPH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1218
swis2-VHDL20_DWPH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1295
swis2-VHDL20_DWSG_101800-2607101800-dsw--0-ia5 10-Jul-2026 18:30:03 850
swis2-VHDL20_DWSG_110200-2607110200-dsw--0-ia5 11-Jul-2026 02:30:06 814
swis2-VHDL20_DWSG_110400-2607110400-dsw--0-ia5 11-Jul-2026 05:00:16 811
swis2-VHDL20_DWSG_110800-2607110800-dsw--0-ia5 11-Jul-2026 08:30:03 907
swis2-VHDL20_DWSG_111800-2607111800-dsw--0-ia5 11-Jul-2026 18:30:49 1235
swis2-VHDL20_DWSG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1039
swis2-VHDL20_DWSG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1036
swis2-VHDL20_DWSG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 1401
wst04-VHDL20_DWEG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:13 236532
wst04-VHDL20_DWEG_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 235385
wst04-VHDL20_DWEG_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 235040
wst04-VHDL20_DWEG_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:13 235971
wst04-VHDL20_DWEG_111800-2607111800-omedes--0.pdf 11-Jul-2026 18:30:49 237239
wst04-VHDL20_DWEG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 237268
wst04-VHDL20_DWEG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 236825
wst04-VHDL20_DWEG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:22 237708
wst04-VHDL20_DWEH_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 238400
wst04-VHDL20_DWEH_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 237615
wst04-VHDL20_DWEH_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 237482
wst04-VHDL20_DWEH_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:14 238388
wst04-VHDL20_DWEH_111800-2607111800-omedes--0.pdf 11-Jul-2026 18:30:49 235008
wst04-VHDL20_DWEH_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 234671
wst04-VHDL20_DWEH_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 234216
wst04-VHDL20_DWEH_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:21 235166
wst04-VHDL20_DWEI_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:30:17 335245
wst04-VHDL20_DWEI_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:30:19 334696
wst04-VHDL20_DWEI_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:12 334280
wst04-VHDL20_DWEI_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:30:16 334682
wst04-VHDL20_DWEI_111800-2607111800-omedes--0.pdf 11-Jul-2026 18:30:49 336906
wst04-VHDL20_DWEI_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 336665
wst04-VHDL20_DWEI_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 336337
wst04-VHDL20_DWEI_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:22 337311
wst04-VHDL20_DWHG_101800-2607101800-omedes--0.pdf 10-Jul-2026 18:45:13 348239
wst04-VHDL20_DWHG_110200-2607110200-omedes--0.pdf 11-Jul-2026 02:45:47 347657
wst04-VHDL20_DWHG_110400-2607110400-omedes--0.pdf 11-Jul-2026 05:00:16 347424
wst04-VHDL20_DWHG_110800-2607110800-omedes--0.pdf 11-Jul-2026 08:45:17 348418
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