Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Jul-2026 12:21:29 3860
FPDL13_DWMZ_150600 15-Jul-2026 13:40:45 4034
SXDL31_DWAV_131800 13-Jul-2026 17:11:43 7983
SXDL31_DWAV_140800 14-Jul-2026 08:04:05 13043
SXDL31_DWAV_141800 14-Jul-2026 17:55:04 9654
SXDL31_DWAV_150800 15-Jul-2026 08:31:31 14528
SXDL31_DWAV_LATEST 15-Jul-2026 08:31:31 14528
SXDL33_DWAV_140000 14-Jul-2026 10:16:40 11362
SXDL33_DWAV_150000 15-Jul-2026 09:28:39 11922
SXDL33_DWAV_LATEST 15-Jul-2026 09:28:39 11922
ber01-FWDL39_DWMS_141200-2607141200-dsw--0-ia5 14-Jul-2026 10:32:45 1859
ber01-FWDL39_DWMS_151200-2607151200-dsw--0-ia5 15-Jul-2026 10:38:55 1524
ber01-VHDL13_DWEG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3722
ber01-VHDL13_DWEG_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:15 3902
ber01-VHDL13_DWEG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 3236
ber01-VHDL13_DWEH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3377
ber01-VHDL13_DWEH_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:31 3348
ber01-VHDL13_DWEH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 2661
ber01-VHDL13_DWEI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3591
ber01-VHDL13_DWEI_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:51 3828
ber01-VHDL13_DWEI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 3063
ber01-VHDL13_DWHG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:07 3334
ber01-VHDL13_DWHG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3461
ber01-VHDL13_DWHH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:07 3122
ber01-VHDL13_DWHH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3314
ber01-VHDL13_DWLG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3120
ber01-VHDL13_DWLG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3127
ber01-VHDL13_DWLH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3329
ber01-VHDL13_DWLH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 2764
ber01-VHDL13_DWLI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2934
ber01-VHDL13_DWLI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 2705
ber01-VHDL13_DWMO_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 3434
ber01-VHDL13_DWMO_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3150
ber01-VHDL13_DWMP_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 3542
ber01-VHDL13_DWMP_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3214
ber01-VHDL13_DWOG_131700-2607131700-dsw--0-ia5 13-Jul-2026 18:00:02 4468
ber01-VHDL13_DWOG_140300-2607140300-dsw--0-ia5 14-Jul-2026 03:00:02 4072
ber01-VHDL13_DWOG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 4211
ber01-VHDL13_DWOG_141700-2607141700-dsw--0-ia5 14-Jul-2026 18:00:02 4792
ber01-VHDL13_DWOG_150300-2607150300-dsw--0-ia5 15-Jul-2026 03:00:03 4058
ber01-VHDL13_DWOG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 4119
ber01-VHDL13_DWON_131742-2607131742-dsw--0-ia5 13-Jul-2026 17:43:04 3845
ber01-VHDL13_DWON_132022-2607132022-dsw--0-ia5 13-Jul-2026 20:22:46 3687
ber01-VHDL13_DWON_140015-2607140015-dsw--0-ia5 14-Jul-2026 00:15:36 3484
ber01-VHDL13_DWON_140253-2607140253-dsw--0-ia5 14-Jul-2026 02:53:29 3484
ber01-VHDL13_DWON_140513-2607140513-dsw--0-ia5 14-Jul-2026 05:13:16 3835
ber01-VHDL13_DWON_140604-2607140604-dsw--0-ia5 14-Jul-2026 06:04:52 3784
ber01-VHDL13_DWON_140816-2607140816-dsw--0-ia5 14-Jul-2026 08:16:22 3811
ber01-VHDL13_DWON_140910-2607140910-dsw--0-ia5 14-Jul-2026 09:10:42 3811
ber01-VHDL13_DWON_141502-2607141502-dsw--0-ia5 14-Jul-2026 15:02:22 3653
ber01-VHDL13_DWON_142248-2607142248-dsw--0-ia5 14-Jul-2026 22:48:16 3711
ber01-VHDL13_DWON_150058-2607150058-dsw--0-ia5 15-Jul-2026 00:58:12 3711
ber01-VHDL13_DWON_150239-2607150239-dsw--0-ia5 15-Jul-2026 02:40:00 3711
ber01-VHDL13_DWON_150529-2607150529-dsw--0-ia5 15-Jul-2026 05:30:02 3958
ber01-VHDL13_DWON_150604-2607150604-dsw--0-ia5 15-Jul-2026 06:04:46 3946
ber01-VHDL13_DWON_151443-2607151443-dsw--0-ia5 15-Jul-2026 14:43:17 3903
ber01-VHDL13_DWON_151447-2607151447-dsw--0-ia5 15-Jul-2026 14:48:40 3900
ber01-VHDL13_DWPG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3603
ber01-VHDL13_DWPG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3230
ber01-VHDL13_DWPH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2656
ber01-VHDL13_DWPH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3930
ber01-VHDL13_DWSG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3713
ber01-VHDL13_DWSG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 4069
ber01-VHDL17_DWOG_141200-2607141200-dsw--0-ia5 14-Jul-2026 11:30:42 2704
ber01-VHDL17_DWOG_151200-2607151200-dsw--0-ia5 15-Jul-2026 11:22:41 2858
swis2-VHDL20_DWEG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2340
swis2-VHDL20_DWEG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1982
swis2-VHDL20_DWEG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1725
swis2-VHDL20_DWEG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2189
swis2-VHDL20_DWEG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2669
swis2-VHDL20_DWEG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1193
swis2-VHDL20_DWEG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 1449
swis2-VHDL20_DWEG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1820
swis2-VHDL20_DWEH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2374
swis2-VHDL20_DWEH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1976
swis2-VHDL20_DWEH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1924
swis2-VHDL20_DWEH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 1943
swis2-VHDL20_DWEH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2318
swis2-VHDL20_DWEH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 953
swis2-VHDL20_DWEH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 949
swis2-VHDL20_DWEH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1377
swis2-VHDL20_DWEI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2366
swis2-VHDL20_DWEI_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1784
swis2-VHDL20_DWEI_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1991
swis2-VHDL20_DWEI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2209
swis2-VHDL20_DWEI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2633
swis2-VHDL20_DWEI_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1334
swis2-VHDL20_DWEI_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 1434
swis2-VHDL20_DWEI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1805
swis2-VHDL20_DWHG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1680
swis2-VHDL20_DWHG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:45:34 1558
swis2-VHDL20_DWHG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1559
swis2-VHDL20_DWHG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:45:14 1610
swis2-VHDL20_DWHG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1616
swis2-VHDL20_DWHG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:45:01 1188
swis2-VHDL20_DWHG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1406
swis2-VHDL20_DWHG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:45:32 1706
swis2-VHDL20_DWHH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1612
swis2-VHDL20_DWHH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:45:34 1336
swis2-VHDL20_DWHH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1343
swis2-VHDL20_DWHH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:45:14 1474
swis2-VHDL20_DWHH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1301
swis2-VHDL20_DWHH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:45:01 1042
swis2-VHDL20_DWHH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1319
swis2-VHDL20_DWHH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:45:32 1586
swis2-VHDL20_DWLG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1508
swis2-VHDL20_DWLG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1519
swis2-VHDL20_DWLG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1365
swis2-VHDL20_DWLG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1484
swis2-VHDL20_DWLG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1667
swis2-VHDL20_DWLG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1694
swis2-VHDL20_DWLG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1049
swis2-VHDL20_DWLG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1583
swis2-VHDL20_DWLH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2032
swis2-VHDL20_DWLH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1973
swis2-VHDL20_DWLH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1533
swis2-VHDL20_DWLH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1697
swis2-VHDL20_DWLH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1469
swis2-VHDL20_DWLH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1043
swis2-VHDL20_DWLH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1020
swis2-VHDL20_DWLH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1347
swis2-VHDL20_DWLI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1680
swis2-VHDL20_DWLI_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1536
swis2-VHDL20_DWLI_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1373
swis2-VHDL20_DWLI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1484
swis2-VHDL20_DWLI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1388
swis2-VHDL20_DWLI_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 875
swis2-VHDL20_DWLI_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1057
swis2-VHDL20_DWLI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1384
swis2-VHDL20_DWMO_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1836
swis2-VHDL20_DWMO_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 2018
swis2-VHDL20_DWMO_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:01 1547
swis2-VHDL20_DWMO_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 1875
swis2-VHDL20_DWMO_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1857
swis2-VHDL20_DWMO_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1390
swis2-VHDL20_DWMO_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:02 1390
swis2-VHDL20_DWMO_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1622
swis2-VHDL20_DWMP_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1966
swis2-VHDL20_DWMP_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1727
swis2-VHDL20_DWMP_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:01 1606
swis2-VHDL20_DWMP_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 1933
swis2-VHDL20_DWMP_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1697
swis2-VHDL20_DWMP_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1404
swis2-VHDL20_DWMP_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:02 1417
swis2-VHDL20_DWMP_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1626
swis2-VHDL20_DWPG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2012
swis2-VHDL20_DWPG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1591
swis2-VHDL20_DWPG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1668
swis2-VHDL20_DWPG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1818
swis2-VHDL20_DWPG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1569
swis2-VHDL20_DWPG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1272
swis2-VHDL20_DWPG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1442
swis2-VHDL20_DWPG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1720
swis2-VHDL20_DWPH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1501
swis2-VHDL20_DWPH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1209
swis2-VHDL20_DWPH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1184
swis2-VHDL20_DWPH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1440
swis2-VHDL20_DWPH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1642
swis2-VHDL20_DWPH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1416
swis2-VHDL20_DWPH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1590
swis2-VHDL20_DWPH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 2185
swis2-VHDL20_DWSG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2014
swis2-VHDL20_DWSG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1932
swis2-VHDL20_DWSG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1680
swis2-VHDL20_DWSG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2123
swis2-VHDL20_DWSG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2273
swis2-VHDL20_DWSG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1596
swis2-VHDL20_DWSG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1590
swis2-VHDL20_DWSG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 2230
wst04-VHDL20_DWEG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 250466
wst04-VHDL20_DWEG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 249549
wst04-VHDL20_DWEG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 249413
wst04-VHDL20_DWEG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 250338
wst04-VHDL20_DWEG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 243699
wst04-VHDL20_DWEG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 241737
wst04-VHDL20_DWEG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 241949
wst04-VHDL20_DWEG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:12 242977
wst04-VHDL20_DWEH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 245588
wst04-VHDL20_DWEH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 245626
wst04-VHDL20_DWEH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 245594
wst04-VHDL20_DWEH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 246272
wst04-VHDL20_DWEH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 238368
wst04-VHDL20_DWEH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 236141
wst04-VHDL20_DWEH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 236266
wst04-VHDL20_DWEH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:12 237354
wst04-VHDL20_DWEI_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 359237
wst04-VHDL20_DWEI_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 358667
wst04-VHDL20_DWEI_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 358853
wst04-VHDL20_DWEI_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 359106
wst04-VHDL20_DWEI_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 351459
wst04-VHDL20_DWEI_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:17 349457
wst04-VHDL20_DWEI_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 349609
wst04-VHDL20_DWEI_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:16 350733
wst04-VHDL20_DWHG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:45:11 350556
wst04-VHDL20_DWHG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:45:34 350522
wst04-VHDL20_DWHG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:17 350500
wst04-VHDL20_DWHG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:45:14 351236
wst04-VHDL20_DWHG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:45:11 344865
wst04-VHDL20_DWHG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:45:42 343689
wst04-VHDL20_DWHG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 343492
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wst04-VHDL20_DWHH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:45:42 331256
wst04-VHDL20_DWHH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 225518
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wst04-VHDL20_DWLG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 342401
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wst04-VHDL20_DWLH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:45 349742
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wst04-VHDL20_DWLH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:29 344781
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wst04-VHDL20_DWLI_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 346036
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wst04-VHDL20_DWMO_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 464205
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wst04-VHDL20_DWMO_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 471421
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wst04-VHDL20_DWMP_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:17 590785
wst04-VHDL20_DWMP_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 590927
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wst04-VHDL20_DWPG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 246600
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wst04-VHDL20_DWPG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 244586
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wst04-VHDL20_DWPH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 249188
wst04-VHDL20_DWPH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:31 249250
wst04-VHDL20_DWPH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:41 249533
wst04-VHDL20_DWPH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 247426
wst04-VHDL20_DWPH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 246902
wst04-VHDL20_DWPH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:32 247190
wst04-VHDL20_DWPH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:44 247809
wst04-VHDL20_DWSG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 355294
wst04-VHDL20_DWSG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 356357
wst04-VHDL20_DWSG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 355099
wst04-VHDL20_DWSG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:22 355486
wst04-VHDL20_DWSG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 361799
wst04-VHDL20_DWSG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 361133
wst04-VHDL20_DWSG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 360276
wst04-VHDL20_DWSG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:16 361304