Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Oct-2026 13:17:38 4019
FPDL13_DWMZ_150600 15-Oct-2026 13:59:28 4684
SXDL31_DWAV_131800 13-Oct-2026 18:30:31 5408
SXDL31_DWAV_140800 14-Oct-2026 07:16:15 9177
SXDL31_DWAV_141800 14-Oct-2026 16:42:54 5533
SXDL31_DWAV_150800 15-Oct-2026 07:34:24 8933
SXDL31_DWAV_LATEST 15-Oct-2026 07:34:24 8933
SXDL33_DWAV_140000 14-Oct-2026 11:24:10 7868
SXDL33_DWAV_150000 15-Oct-2026 09:43:48 8272
SXDL33_DWAV_LATEST 15-Oct-2026 09:43:48 8272
ber01-FWDL39_DWMS_141200-2610141200-dsw--0-ia5 14-Oct-2026 11:32:47 1357
ber01-FWDL39_DWMS_151200-2610151200-dsw--0-ia5 15-Oct-2026 11:23:28 1710
ber01-VHDL13_DWEG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2499
ber01-VHDL13_DWEG_140800_COR-2610140800-dsw--0-ia5 15-Oct-2026 04:58:00 2746
ber01-VHDL13_DWEG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 2767
ber01-VHDL13_DWEH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2471
ber01-VHDL13_DWEH_140800_COR-2610140800-dsw--0-ia5 15-Oct-2026 04:58:09 2988
ber01-VHDL13_DWEH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 2992
ber01-VHDL13_DWEI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2545
ber01-VHDL13_DWEI_140800_COR-2610140800-dsw--0-ia5 15-Oct-2026 04:58:23 2828
ber01-VHDL13_DWEI_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 2849
ber01-VHDL13_DWHG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 3153
ber01-VHDL13_DWHG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 3122
ber01-VHDL13_DWHH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 3162
ber01-VHDL13_DWHH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 3103
ber01-VHDL13_DWLG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2457
ber01-VHDL13_DWLG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2461
ber01-VHDL13_DWLH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2701
ber01-VHDL13_DWLH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2620
ber01-VHDL13_DWLI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2485
ber01-VHDL13_DWLI_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2600
ber01-VHDL13_DWMO_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3026
ber01-VHDL13_DWMO_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 3187
ber01-VHDL13_DWMP_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3348
ber01-VHDL13_DWMP_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 3335
ber01-VHDL13_DWOG_131700-2610131700-dsw--0-ia5 13-Oct-2026 18:00:05 4054
ber01-VHDL13_DWOG_140300-2610140300-dsw--0-ia5 14-Oct-2026 03:02:09 4189
ber01-VHDL13_DWOG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 4168
ber01-VHDL13_DWOG_141700-2610141700-dsw--0-ia5 14-Oct-2026 18:00:10 3294
ber01-VHDL13_DWOG_150300-2610150300-dsw--0-ia5 15-Oct-2026 03:00:25 3516
ber01-VHDL13_DWOG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 3529
ber01-VHDL13_DWON_131441-2610131441-dsw--0-ia5 13-Oct-2026 14:41:38 4171
ber01-VHDL13_DWON_131733-2610131733-dsw--0-ia5 13-Oct-2026 17:33:59 3482
ber01-VHDL13_DWON_131842-2610131842-dsw--0-ia5 13-Oct-2026 18:42:35 3722
ber01-VHDL13_DWON_132045-2610132045-dsw--0-ia5 13-Oct-2026 20:45:28 3437
ber01-VHDL13_DWON_132134-2610132134-dsw--0-ia5 13-Oct-2026 21:34:48 3440
ber01-VHDL13_DWON_140006-2610140006-dsw--0-ia5 14-Oct-2026 00:06:14 4255
ber01-VHDL13_DWON_140144-2610140144-dsw--0-ia5 14-Oct-2026 01:44:14 4231
ber01-VHDL13_DWON_140248-2610140248-dsw--0-ia5 14-Oct-2026 02:50:19 4231
ber01-VHDL13_DWON_140353-2610140353-dsw--0-ia5 14-Oct-2026 03:53:45 4231
ber01-VHDL13_DWON_140527-2610140527-dsw--0-ia5 14-Oct-2026 05:28:04 4427
ber01-VHDL13_DWON_140611-2610140611-dsw--0-ia5 14-Oct-2026 06:11:48 4421
ber01-VHDL13_DWON_140835-2610140835-dsw--0-ia5 14-Oct-2026 08:35:54 4366
ber01-VHDL13_DWON_141451-2610141451-dsw--0-ia5 14-Oct-2026 14:54:14 3841
ber01-VHDL13_DWON_141659-2610141659-dsw--0-ia5 14-Oct-2026 16:59:31 3514
ber01-VHDL13_DWON_150104-2610150104-dsw--0-ia5 15-Oct-2026 01:04:13 3556
ber01-VHDL13_DWON_150240-2610150240-dsw--0-ia5 15-Oct-2026 02:40:50 3556
ber01-VHDL13_DWON_150528-2610150528-dsw--0-ia5 15-Oct-2026 05:28:54 3849
ber01-VHDL13_DWON_150629-2610150629-dsw--0-ia5 15-Oct-2026 06:29:53 3849
ber01-VHDL13_DWON_150750-2610150750-dsw--0-ia5 15-Oct-2026 07:50:18 3761
ber01-VHDL13_DWON_150820-2610150820-dsw--0-ia5 15-Oct-2026 08:20:18 3761
ber01-VHDL13_DWPG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2997
ber01-VHDL13_DWPG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2510
ber01-VHDL13_DWPH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3493
ber01-VHDL13_DWPH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2840
ber01-VHDL13_DWSG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2792
ber01-VHDL13_DWSG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 2931
ber01-VHDL17_DWOG_141200-2610141200-dsw--0-ia5 14-Oct-2026 11:33:24 2979
ber01-VHDL17_DWOG_151200-2610151200-dsw--0-ia5 15-Oct-2026 11:14:35 2876
swis2-VHDL20_DWEG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 917
swis2-VHDL20_DWEG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 830
swis2-VHDL20_DWEG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 830
swis2-VHDL20_DWEG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1211
swis2-VHDL20_DWEG_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:05 1178
swis2-VHDL20_DWEG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:13 1202
swis2-VHDL20_DWEG_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 878
swis2-VHDL20_DWEG_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:01:23 917
swis2-VHDL20_DWEG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 1465
swis2-VHDL20_DWEH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 1021
swis2-VHDL20_DWEH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 857
swis2-VHDL20_DWEH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 857
swis2-VHDL20_DWEH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1040
swis2-VHDL20_DWEH_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:39:54 1177
swis2-VHDL20_DWEH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:14 1216
swis2-VHDL20_DWEH_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 880
swis2-VHDL20_DWEH_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:01:23 929
swis2-VHDL20_DWEH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 1491
swis2-VHDL20_DWEI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 939
swis2-VHDL20_DWEI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 852
swis2-VHDL20_DWEI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 852
swis2-VHDL20_DWEI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1233
swis2-VHDL20_DWEI_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:05 1203
swis2-VHDL20_DWEI_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:13 1224
swis2-VHDL20_DWEI_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 900
swis2-VHDL20_DWEI_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:01:23 939
swis2-VHDL20_DWEI_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 1543
swis2-VHDL20_DWHG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 1808
swis2-VHDL20_DWHG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1360
swis2-VHDL20_DWHG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1357
swis2-VHDL20_DWHG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1233
swis2-VHDL20_DWHG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:45:23 1320
swis2-VHDL20_DWHG_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:49:13 1174
swis2-VHDL20_DWHG_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:19 1082
swis2-VHDL20_DWHG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 1474
swis2-VHDL20_DWHH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 2027
swis2-VHDL20_DWHH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1505
swis2-VHDL20_DWHH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1505
swis2-VHDL20_DWHH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1273
swis2-VHDL20_DWHH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:45:23 1106
swis2-VHDL20_DWHH_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:49:13 1045
swis2-VHDL20_DWHH_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:19 1045
swis2-VHDL20_DWHH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 1457
swis2-VHDL20_DWLG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 827
swis2-VHDL20_DWLG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 860
swis2-VHDL20_DWLG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 866
swis2-VHDL20_DWLG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 960
swis2-VHDL20_DWLG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 891
swis2-VHDL20_DWLG_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:42 1020
swis2-VHDL20_DWLG_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:13 875
swis2-VHDL20_DWLG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:29 1398
swis2-VHDL20_DWLH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 991
swis2-VHDL20_DWLH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1020
swis2-VHDL20_DWLH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1003
swis2-VHDL20_DWLH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 973
swis2-VHDL20_DWLH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 899
swis2-VHDL20_DWLH_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:42 862
swis2-VHDL20_DWLH_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:13 875
swis2-VHDL20_DWLH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:29 1415
swis2-VHDL20_DWLI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 898
swis2-VHDL20_DWLI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 843
swis2-VHDL20_DWLI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 849
swis2-VHDL20_DWLI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 927
swis2-VHDL20_DWLI_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 858
swis2-VHDL20_DWLI_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:42 852
swis2-VHDL20_DWLI_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:13 877
swis2-VHDL20_DWLI_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:29 1373
swis2-VHDL20_DWMO_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1322
swis2-VHDL20_DWMO_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1113
swis2-VHDL20_DWMO_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1301
swis2-VHDL20_DWMO_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1222
swis2-VHDL20_DWMO_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1408
swis2-VHDL20_DWMO_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 1160
swis2-VHDL20_DWMO_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:09 1189
swis2-VHDL20_DWMO_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 1714
swis2-VHDL20_DWMP_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1250
swis2-VHDL20_DWMP_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1173
swis2-VHDL20_DWMP_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1260
swis2-VHDL20_DWMP_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1578
swis2-VHDL20_DWMP_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1465
swis2-VHDL20_DWMP_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 1183
swis2-VHDL20_DWMP_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:09 1211
swis2-VHDL20_DWMP_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:11 1755
swis2-VHDL20_DWPG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1081
swis2-VHDL20_DWPG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1010
swis2-VHDL20_DWPG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1016
swis2-VHDL20_DWPG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 1290
swis2-VHDL20_DWPG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 931
swis2-VHDL20_DWPG_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:42 1034
swis2-VHDL20_DWPG_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:13 896
swis2-VHDL20_DWPG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:29 1407
swis2-VHDL20_DWPH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1265
swis2-VHDL20_DWPH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1130
swis2-VHDL20_DWPH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1148
swis2-VHDL20_DWPH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 1554
swis2-VHDL20_DWPH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 951
swis2-VHDL20_DWPH_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:42 990
swis2-VHDL20_DWPH_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:13 926
swis2-VHDL20_DWPH_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:29 1452
swis2-VHDL20_DWSG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:08 1333
swis2-VHDL20_DWSG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1019
swis2-VHDL20_DWSG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1149
swis2-VHDL20_DWSG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1315
swis2-VHDL20_DWSG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1145
swis2-VHDL20_DWSG_150200-2610150200-dsw--0-ia5 15-Oct-2026 02:30:06 1078
swis2-VHDL20_DWSG_150400-2610150400-dsw--0-ia5 15-Oct-2026 05:00:19 1103
swis2-VHDL20_DWSG_150800-2610150800-dsw--0-ia5 15-Oct-2026 08:30:04 1467
swis2-VHDL20_DWSG_150800_COR-2610150800-dsw--0-ia5 15-Oct-2026 08:43:33 1551
wst04-VHDL20_DWEG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 236727
wst04-VHDL20_DWEG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:20 236005
wst04-VHDL20_DWEG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 236037
wst04-VHDL20_DWEG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 237059
wst04-VHDL20_DWEG_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 239249
wst04-VHDL20_DWEG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 239318
wst04-VHDL20_DWEG_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:20 237729
wst04-VHDL20_DWEG_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:13 237734
wst04-VHDL20_DWEG_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:25 240434
wst04-VHDL20_DWEH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 237578
wst04-VHDL20_DWEH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 237030
wst04-VHDL20_DWEH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:14 237380
wst04-VHDL20_DWEH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 238284
wst04-VHDL20_DWEH_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 237422
wst04-VHDL20_DWEH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 236870
wst04-VHDL20_DWEH_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:20 235580
wst04-VHDL20_DWEH_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:13 235840
wst04-VHDL20_DWEH_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:25 238207
wst04-VHDL20_DWEI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 336757
wst04-VHDL20_DWEI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 336627
wst04-VHDL20_DWEI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 336618
wst04-VHDL20_DWEI_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 337135
wst04-VHDL20_DWEI_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 344168
wst04-VHDL20_DWEI_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 344173
wst04-VHDL20_DWEI_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 343140
wst04-VHDL20_DWEI_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:13 343146
wst04-VHDL20_DWEI_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:25 346198
wst04-VHDL20_DWHG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 340801
wst04-VHDL20_DWHG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 339169
wst04-VHDL20_DWHG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 339183
wst04-VHDL20_DWHG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:38 339319
wst04-VHDL20_DWHG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:45:23 332325
wst04-VHDL20_DWHG_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:49:13 331628
wst04-VHDL20_DWHG_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:19 331331
wst04-VHDL20_DWHG_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:41 333980
wst04-VHDL20_DWHH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 318801
wst04-VHDL20_DWHH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 317440
wst04-VHDL20_DWHH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 221673
wst04-VHDL20_DWHH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 316094
wst04-VHDL20_DWHH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:45:23 312667
wst04-VHDL20_DWHH_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:49:13 312519
wst04-VHDL20_DWHH_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:19 219865
wst04-VHDL20_DWHH_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:41 314306
wst04-VHDL20_DWLG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 328240
wst04-VHDL20_DWLG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 328457
wst04-VHDL20_DWLG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 327802
wst04-VHDL20_DWLG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 327442
wst04-VHDL20_DWLG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 321824
wst04-VHDL20_DWLG_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 322528
wst04-VHDL20_DWLG_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:43 321043
wst04-VHDL20_DWLG_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:49 323478
wst04-VHDL20_DWLH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324791
wst04-VHDL20_DWLH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325285
wst04-VHDL20_DWLH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324645
wst04-VHDL20_DWLH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 323821
wst04-VHDL20_DWLH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:31 324731
wst04-VHDL20_DWLH_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 324873
wst04-VHDL20_DWLH_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:43 323969
wst04-VHDL20_DWLH_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:51 326556
wst04-VHDL20_DWLI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324643
wst04-VHDL20_DWLI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325286
wst04-VHDL20_DWLI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324608
wst04-VHDL20_DWLI_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 368835
wst04-VHDL20_DWLI_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 322676
wst04-VHDL20_DWLI_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 322833
wst04-VHDL20_DWLI_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:43 321922
wst04-VHDL20_DWLI_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:49 368764
wst04-VHDL20_DWMO_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:20 343284
wst04-VHDL20_DWMO_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 446202
wst04-VHDL20_DWMO_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 445428
wst04-VHDL20_DWMO_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 445688
wst04-VHDL20_DWMO_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 342865
wst04-VHDL20_DWMO_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:20 441283
wst04-VHDL20_DWMO_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:19 441128
wst04-VHDL20_DWMO_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:25 441909
wst04-VHDL20_DWMP_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 444927
wst04-VHDL20_DWMP_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:18 542884
wst04-VHDL20_DWMP_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 542024
wst04-VHDL20_DWMP_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 445336
wst04-VHDL20_DWMP_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 461370
wst04-VHDL20_DWMP_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:20 561733
wst04-VHDL20_DWMP_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:19 561671
wst04-VHDL20_DWMP_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:34 563378
wst04-VHDL20_DWPG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 334118
wst04-VHDL20_DWPG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 236974
wst04-VHDL20_DWPG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 333994
wst04-VHDL20_DWPG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 378926
wst04-VHDL20_DWPG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:31 333139
wst04-VHDL20_DWPG_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 237503
wst04-VHDL20_DWPG_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:33 332091
wst04-VHDL20_DWPG_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:51 378809
wst04-VHDL20_DWPH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 239153
wst04-VHDL20_DWPH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 238906
wst04-VHDL20_DWPH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 238997
wst04-VHDL20_DWPH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 239078
wst04-VHDL20_DWPH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 230069
wst04-VHDL20_DWPH_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:42 230231
wst04-VHDL20_DWPH_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:33 229657
wst04-VHDL20_DWPH_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:49 230968
wst04-VHDL20_DWSG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:12 333812
wst04-VHDL20_DWSG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 333590
wst04-VHDL20_DWSG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 333909
wst04-VHDL20_DWSG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 334741
wst04-VHDL20_DWSG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:20 343140
wst04-VHDL20_DWSG_150200-2610150200-omedes--0.pdf 15-Oct-2026 02:30:20 343250
wst04-VHDL20_DWSG_150400-2610150400-omedes--0.pdf 15-Oct-2026 05:00:13 343011
wst04-VHDL20_DWSG_150800-2610150800-omedes--0.pdf 15-Oct-2026 08:30:11 344136
wst04-VHDL20_DWSG_150800_COR-2610150800-omedes-..> 15-Oct-2026 08:41:19 344312