Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Aug-2026 11:47:04 3663
FPDL13_DWMZ_160600 16-Aug-2026 12:13:05 2919
SXDL31_DWAV_141800 14-Aug-2026 17:34:28 8122
SXDL31_DWAV_150800 15-Aug-2026 07:42:21 8267
SXDL31_DWAV_151800 15-Aug-2026 17:22:00 5750
SXDL31_DWAV_160800 16-Aug-2026 08:29:35 8701
SXDL31_DWAV_161800 16-Aug-2026 16:47:36 8712
SXDL31_DWAV_LATEST 16-Aug-2026 16:47:36 8712
SXDL33_DWAV_150000 15-Aug-2026 09:42:41 10767
SXDL33_DWAV_160000 16-Aug-2026 09:47:53 15407
SXDL33_DWAV_LATEST 16-Aug-2026 09:47:53 15407
ber01-FWDL39_DWMS_151200-2608151200-dsw--0-ia5 15-Aug-2026 11:37:32 1128
ber01-FWDL39_DWMS_161200-2608161200-dsw--0-ia5 16-Aug-2026 12:20:08 1390
ber01-VHDL13_DWEG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:18 3934
ber01-VHDL13_DWEG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 3375
ber01-VHDL13_DWEH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:18 3728
ber01-VHDL13_DWEH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 2440
ber01-VHDL13_DWEI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:28:14 3752
ber01-VHDL13_DWEI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:28:18 3318
ber01-VHDL13_DWHG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 4133
ber01-VHDL13_DWHG_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:37:52 4124
ber01-VHDL13_DWHG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2995
ber01-VHDL13_DWHH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3211
ber01-VHDL13_DWHH_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:38:04 3215
ber01-VHDL13_DWHH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3022
ber01-VHDL13_DWLG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3139
ber01-VHDL13_DWLG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3088
ber01-VHDL13_DWLH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3309
ber01-VHDL13_DWLH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2818
ber01-VHDL13_DWLI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3602
ber01-VHDL13_DWLI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2777
ber01-VHDL13_DWMO_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3501
ber01-VHDL13_DWMO_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3654
ber01-VHDL13_DWMP_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3467
ber01-VHDL13_DWMP_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3691
ber01-VHDL13_DWOG_141700-2608141700-dsw--0-ia5 14-Aug-2026 18:00:08 3511
ber01-VHDL13_DWOG_150300-2608150300-dsw--0-ia5 15-Aug-2026 03:00:09 4126
ber01-VHDL13_DWOG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 4183
ber01-VHDL13_DWOG_151700-2608151700-dsw--0-ia5 15-Aug-2026 18:00:06 3818
ber01-VHDL13_DWOG_160300-2608160300-dsw--0-ia5 16-Aug-2026 03:00:10 3602
ber01-VHDL13_DWOG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 4010
ber01-VHDL13_DWON_141746-2608141746-dsw--0-ia5 14-Aug-2026 17:46:28 3427
ber01-VHDL13_DWON_141940-2608141940-dsw--0-ia5 14-Aug-2026 19:40:25 3384
ber01-VHDL13_DWON_150135-2608150135-dsw--0-ia5 15-Aug-2026 01:35:11 3376
ber01-VHDL13_DWON_150147-2608150147-dsw--0-ia5 15-Aug-2026 01:47:20 3376
ber01-VHDL13_DWON_150347-2608150347-dsw--0-ia5 15-Aug-2026 03:47:08 3376
ber01-VHDL13_DWON_150508-2608150508-dsw--0-ia5 15-Aug-2026 05:08:34 3677
ber01-VHDL13_DWON_150607-2608150607-dsw--0-ia5 15-Aug-2026 06:07:54 3677
ber01-VHDL13_DWON_150821-2608150821-dsw--0-ia5 15-Aug-2026 08:21:14 3677
ber01-VHDL13_DWON_151438-2608151438-dsw--0-ia5 15-Aug-2026 14:38:59 3039
ber01-VHDL13_DWON_151739-2608151739-dsw--0-ia5 15-Aug-2026 17:40:00 2919
ber01-VHDL13_DWON_152156-2608152156-dsw--0-ia5 15-Aug-2026 21:56:34 2924
ber01-VHDL13_DWON_160129-2608160129-dsw--0-ia5 16-Aug-2026 01:29:18 2828
ber01-VHDL13_DWON_160134-2608160134-dsw--0-ia5 16-Aug-2026 01:35:14 3001
ber01-VHDL13_DWON_160152-2608160152-dsw--0-ia5 16-Aug-2026 01:52:54 3001
ber01-VHDL13_DWON_160531-2608160531-dsw--0-ia5 16-Aug-2026 05:31:25 3415
ber01-VHDL13_DWON_160628-2608160628-dsw--0-ia5 16-Aug-2026 06:28:54 3689
ber01-VHDL13_DWON_160635-2608160635-dsw--0-ia5 16-Aug-2026 06:35:23 3691
ber01-VHDL13_DWON_160912-2608160912-dsw--0-ia5 16-Aug-2026 09:12:17 3466
ber01-VHDL13_DWON_161153-2608161153-dsw--0-ia5 16-Aug-2026 11:53:08 3420
ber01-VHDL13_DWON_161434-2608161434-dsw--0-ia5 16-Aug-2026 14:34:22 3793
ber01-VHDL13_DWON_161438-2608161438-dsw--0-ia5 16-Aug-2026 14:38:50 3774
ber01-VHDL13_DWPG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3467
ber01-VHDL13_DWPG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2913
ber01-VHDL13_DWPH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 3030
ber01-VHDL13_DWPH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2417
ber01-VHDL13_DWSG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 3556
ber01-VHDL13_DWSG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 3573
ber01-VHDL17_DWOG_151200-2608151200-dsw--0-ia5 15-Aug-2026 11:02:58 2605
ber01-VHDL17_DWOG_161200-2608161200-dsw--0-ia5 16-Aug-2026 10:59:58 2999
swis2-VHDL20_DWEG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2123
swis2-VHDL20_DWEG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1930
swis2-VHDL20_DWEG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1946
swis2-VHDL20_DWEG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 2039
swis2-VHDL20_DWEG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 2072
swis2-VHDL20_DWEG_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1742
swis2-VHDL20_DWEG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 1599
swis2-VHDL20_DWEG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 1364
swis2-VHDL20_DWEG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1652
swis2-VHDL20_DWEH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2033
swis2-VHDL20_DWEH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1653
swis2-VHDL20_DWEH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1701
swis2-VHDL20_DWEH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 1819
swis2-VHDL20_DWEH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1858
swis2-VHDL20_DWEH_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1289
swis2-VHDL20_DWEH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 873
swis2-VHDL20_DWEH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 865
swis2-VHDL20_DWEH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1014
swis2-VHDL20_DWEI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 2081
swis2-VHDL20_DWEI_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1894
swis2-VHDL20_DWEI_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:01:23 1913
swis2-VHDL20_DWEI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:12 2031
swis2-VHDL20_DWEI_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 2056
swis2-VHDL20_DWEI_151800_COR-2608151800-dsw--0-ia5 15-Aug-2026 18:36:30 1744
swis2-VHDL20_DWEI_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:09 1612
swis2-VHDL20_DWEI_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:01:18 1391
swis2-VHDL20_DWEI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1686
swis2-VHDL20_DWHG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 2144
swis2-VHDL20_DWHG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:47:07 2066
swis2-VHDL20_DWHG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 2051
swis2-VHDL20_DWHG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:45:45 2236
swis2-VHDL20_DWHG_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:38:51 2240
swis2-VHDL20_DWHG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:45:11 1444
swis2-VHDL20_DWHG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:45:47 1294
swis2-VHDL20_DWHG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 971
swis2-VHDL20_DWHG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:45:36 1250
swis2-VHDL20_DWHH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:45:10 1658
swis2-VHDL20_DWHH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:47:07 1463
swis2-VHDL20_DWHH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 1449
swis2-VHDL20_DWHH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:45:45 1727
swis2-VHDL20_DWHH_150800_COR-2608150800-dsw--0-ia5 15-Aug-2026 08:39:32 1731
swis2-VHDL20_DWHH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:45:11 1376
swis2-VHDL20_DWHH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:45:47 1340
swis2-VHDL20_DWHH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1230
swis2-VHDL20_DWHH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:45:36 1546
swis2-VHDL20_DWLG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1345
swis2-VHDL20_DWLG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1589
swis2-VHDL20_DWLG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1495
swis2-VHDL20_DWLG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1588
swis2-VHDL20_DWLG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1416
swis2-VHDL20_DWLG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1527
swis2-VHDL20_DWLG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1615
swis2-VHDL20_DWLG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1414
swis2-VHDL20_DWLH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1249
swis2-VHDL20_DWLH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1551
swis2-VHDL20_DWLH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1522
swis2-VHDL20_DWLH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1593
swis2-VHDL20_DWLH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1407
swis2-VHDL20_DWLH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1373
swis2-VHDL20_DWLH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1485
swis2-VHDL20_DWLH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1242
swis2-VHDL20_DWLI_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1405
swis2-VHDL20_DWLI_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1742
swis2-VHDL20_DWLI_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1723
swis2-VHDL20_DWLI_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1814
swis2-VHDL20_DWLI_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1427
swis2-VHDL20_DWLI_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1479
swis2-VHDL20_DWLI_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1503
swis2-VHDL20_DWLI_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1204
swis2-VHDL20_DWMO_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1691
swis2-VHDL20_DWMO_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1609
swis2-VHDL20_DWMO_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:08 1632
swis2-VHDL20_DWMO_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1844
swis2-VHDL20_DWMO_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1731
swis2-VHDL20_DWMO_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1672
swis2-VHDL20_DWMO_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:08 1700
swis2-VHDL20_DWMO_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1767
swis2-VHDL20_DWMP_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:12 1739
swis2-VHDL20_DWMP_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1675
swis2-VHDL20_DWMP_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:08 1697
swis2-VHDL20_DWMP_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1818
swis2-VHDL20_DWMP_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1719
swis2-VHDL20_DWMP_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1597
swis2-VHDL20_DWMP_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:08 1579
swis2-VHDL20_DWMP_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 2006
swis2-VHDL20_DWPG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1254
swis2-VHDL20_DWPG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1505
swis2-VHDL20_DWPG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1580
swis2-VHDL20_DWPG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1667
swis2-VHDL20_DWPG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 1345
swis2-VHDL20_DWPG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 1458
swis2-VHDL20_DWPG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 1222
swis2-VHDL20_DWPG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 1243
swis2-VHDL20_DWPH_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:31:05 1012
swis2-VHDL20_DWPH_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:34 1256
swis2-VHDL20_DWPH_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:14 1262
swis2-VHDL20_DWPH_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:24 1366
swis2-VHDL20_DWPH_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:31:09 959
swis2-VHDL20_DWPH_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:33 884
swis2-VHDL20_DWPH_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:14 873
swis2-VHDL20_DWPH_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:26 913
swis2-VHDL20_DWSG_141800-2608141800-dsw--0-ia5 14-Aug-2026 18:30:07 1692
swis2-VHDL20_DWSG_141800_COR-2608141800-dsw--0-ia5 14-Aug-2026 18:33:52 1603
swis2-VHDL20_DWSG_150200-2608150200-dsw--0-ia5 15-Aug-2026 02:30:18 1501
swis2-VHDL20_DWSG_150400-2608150400-dsw--0-ia5 15-Aug-2026 05:00:18 1499
swis2-VHDL20_DWSG_150800-2608150800-dsw--0-ia5 15-Aug-2026 08:30:10 1712
swis2-VHDL20_DWSG_151800-2608151800-dsw--0-ia5 15-Aug-2026 18:30:08 1771
swis2-VHDL20_DWSG_160200-2608160200-dsw--0-ia5 16-Aug-2026 02:30:04 1595
swis2-VHDL20_DWSG_160400-2608160400-dsw--0-ia5 16-Aug-2026 05:00:18 1570
swis2-VHDL20_DWSG_160800-2608160800-dsw--0-ia5 16-Aug-2026 08:30:10 1724
wst04-VHDL20_DWEG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 246884
wst04-VHDL20_DWEG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 245951
wst04-VHDL20_DWEG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 245925
wst04-VHDL20_DWEG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:12 246735
wst04-VHDL20_DWEG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 243201
wst04-VHDL20_DWEG_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 242911
wst04-VHDL20_DWEG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 242039
wst04-VHDL20_DWEG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 241262
wst04-VHDL20_DWEG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:10 242505
wst04-VHDL20_DWEH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 244007
wst04-VHDL20_DWEH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 243238
wst04-VHDL20_DWEH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 243481
wst04-VHDL20_DWEH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:12 244284
wst04-VHDL20_DWEH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 242463
wst04-VHDL20_DWEH_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 241165
wst04-VHDL20_DWEH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 239377
wst04-VHDL20_DWEH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:14 239432
wst04-VHDL20_DWEH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:10 240628
wst04-VHDL20_DWEI_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:30:24 354251
wst04-VHDL20_DWEI_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 353874
wst04-VHDL20_DWEI_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:14 353849
wst04-VHDL20_DWEI_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:18 354115
wst04-VHDL20_DWEI_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 350082
wst04-VHDL20_DWEI_151800_COR-2608151800-omedes-..> 15-Aug-2026 18:36:45 349875
wst04-VHDL20_DWEI_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:31 349152
wst04-VHDL20_DWEI_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:18 348079
wst04-VHDL20_DWEI_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:23 349490
wst04-VHDL20_DWHG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:45:21 342679
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wst04-VHDL20_DWHG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:45:45 343437
wst04-VHDL20_DWHG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:45:21 350781
wst04-VHDL20_DWHG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:45:47 350358
wst04-VHDL20_DWHG_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:20 349244
wst04-VHDL20_DWHG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:45:36 351744
wst04-VHDL20_DWHH_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:45:21 334647
wst04-VHDL20_DWHH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:47:07 334506
wst04-VHDL20_DWHH_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 232685
wst04-VHDL20_DWHH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:45:45 335912
wst04-VHDL20_DWHH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:45:21 335431
wst04-VHDL20_DWHH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:45:47 335482
wst04-VHDL20_DWHH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:20 231304
wst04-VHDL20_DWHH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:45:36 336417
wst04-VHDL20_DWLG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:31:24 342772
wst04-VHDL20_DWLG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 343836
wst04-VHDL20_DWLG_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:44 343308
wst04-VHDL20_DWLG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 344272
wst04-VHDL20_DWLG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 339393
wst04-VHDL20_DWLG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 339547
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wst04-VHDL20_DWLH_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:44 350870
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wst04-VHDL20_DWLH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 347878
wst04-VHDL20_DWLH_160400-2608160400-omedes--0.pdf 16-Aug-2026 05:00:44 347565
wst04-VHDL20_DWLH_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:54 347160
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wst04-VHDL20_DWLI_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 341103
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wst04-VHDL20_DWMO_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 459776
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wst04-VHDL20_DWMP_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 580939
wst04-VHDL20_DWMP_150400-2608150400-omedes--0.pdf 15-Aug-2026 05:00:18 581284
wst04-VHDL20_DWMP_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:24 472434
wst04-VHDL20_DWMP_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 471257
wst04-VHDL20_DWMP_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:31 578336
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wst04-VHDL20_DWPG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 244242
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wst04-VHDL20_DWPH_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:34 242307
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wst04-VHDL20_DWPH_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:31:27 283561
wst04-VHDL20_DWPH_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:33 239696
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wst04-VHDL20_DWSG_141800-2608141800-omedes--0.pdf 14-Aug-2026 18:33:54 355200
wst04-VHDL20_DWSG_150200-2608150200-omedes--0.pdf 15-Aug-2026 02:30:32 355223
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wst04-VHDL20_DWSG_150800-2608150800-omedes--0.pdf 15-Aug-2026 08:30:18 356040
wst04-VHDL20_DWSG_151800-2608151800-omedes--0.pdf 15-Aug-2026 18:30:19 353821
wst04-VHDL20_DWSG_160200-2608160200-omedes--0.pdf 16-Aug-2026 02:30:13 353103
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wst04-VHDL20_DWSG_160800-2608160800-omedes--0.pdf 16-Aug-2026 08:30:23 353550