Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Jul-2026 13:33:17 5380
FPDL13_DWMZ_250600 25-Jul-2026 12:28:54 3089
SXDL31_DWAV_241800 24-Jul-2026 15:50:44 10063
SXDL31_DWAV_250800 25-Jul-2026 07:12:30 15367
SXDL31_DWAV_251800 25-Jul-2026 16:59:39 7451
SXDL31_DWAV_260800 26-Jul-2026 07:41:47 9246
SXDL31_DWAV_LATEST 26-Jul-2026 07:41:47 9246
SXDL33_DWAV_240000 24-Jul-2026 09:46:55 8795
SXDL33_DWAV_250000 25-Jul-2026 10:40:57 8090
SXDL33_DWAV_LATEST 25-Jul-2026 10:40:57 8090
ber01-FWDL39_DWMS_241200-2607241200-dsw--0-ia5 24-Jul-2026 11:57:01 2068
ber01-FWDL39_DWMS_251200-2607251200-dsw--0-ia5 25-Jul-2026 10:03:17 1593
ber01-VHDL13_DWEG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:17 2715
ber01-VHDL13_DWEG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:12 2825
ber01-VHDL13_DWEH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:11 2665
ber01-VHDL13_DWEH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:18 3239
ber01-VHDL13_DWEI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:28:11 2677
ber01-VHDL13_DWEI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:28:18 2672
ber01-VHDL13_DWHG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 4066
ber01-VHDL13_DWHG_250800_COR-2607250800-dsw--0-ia5 25-Jul-2026 08:51:15 4070
ber01-VHDL13_DWHG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3883
ber01-VHDL13_DWHH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 4207
ber01-VHDL13_DWHH_250800_COR-2607250800-dsw--0-ia5 25-Jul-2026 08:51:45 4211
ber01-VHDL13_DWHH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3752
ber01-VHDL13_DWLG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2024
ber01-VHDL13_DWLG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2508
ber01-VHDL13_DWLH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2297
ber01-VHDL13_DWLH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2931
ber01-VHDL13_DWLI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2025
ber01-VHDL13_DWLI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2418
ber01-VHDL13_DWMO_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 2818
ber01-VHDL13_DWMO_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2788
ber01-VHDL13_DWMP_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3207
ber01-VHDL13_DWMP_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3278
ber01-VHDL13_DWOG_241700-2607241700-dsw--0-ia5 24-Jul-2026 18:00:00 3284
ber01-VHDL13_DWOG_250300-2607250300-dsw--0-ia5 25-Jul-2026 03:00:12 3263
ber01-VHDL13_DWOG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3371
ber01-VHDL13_DWOG_251700-2607251700-dsw--0-ia5 25-Jul-2026 18:00:00 3933
ber01-VHDL13_DWOG_260300-2607260300-dsw--0-ia5 26-Jul-2026 03:00:12 3937
ber01-VHDL13_DWOG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 4068
ber01-VHDL13_DWON_241437-2607241437-dsw--0-ia5 24-Jul-2026 14:38:05 3478
ber01-VHDL13_DWON_241628-2607241628-dsw--0-ia5 24-Jul-2026 16:28:51 3290
ber01-VHDL13_DWON_241631-2607241631-dsw--0-ia5 24-Jul-2026 16:32:10 3226
ber01-VHDL13_DWON_250129-2607250129-dsw--0-ia5 25-Jul-2026 01:29:56 3657
ber01-VHDL13_DWON_250147-2607250147-dsw--0-ia5 25-Jul-2026 01:47:32 3186
ber01-VHDL13_DWON_250343-2607250343-dsw--0-ia5 25-Jul-2026 03:43:26 3186
ber01-VHDL13_DWON_250524-2607250524-dsw--0-ia5 25-Jul-2026 05:25:02 3520
ber01-VHDL13_DWON_250629-2607250629-dsw--0-ia5 25-Jul-2026 06:29:31 3607
ber01-VHDL13_DWON_250709-2607250709-dsw--0-ia5 25-Jul-2026 07:09:32 3657
ber01-VHDL13_DWON_251145-2607251145-dsw--0-ia5 25-Jul-2026 11:45:10 3658
ber01-VHDL13_DWON_251451-2607251451-dsw--0-ia5 25-Jul-2026 14:51:13 3821
ber01-VHDL13_DWON_251732-2607251732-dsw--0-ia5 25-Jul-2026 17:33:00 3331
ber01-VHDL13_DWON_260258-2607260258-dsw--0-ia5 26-Jul-2026 03:00:12 3657
ber01-VHDL13_DWON_260517-2607260517-dsw--0-ia5 26-Jul-2026 05:17:47 3560
ber01-VHDL13_DWON_260615-2607260615-dsw--0-ia5 26-Jul-2026 06:15:17 3435
ber01-VHDL13_DWON_260748-2607260748-dsw--0-ia5 26-Jul-2026 07:48:31 3558
ber01-VHDL13_DWPG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3006
ber01-VHDL13_DWPG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2884
ber01-VHDL13_DWPH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3262
ber01-VHDL13_DWPH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 3152
ber01-VHDL13_DWSG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 3507
ber01-VHDL13_DWSG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 2748
ber01-VHDL17_DWOG_241200-2607241200-dsw--0-ia5 24-Jul-2026 10:50:42 3901
ber01-VHDL17_DWOG_251200-2607251200-dsw--0-ia5 25-Jul-2026 11:32:05 3024
swis2-VHDL20_DWEG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1132
swis2-VHDL20_DWEG_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1043
swis2-VHDL20_DWEG_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:01:21 1111
swis2-VHDL20_DWEG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1218
swis2-VHDL20_DWEG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1285
swis2-VHDL20_DWEG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1036
swis2-VHDL20_DWEG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1231
swis2-VHDL20_DWEG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1404
swis2-VHDL20_DWEH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1165
swis2-VHDL20_DWEH_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1032
swis2-VHDL20_DWEH_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:01:21 1100
swis2-VHDL20_DWEH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1202
swis2-VHDL20_DWEH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1259
swis2-VHDL20_DWEH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1083
swis2-VHDL20_DWEH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1478
swis2-VHDL20_DWEH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1742
swis2-VHDL20_DWEI_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1163
swis2-VHDL20_DWEI_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1078
swis2-VHDL20_DWEI_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:01:21 1146
swis2-VHDL20_DWEI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1254
swis2-VHDL20_DWEI_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:04 1328
swis2-VHDL20_DWEI_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1004
swis2-VHDL20_DWEI_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:01:17 1188
swis2-VHDL20_DWEI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1361
swis2-VHDL20_DWHG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:45:04 1400
swis2-VHDL20_DWHG_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:45:49 1266
swis2-VHDL20_DWHG_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:17 1254
swis2-VHDL20_DWHG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:45:13 2247
swis2-VHDL20_DWHG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:45:07 2000
swis2-VHDL20_DWHG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:45:49 1933
swis2-VHDL20_DWHG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1879
swis2-VHDL20_DWHG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:45:07 2015
swis2-VHDL20_DWHH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:45:04 1419
swis2-VHDL20_DWHH_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:45:49 1523
swis2-VHDL20_DWHH_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:17 1516
swis2-VHDL20_DWHH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:45:13 2233
swis2-VHDL20_DWHH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:45:07 2162
swis2-VHDL20_DWHH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:45:49 1860
swis2-VHDL20_DWHH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1792
swis2-VHDL20_DWHH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:45:07 2141
swis2-VHDL20_DWLG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1120
swis2-VHDL20_DWLG_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:25 818
swis2-VHDL20_DWLG_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:11 921
swis2-VHDL20_DWLG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1118
swis2-VHDL20_DWLG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1446
swis2-VHDL20_DWLG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1283
swis2-VHDL20_DWLG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1317
swis2-VHDL20_DWLG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1517
swis2-VHDL20_DWLH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1490
swis2-VHDL20_DWLH_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:25 1098
swis2-VHDL20_DWLH_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:11 1036
swis2-VHDL20_DWLH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1160
swis2-VHDL20_DWLH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1311
swis2-VHDL20_DWLH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1452
swis2-VHDL20_DWLH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1587
swis2-VHDL20_DWLH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1685
swis2-VHDL20_DWLI_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1051
swis2-VHDL20_DWLI_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:25 822
swis2-VHDL20_DWLI_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:11 921
swis2-VHDL20_DWLI_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1042
swis2-VHDL20_DWLI_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1314
swis2-VHDL20_DWLI_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1432
swis2-VHDL20_DWLI_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1353
swis2-VHDL20_DWLI_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1448
swis2-VHDL20_DWMO_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1499
swis2-VHDL20_DWMO_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1382
swis2-VHDL20_DWMO_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:07 1394
swis2-VHDL20_DWMO_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1345
swis2-VHDL20_DWMO_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:15 1641
swis2-VHDL20_DWMO_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1450
swis2-VHDL20_DWMO_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:02 1466
swis2-VHDL20_DWMO_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1367
swis2-VHDL20_DWMP_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:11 1586
swis2-VHDL20_DWMP_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1490
swis2-VHDL20_DWMP_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:07 1512
swis2-VHDL20_DWMP_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1609
swis2-VHDL20_DWMP_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:15 1812
swis2-VHDL20_DWMP_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1607
swis2-VHDL20_DWMP_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:02 1623
swis2-VHDL20_DWMP_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1720
swis2-VHDL20_DWPG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1296
swis2-VHDL20_DWPG_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:25 1016
swis2-VHDL20_DWPG_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:11 975
swis2-VHDL20_DWPG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1442
swis2-VHDL20_DWPG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1451
swis2-VHDL20_DWPG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1452
swis2-VHDL20_DWPG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1501
swis2-VHDL20_DWPG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1596
swis2-VHDL20_DWPH_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:31:01 1411
swis2-VHDL20_DWPH_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:25 1022
swis2-VHDL20_DWPH_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:11 979
swis2-VHDL20_DWPH_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:26 1603
swis2-VHDL20_DWPH_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:31:10 1582
swis2-VHDL20_DWPH_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:31 1596
swis2-VHDL20_DWPH_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:12 1652
swis2-VHDL20_DWPH_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:25 1746
swis2-VHDL20_DWSG_241800-2607241800-dsw--0-ia5 24-Jul-2026 18:30:03 1659
swis2-VHDL20_DWSG_250200-2607250200-dsw--0-ia5 25-Jul-2026 02:30:05 1568
swis2-VHDL20_DWSG_250400-2607250400-dsw--0-ia5 25-Jul-2026 05:00:17 1610
swis2-VHDL20_DWSG_250400_COR-2607250400-dsw--0-ia5 25-Jul-2026 05:07:01 1612
swis2-VHDL20_DWSG_250800-2607250800-dsw--0-ia5 25-Jul-2026 08:30:12 1693
swis2-VHDL20_DWSG_251800-2607251800-dsw--0-ia5 25-Jul-2026 18:30:03 1720
swis2-VHDL20_DWSG_260200-2607260200-dsw--0-ia5 26-Jul-2026 02:30:11 1505
swis2-VHDL20_DWSG_260400-2607260400-dsw--0-ia5 26-Jul-2026 05:00:17 1502
swis2-VHDL20_DWSG_260400_COR-2607260400-dsw--0-ia5 26-Jul-2026 05:00:37 1549
swis2-VHDL20_DWSG_260800-2607260800-dsw--0-ia5 26-Jul-2026 08:30:16 1385
wst04-VHDL20_DWEG_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:21 239456
wst04-VHDL20_DWEG_250200-2607250200-omedes--0.pdf 25-Jul-2026 02:30:15 239020
wst04-VHDL20_DWEG_250400-2607250400-omedes--0.pdf 25-Jul-2026 05:00:11 238324
wst04-VHDL20_DWEG_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:12 239027
wst04-VHDL20_DWEG_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 238933
wst04-VHDL20_DWEG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 237427
wst04-VHDL20_DWEG_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 237188
wst04-VHDL20_DWEG_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 237991
wst04-VHDL20_DWEH_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:21 238485
wst04-VHDL20_DWEH_250200-2607250200-omedes--0.pdf 25-Jul-2026 02:30:15 238331
wst04-VHDL20_DWEH_250400-2607250400-omedes--0.pdf 25-Jul-2026 05:00:11 237934
wst04-VHDL20_DWEH_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:12 238734
wst04-VHDL20_DWEH_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 241019
wst04-VHDL20_DWEH_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 240113
wst04-VHDL20_DWEH_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 240188
wst04-VHDL20_DWEH_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 241111
wst04-VHDL20_DWEI_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:30:11 341316
wst04-VHDL20_DWEI_250200-2607250200-omedes--0.pdf 25-Jul-2026 02:30:15 341435
wst04-VHDL20_DWEI_250400-2607250400-omedes--0.pdf 25-Jul-2026 05:00:11 340661
wst04-VHDL20_DWEI_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:30:18 340884
wst04-VHDL20_DWEI_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:30:15 340346
wst04-VHDL20_DWEI_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:31 339362
wst04-VHDL20_DWEI_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:12 339053
wst04-VHDL20_DWEI_260800-2607260800-omedes--0.pdf 26-Jul-2026 08:30:16 339389
wst04-VHDL20_DWHG_241800-2607241800-omedes--0.pdf 24-Jul-2026 18:45:12 346876
wst04-VHDL20_DWHG_250200-2607250200-omedes--0.pdf 25-Jul-2026 02:45:49 346461
wst04-VHDL20_DWHG_250400-2607250400-omedes--0.pdf 25-Jul-2026 05:00:17 346237
wst04-VHDL20_DWHG_250800-2607250800-omedes--0.pdf 25-Jul-2026 08:45:13 350027
wst04-VHDL20_DWHG_251800-2607251800-omedes--0.pdf 25-Jul-2026 18:45:17 352710
wst04-VHDL20_DWHG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:45:49 352424
wst04-VHDL20_DWHG_260400-2607260400-omedes--0.pdf 26-Jul-2026 05:00:17 351521
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wst04-VHDL20_DWSG_260200-2607260200-omedes--0.pdf 26-Jul-2026 02:30:11 341904
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