Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Oct-2026 15:49:45 6496
FPDL13_DWMZ_280600 28-Oct-2026 11:35:14 6523
SXDL31_DWAV_270800 27-Oct-2026 08:11:20 12439
SXDL31_DWAV_271800 27-Oct-2026 16:56:24 6613
SXDL31_DWAV_280800 28-Oct-2026 08:27:39 6446
SXDL31_DWAV_281800 28-Oct-2026 16:32:45 7125
SXDL31_DWAV_LATEST 28-Oct-2026 16:32:45 7125
SXDL33_DWAV_270000 27-Oct-2026 10:53:07 4905
SXDL33_DWAV_280000 28-Oct-2026 09:37:46 5842
SXDL33_DWAV_LATEST 28-Oct-2026 09:37:46 5842
ber01-FWDL39_DWMS_271200-2610271200-dsw--0-ia5 27-Oct-2026 11:38:24 1622
ber01-FWDL39_DWMS_281200-2610281200-dsw--0-ia5 28-Oct-2026 12:18:59 1586
ber01-VHDL13_DWEG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:20 2823
ber01-VHDL13_DWEG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2864
ber01-VHDL13_DWEH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:20 2998
ber01-VHDL13_DWEH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2566
ber01-VHDL13_DWEI_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:20 2873
ber01-VHDL13_DWEI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:19 2596
ber01-VHDL13_DWHG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 3550
ber01-VHDL13_DWHG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 2961
ber01-VHDL13_DWHH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 3612
ber01-VHDL13_DWHH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 2880
ber01-VHDL13_DWLG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 2342
ber01-VHDL13_DWLG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2838
ber01-VHDL13_DWLH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:05 2458
ber01-VHDL13_DWLH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2960
ber01-VHDL13_DWLI_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 2336
ber01-VHDL13_DWLI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2866
ber01-VHDL13_DWMO_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 2974
ber01-VHDL13_DWMO_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2934
ber01-VHDL13_DWMP_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 3191
ber01-VHDL13_DWMP_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3259
ber01-VHDL13_DWOG_270300-2610270300-dsw--0-ia5 27-Oct-2026 04:00:07 3379
ber01-VHDL13_DWOG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 3788
ber01-VHDL13_DWOG_271700-2610271700-dsw--0-ia5 27-Oct-2026 19:00:06 3457
ber01-VHDL13_DWOG_280300-2610280300-dsw--0-ia5 28-Oct-2026 04:00:09 3613
ber01-VHDL13_DWOG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3420
ber01-VHDL13_DWOG_281700-2610281700-dsw--0-ia5 28-Oct-2026 19:00:24 2842
ber01-VHDL13_DWON_270205-2610270205-dsw--0-ia5 27-Oct-2026 02:05:58 3117
ber01-VHDL13_DWON_270342-2610270342-dsw--0-ia5 27-Oct-2026 03:42:22 3138
ber01-VHDL13_DWON_270523-2610270523-dsw--0-ia5 27-Oct-2026 05:23:48 3138
ber01-VHDL13_DWON_270623-2610270623-dsw--0-ia5 27-Oct-2026 06:23:59 3633
ber01-VHDL13_DWON_270920-2610270920-dsw--0-ia5 27-Oct-2026 09:20:43 3633
ber01-VHDL13_DWON_271514-2610271514-dsw--0-ia5 27-Oct-2026 15:15:17 3278
ber01-VHDL13_DWON_271755-2610271755-dsw--0-ia5 27-Oct-2026 17:55:44 3200
ber01-VHDL13_DWON_280209-2610280209-dsw--0-ia5 28-Oct-2026 02:10:10 3166
ber01-VHDL13_DWON_280345-2610280345-dsw--0-ia5 28-Oct-2026 03:45:53 3166
ber01-VHDL13_DWON_280620-2610280620-dsw--0-ia5 28-Oct-2026 06:20:44 3671
ber01-VHDL13_DWON_280651-2610280651-dsw--0-ia5 28-Oct-2026 06:51:32 3638
ber01-VHDL13_DWON_280928-2610280928-dsw--0-ia5 28-Oct-2026 09:28:59 3638
ber01-VHDL13_DWON_281549-2610281549-dsw--0-ia5 28-Oct-2026 15:49:32 3258
ber01-VHDL13_DWON_281619-2610281619-dsw--0-ia5 28-Oct-2026 16:19:34 2882
ber01-VHDL13_DWON_281802-2610281802-dsw--0-ia5 28-Oct-2026 18:02:23 2882
ber01-VHDL13_DWPG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 2219
ber01-VHDL13_DWPG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3061
ber01-VHDL13_DWPH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 2341
ber01-VHDL13_DWPH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 2571
ber01-VHDL13_DWSG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 3382
ber01-VHDL13_DWSG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 3463
ber01-VHDL17_DWOG_271200-2610271200-dsw--0-ia5 27-Oct-2026 12:31:06 2881
ber01-VHDL17_DWOG_281200-2610281200-dsw--0-ia5 28-Oct-2026 12:11:28 2654
swis2-VHDL20_DWEG_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:11 1201
swis2-VHDL20_DWEG_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:01:00 1251
swis2-VHDL20_DWEG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 1633
swis2-VHDL20_DWEG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1343
swis2-VHDL20_DWEG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1133
swis2-VHDL20_DWEG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1150
swis2-VHDL20_DWEG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1420
swis2-VHDL20_DWEG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1116
swis2-VHDL20_DWEH_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:11 1108
swis2-VHDL20_DWEH_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:01:00 1451
swis2-VHDL20_DWEH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 1762
swis2-VHDL20_DWEH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1380
swis2-VHDL20_DWEH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1081
swis2-VHDL20_DWEH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1012
swis2-VHDL20_DWEH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1298
swis2-VHDL20_DWEH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1065
swis2-VHDL20_DWEI_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:11 1239
swis2-VHDL20_DWEI_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:01:00 1311
swis2-VHDL20_DWEI_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:03 1691
swis2-VHDL20_DWEI_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1352
swis2-VHDL20_DWEI_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:11 1151
swis2-VHDL20_DWEI_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:01:03 1153
swis2-VHDL20_DWEI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1436
swis2-VHDL20_DWEI_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1161
swis2-VHDL20_DWHG_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 1503
swis2-VHDL20_DWHG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 1937
swis2-VHDL20_DWHG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:45:11 1796
swis2-VHDL20_DWHG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1330
swis2-VHDL20_DWHG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1712
swis2-VHDL20_DWHG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:45:22 1396
swis2-VHDL20_DWHH_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:45:11 1624
swis2-VHDL20_DWHH_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 1624
swis2-VHDL20_DWHH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 1994
swis2-VHDL20_DWHH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:45:11 1795
swis2-VHDL20_DWHH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:45:10 1455
swis2-VHDL20_DWHH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:19 1311
swis2-VHDL20_DWHH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:09 1628
swis2-VHDL20_DWHH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:45:22 1468
swis2-VHDL20_DWLG_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:36 812
swis2-VHDL20_DWLG_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 959
swis2-VHDL20_DWLG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:38 1197
swis2-VHDL20_DWLG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1092
swis2-VHDL20_DWLG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 887
swis2-VHDL20_DWLG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1220
swis2-VHDL20_DWLG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1465
swis2-VHDL20_DWLG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 993
swis2-VHDL20_DWLH_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:36 890
swis2-VHDL20_DWLH_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 1037
swis2-VHDL20_DWLH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:38 1279
swis2-VHDL20_DWLH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1094
swis2-VHDL20_DWLH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 896
swis2-VHDL20_DWLH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1215
swis2-VHDL20_DWLH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1467
swis2-VHDL20_DWLH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 985
swis2-VHDL20_DWLI_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:36 811
swis2-VHDL20_DWLI_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 958
swis2-VHDL20_DWLI_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:38 1195
swis2-VHDL20_DWLI_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1091
swis2-VHDL20_DWLI_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 1011
swis2-VHDL20_DWLI_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1184
swis2-VHDL20_DWLI_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1431
swis2-VHDL20_DWLI_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 998
swis2-VHDL20_DWMO_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:11 1502
swis2-VHDL20_DWMO_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:10 1477
swis2-VHDL20_DWMO_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 1740
swis2-VHDL20_DWMO_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1501
swis2-VHDL20_DWMO_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1416
swis2-VHDL20_DWMO_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:05 1414
swis2-VHDL20_DWMO_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1769
swis2-VHDL20_DWMO_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:05 1386
swis2-VHDL20_DWMP_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:11 1499
swis2-VHDL20_DWMP_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:10 1482
swis2-VHDL20_DWMP_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 1785
swis2-VHDL20_DWMP_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:05 1482
swis2-VHDL20_DWMP_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1456
swis2-VHDL20_DWMP_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:05 1474
swis2-VHDL20_DWMP_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1843
swis2-VHDL20_DWMP_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:05 1428
swis2-VHDL20_DWPG_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:36 833
swis2-VHDL20_DWPG_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 980
swis2-VHDL20_DWPG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:38 1226
swis2-VHDL20_DWPG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1077
swis2-VHDL20_DWPG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 908
swis2-VHDL20_DWPG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 1223
swis2-VHDL20_DWPG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1479
swis2-VHDL20_DWPG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 1002
swis2-VHDL20_DWPH_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:36 840
swis2-VHDL20_DWPH_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 987
swis2-VHDL20_DWPH_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:38 1240
swis2-VHDL20_DWPH_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:31:07 1084
swis2-VHDL20_DWPH_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:36 910
swis2-VHDL20_DWPH_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:13 991
swis2-VHDL20_DWPH_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:38 1251
swis2-VHDL20_DWPH_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:31:06 1007
swis2-VHDL20_DWSG_270200-2610270200-dsw--0-ia5 27-Oct-2026 03:30:03 1297
swis2-VHDL20_DWSG_270400-2610270400-dsw--0-ia5 27-Oct-2026 06:00:15 1436
swis2-VHDL20_DWSG_270800-2610270800-dsw--0-ia5 27-Oct-2026 09:30:09 1958
swis2-VHDL20_DWSG_271800-2610271800-dsw--0-ia5 27-Oct-2026 19:30:09 1851
swis2-VHDL20_DWSG_280200-2610280200-dsw--0-ia5 28-Oct-2026 03:30:04 1450
swis2-VHDL20_DWSG_280400-2610280400-dsw--0-ia5 28-Oct-2026 06:00:19 1455
swis2-VHDL20_DWSG_280800-2610280800-dsw--0-ia5 28-Oct-2026 09:30:03 1862
swis2-VHDL20_DWSG_281800-2610281800-dsw--0-ia5 28-Oct-2026 19:30:07 1568
wst04-VHDL20_DWEG_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:19 234299
wst04-VHDL20_DWEG_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:15 233402
wst04-VHDL20_DWEG_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:20 234633
wst04-VHDL20_DWEG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 235355
wst04-VHDL20_DWEG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 235686
wst04-VHDL20_DWEG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 234965
wst04-VHDL20_DWEG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:30 234951
wst04-VHDL20_DWEG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 233926
wst04-VHDL20_DWEH_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:17 234899
wst04-VHDL20_DWEH_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:15 234263
wst04-VHDL20_DWEH_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:20 235056
wst04-VHDL20_DWEH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 227845
wst04-VHDL20_DWEH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 228221
wst04-VHDL20_DWEH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 226994
wst04-VHDL20_DWEH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:19 231526
wst04-VHDL20_DWEH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 231491
wst04-VHDL20_DWEI_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:19 329674
wst04-VHDL20_DWEI_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:15 329224
wst04-VHDL20_DWEI_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:20 330058
wst04-VHDL20_DWEI_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 328661
wst04-VHDL20_DWEI_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:28 328500
wst04-VHDL20_DWEI_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 328236
wst04-VHDL20_DWEI_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:38 334042
wst04-VHDL20_DWEI_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 332794
wst04-VHDL20_DWHG_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:45:13 329076
wst04-VHDL20_DWHG_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:19 328878
wst04-VHDL20_DWHG_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:38 331706
wst04-VHDL20_DWHG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:45:21 319278
wst04-VHDL20_DWHG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:45:14 317868
wst04-VHDL20_DWHG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 316853
wst04-VHDL20_DWHG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:38 322187
wst04-VHDL20_DWHG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:45:35 319735
wst04-VHDL20_DWHH_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:45:13 320054
wst04-VHDL20_DWHH_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:19 221935
wst04-VHDL20_DWHH_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:38 321538
wst04-VHDL20_DWHH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:45:21 314374
wst04-VHDL20_DWHH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:45:14 313114
wst04-VHDL20_DWHH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 219440
wst04-VHDL20_DWHH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:38 310041
wst04-VHDL20_DWHH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:45:35 309701
wst04-VHDL20_DWLG_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:36 325590
wst04-VHDL20_DWLG_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:43 325993
wst04-VHDL20_DWLG_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:49 327323
wst04-VHDL20_DWLG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 322502
wst04-VHDL20_DWLG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 322026
wst04-VHDL20_DWLG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:41 322225
wst04-VHDL20_DWLG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 319951
wst04-VHDL20_DWLG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 318459
wst04-VHDL20_DWLH_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:36 317480
wst04-VHDL20_DWLH_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:43 318342
wst04-VHDL20_DWLH_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:49 319671
wst04-VHDL20_DWLH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 314029
wst04-VHDL20_DWLH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 313585
wst04-VHDL20_DWLH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:41 314015
wst04-VHDL20_DWLH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 316196
wst04-VHDL20_DWLH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 314519
wst04-VHDL20_DWLI_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:36 323680
wst04-VHDL20_DWLI_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:43 324057
wst04-VHDL20_DWLI_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:49 369943
wst04-VHDL20_DWLI_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 322142
wst04-VHDL20_DWLI_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 321900
wst04-VHDL20_DWLI_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:41 321865
wst04-VHDL20_DWLI_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 362779
wst04-VHDL20_DWLI_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:34 316762
wst04-VHDL20_DWMO_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:17 443765
wst04-VHDL20_DWMO_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:19 444749
wst04-VHDL20_DWMO_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:38 444797
wst04-VHDL20_DWMO_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 438219
wst04-VHDL20_DWMO_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 438536
wst04-VHDL20_DWMO_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 439625
wst04-VHDL20_DWMO_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:13 446736
wst04-VHDL20_DWMO_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:20 445618
wst04-VHDL20_DWMP_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:19 547795
wst04-VHDL20_DWMP_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:19 547792
wst04-VHDL20_DWMP_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:38 549739
wst04-VHDL20_DWMP_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:22 540456
wst04-VHDL20_DWMP_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 540329
wst04-VHDL20_DWMP_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:19 541188
wst04-VHDL20_DWMP_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:19 543852
wst04-VHDL20_DWMP_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:34 541922
wst04-VHDL20_DWPG_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:36 234624
wst04-VHDL20_DWPG_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:33 330301
wst04-VHDL20_DWPG_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:49 376136
wst04-VHDL20_DWPG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:37 325252
wst04-VHDL20_DWPG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 230971
wst04-VHDL20_DWPG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:33 325089
wst04-VHDL20_DWPG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:31:00 374410
wst04-VHDL20_DWPG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:34 328388
wst04-VHDL20_DWPH_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:36 232708
wst04-VHDL20_DWPH_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:33 233164
wst04-VHDL20_DWPH_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:49 233646
wst04-VHDL20_DWPH_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:31:23 227603
wst04-VHDL20_DWPH_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:36 227187
wst04-VHDL20_DWPH_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:33 227179
wst04-VHDL20_DWPH_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:42 234524
wst04-VHDL20_DWPH_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:31:23 234156
wst04-VHDL20_DWSG_270200-2610270200-omedes--0.pdf 27-Oct-2026 03:30:19 332133
wst04-VHDL20_DWSG_270400-2610270400-omedes--0.pdf 27-Oct-2026 06:00:15 332119
wst04-VHDL20_DWSG_270800-2610270800-omedes--0.pdf 27-Oct-2026 09:30:38 332370
wst04-VHDL20_DWSG_271800-2610271800-omedes--0.pdf 27-Oct-2026 19:30:20 327276
wst04-VHDL20_DWSG_280200-2610280200-omedes--0.pdf 28-Oct-2026 03:30:19 325602
wst04-VHDL20_DWSG_280400-2610280400-omedes--0.pdf 28-Oct-2026 06:00:13 325357
wst04-VHDL20_DWSG_280800-2610280800-omedes--0.pdf 28-Oct-2026 09:30:13 332292
wst04-VHDL20_DWSG_281800-2610281800-omedes--0.pdf 28-Oct-2026 19:30:18 336755