Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_080600 08-Jan-2026 14:19:25 3817
FPDL13_DWMZ_090600 09-Jan-2026 14:30:58 3250
SXDL31_DWAV_080800 08-Jan-2026 09:15:12 10469
SXDL31_DWAV_081800 08-Jan-2026 18:39:35 7359
SXDL31_DWAV_090800 09-Jan-2026 09:00:36 13548
SXDL31_DWAV_091800 09-Jan-2026 18:00:19 9642
SXDL31_DWAV_LATEST 09-Jan-2026 18:00:19 9642
SXDL33_DWAV_080000 08-Jan-2026 11:13:20 12412
SXDL33_DWAV_090000 09-Jan-2026 11:52:05 10948
SXDL33_DWAV_LATEST 09-Jan-2026 11:52:05 10948
ber01-FWDL39_DWMS_081230-2601081230-dsw--0-ia5 08-Jan-2026 12:49:42 2513
ber01-FWDL39_DWMS_091230-2601091230-dsw--0-ia5 09-Jan-2026 13:00:52 1386
ber01-VHDL13_DWEH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:28:11 4855
ber01-VHDL13_DWEH_080400-2601080400-dsw--0-ia5 08-Jan-2026 05:58:17 5684
ber01-VHDL13_DWEH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:28:18 5852
ber01-VHDL13_DWEH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:15 5453
ber01-VHDL13_DWEH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:11 5318
ber01-VHDL13_DWEH_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:16 4872
ber01-VHDL13_DWEH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:16 5120
ber01-VHDL13_DWEH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:18 3745
ber01-VHDL13_DWHG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:06 5539
ber01-VHDL13_DWHG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 5549
ber01-VHDL13_DWHG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:07 5549
ber01-VHDL13_DWHG_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 09:50:22 5082
ber01-VHDL13_DWHG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 4937
ber01-VHDL13_DWHG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4980
ber01-VHDL13_DWHG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4748
ber01-VHDL13_DWHG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4577
ber01-VHDL13_DWHG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 4395
ber01-VHDL13_DWHH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:06 5237
ber01-VHDL13_DWHH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 5237
ber01-VHDL13_DWHH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:07 5237
ber01-VHDL13_DWHH_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 09:53:11 5241
ber01-VHDL13_DWHH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 4513
ber01-VHDL13_DWHH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 3993
ber01-VHDL13_DWHH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4015
ber01-VHDL13_DWHH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3860
ber01-VHDL13_DWHH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 4470
ber01-VHDL13_DWLG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 3067
ber01-VHDL13_DWLG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:01 3217
ber01-VHDL13_DWLG_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:18:01 3230
ber01-VHDL13_DWLG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 3298
ber01-VHDL13_DWLG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3083
ber01-VHDL13_DWLG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 3422
ber01-VHDL13_DWLG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3451
ber01-VHDL13_DWLG_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:36:06 3714
ber01-VHDL13_DWLG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4315
ber01-VHDL13_DWLG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2910
ber01-VHDL13_DWLH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 3331
ber01-VHDL13_DWLH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:01 3467
ber01-VHDL13_DWLH_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:17:37 3513
ber01-VHDL13_DWLH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 3375
ber01-VHDL13_DWLH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3091
ber01-VHDL13_DWLH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2902
ber01-VHDL13_DWLH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3271
ber01-VHDL13_DWLH_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:33:52 3523
ber01-VHDL13_DWLH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4005
ber01-VHDL13_DWLH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2654
ber01-VHDL13_DWLI_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 3274
ber01-VHDL13_DWLI_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:01 3448
ber01-VHDL13_DWLI_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:18:27 3459
ber01-VHDL13_DWLI_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 3513
ber01-VHDL13_DWLI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3108
ber01-VHDL13_DWLI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2948
ber01-VHDL13_DWLI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3124
ber01-VHDL13_DWLI_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:35:15 3412
ber01-VHDL13_DWLI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3592
ber01-VHDL13_DWLI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2748
ber01-VHDL13_DWMG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:06 4197
ber01-VHDL13_DWMG_080200_COR-2601080200-dsw--0-ia5 08-Jan-2026 04:02:00 4474
ber01-VHDL13_DWMG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 4519
ber01-VHDL13_DWMG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 5436
ber01-VHDL13_DWMG_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 13:44:19 5261
ber01-VHDL13_DWMG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 4399
ber01-VHDL13_DWMG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4243
ber01-VHDL13_DWMG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4239
ber01-VHDL13_DWMG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:01 4498
ber01-VHDL13_DWMG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3491
ber01-VHDL13_DWMO_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:06 3498
ber01-VHDL13_DWMO_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 3697
ber01-VHDL13_DWMO_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 4386
ber01-VHDL13_DWMO_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 13:44:50 4390
ber01-VHDL13_DWMO_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 3696
ber01-VHDL13_DWMO_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 3925
ber01-VHDL13_DWMO_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 3925
ber01-VHDL13_DWMO_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:01 3897
ber01-VHDL13_DWMO_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3058
ber01-VHDL13_DWMP_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:06 4326
ber01-VHDL13_DWMP_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 4555
ber01-VHDL13_DWMP_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 4813
ber01-VHDL13_DWMP_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 13:44:50 4817
ber01-VHDL13_DWMP_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 3984
ber01-VHDL13_DWMP_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4156
ber01-VHDL13_DWMP_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4156
ber01-VHDL13_DWMP_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:41:03 4346
ber01-VHDL13_DWMP_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 09:41:22 4350
ber01-VHDL13_DWMP_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3401
ber01-VHDL13_DWOG_080300-2601080300-dsw--0-ia5 08-Jan-2026 04:00:05 6145
ber01-VHDL13_DWOG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:07 6249
ber01-VHDL13_DWOG_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 16:32:55 7627
ber01-VHDL13_DWOG_081700-2601081700-dsw--0-ia5 08-Jan-2026 19:00:01 7666
ber01-VHDL13_DWOG_090300-2601090300-dsw--0-ia5 09-Jan-2026 04:00:02 8827
ber01-VHDL13_DWOG_090300_COR-2601090300-dsw--0-ia5 09-Jan-2026 01:51:47 8828
ber01-VHDL13_DWOG_090800-2601090800-dsw--0-ia5 09-Jan-2026 14:19:01 8723
ber01-VHDL13_DWOG_091700-2601091700-dsw--0-ia5 09-Jan-2026 19:00:01 7163
ber01-VHDL13_DWOH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:28:11 4606
ber01-VHDL13_DWOH_080400-2601080400-dsw--0-ia5 08-Jan-2026 05:58:11 4601
ber01-VHDL13_DWOH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:28:12 5532
ber01-VHDL13_DWOH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:15 5165
ber01-VHDL13_DWOH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:11 4786
ber01-VHDL13_DWOH_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:11 4753
ber01-VHDL13_DWOH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:16 4528
ber01-VHDL13_DWOH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:12 3549
ber01-VHDL13_DWOI_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:28:11 4753
ber01-VHDL13_DWOI_080400-2601080400-dsw--0-ia5 08-Jan-2026 05:58:11 4639
ber01-VHDL13_DWOI_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:28:12 5658
ber01-VHDL13_DWOI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:12 5374
ber01-VHDL13_DWOI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:17 4733
ber01-VHDL13_DWOI_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:16 4499
ber01-VHDL13_DWOI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:12 4894
ber01-VHDL13_DWOI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:12 4162
ber01-VHDL13_DWON_080350-2601080350-dsw--0-ia5 08-Jan-2026 03:50:31 4564
ber01-VHDL13_DWON_080618-2601080618-dsw--0-ia5 08-Jan-2026 06:18:47 4741
ber01-VHDL13_DWON_080715-2601080715-dsw--0-ia5 08-Jan-2026 07:15:37 4738
ber01-VHDL13_DWON_081051-2601081051-dsw--0-ia5 08-Jan-2026 10:51:57 4738
ber01-VHDL13_DWON_081345-2601081345-dsw--0-ia5 08-Jan-2026 13:46:07 4731
ber01-VHDL13_DWON_081553-2601081553-dsw--0-ia5 08-Jan-2026 15:53:56 4243
ber01-VHDL13_DWON_081632-2601081632-dsw--0-ia5 08-Jan-2026 16:32:43 4243
ber01-VHDL13_DWON_081632_COR-2601081632-dsw--0-ia5 08-Jan-2026 16:32:59 4247
ber01-VHDL13_DWON_081758-2601081758-dsw--0-ia5 08-Jan-2026 17:58:47 4243
ber01-VHDL13_DWON_081834-2601081834-dsw--0-ia5 08-Jan-2026 18:34:51 4243
ber01-VHDL13_DWON_082018-2601082018-dsw--0-ia5 08-Jan-2026 20:18:32 4512
ber01-VHDL13_DWON_082320-2601082320-dsw--0-ia5 08-Jan-2026 23:20:07 5395
ber01-VHDL13_DWON_090150-2601090150-dsw--0-ia5 09-Jan-2026 01:50:52 5360
ber01-VHDL13_DWON_090341-2601090341-dsw--0-ia5 09-Jan-2026 03:41:07 5360
ber01-VHDL13_DWON_090629-2601090629-dsw--0-ia5 09-Jan-2026 06:29:21 5022
ber01-VHDL13_DWON_090725-2601090725-dsw--0-ia5 09-Jan-2026 07:25:21 5341
ber01-VHDL13_DWON_091228-2601091228-dsw--0-ia5 09-Jan-2026 12:28:11 5326
ber01-VHDL13_DWON_091418-2601091418-dsw--0-ia5 09-Jan-2026 14:18:25 5334
ber01-VHDL13_DWON_091543-2601091543-dsw--0-ia5 09-Jan-2026 15:43:44 4430
ber01-VHDL13_DWON_091847-2601091847-dsw--0-ia5 09-Jan-2026 18:47:32 4430
ber01-VHDL13_DWON_091952-2601091952-dsw--0-ia5 09-Jan-2026 19:52:27 4516
ber01-VHDL13_DWON_092221-2601092221-dsw--0-ia5 09-Jan-2026 22:21:07 4516
ber01-VHDL13_DWON_092253-2601092253-dsw--0-ia5 09-Jan-2026 22:53:41 4550
ber01-VHDL13_DWPG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 2681
ber01-VHDL13_DWPG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:01 2682
ber01-VHDL13_DWPG_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:13:16 3120
ber01-VHDL13_DWPG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 3318
ber01-VHDL13_DWPG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 2834
ber01-VHDL13_DWPG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2905
ber01-VHDL13_DWPG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3144
ber01-VHDL13_DWPG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3573
ber01-VHDL13_DWPG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:39:25 3569
ber01-VHDL13_DWPG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2878
ber01-VHDL13_DWPH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 3004
ber01-VHDL13_DWPH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:01 3004
ber01-VHDL13_DWPH_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:15:00 3135
ber01-VHDL13_DWPH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 3281
ber01-VHDL13_DWPH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3028
ber01-VHDL13_DWPH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 3214
ber01-VHDL13_DWPH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3332
ber01-VHDL13_DWPH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3444
ber01-VHDL13_DWPH_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:39:36 3503
ber01-VHDL13_DWPH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 3099
ber01-VHDL13_DWSG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:30:02 3950
ber01-VHDL13_DWSG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 4406
ber01-VHDL13_DWSG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:30:02 4593
ber01-VHDL13_DWSG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 3983
ber01-VHDL13_DWSG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4119
ber01-VHDL13_DWSG_090200_COR-2601090200-dsw--0-ia5 09-Jan-2026 03:39:51 4251
ber01-VHDL13_DWSG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4678
ber01-VHDL13_DWSG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 5085
ber01-VHDL13_DWSG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 4853
ber01-VHDL17_DWOG_081200-2601081200-dsw--0-ia5 08-Jan-2026 12:40:04 4007
ber01-VHDL17_DWOG_091200-2601091200-dsw--0-ia5 09-Jan-2026 12:05:36 3211
swis2-VHDL20_DWEG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 5015
swis2-VHDL20_DWEG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:06 5146
swis2-VHDL20_DWEG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 6517
swis2-VHDL20_DWEG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5763
swis2-VHDL20_DWEG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5334
swis2-VHDL20_DWEG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5250
swis2-VHDL20_DWEG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5354
swis2-VHDL20_DWEG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4157
swis2-VHDL20_DWEH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 5411
swis2-VHDL20_DWEH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:06 6262
swis2-VHDL20_DWEH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 6910
swis2-VHDL20_DWEH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 6125
swis2-VHDL20_DWEH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5957
swis2-VHDL20_DWEH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5397
swis2-VHDL20_DWEH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5904
swis2-VHDL20_DWEH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4314
swis2-VHDL20_DWEI_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 5252
swis2-VHDL20_DWEI_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:06 5152
swis2-VHDL20_DWEI_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 6648
swis2-VHDL20_DWEI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5953
swis2-VHDL20_DWEI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5157
swis2-VHDL20_DWEI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5028
swis2-VHDL20_DWEI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5786
swis2-VHDL20_DWEI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4814
swis2-VHDL20_DWHG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 5725
swis2-VHDL20_DWHG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 5732
swis2-VHDL20_DWHG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 5881
swis2-VHDL20_DWHG_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 09:53:47 5885
swis2-VHDL20_DWHG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5120
swis2-VHDL20_DWHG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 5166
swis2-VHDL20_DWHG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:14 4931
swis2-VHDL20_DWHG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:06 5238
swis2-VHDL20_DWHG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 4578
swis2-VHDL20_DWHH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 5423
swis2-VHDL20_DWHH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:07 5423
swis2-VHDL20_DWHH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 5853
swis2-VHDL20_DWHH_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 09:54:11 5857
swis2-VHDL20_DWHH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 4699
swis2-VHDL20_DWHH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 4179
swis2-VHDL20_DWHH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:14 4201
swis2-VHDL20_DWHH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:06 4648
swis2-VHDL20_DWHH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 4656
swis2-VHDL20_DWLG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 3473
swis2-VHDL20_DWLG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:11 3775
swis2-VHDL20_DWLG_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:21:37 3788
swis2-VHDL20_DWLG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:01 4038
swis2-VHDL20_DWLG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3641
swis2-VHDL20_DWLG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3983
swis2-VHDL20_DWLG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3829
swis2-VHDL20_DWLG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4955
swis2-VHDL20_DWLG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3322
swis2-VHDL20_DWLH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 3743
swis2-VHDL20_DWLH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:11 4049
swis2-VHDL20_DWLH_080400_COR-2601080400-dsw--0-ia5 08-Jan-2026 06:21:01 4095
swis2-VHDL20_DWLH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:01 4143
swis2-VHDL20_DWLH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3673
swis2-VHDL20_DWLH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3487
swis2-VHDL20_DWLH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3656
swis2-VHDL20_DWLH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4653
swis2-VHDL20_DWLH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3069
swis2-VHDL20_DWLI_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 3681
swis2-VHDL20_DWLI_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:22:07 4015
swis2-VHDL20_DWLI_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:01 4254
swis2-VHDL20_DWLI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3668
swis2-VHDL20_DWLI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3511
swis2-VHDL20_DWLI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3504
swis2-VHDL20_DWLI_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:36:51 3822
swis2-VHDL20_DWLI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4230
swis2-VHDL20_DWLI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3158
swis2-VHDL20_DWMG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 4590
swis2-VHDL20_DWMG_080200_COR-2601080200-dsw--0-ia5 08-Jan-2026 04:02:00 4867
swis2-VHDL20_DWMG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:03 5058
swis2-VHDL20_DWMG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 6312
swis2-VHDL20_DWMG_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 13:54:32 6137
swis2-VHDL20_DWMG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4810
swis2-VHDL20_DWMG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4723
swis2-VHDL20_DWMG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4650
swis2-VHDL20_DWMG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5333
swis2-VHDL20_DWMG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:47:07 5350
swis2-VHDL20_DWMG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3904
swis2-VHDL20_DWMO_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 3900
swis2-VHDL20_DWMO_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:03 4240
swis2-VHDL20_DWMO_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 5201
swis2-VHDL20_DWMO_080800_COR-2601080800-dsw--0-ia5 08-Jan-2026 13:54:51 4806
swis2-VHDL20_DWMO_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4113
swis2-VHDL20_DWMO_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4411
swis2-VHDL20_DWMO_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4342
swis2-VHDL20_DWMO_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4700
swis2-VHDL20_DWMO_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:48:07 4695
swis2-VHDL20_DWMO_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3476
swis2-VHDL20_DWMP_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:02 4725
swis2-VHDL20_DWMP_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:03 5094
swis2-VHDL20_DWMP_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 5666
swis2-VHDL20_DWMP_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4414
swis2-VHDL20_DWMP_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4631
swis2-VHDL20_DWMP_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4570
swis2-VHDL20_DWMP_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5158
swis2-VHDL20_DWMP_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:48:40 5175
swis2-VHDL20_DWMP_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3804
swis2-VHDL20_DWPG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 3113
swis2-VHDL20_DWPG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:11 3164
swis2-VHDL20_DWPG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:01 3971
swis2-VHDL20_DWPG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3487
swis2-VHDL20_DWPG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3386
swis2-VHDL20_DWPG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3512
swis2-VHDL20_DWPG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4091
swis2-VHDL20_DWPG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:42:01 4087
swis2-VHDL20_DWPG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3396
swis2-VHDL20_DWPH_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 3476
swis2-VHDL20_DWPH_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:00:11 3458
swis2-VHDL20_DWPH_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:01 3925
swis2-VHDL20_DWPH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3672
swis2-VHDL20_DWPH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3684
swis2-VHDL20_DWPH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3692
swis2-VHDL20_DWPH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 3957
swis2-VHDL20_DWPH_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:42:01 4016
swis2-VHDL20_DWPH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3612
swis2-VHDL20_DWSG_080200-2601080200-dsw--0-ia5 08-Jan-2026 03:45:06 4365
swis2-VHDL20_DWSG_080400-2601080400-dsw--0-ia5 08-Jan-2026 06:15:03 4803
swis2-VHDL20_DWSG_080800-2601080800-dsw--0-ia5 08-Jan-2026 09:45:08 5182
swis2-VHDL20_DWSG_081300-2601081300-dsw--0-ia5 08-Jan-2026 14:45:18 5019
swis2-VHDL20_DWSG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4382
swis2-VHDL20_DWSG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 4676
swis2-VHDL20_DWSG_090200_COR-2601090200-dsw--0-ia5 09-Jan-2026 03:39:51 4485
swis2-VHDL20_DWSG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:02 5076
swis2-VHDL20_DWSG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5872
swis2-VHDL20_DWSG_091300-2601091300-dsw--0-ia5 09-Jan-2026 14:45:08 5659
swis2-VHDL20_DWSG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 5369
wst04-VHDL20_DWEG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:12 231004
wst04-VHDL20_DWEG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:21 230007
wst04-VHDL20_DWEG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:21 236393
wst04-VHDL20_DWEG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 234967
wst04-VHDL20_DWEG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 235841
wst04-VHDL20_DWEG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 235362
wst04-VHDL20_DWEG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 235888
wst04-VHDL20_DWEG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:11 234062
wst04-VHDL20_DWEH_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:12 228810
wst04-VHDL20_DWEH_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:21 229153
wst04-VHDL20_DWEH_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:16 232255
wst04-VHDL20_DWEH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 230813
wst04-VHDL20_DWEH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 231288
wst04-VHDL20_DWEH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 230795
wst04-VHDL20_DWEH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 232126
wst04-VHDL20_DWEH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:11 230228
wst04-VHDL20_DWEI_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:16 319512
wst04-VHDL20_DWEI_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:27 318184
wst04-VHDL20_DWEI_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:26 329180
wst04-VHDL20_DWEI_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 328339
wst04-VHDL20_DWEI_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 328502
wst04-VHDL20_DWEI_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:27 327449
wst04-VHDL20_DWEI_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:26 326485
wst04-VHDL20_DWEI_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 324877
wst04-VHDL20_DWHG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:12 311077
wst04-VHDL20_DWHG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:13 311144
wst04-VHDL20_DWHG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:16 315935
wst04-VHDL20_DWHG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 314075
wst04-VHDL20_DWHG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 314413
wst04-VHDL20_DWHG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:14 314082
wst04-VHDL20_DWHG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 314197
wst04-VHDL20_DWHG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 312567
wst04-VHDL20_DWHH_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:12 298856
wst04-VHDL20_DWHH_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:18 298910
wst04-VHDL20_DWHH_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:16 302393
wst04-VHDL20_DWHH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 301286
wst04-VHDL20_DWHH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 300645
wst04-VHDL20_DWHH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:14 300601
wst04-VHDL20_DWHH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:16 301585
wst04-VHDL20_DWHH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 300512
wst04-VHDL20_DWLG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:26 312826
wst04-VHDL20_DWLG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:41 313014
wst04-VHDL20_DWLG_080400_COR-2601080400-omedes-..> 08-Jan-2026 06:19:26 313015
wst04-VHDL20_DWLG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:32 317547
wst04-VHDL20_DWLG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 316972
wst04-VHDL20_DWLG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:27 317052
wst04-VHDL20_DWLG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 316557
wst04-VHDL20_DWLG_090400_COR-2601090400-omedes-..> 09-Jan-2026 07:32:46 317098
wst04-VHDL20_DWLG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 320387
wst04-VHDL20_DWLG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 318737
wst04-VHDL20_DWLH_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:22 303463
wst04-VHDL20_DWLH_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:41 303591
wst04-VHDL20_DWLH_080400_COR-2601080400-omedes-..> 08-Jan-2026 06:19:01 303614
wst04-VHDL20_DWLH_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:36 315857
wst04-VHDL20_DWLH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:26 315509
wst04-VHDL20_DWLH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 315073
wst04-VHDL20_DWLH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 314501
wst04-VHDL20_DWLH_090400_COR-2601090400-omedes-..> 09-Jan-2026 07:31:17 314452
wst04-VHDL20_DWLH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 311820
wst04-VHDL20_DWLH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 310803
wst04-VHDL20_DWLI_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:26 310562
wst04-VHDL20_DWLI_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:41 310719
wst04-VHDL20_DWLI_080400_COR-2601080400-omedes-..> 08-Jan-2026 06:20:17 310705
wst04-VHDL20_DWLI_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:32 318545
wst04-VHDL20_DWLI_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:26 318073
wst04-VHDL20_DWLI_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:27 317645
wst04-VHDL20_DWLI_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 317340
wst04-VHDL20_DWLI_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 314301
wst04-VHDL20_DWLI_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:27 313305
wst04-VHDL20_DWMG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:22 522920
wst04-VHDL20_DWMG_080200_COR-2601080200-omedes-..> 08-Jan-2026 04:02:05 523008
wst04-VHDL20_DWMG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:17 523909
wst04-VHDL20_DWMG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:21 530845
wst04-VHDL20_DWMG_080800_COR-2601080800-omedes-..> 08-Jan-2026 13:53:08 530355
wst04-VHDL20_DWMG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:20 529448
wst04-VHDL20_DWMG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 528841
wst04-VHDL20_DWMG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 528714
wst04-VHDL20_DWMG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:18 535890
wst04-VHDL20_DWMG_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:45:26 535900
wst04-VHDL20_DWMG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 533424
wst04-VHDL20_DWMO_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:22 419601
wst04-VHDL20_DWMO_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:17 420319
wst04-VHDL20_DWMO_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:21 430560
wst04-VHDL20_DWMO_080800_COR-2601080800-omedes-..> 08-Jan-2026 13:53:27 429938
wst04-VHDL20_DWMO_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 429496
wst04-VHDL20_DWMO_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 429686
wst04-VHDL20_DWMO_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:17 430041
wst04-VHDL20_DWMO_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:12 430128
wst04-VHDL20_DWMO_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:45:56 430098
wst04-VHDL20_DWMO_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 428338
wst04-VHDL20_DWMP_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:16 535384
wst04-VHDL20_DWMP_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:17 538013
wst04-VHDL20_DWMP_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:26 547303
wst04-VHDL20_DWMP_080800_COR-2601080800-omedes-..> 08-Jan-2026 13:53:56 547262
wst04-VHDL20_DWMP_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 544942
wst04-VHDL20_DWMP_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 544324
wst04-VHDL20_DWMP_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 546137
wst04-VHDL20_DWMP_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:18 551882
wst04-VHDL20_DWMP_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:46:27 551899
wst04-VHDL20_DWMP_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 549439
wst04-VHDL20_DWPG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:22 306055
wst04-VHDL20_DWPG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:32 305942
wst04-VHDL20_DWPG_080400_COR-2601080400-omedes-..> 08-Jan-2026 06:12:22 306425
wst04-VHDL20_DWPG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:32 356199
wst04-VHDL20_DWPG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 311661
wst04-VHDL20_DWPG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 311182
wst04-VHDL20_DWPG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:32 311233
wst04-VHDL20_DWPG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 357626
wst04-VHDL20_DWPG_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:40:50 357018
wst04-VHDL20_DWPG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:27 311835
wst04-VHDL20_DWPH_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:22 221900
wst04-VHDL20_DWPH_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:00:32 221851
wst04-VHDL20_DWPH_080400_COR-2601080400-omedes-..> 08-Jan-2026 06:13:50 221954
wst04-VHDL20_DWPH_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:26 267709
wst04-VHDL20_DWPH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 267813
wst04-VHDL20_DWPH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 222722
wst04-VHDL20_DWPH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:32 222972
wst04-VHDL20_DWPH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:26 269648
wst04-VHDL20_DWPH_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:41:16 269710
wst04-VHDL20_DWPH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 268911
wst04-VHDL20_DWSG_080200-2601080200-omedes--0.pdf 08-Jan-2026 03:45:16 332647
wst04-VHDL20_DWSG_080400-2601080400-omedes--0.pdf 08-Jan-2026 06:15:11 333711
wst04-VHDL20_DWSG_080800-2601080800-omedes--0.pdf 08-Jan-2026 09:45:12 340838
wst04-VHDL20_DWSG_081300-2601081300-omedes--0.pdf 08-Jan-2026 14:45:18 340865
wst04-VHDL20_DWSG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 338546
wst04-VHDL20_DWSG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 339397
wst04-VHDL20_DWSG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:17 340622
wst04-VHDL20_DWSG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:12 341169
wst04-VHDL20_DWSG_091300-2601091300-omedes--0.pdf 09-Jan-2026 14:45:14 341228
wst04-VHDL20_DWSG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:11 340790