Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Jul-2025 13:06:54 3273
FPDL13_DWMZ_180600 18-Jul-2025 12:11:43 3908
SXDL31_DWAV_170800 17-Jul-2025 07:00:04 11846
SXDL31_DWAV_171800 17-Jul-2025 16:11:45 12233
SXDL31_DWAV_180800 18-Jul-2025 08:08:10 8702
SXDL31_DWAV_181800 18-Jul-2025 17:19:10 8120
SXDL31_DWAV_LATEST 18-Jul-2025 17:19:10 8120
SXDL33_DWAV_170000 17-Jul-2025 09:32:47 9251
SXDL33_DWAV_180000 18-Jul-2025 09:18:46 8446
SXDL33_DWAV_LATEST 18-Jul-2025 09:18:46 8446
ber01-FWDL39_DWMS_171230-2507171230-dsw--0-ia5 17-Jul-2025 11:42:21 1568
ber01-FWDL39_DWMS_181230-2507181230-dsw--0-ia5 18-Jul-2025 12:29:42 1151
ber01-VHDL13_DWEH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:28:12 2477
ber01-VHDL13_DWEH_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:58:11 2354
ber01-VHDL13_DWEH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:28:12 2341
ber01-VHDL13_DWEH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:28:13 2126
ber01-VHDL13_DWEH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:28:06 2840
ber01-VHDL13_DWEH_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:58:12 2692
ber01-VHDL13_DWEH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:28:13 2967
ber01-VHDL13_DWEH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:28:12 2753
ber01-VHDL13_DWHG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:07 2771
ber01-VHDL13_DWHG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 3122
ber01-VHDL13_DWHG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 3545
ber01-VHDL13_DWHG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 2841
ber01-VHDL13_DWHG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:06 3014
ber01-VHDL13_DWHG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:11 3010
ber01-VHDL13_DWHG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:08 3103
ber01-VHDL13_DWHG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:06 2578
ber01-VHDL13_DWHH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:07 2517
ber01-VHDL13_DWHH_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 2896
ber01-VHDL13_DWHH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 3304
ber01-VHDL13_DWHH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 2647
ber01-VHDL13_DWHH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:06 2891
ber01-VHDL13_DWHH_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:11 2895
ber01-VHDL13_DWHH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:08 3023
ber01-VHDL13_DWHH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:06 2487
ber01-VHDL13_DWLG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:03 2159
ber01-VHDL13_DWLG_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:59:56 2074
ber01-VHDL13_DWLG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2774
ber01-VHDL13_DWLG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 1811
ber01-VHDL13_DWLG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 1887
ber01-VHDL13_DWLG_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:59:57 2182
ber01-VHDL13_DWLG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2346
ber01-VHDL13_DWLG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 2086
ber01-VHDL13_DWLH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:03 2188
ber01-VHDL13_DWLH_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:59:56 2419
ber01-VHDL13_DWLH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2857
ber01-VHDL13_DWLH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 1716
ber01-VHDL13_DWLH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 1938
ber01-VHDL13_DWLH_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:59:57 2384
ber01-VHDL13_DWLH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2723
ber01-VHDL13_DWLH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 2135
ber01-VHDL13_DWLI_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:03 1976
ber01-VHDL13_DWLI_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:59:56 2009
ber01-VHDL13_DWLI_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2263
ber01-VHDL13_DWLI_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 1712
ber01-VHDL13_DWLI_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 1923
ber01-VHDL13_DWLI_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:59:57 2221
ber01-VHDL13_DWLI_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2341
ber01-VHDL13_DWLI_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 2065
ber01-VHDL13_DWMG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2656
ber01-VHDL13_DWMG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:02 2486
ber01-VHDL13_DWMG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2435
ber01-VHDL13_DWMG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:00 2067
ber01-VHDL13_DWMG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 2471
ber01-VHDL13_DWMG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 2470
ber01-VHDL13_DWMG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2497
ber01-VHDL13_DWMG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:06 2467
ber01-VHDL13_DWMO_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2484
ber01-VHDL13_DWMO_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:02 2479
ber01-VHDL13_DWMO_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2488
ber01-VHDL13_DWMO_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:10 2138
ber01-VHDL13_DWMO_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 2559
ber01-VHDL13_DWMO_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 2556
ber01-VHDL13_DWMO_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2465
ber01-VHDL13_DWMO_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:06 2332
ber01-VHDL13_DWMP_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2690
ber01-VHDL13_DWMP_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:02 2535
ber01-VHDL13_DWMP_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 2513
ber01-VHDL13_DWMP_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:00 2146
ber01-VHDL13_DWMP_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 2477
ber01-VHDL13_DWMP_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 2475
ber01-VHDL13_DWMP_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2630
ber01-VHDL13_DWMP_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:06 2480
ber01-VHDL13_DWOG_170300-2507170300-dsw--0-ia5 17-Jul-2025 03:00:01 3228
ber01-VHDL13_DWOG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:10 3448
ber01-VHDL13_DWOG_171700-2507171700-dsw--0-ia5 17-Jul-2025 18:00:01 3911
ber01-VHDL13_DWOG_180300-2507180300-dsw--0-ia5 18-Jul-2025 03:00:03 4461
ber01-VHDL13_DWOG_180300_COR-2507180300-dsw--0-ia5 18-Jul-2025 03:15:34 4459
ber01-VHDL13_DWOG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:03 4350
ber01-VHDL13_DWOG_181700-2507181700-dsw--0-ia5 18-Jul-2025 18:00:02 3930
ber01-VHDL13_DWOH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:28:06 2357
ber01-VHDL13_DWOH_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:58:05 2222
ber01-VHDL13_DWOH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:28:12 2263
ber01-VHDL13_DWOH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:28:13 2104
ber01-VHDL13_DWOH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:28:12 2796
ber01-VHDL13_DWOH_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:58:12 2691
ber01-VHDL13_DWOH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:28:13 2966
ber01-VHDL13_DWOH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:28:12 2643
ber01-VHDL13_DWOI_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:28:12 2089
ber01-VHDL13_DWOI_170400-2507170400-dsw--0-ia5 17-Jul-2025 04:58:11 1957
ber01-VHDL13_DWOI_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:28:06 1966
ber01-VHDL13_DWOI_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:28:07 1793
ber01-VHDL13_DWOI_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:28:12 2304
ber01-VHDL13_DWOI_180400-2507180400-dsw--0-ia5 18-Jul-2025 04:58:06 2259
ber01-VHDL13_DWOI_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:28:08 2524
ber01-VHDL13_DWOI_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:28:06 2523
ber01-VHDL13_DWON_170515-2507170515-dsw--0-ia5 17-Jul-2025 05:15:38 3766
ber01-VHDL13_DWON_170547-2507170547-dsw--0-ia5 17-Jul-2025 05:47:41 3906
ber01-VHDL13_DWON_171247-2507171247-dsw--0-ia5 17-Jul-2025 12:47:16 4048
ber01-VHDL13_DWON_171433-2507171433-dsw--0-ia5 17-Jul-2025 14:33:37 3317
ber01-VHDL13_DWON_171636-2507171636-dsw--0-ia5 17-Jul-2025 16:36:26 3372
ber01-VHDL13_DWON_172157-2507172157-dsw--0-ia5 17-Jul-2025 21:57:56 3015
ber01-VHDL13_DWON_172227-2507172227-dsw--0-ia5 17-Jul-2025 22:27:57 3662
ber01-VHDL13_DWON_172228-2507172228-dsw--0-ia5 17-Jul-2025 22:28:56 3433
ber01-VHDL13_DWON_180315-2507180315-dsw--0-ia5 18-Jul-2025 03:15:11 3435
ber01-VHDL13_DWON_180526-2507180526-dsw--0-ia5 18-Jul-2025 05:27:01 3884
ber01-VHDL13_DWON_180602-2507180602-dsw--0-ia5 18-Jul-2025 06:02:11 3766
ber01-VHDL13_DWON_181004-2507181004-dsw--0-ia5 18-Jul-2025 10:04:41 3766
ber01-VHDL13_DWON_181355-2507181355-dsw--0-ia5 18-Jul-2025 13:55:06 4015
ber01-VHDL13_DWON_181742-2507181742-dsw--0-ia5 18-Jul-2025 17:42:12 3318
ber01-VHDL13_DWON_190000-2507190000-dsw--0-ia5 19-Jul-2025 00:00:11 3609
ber01-VHDL13_DWPG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2221
ber01-VHDL13_DWPG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 2485
ber01-VHDL13_DWPG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:02 2383
ber01-VHDL13_DWPG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:00 1738
ber01-VHDL13_DWPG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 1982
ber01-VHDL13_DWPG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 2304
ber01-VHDL13_DWPG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2754
ber01-VHDL13_DWPG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 2192
ber01-VHDL13_DWPH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2397
ber01-VHDL13_DWPH_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 2556
ber01-VHDL13_DWPH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:02 2515
ber01-VHDL13_DWPH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:00 2048
ber01-VHDL13_DWPH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 2342
ber01-VHDL13_DWPH_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 2562
ber01-VHDL13_DWPH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:01 2980
ber01-VHDL13_DWPH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 2287
ber01-VHDL13_DWSG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:30:01 2456
ber01-VHDL13_DWSG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 2485
ber01-VHDL13_DWSG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:30:02 2485
ber01-VHDL13_DWSG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:30:00 2211
ber01-VHDL13_DWSG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:30:01 2648
ber01-VHDL13_DWSG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:07 3163
ber01-VHDL13_DWSG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:30:03 3164
ber01-VHDL13_DWSG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:30:04 3225
ber01-VHDL17_DWOG_171200-2507171200-dsw--0-ia5 17-Jul-2025 11:52:52 3304
ber01-VHDL17_DWOG_181200-2507181200-dsw--0-ia5 18-Jul-2025 10:56:41 2759
swis2-VHDL20_DWEG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:11 2489
swis2-VHDL20_DWEG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:15:07 2430
swis2-VHDL20_DWEG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:01 2442
swis2-VHDL20_DWEG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:07 2289
swis2-VHDL20_DWEG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:07 2928
swis2-VHDL20_DWEG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:15:06 2899
swis2-VHDL20_DWEG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 3145
swis2-VHDL20_DWEG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:02 2828
swis2-VHDL20_DWEH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:11 2641
swis2-VHDL20_DWEH_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:15:11 2532
swis2-VHDL20_DWEH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:06 2519
swis2-VHDL20_DWEH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:11 2326
swis2-VHDL20_DWEH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:17 3004
swis2-VHDL20_DWEH_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:15:12 2870
swis2-VHDL20_DWEH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 3145
swis2-VHDL20_DWEH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:06 2953
swis2-VHDL20_DWEI_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:11 2222
swis2-VHDL20_DWEI_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:15:11 2142
swis2-VHDL20_DWEI_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:01 2145
swis2-VHDL20_DWEI_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:07 1978
swis2-VHDL20_DWEI_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:07 2437
swis2-VHDL20_DWEI_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:15:12 2444
swis2-VHDL20_DWEI_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 2703
swis2-VHDL20_DWEI_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:02 2708
swis2-VHDL20_DWHG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:02 2957
swis2-VHDL20_DWHG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 3305
swis2-VHDL20_DWHG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:06 3728
swis2-VHDL20_DWHG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:04 3024
swis2-VHDL20_DWHG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:07 3200
swis2-VHDL20_DWHG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:11 3193
swis2-VHDL20_DWHG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 3286
swis2-VHDL20_DWHG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:02 2761
swis2-VHDL20_DWHH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:02 2703
swis2-VHDL20_DWHH_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:11 3082
swis2-VHDL20_DWHH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:06 3490
swis2-VHDL20_DWHH_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:04 2833
swis2-VHDL20_DWHH_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:07 3077
swis2-VHDL20_DWHH_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:11 3081
swis2-VHDL20_DWHH_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 3209
swis2-VHDL20_DWHH_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:02 2673
swis2-VHDL20_DWLG_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:02 2380
swis2-VHDL20_DWLG_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:23 2295
swis2-VHDL20_DWLG_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:06 2998
swis2-VHDL20_DWLG_171800-2507171800-dsw--0-ia5 17-Jul-2025 18:45:04 2032
swis2-VHDL20_DWLG_180200-2507180200-dsw--0-ia5 18-Jul-2025 02:45:04 2108
swis2-VHDL20_DWLG_180400-2507180400-dsw--0-ia5 18-Jul-2025 05:00:23 2403
swis2-VHDL20_DWLG_180800-2507180800-dsw--0-ia5 18-Jul-2025 08:45:12 2570
swis2-VHDL20_DWLG_181800-2507181800-dsw--0-ia5 18-Jul-2025 18:45:02 2307
swis2-VHDL20_DWLH_170200-2507170200-dsw--0-ia5 17-Jul-2025 02:45:02 2409
swis2-VHDL20_DWLH_170400-2507170400-dsw--0-ia5 17-Jul-2025 05:00:23 2640
swis2-VHDL20_DWLH_170800-2507170800-dsw--0-ia5 17-Jul-2025 08:45:06 3078
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