Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-May-2026 12:30:17 17108
FPDL13_DWMZ_040600 04-May-2026 12:48:39 3447
SXDL31_DWAV_031800 03-May-2026 15:22:35 8449
SXDL31_DWAV_040800 04-May-2026 08:13:23 14074
SXDL31_DWAV_041800 04-May-2026 16:03:43 9769
SXDL31_DWAV_050800 05-May-2026 07:35:19 7712
SXDL31_DWAV_LATEST 05-May-2026 07:35:19 7712
SXDL33_DWAV_040000 04-May-2026 10:59:14 6379
SXDL33_DWAV_051014 05-May-2026 10:14:43 8270
SXDL33_DWAV_LATEST 05-May-2026 10:14:43 8270
ber01-FWDL39_DWMS_031230-2605031230-dsw--0-ia5 03-May-2026 11:38:31 929
ber01-FWDL39_DWMS_041230-2605041230-dsw--0-ia5 04-May-2026 11:35:24 1557
ber01-VHDL13_DWEG_040800-2605040800-dsw--0-ia5 04-May-2026 08:28:26 3402
ber01-VHDL13_DWEG_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:22 3660
ber01-VHDL13_DWEH_040800-2605040800-dsw--0-ia5 04-May-2026 08:28:26 3282
ber01-VHDL13_DWEH_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:22 3732
ber01-VHDL13_DWEI_040800-2605040800-dsw--0-ia5 04-May-2026 08:28:26 3229
ber01-VHDL13_DWEI_050800-2605050800-dsw--0-ia5 05-May-2026 08:28:26 3454
ber01-VHDL13_DWHG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 11:18:21 3907
ber01-VHDL13_DWHG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 3798
ber01-VHDL13_DWHG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 4085
ber01-VHDL13_DWHH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 2997
ber01-VHDL13_DWHH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3160
ber01-VHDL13_DWLG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 2367
ber01-VHDL13_DWLG_040800_COR-2605040800-dsw--0-ia5 04-May-2026 10:04:32 2316
ber01-VHDL13_DWLG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2680
ber01-VHDL13_DWLH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 2621
ber01-VHDL13_DWLH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3069
ber01-VHDL13_DWLI_040800-2605040800-dsw--0-ia5 04-May-2026 10:05:02 2379
ber01-VHDL13_DWLI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2873
ber01-VHDL13_DWMO_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 3209
ber01-VHDL13_DWMO_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3492
ber01-VHDL13_DWMP_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 2866
ber01-VHDL13_DWMP_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3563
ber01-VHDL13_DWOG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 13:24:11 5434
ber01-VHDL13_DWOG_031700-2605031700-dsw--0-ia5 03-May-2026 18:00:07 5038
ber01-VHDL13_DWOG_031700_COR-2605031700-dsw--0-ia5 03-May-2026 17:39:47 5041
ber01-VHDL13_DWOG_040300-2605040300-dsw--0-ia5 04-May-2026 03:00:06 4157
ber01-VHDL13_DWOG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 4517
ber01-VHDL13_DWOG_041700-2605041700-dsw--0-ia5 04-May-2026 18:00:07 4747
ber01-VHDL13_DWOG_050300-2605050300-dsw--0-ia5 05-May-2026 03:00:15 5053
ber01-VHDL13_DWOG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 4581
ber01-VHDL13_DWON_031321-2605031321-dsw--0-ia5 03-May-2026 13:21:57 4640
ber01-VHDL13_DWON_031455-2605031455-dsw--0-ia5 03-May-2026 14:55:20 4616
ber01-VHDL13_DWON_031627-2605031627-dsw--0-ia5 03-May-2026 16:28:01 4536
ber01-VHDL13_DWON_031739-2605031739-dsw--0-ia5 03-May-2026 17:39:33 4536
ber01-VHDL13_DWON_040129-2605040129-dsw--0-ia5 04-May-2026 01:30:07 4281
ber01-VHDL13_DWON_040140-2605040140-dsw--0-ia5 04-May-2026 01:40:21 4173
ber01-VHDL13_DWON_040249-2605040249-dsw--0-ia5 04-May-2026 02:50:09 4222
ber01-VHDL13_DWON_040527-2605040527-dsw--0-ia5 04-May-2026 05:27:16 4331
ber01-VHDL13_DWON_040625-2605040625-dsw--0-ia5 04-May-2026 06:25:17 4722
ber01-VHDL13_DWON_040808-2605040808-dsw--0-ia5 04-May-2026 08:08:52 4521
ber01-VHDL13_DWON_040852-2605040852-dsw--0-ia5 04-May-2026 08:52:26 4521
ber01-VHDL13_DWON_041416-2605041416-dsw--0-ia5 04-May-2026 14:16:11 4398
ber01-VHDL13_DWON_041657-2605041657-dsw--0-ia5 04-May-2026 16:57:21 4242
ber01-VHDL13_DWON_041845-2605041845-dsw--0-ia5 04-May-2026 18:46:01 4494
ber01-VHDL13_DWON_042132-2605042132-dsw--0-ia5 04-May-2026 21:32:37 4538
ber01-VHDL13_DWON_050010-2605050010-dsw--0-ia5 05-May-2026 00:10:22 5024
ber01-VHDL13_DWON_050145-2605050145-dsw--0-ia5 05-May-2026 01:45:56 4954
ber01-VHDL13_DWON_050257-2605050257-dsw--0-ia5 05-May-2026 02:57:17 4954
ber01-VHDL13_DWON_050303-2605050303-dsw--0-ia5 05-May-2026 03:03:08 4954
ber01-VHDL13_DWON_050518-2605050518-dsw--0-ia5 05-May-2026 05:18:21 5331
ber01-VHDL13_DWON_050546-2605050546-dsw--0-ia5 05-May-2026 05:46:51 5331
ber01-VHDL13_DWON_050743-2605050743-dsw--0-ia5 05-May-2026 07:43:52 5039
ber01-VHDL13_DWON_050847-2605050847-dsw--0-ia5 05-May-2026 08:47:40 4957
ber01-VHDL13_DWPG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 3850
ber01-VHDL13_DWPG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3458
ber01-VHDL13_DWPH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 2832
ber01-VHDL13_DWPH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 2667
ber01-VHDL13_DWSG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 15:17:51 2979
ber01-VHDL13_DWSG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 2644
ber01-VHDL13_DWSG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 3010
ber01-VHDL17_DWOG_031200-2605031200-dsw--0-ia5 03-May-2026 11:47:57 3054
ber01-VHDL17_DWOG_041200-2605041200-dsw--0-ia5 04-May-2026 12:01:21 3688
swis2-VHDL20_DWEG_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1491
swis2-VHDL20_DWEG_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 1309
swis2-VHDL20_DWEG_040400-2605040400-dsw--0-ia5 04-May-2026 05:02:17 1547
swis2-VHDL20_DWEG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 1820
swis2-VHDL20_DWEG_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1966
swis2-VHDL20_DWEG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1926
swis2-VHDL20_DWEG_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 2009
swis2-VHDL20_DWEG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 2218
swis2-VHDL20_DWEH_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1799
swis2-VHDL20_DWEH_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 1570
swis2-VHDL20_DWEH_040400-2605040400-dsw--0-ia5 04-May-2026 05:02:17 1818
swis2-VHDL20_DWEH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 2120
swis2-VHDL20_DWEH_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 2244
swis2-VHDL20_DWEH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1903
swis2-VHDL20_DWEH_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 1796
swis2-VHDL20_DWEH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 2005
swis2-VHDL20_DWEI_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1488
swis2-VHDL20_DWEI_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 1331
swis2-VHDL20_DWEI_040400-2605040400-dsw--0-ia5 04-May-2026 05:02:17 1507
swis2-VHDL20_DWEI_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 1733
swis2-VHDL20_DWEI_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1665
swis2-VHDL20_DWEI_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1679
swis2-VHDL20_DWEI_050400-2605050400-dsw--0-ia5 05-May-2026 05:02:17 1781
swis2-VHDL20_DWEI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:01 1991
swis2-VHDL20_DWHG_031800-2605031800-dsw--0-ia5 03-May-2026 18:45:01 2062
swis2-VHDL20_DWHG_040200-2605040200-dsw--0-ia5 04-May-2026 02:45:19 1740
swis2-VHDL20_DWHG_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:07 1560
swis2-VHDL20_DWHG_040800-2605040800-dsw--0-ia5 04-May-2026 08:45:10 1909
swis2-VHDL20_DWHG_041800-2605041800-dsw--0-ia5 04-May-2026 18:45:04 2247
swis2-VHDL20_DWHG_050200-2605050200-dsw--0-ia5 05-May-2026 02:45:07 2028
swis2-VHDL20_DWHG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 2025
swis2-VHDL20_DWHG_050800-2605050800-dsw--0-ia5 05-May-2026 08:45:08 2274
swis2-VHDL20_DWHH_031800-2605031800-dsw--0-ia5 03-May-2026 18:45:01 1433
swis2-VHDL20_DWHH_040200-2605040200-dsw--0-ia5 04-May-2026 02:45:19 1004
swis2-VHDL20_DWHH_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:07 1004
swis2-VHDL20_DWHH_040800-2605040800-dsw--0-ia5 04-May-2026 08:45:10 1077
swis2-VHDL20_DWHH_041800-2605041800-dsw--0-ia5 04-May-2026 18:45:04 1178
swis2-VHDL20_DWHH_050200-2605050200-dsw--0-ia5 05-May-2026 02:45:07 1127
swis2-VHDL20_DWHH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1127
swis2-VHDL20_DWHH_050800-2605050800-dsw--0-ia5 05-May-2026 08:45:08 1349
swis2-VHDL20_DWLG_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1142
swis2-VHDL20_DWLG_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:24 1012
swis2-VHDL20_DWLG_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:11 984
swis2-VHDL20_DWLG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:23 1113
swis2-VHDL20_DWLG_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1510
swis2-VHDL20_DWLG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1221
swis2-VHDL20_DWLG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1254
swis2-VHDL20_DWLG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1570
swis2-VHDL20_DWLH_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1217
swis2-VHDL20_DWLH_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:24 1177
swis2-VHDL20_DWLH_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:11 1152
swis2-VHDL20_DWLH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:21 1280
swis2-VHDL20_DWLH_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1576
swis2-VHDL20_DWLH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1227
swis2-VHDL20_DWLH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1260
swis2-VHDL20_DWLH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1650
swis2-VHDL20_DWLI_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1161
swis2-VHDL20_DWLI_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:24 1174
swis2-VHDL20_DWLI_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:11 1146
swis2-VHDL20_DWLI_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:21 1275
swis2-VHDL20_DWLI_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1532
swis2-VHDL20_DWLI_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1223
swis2-VHDL20_DWLI_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1412
swis2-VHDL20_DWLI_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1733
swis2-VHDL20_DWMO_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:06 1446
swis2-VHDL20_DWMO_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 1118
swis2-VHDL20_DWMO_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:07 1202
swis2-VHDL20_DWMO_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 1658
swis2-VHDL20_DWMO_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1328
swis2-VHDL20_DWMO_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1331
swis2-VHDL20_DWMO_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1287
swis2-VHDL20_DWMO_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1465
swis2-VHDL20_DWMP_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:06 1706
swis2-VHDL20_DWMP_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 1146
swis2-VHDL20_DWMP_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:07 1226
swis2-VHDL20_DWMP_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:07 1684
swis2-VHDL20_DWMP_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1706
swis2-VHDL20_DWMP_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:02 1199
swis2-VHDL20_DWMP_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:07 1151
swis2-VHDL20_DWMP_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1646
swis2-VHDL20_DWPG_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1237
swis2-VHDL20_DWPG_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:24 1390
swis2-VHDL20_DWPG_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:11 1384
swis2-VHDL20_DWPG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:21 2082
swis2-VHDL20_DWPG_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 1684
swis2-VHDL20_DWPG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 1231
swis2-VHDL20_DWPG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 1228
swis2-VHDL20_DWPG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 1562
swis2-VHDL20_DWPH_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1295
swis2-VHDL20_DWPH_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:24 1048
swis2-VHDL20_DWPH_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:11 1116
swis2-VHDL20_DWPH_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:21 1263
swis2-VHDL20_DWPH_041800-2605041800-dsw--0-ia5 04-May-2026 18:31:03 968
swis2-VHDL20_DWPH_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:22 903
swis2-VHDL20_DWPH_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:17 878
swis2-VHDL20_DWPH_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:21 968
swis2-VHDL20_DWSG_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1442
swis2-VHDL20_DWSG_040200-2605040200-dsw--0-ia5 04-May-2026 02:30:07 867
swis2-VHDL20_DWSG_040400-2605040400-dsw--0-ia5 04-May-2026 05:00:22 919
swis2-VHDL20_DWSG_040800-2605040800-dsw--0-ia5 04-May-2026 08:30:03 1303
swis2-VHDL20_DWSG_041800-2605041800-dsw--0-ia5 04-May-2026 18:30:05 1625
swis2-VHDL20_DWSG_050200-2605050200-dsw--0-ia5 05-May-2026 02:30:06 1490
swis2-VHDL20_DWSG_050400-2605050400-dsw--0-ia5 05-May-2026 05:00:21 1388
swis2-VHDL20_DWSG_050800-2605050800-dsw--0-ia5 05-May-2026 08:30:07 1226
wst04-VHDL20_DWEG_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:22 242185
wst04-VHDL20_DWEG_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:17 241154
wst04-VHDL20_DWEG_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:13 241892
wst04-VHDL20_DWEG_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:11 243125
wst04-VHDL20_DWEG_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:22 244126
wst04-VHDL20_DWEG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:13 243194
wst04-VHDL20_DWEG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:13 243427
wst04-VHDL20_DWEG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:11 244490
wst04-VHDL20_DWEH_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:12 238825
wst04-VHDL20_DWEH_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:11 238241
wst04-VHDL20_DWEH_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:13 238453
wst04-VHDL20_DWEH_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:11 239590
wst04-VHDL20_DWEH_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:18 244654
wst04-VHDL20_DWEH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:18 244192
wst04-VHDL20_DWEH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:17 243789
wst04-VHDL20_DWEH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:11 244871
wst04-VHDL20_DWEI_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:18 344853
wst04-VHDL20_DWEI_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:24 343704
wst04-VHDL20_DWEI_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:17 343916
wst04-VHDL20_DWEI_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:17 345292
wst04-VHDL20_DWEI_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:28 346586
wst04-VHDL20_DWEI_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:18 346919
wst04-VHDL20_DWEI_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:17 346495
wst04-VHDL20_DWEI_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:17 346845
wst04-VHDL20_DWHG_031800-2605031800-omedes--0.pdf 03-May-2026 18:45:12 343809
wst04-VHDL20_DWHG_040200-2605040200-omedes--0.pdf 04-May-2026 02:45:19 342508
wst04-VHDL20_DWHG_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:11 341706
wst04-VHDL20_DWHG_040800-2605040800-omedes--0.pdf 04-May-2026 08:45:15 344042
wst04-VHDL20_DWHG_041800-2605041800-omedes--0.pdf 04-May-2026 18:45:12 351034
wst04-VHDL20_DWHG_050200-2605050200-omedes--0.pdf 05-May-2026 02:45:32 350509
wst04-VHDL20_DWHG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 350492
wst04-VHDL20_DWHG_050800-2605050800-omedes--0.pdf 05-May-2026 08:45:18 352198
wst04-VHDL20_DWHH_031800-2605031800-omedes--0.pdf 03-May-2026 18:45:12 333286
wst04-VHDL20_DWHH_040200-2605040200-omedes--0.pdf 04-May-2026 02:45:19 331356
wst04-VHDL20_DWHH_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:11 225574
wst04-VHDL20_DWHH_040800-2605040800-omedes--0.pdf 04-May-2026 08:45:15 332019
wst04-VHDL20_DWHH_041800-2605041800-omedes--0.pdf 04-May-2026 18:45:12 321790
wst04-VHDL20_DWHH_050200-2605050200-omedes--0.pdf 05-May-2026 02:45:32 321788
wst04-VHDL20_DWHH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 219659
wst04-VHDL20_DWHH_050800-2605050800-omedes--0.pdf 05-May-2026 08:45:18 322722
wst04-VHDL20_DWLG_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 341766
wst04-VHDL20_DWLG_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:37 341513
wst04-VHDL20_DWLG_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:43 341732
wst04-VHDL20_DWLG_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:51 342008
wst04-VHDL20_DWLG_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:33 344822
wst04-VHDL20_DWLG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:27 344754
wst04-VHDL20_DWLG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:41 344500
wst04-VHDL20_DWLG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:51 345949
wst04-VHDL20_DWLH_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:21 337548
wst04-VHDL20_DWLH_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:28 337575
wst04-VHDL20_DWLH_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:43 337838
wst04-VHDL20_DWLH_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:41 338118
wst04-VHDL20_DWLH_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:24 352427
wst04-VHDL20_DWLH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 352076
wst04-VHDL20_DWLH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:47 351544
wst04-VHDL20_DWLH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:46 353200
wst04-VHDL20_DWLI_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:33 341876
wst04-VHDL20_DWLI_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:32 342045
wst04-VHDL20_DWLI_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:47 342227
wst04-VHDL20_DWLI_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:47 387091
wst04-VHDL20_DWLI_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:29 348819
wst04-VHDL20_DWLI_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 348687
wst04-VHDL20_DWLI_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:41 348912
wst04-VHDL20_DWLI_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:41 395003
wst04-VHDL20_DWMO_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:27 350726
wst04-VHDL20_DWMO_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:17 457211
wst04-VHDL20_DWMO_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:22 457125
wst04-VHDL20_DWMO_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:27 456586
wst04-VHDL20_DWMO_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:22 354458
wst04-VHDL20_DWMO_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:22 466024
wst04-VHDL20_DWMO_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:21 466186
wst04-VHDL20_DWMO_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:26 467004
wst04-VHDL20_DWMP_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:27 468793
wst04-VHDL20_DWMP_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:24 571385
wst04-VHDL20_DWMP_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:22 571344
wst04-VHDL20_DWMP_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:33 468574
wst04-VHDL20_DWMP_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:28 474927
wst04-VHDL20_DWMP_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:22 578608
wst04-VHDL20_DWMP_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:21 578506
wst04-VHDL20_DWMP_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:33 475199
wst04-VHDL20_DWPG_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 334438
wst04-VHDL20_DWPG_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:28 237910
wst04-VHDL20_DWPG_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:32 334755
wst04-VHDL20_DWPG_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:47 380543
wst04-VHDL20_DWPG_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:29 354021
wst04-VHDL20_DWPG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:31 244697
wst04-VHDL20_DWPG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:31 352977
wst04-VHDL20_DWPG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:46 398505
wst04-VHDL20_DWPH_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 241401
wst04-VHDL20_DWPH_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:28 241057
wst04-VHDL20_DWPH_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:32 242139
wst04-VHDL20_DWPH_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:41 242058
wst04-VHDL20_DWPH_041800-2605041800-omedes--0.pdf 04-May-2026 18:31:24 243625
wst04-VHDL20_DWPH_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:27 243879
wst04-VHDL20_DWPH_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:31 243453
wst04-VHDL20_DWPH_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:41 243395
wst04-VHDL20_DWSG_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:22 356514
wst04-VHDL20_DWSG_040200-2605040200-omedes--0.pdf 04-May-2026 02:30:11 355622
wst04-VHDL20_DWSG_040400-2605040400-omedes--0.pdf 04-May-2026 05:00:17 355645
wst04-VHDL20_DWSG_040800-2605040800-omedes--0.pdf 04-May-2026 08:30:25 356052
wst04-VHDL20_DWSG_041800-2605041800-omedes--0.pdf 04-May-2026 18:30:18 353266
wst04-VHDL20_DWSG_050200-2605050200-omedes--0.pdf 05-May-2026 02:30:11 352729
wst04-VHDL20_DWSG_050400-2605050400-omedes--0.pdf 05-May-2026 05:00:11 352017
wst04-VHDL20_DWSG_050800-2605050800-omedes--0.pdf 05-May-2026 08:30:26 351552