Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_090600 09-Jan-2026 14:30:58 3250
FPDL13_DWMZ_100600 10-Jan-2026 13:22:39 3927
SXDL31_DWAV_090800 09-Jan-2026 09:00:36 13548
SXDL31_DWAV_091800 09-Jan-2026 18:00:19 9642
SXDL31_DWAV_100800 10-Jan-2026 09:29:23 10405
SXDL31_DWAV_101800 10-Jan-2026 18:12:49 7477
SXDL31_DWAV_LATEST 10-Jan-2026 18:12:49 7477
SXDL33_DWAV_090000 09-Jan-2026 11:52:05 10948
SXDL33_DWAV_100000 10-Jan-2026 10:33:21 6268
SXDL33_DWAV_LATEST 10-Jan-2026 10:33:21 6268
ber01-FWDL39_DWMS_091230-2601091230-dsw--0-ia5 09-Jan-2026 13:00:52 1386
ber01-FWDL39_DWMS_101230-2601101230-dsw--0-ia5 10-Jan-2026 12:25:28 1416
ber01-VHDL13_DWEH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:15 5453
ber01-VHDL13_DWEH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:11 5318
ber01-VHDL13_DWEH_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:16 4872
ber01-VHDL13_DWEH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:16 5120
ber01-VHDL13_DWEH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:18 3745
ber01-VHDL13_DWEH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:11 4058
ber01-VHDL13_DWEH_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:12 3971
ber01-VHDL13_DWEH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:16 3894
ber01-VHDL13_DWHG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 4937
ber01-VHDL13_DWHG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4980
ber01-VHDL13_DWHG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4748
ber01-VHDL13_DWHG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4577
ber01-VHDL13_DWHG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 4395
ber01-VHDL13_DWHG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 4915
ber01-VHDL13_DWHG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4575
ber01-VHDL13_DWHG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4561
ber01-VHDL13_DWHH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 4513
ber01-VHDL13_DWHH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 3993
ber01-VHDL13_DWHH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4015
ber01-VHDL13_DWHH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3860
ber01-VHDL13_DWHH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 4470
ber01-VHDL13_DWHH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 4282
ber01-VHDL13_DWHH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4005
ber01-VHDL13_DWHH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4326
ber01-VHDL13_DWLG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3083
ber01-VHDL13_DWLG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 3422
ber01-VHDL13_DWLG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3451
ber01-VHDL13_DWLG_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:36:06 3714
ber01-VHDL13_DWLG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4315
ber01-VHDL13_DWLG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2910
ber01-VHDL13_DWLG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 3262
ber01-VHDL13_DWLG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3301
ber01-VHDL13_DWLG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3399
ber01-VHDL13_DWLH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3091
ber01-VHDL13_DWLH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2902
ber01-VHDL13_DWLH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3271
ber01-VHDL13_DWLH_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:33:52 3523
ber01-VHDL13_DWLH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 4005
ber01-VHDL13_DWLH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2654
ber01-VHDL13_DWLH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2879
ber01-VHDL13_DWLH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3050
ber01-VHDL13_DWLH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 2934
ber01-VHDL13_DWLI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3108
ber01-VHDL13_DWLI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2948
ber01-VHDL13_DWLI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3124
ber01-VHDL13_DWLI_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:35:15 3412
ber01-VHDL13_DWLI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3592
ber01-VHDL13_DWLI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2748
ber01-VHDL13_DWLI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2924
ber01-VHDL13_DWLI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3008
ber01-VHDL13_DWLI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3100
ber01-VHDL13_DWMG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 4399
ber01-VHDL13_DWMG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4243
ber01-VHDL13_DWMG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4239
ber01-VHDL13_DWMG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:01 4498
ber01-VHDL13_DWMG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3491
ber01-VHDL13_DWMG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3879
ber01-VHDL13_DWMG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3882
ber01-VHDL13_DWMG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 4073
ber01-VHDL13_DWMO_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 3696
ber01-VHDL13_DWMO_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 3925
ber01-VHDL13_DWMO_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 3925
ber01-VHDL13_DWMO_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:01 3897
ber01-VHDL13_DWMO_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3058
ber01-VHDL13_DWMO_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3365
ber01-VHDL13_DWMO_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3357
ber01-VHDL13_DWMO_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 3685
ber01-VHDL13_DWMP_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:03 3984
ber01-VHDL13_DWMP_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4156
ber01-VHDL13_DWMP_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4156
ber01-VHDL13_DWMP_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:41:03 4346
ber01-VHDL13_DWMP_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 09:41:22 4350
ber01-VHDL13_DWMP_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:07 3401
ber01-VHDL13_DWMP_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:01 3947
ber01-VHDL13_DWMP_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:02 3939
ber01-VHDL13_DWMP_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:10 3891
ber01-VHDL13_DWOG_081700-2601081700-dsw--0-ia5 08-Jan-2026 19:00:01 7666
ber01-VHDL13_DWOG_090300-2601090300-dsw--0-ia5 09-Jan-2026 04:00:02 8827
ber01-VHDL13_DWOG_090300_COR-2601090300-dsw--0-ia5 09-Jan-2026 01:51:47 8828
ber01-VHDL13_DWOG_090800-2601090800-dsw--0-ia5 09-Jan-2026 14:19:01 8723
ber01-VHDL13_DWOG_091700-2601091700-dsw--0-ia5 09-Jan-2026 19:00:01 7163
ber01-VHDL13_DWOG_100300-2601100300-dsw--0-ia5 10-Jan-2026 04:00:07 7013
ber01-VHDL13_DWOG_100800-2601100800-dsw--0-ia5 10-Jan-2026 10:05:36 6159
ber01-VHDL13_DWOH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:15 5165
ber01-VHDL13_DWOH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:11 4786
ber01-VHDL13_DWOH_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:11 4753
ber01-VHDL13_DWOH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:16 4528
ber01-VHDL13_DWOH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:12 3549
ber01-VHDL13_DWOH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:17 3741
ber01-VHDL13_DWOH_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:17 3710
ber01-VHDL13_DWOH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:18 3841
ber01-VHDL13_DWOI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:28:12 5374
ber01-VHDL13_DWOI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:28:17 4733
ber01-VHDL13_DWOI_090400-2601090400-dsw--0-ia5 09-Jan-2026 05:58:16 4499
ber01-VHDL13_DWOI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:28:12 4894
ber01-VHDL13_DWOI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:28:12 4162
ber01-VHDL13_DWOI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:28:11 3653
ber01-VHDL13_DWOI_100400-2601100400-dsw--0-ia5 10-Jan-2026 05:58:17 3621
ber01-VHDL13_DWOI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:28:12 3660
ber01-VHDL13_DWON_082018-2601082018-dsw--0-ia5 08-Jan-2026 20:18:32 4512
ber01-VHDL13_DWON_082320-2601082320-dsw--0-ia5 08-Jan-2026 23:20:07 5395
ber01-VHDL13_DWON_090150-2601090150-dsw--0-ia5 09-Jan-2026 01:50:52 5360
ber01-VHDL13_DWON_090341-2601090341-dsw--0-ia5 09-Jan-2026 03:41:07 5360
ber01-VHDL13_DWON_090629-2601090629-dsw--0-ia5 09-Jan-2026 06:29:21 5022
ber01-VHDL13_DWON_090725-2601090725-dsw--0-ia5 09-Jan-2026 07:25:21 5341
ber01-VHDL13_DWON_091228-2601091228-dsw--0-ia5 09-Jan-2026 12:28:11 5326
ber01-VHDL13_DWON_091418-2601091418-dsw--0-ia5 09-Jan-2026 14:18:25 5334
ber01-VHDL13_DWON_091543-2601091543-dsw--0-ia5 09-Jan-2026 15:43:44 4430
ber01-VHDL13_DWON_091847-2601091847-dsw--0-ia5 09-Jan-2026 18:47:32 4430
ber01-VHDL13_DWON_091952-2601091952-dsw--0-ia5 09-Jan-2026 19:52:27 4516
ber01-VHDL13_DWON_092221-2601092221-dsw--0-ia5 09-Jan-2026 22:21:07 4516
ber01-VHDL13_DWON_092253-2601092253-dsw--0-ia5 09-Jan-2026 22:53:41 4550
ber01-VHDL13_DWON_100147-2601100147-dsw--0-ia5 10-Jan-2026 01:47:22 5043
ber01-VHDL13_DWON_100331-2601100331-dsw--0-ia5 10-Jan-2026 03:31:06 5043
ber01-VHDL13_DWON_100342-2601100342-dsw--0-ia5 10-Jan-2026 03:42:31 5043
ber01-VHDL13_DWON_100349-2601100349-dsw--0-ia5 10-Jan-2026 03:49:27 4916
ber01-VHDL13_DWON_100620-2601100620-dsw--0-ia5 10-Jan-2026 06:20:11 4595
ber01-VHDL13_DWON_100622-2601100622-dsw--0-ia5 10-Jan-2026 06:22:31 4595
ber01-VHDL13_DWON_100704-2601100704-dsw--0-ia5 10-Jan-2026 07:04:52 4595
ber01-VHDL13_DWON_100840-2601100840-dsw--0-ia5 10-Jan-2026 08:40:44 4595
ber01-VHDL13_DWON_100929-2601100929-dsw--0-ia5 10-Jan-2026 09:29:08 4595
ber01-VHDL13_DWON_101005-2601101005-dsw--0-ia5 10-Jan-2026 10:05:12 4709
ber01-VHDL13_DWON_101551-2601101551-dsw--0-ia5 10-Jan-2026 15:51:17 3655
ber01-VHDL13_DWON_101818-2601101818-dsw--0-ia5 10-Jan-2026 18:18:21 3664
ber01-VHDL13_DWPG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 2834
ber01-VHDL13_DWPG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 2905
ber01-VHDL13_DWPG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3144
ber01-VHDL13_DWPG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3573
ber01-VHDL13_DWPG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:39:25 3569
ber01-VHDL13_DWPG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 2878
ber01-VHDL13_DWPG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2621
ber01-VHDL13_DWPG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 2811
ber01-VHDL13_DWPG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 2725
ber01-VHDL13_DWPH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:01 3028
ber01-VHDL13_DWPH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:04 3214
ber01-VHDL13_DWPH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:01 3332
ber01-VHDL13_DWPH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 3444
ber01-VHDL13_DWPH_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:39:36 3503
ber01-VHDL13_DWPH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 3099
ber01-VHDL13_DWPH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:08 2904
ber01-VHDL13_DWPH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 3077
ber01-VHDL13_DWPH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 3330
ber01-VHDL13_DWSG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:30:07 3983
ber01-VHDL13_DWSG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:30:12 4119
ber01-VHDL13_DWSG_090200_COR-2601090200-dsw--0-ia5 09-Jan-2026 03:39:51 4251
ber01-VHDL13_DWSG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:07 4678
ber01-VHDL13_DWSG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:30:07 5085
ber01-VHDL13_DWSG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:30:01 4853
ber01-VHDL13_DWSG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:30:03 4824
ber01-VHDL13_DWSG_100200_COR-2601100200-dsw--0-ia5 10-Jan-2026 03:34:48 4659
ber01-VHDL13_DWSG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:06 4399
ber01-VHDL13_DWSG_100400_COR-2601100400-dsw--0-ia5 10-Jan-2026 07:24:00 4408
ber01-VHDL13_DWSG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:30:02 4481
ber01-VHDL17_DWOG_091200-2601091200-dsw--0-ia5 09-Jan-2026 12:05:36 3211
ber01-VHDL17_DWOG_101200-2601101200-dsw--0-ia5 10-Jan-2026 12:33:01 2641
swis2-VHDL20_DWEG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5763
swis2-VHDL20_DWEG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5334
swis2-VHDL20_DWEG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5250
swis2-VHDL20_DWEG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5354
swis2-VHDL20_DWEG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4157
swis2-VHDL20_DWEG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4299
swis2-VHDL20_DWEG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4099
swis2-VHDL20_DWEG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4674
swis2-VHDL20_DWEH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 6125
swis2-VHDL20_DWEH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5957
swis2-VHDL20_DWEH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5397
swis2-VHDL20_DWEH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5904
swis2-VHDL20_DWEH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4314
swis2-VHDL20_DWEH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4594
swis2-VHDL20_DWEH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4372
swis2-VHDL20_DWEH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4736
swis2-VHDL20_DWEI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5953
swis2-VHDL20_DWEI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 5157
swis2-VHDL20_DWEI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 5028
swis2-VHDL20_DWEI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5786
swis2-VHDL20_DWEI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 4814
swis2-VHDL20_DWEI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4246
swis2-VHDL20_DWEI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:06 4041
swis2-VHDL20_DWEI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4523
swis2-VHDL20_DWHG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 5120
swis2-VHDL20_DWHG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 5166
swis2-VHDL20_DWHG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:14 4931
swis2-VHDL20_DWHG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:06 5238
swis2-VHDL20_DWHG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 4578
swis2-VHDL20_DWHG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 5101
swis2-VHDL20_DWHG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:11 4758
swis2-VHDL20_DWHG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 5365
swis2-VHDL20_DWHH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:06 4699
swis2-VHDL20_DWHH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 4179
swis2-VHDL20_DWHH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:14 4201
swis2-VHDL20_DWHH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:06 4648
swis2-VHDL20_DWHH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 4656
swis2-VHDL20_DWHH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 4468
swis2-VHDL20_DWHH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:11 4191
swis2-VHDL20_DWHH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 5058
swis2-VHDL20_DWLG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3641
swis2-VHDL20_DWLG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3983
swis2-VHDL20_DWLG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3829
swis2-VHDL20_DWLG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4955
swis2-VHDL20_DWLG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3322
swis2-VHDL20_DWLG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3677
swis2-VHDL20_DWLG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3705
swis2-VHDL20_DWLG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3955
swis2-VHDL20_DWLH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3673
swis2-VHDL20_DWLH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3487
swis2-VHDL20_DWLH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3656
swis2-VHDL20_DWLH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4653
swis2-VHDL20_DWLH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3069
swis2-VHDL20_DWLH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3297
swis2-VHDL20_DWLH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3462
swis2-VHDL20_DWLH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3502
swis2-VHDL20_DWLI_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3668
swis2-VHDL20_DWLI_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3511
swis2-VHDL20_DWLI_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3504
swis2-VHDL20_DWLI_090400_COR-2601090400-dsw--0-ia5 09-Jan-2026 07:36:51 3822
swis2-VHDL20_DWLI_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4230
swis2-VHDL20_DWLI_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3158
swis2-VHDL20_DWLI_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3337
swis2-VHDL20_DWLI_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3416
swis2-VHDL20_DWLI_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3659
swis2-VHDL20_DWMG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4810
swis2-VHDL20_DWMG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4723
swis2-VHDL20_DWMG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4650
swis2-VHDL20_DWMG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5333
swis2-VHDL20_DWMG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:47:07 5350
swis2-VHDL20_DWMG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3904
swis2-VHDL20_DWMG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4374
swis2-VHDL20_DWMG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4295
swis2-VHDL20_DWMG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4800
swis2-VHDL20_DWMO_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4113
swis2-VHDL20_DWMO_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4411
swis2-VHDL20_DWMO_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4342
swis2-VHDL20_DWMO_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4700
swis2-VHDL20_DWMO_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:48:07 4695
swis2-VHDL20_DWMO_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3476
swis2-VHDL20_DWMO_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 3814
swis2-VHDL20_DWMO_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 3775
swis2-VHDL20_DWMO_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4466
swis2-VHDL20_DWMP_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4414
swis2-VHDL20_DWMP_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:07 4631
swis2-VHDL20_DWMP_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:06 4570
swis2-VHDL20_DWMP_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5158
swis2-VHDL20_DWMP_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:48:40 5175
swis2-VHDL20_DWMP_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:07 3804
swis2-VHDL20_DWMP_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:07 4442
swis2-VHDL20_DWMP_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4352
swis2-VHDL20_DWMP_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 4632
swis2-VHDL20_DWPG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3487
swis2-VHDL20_DWPG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3386
swis2-VHDL20_DWPG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3512
swis2-VHDL20_DWPG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 4091
swis2-VHDL20_DWPG_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:42:01 4087
swis2-VHDL20_DWPG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3396
swis2-VHDL20_DWPG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 2992
swis2-VHDL20_DWPG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3173
swis2-VHDL20_DWPG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3229
swis2-VHDL20_DWPH_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 3672
swis2-VHDL20_DWPH_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 3684
swis2-VHDL20_DWPH_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:00:11 3692
swis2-VHDL20_DWPH_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 3957
swis2-VHDL20_DWPH_090800_COR-2601090800-dsw--0-ia5 09-Jan-2026 13:42:01 4016
swis2-VHDL20_DWPH_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 3612
swis2-VHDL20_DWPH_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 3269
swis2-VHDL20_DWPH_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:00:15 3441
swis2-VHDL20_DWPH_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:02 3834
swis2-VHDL20_DWSG_081800-2601081800-dsw--0-ia5 08-Jan-2026 19:45:04 4382
swis2-VHDL20_DWSG_090200-2601090200-dsw--0-ia5 09-Jan-2026 03:45:01 4676
swis2-VHDL20_DWSG_090200_COR-2601090200-dsw--0-ia5 09-Jan-2026 03:39:51 4485
swis2-VHDL20_DWSG_090400-2601090400-dsw--0-ia5 09-Jan-2026 06:15:02 5076
swis2-VHDL20_DWSG_090800-2601090800-dsw--0-ia5 09-Jan-2026 09:45:02 5872
swis2-VHDL20_DWSG_091300-2601091300-dsw--0-ia5 09-Jan-2026 14:45:08 5659
swis2-VHDL20_DWSG_091800-2601091800-dsw--0-ia5 09-Jan-2026 19:45:03 5369
swis2-VHDL20_DWSG_100200-2601100200-dsw--0-ia5 10-Jan-2026 03:45:02 5161
swis2-VHDL20_DWSG_100200_COR-2601100200-dsw--0-ia5 10-Jan-2026 03:34:48 4893
swis2-VHDL20_DWSG_100400-2601100400-dsw--0-ia5 10-Jan-2026 06:15:02 4809
swis2-VHDL20_DWSG_100400_COR-2601100400-dsw--0-ia5 10-Jan-2026 07:24:00 4818
swis2-VHDL20_DWSG_100800-2601100800-dsw--0-ia5 10-Jan-2026 09:45:06 5141
swis2-VHDL20_DWSG_101300-2601101300-dsw--0-ia5 10-Jan-2026 14:45:06 4879
wst04-VHDL20_DWEG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 234967
wst04-VHDL20_DWEG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 235841
wst04-VHDL20_DWEG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 235362
wst04-VHDL20_DWEG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 235888
wst04-VHDL20_DWEG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:11 234062
wst04-VHDL20_DWEG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 234886
wst04-VHDL20_DWEG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 234415
wst04-VHDL20_DWEG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 234049
wst04-VHDL20_DWEH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 230813
wst04-VHDL20_DWEH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 231288
wst04-VHDL20_DWEH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 230795
wst04-VHDL20_DWEH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 232126
wst04-VHDL20_DWEH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:11 230228
wst04-VHDL20_DWEH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 230857
wst04-VHDL20_DWEH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 230353
wst04-VHDL20_DWEH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 228779
wst04-VHDL20_DWEI_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 328339
wst04-VHDL20_DWEI_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 328502
wst04-VHDL20_DWEI_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:27 327449
wst04-VHDL20_DWEI_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:26 326485
wst04-VHDL20_DWEI_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 324877
wst04-VHDL20_DWEI_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 324144
wst04-VHDL20_DWEI_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:27 323949
wst04-VHDL20_DWEI_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:22 322239
wst04-VHDL20_DWHG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 314075
wst04-VHDL20_DWHG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 314413
wst04-VHDL20_DWHG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:14 314082
wst04-VHDL20_DWHG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:22 314197
wst04-VHDL20_DWHG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 312567
wst04-VHDL20_DWHG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 313346
wst04-VHDL20_DWHG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:11 313049
wst04-VHDL20_DWHG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:18 313535
wst04-VHDL20_DWHH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:12 301286
wst04-VHDL20_DWHH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:11 300645
wst04-VHDL20_DWHH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:14 300601
wst04-VHDL20_DWHH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:16 301585
wst04-VHDL20_DWHH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 300512
wst04-VHDL20_DWHH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:11 300348
wst04-VHDL20_DWHH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:11 299518
wst04-VHDL20_DWHH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:18 302188
wst04-VHDL20_DWLG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 316972
wst04-VHDL20_DWLG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:27 317052
wst04-VHDL20_DWLG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 316557
wst04-VHDL20_DWLG_090400_COR-2601090400-omedes-..> 09-Jan-2026 07:32:46 317098
wst04-VHDL20_DWLG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 320387
wst04-VHDL20_DWLG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 318737
wst04-VHDL20_DWLG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 319200
wst04-VHDL20_DWLG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 319196
wst04-VHDL20_DWLG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 313984
wst04-VHDL20_DWLH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:26 315509
wst04-VHDL20_DWLH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 315073
wst04-VHDL20_DWLH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 314501
wst04-VHDL20_DWLH_090400_COR-2601090400-omedes-..> 09-Jan-2026 07:31:17 314452
wst04-VHDL20_DWLH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 311820
wst04-VHDL20_DWLH_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:21 310803
wst04-VHDL20_DWLH_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 311090
wst04-VHDL20_DWLH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 311212
wst04-VHDL20_DWLH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 307534
wst04-VHDL20_DWLI_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:26 318073
wst04-VHDL20_DWLI_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:27 317645
wst04-VHDL20_DWLI_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:41 317340
wst04-VHDL20_DWLI_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 314301
wst04-VHDL20_DWLI_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:27 313305
wst04-VHDL20_DWLI_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:26 313589
wst04-VHDL20_DWLI_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:41 313680
wst04-VHDL20_DWLI_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:32 312949
wst04-VHDL20_DWMG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:20 529448
wst04-VHDL20_DWMG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:17 528841
wst04-VHDL20_DWMG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 528714
wst04-VHDL20_DWMG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:18 535890
wst04-VHDL20_DWMG_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:45:26 535900
wst04-VHDL20_DWMG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 533424
wst04-VHDL20_DWMG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 533949
wst04-VHDL20_DWMG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:16 533907
wst04-VHDL20_DWMG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:16 526739
wst04-VHDL20_DWMO_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 429496
wst04-VHDL20_DWMO_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 429686
wst04-VHDL20_DWMO_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:17 430041
wst04-VHDL20_DWMO_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:12 430128
wst04-VHDL20_DWMO_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:45:56 430098
wst04-VHDL20_DWMO_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 428338
wst04-VHDL20_DWMO_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:17 428776
wst04-VHDL20_DWMO_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:16 429363
wst04-VHDL20_DWMO_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:12 424233
wst04-VHDL20_DWMP_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:16 544942
wst04-VHDL20_DWMP_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 544324
wst04-VHDL20_DWMP_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:15:21 546137
wst04-VHDL20_DWMP_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:18 551882
wst04-VHDL20_DWMP_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:46:27 551899
wst04-VHDL20_DWMP_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:17 549439
wst04-VHDL20_DWMP_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:22 549202
wst04-VHDL20_DWMP_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:15:21 550958
wst04-VHDL20_DWMP_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:16 542391
wst04-VHDL20_DWPG_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 311661
wst04-VHDL20_DWPG_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 311182
wst04-VHDL20_DWPG_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:32 311233
wst04-VHDL20_DWPG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:32 357626
wst04-VHDL20_DWPG_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:40:50 357018
wst04-VHDL20_DWPG_091800-2601091800-omedes--0.pdf 09-Jan-2026 19:45:27 311835
wst04-VHDL20_DWPG_100200-2601100200-omedes--0.pdf 10-Jan-2026 03:45:22 310976
wst04-VHDL20_DWPG_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:32 310897
wst04-VHDL20_DWPG_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:26 351951
wst04-VHDL20_DWPH_081800-2601081800-omedes--0.pdf 08-Jan-2026 19:45:22 267813
wst04-VHDL20_DWPH_090200-2601090200-omedes--0.pdf 09-Jan-2026 03:45:21 222722
wst04-VHDL20_DWPH_090400-2601090400-omedes--0.pdf 09-Jan-2026 06:00:32 222972
wst04-VHDL20_DWPH_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:26 269648
wst04-VHDL20_DWPH_090800_COR-2601090800-omedes-..> 09-Jan-2026 13:41:16 269710
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wst04-VHDL20_DWPH_100400-2601100400-omedes--0.pdf 10-Jan-2026 06:00:32 222343
wst04-VHDL20_DWPH_100800-2601100800-omedes--0.pdf 10-Jan-2026 09:45:26 269037
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wst04-VHDL20_DWSG_090800-2601090800-omedes--0.pdf 09-Jan-2026 09:45:12 341169
wst04-VHDL20_DWSG_091300-2601091300-omedes--0.pdf 09-Jan-2026 14:45:14 341228
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wst04-VHDL20_DWSG_100400_COR-2601100400-omedes-..> 10-Jan-2026 07:24:12 339904
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