Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Jun-2026 12:30:12 3432
FPDL13_DWMZ_260600 26-Jun-2026 13:30:15 16106
SXDL31_DWAV_250800 25-Jun-2026 09:20:19 8619
SXDL31_DWAV_251800 25-Jun-2026 15:51:44 7555
SXDL31_DWAV_260800 26-Jun-2026 08:36:37 12293
SXDL31_DWAV_261800 26-Jun-2026 16:25:34 8103
SXDL31_DWAV_LATEST 26-Jun-2026 16:25:34 8103
SXDL33_DWAV_250000 25-Jun-2026 10:09:14 7899
SXDL33_DWAV_260000 26-Jun-2026 10:27:29 8302
SXDL33_DWAV_LATEST 26-Jun-2026 10:27:29 8302
ber01-FWDL39_DWMS_251200-2606251200-dsw--0-ia5 25-Jun-2026 12:13:37 1982
ber01-FWDL39_DWMS_261200-2606261200-dsw--0-ia5 26-Jun-2026 12:04:27 1989
ber01-VHDL13_DWEG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:28:16 2515
ber01-VHDL13_DWEG_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:06:07 3268
ber01-VHDL13_DWEG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:28:18 3415
ber01-VHDL13_DWEH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:28:16 3099
ber01-VHDL13_DWEH_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:07:12 3335
ber01-VHDL13_DWEH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:28:18 3809
ber01-VHDL13_DWEI_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:28:12 3194
ber01-VHDL13_DWEI_250800_COR-2606250800-dsw--0-ia5 26-Jun-2026 05:07:58 3110
ber01-VHDL13_DWEI_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:28:18 3810
ber01-VHDL13_DWHG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 2757
ber01-VHDL13_DWHG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:07 3735
ber01-VHDL13_DWHH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 2413
ber01-VHDL13_DWHH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:07 3483
ber01-VHDL13_DWLG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 2425
ber01-VHDL13_DWLG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2602
ber01-VHDL13_DWLH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 2501
ber01-VHDL13_DWLH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2944
ber01-VHDL13_DWLI_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 2510
ber01-VHDL13_DWLI_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2933
ber01-VHDL13_DWMO_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 2582
ber01-VHDL13_DWMO_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2866
ber01-VHDL13_DWMP_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 2596
ber01-VHDL13_DWMP_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 3225
ber01-VHDL13_DWOG_250300-2606250300-dsw--0-ia5 25-Jun-2026 03:00:06 3626
ber01-VHDL13_DWOG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 3406
ber01-VHDL13_DWOG_251700-2606251700-dsw--0-ia5 25-Jun-2026 18:00:01 2758
ber01-VHDL13_DWOG_260300-2606260300-dsw--0-ia5 26-Jun-2026 03:00:03 3396
ber01-VHDL13_DWOG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 3509
ber01-VHDL13_DWOG_261700-2606261700-dsw--0-ia5 26-Jun-2026 18:00:01 4231
ber01-VHDL13_DWON_242144-2606242144-dsw--0-ia5 24-Jun-2026 21:45:03 2908
ber01-VHDL13_DWON_242359-2606242359-dsw--0-ia5 24-Jun-2026 23:59:27 3585
ber01-VHDL13_DWON_250126-2606250126-dsw--0-ia5 25-Jun-2026 01:26:52 3837
ber01-VHDL13_DWON_250132-2606250132-dsw--0-ia5 25-Jun-2026 01:32:42 3952
ber01-VHDL13_DWON_250237-2606250237-dsw--0-ia5 25-Jun-2026 02:37:18 3952
ber01-VHDL13_DWON_250513-2606250513-dsw--0-ia5 25-Jun-2026 05:13:50 4108
ber01-VHDL13_DWON_250557-2606250557-dsw--0-ia5 25-Jun-2026 05:58:02 3807
ber01-VHDL13_DWON_250625-2606250625-dsw--0-ia5 25-Jun-2026 06:26:03 3807
ber01-VHDL13_DWON_250817-2606250817-dsw--0-ia5 25-Jun-2026 08:18:01 3592
ber01-VHDL13_DWON_251503-2606251503-dsw--0-ia5 25-Jun-2026 15:03:06 3046
ber01-VHDL13_DWON_251751-2606251751-dsw--0-ia5 25-Jun-2026 17:51:17 3046
ber01-VHDL13_DWON_251825-2606251825-dsw--0-ia5 25-Jun-2026 18:25:38 3316
ber01-VHDL13_DWON_252208-2606252208-dsw--0-ia5 25-Jun-2026 22:08:17 3929
ber01-VHDL13_DWON_260002-2606260002-dsw--0-ia5 26-Jun-2026 00:02:56 3929
ber01-VHDL13_DWON_260127-2606260127-dsw--0-ia5 26-Jun-2026 01:27:22 3413
ber01-VHDL13_DWON_260242-2606260242-dsw--0-ia5 26-Jun-2026 02:42:46 3413
ber01-VHDL13_DWON_260524-2606260524-dsw--0-ia5 26-Jun-2026 05:24:56 3795
ber01-VHDL13_DWON_260626-2606260626-dsw--0-ia5 26-Jun-2026 06:26:17 3792
ber01-VHDL13_DWON_260948-2606260948-dsw--0-ia5 26-Jun-2026 09:48:26 3792
ber01-VHDL13_DWON_261500-2606261500-dsw--0-ia5 26-Jun-2026 15:01:01 4175
ber01-VHDL13_DWON_261732-2606261732-dsw--0-ia5 26-Jun-2026 17:32:58 3925
ber01-VHDL13_DWPG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 2523
ber01-VHDL13_DWPG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2920
ber01-VHDL13_DWPH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 2685
ber01-VHDL13_DWPH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 3080
ber01-VHDL13_DWSG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 3269
ber01-VHDL13_DWSG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 4063
ber01-VHDL13_DWSG_260800_COR-2606260800-dsw--0-ia5 26-Jun-2026 16:28:31 4172
ber01-VHDL17_DWOG_251200-2606251200-dsw--0-ia5 25-Jun-2026 11:33:01 2912
ber01-VHDL17_DWOG_261200-2606261200-dsw--0-ia5 26-Jun-2026 11:25:16 3224
swis2-VHDL20_DWEG_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:03 664
swis2-VHDL20_DWEG_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:01:20 662
swis2-VHDL20_DWEG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 916
swis2-VHDL20_DWEG_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 1850
swis2-VHDL20_DWEG_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:04 1381
swis2-VHDL20_DWEG_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:01:21 1297
swis2-VHDL20_DWEG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:07 1714
swis2-VHDL20_DWEG_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:07 2421
swis2-VHDL20_DWEH_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:03 1183
swis2-VHDL20_DWEH_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:01:20 1180
swis2-VHDL20_DWEH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 1454
swis2-VHDL20_DWEH_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 1743
swis2-VHDL20_DWEH_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:04 1389
swis2-VHDL20_DWEH_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:01:21 1381
swis2-VHDL20_DWEH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:07 2089
swis2-VHDL20_DWEH_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:07 2573
swis2-VHDL20_DWEI_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:03 1177
swis2-VHDL20_DWEI_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:01:20 1174
swis2-VHDL20_DWEI_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 1462
swis2-VHDL20_DWEI_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 1981
swis2-VHDL20_DWEI_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:04 1414
swis2-VHDL20_DWEI_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:01:21 1313
swis2-VHDL20_DWEI_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:07 2132
swis2-VHDL20_DWEI_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:07 2801
swis2-VHDL20_DWHG_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:45:50 1304
swis2-VHDL20_DWHG_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:20 1301
swis2-VHDL20_DWHG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:45:28 1283
swis2-VHDL20_DWHG_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:45:08 1575
swis2-VHDL20_DWHG_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:47:47 1332
swis2-VHDL20_DWHG_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:17 1352
swis2-VHDL20_DWHG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:45:01 2103
swis2-VHDL20_DWHG_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:45:07 1865
swis2-VHDL20_DWHH_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:45:50 1307
swis2-VHDL20_DWHH_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:20 1307
swis2-VHDL20_DWHH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:45:28 1059
swis2-VHDL20_DWHH_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:45:08 1461
swis2-VHDL20_DWHH_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:47:47 1280
swis2-VHDL20_DWHH_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:17 1299
swis2-VHDL20_DWHH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:45:01 1852
swis2-VHDL20_DWHH_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:45:07 1651
swis2-VHDL20_DWLG_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:21 1067
swis2-VHDL20_DWLG_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:10 1181
swis2-VHDL20_DWLG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:22 1578
swis2-VHDL20_DWLG_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:31:04 1593
swis2-VHDL20_DWLG_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:24 1124
swis2-VHDL20_DWLG_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:11 1124
swis2-VHDL20_DWLG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:23 1542
swis2-VHDL20_DWLG_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:31:01 1446
swis2-VHDL20_DWLH_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:21 1036
swis2-VHDL20_DWLH_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:10 1188
swis2-VHDL20_DWLH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:22 1532
swis2-VHDL20_DWLH_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:31:04 1810
swis2-VHDL20_DWLH_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:24 1381
swis2-VHDL20_DWLH_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:11 1386
swis2-VHDL20_DWLH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:23 1842
swis2-VHDL20_DWLH_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:31:01 1630
swis2-VHDL20_DWLI_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:21 1031
swis2-VHDL20_DWLI_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:10 1183
swis2-VHDL20_DWLI_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:22 1527
swis2-VHDL20_DWLI_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:31:04 1809
swis2-VHDL20_DWLI_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:24 1360
swis2-VHDL20_DWLI_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:11 1365
swis2-VHDL20_DWLI_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:23 1725
swis2-VHDL20_DWLI_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:31:01 1683
swis2-VHDL20_DWMO_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:08 1003
swis2-VHDL20_DWMO_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:02 1003
swis2-VHDL20_DWMO_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 1244
swis2-VHDL20_DWMO_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 1360
swis2-VHDL20_DWMO_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:09 1083
swis2-VHDL20_DWMO_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:07 1091
swis2-VHDL20_DWMO_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 1409
swis2-VHDL20_DWMO_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:01 1731
swis2-VHDL20_DWMP_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:08 983
swis2-VHDL20_DWMP_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:02 982
swis2-VHDL20_DWMP_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:09 1407
swis2-VHDL20_DWMP_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 1520
swis2-VHDL20_DWMP_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:09 1299
swis2-VHDL20_DWMP_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:07 1306
swis2-VHDL20_DWMP_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 1715
swis2-VHDL20_DWMP_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:01 1940
swis2-VHDL20_DWPG_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:21 1085
swis2-VHDL20_DWPG_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:10 1199
swis2-VHDL20_DWPG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:22 1601
swis2-VHDL20_DWPG_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:31:04 1827
swis2-VHDL20_DWPG_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:24 1376
swis2-VHDL20_DWPG_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:11 1381
swis2-VHDL20_DWPG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:23 1845
swis2-VHDL20_DWPG_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:31:01 1612
swis2-VHDL20_DWPH_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:21 1050
swis2-VHDL20_DWPH_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:10 1249
swis2-VHDL20_DWPH_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:22 1646
swis2-VHDL20_DWPH_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:31:04 1876
swis2-VHDL20_DWPH_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:24 1425
swis2-VHDL20_DWPH_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:11 1430
swis2-VHDL20_DWPH_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:23 1825
swis2-VHDL20_DWPH_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:31:01 1698
swis2-VHDL20_DWSG_250200-2606250200-dsw--0-ia5 25-Jun-2026 02:30:03 1101
swis2-VHDL20_DWSG_250400-2606250400-dsw--0-ia5 25-Jun-2026 05:00:20 1100
swis2-VHDL20_DWSG_250800-2606250800-dsw--0-ia5 25-Jun-2026 08:30:04 1474
swis2-VHDL20_DWSG_251800-2606251800-dsw--0-ia5 25-Jun-2026 18:30:06 2128
swis2-VHDL20_DWSG_260200-2606260200-dsw--0-ia5 26-Jun-2026 02:30:04 1617
swis2-VHDL20_DWSG_260400-2606260400-dsw--0-ia5 26-Jun-2026 05:00:17 1624
swis2-VHDL20_DWSG_260800-2606260800-dsw--0-ia5 26-Jun-2026 08:30:01 2096
swis2-VHDL20_DWSG_260800_COR-2606260800-dsw--0-ia5 26-Jun-2026 16:28:31 2312
swis2-VHDL20_DWSG_261800-2606261800-dsw--0-ia5 26-Jun-2026 18:30:01 2474
swis2-VHDL20_DWSG_261800_COR-2606261800-dsw--0-ia5 26-Jun-2026 19:57:07 2507
wst04-VHDL20_DWEG_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:12 235209
wst04-VHDL20_DWEG_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:10 234647
wst04-VHDL20_DWEG_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:14 235929
wst04-VHDL20_DWEG_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:11 241378
wst04-VHDL20_DWEG_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:14 240363
wst04-VHDL20_DWEG_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:11 240243
wst04-VHDL20_DWEG_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:12 241076
wst04-VHDL20_DWEG_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:30:12 244315
wst04-VHDL20_DWEG_261800_COR-2606261800-omedes-..> 26-Jun-2026 19:03:52 244331
wst04-VHDL20_DWEH_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:12 239011
wst04-VHDL20_DWEH_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:10 238460
wst04-VHDL20_DWEH_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:14 239333
wst04-VHDL20_DWEH_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:11 239915
wst04-VHDL20_DWEH_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:14 239584
wst04-VHDL20_DWEH_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:11 239342
wst04-VHDL20_DWEH_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:12 241354
wst04-VHDL20_DWEH_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:30:11 243808
wst04-VHDL20_DWEH_261800_COR-2606261800-omedes-..> 26-Jun-2026 19:05:06 243832
wst04-VHDL20_DWEI_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:12 336571
wst04-VHDL20_DWEI_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:10 335970
wst04-VHDL20_DWEI_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:22 337033
wst04-VHDL20_DWEI_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:17 344941
wst04-VHDL20_DWEI_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:14 343327
wst04-VHDL20_DWEI_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:11 343058
wst04-VHDL20_DWEI_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:17 344855
wst04-VHDL20_DWEI_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:30:15 348400
wst04-VHDL20_DWEI_261800_COR-2606261800-omedes-..> 26-Jun-2026 19:06:42 348419
wst04-VHDL20_DWHG_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:45:50 343783
wst04-VHDL20_DWHG_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:20 343543
wst04-VHDL20_DWHG_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:45:28 343881
wst04-VHDL20_DWHG_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:45:16 341693
wst04-VHDL20_DWHG_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:47:47 341055
wst04-VHDL20_DWHG_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:17 341055
wst04-VHDL20_DWHG_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:45:12 343873
wst04-VHDL20_DWHG_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:45:14 349364
wst04-VHDL20_DWHH_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:45:50 328340
wst04-VHDL20_DWHH_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:20 225656
wst04-VHDL20_DWHH_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:45:28 327677
wst04-VHDL20_DWHH_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:45:16 331295
wst04-VHDL20_DWHH_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:47:47 330874
wst04-VHDL20_DWHH_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:17 228444
wst04-VHDL20_DWHH_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:45:12 332740
wst04-VHDL20_DWHH_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:45:14 330368
wst04-VHDL20_DWLG_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:21 332905
wst04-VHDL20_DWLG_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:49 332843
wst04-VHDL20_DWLG_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:52 333295
wst04-VHDL20_DWLG_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:31:22 337532
wst04-VHDL20_DWLG_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:28 336888
wst04-VHDL20_DWLG_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:42 336753
wst04-VHDL20_DWLG_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:42 338471
wst04-VHDL20_DWLG_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:31:24 336724
wst04-VHDL20_DWLH_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:27 334767
wst04-VHDL20_DWLH_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:49 334726
wst04-VHDL20_DWLH_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:41 335116
wst04-VHDL20_DWLH_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:31:22 338340
wst04-VHDL20_DWLH_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:24 337306
wst04-VHDL20_DWLH_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:42 337140
wst04-VHDL20_DWLH_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:42 338474
wst04-VHDL20_DWLH_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:31:24 340897
wst04-VHDL20_DWLI_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:21 339584
wst04-VHDL20_DWLI_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:49 339485
wst04-VHDL20_DWLI_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:41 384488
wst04-VHDL20_DWLI_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:31:22 344436
wst04-VHDL20_DWLI_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:24 343371
wst04-VHDL20_DWLI_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:42 343199
wst04-VHDL20_DWLI_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:42 389065
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wst04-VHDL20_DWMO_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:17 455120
wst04-VHDL20_DWMO_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:20 455007
wst04-VHDL20_DWMO_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:22 455380
wst04-VHDL20_DWMO_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:17 353434
wst04-VHDL20_DWMO_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:19 461773
wst04-VHDL20_DWMO_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:17 461674
wst04-VHDL20_DWMO_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:17 462047
wst04-VHDL20_DWMO_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:30:17 351894
wst04-VHDL20_DWMP_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:17 556263
wst04-VHDL20_DWMP_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:20 556233
wst04-VHDL20_DWMP_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:22 454073
wst04-VHDL20_DWMP_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:17 460212
wst04-VHDL20_DWMP_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:19 560422
wst04-VHDL20_DWMP_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:17 560372
wst04-VHDL20_DWMP_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:23 460363
wst04-VHDL20_DWMP_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:30:17 463768
wst04-VHDL20_DWPG_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:21 240683
wst04-VHDL20_DWPG_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:32 340489
wst04-VHDL20_DWPG_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:41 385442
wst04-VHDL20_DWPG_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:31:27 351340
wst04-VHDL20_DWPG_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:24 244919
wst04-VHDL20_DWPG_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:30 350157
wst04-VHDL20_DWPG_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:46 396372
wst04-VHDL20_DWPG_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:31:26 349186
wst04-VHDL20_DWPH_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:21 239243
wst04-VHDL20_DWPH_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:32 239811
wst04-VHDL20_DWPH_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:41 240146
wst04-VHDL20_DWPH_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:31:22 239047
wst04-VHDL20_DWPH_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:24 238764
wst04-VHDL20_DWPH_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:30 238611
wst04-VHDL20_DWPH_260800-2606260800-omedes--0.pdf 26-Jun-2026 08:30:42 239447
wst04-VHDL20_DWPH_261800-2606261800-omedes--0.pdf 26-Jun-2026 18:31:24 243910
wst04-VHDL20_DWSG_250200-2606250200-omedes--0.pdf 25-Jun-2026 02:30:12 335882
wst04-VHDL20_DWSG_250400-2606250400-omedes--0.pdf 25-Jun-2026 05:00:20 335900
wst04-VHDL20_DWSG_250800-2606250800-omedes--0.pdf 25-Jun-2026 08:30:22 336726
wst04-VHDL20_DWSG_251800-2606251800-omedes--0.pdf 25-Jun-2026 18:30:11 348272
wst04-VHDL20_DWSG_260200-2606260200-omedes--0.pdf 26-Jun-2026 02:30:14 346964
wst04-VHDL20_DWSG_260400-2606260400-omedes--0.pdf 26-Jun-2026 05:00:11 347080
wst04-VHDL20_DWSG_260800-2606260800-omedes--0.pdf 26-Jun-2026 16:28:36 348051
wst04-VHDL20_DWSG_261800-2606261800-omedes--0.pdf 26-Jun-2026 19:57:11 348503