Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_090600 09-Oct-2026 13:52:44 5703
FPDL13_DWMZ_100600 10-Oct-2026 12:50:38 21815
SXDL31_DWAV_081800 08-Oct-2026 16:07:37 7707
SXDL31_DWAV_090800 09-Oct-2026 07:37:02 18022
SXDL31_DWAV_091800 09-Oct-2026 16:48:33 10496
SXDL31_DWAV_100800 10-Oct-2026 07:47:05 8116
SXDL31_DWAV_LATEST 10-Oct-2026 07:47:05 8116
SXDL33_DWAV_090000 09-Oct-2026 09:29:15 6114
SXDL33_DWAV_100000 10-Oct-2026 09:50:20 11034
SXDL33_DWAV_LATEST 10-Oct-2026 09:50:20 11034
ber01-FWDL39_DWMS_091200-2610091200-dsw--0-ia5 09-Oct-2026 12:23:09 2308
ber01-FWDL39_DWMS_101200-2610101200-dsw--0-ia5 10-Oct-2026 11:13:48 1556
ber01-VHDL13_DWEG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:28:23 2880
ber01-VHDL13_DWEG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:28:18 2779
ber01-VHDL13_DWEG_100800_COR-2610100800-dsw--0-ia5 10-Oct-2026 09:50:34 2783
ber01-VHDL13_DWEH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:28:17 3623
ber01-VHDL13_DWEH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:28:24 3300
ber01-VHDL13_DWEI_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:28:17 3039
ber01-VHDL13_DWEI_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:28:18 2505
ber01-VHDL13_DWHG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 3535
ber01-VHDL13_DWHG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 3884
ber01-VHDL13_DWHH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 3629
ber01-VHDL13_DWHH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 4098
ber01-VHDL13_DWLG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:02 3162
ber01-VHDL13_DWLG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 3063
ber01-VHDL13_DWLH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:02 3110
ber01-VHDL13_DWLH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 3109
ber01-VHDL13_DWLI_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:02 3045
ber01-VHDL13_DWLI_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 2713
ber01-VHDL13_DWMO_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 3172
ber01-VHDL13_DWMO_090800_COR-2610090800-dsw--0-ia5 09-Oct-2026 08:37:39 3176
ber01-VHDL13_DWMO_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 3516
ber01-VHDL13_DWMP_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 3373
ber01-VHDL13_DWMP_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 4098
ber01-VHDL13_DWOG_080800_COR-2610080800-dsw--0-ia5 08-Oct-2026 15:15:30 5624
ber01-VHDL13_DWOG_081700-2610081700-dsw--0-ia5 08-Oct-2026 18:00:05 5981
ber01-VHDL13_DWOG_081700_COR-2610081700-dsw--0-ia5 08-Oct-2026 16:29:34 5985
ber01-VHDL13_DWOG_090300-2610090300-dsw--0-ia5 09-Oct-2026 03:00:07 5390
ber01-VHDL13_DWOG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:07 5456
ber01-VHDL13_DWOG_091700-2610091700-dsw--0-ia5 09-Oct-2026 18:00:03 5087
ber01-VHDL13_DWOG_100300-2610100300-dsw--0-ia5 10-Oct-2026 03:02:33 5033
ber01-VHDL13_DWOG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 4608
ber01-VHDL13_DWON_081310-2610081310-dsw--0-ia5 08-Oct-2026 13:10:20 4179
ber01-VHDL13_DWON_081446-2610081446-dsw--0-ia5 08-Oct-2026 14:46:50 3860
ber01-VHDL13_DWON_081515-2610081515-dsw--0-ia5 08-Oct-2026 15:15:14 3860
ber01-VHDL13_DWON_081629-2610081629-dsw--0-ia5 08-Oct-2026 16:29:18 4888
ber01-VHDL13_DWON_082033-2610082033-dsw--0-ia5 08-Oct-2026 20:34:05 4527
ber01-VHDL13_DWON_090054-2610090054-dsw--0-ia5 09-Oct-2026 00:55:07 5013
ber01-VHDL13_DWON_090250-2610090250-dsw--0-ia5 09-Oct-2026 02:52:43 4225
ber01-VHDL13_DWON_090443-2610090443-dsw--0-ia5 09-Oct-2026 04:43:13 4351
ber01-VHDL13_DWON_090519-2610090519-dsw--0-ia5 09-Oct-2026 05:19:55 4439
ber01-VHDL13_DWON_090521-2610090521-dsw--0-ia5 09-Oct-2026 05:21:58 4677
ber01-VHDL13_DWON_090804-2610090804-dsw--0-ia5 09-Oct-2026 08:04:49 4677
ber01-VHDL13_DWON_091431-2610091431-dsw--0-ia5 09-Oct-2026 14:31:12 4064
ber01-VHDL13_DWON_091719-2610091719-dsw--0-ia5 09-Oct-2026 17:19:14 3708
ber01-VHDL13_DWON_091938-2610091938-dsw--0-ia5 09-Oct-2026 19:38:21 3619
ber01-VHDL13_DWON_100142-2610100142-dsw--0-ia5 10-Oct-2026 01:42:32 3608
ber01-VHDL13_DWON_100237-2610100237-dsw--0-ia5 10-Oct-2026 02:38:08 3800
ber01-VHDL13_DWON_100526-2610100526-dsw--0-ia5 10-Oct-2026 05:26:48 4286
ber01-VHDL13_DWON_100622-2610100622-dsw--0-ia5 10-Oct-2026 06:22:28 4286
ber01-VHDL13_DWON_100746-2610100746-dsw--0-ia5 10-Oct-2026 07:46:50 4370
ber01-VHDL13_DWON_101221-2610101221-dsw--0-ia5 10-Oct-2026 12:21:29 4155
ber01-VHDL13_DWPG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:02 2334
ber01-VHDL13_DWPG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 2760
ber01-VHDL13_DWPH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:02 3330
ber01-VHDL13_DWPH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 3373
ber01-VHDL13_DWSG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 3086
ber01-VHDL13_DWSG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 3221
ber01-VHDL17_DWOG_091200-2610091200-dsw--0-ia5 09-Oct-2026 10:50:03 3259
ber01-VHDL17_DWOG_101200-2610101200-dsw--0-ia5 10-Oct-2026 11:11:08 3090
swis2-VHDL20_DWEG_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:05 1523
swis2-VHDL20_DWEG_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:04 1051
swis2-VHDL20_DWEG_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:01:18 1122
swis2-VHDL20_DWEG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:07 1501
swis2-VHDL20_DWEG_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:12 1486
swis2-VHDL20_DWEG_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 1238
swis2-VHDL20_DWEG_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:01:17 1129
swis2-VHDL20_DWEG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 1290
swis2-VHDL20_DWEH_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:05 1948
swis2-VHDL20_DWEH_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:04 1487
swis2-VHDL20_DWEH_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:01:18 1571
swis2-VHDL20_DWEH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:07 2001
swis2-VHDL20_DWEH_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:12 2127
swis2-VHDL20_DWEH_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 1496
swis2-VHDL20_DWEH_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:01:17 1494
swis2-VHDL20_DWEH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 1656
swis2-VHDL20_DWEI_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:05 1408
swis2-VHDL20_DWEI_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:04 1062
swis2-VHDL20_DWEI_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:01:18 1323
swis2-VHDL20_DWEI_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:07 1564
swis2-VHDL20_DWEI_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:12 1528
swis2-VHDL20_DWEI_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 923
swis2-VHDL20_DWEI_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:01:17 896
swis2-VHDL20_DWEI_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:10 1057
swis2-VHDL20_DWHG_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:45:12 1861
swis2-VHDL20_DWHG_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:46:50 1482
swis2-VHDL20_DWHG_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:19 1480
swis2-VHDL20_DWHG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:47:27 1956
swis2-VHDL20_DWHG_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:45:17 2455
swis2-VHDL20_DWHG_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:45:59 2178
swis2-VHDL20_DWHG_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:19 2175
swis2-VHDL20_DWHG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:45:46 2262
swis2-VHDL20_DWHH_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:45:12 1727
swis2-VHDL20_DWHH_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:46:50 1490
swis2-VHDL20_DWHH_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:19 1491
swis2-VHDL20_DWHH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:47:27 1944
swis2-VHDL20_DWHH_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:45:17 2201
swis2-VHDL20_DWHH_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:45:59 1872
swis2-VHDL20_DWHH_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:19 1872
swis2-VHDL20_DWHH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:45:46 2218
swis2-VHDL20_DWLG_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:31:07 1215
swis2-VHDL20_DWLG_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:34 1076
swis2-VHDL20_DWLG_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 1093
swis2-VHDL20_DWLG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:35 1294
swis2-VHDL20_DWLG_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:31:07 1015
swis2-VHDL20_DWLG_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:38 897
swis2-VHDL20_DWLG_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:13 1040
swis2-VHDL20_DWLG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:28 1375
swis2-VHDL20_DWLH_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:31:07 1421
swis2-VHDL20_DWLH_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:34 1285
swis2-VHDL20_DWLH_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 1321
swis2-VHDL20_DWLH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:35 1653
swis2-VHDL20_DWLH_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:31:07 1170
swis2-VHDL20_DWLH_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:38 903
swis2-VHDL20_DWLH_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:13 1280
swis2-VHDL20_DWLH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:28 1605
swis2-VHDL20_DWLI_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:31:07 968
swis2-VHDL20_DWLI_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:34 914
swis2-VHDL20_DWLI_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 1105
swis2-VHDL20_DWLI_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:35 1290
swis2-VHDL20_DWLI_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:31:07 987
swis2-VHDL20_DWLI_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:38 870
swis2-VHDL20_DWLI_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:13 1057
swis2-VHDL20_DWLI_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:28 1262
swis2-VHDL20_DWMO_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:05 1475
swis2-VHDL20_DWMO_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:04 1307
swis2-VHDL20_DWMO_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:03 1313
swis2-VHDL20_DWMO_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 1413
swis2-VHDL20_DWMO_090800_COR-2610090800-dsw--0-ia5 09-Oct-2026 08:37:39 1725
swis2-VHDL20_DWMO_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:03 1540
swis2-VHDL20_DWMO_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 1368
swis2-VHDL20_DWMO_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:03 1635
swis2-VHDL20_DWMO_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 1737
swis2-VHDL20_DWMP_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:05 2019
swis2-VHDL20_DWMP_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:15 1625
swis2-VHDL20_DWMP_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:03 1265
swis2-VHDL20_DWMP_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 1555
swis2-VHDL20_DWMP_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:03 1688
swis2-VHDL20_DWMP_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 1464
swis2-VHDL20_DWMP_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:03 1741
swis2-VHDL20_DWMP_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 2151
swis2-VHDL20_DWPG_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:31:07 906
swis2-VHDL20_DWPG_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:34 774
swis2-VHDL20_DWPG_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 900
swis2-VHDL20_DWPG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:35 1111
swis2-VHDL20_DWPG_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:31:07 920
swis2-VHDL20_DWPG_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:38 798
swis2-VHDL20_DWPG_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:13 1064
swis2-VHDL20_DWPG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:28 1271
swis2-VHDL20_DWPH_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:31:07 1229
swis2-VHDL20_DWPH_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:34 1093
swis2-VHDL20_DWPH_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 1386
swis2-VHDL20_DWPH_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:35 1729
swis2-VHDL20_DWPH_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:31:07 1126
swis2-VHDL20_DWPH_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:38 1023
swis2-VHDL20_DWPH_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:13 1201
swis2-VHDL20_DWPH_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:28 1570
swis2-VHDL20_DWSG_081800-2610081800-dsw--0-ia5 08-Oct-2026 18:30:03 1201
swis2-VHDL20_DWSG_090200-2610090200-dsw--0-ia5 09-Oct-2026 02:30:15 1217
swis2-VHDL20_DWSG_090400-2610090400-dsw--0-ia5 09-Oct-2026 05:00:13 1234
swis2-VHDL20_DWSG_090800-2610090800-dsw--0-ia5 09-Oct-2026 08:30:10 1289
swis2-VHDL20_DWSG_091800-2610091800-dsw--0-ia5 09-Oct-2026 18:30:03 1059
swis2-VHDL20_DWSG_100200-2610100200-dsw--0-ia5 10-Oct-2026 02:30:04 916
swis2-VHDL20_DWSG_100400-2610100400-dsw--0-ia5 10-Oct-2026 05:00:19 1742
swis2-VHDL20_DWSG_100800-2610100800-dsw--0-ia5 10-Oct-2026 08:30:14 1425
wst04-VHDL20_DWEG_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:31 241897
wst04-VHDL20_DWEG_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:24 240206
wst04-VHDL20_DWEG_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:13 239381
wst04-VHDL20_DWEG_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:16 240939
wst04-VHDL20_DWEG_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:24 244114
wst04-VHDL20_DWEG_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:15 243105
wst04-VHDL20_DWEG_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:13 242311
wst04-VHDL20_DWEG_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:14 243319
wst04-VHDL20_DWEH_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:31 243137
wst04-VHDL20_DWEH_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:24 242403
wst04-VHDL20_DWEH_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:13 241516
wst04-VHDL20_DWEH_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:16 242819
wst04-VHDL20_DWEH_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:14 242592
wst04-VHDL20_DWEH_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:15 241174
wst04-VHDL20_DWEH_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:13 240754
wst04-VHDL20_DWEH_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:14 241825
wst04-VHDL20_DWEI_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:31 344274
wst04-VHDL20_DWEI_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:24 343009
wst04-VHDL20_DWEI_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:13 343002
wst04-VHDL20_DWEI_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:26 344232
wst04-VHDL20_DWEI_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:24 349265
wst04-VHDL20_DWEI_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:20 347148
wst04-VHDL20_DWEI_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:19 346375
wst04-VHDL20_DWEI_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:21 346924
wst04-VHDL20_DWHG_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:45:14 342681
wst04-VHDL20_DWHG_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:46:50 341203
wst04-VHDL20_DWHG_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:23 340979
wst04-VHDL20_DWHG_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:47:27 342728
wst04-VHDL20_DWHG_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:45:27 348515
wst04-VHDL20_DWHG_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:45:59 347176
wst04-VHDL20_DWHG_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:19 347201
wst04-VHDL20_DWHG_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:45:46 348556
wst04-VHDL20_DWHH_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:45:14 340343
wst04-VHDL20_DWHH_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:46:50 339509
wst04-VHDL20_DWHH_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:19 236370
wst04-VHDL20_DWHH_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:47:27 340561
wst04-VHDL20_DWHH_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:45:27 339601
wst04-VHDL20_DWHH_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:45:59 338313
wst04-VHDL20_DWHH_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:19 235779
wst04-VHDL20_DWHH_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:45:47 339371
wst04-VHDL20_DWLG_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:31:28 337606
wst04-VHDL20_DWLG_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 337694
wst04-VHDL20_DWLG_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:44 337144
wst04-VHDL20_DWLG_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:55 337895
wst04-VHDL20_DWLG_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:31:23 328733
wst04-VHDL20_DWLG_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:38 328622
wst04-VHDL20_DWLG_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:43 328735
wst04-VHDL20_DWLG_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:44 329193
wst04-VHDL20_DWLH_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:31:28 331577
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wst04-VHDL20_DWLH_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:44 331164
wst04-VHDL20_DWLH_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:55 332458
wst04-VHDL20_DWLH_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:31:28 337393
wst04-VHDL20_DWLH_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:38 337303
wst04-VHDL20_DWLH_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:43 337130
wst04-VHDL20_DWLH_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:44 338447
wst04-VHDL20_DWLI_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:31:28 336497
wst04-VHDL20_DWLI_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:36 336478
wst04-VHDL20_DWLI_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:44 336347
wst04-VHDL20_DWLI_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:31:04 381623
wst04-VHDL20_DWLI_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:31:28 336561
wst04-VHDL20_DWLI_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:42 336120
wst04-VHDL20_DWLI_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:43 336254
wst04-VHDL20_DWLI_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:53 381285
wst04-VHDL20_DWMO_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:31 353327
wst04-VHDL20_DWMO_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 458179
wst04-VHDL20_DWMO_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:19 458029
wst04-VHDL20_DWMO_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:35 458222
wst04-VHDL20_DWMO_090800_COR-2610090800-omedes-..> 09-Oct-2026 08:37:49 459253
wst04-VHDL20_DWMO_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:24 350297
wst04-VHDL20_DWMO_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:15 455502
wst04-VHDL20_DWMO_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:13 455745
wst04-VHDL20_DWMO_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:28 455700
wst04-VHDL20_DWMP_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:31 470032
wst04-VHDL20_DWMP_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 572342
wst04-VHDL20_DWMP_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:19 570525
wst04-VHDL20_DWMP_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:35 468871
wst04-VHDL20_DWMP_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:35 461111
wst04-VHDL20_DWMP_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:20 560663
wst04-VHDL20_DWMP_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:19 560729
wst04-VHDL20_DWMP_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:28 461651
wst04-VHDL20_DWPG_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:31:28 349116
wst04-VHDL20_DWPG_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 243124
wst04-VHDL20_DWPG_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:33 348722
wst04-VHDL20_DWPG_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:31:04 394008
wst04-VHDL20_DWPG_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:31:23 343984
wst04-VHDL20_DWPG_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:38 241177
wst04-VHDL20_DWPG_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:33 343758
wst04-VHDL20_DWPG_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:53 388722
wst04-VHDL20_DWPH_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:31:28 241194
wst04-VHDL20_DWPH_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 241079
wst04-VHDL20_DWPH_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:33 241304
wst04-VHDL20_DWPH_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:55 241643
wst04-VHDL20_DWPH_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:31:23 240692
wst04-VHDL20_DWPH_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:38 240235
wst04-VHDL20_DWPH_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:33 240155
wst04-VHDL20_DWPH_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:44 240832
wst04-VHDL20_DWSG_081800-2610081800-omedes--0.pdf 08-Oct-2026 18:30:25 353915
wst04-VHDL20_DWSG_090200-2610090200-omedes--0.pdf 09-Oct-2026 02:30:34 354131
wst04-VHDL20_DWSG_090400-2610090400-omedes--0.pdf 09-Oct-2026 05:00:13 353941
wst04-VHDL20_DWSG_090800-2610090800-omedes--0.pdf 09-Oct-2026 08:30:26 354420
wst04-VHDL20_DWSG_091800-2610091800-omedes--0.pdf 09-Oct-2026 18:30:24 352335
wst04-VHDL20_DWSG_100200-2610100200-omedes--0.pdf 10-Oct-2026 02:30:15 352698
wst04-VHDL20_DWSG_100400-2610100400-omedes--0.pdf 10-Oct-2026 05:00:13 354635
wst04-VHDL20_DWSG_100800-2610100800-omedes--0.pdf 10-Oct-2026 08:30:21 353268