Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Apr-2026 12:32:14 3694
FPDL13_DWMZ_020600 02-Apr-2026 11:02:54 2468
SXDL31_DWAV_011800 01-Apr-2026 16:35:16 6418
SXDL31_DWAV_020800 02-Apr-2026 07:26:15 6567
SXDL31_DWAV_021800 02-Apr-2026 16:34:00 6157
SXDL31_DWAV_030800 03-Apr-2026 07:25:59 9453
SXDL31_DWAV_LATEST 03-Apr-2026 07:25:59 9453
SXDL33_DWAV_010000 01-Apr-2026 09:46:49 8420
SXDL33_DWAV_020000 02-Apr-2026 09:51:02 9767
SXDL33_DWAV_LATEST 02-Apr-2026 09:51:02 9767
ber01-FWDL39_DWMS_011230-2604011230-dsw--0-ia5 01-Apr-2026 12:06:16 1636
ber01-FWDL39_DWMS_021230-2604021230-dsw--0-ia5 02-Apr-2026 11:03:27 1122
ber01-VHDL13_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2644
ber01-VHDL13_DWEH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:11 2977
ber01-VHDL13_DWEH_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:12 3001
ber01-VHDL13_DWEH_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:44:57 2806
ber01-VHDL13_DWEH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:17 2745
ber01-VHDL13_DWEH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:11 2874
ber01-VHDL13_DWEH_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:13 2844
ber01-VHDL13_DWEH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:11 2947
ber01-VHDL13_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 3001
ber01-VHDL13_DWHG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:06 3315
ber01-VHDL13_DWHG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3131
ber01-VHDL13_DWHG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 3185
ber01-VHDL13_DWHG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2792
ber01-VHDL13_DWHG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:09 2900
ber01-VHDL13_DWHG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2927
ber01-VHDL13_DWHG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 3436
ber01-VHDL13_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 2997
ber01-VHDL13_DWHH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:06 3201
ber01-VHDL13_DWHH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3210
ber01-VHDL13_DWHH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 3348
ber01-VHDL13_DWHH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2779
ber01-VHDL13_DWHH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:09 2689
ber01-VHDL13_DWHH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2630
ber01-VHDL13_DWHH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2987
ber01-VHDL13_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2403
ber01-VHDL13_DWLG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2688
ber01-VHDL13_DWLG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2807
ber01-VHDL13_DWLG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2954
ber01-VHDL13_DWLG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 3306
ber01-VHDL13_DWLG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 3212
ber01-VHDL13_DWLG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 3387
ber01-VHDL13_DWLG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 3356
ber01-VHDL13_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2332
ber01-VHDL13_DWLH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2452
ber01-VHDL13_DWLH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2502
ber01-VHDL13_DWLH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2807
ber01-VHDL13_DWLH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 3474
ber01-VHDL13_DWLH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 3335
ber01-VHDL13_DWLH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 3352
ber01-VHDL13_DWLH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 3244
ber01-VHDL13_DWLI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2264
ber01-VHDL13_DWLI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2509
ber01-VHDL13_DWLI_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2560
ber01-VHDL13_DWLI_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2580
ber01-VHDL13_DWLI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2905
ber01-VHDL13_DWLI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2625
ber01-VHDL13_DWLI_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2772
ber01-VHDL13_DWLI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2854
ber01-VHDL13_DWMG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWMG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2833
ber01-VHDL13_DWMG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2905
ber01-VHDL13_DWMG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2671
ber01-VHDL13_DWMG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2559
ber01-VHDL13_DWMG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2592
ber01-VHDL13_DWMG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2373
ber01-VHDL13_DWMG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2475
ber01-VHDL13_DWMO_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2143
ber01-VHDL13_DWMO_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2553
ber01-VHDL13_DWMO_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2665
ber01-VHDL13_DWMO_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2424
ber01-VHDL13_DWMO_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2334
ber01-VHDL13_DWMO_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2473
ber01-VHDL13_DWMO_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2391
ber01-VHDL13_DWMO_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2476
ber01-VHDL13_DWMP_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2615
ber01-VHDL13_DWMP_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2795
ber01-VHDL13_DWMP_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2806
ber01-VHDL13_DWMP_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2633
ber01-VHDL13_DWMP_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:06 2478
ber01-VHDL13_DWMP_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2585
ber01-VHDL13_DWMP_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2375
ber01-VHDL13_DWMP_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2572
ber01-VHDL13_DWOG_011700-2604011700-dsw--0-ia5 01-Apr-2026 18:00:01 3033
ber01-VHDL13_DWOG_020300-2604020300-dsw--0-ia5 02-Apr-2026 03:00:08 4040
ber01-VHDL13_DWOG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:01 4052
ber01-VHDL13_DWOG_021700-2604021700-dsw--0-ia5 02-Apr-2026 18:00:01 3575
ber01-VHDL13_DWOG_030300-2604030300-dsw--0-ia5 03-Apr-2026 03:00:08 4232
ber01-VHDL13_DWOG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 4076
ber01-VHDL13_DWOH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2529
ber01-VHDL13_DWOH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:11 2915
ber01-VHDL13_DWOH_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:16 2762
ber01-VHDL13_DWOH_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:45:22 2591
ber01-VHDL13_DWOH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:11 2476
ber01-VHDL13_DWOH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:11 2525
ber01-VHDL13_DWOH_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:17 2574
ber01-VHDL13_DWOH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:17 2672
ber01-VHDL13_DWOI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:12 2578
ber01-VHDL13_DWOI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:28:17 2758
ber01-VHDL13_DWOI_020400-2604020400-dsw--0-ia5 02-Apr-2026 04:58:16 2613
ber01-VHDL13_DWOI_020800-2604020800-dsw--0-ia5 02-Apr-2026 11:45:42 2390
ber01-VHDL13_DWOI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:28:11 2329
ber01-VHDL13_DWOI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:17 2603
ber01-VHDL13_DWOI_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:17 2541
ber01-VHDL13_DWOI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:17 2624
ber01-VHDL13_DWON_010931-2604010931-dsw--0-ia5 01-Apr-2026 09:31:31 3920
ber01-VHDL13_DWON_011455-2604011455-dsw--0-ia5 01-Apr-2026 14:55:07 3631
ber01-VHDL13_DWON_011727-2604011727-dsw--0-ia5 01-Apr-2026 17:28:01 3214
ber01-VHDL13_DWON_012126-2604012126-dsw--0-ia5 01-Apr-2026 21:26:51 3172
ber01-VHDL13_DWON_020154-2604020154-dsw--0-ia5 02-Apr-2026 01:54:27 3491
ber01-VHDL13_DWON_020246-2604020246-dsw--0-ia5 02-Apr-2026 02:46:46 3627
ber01-VHDL13_DWON_020248-2604020248-dsw--0-ia5 02-Apr-2026 02:48:11 3627
ber01-VHDL13_DWON_020513-2604020513-dsw--0-ia5 02-Apr-2026 05:13:57 4064
ber01-VHDL13_DWON_020631-2604020631-dsw--0-ia5 02-Apr-2026 06:31:31 4064
ber01-VHDL13_DWON_020823-2604020823-dsw--0-ia5 02-Apr-2026 08:23:26 4062
ber01-VHDL13_DWON_020921-2604020921-dsw--0-ia5 02-Apr-2026 09:21:42 4115
ber01-VHDL13_DWON_021433-2604021433-dsw--0-ia5 02-Apr-2026 14:33:52 4025
ber01-VHDL13_DWON_021712-2604021712-dsw--0-ia5 02-Apr-2026 17:12:42 3527
ber01-VHDL13_DWON_022041-2604022041-dsw--0-ia5 02-Apr-2026 20:41:31 3523
ber01-VHDL13_DWON_022243-2604022243-dsw--0-ia5 02-Apr-2026 22:44:02 3674
ber01-VHDL13_DWON_030232-2604030232-dsw--0-ia5 03-Apr-2026 02:32:52 3718
ber01-VHDL13_DWON_030525-2604030525-dsw--0-ia5 03-Apr-2026 05:25:12 4262
ber01-VHDL13_DWON_030615-2604030615-dsw--0-ia5 03-Apr-2026 06:15:22 4262
ber01-VHDL13_DWON_030822-2604030822-dsw--0-ia5 03-Apr-2026 08:23:02 4262
ber01-VHDL13_DWON_030858-2604030858-dsw--0-ia5 03-Apr-2026 08:58:31 4262
ber01-VHDL13_DWPG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2475
ber01-VHDL13_DWPG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2588
ber01-VHDL13_DWPG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2549
ber01-VHDL13_DWPG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2607
ber01-VHDL13_DWPG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2294
ber01-VHDL13_DWPG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2293
ber01-VHDL13_DWPG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2403
ber01-VHDL13_DWPG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2583
ber01-VHDL13_DWPH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWPH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2477
ber01-VHDL13_DWPH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:01 2486
ber01-VHDL13_DWPH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:07 2639
ber01-VHDL13_DWPH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:00 2267
ber01-VHDL13_DWPH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2433
ber01-VHDL13_DWPH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2728
ber01-VHDL13_DWPH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2988
ber01-VHDL13_DWSG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2396
ber01-VHDL13_DWSG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:30:01 2829
ber01-VHDL13_DWSG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:17 2630
ber01-VHDL13_DWSG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:30:01 2612
ber01-VHDL13_DWSG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:30:02 2518
ber01-VHDL13_DWSG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2662
ber01-VHDL13_DWSG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2786
ber01-VHDL13_DWSG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2588
ber01-VHDL17_DWOG_011200-2604011200-dsw--0-ia5 01-Apr-2026 11:03:56 3234
ber01-VHDL17_DWOG_021200-2604021200-dsw--0-ia5 02-Apr-2026 11:45:32 3094
swis2-VHDL20_DWEG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2995
swis2-VHDL20_DWEG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3334
swis2-VHDL20_DWEG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:01 3080
swis2-VHDL20_DWEG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3067
swis2-VHDL20_DWEG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2800
swis2-VHDL20_DWEG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 2802
swis2-VHDL20_DWEG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 2894
swis2-VHDL20_DWEG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3147
swis2-VHDL20_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3141
swis2-VHDL20_DWEH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3441
swis2-VHDL20_DWEH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:07 3489
swis2-VHDL20_DWEH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3465
swis2-VHDL20_DWEH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 3255
swis2-VHDL20_DWEH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 3196
swis2-VHDL20_DWEH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 3176
swis2-VHDL20_DWEH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3447
swis2-VHDL20_DWEI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3069
swis2-VHDL20_DWEI_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3190
swis2-VHDL20_DWEI_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:15:07 2962
swis2-VHDL20_DWEI_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 2913
swis2-VHDL20_DWEI_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2678
swis2-VHDL20_DWEI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 2896
swis2-VHDL20_DWEI_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 2892
swis2-VHDL20_DWEI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3146
swis2-VHDL20_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3184
swis2-VHDL20_DWHG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3501
swis2-VHDL20_DWHG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3314
swis2-VHDL20_DWHG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3779
swis2-VHDL20_DWHG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2975
swis2-VHDL20_DWHG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 3086
swis2-VHDL20_DWHG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 3110
swis2-VHDL20_DWHG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3964
swis2-VHDL20_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3183
swis2-VHDL20_DWHH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3387
swis2-VHDL20_DWHH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3396
swis2-VHDL20_DWHH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:06 3888
swis2-VHDL20_DWHH_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:02 2965
swis2-VHDL20_DWHH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 2875
swis2-VHDL20_DWHH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2816
swis2-VHDL20_DWHH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3527
swis2-VHDL20_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2773
swis2-VHDL20_DWLG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 3058
swis2-VHDL20_DWLG_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 3232
swis2-VHDL20_DWLG_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3524
swis2-VHDL20_DWLG_021800-2604021800-dsw--0-ia5 02-Apr-2026 18:45:06 3731
swis2-VHDL20_DWLG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 3625
swis2-VHDL20_DWLG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:11 3728
swis2-VHDL20_DWLG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3843
swis2-VHDL20_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2710
swis2-VHDL20_DWLH_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:02 2830
swis2-VHDL20_DWLH_020400-2604020400-dsw--0-ia5 02-Apr-2026 05:00:11 2923
swis2-VHDL20_DWLH_020800-2604020800-dsw--0-ia5 02-Apr-2026 08:45:05 3377
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swis2-VHDL20_DWSG_020200-2604020200-dsw--0-ia5 02-Apr-2026 02:45:06 3249
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wst04-VHDL20_DWEH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:11 237251
wst04-VHDL20_DWEH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 236707
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wst04-VHDL20_DWEH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 239449
wst04-VHDL20_DWEH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 238945
wst04-VHDL20_DWEH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 239489
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wst04-VHDL20_DWEI_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 337701
wst04-VHDL20_DWEI_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 337444
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wst04-VHDL20_DWEI_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 343624
wst04-VHDL20_DWEI_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 343514
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wst04-VHDL20_DWHG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 335422
wst04-VHDL20_DWHG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:11 335284
wst04-VHDL20_DWHG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:16 336057
wst04-VHDL20_DWHG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 337903
wst04-VHDL20_DWHG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 337686
wst04-VHDL20_DWHG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:11 337658
wst04-VHDL20_DWHG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:17 339970
wst04-VHDL20_DWHH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 320385
wst04-VHDL20_DWHH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:13 321486
wst04-VHDL20_DWHH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:11 321472
wst04-VHDL20_DWHH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 321127
wst04-VHDL20_DWHH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 324622
wst04-VHDL20_DWHH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 325860
wst04-VHDL20_DWHH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:11 325859
wst04-VHDL20_DWHH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 326203
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wst04-VHDL20_DWLG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 327988
wst04-VHDL20_DWLG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 327958
wst04-VHDL20_DWLG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:30 328725
wst04-VHDL20_DWLG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:26 329139
wst04-VHDL20_DWLG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 329369
wst04-VHDL20_DWLG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:41 329252
wst04-VHDL20_DWLG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 329542
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wst04-VHDL20_DWLH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 328091
wst04-VHDL20_DWLH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 328280
wst04-VHDL20_DWLH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:30 328808
wst04-VHDL20_DWLH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 329303
wst04-VHDL20_DWLH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:36 328348
wst04-VHDL20_DWLH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:41 328563
wst04-VHDL20_DWLH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 328751
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wst04-VHDL20_DWLI_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 329782
wst04-VHDL20_DWLI_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:41 329338
wst04-VHDL20_DWLI_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 329529
wst04-VHDL20_DWLI_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:26 331323
wst04-VHDL20_DWLI_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:36 330536
wst04-VHDL20_DWLI_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:41 330379
wst04-VHDL20_DWLI_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 330905
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wst04-VHDL20_DWMG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 541314
wst04-VHDL20_DWMG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 541311
wst04-VHDL20_DWMG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 541675
wst04-VHDL20_DWMG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 546455
wst04-VHDL20_DWMG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 546743
wst04-VHDL20_DWMG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:22 546370
wst04-VHDL20_DWMG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:17 546484
wst04-VHDL20_DWMO_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 439947
wst04-VHDL20_DWMO_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 440966
wst04-VHDL20_DWMO_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:17 441853
wst04-VHDL20_DWMO_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 441736
wst04-VHDL20_DWMO_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 448753
wst04-VHDL20_DWMO_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 449843
wst04-VHDL20_DWMO_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 450215
wst04-VHDL20_DWMO_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 450025
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wst04-VHDL20_DWMP_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 539981
wst04-VHDL20_DWMP_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:21 540991
wst04-VHDL20_DWMP_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:22 541423
wst04-VHDL20_DWMP_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:16 538034
wst04-VHDL20_DWMP_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 537359
wst04-VHDL20_DWMP_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 537866
wst04-VHDL20_DWMP_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 537961
wst04-VHDL20_DWPG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:26 332658
wst04-VHDL20_DWPG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:27 331945
wst04-VHDL20_DWPG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:31 331629
wst04-VHDL20_DWPG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 376786
wst04-VHDL20_DWPG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 339368
wst04-VHDL20_DWPG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:36 339165
wst04-VHDL20_DWPG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:31 339116
wst04-VHDL20_DWPG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 384665
wst04-VHDL20_DWPH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 282558
wst04-VHDL20_DWPH_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:21 237161
wst04-VHDL20_DWPH_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:00:31 237059
wst04-VHDL20_DWPH_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:26 282382
wst04-VHDL20_DWPH_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:22 283126
wst04-VHDL20_DWPH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 238082
wst04-VHDL20_DWPH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:31 237986
wst04-VHDL20_DWPH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 284309
wst04-VHDL20_DWSG_011300-2604011300-omedes--0.pdf 01-Apr-2026 13:45:12 341028
wst04-VHDL20_DWSG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 341744
wst04-VHDL20_DWSG_020200-2604020200-omedes--0.pdf 02-Apr-2026 02:45:16 342439
wst04-VHDL20_DWSG_020400-2604020400-omedes--0.pdf 02-Apr-2026 05:15:11 342348
wst04-VHDL20_DWSG_020800-2604020800-omedes--0.pdf 02-Apr-2026 08:45:12 342277
wst04-VHDL20_DWSG_021300-2604021300-omedes--0.pdf 02-Apr-2026 13:45:12 348566
wst04-VHDL20_DWSG_021800-2604021800-omedes--0.pdf 02-Apr-2026 18:45:12 347807
wst04-VHDL20_DWSG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 348684
wst04-VHDL20_DWSG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:12 347644
wst04-VHDL20_DWSG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 347501