Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Oct-2026 10:22:43 5833
SXDL31_DWAV_021800 02-Oct-2026 15:36:49 7201
SXDL31_DWAV_030800 03-Oct-2026 07:54:44 8464
SXDL31_DWAV_031800 03-Oct-2026 16:08:32 6665
SXDL31_DWAV_040800 04-Oct-2026 07:54:59 6664
SXDL31_DWAV_LATEST 04-Oct-2026 07:54:59 6664
SXDL33_DWAV_020000 02-Oct-2026 10:41:34 8670
SXDL33_DWAV_030000 03-Oct-2026 11:34:18 10777
SXDL33_DWAV_040000 04-Oct-2026 09:49:37 5929
SXDL33_DWAV_LATEST 04-Oct-2026 09:49:37 5929
ber01-FWDL39_DWMS_021200-2610021200-dsw--0-ia5 02-Oct-2026 10:36:09 1743
ber01-FWDL39_DWMS_031200-2610031200-dsw--0-ia5 03-Oct-2026 11:52:59 1128
ber01-VHDL13_DWEG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:20 2215
ber01-VHDL13_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:14 2420
ber01-VHDL13_DWEH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:13 2212
ber01-VHDL13_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:18 2507
ber01-VHDL13_DWEI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:24 2511
ber01-VHDL13_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:24 2519
ber01-VHDL13_DWHG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2722
ber01-VHDL13_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2940
ber01-VHDL13_DWHH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2617
ber01-VHDL13_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2848
ber01-VHDL13_DWLG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2237
ber01-VHDL13_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1894
ber01-VHDL13_DWLH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2218
ber01-VHDL13_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2072
ber01-VHDL13_DWLI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2277
ber01-VHDL13_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1945
ber01-VHDL13_DWMO_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 2918
ber01-VHDL13_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2717
ber01-VHDL13_DWMP_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 3401
ber01-VHDL13_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 3018
ber01-VHDL13_DWOG_021700-2610021700-dsw--0-ia5 02-Oct-2026 18:00:11 2643
ber01-VHDL13_DWOG_030300-2610030300-dsw--0-ia5 03-Oct-2026 03:01:05 2922
ber01-VHDL13_DWOG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2729
ber01-VHDL13_DWOG_031700-2610031700-dsw--0-ia5 03-Oct-2026 18:00:14 3029
ber01-VHDL13_DWOG_040300-2610040300-dsw--0-ia5 04-Oct-2026 03:00:23 3827
ber01-VHDL13_DWOG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:12 3554
ber01-VHDL13_DWON_021110-2610021110-dsw--0-ia5 02-Oct-2026 11:10:33 3703
ber01-VHDL13_DWON_021425-2610021425-dsw--0-ia5 02-Oct-2026 14:25:19 3149
ber01-VHDL13_DWON_021540-2610021540-dsw--0-ia5 02-Oct-2026 15:41:04 3016
ber01-VHDL13_DWON_021543-2610021543-dsw--0-ia5 02-Oct-2026 15:43:14 2906
ber01-VHDL13_DWON_021725-2610021725-dsw--0-ia5 02-Oct-2026 17:25:33 2930
ber01-VHDL13_DWON_022103-2610022103-dsw--0-ia5 02-Oct-2026 21:03:39 2709
ber01-VHDL13_DWON_030110-2610030110-dsw--0-ia5 03-Oct-2026 01:10:10 2850
ber01-VHDL13_DWON_030244-2610030244-dsw--0-ia5 03-Oct-2026 02:45:38 2845
ber01-VHDL13_DWON_030518-2610030518-dsw--0-ia5 03-Oct-2026 05:18:23 3187
ber01-VHDL13_DWON_030927-2610030927-dsw--0-ia5 03-Oct-2026 09:27:44 3234
ber01-VHDL13_DWON_031320-2610031320-dsw--0-ia5 03-Oct-2026 13:21:03 3037
ber01-VHDL13_DWON_031649-2610031649-dsw--0-ia5 03-Oct-2026 16:50:10 3180
ber01-VHDL13_DWON_031849-2610031849-dsw--0-ia5 03-Oct-2026 18:49:49 3477
ber01-VHDL13_DWON_032143-2610032143-dsw--0-ia5 03-Oct-2026 21:43:51 3459
ber01-VHDL13_DWON_032144-2610032144-dsw--0-ia5 03-Oct-2026 21:44:31 3459
ber01-VHDL13_DWON_040004-2610040004-dsw--0-ia5 04-Oct-2026 00:04:48 4032
ber01-VHDL13_DWON_040142-2610040142-dsw--0-ia5 04-Oct-2026 01:42:32 4010
ber01-VHDL13_DWON_040252-2610040252-dsw--0-ia5 04-Oct-2026 02:52:30 4010
ber01-VHDL13_DWON_040529-2610040529-dsw--0-ia5 04-Oct-2026 05:29:58 4277
ber01-VHDL13_DWON_040628-2610040628-dsw--0-ia5 04-Oct-2026 06:28:53 4016
ber01-VHDL13_DWON_040649-2610040649-dsw--0-ia5 04-Oct-2026 06:49:49 4016
ber01-VHDL13_DWON_040802-2610040802-dsw--0-ia5 04-Oct-2026 08:03:13 4016
ber01-VHDL13_DWPG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2170
ber01-VHDL13_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1940
ber01-VHDL13_DWPH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2452
ber01-VHDL13_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1995
ber01-VHDL13_DWSG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2979
ber01-VHDL13_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 3036
ber01-VHDL17_DWOG_021200-2610021200-dsw--0-ia5 02-Oct-2026 11:49:04 2978
ber01-VHDL17_DWOG_031200-2610031200-dsw--0-ia5 03-Oct-2026 11:00:43 2726
swis2-VHDL20_DWEG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 938
swis2-VHDL20_DWEG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 757
swis2-VHDL20_DWEG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 820
swis2-VHDL20_DWEG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1007
swis2-VHDL20_DWEG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1071
swis2-VHDL20_DWEG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 793
swis2-VHDL20_DWEG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 793
swis2-VHDL20_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1052
swis2-VHDL20_DWEH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 964
swis2-VHDL20_DWEH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 771
swis2-VHDL20_DWEH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 834
swis2-VHDL20_DWEH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1015
swis2-VHDL20_DWEH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1087
swis2-VHDL20_DWEH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 805
swis2-VHDL20_DWEH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 805
swis2-VHDL20_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1063
swis2-VHDL20_DWEI_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 1211
swis2-VHDL20_DWEI_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1030
swis2-VHDL20_DWEI_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 1087
swis2-VHDL20_DWEI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1194
swis2-VHDL20_DWEI_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1102
swis2-VHDL20_DWEI_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 816
swis2-VHDL20_DWEI_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 816
swis2-VHDL20_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1080
swis2-VHDL20_DWHG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:45:19 1109
swis2-VHDL20_DWHG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:45:43 995
swis2-VHDL20_DWHG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 992
swis2-VHDL20_DWHG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:45:51 1076
swis2-VHDL20_DWHG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:45:20 1363
swis2-VHDL20_DWHG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:45:35 1127
swis2-VHDL20_DWHG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1124
swis2-VHDL20_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1370
swis2-VHDL20_DWHH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:45:19 1143
swis2-VHDL20_DWHH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:45:43 1017
swis2-VHDL20_DWHH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 1017
swis2-VHDL20_DWHH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:45:51 1083
swis2-VHDL20_DWHH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:45:20 1424
swis2-VHDL20_DWHH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:45:35 1213
swis2-VHDL20_DWHH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1213
swis2-VHDL20_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1371
swis2-VHDL20_DWLG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 911
swis2-VHDL20_DWLG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 778
swis2-VHDL20_DWLG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 908
swis2-VHDL20_DWLG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 854
swis2-VHDL20_DWLG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 821
swis2-VHDL20_DWLG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 771
swis2-VHDL20_DWLG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 785
swis2-VHDL20_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 810
swis2-VHDL20_DWLH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 918
swis2-VHDL20_DWLH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 785
swis2-VHDL20_DWLH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 865
swis2-VHDL20_DWLH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 908
swis2-VHDL20_DWLH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 828
swis2-VHDL20_DWLH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 778
swis2-VHDL20_DWLH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 792
swis2-VHDL20_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 817
swis2-VHDL20_DWLI_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 913
swis2-VHDL20_DWLI_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 780
swis2-VHDL20_DWLI_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 860
swis2-VHDL20_DWLI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 903
swis2-VHDL20_DWLI_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 823
swis2-VHDL20_DWLI_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 773
swis2-VHDL20_DWLI_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 787
swis2-VHDL20_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 812
swis2-VHDL20_DWMO_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:02 1117
swis2-VHDL20_DWMO_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1500
swis2-VHDL20_DWMO_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:18 1506
swis2-VHDL20_DWMO_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1398
swis2-VHDL20_DWMO_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1136
swis2-VHDL20_DWMO_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1061
swis2-VHDL20_DWMO_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:09 1078
swis2-VHDL20_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1234
swis2-VHDL20_DWMP_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:02 1356
swis2-VHDL20_DWMP_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1686
swis2-VHDL20_DWMP_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:18 1691
swis2-VHDL20_DWMP_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1763
swis2-VHDL20_DWMP_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1417
swis2-VHDL20_DWMP_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1353
swis2-VHDL20_DWMP_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:07 1365
swis2-VHDL20_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1417
swis2-VHDL20_DWPG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 923
swis2-VHDL20_DWPG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 787
swis2-VHDL20_DWPG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 912
swis2-VHDL20_DWPG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 872
swis2-VHDL20_DWPG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 839
swis2-VHDL20_DWPG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 789
swis2-VHDL20_DWPG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 803
swis2-VHDL20_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 828
swis2-VHDL20_DWPH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 917
swis2-VHDL20_DWPH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 796
swis2-VHDL20_DWPH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 902
swis2-VHDL20_DWPH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 904
swis2-VHDL20_DWPH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 881
swis2-VHDL20_DWPH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 779
swis2-VHDL20_DWPH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 775
swis2-VHDL20_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 803
swis2-VHDL20_DWSG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 1167
swis2-VHDL20_DWSG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1498
swis2-VHDL20_DWSG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 1496
swis2-VHDL20_DWSG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 1458
swis2-VHDL20_DWSG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1409
swis2-VHDL20_DWSG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1257
swis2-VHDL20_DWSG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1250
swis2-VHDL20_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 1308
wst04-VHDL20_DWEG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 240497
wst04-VHDL20_DWEG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 239523
wst04-VHDL20_DWEG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 239563
wst04-VHDL20_DWEG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 240318
wst04-VHDL20_DWEG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:12 242247
wst04-VHDL20_DWEG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 240224
wst04-VHDL20_DWEG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 240260
wst04-VHDL20_DWEG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 242050
wst04-VHDL20_DWEH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 233381
wst04-VHDL20_DWEH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 233002
wst04-VHDL20_DWEH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 233018
wst04-VHDL20_DWEH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 233806
wst04-VHDL20_DWEH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:12 235087
wst04-VHDL20_DWEH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 233374
wst04-VHDL20_DWEH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 233727
wst04-VHDL20_DWEH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 235539
wst04-VHDL20_DWEI_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:28 348248
wst04-VHDL20_DWEI_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 347261
wst04-VHDL20_DWEI_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 347258
wst04-VHDL20_DWEI_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 347106
wst04-VHDL20_DWEI_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 347972
wst04-VHDL20_DWEI_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 346509
wst04-VHDL20_DWEI_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 346496
wst04-VHDL20_DWEI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 347746
wst04-VHDL20_DWHG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:45:22 347343
wst04-VHDL20_DWHG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:45:43 346917
wst04-VHDL20_DWHG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 346679
wst04-VHDL20_DWHG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:45:51 347427
wst04-VHDL20_DWHG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:45:20 348057
wst04-VHDL20_DWHG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:45:35 347028
wst04-VHDL20_DWHG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 347031
wst04-VHDL20_DWHG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 348375
wst04-VHDL20_DWHH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:45:22 332825
wst04-VHDL20_DWHH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:45:43 332591
wst04-VHDL20_DWHH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 228444
wst04-VHDL20_DWHH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:45:51 333115
wst04-VHDL20_DWHH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:45:20 334068
wst04-VHDL20_DWHH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:45:35 333153
wst04-VHDL20_DWHH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:23 229245
wst04-VHDL20_DWHH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 333809
wst04-VHDL20_DWLG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 333078
wst04-VHDL20_DWLG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 332412
wst04-VHDL20_DWLG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 332783
wst04-VHDL20_DWLG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 332811
wst04-VHDL20_DWLG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:41 332988
wst04-VHDL20_DWLG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 332410
wst04-VHDL20_DWLG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 332473
wst04-VHDL20_DWLG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 332978
wst04-VHDL20_DWLH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 337094
wst04-VHDL20_DWLH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 336430
wst04-VHDL20_DWLH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 336429
wst04-VHDL20_DWLH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 336376
wst04-VHDL20_DWLH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 337010
wst04-VHDL20_DWLH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:27 336421
wst04-VHDL20_DWLH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 336479
wst04-VHDL20_DWLH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 337007
wst04-VHDL20_DWLI_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 338160
wst04-VHDL20_DWLI_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 337515
wst04-VHDL20_DWLI_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 337481
wst04-VHDL20_DWLI_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 382008
wst04-VHDL20_DWLI_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:41 338068
wst04-VHDL20_DWLI_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 337502
wst04-VHDL20_DWLI_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 337527
wst04-VHDL20_DWLI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 382640
wst04-VHDL20_DWMO_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 353320
wst04-VHDL20_DWMO_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 455830
wst04-VHDL20_DWMO_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 455983
wst04-VHDL20_DWMO_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 455614
wst04-VHDL20_DWMO_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 353579
wst04-VHDL20_DWMO_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 455560
wst04-VHDL20_DWMO_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 454724
wst04-VHDL20_DWMO_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 454807
wst04-VHDL20_DWMP_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 460848
wst04-VHDL20_DWMP_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 562283
wst04-VHDL20_DWMP_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 562557
wst04-VHDL20_DWMP_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 461068
wst04-VHDL20_DWMP_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:32 461653
wst04-VHDL20_DWMP_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 562656
wst04-VHDL20_DWMP_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 562410
wst04-VHDL20_DWMP_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 460720
wst04-VHDL20_DWPG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 347521
wst04-VHDL20_DWPG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:37 243295
wst04-VHDL20_DWPG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:45 346931
wst04-VHDL20_DWPG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 391829
wst04-VHDL20_DWPG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 347424
wst04-VHDL20_DWPG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 243304
wst04-VHDL20_DWPG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:34 346967
wst04-VHDL20_DWPG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 391996
wst04-VHDL20_DWPH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 242475
wst04-VHDL20_DWPH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 241781
wst04-VHDL20_DWPH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:45 241829
wst04-VHDL20_DWPH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 242150
wst04-VHDL20_DWPH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 242349
wst04-VHDL20_DWPH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 241764
wst04-VHDL20_DWPH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:34 241832
wst04-VHDL20_DWPH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 242279
wst04-VHDL20_DWSG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 347958
wst04-VHDL20_DWSG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 347599
wst04-VHDL20_DWSG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 347390
wst04-VHDL20_DWSG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 347519
wst04-VHDL20_DWSG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 349477
wst04-VHDL20_DWSG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 347707
wst04-VHDL20_DWSG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 347435
wst04-VHDL20_DWSG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 347632