Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Oct-2026 13:47:31 4081
FPDL13_DWMZ_140600 14-Oct-2026 13:17:38 4019
SXDL31_DWAV_130800 13-Oct-2026 07:24:55 8104
SXDL31_DWAV_131800 13-Oct-2026 18:30:31 5408
SXDL31_DWAV_140800 14-Oct-2026 07:16:15 9177
SXDL31_DWAV_141800 14-Oct-2026 16:42:54 5533
SXDL31_DWAV_LATEST 14-Oct-2026 16:42:54 5533
SXDL33_DWAV_130000 13-Oct-2026 10:27:10 12123
SXDL33_DWAV_140000 14-Oct-2026 11:24:10 7868
SXDL33_DWAV_LATEST 14-Oct-2026 11:24:10 7868
ber01-FWDL39_DWMS_131200-2610131200-dsw--0-ia5 13-Oct-2026 10:26:57 1306
ber01-FWDL39_DWMS_141200-2610141200-dsw--0-ia5 14-Oct-2026 11:32:47 1357
ber01-VHDL13_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2429
ber01-VHDL13_DWEG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2499
ber01-VHDL13_DWEG_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:16 2594
ber01-VHDL13_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 2677
ber01-VHDL13_DWEH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2471
ber01-VHDL13_DWEH_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:05 2813
ber01-VHDL13_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2455
ber01-VHDL13_DWEI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:21 2545
ber01-VHDL13_DWEI_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:16 2642
ber01-VHDL13_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3831
ber01-VHDL13_DWHG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 3153
ber01-VHDL13_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3616
ber01-VHDL13_DWHH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 3162
ber01-VHDL13_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2604
ber01-VHDL13_DWLG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2457
ber01-VHDL13_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2878
ber01-VHDL13_DWLH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2701
ber01-VHDL13_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2649
ber01-VHDL13_DWLI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2485
ber01-VHDL13_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3145
ber01-VHDL13_DWMO_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3026
ber01-VHDL13_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3082
ber01-VHDL13_DWMP_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3348
ber01-VHDL13_DWOG_130300-2610130300-dsw--0-ia5 13-Oct-2026 03:00:31 4586
ber01-VHDL13_DWOG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 4182
ber01-VHDL13_DWOG_131700-2610131700-dsw--0-ia5 13-Oct-2026 18:00:05 4054
ber01-VHDL13_DWOG_140300-2610140300-dsw--0-ia5 14-Oct-2026 03:02:09 4189
ber01-VHDL13_DWOG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 4168
ber01-VHDL13_DWOG_141700-2610141700-dsw--0-ia5 14-Oct-2026 18:00:10 3294
ber01-VHDL13_DWON_130000-2610130000-dsw--0-ia5 13-Oct-2026 00:00:59 3885
ber01-VHDL13_DWON_130131-2610130131-dsw--0-ia5 13-Oct-2026 01:31:55 3843
ber01-VHDL13_DWON_130242-2610130242-dsw--0-ia5 13-Oct-2026 02:42:20 3843
ber01-VHDL13_DWON_130257-2610130257-dsw--0-ia5 13-Oct-2026 02:57:27 3815
ber01-VHDL13_DWON_130258-2610130258-dsw--0-ia5 13-Oct-2026 03:00:31 3839
ber01-VHDL13_DWON_130529-2610130529-dsw--0-ia5 13-Oct-2026 05:29:14 3908
ber01-VHDL13_DWON_130630-2610130630-dsw--0-ia5 13-Oct-2026 06:30:46 3789
ber01-VHDL13_DWON_131042-2610131042-dsw--0-ia5 13-Oct-2026 10:43:19 3874
ber01-VHDL13_DWON_131441-2610131441-dsw--0-ia5 13-Oct-2026 14:41:38 4171
ber01-VHDL13_DWON_131733-2610131733-dsw--0-ia5 13-Oct-2026 17:33:59 3482
ber01-VHDL13_DWON_131842-2610131842-dsw--0-ia5 13-Oct-2026 18:42:35 3722
ber01-VHDL13_DWON_132045-2610132045-dsw--0-ia5 13-Oct-2026 20:45:28 3437
ber01-VHDL13_DWON_132134-2610132134-dsw--0-ia5 13-Oct-2026 21:34:48 3440
ber01-VHDL13_DWON_140006-2610140006-dsw--0-ia5 14-Oct-2026 00:06:14 4255
ber01-VHDL13_DWON_140144-2610140144-dsw--0-ia5 14-Oct-2026 01:44:14 4231
ber01-VHDL13_DWON_140248-2610140248-dsw--0-ia5 14-Oct-2026 02:50:19 4231
ber01-VHDL13_DWON_140353-2610140353-dsw--0-ia5 14-Oct-2026 03:53:45 4231
ber01-VHDL13_DWON_140527-2610140527-dsw--0-ia5 14-Oct-2026 05:28:04 4427
ber01-VHDL13_DWON_140611-2610140611-dsw--0-ia5 14-Oct-2026 06:11:48 4421
ber01-VHDL13_DWON_140835-2610140835-dsw--0-ia5 14-Oct-2026 08:35:54 4366
ber01-VHDL13_DWON_141451-2610141451-dsw--0-ia5 14-Oct-2026 14:54:14 3841
ber01-VHDL13_DWON_141659-2610141659-dsw--0-ia5 14-Oct-2026 16:59:31 3514
ber01-VHDL13_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2997
ber01-VHDL13_DWPG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2997
ber01-VHDL13_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 3377
ber01-VHDL13_DWPH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 3493
ber01-VHDL13_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 2799
ber01-VHDL13_DWSG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 2792
ber01-VHDL17_DWOG_131200-2610131200-dsw--0-ia5 13-Oct-2026 11:46:12 4159
ber01-VHDL17_DWOG_141200-2610141200-dsw--0-ia5 14-Oct-2026 11:33:24 2979
swis2-VHDL20_DWEG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1082
swis2-VHDL20_DWEG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 986
swis2-VHDL20_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 951
swis2-VHDL20_DWEG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 917
swis2-VHDL20_DWEG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 830
swis2-VHDL20_DWEG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 830
swis2-VHDL20_DWEG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1211
swis2-VHDL20_DWEG_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:05 1178
swis2-VHDL20_DWEG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:13 1202
swis2-VHDL20_DWEH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 971
swis2-VHDL20_DWEH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 915
swis2-VHDL20_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1037
swis2-VHDL20_DWEH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 1021
swis2-VHDL20_DWEH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 857
swis2-VHDL20_DWEH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 857
swis2-VHDL20_DWEH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1040
swis2-VHDL20_DWEH_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:39:54 1177
swis2-VHDL20_DWEH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:14 1216
swis2-VHDL20_DWEI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 982
swis2-VHDL20_DWEI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 873
swis2-VHDL20_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 973
swis2-VHDL20_DWEI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 939
swis2-VHDL20_DWEI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 852
swis2-VHDL20_DWEI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 852
swis2-VHDL20_DWEI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1233
swis2-VHDL20_DWEI_140800_COR-2610140800-dsw--0-ia5 14-Oct-2026 14:40:05 1203
swis2-VHDL20_DWEI_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:13 1224
swis2-VHDL20_DWHG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1545
swis2-VHDL20_DWHG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1475
swis2-VHDL20_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1765
swis2-VHDL20_DWHG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 1808
swis2-VHDL20_DWHG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1360
swis2-VHDL20_DWHG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1357
swis2-VHDL20_DWHG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1233
swis2-VHDL20_DWHG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:45:23 1320
swis2-VHDL20_DWHH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1492
swis2-VHDL20_DWHH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1425
swis2-VHDL20_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1612
swis2-VHDL20_DWHH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 2027
swis2-VHDL20_DWHH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1505
swis2-VHDL20_DWHH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1505
swis2-VHDL20_DWHH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:08 1273
swis2-VHDL20_DWHH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:45:23 1106
swis2-VHDL20_DWLG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 893
swis2-VHDL20_DWLG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1060
swis2-VHDL20_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 955
swis2-VHDL20_DWLG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 827
swis2-VHDL20_DWLG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 860
swis2-VHDL20_DWLG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 866
swis2-VHDL20_DWLG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 960
swis2-VHDL20_DWLG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 891
swis2-VHDL20_DWLH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1003
swis2-VHDL20_DWLH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1155
swis2-VHDL20_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1019
swis2-VHDL20_DWLH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 991
swis2-VHDL20_DWLH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1020
swis2-VHDL20_DWLH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1003
swis2-VHDL20_DWLH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 973
swis2-VHDL20_DWLH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 899
swis2-VHDL20_DWLI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 874
swis2-VHDL20_DWLI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1085
swis2-VHDL20_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1017
swis2-VHDL20_DWLI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 898
swis2-VHDL20_DWLI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 843
swis2-VHDL20_DWLI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 849
swis2-VHDL20_DWLI_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 927
swis2-VHDL20_DWLI_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 858
swis2-VHDL20_DWMO_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1194
swis2-VHDL20_DWMO_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1152
swis2-VHDL20_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1394
swis2-VHDL20_DWMO_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1322
swis2-VHDL20_DWMO_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1113
swis2-VHDL20_DWMO_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1301
swis2-VHDL20_DWMO_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1222
swis2-VHDL20_DWMO_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1408
swis2-VHDL20_DWMP_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1244
swis2-VHDL20_DWMP_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1216
swis2-VHDL20_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1323
swis2-VHDL20_DWMP_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1250
swis2-VHDL20_DWMP_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1173
swis2-VHDL20_DWMP_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1260
swis2-VHDL20_DWMP_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1578
swis2-VHDL20_DWMP_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1465
swis2-VHDL20_DWPG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 969
swis2-VHDL20_DWPG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1295
swis2-VHDL20_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1204
swis2-VHDL20_DWPG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1081
swis2-VHDL20_DWPG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1010
swis2-VHDL20_DWPG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1016
swis2-VHDL20_DWPG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 1290
swis2-VHDL20_DWPG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 931
swis2-VHDL20_DWPH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1240
swis2-VHDL20_DWPH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1575
swis2-VHDL20_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1351
swis2-VHDL20_DWPH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1265
swis2-VHDL20_DWPH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1130
swis2-VHDL20_DWPH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1148
swis2-VHDL20_DWPH_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:23 1554
swis2-VHDL20_DWPH_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:31:20 951
swis2-VHDL20_DWSG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:03 1317
swis2-VHDL20_DWSG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1233
swis2-VHDL20_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1243
swis2-VHDL20_DWSG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:08 1333
swis2-VHDL20_DWSG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1019
swis2-VHDL20_DWSG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1149
swis2-VHDL20_DWSG_140800-2610140800-dsw--0-ia5 14-Oct-2026 08:30:04 1315
swis2-VHDL20_DWSG_141800-2610141800-dsw--0-ia5 14-Oct-2026 18:30:07 1145
wst04-VHDL20_DWEG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 235744
wst04-VHDL20_DWEG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 235516
wst04-VHDL20_DWEG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 235091
wst04-VHDL20_DWEG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 236727
wst04-VHDL20_DWEG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:20 236005
wst04-VHDL20_DWEG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 236037
wst04-VHDL20_DWEG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 237059
wst04-VHDL20_DWEG_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 239249
wst04-VHDL20_DWEG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 239318
wst04-VHDL20_DWEH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 233432
wst04-VHDL20_DWEH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 233227
wst04-VHDL20_DWEH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 233931
wst04-VHDL20_DWEH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 237578
wst04-VHDL20_DWEH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 237030
wst04-VHDL20_DWEH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:14 237380
wst04-VHDL20_DWEH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 238284
wst04-VHDL20_DWEH_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 237422
wst04-VHDL20_DWEH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 236870
wst04-VHDL20_DWEI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 338074
wst04-VHDL20_DWEI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 337814
wst04-VHDL20_DWEI_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 337979
wst04-VHDL20_DWEI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 336757
wst04-VHDL20_DWEI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 336627
wst04-VHDL20_DWEI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 336618
wst04-VHDL20_DWEI_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 337135
wst04-VHDL20_DWEI_140800_COR-2610140800-omedes-..> 14-Oct-2026 14:40:16 344168
wst04-VHDL20_DWEI_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 344173
wst04-VHDL20_DWHG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 336662
wst04-VHDL20_DWHG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 336418
wst04-VHDL20_DWHG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:41 338776
wst04-VHDL20_DWHG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 340801
wst04-VHDL20_DWHG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 339169
wst04-VHDL20_DWHG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 339183
wst04-VHDL20_DWHG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:38 339319
wst04-VHDL20_DWHG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:45:23 332325
wst04-VHDL20_DWHH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 318469
wst04-VHDL20_DWHH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:18 225099
wst04-VHDL20_DWHH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:41 318801
wst04-VHDL20_DWHH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 318801
wst04-VHDL20_DWHH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 317440
wst04-VHDL20_DWHH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 221673
wst04-VHDL20_DWHH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 316094
wst04-VHDL20_DWHH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:45:23 312667
wst04-VHDL20_DWLG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 323947
wst04-VHDL20_DWLG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 324574
wst04-VHDL20_DWLG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:49 368608
wst04-VHDL20_DWLG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 328240
wst04-VHDL20_DWLG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 328457
wst04-VHDL20_DWLG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 327802
wst04-VHDL20_DWLG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 327442
wst04-VHDL20_DWLG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 321824
wst04-VHDL20_DWLH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 325126
wst04-VHDL20_DWLH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 325751
wst04-VHDL20_DWLH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 369816
wst04-VHDL20_DWLH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324791
wst04-VHDL20_DWLH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325285
wst04-VHDL20_DWLH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324645
wst04-VHDL20_DWLH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 323821
wst04-VHDL20_DWLH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:31 324731
wst04-VHDL20_DWLI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 326291
wst04-VHDL20_DWLI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 326939
wst04-VHDL20_DWLI_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 371090
wst04-VHDL20_DWLI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324643
wst04-VHDL20_DWLI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325286
wst04-VHDL20_DWLI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324608
wst04-VHDL20_DWLI_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 368835
wst04-VHDL20_DWLI_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 322676
wst04-VHDL20_DWMO_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 447482
wst04-VHDL20_DWMO_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:18 447603
wst04-VHDL20_DWMO_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:39 447796
wst04-VHDL20_DWMO_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:20 343284
wst04-VHDL20_DWMO_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 446202
wst04-VHDL20_DWMO_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 445428
wst04-VHDL20_DWMO_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 445688
wst04-VHDL20_DWMO_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 342865
wst04-VHDL20_DWMP_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 537776
wst04-VHDL20_DWMP_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 538041
wst04-VHDL20_DWMP_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:39 443300
wst04-VHDL20_DWMP_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 444927
wst04-VHDL20_DWMP_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:18 542884
wst04-VHDL20_DWMP_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 542024
wst04-VHDL20_DWMP_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:36 445336
wst04-VHDL20_DWMP_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:28 461370
wst04-VHDL20_DWPG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236347
wst04-VHDL20_DWPG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 335542
wst04-VHDL20_DWPG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:49 379952
wst04-VHDL20_DWPG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 334118
wst04-VHDL20_DWPG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 236974
wst04-VHDL20_DWPG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 333994
wst04-VHDL20_DWPG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 378926
wst04-VHDL20_DWPG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:31 333139
wst04-VHDL20_DWPH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236589
wst04-VHDL20_DWPH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 237433
wst04-VHDL20_DWPH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 281393
wst04-VHDL20_DWPH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 239153
wst04-VHDL20_DWPH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 238906
wst04-VHDL20_DWPH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 238997
wst04-VHDL20_DWPH_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:54 239078
wst04-VHDL20_DWPH_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:31:25 230069
wst04-VHDL20_DWSG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 334829
wst04-VHDL20_DWSG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 334851
wst04-VHDL20_DWSG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 334211
wst04-VHDL20_DWSG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:12 333812
wst04-VHDL20_DWSG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 333590
wst04-VHDL20_DWSG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 333909
wst04-VHDL20_DWSG_140800-2610140800-omedes--0.pdf 14-Oct-2026 08:30:23 334741
wst04-VHDL20_DWSG_141800-2610141800-omedes--0.pdf 14-Oct-2026 18:30:20 343140