Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Jan-2026 15:00:41 6589
FPDL13_DWMZ_140600 14-Jan-2026 11:36:37 3017
SXDL31_DWAV_130800 13-Jan-2026 08:01:59 14718
SXDL31_DWAV_131800 13-Jan-2026 17:37:02 7237
SXDL31_DWAV_140800 14-Jan-2026 08:08:35 7241
SXDL31_DWAV_141800 14-Jan-2026 17:10:09 9414
SXDL31_DWAV_LATEST 14-Jan-2026 17:10:09 9414
SXDL33_DWAV_130000 13-Jan-2026 10:27:03 6393
SXDL33_DWAV_140000 14-Jan-2026 09:55:49 7633
SXDL33_DWAV_LATEST 14-Jan-2026 09:55:49 7633
ber01-FWDL39_DWMS_131230-2601131230-dsw--0-ia5 13-Jan-2026 12:34:11 1994
ber01-FWDL39_DWMS_141230-2601141230-dsw--0-ia5 14-Jan-2026 12:02:51 1474
ber01-VHDL13_DWEH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2667
ber01-VHDL13_DWEH_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:17 2689
ber01-VHDL13_DWEH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:15 2562
ber01-VHDL13_DWEH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:28:17 2286
ber01-VHDL13_DWEH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:11 2121
ber01-VHDL13_DWEH_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:12 2187
ber01-VHDL13_DWEH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:18 2075
ber01-VHDL13_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 2305
ber01-VHDL13_DWHG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2524
ber01-VHDL13_DWHG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2448
ber01-VHDL13_DWHG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 3141
ber01-VHDL13_DWHG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:56:28 3303
ber01-VHDL13_DWHG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2746
ber01-VHDL13_DWHG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 2977
ber01-VHDL13_DWHG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2977
ber01-VHDL13_DWHG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:10 3082
ber01-VHDL13_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 3017
ber01-VHDL13_DWHH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2340
ber01-VHDL13_DWHH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2349
ber01-VHDL13_DWHH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 2524
ber01-VHDL13_DWHH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:56:42 2818
ber01-VHDL13_DWHH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2555
ber01-VHDL13_DWHH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 2494
ber01-VHDL13_DWHH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2494
ber01-VHDL13_DWHH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:10 2590
ber01-VHDL13_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 2563
ber01-VHDL13_DWLG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2683
ber01-VHDL13_DWLG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2442
ber01-VHDL13_DWLG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2431
ber01-VHDL13_DWLG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2495
ber01-VHDL13_DWLG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2684
ber01-VHDL13_DWLG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2599
ber01-VHDL13_DWLG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2817
ber01-VHDL13_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2581
ber01-VHDL13_DWLH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2389
ber01-VHDL13_DWLH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2222
ber01-VHDL13_DWLH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2232
ber01-VHDL13_DWLH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2233
ber01-VHDL13_DWLH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2732
ber01-VHDL13_DWLH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2507
ber01-VHDL13_DWLH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2664
ber01-VHDL13_DWLH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2843
ber01-VHDL13_DWLI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2341
ber01-VHDL13_DWLI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2030
ber01-VHDL13_DWLI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2148
ber01-VHDL13_DWLI_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2174
ber01-VHDL13_DWLI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2261
ber01-VHDL13_DWLI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2174
ber01-VHDL13_DWLI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2263
ber01-VHDL13_DWLI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2393
ber01-VHDL13_DWMG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 4071
ber01-VHDL13_DWMG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4099
ber01-VHDL13_DWMG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 3673
ber01-VHDL13_DWMG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:56:02 3752
ber01-VHDL13_DWMG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 3142
ber01-VHDL13_DWMG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3660
ber01-VHDL13_DWMG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3612
ber01-VHDL13_DWMG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3526
ber01-VHDL13_DWMG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 3175
ber01-VHDL13_DWMO_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 3997
ber01-VHDL13_DWMO_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4145
ber01-VHDL13_DWMO_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 4145
ber01-VHDL13_DWMO_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:56:43 3834
ber01-VHDL13_DWMO_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 3166
ber01-VHDL13_DWMO_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3645
ber01-VHDL13_DWMO_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3579
ber01-VHDL13_DWMO_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3240
ber01-VHDL13_DWMO_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2966
ber01-VHDL13_DWMP_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 4063
ber01-VHDL13_DWMP_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4075
ber01-VHDL13_DWMP_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 4075
ber01-VHDL13_DWMP_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:57:36 3394
ber01-VHDL13_DWMP_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2800
ber01-VHDL13_DWMP_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:09 3693
ber01-VHDL13_DWMP_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:05 3679
ber01-VHDL13_DWMP_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3509
ber01-VHDL13_DWMP_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2945
ber01-VHDL13_DWOG_130300-2601130300-dsw--0-ia5 13-Jan-2026 06:52:37 5144
ber01-VHDL13_DWOG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 4697
ber01-VHDL13_DWOG_131700-2601131700-dsw--0-ia5 13-Jan-2026 19:00:02 4037
ber01-VHDL13_DWOG_140300-2601140300-dsw--0-ia5 14-Jan-2026 04:00:02 3963
ber01-VHDL13_DWOG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3762
ber01-VHDL13_DWOG_141700-2601141700-dsw--0-ia5 14-Jan-2026 19:00:04 3307
ber01-VHDL13_DWOH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2446
ber01-VHDL13_DWOH_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:12 2223
ber01-VHDL13_DWOH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:15 2150
ber01-VHDL13_DWOH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:55:57 2467
ber01-VHDL13_DWOH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:28:17 2277
ber01-VHDL13_DWOH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:11 2013
ber01-VHDL13_DWOH_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:12 2198
ber01-VHDL13_DWOH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:13 1955
ber01-VHDL13_DWOH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 1954
ber01-VHDL13_DWOI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2114
ber01-VHDL13_DWOI_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:17 2152
ber01-VHDL13_DWOI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:11 2194
ber01-VHDL13_DWOI_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:28:11 1962
ber01-VHDL13_DWOI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:28:17 1985
ber01-VHDL13_DWOI_140400-2601140400-dsw--0-ia5 14-Jan-2026 05:58:16 2037
ber01-VHDL13_DWOI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:28:13 1986
ber01-VHDL13_DWOI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:12 1989
ber01-VHDL13_DWON_130222-2601130222-dsw--0-ia5 13-Jan-2026 02:22:21 3922
ber01-VHDL13_DWON_130409-2601130409-dsw--0-ia5 13-Jan-2026 04:09:17 3922
ber01-VHDL13_DWON_130629-2601130629-dsw--0-ia5 13-Jan-2026 06:29:46 4124
ber01-VHDL13_DWON_130719-2601130719-dsw--0-ia5 13-Jan-2026 07:19:52 4136
ber01-VHDL13_DWON_130923-2601130923-dsw--0-ia5 13-Jan-2026 09:23:06 4123
ber01-VHDL13_DWON_131211-2601131211-dsw--0-ia5 13-Jan-2026 12:11:57 3775
ber01-VHDL13_DWON_131524-2601131524-dsw--0-ia5 13-Jan-2026 15:24:12 3450
ber01-VHDL13_DWON_131817-2601131817-dsw--0-ia5 13-Jan-2026 18:17:51 3455
ber01-VHDL13_DWON_140017-2601140017-dsw--0-ia5 14-Jan-2026 00:17:21 3618
ber01-VHDL13_DWON_140208-2601140208-dsw--0-ia5 14-Jan-2026 02:08:41 3618
ber01-VHDL13_DWON_140425-2601140425-dsw--0-ia5 14-Jan-2026 04:25:22 3459
ber01-VHDL13_DWON_140554-2601140554-dsw--0-ia5 14-Jan-2026 05:54:06 3459
ber01-VHDL13_DWON_140642-2601140642-dsw--0-ia5 14-Jan-2026 06:42:47 3459
ber01-VHDL13_DWON_140708-2601140708-dsw--0-ia5 14-Jan-2026 07:08:22 3668
ber01-VHDL13_DWON_140850-2601140850-dsw--0-ia5 14-Jan-2026 08:50:36 3668
ber01-VHDL13_DWON_141152-2601141152-dsw--0-ia5 14-Jan-2026 11:52:46 3668
ber01-VHDL13_DWON_141227-2601141227-dsw--0-ia5 14-Jan-2026 12:27:41 3848
ber01-VHDL13_DWON_141409-2601141409-dsw--0-ia5 14-Jan-2026 14:09:37 3898
ber01-VHDL13_DWON_141534-2601141534-dsw--0-ia5 14-Jan-2026 15:34:12 3898
ber01-VHDL13_DWON_141729-2601141729-dsw--0-ia5 14-Jan-2026 17:29:56 3225
ber01-VHDL13_DWON_141737-2601141737-dsw--0-ia5 14-Jan-2026 17:37:40 3225
ber01-VHDL13_DWON_141823-2601141823-dsw--0-ia5 14-Jan-2026 18:23:42 3225
ber01-VHDL13_DWON_141947-2601141947-dsw--0-ia5 14-Jan-2026 19:47:51 3209
ber01-VHDL13_DWON_142000-2601142000-dsw--0-ia5 14-Jan-2026 20:00:36 3209
ber01-VHDL13_DWPG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2665
ber01-VHDL13_DWPG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2597
ber01-VHDL13_DWPG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2500
ber01-VHDL13_DWPG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2383
ber01-VHDL13_DWPG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2507
ber01-VHDL13_DWPG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2321
ber01-VHDL13_DWPG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2268
ber01-VHDL13_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2116
ber01-VHDL13_DWPG_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:11 2339
ber01-VHDL13_DWPH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2633
ber01-VHDL13_DWPH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2623
ber01-VHDL13_DWPH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2567
ber01-VHDL13_DWPH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 2412
ber01-VHDL13_DWPH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 2386
ber01-VHDL13_DWPH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:01 2195
ber01-VHDL13_DWPH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 2224
ber01-VHDL13_DWPH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2054
ber01-VHDL13_DWPH_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:27 2194
ber01-VHDL13_DWSG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:07 3741
ber01-VHDL13_DWSG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2661
ber01-VHDL13_DWSG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 3103
ber01-VHDL13_DWSG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:30:12 3036
ber01-VHDL13_DWSG_131800_COR-2601131800-dsw--0-ia5 13-Jan-2026 19:42:57 2928
ber01-VHDL13_DWSG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:30:03 3147
ber01-VHDL13_DWSG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3035
ber01-VHDL13_DWSG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:30:02 3102
ber01-VHDL13_DWSG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2586
ber01-VHDL17_DWOG_131200-2601131200-dsw--0-ia5 13-Jan-2026 12:03:31 2354
ber01-VHDL17_DWOG_141200-2601141200-dsw--0-ia5 14-Jan-2026 11:26:47 2379
swis2-VHDL20_DWEG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2847
swis2-VHDL20_DWEG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 2543
swis2-VHDL20_DWEG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 2632
swis2-VHDL20_DWEG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:17 3074
swis2-VHDL20_DWEG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:06 2731
swis2-VHDL20_DWEG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2462
swis2-VHDL20_DWEG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2522
swis2-VHDL20_DWEG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2438
swis2-VHDL20_DWEG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2284
swis2-VHDL20_DWEH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3101
swis2-VHDL20_DWEH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 3023
swis2-VHDL20_DWEH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 3068
swis2-VHDL20_DWEH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:06 2643
swis2-VHDL20_DWEH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2444
swis2-VHDL20_DWEH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2523
swis2-VHDL20_DWEH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2583
swis2-VHDL20_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2666
swis2-VHDL20_DWEI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2408
swis2-VHDL20_DWEI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 2505
swis2-VHDL20_DWEI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 2722
swis2-VHDL20_DWEI_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:06 2382
swis2-VHDL20_DWEI_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2278
swis2-VHDL20_DWEI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 2392
swis2-VHDL20_DWEI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2516
swis2-VHDL20_DWEI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2344
swis2-VHDL20_DWHG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 2710
swis2-VHDL20_DWHG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2631
swis2-VHDL20_DWHG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4021
swis2-VHDL20_DWHG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:34 4296
swis2-VHDL20_DWHG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 2929
swis2-VHDL20_DWHG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3163
swis2-VHDL20_DWHG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3160
swis2-VHDL20_DWHG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3732
swis2-VHDL20_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 3200
swis2-VHDL20_DWHH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 2526
swis2-VHDL20_DWHH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2535
swis2-VHDL20_DWHH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3204
swis2-VHDL20_DWHH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:55 3790
swis2-VHDL20_DWHH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 2741
swis2-VHDL20_DWHH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2680
swis2-VHDL20_DWHH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2680
swis2-VHDL20_DWHH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3218
swis2-VHDL20_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2749
swis2-VHDL20_DWLG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3211
swis2-VHDL20_DWLG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2811
swis2-VHDL20_DWLG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3066
swis2-VHDL20_DWLG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 2896
swis2-VHDL20_DWLG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3095
swis2-VHDL20_DWLG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 3074
swis2-VHDL20_DWLG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 3469
swis2-VHDL20_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3056
swis2-VHDL20_DWLH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2831
swis2-VHDL20_DWLH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2599
swis2-VHDL20_DWLH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 2881
swis2-VHDL20_DWLH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 2607
swis2-VHDL20_DWLH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3116
swis2-VHDL20_DWLH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2921
swis2-VHDL20_DWLH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3261
swis2-VHDL20_DWLH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3257
swis2-VHDL20_DWLI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2780
swis2-VHDL20_DWLI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2402
swis2-VHDL20_DWLI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 2785
swis2-VHDL20_DWLI_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 2544
swis2-VHDL20_DWLI_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2651
swis2-VHDL20_DWLI_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2916
swis2-VHDL20_DWLI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2870
swis2-VHDL20_DWMG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4631
swis2-VHDL20_DWMG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4627
swis2-VHDL20_DWMG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4455
swis2-VHDL20_DWMG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:03:23 4534
swis2-VHDL20_DWMG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3581
swis2-VHDL20_DWMG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 4209
swis2-VHDL20_DWMG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4184
swis2-VHDL20_DWMG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 4390
swis2-VHDL20_DWMG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3827
swis2-VHDL20_DWMO_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4557
swis2-VHDL20_DWMO_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4665
swis2-VHDL20_DWMO_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4569
swis2-VHDL20_DWMO_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:03:50 4590
swis2-VHDL20_DWMO_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3633
swis2-VHDL20_DWMO_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:08 4195
swis2-VHDL20_DWMO_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4147
swis2-VHDL20_DWMO_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:09 4099
swis2-VHDL20_DWMO_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3604
swis2-VHDL20_DWMP_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4589
swis2-VHDL20_DWMP_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4504
swis2-VHDL20_DWMP_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4058
swis2-VHDL20_DWMP_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:05:27 4086
swis2-VHDL20_DWMP_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3298
swis2-VHDL20_DWMP_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 4105
swis2-VHDL20_DWMP_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:07 4101
swis2-VHDL20_DWMP_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 4349
swis2-VHDL20_DWMP_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3538
swis2-VHDL20_DWPG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3121
swis2-VHDL20_DWPG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2950
swis2-VHDL20_DWPG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3249
swis2-VHDL20_DWPG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3045
swis2-VHDL20_DWPG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2959
swis2-VHDL20_DWPG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2767
swis2-VHDL20_DWPG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2847
swis2-VHDL20_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2695
swis2-VHDL20_DWPG_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:16:01 3038
swis2-VHDL20_DWPH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3088
swis2-VHDL20_DWPH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2985
swis2-VHDL20_DWPH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3168
swis2-VHDL20_DWPH_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3011
swis2-VHDL20_DWPH_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 2810
swis2-VHDL20_DWPH_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:00:11 2577
swis2-VHDL20_DWPH_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 2737
swis2-VHDL20_DWPH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2567
swis2-VHDL20_DWPH_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:16:11 2881
swis2-VHDL20_DWSG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 4191
swis2-VHDL20_DWSG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:03 3766
swis2-VHDL20_DWSG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3758
swis2-VHDL20_DWSG_131300-2601131300-dsw--0-ia5 13-Jan-2026 14:45:02 3529
swis2-VHDL20_DWSG_131800-2601131800-dsw--0-ia5 13-Jan-2026 19:45:02 3351
swis2-VHDL20_DWSG_131800_COR-2601131800-dsw--0-ia5 13-Jan-2026 19:42:57 3355
swis2-VHDL20_DWSG_140200-2601140200-dsw--0-ia5 14-Jan-2026 03:45:07 3583
swis2-VHDL20_DWSG_140400-2601140400-dsw--0-ia5 14-Jan-2026 06:15:02 3532
swis2-VHDL20_DWSG_140800-2601140800-dsw--0-ia5 14-Jan-2026 09:45:08 3822
swis2-VHDL20_DWSG_141300-2601141300-dsw--0-ia5 14-Jan-2026 14:45:10 3549
swis2-VHDL20_DWSG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3114
wst04-VHDL20_DWEG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 238438
wst04-VHDL20_DWEG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 236860
wst04-VHDL20_DWEG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:22 238128
wst04-VHDL20_DWEG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:12 228530
wst04-VHDL20_DWEG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 228205
wst04-VHDL20_DWEG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 227922
wst04-VHDL20_DWEG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 227413
wst04-VHDL20_DWEG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 226572
wst04-VHDL20_DWEH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 231678
wst04-VHDL20_DWEH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 230971
wst04-VHDL20_DWEH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 230893
wst04-VHDL20_DWEH_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:12 227755
wst04-VHDL20_DWEH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 228491
wst04-VHDL20_DWEH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 228134
wst04-VHDL20_DWEH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 228617
wst04-VHDL20_DWEH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 228699
wst04-VHDL20_DWEI_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 332794
wst04-VHDL20_DWEI_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:28 332313
wst04-VHDL20_DWEI_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:22 332422
wst04-VHDL20_DWEI_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:12 317781
wst04-VHDL20_DWEI_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 318217
wst04-VHDL20_DWEI_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 318320
wst04-VHDL20_DWEI_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 321697
wst04-VHDL20_DWEI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 321181
wst04-VHDL20_DWHG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 310686
wst04-VHDL20_DWHG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:12 310592
wst04-VHDL20_DWHG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:18 312698
wst04-VHDL20_DWHG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:16 317062
wst04-VHDL20_DWHG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 317945
wst04-VHDL20_DWHG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:11 318152
wst04-VHDL20_DWHG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 318148
wst04-VHDL20_DWHG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 316370
wst04-VHDL20_DWHH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 303695
wst04-VHDL20_DWHH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:12 303691
wst04-VHDL20_DWHH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:18 304276
wst04-VHDL20_DWHH_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:22 305307
wst04-VHDL20_DWHH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 305631
wst04-VHDL20_DWHH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:11 305565
wst04-VHDL20_DWHH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 301975
wst04-VHDL20_DWHH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 301223
wst04-VHDL20_DWLG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 309726
wst04-VHDL20_DWLG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 309465
wst04-VHDL20_DWLG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 309818
wst04-VHDL20_DWLG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:22 299136
wst04-VHDL20_DWLG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 300165
wst04-VHDL20_DWLG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 299983
wst04-VHDL20_DWLG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 301545
wst04-VHDL20_DWLG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 300079
wst04-VHDL20_DWLH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:26 310175
wst04-VHDL20_DWLH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 310177
wst04-VHDL20_DWLH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 310553
wst04-VHDL20_DWLH_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:22 311211
wst04-VHDL20_DWLH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:27 312575
wst04-VHDL20_DWLH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 311841
wst04-VHDL20_DWLH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 320973
wst04-VHDL20_DWLH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 320411
wst04-VHDL20_DWLI_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 317647
wst04-VHDL20_DWLI_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 317623
wst04-VHDL20_DWLI_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 318194
wst04-VHDL20_DWLI_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:22 307212
wst04-VHDL20_DWLI_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:27 307495
wst04-VHDL20_DWLI_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:42 307331
wst04-VHDL20_DWLI_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 310760
wst04-VHDL20_DWLI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 310272
wst04-VHDL20_DWMG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 521752
wst04-VHDL20_DWMG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 521071
wst04-VHDL20_DWMG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 520848
wst04-VHDL20_DWMG_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:01:16 520712
wst04-VHDL20_DWMG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:16 519439
wst04-VHDL20_DWMG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 519569
wst04-VHDL20_DWMG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 520372
wst04-VHDL20_DWMG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 520406
wst04-VHDL20_DWMG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 518542
wst04-VHDL20_DWMO_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 420426
wst04-VHDL20_DWMO_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 421391
wst04-VHDL20_DWMO_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 420643
wst04-VHDL20_DWMO_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:01:52 416440
wst04-VHDL20_DWMO_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:18 415161
wst04-VHDL20_DWMO_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:19 415424
wst04-VHDL20_DWMO_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:17 415906
wst04-VHDL20_DWMO_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 421846
wst04-VHDL20_DWMO_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 419975
wst04-VHDL20_DWMP_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 555155
wst04-VHDL20_DWMP_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 557127
wst04-VHDL20_DWMP_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:16 556297
wst04-VHDL20_DWMP_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:06:02 545355
wst04-VHDL20_DWMP_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:16 543830
wst04-VHDL20_DWMP_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 544033
wst04-VHDL20_DWMP_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:21 545243
wst04-VHDL20_DWMP_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 544751
wst04-VHDL20_DWMP_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:22 542122
wst04-VHDL20_DWPG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:26 311145
wst04-VHDL20_DWPG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:31 311326
wst04-VHDL20_DWPG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 356167
wst04-VHDL20_DWPG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:26 320932
wst04-VHDL20_DWPG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 320823
wst04-VHDL20_DWPG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:31 320579
wst04-VHDL20_DWPG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 363439
wst04-VHDL20_DWPG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 317641
wst04-VHDL20_DWPG_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:14:47 317768
wst04-VHDL20_DWPH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 222305
wst04-VHDL20_DWPH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:31 222649
wst04-VHDL20_DWPH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 267514
wst04-VHDL20_DWPH_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:22 270496
wst04-VHDL20_DWPH_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:24 225831
wst04-VHDL20_DWPH_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:00:31 225602
wst04-VHDL20_DWPH_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 270201
wst04-VHDL20_DWPH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 269755
wst04-VHDL20_DWPH_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:15:01 269520
wst04-VHDL20_DWSG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 343173
wst04-VHDL20_DWSG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 342787
wst04-VHDL20_DWSG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 342568
wst04-VHDL20_DWSG_131300-2601131300-omedes--0.pdf 13-Jan-2026 14:45:11 325692
wst04-VHDL20_DWSG_131800-2601131800-omedes--0.pdf 13-Jan-2026 19:45:12 325534
wst04-VHDL20_DWSG_131800_COR-2601131800-omedes-..> 13-Jan-2026 19:43:02 325529
wst04-VHDL20_DWSG_140200-2601140200-omedes--0.pdf 14-Jan-2026 03:45:10 325999
wst04-VHDL20_DWSG_140400-2601140400-omedes--0.pdf 14-Jan-2026 06:15:13 326460
wst04-VHDL20_DWSG_140800-2601140800-omedes--0.pdf 14-Jan-2026 09:45:34 331518
wst04-VHDL20_DWSG_141300-2601141300-omedes--0.pdf 14-Jan-2026 14:45:16 331244
wst04-VHDL20_DWSG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 330822