Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Oct-2026 14:42:13 6310
FPDL13_DWMZ_230600 23-Oct-2026 12:49:25 4441
SXDL31_DWAV_220800 22-Oct-2026 08:18:00 11220
SXDL31_DWAV_221800 22-Oct-2026 16:21:49 15200
SXDL31_DWAV_230800 23-Oct-2026 08:27:04 14469
SXDL31_DWAV_231800 23-Oct-2026 15:56:40 14671
SXDL31_DWAV_LATEST 23-Oct-2026 15:56:40 14671
SXDL33_DWAV_220000 22-Oct-2026 10:16:08 11133
SXDL33_DWAV_230000 23-Oct-2026 09:24:10 7609
SXDL33_DWAV_LATEST 23-Oct-2026 09:24:10 7609
ber01-FWDL39_DWMS_221200-2610221200-dsw--0-ia5 22-Oct-2026 12:12:58 2376
ber01-FWDL39_DWMS_231200-2610231200-dsw--0-ia5 23-Oct-2026 10:41:58 2470
ber01-VHDL13_DWEG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 3262
ber01-VHDL13_DWEG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:13 3647
ber01-VHDL13_DWEH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 4044
ber01-VHDL13_DWEH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:13 4391
ber01-VHDL13_DWEI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:18 3250
ber01-VHDL13_DWEI_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:13 3715
ber01-VHDL13_DWHG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4463
ber01-VHDL13_DWHG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:11 4145
ber01-VHDL13_DWHH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4108
ber01-VHDL13_DWHH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:11 3785
ber01-VHDL13_DWLG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3411
ber01-VHDL13_DWLG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 3652
ber01-VHDL13_DWLH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3347
ber01-VHDL13_DWLH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 3715
ber01-VHDL13_DWLI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3362
ber01-VHDL13_DWLI_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 3798
ber01-VHDL13_DWMO_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3537
ber01-VHDL13_DWMO_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 3868
ber01-VHDL13_DWMP_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3388
ber01-VHDL13_DWMP_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 4273
ber01-VHDL13_DWOG_220300-2610220300-dsw--0-ia5 22-Oct-2026 03:03:52 5936
ber01-VHDL13_DWOG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 5456
ber01-VHDL13_DWOG_221700-2610221700-dsw--0-ia5 22-Oct-2026 18:00:04 5074
ber01-VHDL13_DWOG_230300-2610230300-dsw--0-ia5 23-Oct-2026 03:00:25 4903
ber01-VHDL13_DWOG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 4608
ber01-VHDL13_DWOG_231700-2610231700-dsw--0-ia5 23-Oct-2026 18:00:17 5381
ber01-VHDL13_DWON_220004-2610220004-dsw--0-ia5 22-Oct-2026 00:04:18 5214
ber01-VHDL13_DWON_220144-2610220144-dsw--0-ia5 22-Oct-2026 01:44:34 5188
ber01-VHDL13_DWON_220251-2610220251-dsw--0-ia5 22-Oct-2026 02:54:01 5209
ber01-VHDL13_DWON_220348-2610220348-dsw--0-ia5 22-Oct-2026 03:48:56 5209
ber01-VHDL13_DWON_220527-2610220527-dsw--0-ia5 22-Oct-2026 05:27:33 4937
ber01-VHDL13_DWON_220628-2610220628-dsw--0-ia5 22-Oct-2026 06:28:24 4884
ber01-VHDL13_DWON_220743-2610220743-dsw--0-ia5 22-Oct-2026 07:43:27 4693
ber01-VHDL13_DWON_220845-2610220845-dsw--0-ia5 22-Oct-2026 08:45:33 4518
ber01-VHDL13_DWON_221059-2610221059-dsw--0-ia5 22-Oct-2026 10:59:17 4365
ber01-VHDL13_DWON_221517-2610221517-dsw--0-ia5 22-Oct-2026 15:17:17 3894
ber01-VHDL13_DWON_221647-2610221647-dsw--0-ia5 22-Oct-2026 16:47:38 3894
ber01-VHDL13_DWON_221709-2610221709-dsw--0-ia5 22-Oct-2026 17:10:09 3894
ber01-VHDL13_DWON_230136-2610230136-dsw--0-ia5 23-Oct-2026 01:36:28 3932
ber01-VHDL13_DWON_230248-2610230248-dsw--0-ia5 23-Oct-2026 02:49:51 3933
ber01-VHDL13_DWON_230517-2610230517-dsw--0-ia5 23-Oct-2026 05:17:39 4644
ber01-VHDL13_DWON_230607-2610230607-dsw--0-ia5 23-Oct-2026 06:07:14 4644
ber01-VHDL13_DWON_230824-2610230824-dsw--0-ia5 23-Oct-2026 08:24:24 4644
ber01-VHDL13_DWON_231459-2610231459-dsw--0-ia5 23-Oct-2026 15:00:00 3674
ber01-VHDL13_DWON_231607-2610231607-dsw--0-ia5 23-Oct-2026 16:07:23 3674
ber01-VHDL13_DWON_231728-2610231728-dsw--0-ia5 23-Oct-2026 17:28:23 3674
ber01-VHDL13_DWON_231812-2610231812-dsw--0-ia5 23-Oct-2026 18:13:03 3674
ber01-VHDL13_DWPG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2084
ber01-VHDL13_DWPG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 2811
ber01-VHDL13_DWPH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2572
ber01-VHDL13_DWPH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 3144
ber01-VHDL13_DWSG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 4149
ber01-VHDL13_DWSG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:07 5077
ber01-VHDL17_DWOG_221200-2610221200-dsw--0-ia5 22-Oct-2026 11:55:13 3434
ber01-VHDL17_DWOG_231200-2610231200-dsw--0-ia5 23-Oct-2026 10:57:52 3048
swis2-VHDL20_DWEG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1056
swis2-VHDL20_DWEG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 1434
swis2-VHDL20_DWEG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 1842
swis2-VHDL20_DWEG_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:04 1798
swis2-VHDL20_DWEG_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 1813
swis2-VHDL20_DWEG_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:01:23 1796
swis2-VHDL20_DWEG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:07 2300
swis2-VHDL20_DWEG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 1838
swis2-VHDL20_DWEH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1079
swis2-VHDL20_DWEH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 2078
swis2-VHDL20_DWEH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2673
swis2-VHDL20_DWEH_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:04 2516
swis2-VHDL20_DWEH_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 1072
swis2-VHDL20_DWEH_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:01:23 2658
swis2-VHDL20_DWEH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:07 3092
swis2-VHDL20_DWEH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2404
swis2-VHDL20_DWEI_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:16 1225
swis2-VHDL20_DWEI_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:01:25 1538
swis2-VHDL20_DWEI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 1945
swis2-VHDL20_DWEI_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:04 1838
swis2-VHDL20_DWEI_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 1868
swis2-VHDL20_DWEI_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:01:23 2022
swis2-VHDL20_DWEI_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:07 2544
swis2-VHDL20_DWEI_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2055
swis2-VHDL20_DWHG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1884
swis2-VHDL20_DWHG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3871
swis2-VHDL20_DWHG_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:45:29 3002
swis2-VHDL20_DWHG_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:19 2243
swis2-VHDL20_DWHG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:11 3169
swis2-VHDL20_DWHG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:45:25 4304
swis2-VHDL20_DWHH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:46:53 1740
swis2-VHDL20_DWHH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1723
swis2-VHDL20_DWHH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 3413
swis2-VHDL20_DWHH_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:45:29 3215
swis2-VHDL20_DWHH_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:46:58 2200
swis2-VHDL20_DWHH_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:19 2240
swis2-VHDL20_DWHH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:11 2993
swis2-VHDL20_DWHH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:45:25 3826
swis2-VHDL20_DWLG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1527
swis2-VHDL20_DWLG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1554
swis2-VHDL20_DWLG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1889
swis2-VHDL20_DWLG_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:31:03 1803
swis2-VHDL20_DWLG_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:34 1629
swis2-VHDL20_DWLG_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:13 1682
swis2-VHDL20_DWLG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:23 2132
swis2-VHDL20_DWLG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:05 1884
swis2-VHDL20_DWLH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1418
swis2-VHDL20_DWLH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1531
swis2-VHDL20_DWLH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1976
swis2-VHDL20_DWLH_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:31:03 1939
swis2-VHDL20_DWLH_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:34 1688
swis2-VHDL20_DWLH_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:13 1856
swis2-VHDL20_DWLH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:23 2310
swis2-VHDL20_DWLH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:05 2023
swis2-VHDL20_DWLI_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1483
swis2-VHDL20_DWLI_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1537
swis2-VHDL20_DWLI_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1908
swis2-VHDL20_DWLI_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:31:03 1890
swis2-VHDL20_DWLI_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:34 1798
swis2-VHDL20_DWLI_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:13 2026
swis2-VHDL20_DWLI_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:23 2390
swis2-VHDL20_DWLI_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1869
swis2-VHDL20_DWMO_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 1675
swis2-VHDL20_DWMO_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:03 1659
swis2-VHDL20_DWMO_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2285
swis2-VHDL20_DWMO_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:16 2222
swis2-VHDL20_DWMO_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 2148
swis2-VHDL20_DWMO_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:09 1944
swis2-VHDL20_DWMO_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 2512
swis2-VHDL20_DWMO_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:09 1395
swis2-VHDL20_DWMP_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 2016
swis2-VHDL20_DWMP_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:03 1753
swis2-VHDL20_DWMP_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2259
swis2-VHDL20_DWMP_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:16 2319
swis2-VHDL20_DWMP_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 2212
swis2-VHDL20_DWMP_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:09 2280
swis2-VHDL20_DWMP_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:03 2846
swis2-VHDL20_DWMP_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:09 2365
swis2-VHDL20_DWPG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 862
swis2-VHDL20_DWPG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 891
swis2-VHDL20_DWPG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1476
swis2-VHDL20_DWPG_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:31:03 1297
swis2-VHDL20_DWPG_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:34 1164
swis2-VHDL20_DWPG_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:13 1571
swis2-VHDL20_DWPG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:23 1909
swis2-VHDL20_DWPG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1411
swis2-VHDL20_DWPH_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:31 1089
swis2-VHDL20_DWPH_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:13 1115
swis2-VHDL20_DWPH_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:28 1774
swis2-VHDL20_DWPH_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:31:03 1757
swis2-VHDL20_DWPH_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:34 1472
swis2-VHDL20_DWPH_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:13 1602
swis2-VHDL20_DWPH_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:23 2008
swis2-VHDL20_DWPH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1705
swis2-VHDL20_DWSG_220200-2610220200-dsw--0-ia5 22-Oct-2026 02:30:06 1833
swis2-VHDL20_DWSG_220400-2610220400-dsw--0-ia5 22-Oct-2026 05:00:19 1863
swis2-VHDL20_DWSG_220800-2610220800-dsw--0-ia5 22-Oct-2026 08:30:06 2428
swis2-VHDL20_DWSG_221800-2610221800-dsw--0-ia5 22-Oct-2026 18:30:04 3278
swis2-VHDL20_DWSG_230200-2610230200-dsw--0-ia5 23-Oct-2026 02:30:04 2864
swis2-VHDL20_DWSG_230400-2610230400-dsw--0-ia5 23-Oct-2026 05:00:19 2709
swis2-VHDL20_DWSG_230800-2610230800-dsw--0-ia5 23-Oct-2026 08:30:07 2998
swis2-VHDL20_DWSG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2642
wst04-VHDL20_DWEG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 245946
wst04-VHDL20_DWEG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 245900
wst04-VHDL20_DWEG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 247058
wst04-VHDL20_DWEG_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 244103
wst04-VHDL20_DWEG_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 244781
wst04-VHDL20_DWEG_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:13 244134
wst04-VHDL20_DWEG_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:23 245400
wst04-VHDL20_DWEG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:19 246996
wst04-VHDL20_DWEH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 243345
wst04-VHDL20_DWEH_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 243628
wst04-VHDL20_DWEH_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 245098
wst04-VHDL20_DWEH_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 240668
wst04-VHDL20_DWEH_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 243318
wst04-VHDL20_DWEH_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:13 242940
wst04-VHDL20_DWEH_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:23 244516
wst04-VHDL20_DWEH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:15 240799
wst04-VHDL20_DWEI_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 349795
wst04-VHDL20_DWEI_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:19 349769
wst04-VHDL20_DWEI_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 350959
wst04-VHDL20_DWEI_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 352663
wst04-VHDL20_DWEI_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 352903
wst04-VHDL20_DWEI_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:13 353054
wst04-VHDL20_DWEI_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:23 353967
wst04-VHDL20_DWEI_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:19 356470
wst04-VHDL20_DWHG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:46:53 344569
wst04-VHDL20_DWHG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:19 344371
wst04-VHDL20_DWHG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:34 347619
wst04-VHDL20_DWHG_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:45:40 342141
wst04-VHDL20_DWHG_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:46:59 341259
wst04-VHDL20_DWHG_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:19 340797
wst04-VHDL20_DWHG_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:33 342709
wst04-VHDL20_DWHG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:45:25 344223
wst04-VHDL20_DWHH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:46:53 336554
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wst04-VHDL20_DWLG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 342130
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wst04-VHDL20_DWLG_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:34 329815
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wst04-VHDL20_DWLH_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:44 334114
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wst04-VHDL20_DWLH_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:34 337568
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wst04-VHDL20_DWLI_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:31:34 333457
wst04-VHDL20_DWLI_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:34 333126
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wst04-VHDL20_DWLI_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:58 378397
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wst04-VHDL20_DWMO_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 455173
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wst04-VHDL20_DWMO_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 450037
wst04-VHDL20_DWMO_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 450182
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wst04-VHDL20_DWMP_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:28 582179
wst04-VHDL20_DWMP_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 567670
wst04-VHDL20_DWMP_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 567397
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wst04-VHDL20_DWMP_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:23 569159
wst04-VHDL20_DWMP_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:28 574775
wst04-VHDL20_DWPG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 242456
wst04-VHDL20_DWPG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:33 342952
wst04-VHDL20_DWPG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:31:02 389082
wst04-VHDL20_DWPG_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:31:34 337399
wst04-VHDL20_DWPG_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:34 237804
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wst04-VHDL20_DWPG_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:48 382884
wst04-VHDL20_DWPG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 339663
wst04-VHDL20_DWPH_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:31 240098
wst04-VHDL20_DWPH_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:33 240332
wst04-VHDL20_DWPH_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:44 241776
wst04-VHDL20_DWPH_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:31:34 241233
wst04-VHDL20_DWPH_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:34 240517
wst04-VHDL20_DWPH_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:33 240356
wst04-VHDL20_DWPH_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:48 241019
wst04-VHDL20_DWPH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 241066
wst04-VHDL20_DWSG_220200-2610220200-omedes--0.pdf 22-Oct-2026 02:30:18 353520
wst04-VHDL20_DWSG_220400-2610220400-omedes--0.pdf 22-Oct-2026 05:00:13 353487
wst04-VHDL20_DWSG_220800-2610220800-omedes--0.pdf 22-Oct-2026 08:30:20 354121
wst04-VHDL20_DWSG_221800-2610221800-omedes--0.pdf 22-Oct-2026 18:30:19 349474
wst04-VHDL20_DWSG_230200-2610230200-omedes--0.pdf 23-Oct-2026 02:30:30 349072
wst04-VHDL20_DWSG_230400-2610230400-omedes--0.pdf 23-Oct-2026 05:00:13 348541
wst04-VHDL20_DWSG_230800-2610230800-omedes--0.pdf 23-Oct-2026 08:30:23 348793
wst04-VHDL20_DWSG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:13 352571