Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Aug-2026 14:02:23 4687
FPDL13_DWMZ_070600 07-Aug-2026 12:59:24 9546
SXDL31_DWAV_060800 06-Aug-2026 06:49:19 13593
SXDL31_DWAV_061800 06-Aug-2026 17:21:40 4784
SXDL31_DWAV_070800 07-Aug-2026 06:44:14 5800
SXDL31_DWAV_071800 07-Aug-2026 16:53:55 3428
SXDL31_DWAV_LATEST 07-Aug-2026 16:53:55 3428
SXDL33_DWAV_060000 06-Aug-2026 09:45:51 5835
SXDL33_DWAV_070000 07-Aug-2026 10:39:32 7075
SXDL33_DWAV_LATEST 07-Aug-2026 10:39:32 7075
ber01-FWDL39_DWMS_061200-2608061200-dsw--0-ia5 06-Aug-2026 10:03:47 1727
ber01-FWDL39_DWMS_071200-2608071200-dsw--0-ia5 07-Aug-2026 11:10:22 1688
ber01-VHDL13_DWEG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2249
ber01-VHDL13_DWEG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:16 2355
ber01-VHDL13_DWEH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2290
ber01-VHDL13_DWEH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:16 2292
ber01-VHDL13_DWEI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:28:16 2101
ber01-VHDL13_DWEI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:28:11 2152
ber01-VHDL13_DWHG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2809
ber01-VHDL13_DWHG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2674
ber01-VHDL13_DWHH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2895
ber01-VHDL13_DWHH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2542
ber01-VHDL13_DWLG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2469
ber01-VHDL13_DWLG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2180
ber01-VHDL13_DWLH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2183
ber01-VHDL13_DWLH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2406
ber01-VHDL13_DWLI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2107
ber01-VHDL13_DWLI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2253
ber01-VHDL13_DWMO_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 2689
ber01-VHDL13_DWMO_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2426
ber01-VHDL13_DWMP_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 3429
ber01-VHDL13_DWMP_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2962
ber01-VHDL13_DWOG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 3682
ber01-VHDL13_DWOG_061700-2608061700-dsw--0-ia5 06-Aug-2026 18:00:06 3437
ber01-VHDL13_DWOG_070300-2608070300-dsw--0-ia5 07-Aug-2026 03:00:02 2965
ber01-VHDL13_DWOG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2831
ber01-VHDL13_DWOG_071700-2608071700-dsw--0-ia5 07-Aug-2026 18:00:06 2547
ber01-VHDL13_DWOG_080300-2608080300-dsw--0-ia5 08-Aug-2026 03:00:02 2690
ber01-VHDL13_DWON_060610-2608060610-dsw--0-ia5 06-Aug-2026 06:10:07 3035
ber01-VHDL13_DWON_060721-2608060721-dsw--0-ia5 06-Aug-2026 07:21:21 3035
ber01-VHDL13_DWON_060812-2608060812-dsw--0-ia5 06-Aug-2026 08:12:41 3035
ber01-VHDL13_DWON_061445-2608061445-dsw--0-ia5 06-Aug-2026 14:45:17 2673
ber01-VHDL13_DWON_061729-2608061729-dsw--0-ia5 06-Aug-2026 17:29:22 2417
ber01-VHDL13_DWON_070105-2608070105-dsw--0-ia5 07-Aug-2026 01:05:22 2944
ber01-VHDL13_DWON_070233-2608070233-dsw--0-ia5 07-Aug-2026 02:34:03 2944
ber01-VHDL13_DWON_070526-2608070526-dsw--0-ia5 07-Aug-2026 05:26:17 2762
ber01-VHDL13_DWON_070550-2608070550-dsw--0-ia5 07-Aug-2026 05:50:46 2808
ber01-VHDL13_DWON_070746-2608070746-dsw--0-ia5 07-Aug-2026 07:46:21 2870
ber01-VHDL13_DWON_071446-2608071446-dsw--0-ia5 07-Aug-2026 14:46:28 2800
ber01-VHDL13_DWON_071742-2608071742-dsw--0-ia5 07-Aug-2026 17:42:59 2281
ber01-VHDL13_DWON_080246-2608080246-dsw--0-ia5 08-Aug-2026 02:47:30 2588
ber01-VHDL13_DWON_080522-2608080522-dsw--0-ia5 08-Aug-2026 05:22:37 2993
ber01-VHDL13_DWPG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2255
ber01-VHDL13_DWPG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2502
ber01-VHDL13_DWPH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:10 2734
ber01-VHDL13_DWPH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 2996
ber01-VHDL13_DWSG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 2642
ber01-VHDL13_DWSG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 2163
ber01-VHDL17_DWOG_061200-2608061200-dsw--0-ia5 06-Aug-2026 11:47:01 2621
ber01-VHDL17_DWOG_071200-2608071200-dsw--0-ia5 07-Aug-2026 11:58:06 2841
swis2-VHDL20_DWEG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 926
swis2-VHDL20_DWEG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1177
swis2-VHDL20_DWEG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 733
swis2-VHDL20_DWEG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 763
swis2-VHDL20_DWEG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 999
swis2-VHDL20_DWEG_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1467
swis2-VHDL20_DWEG_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:07 867
swis2-VHDL20_DWEG_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:01:17 1063
swis2-VHDL20_DWEH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1171
swis2-VHDL20_DWEH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1007
swis2-VHDL20_DWEH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 751
swis2-VHDL20_DWEH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 771
swis2-VHDL20_DWEH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 978
swis2-VHDL20_DWEH_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1142
swis2-VHDL20_DWEH_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:07 831
swis2-VHDL20_DWEH_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:01:17 830
swis2-VHDL20_DWEI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 949
swis2-VHDL20_DWEI_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1072
swis2-VHDL20_DWEI_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 755
swis2-VHDL20_DWEI_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:01:21 755
swis2-VHDL20_DWEI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 924
swis2-VHDL20_DWEI_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1498
swis2-VHDL20_DWEI_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:07 1134
swis2-VHDL20_DWEI_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:01:17 1134
swis2-VHDL20_DWHG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:45:34 1425
swis2-VHDL20_DWHG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:45:05 1520
swis2-VHDL20_DWHG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:45:56 1139
swis2-VHDL20_DWHG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 1160
swis2-VHDL20_DWHG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:55:45 1282
swis2-VHDL20_DWHG_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:45:16 1278
swis2-VHDL20_DWHG_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:45:14 1137
swis2-VHDL20_DWHG_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:16 1079
swis2-VHDL20_DWHH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:45:34 1604
swis2-VHDL20_DWHH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:45:05 1698
swis2-VHDL20_DWHH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:45:56 1310
swis2-VHDL20_DWHH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 1343
swis2-VHDL20_DWHH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:55:45 1292
swis2-VHDL20_DWHH_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:45:16 1158
swis2-VHDL20_DWHH_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:45:14 982
swis2-VHDL20_DWHH_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:16 981
swis2-VHDL20_DWLG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1139
swis2-VHDL20_DWLG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 958
swis2-VHDL20_DWLG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 773
swis2-VHDL20_DWLG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 851
swis2-VHDL20_DWLG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 998
swis2-VHDL20_DWLG_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:31:03 946
swis2-VHDL20_DWLG_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:33 1044
swis2-VHDL20_DWLG_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:12 965
swis2-VHDL20_DWLH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 920
swis2-VHDL20_DWLH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 933
swis2-VHDL20_DWLH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 753
swis2-VHDL20_DWLH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 858
swis2-VHDL20_DWLH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1003
swis2-VHDL20_DWLH_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:31:03 970
swis2-VHDL20_DWLH_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:33 1051
swis2-VHDL20_DWLH_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:12 979
swis2-VHDL20_DWLI_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 912
swis2-VHDL20_DWLI_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 925
swis2-VHDL20_DWLI_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 740
swis2-VHDL20_DWLI_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 854
swis2-VHDL20_DWLI_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1004
swis2-VHDL20_DWLI_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:31:03 952
swis2-VHDL20_DWLI_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:33 1047
swis2-VHDL20_DWLI_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:12 971
swis2-VHDL20_DWMO_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1288
swis2-VHDL20_DWMO_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1133
swis2-VHDL20_DWMO_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:02 839
swis2-VHDL20_DWMO_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:02 840
swis2-VHDL20_DWMO_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 1029
swis2-VHDL20_DWMO_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1057
swis2-VHDL20_DWMO_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:07 1083
swis2-VHDL20_DWMO_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:02 1104
swis2-VHDL20_DWMP_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1768
swis2-VHDL20_DWMP_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:02 1684
swis2-VHDL20_DWMP_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:02 1163
swis2-VHDL20_DWMP_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:02 1163
swis2-VHDL20_DWMP_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:01 1520
swis2-VHDL20_DWMP_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1266
swis2-VHDL20_DWMP_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:07 1103
swis2-VHDL20_DWMP_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:02 1124
swis2-VHDL20_DWPG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1030
swis2-VHDL20_DWPG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 961
swis2-VHDL20_DWPG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 773
swis2-VHDL20_DWPG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 854
swis2-VHDL20_DWPG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1018
swis2-VHDL20_DWPG_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:31:03 984
swis2-VHDL20_DWPG_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:33 961
swis2-VHDL20_DWPG_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:12 887
swis2-VHDL20_DWPH_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:28 1136
swis2-VHDL20_DWPH_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:31:01 1014
swis2-VHDL20_DWPH_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:26 903
swis2-VHDL20_DWPH_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:11 977
swis2-VHDL20_DWPH_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:32 1205
swis2-VHDL20_DWPH_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:31:03 1105
swis2-VHDL20_DWPH_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:33 868
swis2-VHDL20_DWPH_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:12 749
swis2-VHDL20_DWSG_060800-2608060800-dsw--0-ia5 06-Aug-2026 08:30:02 1226
swis2-VHDL20_DWSG_061800-2608061800-dsw--0-ia5 06-Aug-2026 18:30:10 1205
swis2-VHDL20_DWSG_061800_COR-2608061800-dsw--0-ia5 06-Aug-2026 19:36:21 1412
swis2-VHDL20_DWSG_070200-2608070200-dsw--0-ia5 07-Aug-2026 02:30:10 791
swis2-VHDL20_DWSG_070400-2608070400-dsw--0-ia5 07-Aug-2026 05:00:17 663
swis2-VHDL20_DWSG_070800-2608070800-dsw--0-ia5 07-Aug-2026 08:30:10 915
swis2-VHDL20_DWSG_071800-2608071800-dsw--0-ia5 07-Aug-2026 18:30:09 1177
swis2-VHDL20_DWSG_080200-2608080200-dsw--0-ia5 08-Aug-2026 02:30:01 997
swis2-VHDL20_DWSG_080400-2608080400-dsw--0-ia5 08-Aug-2026 05:00:16 989
wst04-VHDL20_DWEG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 238843
wst04-VHDL20_DWEG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 239358
wst04-VHDL20_DWEG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 237266
wst04-VHDL20_DWEG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 237156
wst04-VHDL20_DWEG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 238379
wst04-VHDL20_DWEG_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:15 240852
wst04-VHDL20_DWEG_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:11 238530
wst04-VHDL20_DWEG_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:12 239580
wst04-VHDL20_DWEH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 237867
wst04-VHDL20_DWEH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 236361
wst04-VHDL20_DWEH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 235399
wst04-VHDL20_DWEH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 235532
wst04-VHDL20_DWEH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 236761
wst04-VHDL20_DWEH_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:16 237639
wst04-VHDL20_DWEH_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:11 236764
wst04-VHDL20_DWEH_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:12 236848
wst04-VHDL20_DWEI_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 342947
wst04-VHDL20_DWEI_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:19 343713
wst04-VHDL20_DWEI_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 342886
wst04-VHDL20_DWEI_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 342719
wst04-VHDL20_DWEI_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 343320
wst04-VHDL20_DWEI_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:16 349546
wst04-VHDL20_DWEI_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 347908
wst04-VHDL20_DWEI_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:12 347681
wst04-VHDL20_DWHG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:45:34 342815
wst04-VHDL20_DWHG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:45:11 334442
wst04-VHDL20_DWHG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:45:56 332845
wst04-VHDL20_DWHG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 333117
wst04-VHDL20_DWHG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:55:45 333658
wst04-VHDL20_DWHG_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:45:16 333201
wst04-VHDL20_DWHG_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:45:14 332835
wst04-VHDL20_DWHG_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:16 332414
wst04-VHDL20_DWHH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:45:34 329921
wst04-VHDL20_DWHH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:45:11 322409
wst04-VHDL20_DWHH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:45:56 321244
wst04-VHDL20_DWHH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 226804
wst04-VHDL20_DWHH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:55:45 321101
wst04-VHDL20_DWHH_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:45:16 319001
wst04-VHDL20_DWHH_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:45:14 317862
wst04-VHDL20_DWHH_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:16 221608
wst04-VHDL20_DWLG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 343244
wst04-VHDL20_DWLG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 330830
wst04-VHDL20_DWLG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330080
wst04-VHDL20_DWLG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:40 329875
wst04-VHDL20_DWLG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 330161
wst04-VHDL20_DWLG_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:31:21 332957
wst04-VHDL20_DWLG_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 333925
wst04-VHDL20_DWLG_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:42 333775
wst04-VHDL20_DWLH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:55 343354
wst04-VHDL20_DWLH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 331042
wst04-VHDL20_DWLH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330047
wst04-VHDL20_DWLH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:40 329819
wst04-VHDL20_DWLH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 330123
wst04-VHDL20_DWLH_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:31:29 328927
wst04-VHDL20_DWLH_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 329909
wst04-VHDL20_DWLH_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:42 329782
wst04-VHDL20_DWLI_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 381344
wst04-VHDL20_DWLI_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 331439
wst04-VHDL20_DWLI_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 330958
wst04-VHDL20_DWLI_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:42 330242
wst04-VHDL20_DWLI_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 375187
wst04-VHDL20_DWLI_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:31:21 334070
wst04-VHDL20_DWLI_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 335018
wst04-VHDL20_DWLI_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:42 334848
wst04-VHDL20_DWMO_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:17 478040
wst04-VHDL20_DWMO_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:12 342472
wst04-VHDL20_DWMO_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 460003
wst04-VHDL20_DWMO_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 459880
wst04-VHDL20_DWMO_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 460180
wst04-VHDL20_DWMO_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:15 349906
wst04-VHDL20_DWMO_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:11 462635
wst04-VHDL20_DWMO_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:16 462536
wst04-VHDL20_DWMP_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:28 500099
wst04-VHDL20_DWMP_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:30:19 483076
wst04-VHDL20_DWMP_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:16 597752
wst04-VHDL20_DWMP_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:17 597578
wst04-VHDL20_DWMP_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:25 483157
wst04-VHDL20_DWMP_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:16 494043
wst04-VHDL20_DWMP_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 610863
wst04-VHDL20_DWMP_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:16 610719
wst04-VHDL20_DWPG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 382822
wst04-VHDL20_DWPG_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 334807
wst04-VHDL20_DWPG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:26 235524
wst04-VHDL20_DWPG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:32 334112
wst04-VHDL20_DWPG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 378986
wst04-VHDL20_DWPG_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:31:21 333130
wst04-VHDL20_DWPG_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 237856
wst04-VHDL20_DWPG_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:32 333227
wst04-VHDL20_DWPH_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:41 240963
wst04-VHDL20_DWPH_061800-2608061800-omedes--0.pdf 06-Aug-2026 18:31:21 236847
wst04-VHDL20_DWPH_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:24 235785
wst04-VHDL20_DWPH_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:32 235264
wst04-VHDL20_DWPH_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:46 235999
wst04-VHDL20_DWPH_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:31:21 234858
wst04-VHDL20_DWPH_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:33 234053
wst04-VHDL20_DWPH_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:30 233945
wst04-VHDL20_DWSG_060800-2608060800-omedes--0.pdf 06-Aug-2026 08:30:10 353299
wst04-VHDL20_DWSG_061800-2608061800-omedes--0.pdf 06-Aug-2026 19:36:30 348211
wst04-VHDL20_DWSG_070200-2608070200-omedes--0.pdf 07-Aug-2026 02:30:10 346162
wst04-VHDL20_DWSG_070400-2608070400-omedes--0.pdf 07-Aug-2026 05:00:11 345800
wst04-VHDL20_DWSG_070800-2608070800-omedes--0.pdf 07-Aug-2026 08:30:17 346574
wst04-VHDL20_DWSG_071800-2608071800-omedes--0.pdf 07-Aug-2026 18:30:15 356998
wst04-VHDL20_DWSG_080200-2608080200-omedes--0.pdf 08-Aug-2026 02:30:11 356177
wst04-VHDL20_DWSG_080400-2608080400-omedes--0.pdf 08-Aug-2026 05:00:12 355690