Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Jul-2026 13:16:49 19115
FPDL13_DWMZ_050600 05-Jul-2026 10:58:49 3878
SXDL31_DWAV_040800 04-Jul-2026 06:47:43 8669
SXDL31_DWAV_041800 04-Jul-2026 16:30:20 9008
SXDL31_DWAV_050800 05-Jul-2026 07:13:05 12238
SXDL31_DWAV_051800 05-Jul-2026 16:27:09 4217
SXDL31_DWAV_LATEST 05-Jul-2026 16:27:09 4217
SXDL33_DWAV_040000 04-Jul-2026 09:59:05 7167
SXDL33_DWAV_050000 05-Jul-2026 09:24:38 7907
SXDL33_DWAV_LATEST 05-Jul-2026 09:24:38 7907
ber01-FWDL39_DWMS_041200-2607041200-dsw--0-ia5 04-Jul-2026 11:47:02 1322
ber01-FWDL39_DWMS_051200-2607051200-dsw--0-ia5 05-Jul-2026 12:03:06 1376
ber01-VHDL13_DWEG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2997
ber01-VHDL13_DWEG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:28:17 2935
ber01-VHDL13_DWEH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2541
ber01-VHDL13_DWEH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:28:17 3093
ber01-VHDL13_DWEI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2533
ber01-VHDL13_DWEI_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:28:11 2689
ber01-VHDL13_DWHG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3859
ber01-VHDL13_DWHG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:13 3848
ber01-VHDL13_DWHH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3281
ber01-VHDL13_DWHH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:14 3178
ber01-VHDL13_DWLG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3047
ber01-VHDL13_DWLG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 3175
ber01-VHDL13_DWLH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2590
ber01-VHDL13_DWLH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 2881
ber01-VHDL13_DWLI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2610
ber01-VHDL13_DWLI_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 2628
ber01-VHDL13_DWMO_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3143
ber01-VHDL13_DWMO_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 3503
ber01-VHDL13_DWMP_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3034
ber01-VHDL13_DWMP_040800_COR-2607040800-dsw--0-ia5 04-Jul-2026 08:44:45 3159
ber01-VHDL13_DWMP_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 3587
ber01-VHDL13_DWOG_040300-2607040300-dsw--0-ia5 04-Jul-2026 03:00:07 4052
ber01-VHDL13_DWOG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3609
ber01-VHDL13_DWOG_041700-2607041700-dsw--0-ia5 04-Jul-2026 18:00:07 3457
ber01-VHDL13_DWOG_050300-2607050300-dsw--0-ia5 05-Jul-2026 03:00:22 3811
ber01-VHDL13_DWOG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 3825
ber01-VHDL13_DWOG_051700-2607051700-dsw--0-ia5 05-Jul-2026 18:00:06 3357
ber01-VHDL13_DWON_040119-2607040119-dsw--0-ia5 04-Jul-2026 01:19:06 3579
ber01-VHDL13_DWON_040237-2607040237-dsw--0-ia5 04-Jul-2026 02:37:16 3579
ber01-VHDL13_DWON_040240-2607040240-dsw--0-ia5 04-Jul-2026 02:40:28 3607
ber01-VHDL13_DWON_040522-2607040522-dsw--0-ia5 04-Jul-2026 05:22:51 3927
ber01-VHDL13_DWON_040621-2607040621-dsw--0-ia5 04-Jul-2026 06:21:55 3927
ber01-VHDL13_DWON_040812-2607040812-dsw--0-ia5 04-Jul-2026 08:12:32 3927
ber01-VHDL13_DWON_040855-2607040855-dsw--0-ia5 04-Jul-2026 08:55:53 3927
ber01-VHDL13_DWON_041452-2607041452-dsw--0-ia5 04-Jul-2026 14:52:11 3300
ber01-VHDL13_DWON_041703-2607041703-dsw--0-ia5 04-Jul-2026 17:03:42 3183
ber01-VHDL13_DWON_050124-2607050124-dsw--0-ia5 05-Jul-2026 01:24:27 3016
ber01-VHDL13_DWON_050247-2607050247-dsw--0-ia5 05-Jul-2026 02:48:20 3016
ber01-VHDL13_DWON_050523-2607050523-dsw--0-ia5 05-Jul-2026 05:23:42 3081
ber01-VHDL13_DWON_050901-2607050901-dsw--0-ia5 05-Jul-2026 09:01:27 3081
ber01-VHDL13_DWON_051243-2607051243-dsw--0-ia5 05-Jul-2026 12:43:31 2708
ber01-VHDL13_DWON_051732-2607051732-dsw--0-ia5 05-Jul-2026 17:32:42 2836
ber01-VHDL13_DWPG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2480
ber01-VHDL13_DWPG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 2833
ber01-VHDL13_DWPH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2752
ber01-VHDL13_DWPH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 2761
ber01-VHDL13_DWSG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3112
ber01-VHDL13_DWSG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:14 3286
ber01-VHDL17_DWOG_041200-2607041200-dsw--0-ia5 04-Jul-2026 12:00:37 2129
ber01-VHDL17_DWOG_051200-2607051200-dsw--0-ia5 05-Jul-2026 12:02:16 2576
swis2-VHDL20_DWEG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 910
swis2-VHDL20_DWEG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 1102
swis2-VHDL20_DWEG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1272
swis2-VHDL20_DWEG_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:02 1275
swis2-VHDL20_DWEG_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1104
swis2-VHDL20_DWEG_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:01:26 1113
swis2-VHDL20_DWEG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:13 1389
swis2-VHDL20_DWEG_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1132
swis2-VHDL20_DWEH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 853
swis2-VHDL20_DWEH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 963
swis2-VHDL20_DWEH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1127
swis2-VHDL20_DWEH_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:02 1252
swis2-VHDL20_DWEH_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1099
swis2-VHDL20_DWEH_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:01:26 1176
swis2-VHDL20_DWEH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:14 1414
swis2-VHDL20_DWEH_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1203
swis2-VHDL20_DWEI_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 929
swis2-VHDL20_DWEI_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 1151
swis2-VHDL20_DWEI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1213
swis2-VHDL20_DWEI_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:02 1266
swis2-VHDL20_DWEI_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1126
swis2-VHDL20_DWEI_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:01:26 1102
swis2-VHDL20_DWEI_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:13 1360
swis2-VHDL20_DWEI_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1116
swis2-VHDL20_DWHG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:45:10 1547
swis2-VHDL20_DWHG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1539
swis2-VHDL20_DWHG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:45:30 1883
swis2-VHDL20_DWHG_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:45:01 1794
swis2-VHDL20_DWHG_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:46:04 1396
swis2-VHDL20_DWHG_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:17 1389
swis2-VHDL20_DWHG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:45:12 1858
swis2-VHDL20_DWHG_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:45:03 2370
swis2-VHDL20_DWHH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:45:10 1330
swis2-VHDL20_DWHH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1330
swis2-VHDL20_DWHH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:45:30 1594
swis2-VHDL20_DWHH_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:45:01 1632
swis2-VHDL20_DWHH_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:46:04 1389
swis2-VHDL20_DWHH_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:17 1385
swis2-VHDL20_DWHH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:45:12 1621
swis2-VHDL20_DWHH_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:45:03 2206
swis2-VHDL20_DWLG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 946
swis2-VHDL20_DWLG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1251
swis2-VHDL20_DWLG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1607
swis2-VHDL20_DWLG_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:31:11 1588
swis2-VHDL20_DWLG_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:25 1394
swis2-VHDL20_DWLG_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:11 1455
swis2-VHDL20_DWLG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:21 1710
swis2-VHDL20_DWLG_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:31:05 1536
swis2-VHDL20_DWLH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 950
swis2-VHDL20_DWLH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1011
swis2-VHDL20_DWLH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1267
swis2-VHDL20_DWLH_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:31:11 1333
swis2-VHDL20_DWLH_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:25 1207
swis2-VHDL20_DWLH_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:11 1203
swis2-VHDL20_DWLH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:21 1405
swis2-VHDL20_DWLH_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:31:05 1531
swis2-VHDL20_DWLI_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 846
swis2-VHDL20_DWLI_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1128
swis2-VHDL20_DWLI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1380
swis2-VHDL20_DWLI_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:31:11 1339
swis2-VHDL20_DWLI_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:25 1201
swis2-VHDL20_DWLI_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:11 1268
swis2-VHDL20_DWLI_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:21 1413
swis2-VHDL20_DWLI_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:31:05 1440
swis2-VHDL20_DWMO_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 1005
swis2-VHDL20_DWMO_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:06 1021
swis2-VHDL20_DWMO_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 1320
swis2-VHDL20_DWMO_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:10 1602
swis2-VHDL20_DWMO_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1522
swis2-VHDL20_DWMO_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:01 1534
swis2-VHDL20_DWMO_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 1715
swis2-VHDL20_DWMO_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1770
swis2-VHDL20_DWMP_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 1003
swis2-VHDL20_DWMP_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:06 1018
swis2-VHDL20_DWMP_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 1227
swis2-VHDL20_DWMP_040800_COR-2607040800-dsw--0-ia5 04-Jul-2026 08:46:04 1282
swis2-VHDL20_DWMP_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:10 1641
swis2-VHDL20_DWMP_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1544
swis2-VHDL20_DWMP_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:01 1554
swis2-VHDL20_DWMP_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:03 1789
swis2-VHDL20_DWMP_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1796
swis2-VHDL20_DWPG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 863
swis2-VHDL20_DWPG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1063
swis2-VHDL20_DWPG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1200
swis2-VHDL20_DWPG_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:31:11 1173
swis2-VHDL20_DWPG_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:25 1040
swis2-VHDL20_DWPG_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:11 1170
swis2-VHDL20_DWPG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:21 1258
swis2-VHDL20_DWPG_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:31:05 1231
swis2-VHDL20_DWPH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 1003
swis2-VHDL20_DWPH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1298
swis2-VHDL20_DWPH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1536
swis2-VHDL20_DWPH_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:31:11 1355
swis2-VHDL20_DWPH_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:25 1192
swis2-VHDL20_DWPH_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:11 1290
swis2-VHDL20_DWPH_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:21 1557
swis2-VHDL20_DWPH_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:31:05 1492
swis2-VHDL20_DWSG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:10 1053
swis2-VHDL20_DWSG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1038
swis2-VHDL20_DWSG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1405
swis2-VHDL20_DWSG_041800-2607041800-dsw--0-ia5 04-Jul-2026 18:30:02 1544
swis2-VHDL20_DWSG_050200-2607050200-dsw--0-ia5 05-Jul-2026 02:30:01 1357
swis2-VHDL20_DWSG_050400-2607050400-dsw--0-ia5 05-Jul-2026 05:00:21 1354
swis2-VHDL20_DWSG_050400_COR-2607050400-dsw--0-ia5 05-Jul-2026 05:11:41 1446
swis2-VHDL20_DWSG_050800-2607050800-dsw--0-ia5 05-Jul-2026 08:30:13 1644
swis2-VHDL20_DWSG_051800-2607051800-dsw--0-ia5 05-Jul-2026 18:30:03 1468
wst04-VHDL20_DWEG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 230766
wst04-VHDL20_DWEG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 231545
wst04-VHDL20_DWEG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 232433
wst04-VHDL20_DWEG_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:12 237759
wst04-VHDL20_DWEG_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:14 236639
wst04-VHDL20_DWEG_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:11 236588
wst04-VHDL20_DWEG_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:13 238161
wst04-VHDL20_DWEG_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:11 237950
wst04-VHDL20_DWEH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 231879
wst04-VHDL20_DWEH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 232357
wst04-VHDL20_DWEH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:10 233367
wst04-VHDL20_DWEH_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:12 237458
wst04-VHDL20_DWEH_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:14 237333
wst04-VHDL20_DWEH_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:11 237630
wst04-VHDL20_DWEH_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:14 238692
wst04-VHDL20_DWEH_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:11 236352
wst04-VHDL20_DWEI_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 324349
wst04-VHDL20_DWEI_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 325350
wst04-VHDL20_DWEI_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 326044
wst04-VHDL20_DWEI_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:12 336025
wst04-VHDL20_DWEI_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:14 336175
wst04-VHDL20_DWEI_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:11 336040
wst04-VHDL20_DWEI_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:21 337336
wst04-VHDL20_DWEI_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:18 340604
wst04-VHDL20_DWHG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:45:40 334579
wst04-VHDL20_DWHG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 334579
wst04-VHDL20_DWHG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:45:30 336186
wst04-VHDL20_DWHG_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:45:11 340964
wst04-VHDL20_DWHG_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:46:04 338929
wst04-VHDL20_DWHG_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:17 338696
wst04-VHDL20_DWHG_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:45:12 340801
wst04-VHDL20_DWHG_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:45:12 342237
wst04-VHDL20_DWHH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:45:40 323285
wst04-VHDL20_DWHH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 226005
wst04-VHDL20_DWHH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:45:30 323358
wst04-VHDL20_DWHH_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:45:11 324599
wst04-VHDL20_DWHH_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:46:04 324443
wst04-VHDL20_DWHH_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:17 228128
wst04-VHDL20_DWHH_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:45:12 324580
wst04-VHDL20_DWHH_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:45:12 331663
wst04-VHDL20_DWLG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 333500
wst04-VHDL20_DWLG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 334136
wst04-VHDL20_DWLG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 335337
wst04-VHDL20_DWLG_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:31:27 337016
wst04-VHDL20_DWLG_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 335723
wst04-VHDL20_DWLG_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:41 336132
wst04-VHDL20_DWLG_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:50 336836
wst04-VHDL20_DWLG_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:31:30 341229
wst04-VHDL20_DWLH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 331620
wst04-VHDL20_DWLH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 331342
wst04-VHDL20_DWLH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 332515
wst04-VHDL20_DWLH_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:31:22 335194
wst04-VHDL20_DWLH_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 334666
wst04-VHDL20_DWLH_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:41 335105
wst04-VHDL20_DWLH_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:40 335028
wst04-VHDL20_DWLH_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:31:30 333432
wst04-VHDL20_DWLI_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:28 331926
wst04-VHDL20_DWLI_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 332677
wst04-VHDL20_DWLI_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 377661
wst04-VHDL20_DWLI_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:31:22 336990
wst04-VHDL20_DWLI_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 336477
wst04-VHDL20_DWLI_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:41 336955
wst04-VHDL20_DWLI_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:40 381408
wst04-VHDL20_DWLI_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:31:30 335776
wst04-VHDL20_DWMO_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:16 444062
wst04-VHDL20_DWMO_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 443945
wst04-VHDL20_DWMO_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 444449
wst04-VHDL20_DWMO_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:16 347583
wst04-VHDL20_DWMO_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 451539
wst04-VHDL20_DWMO_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:17 451267
wst04-VHDL20_DWMO_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:21 451581
wst04-VHDL20_DWMO_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:18 350611
wst04-VHDL20_DWMP_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:16 572779
wst04-VHDL20_DWMP_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 572584
wst04-VHDL20_DWMP_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:22 465188
wst04-VHDL20_DWMP_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:16 449733
wst04-VHDL20_DWMP_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 553377
wst04-VHDL20_DWMP_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:17 553213
wst04-VHDL20_DWMP_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:21 450223
wst04-VHDL20_DWMP_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:18 468169
wst04-VHDL20_DWPG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 237774
wst04-VHDL20_DWPG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:30 339201
wst04-VHDL20_DWPG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 384331
wst04-VHDL20_DWPG_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:31:22 338186
wst04-VHDL20_DWPG_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:28 239323
wst04-VHDL20_DWPG_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:31 338691
wst04-VHDL20_DWPG_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:40 383440
wst04-VHDL20_DWPG_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:31:30 341240
wst04-VHDL20_DWPH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 236982
wst04-VHDL20_DWPH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:30 237327
wst04-VHDL20_DWPH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 237938
wst04-VHDL20_DWPH_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:31:22 237888
wst04-VHDL20_DWPH_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:25 237048
wst04-VHDL20_DWPH_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:00:31 237611
wst04-VHDL20_DWPH_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:40 238253
wst04-VHDL20_DWPH_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:31:30 245794
wst04-VHDL20_DWSG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:10 332685
wst04-VHDL20_DWSG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 333193
wst04-VHDL20_DWSG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:22 334090
wst04-VHDL20_DWSG_041800-2607041800-omedes--0.pdf 04-Jul-2026 18:30:16 343028
wst04-VHDL20_DWSG_050200-2607050200-omedes--0.pdf 05-Jul-2026 02:30:14 341977
wst04-VHDL20_DWSG_050400-2607050400-omedes--0.pdf 05-Jul-2026 05:11:51 341875
wst04-VHDL20_DWSG_050800-2607050800-omedes--0.pdf 05-Jul-2026 08:30:21 343319
wst04-VHDL20_DWSG_051800-2607051800-omedes--0.pdf 05-Jul-2026 18:30:11 353233