Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Apr-2026 13:26:39 14738
FPDL13_DWMZ_060600 06-Apr-2026 12:49:00 2833
SXDL31_DWAV_041800 04-Apr-2026 17:14:41 10217
SXDL31_DWAV_050800 05-Apr-2026 07:06:59 7598
SXDL31_DWAV_051800 05-Apr-2026 16:56:03 8977
SXDL31_DWAV_060800 06-Apr-2026 06:41:54 6608
SXDL31_DWAV_LATEST 06-Apr-2026 06:41:54 6608
SXDL33_DWAV_050000 05-Apr-2026 09:44:10 9979
SXDL33_DWAV_060000 06-Apr-2026 09:20:59 8035
SXDL33_DWAV_LATEST 06-Apr-2026 09:20:59 8035
ber01-FWDL39_DWMS_051230-2604051230-dsw--0-ia5 05-Apr-2026 10:52:31 2156
ber01-FWDL39_DWMS_061230-2604061230-dsw--0-ia5 06-Apr-2026 12:04:31 1749
ber01-VHDL13_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2752
ber01-VHDL13_DWEH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2673
ber01-VHDL13_DWEH_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:16 2454
ber01-VHDL13_DWEH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:17 3028
ber01-VHDL13_DWEH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:13 1899
ber01-VHDL13_DWEH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:11 2235
ber01-VHDL13_DWEH_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:11 2352
ber01-VHDL13_DWEH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:17 2335
ber01-VHDL13_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 3209
ber01-VHDL13_DWHG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:10 3169
ber01-VHDL13_DWHG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 3163
ber01-VHDL13_DWHG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:07 3068
ber01-VHDL13_DWHG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 3280
ber01-VHDL13_DWHG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2936
ber01-VHDL13_DWHG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3026
ber01-VHDL13_DWHG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2947
ber01-VHDL13_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2666
ber01-VHDL13_DWHH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:10 2722
ber01-VHDL13_DWHH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2722
ber01-VHDL13_DWHH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:07 2915
ber01-VHDL13_DWHH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 3455
ber01-VHDL13_DWHH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 3075
ber01-VHDL13_DWHH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3089
ber01-VHDL13_DWHH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2914
ber01-VHDL13_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2715
ber01-VHDL13_DWLG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2638
ber01-VHDL13_DWLG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2602
ber01-VHDL13_DWLG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2941
ber01-VHDL13_DWLG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2333
ber01-VHDL13_DWLG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2513
ber01-VHDL13_DWLG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2583
ber01-VHDL13_DWLG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2339
ber01-VHDL13_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2772
ber01-VHDL13_DWLH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2716
ber01-VHDL13_DWLH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2670
ber01-VHDL13_DWLH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3107
ber01-VHDL13_DWLH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2381
ber01-VHDL13_DWLH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2583
ber01-VHDL13_DWLH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2562
ber01-VHDL13_DWLH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2464
ber01-VHDL13_DWLI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2328
ber01-VHDL13_DWLI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2295
ber01-VHDL13_DWLI_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2215
ber01-VHDL13_DWLI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2382
ber01-VHDL13_DWLI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 1881
ber01-VHDL13_DWLI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 1979
ber01-VHDL13_DWLI_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 1840
ber01-VHDL13_DWLI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 1908
ber01-VHDL13_DWMG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2878
ber01-VHDL13_DWMG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 3277
ber01-VHDL13_DWMG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 3074
ber01-VHDL13_DWMG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3299
ber01-VHDL13_DWMG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2861
ber01-VHDL13_DWMG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2490
ber01-VHDL13_DWMG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2557
ber01-VHDL13_DWMG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2621
ber01-VHDL13_DWMO_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2753
ber01-VHDL13_DWMO_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2693
ber01-VHDL13_DWMO_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 2603
ber01-VHDL13_DWMO_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2777
ber01-VHDL13_DWMO_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2166
ber01-VHDL13_DWMO_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2131
ber01-VHDL13_DWMO_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2151
ber01-VHDL13_DWMO_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2360
ber01-VHDL13_DWMP_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2715
ber01-VHDL13_DWMP_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 3400
ber01-VHDL13_DWMP_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 3428
ber01-VHDL13_DWMP_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2978
ber01-VHDL13_DWMP_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:08 2983
ber01-VHDL13_DWMP_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2662
ber01-VHDL13_DWMP_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:07 2731
ber01-VHDL13_DWMP_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2683
ber01-VHDL13_DWOG_041700-2604041700-dsw--0-ia5 04-Apr-2026 18:00:02 4843
ber01-VHDL13_DWOG_050300-2604050300-dsw--0-ia5 05-Apr-2026 03:00:01 4669
ber01-VHDL13_DWOG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 5026
ber01-VHDL13_DWOG_051700-2604051700-dsw--0-ia5 05-Apr-2026 18:00:02 3876
ber01-VHDL13_DWOG_060300-2604060300-dsw--0-ia5 06-Apr-2026 03:00:02 3712
ber01-VHDL13_DWOG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 3714
ber01-VHDL13_DWOH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2537
ber01-VHDL13_DWOH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2689
ber01-VHDL13_DWOH_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:12 2404
ber01-VHDL13_DWOH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:17 2699
ber01-VHDL13_DWOH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1823
ber01-VHDL13_DWOH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:11 2103
ber01-VHDL13_DWOH_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:17 2190
ber01-VHDL13_DWOH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:11 2193
ber01-VHDL13_DWOI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:10 2471
ber01-VHDL13_DWOI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2583
ber01-VHDL13_DWOI_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:16 2356
ber01-VHDL13_DWOI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:11 2584
ber01-VHDL13_DWOI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1685
ber01-VHDL13_DWOI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:28:17 1975
ber01-VHDL13_DWOI_060400-2604060400-dsw--0-ia5 06-Apr-2026 04:58:11 2153
ber01-VHDL13_DWOI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:28:17 2139
ber01-VHDL13_DWON_041749-2604041749-dsw--0-ia5 04-Apr-2026 17:49:43 4156
ber01-VHDL13_DWON_050243-2604050243-dsw--0-ia5 05-Apr-2026 02:43:31 4039
ber01-VHDL13_DWON_050528-2604050528-dsw--0-ia5 05-Apr-2026 05:28:21 5071
ber01-VHDL13_DWON_050621-2604050621-dsw--0-ia5 05-Apr-2026 06:21:37 5046
ber01-VHDL13_DWON_050823-2604050823-dsw--0-ia5 05-Apr-2026 08:23:07 4862
ber01-VHDL13_DWON_050855-2604050855-dsw--0-ia5 05-Apr-2026 08:55:36 4862
ber01-VHDL13_DWON_051500-2604051500-dsw--0-ia5 05-Apr-2026 15:00:46 3326
ber01-VHDL13_DWON_051736-2604051736-dsw--0-ia5 05-Apr-2026 17:36:31 3219
ber01-VHDL13_DWON_060053-2604060053-dsw--0-ia5 06-Apr-2026 00:53:47 3740
ber01-VHDL13_DWON_060234-2604060234-dsw--0-ia5 06-Apr-2026 02:34:37 3810
ber01-VHDL13_DWON_060235-2604060235-dsw--0-ia5 06-Apr-2026 02:36:09 3810
ber01-VHDL13_DWON_060521-2604060521-dsw--0-ia5 06-Apr-2026 05:21:27 3545
ber01-VHDL13_DWON_060604-2604060604-dsw--0-ia5 06-Apr-2026 06:04:07 3622
ber01-VHDL13_DWON_060734-2604060734-dsw--0-ia5 06-Apr-2026 07:34:38 3702
ber01-VHDL13_DWON_060928-2604060928-dsw--0-ia5 06-Apr-2026 09:28:57 3702
ber01-VHDL13_DWON_061333-2604061333-dsw--0-ia5 06-Apr-2026 13:33:15 3335
ber01-VHDL13_DWON_061423-2604061423-dsw--0-ia5 06-Apr-2026 14:23:32 3335
ber01-VHDL13_DWPG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2390
ber01-VHDL13_DWPG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2404
ber01-VHDL13_DWPG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2375
ber01-VHDL13_DWPG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2681
ber01-VHDL13_DWPG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2261
ber01-VHDL13_DWPG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 2526
ber01-VHDL13_DWPG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2587
ber01-VHDL13_DWPG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2534
ber01-VHDL13_DWPH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2711
ber01-VHDL13_DWPH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2788
ber01-VHDL13_DWPH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2750
ber01-VHDL13_DWPH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3286
ber01-VHDL13_DWPH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 3191
ber01-VHDL13_DWPH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:08 3168
ber01-VHDL13_DWPH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:01 2955
ber01-VHDL13_DWPH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:08 2974
ber01-VHDL13_DWSG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2622
ber01-VHDL13_DWSG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2726
ber01-VHDL13_DWSG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:16 2814
ber01-VHDL13_DWSG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2796
ber01-VHDL13_DWSG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:30:05 2344
ber01-VHDL13_DWSG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:30:03 2230
ber01-VHDL13_DWSG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:17 2283
ber01-VHDL13_DWSG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:30:03 2138
ber01-VHDL17_DWOG_051200-2604051200-dsw--0-ia5 05-Apr-2026 10:49:37 3098
ber01-VHDL17_DWOG_061200-2604061200-dsw--0-ia5 06-Apr-2026 11:10:26 3054
swis2-VHDL20_DWEG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2860
swis2-VHDL20_DWEG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2965
swis2-VHDL20_DWEG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:02 2928
swis2-VHDL20_DWEG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3382
swis2-VHDL20_DWEG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2353
swis2-VHDL20_DWEG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2586
swis2-VHDL20_DWEG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2511
swis2-VHDL20_DWEG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 2670
swis2-VHDL20_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 3103
swis2-VHDL20_DWEH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2994
swis2-VHDL20_DWEH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:06 2990
swis2-VHDL20_DWEH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3736
swis2-VHDL20_DWEH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2456
swis2-VHDL20_DWEH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2763
swis2-VHDL20_DWEH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2685
swis2-VHDL20_DWEH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:12 2837
swis2-VHDL20_DWEI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2819
swis2-VHDL20_DWEI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2875
swis2-VHDL20_DWEI_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:02 2911
swis2-VHDL20_DWEI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3314
swis2-VHDL20_DWEI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2240
swis2-VHDL20_DWEI_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2475
swis2-VHDL20_DWEI_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2505
swis2-VHDL20_DWEI_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 2663
swis2-VHDL20_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 3392
swis2-VHDL20_DWHG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 3355
swis2-VHDL20_DWHG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 3346
swis2-VHDL20_DWHG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:06 3619
swis2-VHDL20_DWHG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 3463
swis2-VHDL20_DWHG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 3122
swis2-VHDL20_DWHG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3209
swis2-VHDL20_DWHG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 3510
swis2-VHDL20_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 2852
swis2-VHDL20_DWHH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2908
swis2-VHDL20_DWHH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2908
swis2-VHDL20_DWHH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:06 3485
swis2-VHDL20_DWHH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 3641
swis2-VHDL20_DWHH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 3261
swis2-VHDL20_DWHH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:11 3275
swis2-VHDL20_DWHH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:02 3485
swis2-VHDL20_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3057
swis2-VHDL20_DWLG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2980
swis2-VHDL20_DWLG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2947
swis2-VHDL20_DWLG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:01 3433
swis2-VHDL20_DWLG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2678
swis2-VHDL20_DWLG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2858
swis2-VHDL20_DWLG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:15 2926
swis2-VHDL20_DWLG_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:12 2829
swis2-VHDL20_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3121
swis2-VHDL20_DWLH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 3065
swis2-VHDL20_DWLH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 3022
swis2-VHDL20_DWLH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:01 3610
swis2-VHDL20_DWLH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:02 2733
swis2-VHDL20_DWLH_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2935
swis2-VHDL20_DWLH_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:00:15 2912
swis2-VHDL20_DWLH_060800-2604060800-dsw--0-ia5 06-Apr-2026 08:45:12 2966
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swis2-VHDL20_DWMO_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 2503
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swis2-VHDL20_DWMP_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:01 3596
swis2-VHDL20_DWMP_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:06 3344
swis2-VHDL20_DWMP_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:09 3033
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swis2-VHDL20_DWSG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 3072
swis2-VHDL20_DWSG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:02 3166
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swis2-VHDL20_DWSG_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:45:06 2698
swis2-VHDL20_DWSG_060200-2604060200-dsw--0-ia5 06-Apr-2026 02:45:01 2576
swis2-VHDL20_DWSG_060400-2604060400-dsw--0-ia5 06-Apr-2026 05:15:02 2637
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wst04-VHDL20_DWEG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 243078
wst04-VHDL20_DWEG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 241963
wst04-VHDL20_DWEG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 244139
wst04-VHDL20_DWEG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:12 240548
wst04-VHDL20_DWEG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 240837
wst04-VHDL20_DWEG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:12 240862
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wst04-VHDL20_DWEH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 242341
wst04-VHDL20_DWEH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 241346
wst04-VHDL20_DWEH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 242856
wst04-VHDL20_DWEH_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:12 244632
wst04-VHDL20_DWEH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 244903
wst04-VHDL20_DWEH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:12 244972
wst04-VHDL20_DWEH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:12 245421
wst04-VHDL20_DWEI_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:12 346183
wst04-VHDL20_DWEI_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 346001
wst04-VHDL20_DWEI_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 345937
wst04-VHDL20_DWEI_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 347154
wst04-VHDL20_DWEI_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:12 346402
wst04-VHDL20_DWEI_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 346506
wst04-VHDL20_DWEI_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 346732
wst04-VHDL20_DWEI_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:18 347182
wst04-VHDL20_DWHG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 341579
wst04-VHDL20_DWHG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 341872
wst04-VHDL20_DWHG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:12 341737
wst04-VHDL20_DWHG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:18 342266
wst04-VHDL20_DWHG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:22 345140
wst04-VHDL20_DWHG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 344824
wst04-VHDL20_DWHG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:11 345257
wst04-VHDL20_DWHG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:18 346612
wst04-VHDL20_DWHH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 320964
wst04-VHDL20_DWHH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 321548
wst04-VHDL20_DWHH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:12 321534
wst04-VHDL20_DWHH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:18 322243
wst04-VHDL20_DWHH_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:22 329336
wst04-VHDL20_DWHH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 328734
wst04-VHDL20_DWHH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:11 328803
wst04-VHDL20_DWHH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:18 329935
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wst04-VHDL20_DWLG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 335253
wst04-VHDL20_DWLG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 335234
wst04-VHDL20_DWLG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:25 335736
wst04-VHDL20_DWLG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:26 339483
wst04-VHDL20_DWLG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 339979
wst04-VHDL20_DWLG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 339684
wst04-VHDL20_DWLG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 340825
wst04-VHDL20_DWLH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 331780
wst04-VHDL20_DWLH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 332064
wst04-VHDL20_DWLH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 332060
wst04-VHDL20_DWLH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:25 332775
wst04-VHDL20_DWLH_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:22 334113
wst04-VHDL20_DWLH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 334967
wst04-VHDL20_DWLH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 334635
wst04-VHDL20_DWLH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 335211
wst04-VHDL20_DWLI_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 333437
wst04-VHDL20_DWLI_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 333428
wst04-VHDL20_DWLI_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 333417
wst04-VHDL20_DWLI_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:32 333406
wst04-VHDL20_DWLI_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:22 334397
wst04-VHDL20_DWLI_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 334788
wst04-VHDL20_DWLI_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:41 334711
wst04-VHDL20_DWLI_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:31 335322
wst04-VHDL20_DWMG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 552152
wst04-VHDL20_DWMG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 552384
wst04-VHDL20_DWMG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 552738
wst04-VHDL20_DWMG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 553725
wst04-VHDL20_DWMG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:16 565123
wst04-VHDL20_DWMG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 564519
wst04-VHDL20_DWMG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:22 564713
wst04-VHDL20_DWMG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 564625
wst04-VHDL20_DWMO_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 450179
wst04-VHDL20_DWMO_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 449972
wst04-VHDL20_DWMO_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 450516
wst04-VHDL20_DWMO_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 450701
wst04-VHDL20_DWMO_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:16 461116
wst04-VHDL20_DWMO_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 461661
wst04-VHDL20_DWMO_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 462787
wst04-VHDL20_DWMO_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 463305
wst04-VHDL20_DWMP_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 549804
wst04-VHDL20_DWMP_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 549239
wst04-VHDL20_DWMP_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 550624
wst04-VHDL20_DWMP_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 550915
wst04-VHDL20_DWMP_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:16 564551
wst04-VHDL20_DWMP_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 563193
wst04-VHDL20_DWMP_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:16 563846
wst04-VHDL20_DWMP_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 564188
wst04-VHDL20_DWPG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 336141
wst04-VHDL20_DWPG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 335424
wst04-VHDL20_DWPG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:32 335346
wst04-VHDL20_DWPG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:28 380268
wst04-VHDL20_DWPG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:26 335464
wst04-VHDL20_DWPG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 336190
wst04-VHDL20_DWPG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:31 335856
wst04-VHDL20_DWPG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:31 381426
wst04-VHDL20_DWPH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 280042
wst04-VHDL20_DWPH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 235073
wst04-VHDL20_DWPH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:32 235040
wst04-VHDL20_DWPH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:28 281072
wst04-VHDL20_DWPH_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:22 286127
wst04-VHDL20_DWPH_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:37 241096
wst04-VHDL20_DWPH_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:00:31 240950
wst04-VHDL20_DWPH_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:29 285922
wst04-VHDL20_DWSG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:12 347019
wst04-VHDL20_DWSG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 346845
wst04-VHDL20_DWSG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 346969
wst04-VHDL20_DWSG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 347266
wst04-VHDL20_DWSG_051300-2604051300-omedes--0.pdf 05-Apr-2026 13:45:12 354478
wst04-VHDL20_DWSG_051800-2604051800-omedes--0.pdf 05-Apr-2026 18:45:12 353999
wst04-VHDL20_DWSG_060200-2604060200-omedes--0.pdf 06-Apr-2026 02:45:11 354460
wst04-VHDL20_DWSG_060400-2604060400-omedes--0.pdf 06-Apr-2026 05:15:12 354767
wst04-VHDL20_DWSG_060800-2604060800-omedes--0.pdf 06-Apr-2026 08:45:22 354412
wst04-VHDL20_DWSG_061300-2604061300-omedes--0.pdf 06-Apr-2026 13:45:12 352952