Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Nov-2025 13:08:10 5386
FPDL13_DWMZ_070600 07-Nov-2025 13:45:00 5239
SXDL31_DWAV_060800 06-Nov-2025 08:15:03 11343
SXDL31_DWAV_061800 06-Nov-2025 16:33:07 10261
SXDL31_DWAV_070800 07-Nov-2025 08:10:37 11630
SXDL31_DWAV_071800 07-Nov-2025 16:30:30 9578
SXDL31_DWAV_LATEST 07-Nov-2025 16:30:30 9578
SXDL33_DWAV_060000 06-Nov-2025 10:43:51 4351
SXDL33_DWAV_070000 07-Nov-2025 08:34:48 7772
SXDL33_DWAV_LATEST 07-Nov-2025 08:34:48 7772
ber01-FWDL39_DWMS_061230-2511061230-dsw--0-ia5 06-Nov-2025 13:13:07 1548
ber01-FWDL39_DWMS_071230-2511071230-dsw--0-ia5 07-Nov-2025 12:50:32 913
ber01-VHDL13_DWEH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:28:17 2159
ber01-VHDL13_DWEH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:28:17 2236
ber01-VHDL13_DWEH_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:58:18 2483
ber01-VHDL13_DWEH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:28:27 2347
ber01-VHDL13_DWEH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:28:23 2313
ber01-VHDL13_DWEH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:28:18 2396
ber01-VHDL13_DWEH_070400-2511070400-dsw--0-ia5 07-Nov-2025 05:58:23 2345
ber01-VHDL13_DWEH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:28:21 2333
ber01-VHDL13_DWHG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2131
ber01-VHDL13_DWHG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2123
ber01-VHDL13_DWHG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:16 2092
ber01-VHDL13_DWHG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 2148
ber01-VHDL13_DWHG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2587
ber01-VHDL13_DWHG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2916
ber01-VHDL13_DWHG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:18 2888
ber01-VHDL13_DWHG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2688
ber01-VHDL13_DWHH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 1884
ber01-VHDL13_DWHH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 1960
ber01-VHDL13_DWHH_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:16 1952
ber01-VHDL13_DWHH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:11 2009
ber01-VHDL13_DWHH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2102
ber01-VHDL13_DWHH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2431
ber01-VHDL13_DWHH_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:18 2431
ber01-VHDL13_DWHH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2381
ber01-VHDL13_DWLG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2205
ber01-VHDL13_DWLG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2493
ber01-VHDL13_DWLG_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:59:57 2460
ber01-VHDL13_DWLG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 2606
ber01-VHDL13_DWLG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2295
ber01-VHDL13_DWLG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2622
ber01-VHDL13_DWLG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:02 2573
ber01-VHDL13_DWLG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2543
ber01-VHDL13_DWLH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 1776
ber01-VHDL13_DWLH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2179
ber01-VHDL13_DWLH_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:59:57 2135
ber01-VHDL13_DWLH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:11 2226
ber01-VHDL13_DWLH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 1931
ber01-VHDL13_DWLH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2079
ber01-VHDL13_DWLH_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:02 1964
ber01-VHDL13_DWLH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 1964
ber01-VHDL13_DWLI_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2113
ber01-VHDL13_DWLI_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2274
ber01-VHDL13_DWLI_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:59:57 2296
ber01-VHDL13_DWLI_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 2397
ber01-VHDL13_DWLI_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2083
ber01-VHDL13_DWLI_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2162
ber01-VHDL13_DWLI_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:02 2049
ber01-VHDL13_DWLI_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2130
ber01-VHDL13_DWMG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2473
ber01-VHDL13_DWMG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2733
ber01-VHDL13_DWMG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:07 2903
ber01-VHDL13_DWMG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 3099
ber01-VHDL13_DWMG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:02 2875
ber01-VHDL13_DWMG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 3019
ber01-VHDL13_DWMG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:08 3030
ber01-VHDL13_DWMG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2868
ber01-VHDL13_DWMO_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2204
ber01-VHDL13_DWMO_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2446
ber01-VHDL13_DWMO_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:07 2540
ber01-VHDL13_DWMO_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 2747
ber01-VHDL13_DWMO_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:02 2495
ber01-VHDL13_DWMO_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2691
ber01-VHDL13_DWMO_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:06 2691
ber01-VHDL13_DWMO_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:10 2638
ber01-VHDL13_DWMP_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2599
ber01-VHDL13_DWMP_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2867
ber01-VHDL13_DWMP_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:07 2998
ber01-VHDL13_DWMP_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 3203
ber01-VHDL13_DWMP_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:02 2793
ber01-VHDL13_DWMP_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 3164
ber01-VHDL13_DWMP_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:08 3164
ber01-VHDL13_DWMP_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:05 3082
ber01-VHDL13_DWOG_051700-2511051700-dsw--0-ia5 05-Nov-2025 19:00:07 3201
ber01-VHDL13_DWOG_060300-2511060300-dsw--0-ia5 06-Nov-2025 04:00:07 3245
ber01-VHDL13_DWOG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:11 3358
ber01-VHDL13_DWOG_061700-2511061700-dsw--0-ia5 06-Nov-2025 19:00:07 2988
ber01-VHDL13_DWOG_070300-2511070300-dsw--0-ia5 07-Nov-2025 04:00:02 3547
ber01-VHDL13_DWOG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:02 3232
ber01-VHDL13_DWOG_070800_COR-2511070800-dsw--0-ia5 07-Nov-2025 15:55:07 3221
ber01-VHDL13_DWOH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:28:23 2208
ber01-VHDL13_DWOH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:28:17 2288
ber01-VHDL13_DWOH_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:58:22 2272
ber01-VHDL13_DWOH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:28:27 2304
ber01-VHDL13_DWOH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:28:23 2080
ber01-VHDL13_DWOH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:28:22 1960
ber01-VHDL13_DWOH_070400-2511070400-dsw--0-ia5 07-Nov-2025 05:58:17 1869
ber01-VHDL13_DWOH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:28:21 1981
ber01-VHDL13_DWOI_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:28:23 2381
ber01-VHDL13_DWOI_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:28:23 2405
ber01-VHDL13_DWOI_060400-2511060400-dsw--0-ia5 06-Nov-2025 05:58:22 2422
ber01-VHDL13_DWOI_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:28:21 2444
ber01-VHDL13_DWOI_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:28:17 2239
ber01-VHDL13_DWOI_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:28:18 2360
ber01-VHDL13_DWOI_070400-2511070400-dsw--0-ia5 07-Nov-2025 05:58:23 2283
ber01-VHDL13_DWOI_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:28:17 2385
ber01-VHDL13_DWON_051742-2511051742-dsw--0-ia5 05-Nov-2025 17:43:01 3250
ber01-VHDL13_DWON_051852-2511051852-dsw--0-ia5 05-Nov-2025 18:52:47 3250
ber01-VHDL13_DWON_052038-2511052038-dsw--0-ia5 05-Nov-2025 20:38:00 3250
ber01-VHDL13_DWON_060335-2511060335-dsw--0-ia5 06-Nov-2025 03:35:36 3255
ber01-VHDL13_DWON_060619-2511060619-dsw--0-ia5 06-Nov-2025 06:19:07 3378
ber01-VHDL13_DWON_061016-2511061016-dsw--0-ia5 06-Nov-2025 10:16:56 3378
ber01-VHDL13_DWON_061433-2511061433-dsw--0-ia5 06-Nov-2025 14:33:22 3070
ber01-VHDL13_DWON_061621-2511061621-dsw--0-ia5 06-Nov-2025 16:21:07 3047
ber01-VHDL13_DWON_061732-2511061732-dsw--0-ia5 06-Nov-2025 17:33:01 3047
ber01-VHDL13_DWON_062056-2511062056-dsw--0-ia5 06-Nov-2025 20:56:42 3083
ber01-VHDL13_DWON_062203-2511062203-dsw--0-ia5 06-Nov-2025 22:03:56 3073
ber01-VHDL13_DWON_070112-2511070112-dsw--0-ia5 07-Nov-2025 01:12:12 3341
ber01-VHDL13_DWON_070352-2511070352-dsw--0-ia5 07-Nov-2025 03:52:11 3386
ber01-VHDL13_DWON_070627-2511070627-dsw--0-ia5 07-Nov-2025 06:27:56 2863
ber01-VHDL13_DWON_070708-2511070708-dsw--0-ia5 07-Nov-2025 07:08:41 2953
ber01-VHDL13_DWON_070925-2511070925-dsw--0-ia5 07-Nov-2025 09:25:31 3035
ber01-VHDL13_DWON_071553-2511071553-dsw--0-ia5 07-Nov-2025 15:53:42 2904
ber01-VHDL13_DWON_071630-2511071630-dsw--0-ia5 07-Nov-2025 16:30:02 3137
ber01-VHDL13_DWPG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 1797
ber01-VHDL13_DWPG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 1953
ber01-VHDL13_DWPG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:07 1968
ber01-VHDL13_DWPG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:01 2196
ber01-VHDL13_DWPG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 1999
ber01-VHDL13_DWPG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2259
ber01-VHDL13_DWPG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:06 2082
ber01-VHDL13_DWPG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:02 2082
ber01-VHDL13_DWPH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 1584
ber01-VHDL13_DWPH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 1913
ber01-VHDL13_DWPH_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:07 1943
ber01-VHDL13_DWPH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:03 2197
ber01-VHDL13_DWPH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2174
ber01-VHDL13_DWPH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2321
ber01-VHDL13_DWPH_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:06 2268
ber01-VHDL13_DWPH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:02 2268
ber01-VHDL13_DWSG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:30:07 2170
ber01-VHDL13_DWSG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:30:06 2282
ber01-VHDL13_DWSG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:14 2692
ber01-VHDL13_DWSG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:30:10 2692
ber01-VHDL13_DWSG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:30:06 2115
ber01-VHDL13_DWSG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:30:07 2290
ber01-VHDL13_DWSG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:16 2281
ber01-VHDL13_DWSG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:30:02 2316
ber01-VHDL17_DWOG_061200-2511061200-dsw--0-ia5 06-Nov-2025 12:50:46 2615
ber01-VHDL17_DWOG_071200-2511071200-dsw--0-ia5 07-Nov-2025 11:54:22 2813
swis2-VHDL20_DWEG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2587
swis2-VHDL20_DWEG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:06 2617
swis2-VHDL20_DWEG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:15:07 2594
swis2-VHDL20_DWEG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2783
swis2-VHDL20_DWEG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:08 2408
swis2-VHDL20_DWEG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:09 2238
swis2-VHDL20_DWEG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:15:06 2191
swis2-VHDL20_DWEG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:06 2460
swis2-VHDL20_DWEH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2525
swis2-VHDL20_DWEH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:08 2566
swis2-VHDL20_DWEH_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:15:07 2817
swis2-VHDL20_DWEH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2851
swis2-VHDL20_DWEH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:08 2669
swis2-VHDL20_DWEH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:09 2719
swis2-VHDL20_DWEH_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:15:06 2679
swis2-VHDL20_DWEH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:08 2837
swis2-VHDL20_DWEI_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2785
swis2-VHDL20_DWEI_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:06 2747
swis2-VHDL20_DWEI_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:15:47 2778
swis2-VHDL20_DWEI_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2973
swis2-VHDL20_DWEI_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:08 2595
swis2-VHDL20_DWEI_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:06 2657
swis2-VHDL20_DWEI_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:15:47 2636
swis2-VHDL20_DWEI_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:06 2911
swis2-VHDL20_DWHG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2314
swis2-VHDL20_DWHG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:01 2309
swis2-VHDL20_DWHG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:16 2275
swis2-VHDL20_DWHG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2708
swis2-VHDL20_DWHG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:06 2770
swis2-VHDL20_DWHG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:02 3102
swis2-VHDL20_DWHG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:18 3071
swis2-VHDL20_DWHG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:06 3225
swis2-VHDL20_DWHH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2070
swis2-VHDL20_DWHH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:01 2146
swis2-VHDL20_DWHH_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:16 2138
swis2-VHDL20_DWHH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2552
swis2-VHDL20_DWHH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:06 2288
swis2-VHDL20_DWHH_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:02 2617
swis2-VHDL20_DWHH_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:18 2617
swis2-VHDL20_DWHH_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:06 2927
swis2-VHDL20_DWLG_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2576
swis2-VHDL20_DWLG_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:06 2867
swis2-VHDL20_DWLG_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:23 2827
swis2-VHDL20_DWLG_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 3122
swis2-VHDL20_DWLG_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:02 2662
swis2-VHDL20_DWLG_070200-2511070200-dsw--0-ia5 07-Nov-2025 03:45:06 2992
swis2-VHDL20_DWLG_070400-2511070400-dsw--0-ia5 07-Nov-2025 06:00:22 2940
swis2-VHDL20_DWLG_070800-2511070800-dsw--0-ia5 07-Nov-2025 09:45:06 3059
swis2-VHDL20_DWLH_051800-2511051800-dsw--0-ia5 05-Nov-2025 19:45:07 2154
swis2-VHDL20_DWLH_060200-2511060200-dsw--0-ia5 06-Nov-2025 03:45:06 2560
swis2-VHDL20_DWLH_060400-2511060400-dsw--0-ia5 06-Nov-2025 06:00:23 2509
swis2-VHDL20_DWLH_060800-2511060800-dsw--0-ia5 06-Nov-2025 09:45:07 2753
swis2-VHDL20_DWLH_061800-2511061800-dsw--0-ia5 06-Nov-2025 19:45:02 2305
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