Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Jun-2026 13:48:00 4057
FPDL13_DWMZ_220600 22-Jun-2026 12:40:46 3886
SXDL31_DWAV_210800 21-Jun-2026 08:13:45 9179
SXDL31_DWAV_211800 21-Jun-2026 17:05:19 9009
SXDL31_DWAV_220800 22-Jun-2026 06:56:00 14323
SXDL31_DWAV_221800 22-Jun-2026 16:57:34 4972
SXDL31_DWAV_LATEST 22-Jun-2026 16:57:34 4972
SXDL33_DWAV_210000 21-Jun-2026 10:36:37 14192
SXDL33_DWAV_220000 22-Jun-2026 09:40:59 6260
SXDL33_DWAV_LATEST 22-Jun-2026 09:40:59 6260
ber01-FWDL39_DWMS_211200-2606211200-dsw--0-ia5 21-Jun-2026 11:06:53 1169
ber01-FWDL39_DWMS_221200-2606221200-dsw--0-ia5 22-Jun-2026 11:31:17 1227
ber01-VHDL13_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3719
ber01-VHDL13_DWEG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:16 3338
ber01-VHDL13_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3725
ber01-VHDL13_DWEH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:12 3120
ber01-VHDL13_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3430
ber01-VHDL13_DWEI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:16 3187
ber01-VHDL13_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3615
ber01-VHDL13_DWHG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2801
ber01-VHDL13_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2871
ber01-VHDL13_DWHH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2439
ber01-VHDL13_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2810
ber01-VHDL13_DWLG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2162
ber01-VHDL13_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2707
ber01-VHDL13_DWLH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2084
ber01-VHDL13_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2760
ber01-VHDL13_DWLI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2125
ber01-VHDL13_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 3483
ber01-VHDL13_DWMO_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 3016
ber01-VHDL13_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL13_DWMP_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2875
ber01-VHDL13_DWOG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 4689
ber01-VHDL13_DWOG_211700-2606211700-dsw--0-ia5 21-Jun-2026 18:00:01 3993
ber01-VHDL13_DWOG_220300-2606220300-dsw--0-ia5 22-Jun-2026 03:00:02 3355
ber01-VHDL13_DWOG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 3574
ber01-VHDL13_DWOG_221700-2606221700-dsw--0-ia5 22-Jun-2026 18:00:02 3158
ber01-VHDL13_DWOG_230300-2606230300-dsw--0-ia5 23-Jun-2026 03:00:02 3391
ber01-VHDL13_DWON_210629-2606210629-dsw--0-ia5 21-Jun-2026 06:29:27 4007
ber01-VHDL13_DWON_210721-2606210721-dsw--0-ia5 21-Jun-2026 07:21:22 4143
ber01-VHDL13_DWON_210722-2606210722-dsw--0-ia5 21-Jun-2026 07:22:51 4147
ber01-VHDL13_DWON_211000-2606211000-dsw--0-ia5 21-Jun-2026 10:00:52 3894
ber01-VHDL13_DWON_211446-2606211446-dsw--0-ia5 21-Jun-2026 14:46:37 3864
ber01-VHDL13_DWON_211728-2606211728-dsw--0-ia5 21-Jun-2026 17:28:12 3283
ber01-VHDL13_DWON_220058-2606220058-dsw--0-ia5 22-Jun-2026 00:58:31 3823
ber01-VHDL13_DWON_220233-2606220233-dsw--0-ia5 22-Jun-2026 02:33:35 3823
ber01-VHDL13_DWON_220522-2606220522-dsw--0-ia5 22-Jun-2026 05:22:47 3355
ber01-VHDL13_DWON_220746-2606220746-dsw--0-ia5 22-Jun-2026 07:46:51 3355
ber01-VHDL13_DWON_221508-2606221508-dsw--0-ia5 22-Jun-2026 15:08:51 3298
ber01-VHDL13_DWON_221730-2606221730-dsw--0-ia5 22-Jun-2026 17:30:06 2849
ber01-VHDL13_DWON_230057-2606230057-dsw--0-ia5 23-Jun-2026 00:57:37 3245
ber01-VHDL13_DWON_230238-2606230238-dsw--0-ia5 23-Jun-2026 02:38:27 3245
ber01-VHDL13_DWON_230523-2606230523-dsw--0-ia5 23-Jun-2026 05:23:07 3235
ber01-VHDL13_DWON_230617-2606230617-dsw--0-ia5 23-Jun-2026 06:17:32 3274
ber01-VHDL13_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2496
ber01-VHDL13_DWPG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1798
ber01-VHDL13_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2126
ber01-VHDL13_DWPH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1944
ber01-VHDL13_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL13_DWSG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 3376
ber01-VHDL17_DWOG_211200-2606211200-dsw--0-ia5 21-Jun-2026 11:45:56 3174
ber01-VHDL17_DWOG_221200-2606221200-dsw--0-ia5 22-Jun-2026 11:10:17 3384
swis2-VHDL20_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1977
swis2-VHDL20_DWEG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2106
swis2-VHDL20_DWEG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1579
swis2-VHDL20_DWEG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:17 1557
swis2-VHDL20_DWEG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1931
swis2-VHDL20_DWEG_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1657
swis2-VHDL20_DWEG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1018
swis2-VHDL20_DWEG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1018
swis2-VHDL20_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2022
swis2-VHDL20_DWEH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2153
swis2-VHDL20_DWEH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:06 1402
swis2-VHDL20_DWEH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:17 1438
swis2-VHDL20_DWEH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1778
swis2-VHDL20_DWEH_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1799
swis2-VHDL20_DWEH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1028
swis2-VHDL20_DWEH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1028
swis2-VHDL20_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1884
swis2-VHDL20_DWEI_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2223
swis2-VHDL20_DWEI_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:06 1599
swis2-VHDL20_DWEI_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:21 1608
swis2-VHDL20_DWEI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1981
swis2-VHDL20_DWEI_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1773
swis2-VHDL20_DWEI_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1003
swis2-VHDL20_DWEI_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:01:21 1003
swis2-VHDL20_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 2030
swis2-VHDL20_DWHG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:45:01 1754
swis2-VHDL20_DWHG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:45:06 1350
swis2-VHDL20_DWHG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 1344
swis2-VHDL20_DWHG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:45:08 1361
swis2-VHDL20_DWHG_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:45:05 1498
swis2-VHDL20_DWHG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:45:13 987
swis2-VHDL20_DWHG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 980
swis2-VHDL20_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 1419
swis2-VHDL20_DWHH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:45:01 1095
swis2-VHDL20_DWHH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:45:06 991
swis2-VHDL20_DWHH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 988
swis2-VHDL20_DWHH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:45:08 1097
swis2-VHDL20_DWHH_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:45:05 1127
swis2-VHDL20_DWHH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:45:13 992
swis2-VHDL20_DWHH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 988
swis2-VHDL20_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1578
swis2-VHDL20_DWLG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:19 1378
swis2-VHDL20_DWLG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1179
swis2-VHDL20_DWLG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 866
swis2-VHDL20_DWLG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1077
swis2-VHDL20_DWLG_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:31:00 919
swis2-VHDL20_DWLG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 882
swis2-VHDL20_DWLG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 881
swis2-VHDL20_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1612
swis2-VHDL20_DWLH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1183
swis2-VHDL20_DWLH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1198
swis2-VHDL20_DWLH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 874
swis2-VHDL20_DWLH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1094
swis2-VHDL20_DWLH_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:31:00 923
swis2-VHDL20_DWLH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 886
swis2-VHDL20_DWLH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 908
swis2-VHDL20_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1700
swis2-VHDL20_DWLI_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1377
swis2-VHDL20_DWLI_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1177
swis2-VHDL20_DWLI_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 867
swis2-VHDL20_DWLI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1087
swis2-VHDL20_DWLI_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:31:00 920
swis2-VHDL20_DWLI_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 917
swis2-VHDL20_DWLI_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 916
swis2-VHDL20_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1806
swis2-VHDL20_DWMO_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:19 1743
swis2-VHDL20_DWMO_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1725
swis2-VHDL20_DWMO_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:02 1611
swis2-VHDL20_DWMO_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 1565
swis2-VHDL20_DWMO_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1303
swis2-VHDL20_DWMO_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1452
swis2-VHDL20_DWMO_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:02 1426
swis2-VHDL20_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 1709
swis2-VHDL20_DWMP_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1710
swis2-VHDL20_DWMP_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1598
swis2-VHDL20_DWMP_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:02 1428
swis2-VHDL20_DWMP_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 1537
swis2-VHDL20_DWMP_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1370
swis2-VHDL20_DWMP_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1328
swis2-VHDL20_DWMP_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:02 1293
swis2-VHDL20_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1445
swis2-VHDL20_DWPG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1053
swis2-VHDL20_DWPG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 836
swis2-VHDL20_DWPG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 773
swis2-VHDL20_DWPG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 978
swis2-VHDL20_DWPG_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:31:00 935
swis2-VHDL20_DWPG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 898
swis2-VHDL20_DWPG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 923
swis2-VHDL20_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1049
swis2-VHDL20_DWPH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 925
swis2-VHDL20_DWPH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 843
swis2-VHDL20_DWPH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 770
swis2-VHDL20_DWPH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 894
swis2-VHDL20_DWPH_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:31:00 932
swis2-VHDL20_DWPH_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:26 827
swis2-VHDL20_DWPH_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:12 892
swis2-VHDL20_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1607
swis2-VHDL20_DWSG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1676
swis2-VHDL20_DWSG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1580
swis2-VHDL20_DWSG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 1445
swis2-VHDL20_DWSG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1595
swis2-VHDL20_DWSG_221800-2606221800-dsw--0-ia5 22-Jun-2026 18:30:03 1301
swis2-VHDL20_DWSG_230200-2606230200-dsw--0-ia5 23-Jun-2026 02:30:01 1432
swis2-VHDL20_DWSG_230400-2606230400-dsw--0-ia5 23-Jun-2026 05:00:16 1429
wst04-VHDL20_DWEG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 251328
wst04-VHDL20_DWEG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:19 250641
wst04-VHDL20_DWEG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 248937
wst04-VHDL20_DWEG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 248350
wst04-VHDL20_DWEG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 249739
wst04-VHDL20_DWEG_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:13 247938
wst04-VHDL20_DWEG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 245146
wst04-VHDL20_DWEG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 244971
wst04-VHDL20_DWEH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 251448
wst04-VHDL20_DWEH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 248963
wst04-VHDL20_DWEH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 247723
wst04-VHDL20_DWEH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 247064
wst04-VHDL20_DWEH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 248708
wst04-VHDL20_DWEH_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:13 248050
wst04-VHDL20_DWEH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 245701
wst04-VHDL20_DWEH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 245494
wst04-VHDL20_DWEI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 363969
wst04-VHDL20_DWEI_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 368362
wst04-VHDL20_DWEI_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 367176
wst04-VHDL20_DWEI_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 366558
wst04-VHDL20_DWEI_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 367392
wst04-VHDL20_DWEI_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:18 353911
wst04-VHDL20_DWEI_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 350787
wst04-VHDL20_DWEI_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 350577
wst04-VHDL20_DWHG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 357125
wst04-VHDL20_DWHG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:45:11 353970
wst04-VHDL20_DWHG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:45:12 351253
wst04-VHDL20_DWHG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 350801
wst04-VHDL20_DWHG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:45:14 352203
wst04-VHDL20_DWHG_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:45:12 355086
wst04-VHDL20_DWHG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:45:13 353402
wst04-VHDL20_DWHG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 353413
wst04-VHDL20_DWHH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 328334
wst04-VHDL20_DWHH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:45:11 322707
wst04-VHDL20_DWHH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:45:12 322955
wst04-VHDL20_DWHH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 219072
wst04-VHDL20_DWHH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:45:14 322212
wst04-VHDL20_DWHH_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:45:12 322566
wst04-VHDL20_DWHH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:45:13 322416
wst04-VHDL20_DWHH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 218645
wst04-VHDL20_DWLG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 353321
wst04-VHDL20_DWLG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 351663
wst04-VHDL20_DWLG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 351932
wst04-VHDL20_DWLG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 351267
wst04-VHDL20_DWLG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 351545
wst04-VHDL20_DWLG_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:31:22 348857
wst04-VHDL20_DWLG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 348240
wst04-VHDL20_DWLG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 347503
wst04-VHDL20_DWLH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 343371
wst04-VHDL20_DWLH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 343471
wst04-VHDL20_DWLH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 343907
wst04-VHDL20_DWLH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 343024
wst04-VHDL20_DWLH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 343307
wst04-VHDL20_DWLH_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:31:22 345468
wst04-VHDL20_DWLH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:26 344859
wst04-VHDL20_DWLH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 344070
wst04-VHDL20_DWLI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:50 398790
wst04-VHDL20_DWLI_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 355868
wst04-VHDL20_DWLI_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:27 356126
wst04-VHDL20_DWLI_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 355497
wst04-VHDL20_DWLI_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:47 400384
wst04-VHDL20_DWLI_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:31:22 352879
wst04-VHDL20_DWLI_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 352278
wst04-VHDL20_DWLI_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:42 351494
wst04-VHDL20_DWMO_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 493573
wst04-VHDL20_DWMO_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 371880
wst04-VHDL20_DWMO_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:16 492903
wst04-VHDL20_DWMO_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 493006
wst04-VHDL20_DWMO_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:16 492102
wst04-VHDL20_DWMO_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:18 363864
wst04-VHDL20_DWMO_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 479183
wst04-VHDL20_DWMO_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 479365
wst04-VHDL20_DWMP_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:21 503869
wst04-VHDL20_DWMP_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 494450
wst04-VHDL20_DWMP_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:16 612612
wst04-VHDL20_DWMP_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 611994
wst04-VHDL20_DWMP_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:23 494097
wst04-VHDL20_DWMP_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:18 470550
wst04-VHDL20_DWMP_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 576731
wst04-VHDL20_DWMP_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:16 576851
wst04-VHDL20_DWPG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 394534
wst04-VHDL20_DWPG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 356703
wst04-VHDL20_DWPG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 250192
wst04-VHDL20_DWPG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:31 356354
wst04-VHDL20_DWPG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 401580
wst04-VHDL20_DWPG_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:31:27 351102
wst04-VHDL20_DWPG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 246122
wst04-VHDL20_DWPG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:30 349809
wst04-VHDL20_DWPH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 240225
wst04-VHDL20_DWPH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 235589
wst04-VHDL20_DWPH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 236017
wst04-VHDL20_DWPH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:31 235633
wst04-VHDL20_DWPH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 235642
wst04-VHDL20_DWPH_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:31:22 240865
wst04-VHDL20_DWPH_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:22 239856
wst04-VHDL20_DWPH_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:30 239260
wst04-VHDL20_DWSG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 361943
wst04-VHDL20_DWSG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 364380
wst04-VHDL20_DWSG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 363798
wst04-VHDL20_DWSG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 363504
wst04-VHDL20_DWSG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:18 364375
wst04-VHDL20_DWSG_221800-2606221800-omedes--0.pdf 22-Jun-2026 18:30:18 353336
wst04-VHDL20_DWSG_230200-2606230200-omedes--0.pdf 23-Jun-2026 02:30:14 353553
wst04-VHDL20_DWSG_230400-2606230400-omedes--0.pdf 23-Jun-2026 05:00:12 353571