Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Jul-2026 12:17:29 19622
FPDL13_DWMZ_280600 28-Jul-2026 15:08:18 5741
SXDL31_DWAV_271800 27-Jul-2026 15:08:16 3132
SXDL31_DWAV_280800 28-Jul-2026 10:17:24 5803
SXDL31_DWAV_281800 28-Jul-2026 15:54:40 4959
SXDL31_DWAV_290800 29-Jul-2026 08:47:28 7174
SXDL31_DWAV_LATEST 29-Jul-2026 08:47:28 7174
SXDL33_DWAV_280000 28-Jul-2026 10:13:04 8542
SXDL33_DWAV_290000 29-Jul-2026 09:26:39 12922
SXDL33_DWAV_LATEST 29-Jul-2026 09:26:39 12922
ber01-FWDL39_DWMS_281200-2607281200-dsw--0-ia5 28-Jul-2026 11:51:07 1590
ber01-FWDL39_DWMS_281200_COR-2607281200-dsw--0-ia5 28-Jul-2026 12:05:06 1544
ber01-FWDL39_DWMS_291200-2607291200-dsw--0-ia5 29-Jul-2026 11:38:38 1605
ber01-VHDL13_DWEG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:28:17 2467
ber01-VHDL13_DWEG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:17 3680
ber01-VHDL13_DWEH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:28:11 2338
ber01-VHDL13_DWEH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:27 3604
ber01-VHDL13_DWEI_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:28:11 2442
ber01-VHDL13_DWEI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:28:27 3732
ber01-VHDL13_DWHG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:06 2777
ber01-VHDL13_DWHG_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 09:39:15 2950
ber01-VHDL13_DWHG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3776
ber01-VHDL13_DWHH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:06 2722
ber01-VHDL13_DWHH_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 09:39:42 2863
ber01-VHDL13_DWHH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3769
ber01-VHDL13_DWLG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2511
ber01-VHDL13_DWLG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3478
ber01-VHDL13_DWLH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2937
ber01-VHDL13_DWLH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3523
ber01-VHDL13_DWLI_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2791
ber01-VHDL13_DWLI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3380
ber01-VHDL13_DWMO_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2718
ber01-VHDL13_DWMO_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3464
ber01-VHDL13_DWMP_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 3134
ber01-VHDL13_DWMP_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3594
ber01-VHDL13_DWOG_271700-2607271700-dsw--0-ia5 27-Jul-2026 18:00:04 3274
ber01-VHDL13_DWOG_280300-2607280300-dsw--0-ia5 28-Jul-2026 03:00:03 3181
ber01-VHDL13_DWOG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 3143
ber01-VHDL13_DWOG_281700-2607281700-dsw--0-ia5 28-Jul-2026 18:00:06 3726
ber01-VHDL13_DWOG_290300-2607290300-dsw--0-ia5 29-Jul-2026 03:00:24 4258
ber01-VHDL13_DWOG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 4100
ber01-VHDL13_DWON_271448-2607271448-dsw--0-ia5 27-Jul-2026 14:48:46 3262
ber01-VHDL13_DWON_271827-2607271827-dsw--0-ia5 27-Jul-2026 18:27:37 3163
ber01-VHDL13_DWON_272140-2607272140-dsw--0-ia5 27-Jul-2026 21:41:06 3027
ber01-VHDL13_DWON_280006-2607280006-dsw--0-ia5 28-Jul-2026 00:06:11 3470
ber01-VHDL13_DWON_280132-2607280132-dsw--0-ia5 28-Jul-2026 01:32:51 3488
ber01-VHDL13_DWON_280238-2607280238-dsw--0-ia5 28-Jul-2026 02:39:16 3488
ber01-VHDL13_DWON_280252-2607280252-dsw--0-ia5 28-Jul-2026 02:53:03 3435
ber01-VHDL13_DWON_280352-2607280352-dsw--0-ia5 28-Jul-2026 03:52:11 3435
ber01-VHDL13_DWON_280529-2607280529-dsw--0-ia5 28-Jul-2026 05:29:11 3850
ber01-VHDL13_DWON_280615-2607280615-dsw--0-ia5 28-Jul-2026 06:15:37 3774
ber01-VHDL13_DWON_280641-2607280641-dsw--0-ia5 28-Jul-2026 06:41:57 3799
ber01-VHDL13_DWON_281448-2607281448-dsw--0-ia5 28-Jul-2026 14:49:17 3940
ber01-VHDL13_DWON_281616-2607281616-dsw--0-ia5 28-Jul-2026 16:16:42 3311
ber01-VHDL13_DWON_281706-2607281706-dsw--0-ia5 28-Jul-2026 17:07:02 3311
ber01-VHDL13_DWON_281735-2607281735-dsw--0-ia5 28-Jul-2026 17:35:31 3311
ber01-VHDL13_DWON_281852-2607281852-dsw--0-ia5 28-Jul-2026 18:52:57 3604
ber01-VHDL13_DWON_282127-2607282127-dsw--0-ia5 28-Jul-2026 21:27:07 3622
ber01-VHDL13_DWON_290008-2607290008-dsw--0-ia5 29-Jul-2026 00:08:07 4150
ber01-VHDL13_DWON_290131-2607290131-dsw--0-ia5 29-Jul-2026 01:32:03 4042
ber01-VHDL13_DWON_290248-2607290248-dsw--0-ia5 29-Jul-2026 02:49:03 4042
ber01-VHDL13_DWON_290541-2607290541-dsw--0-ia5 29-Jul-2026 05:41:05 3628
ber01-VHDL13_DWON_290835-2607290835-dsw--0-ia5 29-Jul-2026 08:35:26 3580
ber01-VHDL13_DWPG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2580
ber01-VHDL13_DWPG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3352
ber01-VHDL13_DWPH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2790
ber01-VHDL13_DWPH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 3495
ber01-VHDL13_DWSG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 2606
ber01-VHDL13_DWSG_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 12:36:42 2649
ber01-VHDL13_DWSG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 3458
ber01-VHDL17_DWOG_281200-2607281200-dsw--0-ia5 28-Jul-2026 11:59:42 3278
ber01-VHDL17_DWOG_291200-2607291200-dsw--0-ia5 29-Jul-2026 11:05:32 2973
swis2-VHDL20_DWEG_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1043
swis2-VHDL20_DWEG_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:04 699
swis2-VHDL20_DWEG_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:01:21 709
swis2-VHDL20_DWEG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1125
swis2-VHDL20_DWEG_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:05 2062
swis2-VHDL20_DWEG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1616
swis2-VHDL20_DWEG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1633
swis2-VHDL20_DWEG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1891
swis2-VHDL20_DWEH_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1008
swis2-VHDL20_DWEH_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:04 711
swis2-VHDL20_DWEH_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:01:21 721
swis2-VHDL20_DWEH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1106
swis2-VHDL20_DWEH_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:05 2018
swis2-VHDL20_DWEH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1628
swis2-VHDL20_DWEH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1645
swis2-VHDL20_DWEH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1815
swis2-VHDL20_DWEI_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1062
swis2-VHDL20_DWEI_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:04 707
swis2-VHDL20_DWEI_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:01:21 717
swis2-VHDL20_DWEI_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1133
swis2-VHDL20_DWEI_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:05 2089
swis2-VHDL20_DWEI_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1634
swis2-VHDL20_DWEI_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:02:27 1634
swis2-VHDL20_DWEI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1909
swis2-VHDL20_DWHG_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:45:08 1034
swis2-VHDL20_DWHG_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:45:36 1008
swis2-VHDL20_DWHG_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:17 990
swis2-VHDL20_DWHG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:45:16 1216
swis2-VHDL20_DWHG_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 09:40:24 1422
swis2-VHDL20_DWHG_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:45:09 1848
swis2-VHDL20_DWHG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:45:20 1609
swis2-VHDL20_DWHG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1680
swis2-VHDL20_DWHG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:45:05 2369
swis2-VHDL20_DWHH_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:45:08 1304
swis2-VHDL20_DWHH_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:45:36 1014
swis2-VHDL20_DWHH_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:17 999
swis2-VHDL20_DWHH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:45:16 1232
swis2-VHDL20_DWHH_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 09:40:58 1406
swis2-VHDL20_DWHH_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:45:09 1905
swis2-VHDL20_DWHH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:45:20 1671
swis2-VHDL20_DWHH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1816
swis2-VHDL20_DWHH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:45:05 2463
swis2-VHDL20_DWLG_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:31:05 1497
swis2-VHDL20_DWLG_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:24 809
swis2-VHDL20_DWLG_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:11 802
swis2-VHDL20_DWLG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:24 1546
swis2-VHDL20_DWLG_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:31:07 1411
swis2-VHDL20_DWLG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1272
swis2-VHDL20_DWLG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1547
swis2-VHDL20_DWLG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1723
swis2-VHDL20_DWLH_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:31:05 1504
swis2-VHDL20_DWLH_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:24 816
swis2-VHDL20_DWLH_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:11 1145
swis2-VHDL20_DWLH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:24 1477
swis2-VHDL20_DWLH_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:31:07 1620
swis2-VHDL20_DWLH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1471
swis2-VHDL20_DWLH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1533
swis2-VHDL20_DWLH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1697
swis2-VHDL20_DWLI_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:31:05 1499
swis2-VHDL20_DWLI_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:24 811
swis2-VHDL20_DWLI_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:11 1140
swis2-VHDL20_DWLI_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:24 1472
swis2-VHDL20_DWLI_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:31:07 1616
swis2-VHDL20_DWLI_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1466
swis2-VHDL20_DWLI_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1528
swis2-VHDL20_DWLI_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1704
swis2-VHDL20_DWMO_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1211
swis2-VHDL20_DWMO_271800_COR-2607271800-dsw--0-ia5 27-Jul-2026 18:42:43 2805
swis2-VHDL20_DWMO_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:11 912
swis2-VHDL20_DWMO_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:03 889
swis2-VHDL20_DWMO_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1278
swis2-VHDL20_DWMO_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:05 1450
swis2-VHDL20_DWMO_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:01 1397
swis2-VHDL20_DWMO_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:01 1509
swis2-VHDL20_DWMO_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 1699
swis2-VHDL20_DWMP_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1368
swis2-VHDL20_DWMP_271800_COR-2607271800-dsw--0-ia5 27-Jul-2026 18:44:06 2909
swis2-VHDL20_DWMP_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:11 1140
swis2-VHDL20_DWMP_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:03 1079
swis2-VHDL20_DWMP_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1334
swis2-VHDL20_DWMP_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:05 1356
swis2-VHDL20_DWMP_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:07 1237
swis2-VHDL20_DWMP_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:01 1409
swis2-VHDL20_DWMP_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:06 1672
swis2-VHDL20_DWPG_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:31:05 1517
swis2-VHDL20_DWPG_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:24 830
swis2-VHDL20_DWPG_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:11 813
swis2-VHDL20_DWPG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:24 1578
swis2-VHDL20_DWPG_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:31:07 1432
swis2-VHDL20_DWPG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1293
swis2-VHDL20_DWPG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1542
swis2-VHDL20_DWPG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1718
swis2-VHDL20_DWPH_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:31:05 1633
swis2-VHDL20_DWPH_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:24 963
swis2-VHDL20_DWPH_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:11 835
swis2-VHDL20_DWPH_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:24 1290
swis2-VHDL20_DWPH_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:31:07 1635
swis2-VHDL20_DWPH_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:26 1534
swis2-VHDL20_DWPH_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:16 1609
swis2-VHDL20_DWPH_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:22 1786
swis2-VHDL20_DWSG_271800-2607271800-dsw--0-ia5 27-Jul-2026 18:30:09 1143
swis2-VHDL20_DWSG_280200-2607280200-dsw--0-ia5 28-Jul-2026 02:30:04 803
swis2-VHDL20_DWSG_280400-2607280400-dsw--0-ia5 28-Jul-2026 05:00:17 768
swis2-VHDL20_DWSG_280800-2607280800-dsw--0-ia5 28-Jul-2026 08:30:02 1091
swis2-VHDL20_DWSG_280800_COR-2607280800-dsw--0-ia5 28-Jul-2026 12:36:42 1163
swis2-VHDL20_DWSG_281800-2607281800-dsw--0-ia5 28-Jul-2026 18:30:01 1303
swis2-VHDL20_DWSG_290200-2607290200-dsw--0-ia5 29-Jul-2026 02:30:01 1216
swis2-VHDL20_DWSG_290400-2607290400-dsw--0-ia5 29-Jul-2026 05:00:26 1237
swis2-VHDL20_DWSG_290800-2607290800-dsw--0-ia5 29-Jul-2026 08:30:07 1594
wst04-VHDL20_DWEG_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:30:17 243782
wst04-VHDL20_DWEG_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:11 242417
wst04-VHDL20_DWEG_280400-2607280400-omedes--0.pdf 28-Jul-2026 05:00:11 242271
wst04-VHDL20_DWEG_280800-2607280800-omedes--0.pdf 28-Jul-2026 08:30:14 243802
wst04-VHDL20_DWEG_281800-2607281800-omedes--0.pdf 28-Jul-2026 18:30:12 243095
wst04-VHDL20_DWEG_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:20 241956
wst04-VHDL20_DWEG_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:16 241796
wst04-VHDL20_DWEG_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:12 242729
wst04-VHDL20_DWEH_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:30:17 241997
wst04-VHDL20_DWEH_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:11 240972
wst04-VHDL20_DWEH_280400-2607280400-omedes--0.pdf 28-Jul-2026 05:00:11 241066
wst04-VHDL20_DWEH_280800-2607280800-omedes--0.pdf 28-Jul-2026 08:30:14 242549
wst04-VHDL20_DWEH_281800-2607281800-omedes--0.pdf 28-Jul-2026 18:30:16 241754
wst04-VHDL20_DWEH_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:20 240990
wst04-VHDL20_DWEH_290400-2607290400-omedes--0.pdf 29-Jul-2026 05:00:22 241093
wst04-VHDL20_DWEH_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:12 241898
wst04-VHDL20_DWEI_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:30:17 352546
wst04-VHDL20_DWEI_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:11 351775
wst04-VHDL20_DWEI_280400-2607280400-omedes--0.pdf 28-Jul-2026 05:00:11 351553
wst04-VHDL20_DWEI_280800-2607280800-omedes--0.pdf 28-Jul-2026 08:30:18 352552
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wst04-VHDL20_DWLH_280400-2607280400-omedes--0.pdf 28-Jul-2026 05:00:41 347713
wst04-VHDL20_DWLH_280800-2607280800-omedes--0.pdf 28-Jul-2026 08:30:44 349069
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wst04-VHDL20_DWMO_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:30:17 361119
wst04-VHDL20_DWMO_271800_COR-2607271800-omedes-..> 27-Jul-2026 18:42:51 471132
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wst04-VHDL20_DWMP_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:30:17 470637
wst04-VHDL20_DWMP_271800_COR-2607271800-omedes-..> 27-Jul-2026 18:44:16 581212
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wst04-VHDL20_DWMP_280800-2607280800-omedes--0.pdf 28-Jul-2026 08:30:24 470501
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wst04-VHDL20_DWPG_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:24 244533
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wst04-VHDL20_DWPG_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:26 251311
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wst04-VHDL20_DWPH_271800-2607271800-omedes--0.pdf 27-Jul-2026 18:31:27 244370
wst04-VHDL20_DWPH_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:24 242997
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wst04-VHDL20_DWSG_280200-2607280200-omedes--0.pdf 28-Jul-2026 02:30:11 352254
wst04-VHDL20_DWSG_280400-2607280400-omedes--0.pdf 28-Jul-2026 05:00:11 352300
wst04-VHDL20_DWSG_280800-2607280800-omedes--0.pdf 28-Jul-2026 12:36:46 360231
wst04-VHDL20_DWSG_281800-2607281800-omedes--0.pdf 28-Jul-2026 18:30:12 361107
wst04-VHDL20_DWSG_290200-2607290200-omedes--0.pdf 29-Jul-2026 02:30:11 359729
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wst04-VHDL20_DWSG_290800-2607290800-omedes--0.pdf 29-Jul-2026 08:30:16 362045