Index of /weather/text_forecasts/txt/
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FPDL13_DWMZ_190600 19-Nov-2024 14:36 5214
SXDL31_DWAV_191800 19-Nov-2024 17:51 7626
SXDL31_DWAV_200800 20-Nov-2024 07:59 9558
SXDL31_DWAV_201800 20-Nov-2024 17:52 12179
SXDL31_DWAV_210800 21-Nov-2024 09:23 8794
SXDL31_DWAV_LATEST 21-Nov-2024 09:23 8794
SXDL33_DWAV_200000 20-Nov-2024 10:38 6858
SXDL33_DWAV_210000 21-Nov-2024 10:45 9252
SXDL33_DWAV_LATEST 21-Nov-2024 10:45 9252
ber01-FWDL39_DWMS_201230-2411201230-dsw--0-ia5 20-Nov-2024 12:37 1579
ber01-FWDL39_DWMS_211230-2411211230-dsw--0-ia5 21-Nov-2024 12:55 2104
ber01-VHDL13_DWEH_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:28 4590
ber01-VHDL13_DWEH_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:28 4709
ber01-VHDL13_DWEH_200400-2411200400-dsw--0-ia5 20-Nov-2024 05:58 4726
ber01-VHDL13_DWEH_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:28 4562
ber01-VHDL13_DWEH_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:28 3944
ber01-VHDL13_DWEH_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:28 3672
ber01-VHDL13_DWEH_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:58 3841
ber01-VHDL13_DWEH_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:28 4386
ber01-VHDL13_DWHG_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3653
ber01-VHDL13_DWHG_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3230
ber01-VHDL13_DWHG_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3490
ber01-VHDL13_DWHG_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3762
ber01-VHDL13_DWHG_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3852
ber01-VHDL13_DWHG_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3768
ber01-VHDL13_DWHG_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 3774
ber01-VHDL13_DWHG_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3926
ber01-VHDL13_DWHH_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3183
ber01-VHDL13_DWHH_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3254
ber01-VHDL13_DWHH_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3389
ber01-VHDL13_DWHH_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3396
ber01-VHDL13_DWHH_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3495
ber01-VHDL13_DWHH_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3631
ber01-VHDL13_DWHH_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 3643
ber01-VHDL13_DWHH_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3634
ber01-VHDL13_DWLG_191433-2411191433-dsw--0-ia5 19-Nov-2024 14:33 3319
ber01-VHDL13_DWLG_191533-2411191533-dsw--0-ia5 19-Nov-2024 15:33 3333
ber01-VHDL13_DWLG_191633-2411191633-dsw--0-ia5 19-Nov-2024 16:33 3374
ber01-VHDL13_DWLG_191733-2411191733-dsw--0-ia5 19-Nov-2024 17:33 3285
ber01-VHDL13_DWLG_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3062
ber01-VHDL13_DWLG_191833-2411191833-dsw--0-ia5 19-Nov-2024 18:33 3285
ber01-VHDL13_DWLG_192033-2411192033-dsw--0-ia5 19-Nov-2024 20:33 3069
ber01-VHDL13_DWLG_192133-2411192133-dsw--0-ia5 19-Nov-2024 21:33 3069
ber01-VHDL13_DWLG_200133-2411200133-dsw--0-ia5 20-Nov-2024 01:33 3165
ber01-VHDL13_DWLG_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3397
ber01-VHDL13_DWLG_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3360
ber01-VHDL13_DWLG_200633-2411200633-dsw--0-ia5 20-Nov-2024 06:33 3366
ber01-VHDL13_DWLG_200733-2411200733-dsw--0-ia5 20-Nov-2024 07:33 3366
ber01-VHDL13_DWLG_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3797
ber01-VHDL13_DWLG_200833-2411200833-dsw--0-ia5 20-Nov-2024 08:33 3806
ber01-VHDL13_DWLG_201033-2411201033-dsw--0-ia5 20-Nov-2024 10:33 3806
ber01-VHDL13_DWLG_201133-2411201133-dsw--0-ia5 20-Nov-2024 11:33 3806
ber01-VHDL13_DWLG_201233-2411201233-dsw--0-ia5 20-Nov-2024 12:33 3806
ber01-VHDL13_DWLG_201433-2411201433-dsw--0-ia5 20-Nov-2024 14:33 3644
ber01-VHDL13_DWLG_201533-2411201533-dsw--0-ia5 20-Nov-2024 15:33 3644
ber01-VHDL13_DWLG_201633-2411201633-dsw--0-ia5 20-Nov-2024 16:33 3720
ber01-VHDL13_DWLG_201733-2411201733-dsw--0-ia5 20-Nov-2024 17:33 3720
ber01-VHDL13_DWLG_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3380
ber01-VHDL13_DWLG_201833-2411201833-dsw--0-ia5 20-Nov-2024 18:33 3396
ber01-VHDL13_DWLG_202033-2411202033-dsw--0-ia5 20-Nov-2024 20:33 3386
ber01-VHDL13_DWLG_202133-2411202133-dsw--0-ia5 20-Nov-2024 21:33 3386
ber01-VHDL13_DWLG_210133-2411210133-dsw--0-ia5 21-Nov-2024 01:33 3606
ber01-VHDL13_DWLG_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3746
ber01-VHDL13_DWLG_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:59 3411
ber01-VHDL13_DWLG_210633-2411210633-dsw--0-ia5 21-Nov-2024 06:33 3417
ber01-VHDL13_DWLG_210733-2411210733-dsw--0-ia5 21-Nov-2024 07:33 2928
ber01-VHDL13_DWLG_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3047
ber01-VHDL13_DWLG_210833-2411210833-dsw--0-ia5 21-Nov-2024 08:33 2928
ber01-VHDL13_DWLG_211033-2411211033-dsw--0-ia5 21-Nov-2024 10:33 3195
ber01-VHDL13_DWLG_211133-2411211133-dsw--0-ia5 21-Nov-2024 11:33 3195
ber01-VHDL13_DWLG_211233-2411211233-dsw--0-ia5 21-Nov-2024 12:33 3195
ber01-VHDL13_DWLH_191433-2411191433-dsw--0-ia5 19-Nov-2024 14:33 3451
ber01-VHDL13_DWLH_191533-2411191533-dsw--0-ia5 19-Nov-2024 15:33 3447
ber01-VHDL13_DWLH_191633-2411191633-dsw--0-ia5 19-Nov-2024 16:33 3683
ber01-VHDL13_DWLH_191733-2411191733-dsw--0-ia5 19-Nov-2024 17:33 3629
ber01-VHDL13_DWLH_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 2813
ber01-VHDL13_DWLH_191833-2411191833-dsw--0-ia5 19-Nov-2024 18:33 3629
ber01-VHDL13_DWLH_192033-2411192033-dsw--0-ia5 19-Nov-2024 20:33 2823
ber01-VHDL13_DWLH_192133-2411192133-dsw--0-ia5 19-Nov-2024 21:33 2823
ber01-VHDL13_DWLH_200133-2411200133-dsw--0-ia5 20-Nov-2024 01:33 2802
ber01-VHDL13_DWLH_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3477
ber01-VHDL13_DWLH_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3442
ber01-VHDL13_DWLH_200633-2411200633-dsw--0-ia5 20-Nov-2024 06:33 3451
ber01-VHDL13_DWLH_200733-2411200733-dsw--0-ia5 20-Nov-2024 07:33 3451
ber01-VHDL13_DWLH_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3571
ber01-VHDL13_DWLH_200833-2411200833-dsw--0-ia5 20-Nov-2024 08:33 3580
ber01-VHDL13_DWLH_201033-2411201033-dsw--0-ia5 20-Nov-2024 10:33 3580
ber01-VHDL13_DWLH_201133-2411201133-dsw--0-ia5 20-Nov-2024 11:33 3580
ber01-VHDL13_DWLH_201233-2411201233-dsw--0-ia5 20-Nov-2024 12:33 3538
ber01-VHDL13_DWLH_201433-2411201433-dsw--0-ia5 20-Nov-2024 14:33 3446
ber01-VHDL13_DWLH_201533-2411201533-dsw--0-ia5 20-Nov-2024 15:33 3446
ber01-VHDL13_DWLH_201633-2411201633-dsw--0-ia5 20-Nov-2024 16:33 3446
ber01-VHDL13_DWLH_201733-2411201733-dsw--0-ia5 20-Nov-2024 17:33 3446
ber01-VHDL13_DWLH_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3003
ber01-VHDL13_DWLH_201833-2411201833-dsw--0-ia5 20-Nov-2024 18:33 2988
ber01-VHDL13_DWLH_202033-2411202033-dsw--0-ia5 20-Nov-2024 20:33 3012
ber01-VHDL13_DWLH_202133-2411202133-dsw--0-ia5 20-Nov-2024 21:33 3012
ber01-VHDL13_DWLH_210133-2411210133-dsw--0-ia5 21-Nov-2024 01:33 3115
ber01-VHDL13_DWLH_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3065
ber01-VHDL13_DWLH_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:59 2902
ber01-VHDL13_DWLH_210633-2411210633-dsw--0-ia5 21-Nov-2024 06:33 2911
ber01-VHDL13_DWLH_210733-2411210733-dsw--0-ia5 21-Nov-2024 07:33 2860
ber01-VHDL13_DWLH_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 2984
ber01-VHDL13_DWLH_210833-2411210833-dsw--0-ia5 21-Nov-2024 08:33 2860
ber01-VHDL13_DWLH_211033-2411211033-dsw--0-ia5 21-Nov-2024 10:33 3123
ber01-VHDL13_DWLH_211133-2411211133-dsw--0-ia5 21-Nov-2024 11:33 3123
ber01-VHDL13_DWLH_211233-2411211233-dsw--0-ia5 21-Nov-2024 12:33 3123
ber01-VHDL13_DWLI_191433-2411191433-dsw--0-ia5 19-Nov-2024 14:33 3247
ber01-VHDL13_DWLI_191533-2411191533-dsw--0-ia5 19-Nov-2024 15:33 3247
ber01-VHDL13_DWLI_191633-2411191633-dsw--0-ia5 19-Nov-2024 16:33 3540
ber01-VHDL13_DWLI_191733-2411191733-dsw--0-ia5 19-Nov-2024 17:33 3541
ber01-VHDL13_DWLI_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3093
ber01-VHDL13_DWLI_191833-2411191833-dsw--0-ia5 19-Nov-2024 18:33 3541
ber01-VHDL13_DWLI_192033-2411192033-dsw--0-ia5 19-Nov-2024 20:33 3100
ber01-VHDL13_DWLI_192133-2411192133-dsw--0-ia5 19-Nov-2024 21:33 3100
ber01-VHDL13_DWLI_200133-2411200133-dsw--0-ia5 20-Nov-2024 01:33 3118
ber01-VHDL13_DWLI_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3300
ber01-VHDL13_DWLI_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3275
ber01-VHDL13_DWLI_200633-2411200633-dsw--0-ia5 20-Nov-2024 06:33 3278
ber01-VHDL13_DWLI_200733-2411200733-dsw--0-ia5 20-Nov-2024 07:33 3278
ber01-VHDL13_DWLI_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3453
ber01-VHDL13_DWLI_200833-2411200833-dsw--0-ia5 20-Nov-2024 08:33 3459
ber01-VHDL13_DWLI_201033-2411201033-dsw--0-ia5 20-Nov-2024 10:33 3459
ber01-VHDL13_DWLI_201133-2411201133-dsw--0-ia5 20-Nov-2024 11:33 3459
ber01-VHDL13_DWLI_201233-2411201233-dsw--0-ia5 20-Nov-2024 12:33 3393
ber01-VHDL13_DWLI_201433-2411201433-dsw--0-ia5 20-Nov-2024 14:33 3155
ber01-VHDL13_DWLI_201533-2411201533-dsw--0-ia5 20-Nov-2024 15:33 3155
ber01-VHDL13_DWLI_201633-2411201633-dsw--0-ia5 20-Nov-2024 16:33 3155
ber01-VHDL13_DWLI_201733-2411201733-dsw--0-ia5 20-Nov-2024 17:33 3155
ber01-VHDL13_DWLI_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 2843
ber01-VHDL13_DWLI_201833-2411201833-dsw--0-ia5 20-Nov-2024 18:33 2851
ber01-VHDL13_DWLI_202033-2411202033-dsw--0-ia5 20-Nov-2024 20:33 2849
ber01-VHDL13_DWLI_202133-2411202133-dsw--0-ia5 20-Nov-2024 21:33 2849
ber01-VHDL13_DWLI_210133-2411210133-dsw--0-ia5 21-Nov-2024 01:33 2983
ber01-VHDL13_DWLI_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3045
ber01-VHDL13_DWLI_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:59 2839
ber01-VHDL13_DWLI_210633-2411210633-dsw--0-ia5 21-Nov-2024 06:33 2842
ber01-VHDL13_DWLI_210733-2411210733-dsw--0-ia5 21-Nov-2024 07:33 2695
ber01-VHDL13_DWLI_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 2834
ber01-VHDL13_DWLI_210833-2411210833-dsw--0-ia5 21-Nov-2024 08:33 2695
ber01-VHDL13_DWLI_211033-2411211033-dsw--0-ia5 21-Nov-2024 10:33 2978
ber01-VHDL13_DWLI_211133-2411211133-dsw--0-ia5 21-Nov-2024 11:33 2978
ber01-VHDL13_DWLI_211233-2411211233-dsw--0-ia5 21-Nov-2024 12:33 2978
ber01-VHDL13_DWMG_191300-2411191300-dsw--0-ia5 19-Nov-2024 13:30 4922
ber01-VHDL13_DWMG_191400-2411191400-dsw--0-ia5 19-Nov-2024 14:30 4922
ber01-VHDL13_DWMG_191500-2411191500-dsw--0-ia5 19-Nov-2024 15:30 4922
ber01-VHDL13_DWMG_191600-2411191600-dsw--0-ia5 19-Nov-2024 16:30 4922
ber01-VHDL13_DWMG_191700-2411191700-dsw--0-ia5 19-Nov-2024 17:30 4922
ber01-VHDL13_DWMG_191800-2411191800-dsw--0-ia5 19-Nov-2024 18:30 4922
ber01-VHDL13_DWMG_191900-2411191900-dsw--0-ia5 19-Nov-2024 19:30 4367
ber01-VHDL13_DWMG_192000-2411192000-dsw--0-ia5 19-Nov-2024 20:30 4368
ber01-VHDL13_DWMG_192100-2411192100-dsw--0-ia5 19-Nov-2024 21:30 4368
ber01-VHDL13_DWMG_192200-2411192200-dsw--0-ia5 19-Nov-2024 22:30 4368
ber01-VHDL13_DWMG_192300-2411192300-dsw--0-ia5 19-Nov-2024 23:30 5141
ber01-VHDL13_DWMG_200000-2411200000-dsw--0-ia5 20-Nov-2024 00:30 5141
ber01-VHDL13_DWMG_200100-2411200100-dsw--0-ia5 20-Nov-2024 01:30 5141
ber01-VHDL13_DWMG_200200-2411200200-dsw--0-ia5 20-Nov-2024 02:30 5141
ber01-VHDL13_DWMG_200300-2411200300-dsw--0-ia5 20-Nov-2024 03:30 4757
ber01-VHDL13_DWMG_200400-2411200400-dsw--0-ia5 20-Nov-2024 04:30 4635
ber01-VHDL13_DWMG_200500-2411200500-dsw--0-ia5 20-Nov-2024 05:30 4219
ber01-VHDL13_DWMG_200600-2411200600-dsw--0-ia5 20-Nov-2024 06:30 4219
ber01-VHDL13_DWMG_200700-2411200700-dsw--0-ia5 20-Nov-2024 07:30 4219
ber01-VHDL13_DWMG_200800-2411200800-dsw--0-ia5 20-Nov-2024 08:30 4219
ber01-VHDL13_DWMG_200900-2411200900-dsw--0-ia5 20-Nov-2024 09:30 4066
ber01-VHDL13_DWMG_201000-2411201000-dsw--0-ia5 20-Nov-2024 10:30 4066
ber01-VHDL13_DWMG_201100-2411201100-dsw--0-ia5 20-Nov-2024 11:30 4066
ber01-VHDL13_DWMG_201200-2411201200-dsw--0-ia5 20-Nov-2024 12:30 4066
ber01-VHDL13_DWMG_201300-2411201300-dsw--0-ia5 20-Nov-2024 13:30 4066
ber01-VHDL13_DWMG_201400-2411201400-dsw--0-ia5 20-Nov-2024 14:30 4066
ber01-VHDL13_DWMG_201500-2411201500-dsw--0-ia5 20-Nov-2024 15:30 4066
ber01-VHDL13_DWMG_201600-2411201600-dsw--0-ia5 20-Nov-2024 16:30 4066
ber01-VHDL13_DWMG_201700-2411201700-dsw--0-ia5 20-Nov-2024 17:30 4066
ber01-VHDL13_DWMG_201800-2411201800-dsw--0-ia5 20-Nov-2024 18:30 4066
ber01-VHDL13_DWMG_201900-2411201900-dsw--0-ia5 20-Nov-2024 19:30 3432
ber01-VHDL13_DWMG_202000-2411202000-dsw--0-ia5 20-Nov-2024 20:30 3829
ber01-VHDL13_DWMG_202100-2411202100-dsw--0-ia5 20-Nov-2024 21:30 3829
ber01-VHDL13_DWMG_202200-2411202200-dsw--0-ia5 20-Nov-2024 22:30 3829
ber01-VHDL13_DWMG_202300-2411202300-dsw--0-ia5 20-Nov-2024 23:30 3886
ber01-VHDL13_DWMG_210000-2411210000-dsw--0-ia5 21-Nov-2024 00:30 3881
ber01-VHDL13_DWMG_210100-2411210100-dsw--0-ia5 21-Nov-2024 01:30 3897
ber01-VHDL13_DWMG_210200-2411210200-dsw--0-ia5 21-Nov-2024 02:30 3897
ber01-VHDL13_DWMG_210300-2411210300-dsw--0-ia5 21-Nov-2024 03:30 3897
ber01-VHDL13_DWMG_210400-2411210400-dsw--0-ia5 21-Nov-2024 04:30 3897
ber01-VHDL13_DWMG_210500-2411210500-dsw--0-ia5 21-Nov-2024 05:30 3897
ber01-VHDL13_DWMG_210600-2411210600-dsw--0-ia5 21-Nov-2024 06:30 4004
ber01-VHDL13_DWMG_210700-2411210700-dsw--0-ia5 21-Nov-2024 07:30 3992
ber01-VHDL13_DWMG_210800-2411210800-dsw--0-ia5 21-Nov-2024 08:30 3992
ber01-VHDL13_DWMG_210900-2411210900-dsw--0-ia5 21-Nov-2024 09:30 4518
ber01-VHDL13_DWMG_211000-2411211000-dsw--0-ia5 21-Nov-2024 10:30 4518
ber01-VHDL13_DWMG_211100-2411211100-dsw--0-ia5 21-Nov-2024 11:30 4518
ber01-VHDL13_DWMG_211200-2411211200-dsw--0-ia5 21-Nov-2024 12:30 4518
ber01-VHDL13_DWMO_191300-2411191300-dsw--0-ia5 19-Nov-2024 13:30 4256
ber01-VHDL13_DWMO_191400-2411191400-dsw--0-ia5 19-Nov-2024 14:30 4210
ber01-VHDL13_DWMO_191500-2411191500-dsw--0-ia5 19-Nov-2024 15:30 4210
ber01-VHDL13_DWMO_191600-2411191600-dsw--0-ia5 19-Nov-2024 16:30 4210
ber01-VHDL13_DWMO_191700-2411191700-dsw--0-ia5 19-Nov-2024 17:30 4210
ber01-VHDL13_DWMO_191800-2411191800-dsw--0-ia5 19-Nov-2024 18:30 4210
ber01-VHDL13_DWMO_191900-2411191900-dsw--0-ia5 19-Nov-2024 19:30 3889
ber01-VHDL13_DWMO_192000-2411192000-dsw--0-ia5 19-Nov-2024 20:30 3889
ber01-VHDL13_DWMO_192100-2411192100-dsw--0-ia5 19-Nov-2024 21:30 3889
ber01-VHDL13_DWMO_192200-2411192200-dsw--0-ia5 19-Nov-2024 22:30 3889
ber01-VHDL13_DWMO_192300-2411192300-dsw--0-ia5 19-Nov-2024 23:30 4223
ber01-VHDL13_DWMO_200000-2411200000-dsw--0-ia5 20-Nov-2024 00:30 4223
ber01-VHDL13_DWMO_200100-2411200100-dsw--0-ia5 20-Nov-2024 01:30 4223
ber01-VHDL13_DWMO_200200-2411200200-dsw--0-ia5 20-Nov-2024 02:30 4223
ber01-VHDL13_DWMO_200300-2411200300-dsw--0-ia5 20-Nov-2024 03:30 4223
ber01-VHDL13_DWMO_200400-2411200400-dsw--0-ia5 20-Nov-2024 04:30 3760
ber01-VHDL13_DWMO_200500-2411200500-dsw--0-ia5 20-Nov-2024 05:30 3748
ber01-VHDL13_DWMO_200600-2411200600-dsw--0-ia5 20-Nov-2024 06:30 3748
ber01-VHDL13_DWMO_200700-2411200700-dsw--0-ia5 20-Nov-2024 07:30 3748
ber01-VHDL13_DWMO_200800-2411200800-dsw--0-ia5 20-Nov-2024 08:30 3748
ber01-VHDL13_DWMO_200900-2411200900-dsw--0-ia5 20-Nov-2024 09:30 3748
ber01-VHDL13_DWMO_201000-2411201000-dsw--0-ia5 20-Nov-2024 10:30 3901
ber01-VHDL13_DWMO_201100-2411201100-dsw--0-ia5 20-Nov-2024 11:30 3901
ber01-VHDL13_DWMO_201200-2411201200-dsw--0-ia5 20-Nov-2024 12:30 3901
ber01-VHDL13_DWMO_201300-2411201300-dsw--0-ia5 20-Nov-2024 13:30 3901
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ber01-VHDL13_DWMP_201100-2411201100-dsw--0-ia5 20-Nov-2024 11:30 4220
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ber01-VHDL13_DWMP_201500-2411201500-dsw--0-ia5 20-Nov-2024 15:30 4220
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ber01-VHDL13_DWOH_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:28 3569
ber01-VHDL13_DWOH_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:58 3795
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ber01-VHDL13_DWOI_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:28 4561
ber01-VHDL13_DWOI_200400-2411200400-dsw--0-ia5 20-Nov-2024 05:58 4340
ber01-VHDL13_DWOI_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:28 4647
ber01-VHDL13_DWOI_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:28 3834
ber01-VHDL13_DWOI_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:28 3174
ber01-VHDL13_DWOI_210400-2411210400-dsw--0-ia5 21-Nov-2024 05:58 3485
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ber01-VHDL13_DWON_200012-2411200012-dsw--0-ia5 20-Nov-2024 00:12 4030
ber01-VHDL13_DWON_200345-2411200345-dsw--0-ia5 20-Nov-2024 03:45 4030
ber01-VHDL13_DWON_200428-2411200428-dsw--0-ia5 20-Nov-2024 04:28 4399
ber01-VHDL13_DWON_200622-2411200622-dsw--0-ia5 20-Nov-2024 06:22 4398
ber01-VHDL13_DWON_200702-2411200702-dsw--0-ia5 20-Nov-2024 07:02 4377
ber01-VHDL13_DWON_200913-2411200913-dsw--0-ia5 20-Nov-2024 09:13 4293
ber01-VHDL13_DWON_201729-2411201729-dsw--0-ia5 20-Nov-2024 17:29 3788
ber01-VHDL13_DWON_201754-2411201754-dsw--0-ia5 20-Nov-2024 17:54 4146
ber01-VHDL13_DWON_202152-2411202152-dsw--0-ia5 20-Nov-2024 21:52 4222
ber01-VHDL13_DWON_210250-2411210250-dsw--0-ia5 21-Nov-2024 02:50 5114
ber01-VHDL13_DWON_210316-2411210316-dsw--0-ia5 21-Nov-2024 03:16 5134
ber01-VHDL13_DWON_210628-2411210628-dsw--0-ia5 21-Nov-2024 06:28 4811
ber01-VHDL13_DWON_210703-2411210703-dsw--0-ia5 21-Nov-2024 07:03 5105
ber01-VHDL13_DWON_211119-2411211119-dsw--0-ia5 21-Nov-2024 11:19 5105
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ber01-VHDL13_DWPG_191830-2411191830-dsw--0-ia5 19-Nov-2024 18:30 3171
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ber01-VHDL13_DWPG_192130-2411192130-dsw--0-ia5 19-Nov-2024 21:30 2942
ber01-VHDL13_DWPG_200130-2411200130-dsw--0-ia5 20-Nov-2024 01:30 2973
ber01-VHDL13_DWPG_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 2816
ber01-VHDL13_DWPG_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3169
ber01-VHDL13_DWPG_200730-2411200730-dsw--0-ia5 20-Nov-2024 07:30 3167
ber01-VHDL13_DWPG_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3178
ber01-VHDL13_DWPG_200830-2411200830-dsw--0-ia5 20-Nov-2024 08:30 3167
ber01-VHDL13_DWPG_201030-2411201030-dsw--0-ia5 20-Nov-2024 10:30 3177
ber01-VHDL13_DWPG_201130-2411201130-dsw--0-ia5 20-Nov-2024 11:30 3177
ber01-VHDL13_DWPG_201230-2411201230-dsw--0-ia5 20-Nov-2024 12:30 3177
ber01-VHDL13_DWPG_201330-2411201330-dsw--0-ia5 20-Nov-2024 13:30 3177
ber01-VHDL13_DWPG_201430-2411201430-dsw--0-ia5 20-Nov-2024 14:30 3171
ber01-VHDL13_DWPG_201530-2411201530-dsw--0-ia5 20-Nov-2024 15:30 3171
ber01-VHDL13_DWPG_201630-2411201630-dsw--0-ia5 20-Nov-2024 16:30 3171
ber01-VHDL13_DWPG_201730-2411201730-dsw--0-ia5 20-Nov-2024 17:30 3171
ber01-VHDL13_DWPG_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3172
ber01-VHDL13_DWPG_201800_COR-2411201800-dsw--0-ia5 20-Nov-2024 20:14 2497
ber01-VHDL13_DWPG_201830-2411201830-dsw--0-ia5 20-Nov-2024 18:30 3171
ber01-VHDL13_DWPG_202030-2411202030-dsw--0-ia5 20-Nov-2024 20:30 2492
ber01-VHDL13_DWPG_202130-2411202130-dsw--0-ia5 20-Nov-2024 21:30 2492
ber01-VHDL13_DWPG_210130-2411210130-dsw--0-ia5 21-Nov-2024 01:30 2987
ber01-VHDL13_DWPG_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 2988
ber01-VHDL13_DWPG_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 2754
ber01-VHDL13_DWPG_210730-2411210730-dsw--0-ia5 21-Nov-2024 07:30 2752
ber01-VHDL13_DWPG_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 2818
ber01-VHDL13_DWPG_210830-2411210830-dsw--0-ia5 21-Nov-2024 08:30 2752
ber01-VHDL13_DWPG_211030-2411211030-dsw--0-ia5 21-Nov-2024 10:30 2817
ber01-VHDL13_DWPG_211130-2411211130-dsw--0-ia5 21-Nov-2024 11:30 2817
ber01-VHDL13_DWPG_211230-2411211230-dsw--0-ia5 21-Nov-2024 12:30 2817
ber01-VHDL13_DWPH_191330-2411191330-dsw--0-ia5 19-Nov-2024 13:30 3767
ber01-VHDL13_DWPH_191430-2411191430-dsw--0-ia5 19-Nov-2024 14:30 3767
ber01-VHDL13_DWPH_191530-2411191530-dsw--0-ia5 19-Nov-2024 15:30 3767
ber01-VHDL13_DWPH_191630-2411191630-dsw--0-ia5 19-Nov-2024 16:30 3913
ber01-VHDL13_DWPH_191730-2411191730-dsw--0-ia5 19-Nov-2024 17:30 3380
ber01-VHDL13_DWPH_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3171
ber01-VHDL13_DWPH_191830-2411191830-dsw--0-ia5 19-Nov-2024 18:30 3380
ber01-VHDL13_DWPH_192030-2411192030-dsw--0-ia5 19-Nov-2024 20:30 3171
ber01-VHDL13_DWPH_192130-2411192130-dsw--0-ia5 19-Nov-2024 21:30 3171
ber01-VHDL13_DWPH_200130-2411200130-dsw--0-ia5 20-Nov-2024 01:30 3376
ber01-VHDL13_DWPH_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3815
ber01-VHDL13_DWPH_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3812
ber01-VHDL13_DWPH_200730-2411200730-dsw--0-ia5 20-Nov-2024 07:30 3812
ber01-VHDL13_DWPH_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3846
ber01-VHDL13_DWPH_200830-2411200830-dsw--0-ia5 20-Nov-2024 08:30 3812
ber01-VHDL13_DWPH_201030-2411201030-dsw--0-ia5 20-Nov-2024 10:30 3846
ber01-VHDL13_DWPH_201130-2411201130-dsw--0-ia5 20-Nov-2024 11:30 3846
ber01-VHDL13_DWPH_201230-2411201230-dsw--0-ia5 20-Nov-2024 12:30 3846
ber01-VHDL13_DWPH_201330-2411201330-dsw--0-ia5 20-Nov-2024 13:30 3846
ber01-VHDL13_DWPH_201430-2411201430-dsw--0-ia5 20-Nov-2024 14:30 3887
ber01-VHDL13_DWPH_201530-2411201530-dsw--0-ia5 20-Nov-2024 15:30 3887
ber01-VHDL13_DWPH_201630-2411201630-dsw--0-ia5 20-Nov-2024 16:30 3887
ber01-VHDL13_DWPH_201730-2411201730-dsw--0-ia5 20-Nov-2024 17:30 3887
ber01-VHDL13_DWPH_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3887
ber01-VHDL13_DWPH_201800_COR-2411201800-dsw--0-ia5 20-Nov-2024 20:15 3273
ber01-VHDL13_DWPH_201830-2411201830-dsw--0-ia5 20-Nov-2024 18:30 3887
ber01-VHDL13_DWPH_202030-2411202030-dsw--0-ia5 20-Nov-2024 20:30 3269
ber01-VHDL13_DWPH_202130-2411202130-dsw--0-ia5 20-Nov-2024 21:30 3269
ber01-VHDL13_DWPH_210130-2411210130-dsw--0-ia5 21-Nov-2024 01:30 3623
ber01-VHDL13_DWPH_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3625
ber01-VHDL13_DWPH_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 3344
ber01-VHDL13_DWPH_210730-2411210730-dsw--0-ia5 21-Nov-2024 07:30 3344
ber01-VHDL13_DWPH_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3618
ber01-VHDL13_DWPH_210830-2411210830-dsw--0-ia5 21-Nov-2024 08:30 3344
ber01-VHDL13_DWPH_211030-2411211030-dsw--0-ia5 21-Nov-2024 10:30 3618
ber01-VHDL13_DWPH_211130-2411211130-dsw--0-ia5 21-Nov-2024 11:30 3618
ber01-VHDL13_DWPH_211230-2411211230-dsw--0-ia5 21-Nov-2024 12:30 3618
ber01-VHDL13_DWSG_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3941
ber01-VHDL13_DWSG_200200-2411200200-dsw--0-ia5 20-Nov-2024 03:30 3586
ber01-VHDL13_DWSG_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3588
ber01-VHDL13_DWSG_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3650
ber01-VHDL13_DWSG_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3864
ber01-VHDL13_DWSG_210200-2411210200-dsw--0-ia5 21-Nov-2024 03:30 3829
ber01-VHDL13_DWSG_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 3826
ber01-VHDL13_DWSG_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3940
ber01-VHDL13_DWSN_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 2973
ber01-VHDL13_DWSN_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 2365
ber01-VHDL13_DWSN_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 2675
ber01-VHDL13_DWSN_201800-2411201800-dsw--0-ia5 20-Nov-2024 20:03 2940
ber01-VHDL13_DWSN_201800_COR-2411201800-dsw--0-ia5 20-Nov-2024 20:03 3060
ber01-VHDL13_DWSN_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 2756
ber01-VHDL13_DWSN_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 2682
ber01-VHDL13_DWSO_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3948
ber01-VHDL13_DWSO_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 3596
ber01-VHDL13_DWSO_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3361
ber01-VHDL13_DWSO_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3356
ber01-VHDL13_DWSO_201800_COR-2411201800-dsw--0-ia5 20-Nov-2024 20:03 3459
ber01-VHDL13_DWSO_210400-2411210400-dsw--0-ia5 21-Nov-2024 06:00 3617
ber01-VHDL13_DWSO_210800-2411210800-dsw--0-ia5 21-Nov-2024 09:30 3699
ber01-VHDL13_DWSP_191800-2411191800-dsw--0-ia5 19-Nov-2024 19:30 3043
ber01-VHDL13_DWSP_200400-2411200400-dsw--0-ia5 20-Nov-2024 06:00 2841
ber01-VHDL13_DWSP_200800-2411200800-dsw--0-ia5 20-Nov-2024 09:30 3225
ber01-VHDL13_DWSP_201800-2411201800-dsw--0-ia5 20-Nov-2024 19:30 3220
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wst04-VHDL20_DWHG_191800-2411191800-oflxs888--0..> 19-Nov-2024 19:45 353937
wst04-VHDL20_DWHG_200200-2411200200-oflxs888--0..> 20-Nov-2024 03:45 352874
wst04-VHDL20_DWHG_200400-2411200400-oflxs888--0..> 20-Nov-2024 06:00 352932
wst04-VHDL20_DWHG_200800-2411200800-oflxs888--0..> 20-Nov-2024 09:45 349296
wst04-VHDL20_DWHG_201800-2411201800-oflxs888--0..> 20-Nov-2024 19:45 348272
wst04-VHDL20_DWHG_210200-2411210200-oflxs888--0..> 21-Nov-2024 03:45 348258
wst04-VHDL20_DWHG_210400-2411210400-oflxs888--0..> 21-Nov-2024 06:00 348226
wst04-VHDL20_DWHG_210800-2411210800-oflxs888--0..> 21-Nov-2024 09:45 346270
wst04-VHDL20_DWHH_191800-2411191800-oflxs888--0..> 19-Nov-2024 19:45 337606
wst04-VHDL20_DWHH_200200-2411200200-oflxs888--0..> 20-Nov-2024 03:45 337039
wst04-VHDL20_DWHH_200400-2411200400-oflxs888--0..> 20-Nov-2024 06:00 337205
wst04-VHDL20_DWHH_200800-2411200800-oflxs888--0..> 20-Nov-2024 09:45 341984
wst04-VHDL20_DWHH_201800-2411201800-oflxs888--0..> 20-Nov-2024 19:45 341421
wst04-VHDL20_DWHH_210200-2411210200-oflxs888--0..> 21-Nov-2024 03:45 342432
wst04-VHDL20_DWHH_210400-2411210400-oflxs888--0..> 21-Nov-2024 06:00 342490
wst04-VHDL20_DWHH_210800-2411210800-oflxs888--0..> 21-Nov-2024 09:45 345566
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wst04-VHDL20_DWMO_210200-2411210200-omedes--0.pdf 21-Nov-2024 03:45 426392
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wst04-VHDL20_DWMP_191800-2411191800-omedes--0.pdf 19-Nov-2024 19:45 559145
wst04-VHDL20_DWMP_200200-2411200200-omedes--0.pdf 20-Nov-2024 03:45 556544
wst04-VHDL20_DWMP_200400-2411200400-omedes--0.pdf 20-Nov-2024 06:15 558639
wst04-VHDL20_DWMP_200800-2411200800-omedes--0.pdf 20-Nov-2024 09:45 560477
wst04-VHDL20_DWMP_201800-2411201800-omedes--0.pdf 20-Nov-2024 19:45 558969
wst04-VHDL20_DWMP_210200-2411210200-omedes--0.pdf 21-Nov-2024 03:45 558607
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wst04-VHDL20_DWMP_210800-2411210800-omedes--0.pdf 21-Nov-2024 09:45 544664
wst04-VHDL20_DWPG_191800-2411191800-oflxs892--0..> 19-Nov-2024 19:45 353526
wst04-VHDL20_DWPG_200200-2411200200-oflxs892--0..> 20-Nov-2024 03:45 352037
wst04-VHDL20_DWPG_200400-2411200400-oflxs892--0..> 20-Nov-2024 06:00 352595
wst04-VHDL20_DWPG_200800-2411200800-oflxs892--0..> 20-Nov-2024 09:45 392984
wst04-VHDL20_DWPG_201800-2411201800-oflxs892--0..> 20-Nov-2024 19:45 348638
wst04-VHDL20_DWPG_201800_COR-2411201800-oflxs89..> 20-Nov-2024 20:16 348349
wst04-VHDL20_DWPG_210200-2411210200-oflxs892--0..> 21-Nov-2024 03:45 348645
wst04-VHDL20_DWPG_210400-2411210400-oflxs892--0..> 21-Nov-2024 06:00 348368
wst04-VHDL20_DWPG_210800-2411210800-oflxs892--0..> 21-Nov-2024 09:45 388897
wst04-VHDL20_DWPH_191800-2411191800-oflxs892--0..> 19-Nov-2024 19:45 300793
wst04-VHDL20_DWPH_200200-2411200200-oflxs892--0..> 20-Nov-2024 03:45 257035
wst04-VHDL20_DWPH_200400-2411200400-oflxs892--0..> 20-Nov-2024 06:00 257018
wst04-VHDL20_DWPH_200800-2411200800-oflxs892--0..> 20-Nov-2024 09:45 301120
wst04-VHDL20_DWPH_201800-2411201800-oflxs892--0..> 20-Nov-2024 19:45 301403
wst04-VHDL20_DWPH_201800_COR-2411201800-oflxs89..> 20-Nov-2024 20:17 300624
wst04-VHDL20_DWPH_210200-2411210200-oflxs892--0..> 21-Nov-2024 03:45 256210
wst04-VHDL20_DWPH_210400-2411210400-oflxs892--0..> 21-Nov-2024 06:00 256003
wst04-VHDL20_DWPH_210800-2411210800-oflxs892--0..> 21-Nov-2024 09:45 303334
wst04-VHDL20_DWSG_191800-2411191800-omedes--0.pdf 19-Nov-2024 19:45 367438
wst04-VHDL20_DWSG_200200-2411200200-omedes--0.pdf 20-Nov-2024 03:45 365831
wst04-VHDL20_DWSG_200400-2411200400-omedes--0.pdf 20-Nov-2024 06:15 366169
wst04-VHDL20_DWSG_200800-2411200800-omedes--0.pdf 20-Nov-2024 09:45 354538
wst04-VHDL20_DWSG_201800-2411201800-omedes--0.pdf 20-Nov-2024 19:45 354811
wst04-VHDL20_DWSG_210200-2411210200-omedes--0.pdf 21-Nov-2024 03:45 355421
wst04-VHDL20_DWSG_210400-2411210400-omedes--0.pdf 21-Nov-2024 06:15 354691
wst04-VHDL20_DWSG_210800-2411210800-omedes--0.pdf 21-Nov-2024 09:45 358491