Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Sep-2026 10:10:48 20959
FPDL13_DWMZ_140600 14-Sep-2026 12:20:24 4106
SXDL31_DWAV_130800 13-Sep-2026 07:19:55 10193
SXDL31_DWAV_131800 13-Sep-2026 17:09:24 3769
SXDL31_DWAV_140800 14-Sep-2026 08:28:24 12072
SXDL31_DWAV_141800 14-Sep-2026 16:55:19 10876
SXDL31_DWAV_LATEST 14-Sep-2026 16:55:19 10876
SXDL33_DWAV_130000 13-Sep-2026 10:06:19 5976
SXDL33_DWAV_140000 14-Sep-2026 09:43:03 13602
SXDL33_DWAV_LATEST 14-Sep-2026 09:43:03 13602
ber01-FWDL39_DWMS_131200-2609131200-dsw--0-ia5 13-Sep-2026 09:58:23 1203
ber01-FWDL39_DWMS_141200-2609141200-dsw--0-ia5 14-Sep-2026 11:45:40 1558
ber01-VHDL13_DWEG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:28:19 2968
ber01-VHDL13_DWEG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:12 2811
ber01-VHDL13_DWEH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:28:19 3097
ber01-VHDL13_DWEH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:18 3001
ber01-VHDL13_DWEI_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:28:19 2973
ber01-VHDL13_DWEI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:28:18 2723
ber01-VHDL13_DWHG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 3220
ber01-VHDL13_DWHG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3338
ber01-VHDL13_DWHH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 2918
ber01-VHDL13_DWHH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3246
ber01-VHDL13_DWLG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2162
ber01-VHDL13_DWLG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2278
ber01-VHDL13_DWLH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2180
ber01-VHDL13_DWLH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2282
ber01-VHDL13_DWLI_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2124
ber01-VHDL13_DWLI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2313
ber01-VHDL13_DWMO_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2690
ber01-VHDL13_DWMO_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 3072
ber01-VHDL13_DWMP_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 3147
ber01-VHDL13_DWMP_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2861
ber01-VHDL13_DWOG_130300-2609130300-dsw--0-ia5 13-Sep-2026 03:01:56 4586
ber01-VHDL13_DWOG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 4300
ber01-VHDL13_DWOG_131700-2609131700-dsw--0-ia5 13-Sep-2026 18:00:05 3536
ber01-VHDL13_DWOG_140300-2609140300-dsw--0-ia5 14-Sep-2026 03:02:48 4054
ber01-VHDL13_DWOG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:17 3657
ber01-VHDL13_DWOG_141700-2609141700-dsw--0-ia5 14-Sep-2026 18:00:04 3851
ber01-VHDL13_DWON_130006-2609130006-dsw--0-ia5 13-Sep-2026 00:06:58 4473
ber01-VHDL13_DWON_130144-2609130144-dsw--0-ia5 13-Sep-2026 01:45:16 4469
ber01-VHDL13_DWON_130246-2609130246-dsw--0-ia5 13-Sep-2026 02:48:31 4495
ber01-VHDL13_DWON_130525-2609130525-dsw--0-ia5 13-Sep-2026 05:25:49 4387
ber01-VHDL13_DWON_130617-2609130617-dsw--0-ia5 13-Sep-2026 06:17:43 4387
ber01-VHDL13_DWON_130808-2609130808-dsw--0-ia5 13-Sep-2026 08:08:53 4387
ber01-VHDL13_DWON_131502-2609131502-dsw--0-ia5 13-Sep-2026 15:02:19 3316
ber01-VHDL13_DWON_131632-2609131632-dsw--0-ia5 13-Sep-2026 16:32:24 3316
ber01-VHDL13_DWON_131821-2609131821-dsw--0-ia5 13-Sep-2026 18:21:48 3617
ber01-VHDL13_DWON_132117-2609132117-dsw--0-ia5 13-Sep-2026 21:17:24 3595
ber01-VHDL13_DWON_140005-2609140005-dsw--0-ia5 14-Sep-2026 00:05:14 4272
ber01-VHDL13_DWON_140133-2609140133-dsw--0-ia5 14-Sep-2026 01:33:34 4248
ber01-VHDL13_DWON_140246-2609140246-dsw--0-ia5 14-Sep-2026 02:49:01 4248
ber01-VHDL13_DWON_140529-2609140529-dsw--0-ia5 14-Sep-2026 05:29:54 4152
ber01-VHDL13_DWON_140601-2609140601-dsw--0-ia5 14-Sep-2026 06:01:49 4204
ber01-VHDL13_DWON_141117-2609141117-dsw--0-ia5 14-Sep-2026 11:18:03 4084
ber01-VHDL13_DWON_141445-2609141445-dsw--0-ia5 14-Sep-2026 14:47:13 3959
ber01-VHDL13_DWON_141713-2609141713-dsw--0-ia5 14-Sep-2026 17:13:34 3746
ber01-VHDL13_DWON_141838-2609141838-dsw--0-ia5 14-Sep-2026 18:38:34 3893
ber01-VHDL13_DWON_142129-2609142129-dsw--0-ia5 14-Sep-2026 21:29:33 3879
ber01-VHDL13_DWPG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2119
ber01-VHDL13_DWPG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2134
ber01-VHDL13_DWPH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 2183
ber01-VHDL13_DWPH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2229
ber01-VHDL13_DWSG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 2875
ber01-VHDL13_DWSG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 2958
ber01-VHDL17_DWOG_131200-2609131200-dsw--0-ia5 13-Sep-2026 11:38:04 2843
ber01-VHDL17_DWOG_141200-2609141200-dsw--0-ia5 14-Sep-2026 11:23:43 3294
swis2-VHDL20_DWEG_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 1140
swis2-VHDL20_DWEG_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:01:29 1113
swis2-VHDL20_DWEG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 1487
swis2-VHDL20_DWEG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1405
swis2-VHDL20_DWEG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1074
swis2-VHDL20_DWEG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1064
swis2-VHDL20_DWEG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1413
swis2-VHDL20_DWEG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1547
swis2-VHDL20_DWEH_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 1142
swis2-VHDL20_DWEH_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:01:29 1145
swis2-VHDL20_DWEH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 1514
swis2-VHDL20_DWEH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1459
swis2-VHDL20_DWEH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1135
swis2-VHDL20_DWEH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1121
swis2-VHDL20_DWEH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1461
swis2-VHDL20_DWEH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 1613
swis2-VHDL20_DWEI_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 1150
swis2-VHDL20_DWEI_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:01:29 1135
swis2-VHDL20_DWEI_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 1509
swis2-VHDL20_DWEI_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1428
swis2-VHDL20_DWEI_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 1098
swis2-VHDL20_DWEI_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:01:28 1088
swis2-VHDL20_DWEI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1434
swis2-VHDL20_DWEI_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1329
swis2-VHDL20_DWHG_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:46:18 1033
swis2-VHDL20_DWHG_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 1030
swis2-VHDL20_DWHG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:45:28 1608
swis2-VHDL20_DWHG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:45:09 1609
swis2-VHDL20_DWHG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:46:16 1432
swis2-VHDL20_DWHG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1419
swis2-VHDL20_DWHG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:45:33 1677
swis2-VHDL20_DWHG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:45:11 1795
swis2-VHDL20_DWHH_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:46:18 1039
swis2-VHDL20_DWHH_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 1039
swis2-VHDL20_DWHH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:45:28 1487
swis2-VHDL20_DWHH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:45:09 1607
swis2-VHDL20_DWHH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:46:16 1358
swis2-VHDL20_DWHH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1330
swis2-VHDL20_DWHH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:45:33 1569
swis2-VHDL20_DWHH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:45:11 1689
swis2-VHDL20_DWLG_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:41 915
swis2-VHDL20_DWLG_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 788
swis2-VHDL20_DWLG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:24 896
swis2-VHDL20_DWLG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 947
swis2-VHDL20_DWLG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 821
swis2-VHDL20_DWLG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 769
swis2-VHDL20_DWLG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 877
swis2-VHDL20_DWLG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1082
swis2-VHDL20_DWLH_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:41 1059
swis2-VHDL20_DWLH_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 800
swis2-VHDL20_DWLH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:24 921
swis2-VHDL20_DWLH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 949
swis2-VHDL20_DWLH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 813
swis2-VHDL20_DWLH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 761
swis2-VHDL20_DWLH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 901
swis2-VHDL20_DWLH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1070
swis2-VHDL20_DWLI_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:41 917
swis2-VHDL20_DWLI_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 778
swis2-VHDL20_DWLI_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:24 899
swis2-VHDL20_DWLI_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 930
swis2-VHDL20_DWLI_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 806
swis2-VHDL20_DWLI_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 754
swis2-VHDL20_DWLI_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 894
swis2-VHDL20_DWLI_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1064
swis2-VHDL20_DWMO_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 991
swis2-VHDL20_DWMO_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:03 1027
swis2-VHDL20_DWMO_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 1289
swis2-VHDL20_DWMO_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1259
swis2-VHDL20_DWMO_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 945
swis2-VHDL20_DWMO_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:03 947
swis2-VHDL20_DWMO_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1281
swis2-VHDL20_DWMO_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 1599
swis2-VHDL20_DWMP_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 1061
swis2-VHDL20_DWMP_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:03 1086
swis2-VHDL20_DWMP_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:04 1477
swis2-VHDL20_DWMP_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1477
swis2-VHDL20_DWMP_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 970
swis2-VHDL20_DWMP_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:03 947
swis2-VHDL20_DWMP_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1253
swis2-VHDL20_DWMP_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:08 2156
swis2-VHDL20_DWPG_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:41 946
swis2-VHDL20_DWPG_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 809
swis2-VHDL20_DWPG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:24 932
swis2-VHDL20_DWPG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 960
swis2-VHDL20_DWPG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 821
swis2-VHDL20_DWPG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 769
swis2-VHDL20_DWPG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 911
swis2-VHDL20_DWPG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1095
swis2-VHDL20_DWPH_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:41 948
swis2-VHDL20_DWPH_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 811
swis2-VHDL20_DWPH_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:24 934
swis2-VHDL20_DWPH_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:31:07 962
swis2-VHDL20_DWPH_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:31 824
swis2-VHDL20_DWPH_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:13 772
swis2-VHDL20_DWPH_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:27 914
swis2-VHDL20_DWPH_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:31:16 1083
swis2-VHDL20_DWSG_130200-2609130200-dsw--0-ia5 13-Sep-2026 02:30:11 930
swis2-VHDL20_DWSG_130400-2609130400-dsw--0-ia5 13-Sep-2026 05:00:19 953
swis2-VHDL20_DWSG_130800-2609130800-dsw--0-ia5 13-Sep-2026 08:30:10 1123
swis2-VHDL20_DWSG_131800-2609131800-dsw--0-ia5 13-Sep-2026 18:30:08 1183
swis2-VHDL20_DWSG_140200-2609140200-dsw--0-ia5 14-Sep-2026 02:30:03 851
swis2-VHDL20_DWSG_140400-2609140400-dsw--0-ia5 14-Sep-2026 05:00:19 1147
swis2-VHDL20_DWSG_140800-2609140800-dsw--0-ia5 14-Sep-2026 08:30:04 1421
swis2-VHDL20_DWSG_141800-2609141800-dsw--0-ia5 14-Sep-2026 18:30:04 1564
wst04-VHDL20_DWEG_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:17 246350
wst04-VHDL20_DWEG_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:13 246150
wst04-VHDL20_DWEG_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:14 247232
wst04-VHDL20_DWEG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:12 250951
wst04-VHDL20_DWEG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 249885
wst04-VHDL20_DWEG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 249904
wst04-VHDL20_DWEG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 250897
wst04-VHDL20_DWEG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:23 242247
wst04-VHDL20_DWEH_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:17 242171
wst04-VHDL20_DWEH_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:13 241898
wst04-VHDL20_DWEH_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:14 243048
wst04-VHDL20_DWEH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:12 247475
wst04-VHDL20_DWEH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 246706
wst04-VHDL20_DWEH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 246942
wst04-VHDL20_DWEH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 247976
wst04-VHDL20_DWEH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 237987
wst04-VHDL20_DWEI_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:17 355714
wst04-VHDL20_DWEI_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:19 355528
wst04-VHDL20_DWEI_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:24 356802
wst04-VHDL20_DWEI_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 357411
wst04-VHDL20_DWEI_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 356219
wst04-VHDL20_DWEI_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 356204
wst04-VHDL20_DWEI_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 357362
wst04-VHDL20_DWEI_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 344414
wst04-VHDL20_DWHG_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:46:18 355068
wst04-VHDL20_DWHG_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:19 354854
wst04-VHDL20_DWHG_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:45:28 357436
wst04-VHDL20_DWHG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:45:14 343271
wst04-VHDL20_DWHG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:46:16 342451
wst04-VHDL20_DWHG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 342904
wst04-VHDL20_DWHG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:45:33 343826
wst04-VHDL20_DWHG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:45:13 344221
wst04-VHDL20_DWHH_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:46:18 341656
wst04-VHDL20_DWHH_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:19 235077
wst04-VHDL20_DWHH_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:45:28 343206
wst04-VHDL20_DWHH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:45:14 338246
wst04-VHDL20_DWHH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:46:16 337679
wst04-VHDL20_DWHH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 237384
wst04-VHDL20_DWHH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:45:33 338346
wst04-VHDL20_DWHH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:45:13 341964
wst04-VHDL20_DWLG_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:41 339854
wst04-VHDL20_DWLG_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:43 339597
wst04-VHDL20_DWLG_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:48 339675
wst04-VHDL20_DWLG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 340063
wst04-VHDL20_DWLG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 340364
wst04-VHDL20_DWLG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 339862
wst04-VHDL20_DWLG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 339950
wst04-VHDL20_DWLG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 335626
wst04-VHDL20_DWLH_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:41 345612
wst04-VHDL20_DWLH_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:43 344829
wst04-VHDL20_DWLH_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:48 344951
wst04-VHDL20_DWLH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 336821
wst04-VHDL20_DWLH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 337110
wst04-VHDL20_DWLH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 336591
wst04-VHDL20_DWLH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 336740
wst04-VHDL20_DWLH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 336752
wst04-VHDL20_DWLI_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:41 337448
wst04-VHDL20_DWLI_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:43 337165
wst04-VHDL20_DWLI_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:48 381859
wst04-VHDL20_DWLI_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 343444
wst04-VHDL20_DWLI_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 343740
wst04-VHDL20_DWLI_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:43 343205
wst04-VHDL20_DWLI_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 387933
wst04-VHDL20_DWLI_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 331972
wst04-VHDL20_DWMO_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:19 461464
wst04-VHDL20_DWMO_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:13 461701
wst04-VHDL20_DWMO_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:24 461439
wst04-VHDL20_DWMO_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 363945
wst04-VHDL20_DWMO_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:19 470546
wst04-VHDL20_DWMO_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 470225
wst04-VHDL20_DWMO_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 471216
wst04-VHDL20_DWMO_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 351005
wst04-VHDL20_DWMP_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:19 580635
wst04-VHDL20_DWMP_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:19 580845
wst04-VHDL20_DWMP_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:24 470296
wst04-VHDL20_DWMP_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 479901
wst04-VHDL20_DWMP_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:19 586000
wst04-VHDL20_DWMP_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:19 585293
wst04-VHDL20_DWMP_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 477807
wst04-VHDL20_DWMP_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:33 472503
wst04-VHDL20_DWPG_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:41 242659
wst04-VHDL20_DWPG_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:33 349629
wst04-VHDL20_DWPG_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:48 394290
wst04-VHDL20_DWPG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:29 345868
wst04-VHDL20_DWPG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 243175
wst04-VHDL20_DWPG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:33 345675
wst04-VHDL20_DWPG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 390367
wst04-VHDL20_DWPG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 334278
wst04-VHDL20_DWPH_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:41 247859
wst04-VHDL20_DWPH_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:33 247648
wst04-VHDL20_DWPH_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:48 247703
wst04-VHDL20_DWPH_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:31:24 242742
wst04-VHDL20_DWPH_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:31 243027
wst04-VHDL20_DWPH_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:33 242533
wst04-VHDL20_DWPH_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:59 242624
wst04-VHDL20_DWPH_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:31:30 242965
wst04-VHDL20_DWSG_130200-2609130200-omedes--0.pdf 13-Sep-2026 02:30:17 356303
wst04-VHDL20_DWSG_130400-2609130400-omedes--0.pdf 13-Sep-2026 05:00:13 356128
wst04-VHDL20_DWSG_130800-2609130800-omedes--0.pdf 13-Sep-2026 08:30:24 357311
wst04-VHDL20_DWSG_131800-2609131800-omedes--0.pdf 13-Sep-2026 18:30:25 356387
wst04-VHDL20_DWSG_140200-2609140200-omedes--0.pdf 14-Sep-2026 02:30:13 355425
wst04-VHDL20_DWSG_140400-2609140400-omedes--0.pdf 14-Sep-2026 05:00:13 355742
wst04-VHDL20_DWSG_140800-2609140800-omedes--0.pdf 14-Sep-2026 08:30:27 358310
wst04-VHDL20_DWSG_141800-2609141800-omedes--0.pdf 14-Sep-2026 18:30:23 343185