Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_220600                                 22-Jul-2026 11:41:43                4057
FPDL13_DWMZ_230600                                 23-Jul-2026 12:52:15                5827
SXDL31_DWAV_220800                                 22-Jul-2026 07:28:34               12549
SXDL31_DWAV_221800                                 22-Jul-2026 16:12:15                5855
SXDL31_DWAV_230800                                 23-Jul-2026 07:49:10               11206
SXDL31_DWAV_231800                                 23-Jul-2026 16:50:04                6255
SXDL31_DWAV_LATEST                                 23-Jul-2026 16:50:04                6255
SXDL33_DWAV_220000                                 22-Jul-2026 10:51:43               12094
SXDL33_DWAV_230000                                 23-Jul-2026 10:41:39                5974
SXDL33_DWAV_LATEST                                 23-Jul-2026 10:41:39                5974
ber01-FWDL39_DWMS_221200-2607221200-dsw--0-ia5     22-Jul-2026 10:41:27                1202
ber01-FWDL39_DWMS_231200-2607231200-dsw--0-ia5     23-Jul-2026 11:09:12                2007
ber01-VHDL13_DWEG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:28:16                2450
ber01-VHDL13_DWEG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:28:12                2526
ber01-VHDL13_DWEG_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03                2359
ber01-VHDL13_DWEH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:28:22                2730
ber01-VHDL13_DWEH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:28:16                2716
ber01-VHDL13_DWEH_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03                2514
ber01-VHDL13_DWEI_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:28:10                2301
ber01-VHDL13_DWEI_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:28:16                2342
ber01-VHDL13_DWEI_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:43:03                2258
ber01-VHDL13_DWHG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                3878
ber01-VHDL13_DWHG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:14                3055
ber01-VHDL13_DWHH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                4026
ber01-VHDL13_DWHH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:14                2870
ber01-VHDL13_DWLG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2899
ber01-VHDL13_DWLG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2800
ber01-VHDL13_DWLH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2708
ber01-VHDL13_DWLH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2545
ber01-VHDL13_DWLI_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2358
ber01-VHDL13_DWLI_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2407
ber01-VHDL13_DWMO_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2543
ber01-VHDL13_DWMO_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2309
ber01-VHDL13_DWMP_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2508
ber01-VHDL13_DWMP_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2940
ber01-VHDL13_DWMP_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 08:49:08                2948
ber01-VHDL13_DWOG_220300-2607220300-dsw--0-ia5     22-Jul-2026 03:00:14                5090
ber01-VHDL13_DWOG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                4611
ber01-VHDL13_DWOG_221700-2607221700-dsw--0-ia5     22-Jul-2026 18:00:03                3753
ber01-VHDL13_DWOG_230300-2607230300-dsw--0-ia5     23-Jul-2026 03:00:03                3714
ber01-VHDL13_DWOG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                3169
ber01-VHDL13_DWOG_231700-2607231700-dsw--0-ia5     23-Jul-2026 18:00:03                2891
ber01-VHDL13_DWON_220207-2607220207-dsw--0-ia5     22-Jul-2026 02:07:52                5048
ber01-VHDL13_DWON_220508-2607220508-dsw--0-ia5     22-Jul-2026 05:08:36                4386
ber01-VHDL13_DWON_220558-2607220558-dsw--0-ia5     22-Jul-2026 05:58:21                4386
ber01-VHDL13_DWON_221102-2607221102-dsw--0-ia5     22-Jul-2026 11:02:52                4386
ber01-VHDL13_DWON_221218-2607221218-dsw--0-ia5     22-Jul-2026 12:18:17                4199
ber01-VHDL13_DWON_221313-2607221313-dsw--0-ia5     22-Jul-2026 13:13:35                3640
ber01-VHDL13_DWON_221431-2607221431-dsw--0-ia5     22-Jul-2026 14:31:20                3640
ber01-VHDL13_DWON_221654-2607221654-dsw--0-ia5     22-Jul-2026 16:54:10                3643
ber01-VHDL13_DWON_222019-2607222019-dsw--0-ia5     22-Jul-2026 20:19:36                3643
ber01-VHDL13_DWON_230011-2607230011-dsw--0-ia5     23-Jul-2026 00:11:41                3815
ber01-VHDL13_DWON_230330-2607230330-dsw--0-ia5     23-Jul-2026 03:30:38                3815
ber01-VHDL13_DWON_230356-2607230356-dsw--0-ia5     23-Jul-2026 03:56:56                3815
ber01-VHDL13_DWON_230522-2607230522-dsw--0-ia5     23-Jul-2026 05:22:17                3801
ber01-VHDL13_DWON_230618-2607230618-dsw--0-ia5     23-Jul-2026 06:18:11                3714
ber01-VHDL13_DWON_231427-2607231427-dsw--0-ia5     23-Jul-2026 14:27:17                3363
ber01-VHDL13_DWON_231728-2607231728-dsw--0-ia5     23-Jul-2026 17:28:06                3022
ber01-VHDL13_DWPG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2591
ber01-VHDL13_DWPG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2945
ber01-VHDL13_DWPH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                3485
ber01-VHDL13_DWPH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2969
ber01-VHDL13_DWSG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                2430
ber01-VHDL13_DWSG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                2651
ber01-VHDL17_DWOG_221200-2607221200-dsw--0-ia5     22-Jul-2026 12:02:57                2851
ber01-VHDL17_DWOG_231200-2607231200-dsw--0-ia5     23-Jul-2026 11:45:36                3539
swis2-VHDL20_DWEG_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:11                 870
swis2-VHDL20_DWEG_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:01:27                 748
swis2-VHDL20_DWEG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                 862
swis2-VHDL20_DWEG_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:02                1005
swis2-VHDL20_DWEG_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:08                 799
swis2-VHDL20_DWEG_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:01:26                 795
swis2-VHDL20_DWEG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                 979
swis2-VHDL20_DWEG_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57                1116
swis2-VHDL20_DWEG_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1132
swis2-VHDL20_DWEH_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:11                 903
swis2-VHDL20_DWEH_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:01:27                 747
swis2-VHDL20_DWEH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                 988
swis2-VHDL20_DWEH_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:02                1074
swis2-VHDL20_DWEH_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:08                 817
swis2-VHDL20_DWEH_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:01:26                 819
swis2-VHDL20_DWEH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                1028
swis2-VHDL20_DWEH_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57                1045
swis2-VHDL20_DWEH_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1079
swis2-VHDL20_DWEI_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:11                 893
swis2-VHDL20_DWEI_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:01:27                 770
swis2-VHDL20_DWEI_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                 884
swis2-VHDL20_DWEI_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:02                1027
swis2-VHDL20_DWEI_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:08                 821
swis2-VHDL20_DWEI_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:01:26                 817
swis2-VHDL20_DWEI_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                 997
swis2-VHDL20_DWEI_230800_COR-2607230800-dsw--0-ia5 23-Jul-2026 16:42:57                1068
swis2-VHDL20_DWEI_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1084
swis2-VHDL20_DWHG_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:45:15                1507
swis2-VHDL20_DWHG_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:16                1507
swis2-VHDL20_DWHG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:45:17                1718
swis2-VHDL20_DWHG_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:45:07                1470
swis2-VHDL20_DWHG_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:45:32                1258
swis2-VHDL20_DWHG_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:16                1080
swis2-VHDL20_DWHG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:45:07                1130
swis2-VHDL20_DWHG_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:45:04                1118
swis2-VHDL20_DWHH_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:45:15                1877
swis2-VHDL20_DWHH_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:16                1880
swis2-VHDL20_DWHH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:45:17                2001
swis2-VHDL20_DWHH_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:45:07                1785
swis2-VHDL20_DWHH_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:45:32                1551
swis2-VHDL20_DWHH_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:16                1214
swis2-VHDL20_DWHH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:45:07                1159
swis2-VHDL20_DWHH_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:45:04                1126
swis2-VHDL20_DWLG_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:26                 941
swis2-VHDL20_DWLG_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:12                1042
swis2-VHDL20_DWLG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:25                1322
swis2-VHDL20_DWLG_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:31:03                1216
swis2-VHDL20_DWLG_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:28                1048
swis2-VHDL20_DWLG_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:12                1197
swis2-VHDL20_DWLG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:23                1504
swis2-VHDL20_DWLG_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:31:05                 915
swis2-VHDL20_DWLH_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:26                1077
swis2-VHDL20_DWLH_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:12                1052
swis2-VHDL20_DWLH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:25                1159
swis2-VHDL20_DWLH_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:31:03                1163
swis2-VHDL20_DWLH_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:28                 842
swis2-VHDL20_DWLH_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:12                1016
swis2-VHDL20_DWLH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:23                1143
swis2-VHDL20_DWLH_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:31:05                 997
swis2-VHDL20_DWLI_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:26                 874
swis2-VHDL20_DWLI_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:12                 869
swis2-VHDL20_DWLI_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:25                 985
swis2-VHDL20_DWLI_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:31:03                 957
swis2-VHDL20_DWLI_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:28                 837
swis2-VHDL20_DWLI_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:12                1036
swis2-VHDL20_DWLI_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:23                1163
swis2-VHDL20_DWLI_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:31:05                1017
swis2-VHDL20_DWMO_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:00                 924
swis2-VHDL20_DWMO_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:01                 869
swis2-VHDL20_DWMO_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                 942
swis2-VHDL20_DWMO_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:08                 862
swis2-VHDL20_DWMO_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:05                 922
swis2-VHDL20_DWMO_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:02                 923
swis2-VHDL20_DWMO_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                1059
swis2-VHDL20_DWMO_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1285
swis2-VHDL20_DWMP_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:00                 933
swis2-VHDL20_DWMP_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:01                 868
swis2-VHDL20_DWMP_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                1058
swis2-VHDL20_DWMP_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:08                 976
swis2-VHDL20_DWMP_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:05                 919
swis2-VHDL20_DWMP_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:02                 915
swis2-VHDL20_DWMP_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                1422
swis2-VHDL20_DWMP_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1541
swis2-VHDL20_DWPG_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:26                 949
swis2-VHDL20_DWPG_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:12                1062
swis2-VHDL20_DWPG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:25                1235
swis2-VHDL20_DWPG_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:31:03                1186
swis2-VHDL20_DWPG_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:28                1053
swis2-VHDL20_DWPG_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:12                1250
swis2-VHDL20_DWPG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:23                1508
swis2-VHDL20_DWPG_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:31:05                 934
swis2-VHDL20_DWPH_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:26                1605
swis2-VHDL20_DWPH_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:12                1754
swis2-VHDL20_DWPH_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:25                1871
swis2-VHDL20_DWPH_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:31:03                1203
swis2-VHDL20_DWPH_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:28                 955
swis2-VHDL20_DWPH_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:12                1063
swis2-VHDL20_DWPH_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:23                1334
swis2-VHDL20_DWPH_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:31:05                1018
swis2-VHDL20_DWSG_220200-2607220200-dsw--0-ia5     22-Jul-2026 02:30:11                 791
swis2-VHDL20_DWSG_220400-2607220400-dsw--0-ia5     22-Jul-2026 05:00:22                 772
swis2-VHDL20_DWSG_220800-2607220800-dsw--0-ia5     22-Jul-2026 08:30:07                 904
swis2-VHDL20_DWSG_221800-2607221800-dsw--0-ia5     22-Jul-2026 18:30:08                 877
swis2-VHDL20_DWSG_230200-2607230200-dsw--0-ia5     23-Jul-2026 02:30:05                 879
swis2-VHDL20_DWSG_230400-2607230400-dsw--0-ia5     23-Jul-2026 05:00:16                 876
swis2-VHDL20_DWSG_230800-2607230800-dsw--0-ia5     23-Jul-2026 08:30:06                 993
swis2-VHDL20_DWSG_231800-2607231800-dsw--0-ia5     23-Jul-2026 18:30:11                1676
wst04-VHDL20_DWEG_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:11              237625
wst04-VHDL20_DWEG_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:12              237317
wst04-VHDL20_DWEG_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:17              238022
wst04-VHDL20_DWEG_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              239007
wst04-VHDL20_DWEG_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:10              238328
wst04-VHDL20_DWEG_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:12              237386
wst04-VHDL20_DWEG_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:14              238576
wst04-VHDL20_DWEG_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06              238644
wst04-VHDL20_DWEG_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:11              238890
wst04-VHDL20_DWEH_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:11              231247
wst04-VHDL20_DWEH_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:12              231239
wst04-VHDL20_DWEH_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:17              232329
wst04-VHDL20_DWEH_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              234945
wst04-VHDL20_DWEH_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:10              235110
wst04-VHDL20_DWEH_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:12              234146
wst04-VHDL20_DWEH_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:14              235414
wst04-VHDL20_DWEH_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06              235919
wst04-VHDL20_DWEH_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:11              235570
wst04-VHDL20_DWEI_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:11              340339
wst04-VHDL20_DWEI_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:12              339929
wst04-VHDL20_DWEI_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:17              340140
wst04-VHDL20_DWEI_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              337917
wst04-VHDL20_DWEI_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:10              337802
wst04-VHDL20_DWEI_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:12              336813
wst04-VHDL20_DWEI_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:23              337503
wst04-VHDL20_DWEI_230800_COR-2607230800-omedes-..> 23-Jul-2026 16:43:06              342105
wst04-VHDL20_DWEI_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:17              342308
wst04-VHDL20_DWHG_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:45:15              343921
wst04-VHDL20_DWHG_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:16              343739
wst04-VHDL20_DWHG_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:45:17              344753
wst04-VHDL20_DWHG_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:45:17              343180
wst04-VHDL20_DWHG_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:45:32              341583
wst04-VHDL20_DWHG_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:16              340464
wst04-VHDL20_DWHG_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:45:17              341585
wst04-VHDL20_DWHG_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:45:13              338674
wst04-VHDL20_DWHH_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:45:15              339808
wst04-VHDL20_DWHH_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:16              235924
wst04-VHDL20_DWHH_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:45:17              340726
wst04-VHDL20_DWHH_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:45:17              336937
wst04-VHDL20_DWHH_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:45:32              334872
wst04-VHDL20_DWHH_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:16              232892
wst04-VHDL20_DWHH_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:45:17              333389
wst04-VHDL20_DWHH_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:45:13              329396
wst04-VHDL20_DWLG_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              340119
wst04-VHDL20_DWLG_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:42              340261
wst04-VHDL20_DWLG_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:42              340660
wst04-VHDL20_DWLG_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:31:26              337663
wst04-VHDL20_DWLG_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:22              337325
wst04-VHDL20_DWLG_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:42              337037
wst04-VHDL20_DWLG_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:41              338096
wst04-VHDL20_DWLG_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:31:23              335339
wst04-VHDL20_DWLH_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              337044
wst04-VHDL20_DWLH_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:42              337153
wst04-VHDL20_DWLH_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:42              337403
wst04-VHDL20_DWLH_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:31:26              330568
wst04-VHDL20_DWLH_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:22              329651
wst04-VHDL20_DWLH_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:42              329384
wst04-VHDL20_DWLH_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:41              329582
wst04-VHDL20_DWLH_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:31:23              334888
wst04-VHDL20_DWLI_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              331591
wst04-VHDL20_DWLI_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:42              331672
wst04-VHDL20_DWLI_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:42              376436
wst04-VHDL20_DWLI_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:31:26              332236
wst04-VHDL20_DWLI_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:28              331973
wst04-VHDL20_DWLI_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:42              331721
wst04-VHDL20_DWLI_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:41              376534
wst04-VHDL20_DWLI_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:31:29              332612
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wst04-VHDL20_DWMO_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:16              445232
wst04-VHDL20_DWMO_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:17              445379
wst04-VHDL20_DWMO_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              337137
wst04-VHDL20_DWMO_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:20              439501
wst04-VHDL20_DWMO_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:16              439739
wst04-VHDL20_DWMO_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:23              439686
wst04-VHDL20_DWMO_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:17              342326
wst04-VHDL20_DWMP_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              567264
wst04-VHDL20_DWMP_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:16              566784
wst04-VHDL20_DWMP_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:25              462153
wst04-VHDL20_DWMP_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              464817
wst04-VHDL20_DWMP_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:20              570775
wst04-VHDL20_DWMP_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:16              570870
wst04-VHDL20_DWMP_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:23              465999
wst04-VHDL20_DWMP_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:17              462596
wst04-VHDL20_DWPG_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              243000
wst04-VHDL20_DWPG_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:32              347126
wst04-VHDL20_DWPG_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:49              391904
wst04-VHDL20_DWPG_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:31:26              344587
wst04-VHDL20_DWPG_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:22              241246
wst04-VHDL20_DWPG_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:32              344052
wst04-VHDL20_DWPG_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:54              389610
wst04-VHDL20_DWPG_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:31:23              339747
wst04-VHDL20_DWPH_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:26              246762
wst04-VHDL20_DWPH_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:32              246602
wst04-VHDL20_DWPH_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:42              246723
wst04-VHDL20_DWPH_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:31:26              243041
wst04-VHDL20_DWPH_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:22              243079
wst04-VHDL20_DWPH_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:32              242260
wst04-VHDL20_DWPH_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:41              243274
wst04-VHDL20_DWPH_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:31:23              238093
wst04-VHDL20_DWSG_220200-2607220200-omedes--0.pdf  22-Jul-2026 02:30:13              339280
wst04-VHDL20_DWSG_220400-2607220400-omedes--0.pdf  22-Jul-2026 05:00:12              339024
wst04-VHDL20_DWSG_220800-2607220800-omedes--0.pdf  22-Jul-2026 08:30:17              339336
wst04-VHDL20_DWSG_221800-2607221800-omedes--0.pdf  22-Jul-2026 18:30:16              341569
wst04-VHDL20_DWSG_230200-2607230200-omedes--0.pdf  23-Jul-2026 02:30:12              341281
wst04-VHDL20_DWSG_230400-2607230400-omedes--0.pdf  23-Jul-2026 05:00:12              340706
wst04-VHDL20_DWSG_230800-2607230800-omedes--0.pdf  23-Jul-2026 08:30:14              341262
wst04-VHDL20_DWSG_231800-2607231800-omedes--0.pdf  23-Jul-2026 18:30:17              342387