Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-Aug-2026 07:29:13 2667
FPDL13_DWMZ_030600 03-Aug-2026 13:59:58 4236
SXDL31_DWAV_011800 01-Aug-2026 16:40:17 7736
SXDL31_DWAV_020800 02-Aug-2026 09:09:09 12475
SXDL31_DWAV_021800 02-Aug-2026 16:37:15 9312
SXDL31_DWAV_030800 03-Aug-2026 07:43:48 15668
SXDL31_DWAV_LATEST 03-Aug-2026 07:43:48 15668
SXDL33_DWAV_020000 02-Aug-2026 09:46:18 6735
SXDL33_DWAV_030000 03-Aug-2026 10:38:20 9514
SXDL33_DWAV_LATEST 03-Aug-2026 10:38:20 9514
ber01-FWDL39_DWMS_021200-2608021200-dsw--0-ia5 02-Aug-2026 11:55:26 1946
ber01-FWDL39_DWMS_031200-2608031200-dsw--0-ia5 03-Aug-2026 12:07:17 1947
ber01-VHDL13_DWEG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:28:22 3039
ber01-VHDL13_DWEG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:23 3553
ber01-VHDL13_DWEH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:28:26 3046
ber01-VHDL13_DWEH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:23 3568
ber01-VHDL13_DWEI_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:28:26 2989
ber01-VHDL13_DWEI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:27 3649
ber01-VHDL13_DWHG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 3142
ber01-VHDL13_DWHG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3996
ber01-VHDL13_DWHH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 2907
ber01-VHDL13_DWHH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3669
ber01-VHDL13_DWLG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 3397
ber01-VHDL13_DWLG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3096
ber01-VHDL13_DWLH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 3354
ber01-VHDL13_DWLH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3330
ber01-VHDL13_DWLI_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 3244
ber01-VHDL13_DWLI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3389
ber01-VHDL13_DWMO_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 3153
ber01-VHDL13_DWMO_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3758
ber01-VHDL13_DWMP_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 3421
ber01-VHDL13_DWMP_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3837
ber01-VHDL13_DWOG_011700-2608011700-dsw--0-ia5 01-Aug-2026 18:00:07 3243
ber01-VHDL13_DWOG_020300-2608020300-dsw--0-ia5 02-Aug-2026 03:00:19 3107
ber01-VHDL13_DWOG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:02 3254
ber01-VHDL13_DWOG_021700-2608021700-dsw--0-ia5 02-Aug-2026 18:00:01 3589
ber01-VHDL13_DWOG_030300-2608030300-dsw--0-ia5 03-Aug-2026 03:00:21 3796
ber01-VHDL13_DWOG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3963
ber01-VHDL13_DWON_011458-2608011458-dsw--0-ia5 01-Aug-2026 14:59:30 2817
ber01-VHDL13_DWON_011726-2608011726-dsw--0-ia5 01-Aug-2026 17:26:57 2817
ber01-VHDL13_DWON_020141-2608020141-dsw--0-ia5 02-Aug-2026 01:43:01 2689
ber01-VHDL13_DWON_020521-2608020521-dsw--0-ia5 02-Aug-2026 05:21:21 2762
ber01-VHDL13_DWON_021001-2608021001-dsw--0-ia5 02-Aug-2026 10:02:01 2762
ber01-VHDL13_DWON_021221-2608021221-dsw--0-ia5 02-Aug-2026 12:21:42 2656
ber01-VHDL13_DWON_021411-2608021411-dsw--0-ia5 02-Aug-2026 14:11:12 2650
ber01-VHDL13_DWON_021729-2608021729-dsw--0-ia5 02-Aug-2026 17:29:21 2401
ber01-VHDL13_DWON_021859-2608021859-dsw--0-ia5 02-Aug-2026 18:59:47 2954
ber01-VHDL13_DWON_021927-2608021927-dsw--0-ia5 02-Aug-2026 19:27:25 3002
ber01-VHDL13_DWON_030115-2608030115-dsw--0-ia5 03-Aug-2026 01:15:42 3118
ber01-VHDL13_DWON_030247-2608030247-dsw--0-ia5 03-Aug-2026 02:48:35 3470
ber01-VHDL13_DWON_030524-2608030524-dsw--0-ia5 03-Aug-2026 05:24:42 3578
ber01-VHDL13_DWON_030553-2608030553-dsw--0-ia5 03-Aug-2026 05:53:51 3578
ber01-VHDL13_DWON_030824-2608030824-dsw--0-ia5 03-Aug-2026 08:24:37 3647
ber01-VHDL13_DWON_031019-2608031019-dsw--0-ia5 03-Aug-2026 10:19:27 3647
ber01-VHDL13_DWPG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 3021
ber01-VHDL13_DWPG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3346
ber01-VHDL13_DWPH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 3085
ber01-VHDL13_DWPH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3368
ber01-VHDL13_DWSG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:02 3276
ber01-VHDL13_DWSG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 4143
ber01-VHDL13_DWSG_030800_COR-2608030800-dsw--0-ia5 03-Aug-2026 12:19:32 4097
ber01-VHDL17_DWOG_021200-2608021200-dsw--0-ia5 02-Aug-2026 10:43:23 2045
ber01-VHDL17_DWOG_031200-2608031200-dsw--0-ia5 03-Aug-2026 12:00:01 2637
swis2-VHDL20_DWEG_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:10 1516
swis2-VHDL20_DWEG_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:11 1151
swis2-VHDL20_DWEG_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:02:16 1167
swis2-VHDL20_DWEG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 1548
swis2-VHDL20_DWEG_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 2288
swis2-VHDL20_DWEG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1638
swis2-VHDL20_DWEG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1788
swis2-VHDL20_DWEG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2064
swis2-VHDL20_DWEH_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:10 1633
swis2-VHDL20_DWEH_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:11 1191
swis2-VHDL20_DWEH_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:02:16 1210
swis2-VHDL20_DWEH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:14 1567
swis2-VHDL20_DWEH_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 2327
swis2-VHDL20_DWEH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1676
swis2-VHDL20_DWEH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1801
swis2-VHDL20_DWEH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2024
swis2-VHDL20_DWEI_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:10 1538
swis2-VHDL20_DWEI_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:11 1173
swis2-VHDL20_DWEI_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:02:16 1223
swis2-VHDL20_DWEI_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 1572
swis2-VHDL20_DWEI_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 2330
swis2-VHDL20_DWEI_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1801
swis2-VHDL20_DWEI_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1932
swis2-VHDL20_DWEI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2127
swis2-VHDL20_DWHG_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:45:07 1728
swis2-VHDL20_DWHG_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:46:48 1487
swis2-VHDL20_DWHG_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 1470
swis2-VHDL20_DWHG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:45:08 2112
swis2-VHDL20_DWHG_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:45:06 2576
swis2-VHDL20_DWHG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:45:31 2101
swis2-VHDL20_DWHG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 2098
swis2-VHDL20_DWHG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:45:27 2575
swis2-VHDL20_DWHH_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:45:07 1521
swis2-VHDL20_DWHH_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:46:48 1205
swis2-VHDL20_DWHH_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 1192
swis2-VHDL20_DWHH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:45:08 1699
swis2-VHDL20_DWHH_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:45:06 2116
swis2-VHDL20_DWHH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:45:31 1608
swis2-VHDL20_DWHH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 1608
swis2-VHDL20_DWHH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:45:27 2234
swis2-VHDL20_DWLG_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:31:06 1072
swis2-VHDL20_DWLG_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:23 1067
swis2-VHDL20_DWLG_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 1222
swis2-VHDL20_DWLG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:23 1607
swis2-VHDL20_DWLG_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:31:08 1599
swis2-VHDL20_DWLG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1344
swis2-VHDL20_DWLG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1203
swis2-VHDL20_DWLG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1423
swis2-VHDL20_DWLH_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:31:06 1084
swis2-VHDL20_DWLH_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:23 1126
swis2-VHDL20_DWLH_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 1235
swis2-VHDL20_DWLH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:23 1624
swis2-VHDL20_DWLH_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:31:08 1608
swis2-VHDL20_DWLH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1321
swis2-VHDL20_DWLH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1423
swis2-VHDL20_DWLH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1645
swis2-VHDL20_DWLI_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:31:06 1063
swis2-VHDL20_DWLI_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:23 1085
swis2-VHDL20_DWLI_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 1282
swis2-VHDL20_DWLI_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:23 1608
swis2-VHDL20_DWLI_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:31:08 1600
swis2-VHDL20_DWLI_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1334
swis2-VHDL20_DWLI_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1448
swis2-VHDL20_DWLI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1668
swis2-VHDL20_DWMO_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:03 1813
swis2-VHDL20_DWMO_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:01 1597
swis2-VHDL20_DWMO_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:01 1617
swis2-VHDL20_DWMO_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 1581
swis2-VHDL20_DWMO_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 1557
swis2-VHDL20_DWMO_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1416
swis2-VHDL20_DWMO_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:06 1752
swis2-VHDL20_DWMO_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2062
swis2-VHDL20_DWMP_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:03 2090
swis2-VHDL20_DWMP_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:01 1810
swis2-VHDL20_DWMP_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:01 1801
swis2-VHDL20_DWMP_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:15 1881
swis2-VHDL20_DWMP_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 1491
swis2-VHDL20_DWMP_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1464
swis2-VHDL20_DWMP_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:06 1726
swis2-VHDL20_DWMP_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2138
swis2-VHDL20_DWPG_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:31:06 1083
swis2-VHDL20_DWPG_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:23 957
swis2-VHDL20_DWPG_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 879
swis2-VHDL20_DWPG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:23 1469
swis2-VHDL20_DWPG_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:31:08 1464
swis2-VHDL20_DWPG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1126
swis2-VHDL20_DWPG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1355
swis2-VHDL20_DWPG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1588
swis2-VHDL20_DWPH_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:31:06 1015
swis2-VHDL20_DWPH_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:23 870
swis2-VHDL20_DWPH_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:16 909
swis2-VHDL20_DWPH_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:23 1447
swis2-VHDL20_DWPH_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:31:08 1437
swis2-VHDL20_DWPH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1108
swis2-VHDL20_DWPH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1313
swis2-VHDL20_DWPH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1570
swis2-VHDL20_DWSG_011800-2608011800-dsw--0-ia5 01-Aug-2026 18:30:03 2018
swis2-VHDL20_DWSG_020200-2608020200-dsw--0-ia5 02-Aug-2026 02:30:01 1602
swis2-VHDL20_DWSG_020400-2608020400-dsw--0-ia5 02-Aug-2026 05:00:22 1328
swis2-VHDL20_DWSG_020800-2608020800-dsw--0-ia5 02-Aug-2026 08:30:02 1678
swis2-VHDL20_DWSG_021800-2608021800-dsw--0-ia5 02-Aug-2026 18:30:07 1789
swis2-VHDL20_DWSG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1450
swis2-VHDL20_DWSG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 1398
swis2-VHDL20_DWSG_030400_COR-2608030400-dsw--0-ia5 03-Aug-2026 05:13:41 1767
swis2-VHDL20_DWSG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 1955
swis2-VHDL20_DWSG_030800_COR-2608030800-dsw--0-ia5 03-Aug-2026 12:19:32 1996
wst04-VHDL20_DWEG_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:17 247278
wst04-VHDL20_DWEG_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:19 247110
wst04-VHDL20_DWEG_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:22 247207
wst04-VHDL20_DWEG_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:23 247936
wst04-VHDL20_DWEG_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:30 241191
wst04-VHDL20_DWEG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:10 239999
wst04-VHDL20_DWEG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 240138
wst04-VHDL20_DWEG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:14 241527
wst04-VHDL20_DWEH_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:17 241199
wst04-VHDL20_DWEH_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:11 241333
wst04-VHDL20_DWEH_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:16 241631
wst04-VHDL20_DWEH_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:14 242391
wst04-VHDL20_DWEH_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:22 239329
wst04-VHDL20_DWEH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 238736
wst04-VHDL20_DWEH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 238792
wst04-VHDL20_DWEH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:14 240232
wst04-VHDL20_DWEI_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:24 356126
wst04-VHDL20_DWEI_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:23 355787
wst04-VHDL20_DWEI_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:22 355894
wst04-VHDL20_DWEI_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:23 356798
wst04-VHDL20_DWEI_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:22 347662
wst04-VHDL20_DWEI_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 346971
wst04-VHDL20_DWEI_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 347020
wst04-VHDL20_DWEI_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:16 347426
wst04-VHDL20_DWHG_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:45:14 341957
wst04-VHDL20_DWHG_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:46:48 340499
wst04-VHDL20_DWHG_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:16 340271
wst04-VHDL20_DWHG_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:45:13 342824
wst04-VHDL20_DWHG_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:45:16 340702
wst04-VHDL20_DWHG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:45:31 339047
wst04-VHDL20_DWHG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:12 338842
wst04-VHDL20_DWHG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:45:27 341093
wst04-VHDL20_DWHH_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:45:14 333504
wst04-VHDL20_DWHH_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:46:48 332751
wst04-VHDL20_DWHH_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:12 226755
wst04-VHDL20_DWHH_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:45:13 334247
wst04-VHDL20_DWHH_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:45:16 333851
wst04-VHDL20_DWHH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:45:31 331766
wst04-VHDL20_DWHH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:16 228783
wst04-VHDL20_DWHH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:45:27 334191
wst04-VHDL20_DWLG_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:31:22 346709
wst04-VHDL20_DWLG_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:29 346721
wst04-VHDL20_DWLG_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:42 347291
wst04-VHDL20_DWLG_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:47 347786
wst04-VHDL20_DWLG_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:31:22 342555
wst04-VHDL20_DWLG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 341232
wst04-VHDL20_DWLG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:42 341176
wst04-VHDL20_DWLG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:52 342203
wst04-VHDL20_DWLH_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:31:26 354965
wst04-VHDL20_DWLH_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:39 355044
wst04-VHDL20_DWLH_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:42 355194
wst04-VHDL20_DWLH_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:47 356002
wst04-VHDL20_DWLH_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:31:29 345044
wst04-VHDL20_DWLH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 343746
wst04-VHDL20_DWLH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:48 343835
wst04-VHDL20_DWLH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 344848
wst04-VHDL20_DWLI_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:31:26 345903
wst04-VHDL20_DWLI_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:23 346002
wst04-VHDL20_DWLI_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:46 346521
wst04-VHDL20_DWLI_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:41 391593
wst04-VHDL20_DWLI_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:31:31 339116
wst04-VHDL20_DWLI_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:37 337809
wst04-VHDL20_DWLI_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:42 337918
wst04-VHDL20_DWLI_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 383476
wst04-VHDL20_DWMO_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:24 354020
wst04-VHDL20_DWMO_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:19 466085
wst04-VHDL20_DWMO_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:16 466187
wst04-VHDL20_DWMO_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:29 466004
wst04-VHDL20_DWMO_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:19 352530
wst04-VHDL20_DWMO_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:10 460536
wst04-VHDL20_DWMO_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:12 459734
wst04-VHDL20_DWMO_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:31 460002
wst04-VHDL20_DWMP_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:24 489529
wst04-VHDL20_DWMP_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:23 599656
wst04-VHDL20_DWMP_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:26 599774
wst04-VHDL20_DWMP_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:29 488206
wst04-VHDL20_DWMP_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:22 479720
wst04-VHDL20_DWMP_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 588703
wst04-VHDL20_DWMP_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:16 588675
wst04-VHDL20_DWMP_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:31 480505
wst04-VHDL20_DWPG_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:31:26 355789
wst04-VHDL20_DWPG_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:39 245532
wst04-VHDL20_DWPG_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:32 354364
wst04-VHDL20_DWPG_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:31:04 401365
wst04-VHDL20_DWPG_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:31:29 348328
wst04-VHDL20_DWPG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 243397
wst04-VHDL20_DWPG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:32 347198
wst04-VHDL20_DWPG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 392953
wst04-VHDL20_DWPH_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:31:22 244586
wst04-VHDL20_DWPH_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:29 243715
wst04-VHDL20_DWPH_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:32 243199
wst04-VHDL20_DWPH_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:43 244849
wst04-VHDL20_DWPH_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:31:22 244487
wst04-VHDL20_DWPH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 244406
wst04-VHDL20_DWPH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:32 244596
wst04-VHDL20_DWPH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 244949
wst04-VHDL20_DWSG_011800-2608011800-omedes--0.pdf 01-Aug-2026 18:30:17 360831
wst04-VHDL20_DWSG_020200-2608020200-omedes--0.pdf 02-Aug-2026 02:30:11 357935
wst04-VHDL20_DWSG_020400-2608020400-omedes--0.pdf 02-Aug-2026 05:00:12 357523
wst04-VHDL20_DWSG_020800-2608020800-omedes--0.pdf 02-Aug-2026 08:30:29 359796
wst04-VHDL20_DWSG_021800-2608021800-omedes--0.pdf 02-Aug-2026 18:30:19 360181
wst04-VHDL20_DWSG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 358622
wst04-VHDL20_DWSG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:13:47 358454
wst04-VHDL20_DWSG_030800-2608030800-omedes--0.pdf 03-Aug-2026 12:19:40 367518