Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Oct-2026 11:16:40 21554
FPDL13_DWMZ_120600 12-Oct-2026 13:38:13 3789
SXDL31_DWAV_110800 11-Oct-2026 07:18:21 7387
SXDL31_DWAV_111800 11-Oct-2026 16:18:45 5288
SXDL31_DWAV_120800 12-Oct-2026 07:44:35 9252
SXDL31_DWAV_121800 12-Oct-2026 16:47:52 5801
SXDL31_DWAV_LATEST 12-Oct-2026 16:47:52 5801
SXDL33_DWAV_110000 11-Oct-2026 09:07:30 7350
SXDL33_DWAV_120000 12-Oct-2026 09:45:06 13816
SXDL33_DWAV_LATEST 12-Oct-2026 09:45:06 13816
ber01-FWDL39_DWMS_111200-2610111200-dsw--0-ia5 11-Oct-2026 11:20:09 1472
ber01-FWDL39_DWMS_121200-2610121200-dsw--0-ia5 12-Oct-2026 10:33:46 1169
ber01-VHDL13_DWEG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:28:19 3266
ber01-VHDL13_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:24 2613
ber01-VHDL13_DWEH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:28:19 3217
ber01-VHDL13_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2639
ber01-VHDL13_DWEI_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:28:25 2983
ber01-VHDL13_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2545
ber01-VHDL13_DWHG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 4002
ber01-VHDL13_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3666
ber01-VHDL13_DWHH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 4179
ber01-VHDL13_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3539
ber01-VHDL13_DWLG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3137
ber01-VHDL13_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2906
ber01-VHDL13_DWLH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3186
ber01-VHDL13_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2996
ber01-VHDL13_DWLI_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 2865
ber01-VHDL13_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2696
ber01-VHDL13_DWMO_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3458
ber01-VHDL13_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 2807
ber01-VHDL13_DWMP_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3553
ber01-VHDL13_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2726
ber01-VHDL13_DWOG_110300-2610110300-dsw--0-ia5 11-Oct-2026 03:02:08 4590
ber01-VHDL13_DWOG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:13 4586
ber01-VHDL13_DWOG_111700-2610111700-dsw--0-ia5 11-Oct-2026 18:00:04 3151
ber01-VHDL13_DWOG_120300-2610120300-dsw--0-ia5 12-Oct-2026 03:01:56 3574
ber01-VHDL13_DWOG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 3714
ber01-VHDL13_DWOG_121700-2610121700-dsw--0-ia5 12-Oct-2026 18:00:12 3536
ber01-VHDL13_DWON_110124-2610110124-dsw--0-ia5 11-Oct-2026 01:24:08 3592
ber01-VHDL13_DWON_110252-2610110252-dsw--0-ia5 11-Oct-2026 02:52:11 3586
ber01-VHDL13_DWON_110521-2610110521-dsw--0-ia5 11-Oct-2026 05:21:14 4057
ber01-VHDL13_DWON_110622-2610110622-dsw--0-ia5 11-Oct-2026 06:22:09 4062
ber01-VHDL13_DWON_110816-2610110816-dsw--0-ia5 11-Oct-2026 08:16:38 4062
ber01-VHDL13_DWON_111151-2610111151-dsw--0-ia5 11-Oct-2026 11:52:01 4062
ber01-VHDL13_DWON_111451-2610111451-dsw--0-ia5 11-Oct-2026 14:52:34 3288
ber01-VHDL13_DWON_111714-2610111714-dsw--0-ia5 11-Oct-2026 17:14:14 3240
ber01-VHDL13_DWON_120115-2610120115-dsw--0-ia5 12-Oct-2026 01:15:08 3487
ber01-VHDL13_DWON_120245-2610120245-dsw--0-ia5 12-Oct-2026 02:46:26 3610
ber01-VHDL13_DWON_120529-2610120529-dsw--0-ia5 12-Oct-2026 05:29:45 3610
ber01-VHDL13_DWON_120556-2610120556-dsw--0-ia5 12-Oct-2026 05:56:09 3749
ber01-VHDL13_DWON_121232-2610121232-dsw--0-ia5 12-Oct-2026 12:32:28 3602
ber01-VHDL13_DWON_121428-2610121428-dsw--0-ia5 12-Oct-2026 14:28:19 3744
ber01-VHDL13_DWON_121709-2610121709-dsw--0-ia5 12-Oct-2026 17:09:24 3313
ber01-VHDL13_DWON_121829-2610121829-dsw--0-ia5 12-Oct-2026 18:29:19 3296
ber01-VHDL13_DWPG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3180
ber01-VHDL13_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2624
ber01-VHDL13_DWPH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 3688
ber01-VHDL13_DWPH_110800_COR-2610110800-dsw--0-ia5 11-Oct-2026 11:37:31 3922
ber01-VHDL13_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3127
ber01-VHDL13_DWSG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:13 2659
ber01-VHDL13_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3007
ber01-VHDL17_DWOG_111200-2610111200-dsw--0-ia5 11-Oct-2026 11:42:14 2942
ber01-VHDL17_DWOG_121200-2610121200-dsw--0-ia5 12-Oct-2026 11:20:28 3235
swis2-VHDL20_DWEG_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:07 1479
swis2-VHDL20_DWEG_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:01:18 1303
swis2-VHDL20_DWEG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 1414
swis2-VHDL20_DWEG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 943
swis2-VHDL20_DWEG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 993
swis2-VHDL20_DWEG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 994
swis2-VHDL20_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 1114
swis2-VHDL20_DWEG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1160
swis2-VHDL20_DWEH_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:07 1537
swis2-VHDL20_DWEH_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:01:18 1332
swis2-VHDL20_DWEH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 1454
swis2-VHDL20_DWEH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 1050
swis2-VHDL20_DWEH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 870
swis2-VHDL20_DWEH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 871
swis2-VHDL20_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 954
swis2-VHDL20_DWEH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1095
swis2-VHDL20_DWEI_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:07 1242
swis2-VHDL20_DWEI_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:01:18 1188
swis2-VHDL20_DWEI_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 1316
swis2-VHDL20_DWEI_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 962
swis2-VHDL20_DWEI_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 875
swis2-VHDL20_DWEI_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 875
swis2-VHDL20_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 995
swis2-VHDL20_DWEI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1024
swis2-VHDL20_DWHG_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:45:16 2000
swis2-VHDL20_DWHG_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:12 2005
swis2-VHDL20_DWHG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:46:21 2298
swis2-VHDL20_DWHG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:45:25 1559
swis2-VHDL20_DWHG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:46:34 1512
swis2-VHDL20_DWHG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1561
swis2-VHDL20_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1534
swis2-VHDL20_DWHG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1847
swis2-VHDL20_DWHH_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:45:16 1967
swis2-VHDL20_DWHH_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:18 1975
swis2-VHDL20_DWHH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:46:22 2323
swis2-VHDL20_DWHH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:45:25 1598
swis2-VHDL20_DWHH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:46:34 1557
swis2-VHDL20_DWHH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1595
swis2-VHDL20_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1626
swis2-VHDL20_DWHH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1796
swis2-VHDL20_DWLG_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:43 1224
swis2-VHDL20_DWLG_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:14 1186
swis2-VHDL20_DWLG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:28 1560
swis2-VHDL20_DWLG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1098
swis2-VHDL20_DWLG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 892
swis2-VHDL20_DWLG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 922
swis2-VHDL20_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1019
swis2-VHDL20_DWLG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1058
swis2-VHDL20_DWLH_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:43 1539
swis2-VHDL20_DWLH_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:14 1440
swis2-VHDL20_DWLH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:28 1604
swis2-VHDL20_DWLH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1229
swis2-VHDL20_DWLH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 953
swis2-VHDL20_DWLH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 1031
swis2-VHDL20_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1128
swis2-VHDL20_DWLH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1174
swis2-VHDL20_DWLI_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:43 1160
swis2-VHDL20_DWLI_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:14 1118
swis2-VHDL20_DWLI_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:28 1376
swis2-VHDL20_DWLI_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 939
swis2-VHDL20_DWLI_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 860
swis2-VHDL20_DWLI_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 890
swis2-VHDL20_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 987
swis2-VHDL20_DWLI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1111
swis2-VHDL20_DWMO_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:03 1507
swis2-VHDL20_DWMO_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:08 1513
swis2-VHDL20_DWMO_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 1741
swis2-VHDL20_DWMO_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1562
swis2-VHDL20_DWMO_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1398
swis2-VHDL20_DWMO_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:05 1316
swis2-VHDL20_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1406
swis2-VHDL20_DWMO_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1524
swis2-VHDL20_DWMP_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:03 1690
swis2-VHDL20_DWMP_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:08 1587
swis2-VHDL20_DWMP_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:15 1698
swis2-VHDL20_DWMP_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1577
swis2-VHDL20_DWMP_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1248
swis2-VHDL20_DWMP_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:05 1166
swis2-VHDL20_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1271
swis2-VHDL20_DWMP_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1332
swis2-VHDL20_DWPG_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:43 1302
swis2-VHDL20_DWPG_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:14 1278
swis2-VHDL20_DWPG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:28 1363
swis2-VHDL20_DWPG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1011
swis2-VHDL20_DWPG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 932
swis2-VHDL20_DWPG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 948
swis2-VHDL20_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1045
swis2-VHDL20_DWPG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1205
swis2-VHDL20_DWPH_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:43 1416
swis2-VHDL20_DWPH_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:14 1385
swis2-VHDL20_DWPH_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:28 1645
swis2-VHDL20_DWPH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1168
swis2-VHDL20_DWPH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 1065
swis2-VHDL20_DWPH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 1028
swis2-VHDL20_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1125
swis2-VHDL20_DWPH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1396
swis2-VHDL20_DWSG_110200-2610110200-dsw--0-ia5 11-Oct-2026 02:30:03 1034
swis2-VHDL20_DWSG_110400-2610110400-dsw--0-ia5 11-Oct-2026 05:00:18 1026
swis2-VHDL20_DWSG_110800-2610110800-dsw--0-ia5 11-Oct-2026 08:30:13 1257
swis2-VHDL20_DWSG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1339
swis2-VHDL20_DWSG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1313
swis2-VHDL20_DWSG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1142
swis2-VHDL20_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1283
swis2-VHDL20_DWSG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1472
wst04-VHDL20_DWEG_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:20 241576
wst04-VHDL20_DWEG_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:14 241498
wst04-VHDL20_DWEG_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:15 242268
wst04-VHDL20_DWEG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 239275
wst04-VHDL20_DWEG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 239621
wst04-VHDL20_DWEG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 239463
wst04-VHDL20_DWEG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 240159
wst04-VHDL20_DWEG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 236868
wst04-VHDL20_DWEH_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:20 238437
wst04-VHDL20_DWEH_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:14 238617
wst04-VHDL20_DWEH_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:15 239391
wst04-VHDL20_DWEH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 233627
wst04-VHDL20_DWEH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 233124
wst04-VHDL20_DWEH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 233242
wst04-VHDL20_DWEH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 233869
wst04-VHDL20_DWEH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 233914
wst04-VHDL20_DWEI_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:31 346601
wst04-VHDL20_DWEI_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:18 346489
wst04-VHDL20_DWEI_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:28 347478
wst04-VHDL20_DWEI_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 342950
wst04-VHDL20_DWEI_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 342863
wst04-VHDL20_DWEI_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 342630
wst04-VHDL20_DWEI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 342769
wst04-VHDL20_DWEI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 338625
wst04-VHDL20_DWHG_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:45:20 340114
wst04-VHDL20_DWHG_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:18 339900
wst04-VHDL20_DWHG_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:46:21 341129
wst04-VHDL20_DWHG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:45:25 336222
wst04-VHDL20_DWHG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:46:34 335748
wst04-VHDL20_DWHG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 335544
wst04-VHDL20_DWHG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:45:19 337001
wst04-VHDL20_DWHG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:45:18 338453
wst04-VHDL20_DWHH_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:45:20 336358
wst04-VHDL20_DWHH_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:24 233122
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wst04-VHDL20_DWLG_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:43 324576
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wst04-VHDL20_DWLG_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:54 325274
wst04-VHDL20_DWLG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:22 327024
wst04-VHDL20_DWLG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 326571
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wst04-VHDL20_DWLG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 324514
wst04-VHDL20_DWLH_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:43 330110
wst04-VHDL20_DWLH_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:44 328913
wst04-VHDL20_DWLH_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:54 329917
wst04-VHDL20_DWLH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:22 326525
wst04-VHDL20_DWLH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:39 326403
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wst04-VHDL20_DWLI_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:54 375806
wst04-VHDL20_DWLI_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:28 328062
wst04-VHDL20_DWLI_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 328241
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wst04-VHDL20_DWLI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 373071
wst04-VHDL20_DWLI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 326451
wst04-VHDL20_DWMO_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:20 452915
wst04-VHDL20_DWMO_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:18 453061
wst04-VHDL20_DWMO_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:28 453317
wst04-VHDL20_DWMO_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:17 342029
wst04-VHDL20_DWMO_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 443807
wst04-VHDL20_DWMO_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 443620
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wst04-VHDL20_DWMO_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 347149
wst04-VHDL20_DWMP_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:31 560638
wst04-VHDL20_DWMP_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:18 560100
wst04-VHDL20_DWMP_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:28 462427
wst04-VHDL20_DWMP_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:29 447169
wst04-VHDL20_DWMP_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 540899
wst04-VHDL20_DWMP_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 540844
wst04-VHDL20_DWMP_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 446440
wst04-VHDL20_DWMP_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 443945
wst04-VHDL20_DWPG_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:43 240453
wst04-VHDL20_DWPG_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:34 337618
wst04-VHDL20_DWPG_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:54 383055
wst04-VHDL20_DWPG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:28 338516
wst04-VHDL20_DWPG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 239342
wst04-VHDL20_DWPG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:33 338856
wst04-VHDL20_DWPG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 383475
wst04-VHDL20_DWPG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:39 334999
wst04-VHDL20_DWPH_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:43 239734
wst04-VHDL20_DWPH_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:34 239361
wst04-VHDL20_DWPH_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:54 239678
wst04-VHDL20_DWPH_110800_COR-2610110800-omedes-..> 11-Oct-2026 11:38:02 239499
wst04-VHDL20_DWPH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:22 238270
wst04-VHDL20_DWPH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 238196
wst04-VHDL20_DWPH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:33 238322
wst04-VHDL20_DWPH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 238521
wst04-VHDL20_DWPH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 236735
wst04-VHDL20_DWSG_110200-2610110200-omedes--0.pdf 11-Oct-2026 02:30:31 343623
wst04-VHDL20_DWSG_110400-2610110400-omedes--0.pdf 11-Oct-2026 05:00:12 344108
wst04-VHDL20_DWSG_110800-2610110800-omedes--0.pdf 11-Oct-2026 08:30:28 344053
wst04-VHDL20_DWSG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:15 339734
wst04-VHDL20_DWSG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 340350
wst04-VHDL20_DWSG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 339445
wst04-VHDL20_DWSG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 339560
wst04-VHDL20_DWSG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:13 335263