Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Jan-2026 11:39:29 4417
FPDL13_DWMZ_020600 02-Jan-2026 10:34:25 2436
SXDL31_DWAV_010800 01-Jan-2026 10:16:09 14800
SXDL31_DWAV_011800 01-Jan-2026 18:10:43 8988
SXDL31_DWAV_020800 02-Jan-2026 08:33:28 8896
SXDL31_DWAV_021800 02-Jan-2026 17:46:19 14030
SXDL31_DWAV_LATEST 02-Jan-2026 17:46:19 14030
SXDL33_DWAV_010000 01-Jan-2026 12:29:58 7712
SXDL33_DWAV_020000 02-Jan-2026 11:18:33 6976
SXDL33_DWAV_LATEST 02-Jan-2026 11:18:33 6976
ber01-FWDL39_DWMS_011230-2601011230-dsw--0-ia5 01-Jan-2026 13:10:37 2304
ber01-FWDL39_DWMS_011230_COR-2601011230-dsw--0-ia5 01-Jan-2026 14:05:16 2308
ber01-FWDL39_DWMS_021230-2601021230-dsw--0-ia5 02-Jan-2026 13:14:31 2011
ber01-VHDL13_DWEH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:11 5149
ber01-VHDL13_DWEH_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 4881
ber01-VHDL13_DWEH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:16 4691
ber01-VHDL13_DWEH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:17 3293
ber01-VHDL13_DWEH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:36 3517
ber01-VHDL13_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 4355
ber01-VHDL13_DWEH_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:18 4391
ber01-VHDL13_DWEH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:17 4516
ber01-VHDL13_DWEH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:22 4668
ber01-VHDL13_DWEH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:16 3894
ber01-VHDL13_DWHG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:07 4969
ber01-VHDL13_DWHG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 5063
ber01-VHDL13_DWHG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3405
ber01-VHDL13_DWHG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:12 3542
ber01-VHDL13_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3605
ber01-VHDL13_DWHG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3605
ber01-VHDL13_DWHG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:07 3641
ber01-VHDL13_DWHG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:07 4379
ber01-VHDL13_DWHH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:07 3607
ber01-VHDL13_DWHH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3582
ber01-VHDL13_DWHH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3043
ber01-VHDL13_DWHH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:12 3570
ber01-VHDL13_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3589
ber01-VHDL13_DWHH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3589
ber01-VHDL13_DWHH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:07 3446
ber01-VHDL13_DWHH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:07 3853
ber01-VHDL13_DWLG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3532
ber01-VHDL13_DWLG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3774
ber01-VHDL13_DWLG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3910
ber01-VHDL13_DWLG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3192
ber01-VHDL13_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3312
ber01-VHDL13_DWLG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3271
ber01-VHDL13_DWLG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3298
ber01-VHDL13_DWLG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:02:16 3349
ber01-VHDL13_DWLG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2996
ber01-VHDL13_DWLH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3366
ber01-VHDL13_DWLH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3482
ber01-VHDL13_DWLH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3709
ber01-VHDL13_DWLH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3076
ber01-VHDL13_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3105
ber01-VHDL13_DWLH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3063
ber01-VHDL13_DWLH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3341
ber01-VHDL13_DWLH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:02:28 3622
ber01-VHDL13_DWLH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3176
ber01-VHDL13_DWLI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3278
ber01-VHDL13_DWLI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3481
ber01-VHDL13_DWLI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3559
ber01-VHDL13_DWLI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3096
ber01-VHDL13_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3053
ber01-VHDL13_DWLI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3010
ber01-VHDL13_DWLI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3059
ber01-VHDL13_DWLI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:03:11 3085
ber01-VHDL13_DWLI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2784
ber01-VHDL13_DWMG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3851
ber01-VHDL13_DWMG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3851
ber01-VHDL13_DWMG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3945
ber01-VHDL13_DWMG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3568
ber01-VHDL13_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4217
ber01-VHDL13_DWMG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 4176
ber01-VHDL13_DWMG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 4226
ber01-VHDL13_DWMG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 4178
ber01-VHDL13_DWMO_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3491
ber01-VHDL13_DWMO_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3501
ber01-VHDL13_DWMO_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3685
ber01-VHDL13_DWMO_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 2933
ber01-VHDL13_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 3649
ber01-VHDL13_DWMO_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 3616
ber01-VHDL13_DWMO_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3671
ber01-VHDL13_DWMO_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3154
ber01-VHDL13_DWMP_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3965
ber01-VHDL13_DWMP_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3976
ber01-VHDL13_DWMP_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:10 3955
ber01-VHDL13_DWMP_010800_COR-2601010800-dsw--0-ia5 01-Jan-2026 09:40:07 4094
ber01-VHDL13_DWMP_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3737
ber01-VHDL13_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:06 4467
ber01-VHDL13_DWMP_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:03 4435
ber01-VHDL13_DWMP_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 4347
ber01-VHDL13_DWMP_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 4066
ber01-VHDL13_DWOG_010300-2601010300-dsw--0-ia5 01-Jan-2026 04:00:01 6456
ber01-VHDL13_DWOG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 5931
ber01-VHDL13_DWOG_011700-2601011700-dsw--0-ia5 01-Jan-2026 19:00:03 5451
ber01-VHDL13_DWOG_011700_COR-2601011700-dsw--0-ia5 01-Jan-2026 21:39:14 5574
ber01-VHDL13_DWOG_020300-2601020300-dsw--0-ia5 02-Jan-2026 04:00:02 5142
ber01-VHDL13_DWOG_020800-2601020800-dsw--0-ia5 02-Jan-2026 10:56:57 5591
ber01-VHDL13_DWOG_021700-2601021700-dsw--0-ia5 02-Jan-2026 19:00:01 5490
ber01-VHDL13_DWOH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:11 4477
ber01-VHDL13_DWOH_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 4131
ber01-VHDL13_DWOH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:16 4107
ber01-VHDL13_DWOH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:17 2858
ber01-VHDL13_DWOH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:31 2862
ber01-VHDL13_DWOH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3698
ber01-VHDL13_DWOH_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:11 3690
ber01-VHDL13_DWOH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:17 4008
ber01-VHDL13_DWOH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:22 4174
ber01-VHDL13_DWOH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:16 3482
ber01-VHDL13_DWOI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:28:17 3854
ber01-VHDL13_DWOI_010400-2601010400-dsw--0-ia5 01-Jan-2026 05:58:16 3789
ber01-VHDL13_DWOI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:28:12 3778
ber01-VHDL13_DWOI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:28:12 2783
ber01-VHDL13_DWOI_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:36 2787
ber01-VHDL13_DWOI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:28:11 3404
ber01-VHDL13_DWOI_020400-2601020400-dsw--0-ia5 02-Jan-2026 05:58:11 3394
ber01-VHDL13_DWOI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:28:11 3321
ber01-VHDL13_DWOI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 09:53:16 3637
ber01-VHDL13_DWOI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:28:12 2933
ber01-VHDL13_DWON_010228-2601010228-dsw--0-ia5 01-Jan-2026 02:28:51 4260
ber01-VHDL13_DWON_010625-2601010625-dsw--0-ia5 01-Jan-2026 06:25:47 4975
ber01-VHDL13_DWON_010929-2601010929-dsw--0-ia5 01-Jan-2026 09:29:28 4975
ber01-VHDL13_DWON_011410-2601011410-dsw--0-ia5 01-Jan-2026 14:11:01 4573
ber01-VHDL13_DWON_011841-2601011841-dsw--0-ia5 01-Jan-2026 18:41:21 3765
ber01-VHDL13_DWON_012138-2601012138-dsw--0-ia5 01-Jan-2026 21:38:41 3434
ber01-VHDL13_DWON_012324-2601012324-dsw--0-ia5 01-Jan-2026 23:24:11 3289
ber01-VHDL13_DWON_020356-2601020356-dsw--0-ia5 02-Jan-2026 03:56:26 3289
ber01-VHDL13_DWON_020629-2601020629-dsw--0-ia5 02-Jan-2026 06:29:12 3755
ber01-VHDL13_DWON_020718-2601020718-dsw--0-ia5 02-Jan-2026 07:18:26 3896
ber01-VHDL13_DWON_021056-2601021056-dsw--0-ia5 02-Jan-2026 10:56:33 3896
ber01-VHDL13_DWON_021533-2601021533-dsw--0-ia5 02-Jan-2026 15:33:41 3205
ber01-VHDL13_DWON_021539-2601021539-dsw--0-ia5 02-Jan-2026 15:39:26 3452
ber01-VHDL13_DWON_021719-2601021719-dsw--0-ia5 02-Jan-2026 17:19:26 3599
ber01-VHDL13_DWON_021746-2601021746-dsw--0-ia5 02-Jan-2026 17:46:23 3599
ber01-VHDL13_DWON_022054-2601022054-dsw--0-ia5 02-Jan-2026 20:55:02 3471
ber01-VHDL13_DWPG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 2685
ber01-VHDL13_DWPG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 2790
ber01-VHDL13_DWPG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 2918
ber01-VHDL13_DWPG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 2394
ber01-VHDL13_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 2476
ber01-VHDL13_DWPG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 2524
ber01-VHDL13_DWPG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 2662
ber01-VHDL13_DWPG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:08:27 3064
ber01-VHDL13_DWPG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 2853
ber01-VHDL13_DWPH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3816
ber01-VHDL13_DWPH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:02 3790
ber01-VHDL13_DWPH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 3776
ber01-VHDL13_DWPH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:01 3212
ber01-VHDL13_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3099
ber01-VHDL13_DWPH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 3115
ber01-VHDL13_DWPH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3122
ber01-VHDL13_DWPH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:09:32 3399
ber01-VHDL13_DWPH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3103
ber01-VHDL13_DWSG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:30:01 3286
ber01-VHDL13_DWSG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3560
ber01-VHDL13_DWSG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:30:01 4213
ber01-VHDL13_DWSG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:30:05 3579
ber01-VHDL13_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:30:01 3726
ber01-VHDL13_DWSG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:07 4144
ber01-VHDL13_DWSG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:30:03 3908
ber01-VHDL13_DWSG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:30:01 3472
ber01-VHDL17_DWOG_011200-2601011200-dsw--0-ia5 01-Jan-2026 12:55:27 2759
ber01-VHDL17_DWOG_021200-2601021200-dsw--0-ia5 02-Jan-2026 12:38:21 2766
swis2-VHDL20_DWEG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4950
swis2-VHDL20_DWEG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 4723
swis2-VHDL20_DWEG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4929
swis2-VHDL20_DWEG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3452
swis2-VHDL20_DWEG_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 3456
swis2-VHDL20_DWEG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4171
swis2-VHDL20_DWEG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4093
swis2-VHDL20_DWEG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4819
swis2-VHDL20_DWEG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:02:56 5365
swis2-VHDL20_DWEG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4308
swis2-VHDL20_DWEH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 5728
swis2-VHDL20_DWEH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 5495
swis2-VHDL20_DWEH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 5627
swis2-VHDL20_DWEH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3921
swis2-VHDL20_DWEH_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 4145
swis2-VHDL20_DWEH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4976
swis2-VHDL20_DWEH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4895
swis2-VHDL20_DWEH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 5503
swis2-VHDL20_DWEH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:01:46 5768
swis2-VHDL20_DWEH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4632
swis2-VHDL20_DWEI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:08 4303
swis2-VHDL20_DWEI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 4334
swis2-VHDL20_DWEI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4688
swis2-VHDL20_DWEI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3324
swis2-VHDL20_DWEI_011800_COR-2601011800-dsw--0-ia5 01-Jan-2026 19:56:21 3328
swis2-VHDL20_DWEI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 3870
swis2-VHDL20_DWEI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 3871
swis2-VHDL20_DWEI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4474
swis2-VHDL20_DWEI_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 10:04:21 4674
swis2-VHDL20_DWEI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3583
swis2-VHDL20_DWHG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 5155
swis2-VHDL20_DWHG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 5246
swis2-VHDL20_DWHG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4400
swis2-VHDL20_DWHG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3725
swis2-VHDL20_DWHG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3791
swis2-VHDL20_DWHG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3788
swis2-VHDL20_DWHG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4373
swis2-VHDL20_DWHG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4562
swis2-VHDL20_DWHH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3793
swis2-VHDL20_DWHH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:06 3768
swis2-VHDL20_DWHH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 3760
swis2-VHDL20_DWHH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3756
swis2-VHDL20_DWHH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3775
swis2-VHDL20_DWHH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3775
swis2-VHDL20_DWHH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4128
swis2-VHDL20_DWHH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4039
swis2-VHDL20_DWLG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3935
swis2-VHDL20_DWLG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 4252
swis2-VHDL20_DWLG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4634
swis2-VHDL20_DWLG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3670
swis2-VHDL20_DWLG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3793
swis2-VHDL20_DWLG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3713
swis2-VHDL20_DWLG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3945
swis2-VHDL20_DWLG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 15:03:40 3996
swis2-VHDL20_DWLG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3438
swis2-VHDL20_DWLH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3789
swis2-VHDL20_DWLH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3962
swis2-VHDL20_DWLH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4437
swis2-VHDL20_DWLH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3556
swis2-VHDL20_DWLH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3588
swis2-VHDL20_DWLH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3510
swis2-VHDL20_DWLH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3994
swis2-VHDL20_DWLH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3623
swis2-VHDL20_DWLI_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3710
swis2-VHDL20_DWLI_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3960
swis2-VHDL20_DWLI_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4284
swis2-VHDL20_DWLI_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3575
swis2-VHDL20_DWLI_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3541
swis2-VHDL20_DWLI_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3455
swis2-VHDL20_DWLI_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3709
swis2-VHDL20_DWLI_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3229
swis2-VHDL20_DWMG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4313
swis2-VHDL20_DWMG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 4348
swis2-VHDL20_DWMG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4648
swis2-VHDL20_DWMG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4004
swis2-VHDL20_DWMG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4642
swis2-VHDL20_DWMG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4695
swis2-VHDL20_DWMG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4951
swis2-VHDL20_DWMG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4693
swis2-VHDL20_DWMO_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4018
swis2-VHDL20_DWMO_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 3936
swis2-VHDL20_DWMO_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4329
swis2-VHDL20_DWMO_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3373
swis2-VHDL20_DWMO_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4083
swis2-VHDL20_DWMO_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4091
swis2-VHDL20_DWMO_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 4355
swis2-VHDL20_DWMO_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3626
swis2-VHDL20_DWMP_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:08 4457
swis2-VHDL20_DWMP_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:01 4472
swis2-VHDL20_DWMP_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:06 4797
swis2-VHDL20_DWMP_010800_COR-2601010800-dsw--0-ia5 01-Jan-2026 09:40:07 4801
swis2-VHDL20_DWMP_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4169
swis2-VHDL20_DWMP_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:02 4900
swis2-VHDL20_DWMP_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4946
swis2-VHDL20_DWMP_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 5069
swis2-VHDL20_DWMP_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 4568
swis2-VHDL20_DWPG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3011
swis2-VHDL20_DWPG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 3326
swis2-VHDL20_DWPG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 3797
swis2-VHDL20_DWPG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 3273
swis2-VHDL20_DWPG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3015
swis2-VHDL20_DWPG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:16 3000
swis2-VHDL20_DWPG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3318
swis2-VHDL20_DWPG_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:13:01 3750
swis2-VHDL20_DWPG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3534
swis2-VHDL20_DWPH_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 4219
swis2-VHDL20_DWPH_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:00:12 4328
swis2-VHDL20_DWPH_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4655
swis2-VHDL20_DWPH_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4091
swis2-VHDL20_DWPH_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 3637
swis2-VHDL20_DWPH_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:00:11 3593
swis2-VHDL20_DWPH_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:02 3776
swis2-VHDL20_DWPH_020800_COR-2601020800-dsw--0-ia5 02-Jan-2026 14:13:16 4083
swis2-VHDL20_DWPH_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3784
swis2-VHDL20_DWSG_010200-2601010200-dsw--0-ia5 01-Jan-2026 03:45:07 3682
swis2-VHDL20_DWSG_010400-2601010400-dsw--0-ia5 01-Jan-2026 06:15:06 3998
swis2-VHDL20_DWSG_010800-2601010800-dsw--0-ia5 01-Jan-2026 09:45:02 4894
swis2-VHDL20_DWSG_011300-2601011300-dsw--0-ia5 01-Jan-2026 14:45:07 4713
swis2-VHDL20_DWSG_011800-2601011800-dsw--0-ia5 01-Jan-2026 19:45:03 4052
swis2-VHDL20_DWSG_020200-2601020200-dsw--0-ia5 02-Jan-2026 03:45:07 4187
swis2-VHDL20_DWSG_020400-2601020400-dsw--0-ia5 02-Jan-2026 06:15:02 4614
swis2-VHDL20_DWSG_020800-2601020800-dsw--0-ia5 02-Jan-2026 09:45:06 4571
swis2-VHDL20_DWSG_021300-2601021300-dsw--0-ia5 02-Jan-2026 14:45:07 4445
swis2-VHDL20_DWSG_021800-2601021800-dsw--0-ia5 02-Jan-2026 19:45:01 3909
wst04-VHDL20_DWEG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 227426
wst04-VHDL20_DWEG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:26 226701
wst04-VHDL20_DWEG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 227286
wst04-VHDL20_DWEG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 224295
wst04-VHDL20_DWEG_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:36 224295
wst04-VHDL20_DWEG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 226084
wst04-VHDL20_DWEG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:27 225388
wst04-VHDL20_DWEG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 230038
wst04-VHDL20_DWEG_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:32 230163
wst04-VHDL20_DWEG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 228453
wst04-VHDL20_DWEH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 224168
wst04-VHDL20_DWEH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:22 223435
wst04-VHDL20_DWEH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 224538
wst04-VHDL20_DWEH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 222030
wst04-VHDL20_DWEH_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:31 222348
wst04-VHDL20_DWEH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 223887
wst04-VHDL20_DWEH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:21 223353
wst04-VHDL20_DWEH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 225172
wst04-VHDL20_DWEH_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:22 225201
wst04-VHDL20_DWEH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 223694
wst04-VHDL20_DWEI_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 309503
wst04-VHDL20_DWEI_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:26 309344
wst04-VHDL20_DWEI_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 312145
wst04-VHDL20_DWEI_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 310178
wst04-VHDL20_DWEI_011800_COR-2601011800-omedes-..> 01-Jan-2026 19:56:36 310178
wst04-VHDL20_DWEI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 310056
wst04-VHDL20_DWEI_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:27 309991
wst04-VHDL20_DWEI_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:22 314465
wst04-VHDL20_DWEI_020800_COR-2601020800-omedes-..> 02-Jan-2026 09:53:26 314465
wst04-VHDL20_DWEI_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 313821
wst04-VHDL20_DWHG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:13 312550
wst04-VHDL20_DWHG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:12 312682
wst04-VHDL20_DWHG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:12 306504
wst04-VHDL20_DWHG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 303262
wst04-VHDL20_DWHG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 303500
wst04-VHDL20_DWHG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:11 303534
wst04-VHDL20_DWHG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 308191
wst04-VHDL20_DWHG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 307802
wst04-VHDL20_DWHH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 307628
wst04-VHDL20_DWHH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:12 307639
wst04-VHDL20_DWHH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:12 310942
wst04-VHDL20_DWHH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 309971
wst04-VHDL20_DWHH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 310034
wst04-VHDL20_DWHH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:11 310078
wst04-VHDL20_DWHH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:12 309924
wst04-VHDL20_DWHH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:13 310099
wst04-VHDL20_DWLG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:27 302849
wst04-VHDL20_DWLG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 303107
wst04-VHDL20_DWLG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 297347
wst04-VHDL20_DWLG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 295943
wst04-VHDL20_DWLG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 295652
wst04-VHDL20_DWLG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 295828
wst04-VHDL20_DWLG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 305055
wst04-VHDL20_DWLG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 304799
wst04-VHDL20_DWLH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 294276
wst04-VHDL20_DWLH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 294452
wst04-VHDL20_DWLH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 295811
wst04-VHDL20_DWLH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:25 294143
wst04-VHDL20_DWLH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 293642
wst04-VHDL20_DWLH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 293828
wst04-VHDL20_DWLH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 304936
wst04-VHDL20_DWLH_020800_COR-2601020800-omedes-..> 02-Jan-2026 15:04:17 305582
wst04-VHDL20_DWLH_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:27 305011
wst04-VHDL20_DWLI_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 296417
wst04-VHDL20_DWLI_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:41 296725
wst04-VHDL20_DWLI_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:32 294356
wst04-VHDL20_DWLI_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 293514
wst04-VHDL20_DWLI_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 292952
wst04-VHDL20_DWLI_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:41 293253
wst04-VHDL20_DWLI_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:26 298333
wst04-VHDL20_DWLI_020800_COR-2601020800-omedes-..> 02-Jan-2026 15:05:05 298049
wst04-VHDL20_DWLI_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 297174
wst04-VHDL20_DWMG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 499648
wst04-VHDL20_DWMG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 499484
wst04-VHDL20_DWMG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:22 497385
wst04-VHDL20_DWMG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 495463
wst04-VHDL20_DWMG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 496655
wst04-VHDL20_DWMG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:21 496599
wst04-VHDL20_DWMG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 509387
wst04-VHDL20_DWMG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 508707
wst04-VHDL20_DWMO_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:17 399662
wst04-VHDL20_DWMO_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 399921
wst04-VHDL20_DWMO_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:16 399376
wst04-VHDL20_DWMO_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 398471
wst04-VHDL20_DWMO_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 398751
wst04-VHDL20_DWMO_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:17 399245
wst04-VHDL20_DWMO_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 405986
wst04-VHDL20_DWMO_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:17 405090
wst04-VHDL20_DWMP_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:23 516596
wst04-VHDL20_DWMP_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:15:16 518378
wst04-VHDL20_DWMP_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:16 523246
wst04-VHDL20_DWMP_010800_COR-2601010800-omedes-..> 01-Jan-2026 09:40:07 523246
wst04-VHDL20_DWMP_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:17 521250
wst04-VHDL20_DWMP_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:17 520595
wst04-VHDL20_DWMP_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:15:17 522472
wst04-VHDL20_DWMP_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:16 532753
wst04-VHDL20_DWMP_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:21 532322
wst04-VHDL20_DWPG_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:27 307360
wst04-VHDL20_DWPG_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:32 307868
wst04-VHDL20_DWPG_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 344418
wst04-VHDL20_DWPG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:25 299446
wst04-VHDL20_DWPG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:27 299185
wst04-VHDL20_DWPG_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:31 299206
wst04-VHDL20_DWPG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:32 360782
wst04-VHDL20_DWPG_020800_COR-2601020800-omedes-..> 02-Jan-2026 14:11:57 360726
wst04-VHDL20_DWPG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:27 315864
wst04-VHDL20_DWPH_010200-2601010200-omedes--0.pdf 01-Jan-2026 03:45:21 225608
wst04-VHDL20_DWPH_010400-2601010400-omedes--0.pdf 01-Jan-2026 06:00:32 225898
wst04-VHDL20_DWPH_010800-2601010800-omedes--0.pdf 01-Jan-2026 09:45:26 269469
wst04-VHDL20_DWPH_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:21 268173
wst04-VHDL20_DWPH_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:21 223259
wst04-VHDL20_DWPH_020400-2601020400-omedes--0.pdf 02-Jan-2026 06:00:31 223408
wst04-VHDL20_DWPH_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:26 269438
wst04-VHDL20_DWPH_020800_COR-2601020800-omedes-..> 02-Jan-2026 14:12:27 269311
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wst04-VHDL20_DWSG_011300-2601011300-omedes--0.pdf 01-Jan-2026 14:45:26 319738
wst04-VHDL20_DWSG_011800-2601011800-omedes--0.pdf 01-Jan-2026 19:45:11 318146
wst04-VHDL20_DWSG_020200-2601020200-omedes--0.pdf 02-Jan-2026 03:45:11 318413
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wst04-VHDL20_DWSG_020800-2601020800-omedes--0.pdf 02-Jan-2026 09:45:12 328154
wst04-VHDL20_DWSG_021300-2601021300-omedes--0.pdf 02-Jan-2026 14:45:12 328111
wst04-VHDL20_DWSG_021800-2601021800-omedes--0.pdf 02-Jan-2026 19:45:11 327760