Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Jan-2026 14:51:38 4378
FPDL13_DWMZ_060600 06-Jan-2026 14:55:12 4672
SXDL31_DWAV_050800 05-Jan-2026 08:07:29 15692
SXDL31_DWAV_051800 05-Jan-2026 17:54:54 7012
SXDL31_DWAV_060800 06-Jan-2026 09:58:14 13587
SXDL31_DWAV_061800 06-Jan-2026 19:12:59 9223
SXDL31_DWAV_LATEST 06-Jan-2026 19:12:59 9223
SXDL33_DWAV_050000 05-Jan-2026 10:57:14 6295
SXDL33_DWAV_060000 06-Jan-2026 11:07:09 6459
SXDL33_DWAV_LATEST 06-Jan-2026 11:07:09 6459
ber01-FWDL39_DWMS_051230-2601051230-dsw--0-ia5 05-Jan-2026 12:12:37 1250
ber01-FWDL39_DWMS_061230-2601061230-dsw--0-ia5 06-Jan-2026 12:54:42 1678
ber01-VHDL13_DWEH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:28:10 3479
ber01-VHDL13_DWEH_050400-2601050400-dsw--0-ia5 05-Jan-2026 05:58:18 3425
ber01-VHDL13_DWEH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:28:16 3359
ber01-VHDL13_DWEH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:28:16 3481
ber01-VHDL13_DWEH_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:51 3683
ber01-VHDL13_DWEH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:28:16 4036
ber01-VHDL13_DWEH_060400-2601060400-dsw--0-ia5 06-Jan-2026 05:58:17 3591
ber01-VHDL13_DWEH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:28:19 4233
ber01-VHDL13_DWEH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:28:16 4725
ber01-VHDL13_DWHG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:06 3309
ber01-VHDL13_DWHG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3309
ber01-VHDL13_DWHG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 4176
ber01-VHDL13_DWHG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:09 3468
ber01-VHDL13_DWHG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:11 3531
ber01-VHDL13_DWHG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:07 3630
ber01-VHDL13_DWHG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:09 4461
ber01-VHDL13_DWHG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:09 4163
ber01-VHDL13_DWHH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:06 3222
ber01-VHDL13_DWHH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3222
ber01-VHDL13_DWHH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 4561
ber01-VHDL13_DWHH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:09 3872
ber01-VHDL13_DWHH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:11 4130
ber01-VHDL13_DWHH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:07 4149
ber01-VHDL13_DWHH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:09 4107
ber01-VHDL13_DWHH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:09 3831
ber01-VHDL13_DWLG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2329
ber01-VHDL13_DWLG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2370
ber01-VHDL13_DWLG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 2510
ber01-VHDL13_DWLG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2400
ber01-VHDL13_DWLG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 2620
ber01-VHDL13_DWLG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 2549
ber01-VHDL13_DWLG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 2442
ber01-VHDL13_DWLG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 2629
ber01-VHDL13_DWLH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2561
ber01-VHDL13_DWLH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2689
ber01-VHDL13_DWLH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 2915
ber01-VHDL13_DWLH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2614
ber01-VHDL13_DWLH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 2880
ber01-VHDL13_DWLH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 2484
ber01-VHDL13_DWLH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 2429
ber01-VHDL13_DWLH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 3093
ber01-VHDL13_DWLI_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2603
ber01-VHDL13_DWLI_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2685
ber01-VHDL13_DWLI_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 2890
ber01-VHDL13_DWLI_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2654
ber01-VHDL13_DWLI_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 2874
ber01-VHDL13_DWLI_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 2528
ber01-VHDL13_DWLI_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 2602
ber01-VHDL13_DWLI_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 3148
ber01-VHDL13_DWMG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 3055
ber01-VHDL13_DWMG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:06 3063
ber01-VHDL13_DWMG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:02 2861
ber01-VHDL13_DWMG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2819
ber01-VHDL13_DWMG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 3222
ber01-VHDL13_DWMG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 3149
ber01-VHDL13_DWMG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:04 3396
ber01-VHDL13_DWMG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:09 3141
ber01-VHDL13_DWMO_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2989
ber01-VHDL13_DWMO_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2997
ber01-VHDL13_DWMO_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:02 2986
ber01-VHDL13_DWMO_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2829
ber01-VHDL13_DWMO_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 3202
ber01-VHDL13_DWMO_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 3149
ber01-VHDL13_DWMO_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:04 3344
ber01-VHDL13_DWMO_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:09 3201
ber01-VHDL13_DWMP_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2581
ber01-VHDL13_DWMP_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:06 2570
ber01-VHDL13_DWMP_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:02 2503
ber01-VHDL13_DWMP_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2698
ber01-VHDL13_DWMP_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 3196
ber01-VHDL13_DWMP_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 3242
ber01-VHDL13_DWMP_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:04 3609
ber01-VHDL13_DWMP_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:09 3336
ber01-VHDL13_DWOG_050300-2601050300-dsw--0-ia5 05-Jan-2026 04:00:03 5707
ber01-VHDL13_DWOG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:02 5956
ber01-VHDL13_DWOG_051700-2601051700-dsw--0-ia5 05-Jan-2026 19:00:02 5266
ber01-VHDL13_DWOG_051700_COR-2601051700-dsw--0-ia5 05-Jan-2026 21:29:07 6265
ber01-VHDL13_DWOG_060300-2601060300-dsw--0-ia5 06-Jan-2026 04:00:02 6976
ber01-VHDL13_DWOG_060300_COR-2601060300-dsw--0-ia5 06-Jan-2026 21:21:57 7027
ber01-VHDL13_DWOG_060800-2601060800-dsw--0-ia5 06-Jan-2026 11:12:12 6775
ber01-VHDL13_DWOG_061700-2601061700-dsw--0-ia5 06-Jan-2026 19:00:02 5646
ber01-VHDL13_DWOH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:28:10 3372
ber01-VHDL13_DWOH_050400-2601050400-dsw--0-ia5 05-Jan-2026 05:58:12 3098
ber01-VHDL13_DWOH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:28:16 3301
ber01-VHDL13_DWOH_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 10:11:22 3355
ber01-VHDL13_DWOH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:28:16 3112
ber01-VHDL13_DWOH_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:57 3116
ber01-VHDL13_DWOH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:28:12 3911
ber01-VHDL13_DWOH_060400-2601060400-dsw--0-ia5 06-Jan-2026 05:58:12 3331
ber01-VHDL13_DWOH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:28:19 3711
ber01-VHDL13_DWOH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:28:16 3835
ber01-VHDL13_DWOI_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:28:15 3535
ber01-VHDL13_DWOI_050400-2601050400-dsw--0-ia5 05-Jan-2026 05:58:18 3132
ber01-VHDL13_DWOI_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:28:12 3236
ber01-VHDL13_DWOI_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 10:12:22 3289
ber01-VHDL13_DWOI_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:28:12 3044
ber01-VHDL13_DWOI_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:51 3048
ber01-VHDL13_DWOI_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:28:12 3909
ber01-VHDL13_DWOI_060400-2601060400-dsw--0-ia5 06-Jan-2026 05:58:17 3232
ber01-VHDL13_DWOI_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:28:11 3677
ber01-VHDL13_DWOI_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:28:12 3895
ber01-VHDL13_DWON_050019-2601050019-dsw--0-ia5 05-Jan-2026 00:19:56 4090
ber01-VHDL13_DWON_050353-2601050353-dsw--0-ia5 05-Jan-2026 03:53:54 4090
ber01-VHDL13_DWON_050625-2601050625-dsw--0-ia5 05-Jan-2026 06:25:07 4090
ber01-VHDL13_DWON_050806-2601050806-dsw--0-ia5 05-Jan-2026 08:06:21 4775
ber01-VHDL13_DWON_051559-2601051559-dsw--0-ia5 05-Jan-2026 15:59:39 3948
ber01-VHDL13_DWON_051604-2601051604-dsw--0-ia5 05-Jan-2026 16:05:04 3967
ber01-VHDL13_DWON_051838-2601051838-dsw--0-ia5 05-Jan-2026 18:38:31 3912
ber01-VHDL13_DWON_052128-2601052128-dsw--0-ia5 05-Jan-2026 21:28:51 5029
ber01-VHDL13_DWON_060303-2601060303-dsw--0-ia5 06-Jan-2026 03:03:21 6014
ber01-VHDL13_DWON_060306-2601060306-dsw--0-ia5 06-Jan-2026 03:06:16 5902
ber01-VHDL13_DWON_060631-2601060631-dsw--0-ia5 06-Jan-2026 06:31:06 5708
ber01-VHDL13_DWON_060644-2601060644-dsw--0-ia5 06-Jan-2026 06:44:12 5262
ber01-VHDL13_DWON_060701-2601060701-dsw--0-ia5 06-Jan-2026 07:01:27 5167
ber01-VHDL13_DWON_060830-2601060830-dsw--0-ia5 06-Jan-2026 08:31:01 5387
ber01-VHDL13_DWON_061111-2601061111-dsw--0-ia5 06-Jan-2026 11:11:41 5387
ber01-VHDL13_DWON_061549-2601061549-dsw--0-ia5 06-Jan-2026 15:49:35 4644
ber01-VHDL13_DWON_061826-2601061826-dsw--0-ia5 06-Jan-2026 18:26:11 4660
ber01-VHDL13_DWON_062121-2601062121-dsw--0-ia5 06-Jan-2026 21:21:46 4725
ber01-VHDL13_DWPG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2402
ber01-VHDL13_DWPG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2551
ber01-VHDL13_DWPG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 2837
ber01-VHDL13_DWPG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2624
ber01-VHDL13_DWPG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 2558
ber01-VHDL13_DWPG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 2374
ber01-VHDL13_DWPG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 2305
ber01-VHDL13_DWPG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 2518
ber01-VHDL13_DWPH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 2340
ber01-VHDL13_DWPH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:03 2299
ber01-VHDL13_DWPH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 2521
ber01-VHDL13_DWPH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 2621
ber01-VHDL13_DWPH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:05 2842
ber01-VHDL13_DWPH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:01 2615
ber01-VHDL13_DWPH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 2559
ber01-VHDL13_DWPH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 2707
ber01-VHDL13_DWSG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:30:02 3379
ber01-VHDL13_DWSG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:06 3390
ber01-VHDL13_DWSG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:30:07 3287
ber01-VHDL13_DWSG_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 11:42:26 3214
ber01-VHDL13_DWSG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:30:06 3452
ber01-VHDL13_DWSG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:30:11 3645
ber01-VHDL13_DWSG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:05 3493
ber01-VHDL13_DWSG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:30:01 3563
ber01-VHDL13_DWSG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:30:05 4091
ber01-VHDL17_DWOG_051200-2601051200-dsw--0-ia5 05-Jan-2026 11:53:11 3881
ber01-VHDL17_DWOG_061200-2601061200-dsw--0-ia5 06-Jan-2026 12:08:47 3589
swis2-VHDL20_DWEG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3915
swis2-VHDL20_DWEG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:07 3569
swis2-VHDL20_DWEG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:07 4121
swis2-VHDL20_DWEG_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 10:13:52 4175
swis2-VHDL20_DWEG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3623
swis2-VHDL20_DWEG_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:41 3627
swis2-VHDL20_DWEG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 4372
swis2-VHDL20_DWEG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:07 3755
swis2-VHDL20_DWEG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:06 4465
swis2-VHDL20_DWEG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 4271
swis2-VHDL20_DWEH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3972
swis2-VHDL20_DWEH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:07 3984
swis2-VHDL20_DWEH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:07 4299
swis2-VHDL20_DWEH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 4077
swis2-VHDL20_DWEH_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:41 4402
swis2-VHDL20_DWEH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 4721
swis2-VHDL20_DWEH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:07 4105
swis2-VHDL20_DWEH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:06 5096
swis2-VHDL20_DWEH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 5255
swis2-VHDL20_DWEI_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 4054
swis2-VHDL20_DWEI_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:07 3686
swis2-VHDL20_DWEI_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:07 4130
swis2-VHDL20_DWEI_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 10:16:17 4183
swis2-VHDL20_DWEI_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3604
swis2-VHDL20_DWEI_051800_COR-2601051800-dsw--0-ia5 05-Jan-2026 19:51:41 3608
swis2-VHDL20_DWEI_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 4409
swis2-VHDL20_DWEI_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:07 3729
swis2-VHDL20_DWEI_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:06 4492
swis2-VHDL20_DWEI_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 4373
swis2-VHDL20_DWHG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3495
swis2-VHDL20_DWHG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3492
swis2-VHDL20_DWHG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 4972
swis2-VHDL20_DWHG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 3651
swis2-VHDL20_DWHG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 3717
swis2-VHDL20_DWHG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:07 3813
swis2-VHDL20_DWHG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 5456
swis2-VHDL20_DWHG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:04 4346
swis2-VHDL20_DWHH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3408
swis2-VHDL20_DWHH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3408
swis2-VHDL20_DWHH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 5369
swis2-VHDL20_DWHH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 4058
swis2-VHDL20_DWHH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 4316
swis2-VHDL20_DWHH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:07 4335
swis2-VHDL20_DWHH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 5122
swis2-VHDL20_DWHH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:04 4017
swis2-VHDL20_DWLG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:01 2714
swis2-VHDL20_DWLG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 2744
swis2-VHDL20_DWLG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3072
swis2-VHDL20_DWLG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 2774
swis2-VHDL20_DWLG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 2997
swis2-VHDL20_DWLG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:11 2933
swis2-VHDL20_DWLG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 2989
swis2-VHDL20_DWLG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3009
swis2-VHDL20_DWLH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:01 2964
swis2-VHDL20_DWLH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3112
swis2-VHDL20_DWLH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3529
swis2-VHDL20_DWLH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 3037
swis2-VHDL20_DWLH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 3306
swis2-VHDL20_DWLH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:11 2874
swis2-VHDL20_DWLH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 2987
swis2-VHDL20_DWLH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3480
swis2-VHDL20_DWLI_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:01 2990
swis2-VHDL20_DWLI_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 3102
swis2-VHDL20_DWLI_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3494
swis2-VHDL20_DWLI_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 3071
swis2-VHDL20_DWLI_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:04 3294
swis2-VHDL20_DWLI_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:11 2914
swis2-VHDL20_DWLI_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 3149
swis2-VHDL20_DWLI_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3529
swis2-VHDL20_DWMG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3520
swis2-VHDL20_DWMG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:02 3540
swis2-VHDL20_DWMG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3582
swis2-VHDL20_DWMG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3374
swis2-VHDL20_DWMG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:04 3647
swis2-VHDL20_DWMG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:01 3597
swis2-VHDL20_DWMG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 3967
swis2-VHDL20_DWMG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:04 3534
swis2-VHDL20_DWMO_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3508
swis2-VHDL20_DWMO_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:07 3477
swis2-VHDL20_DWMO_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3719
swis2-VHDL20_DWMO_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3374
swis2-VHDL20_DWMO_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:04 3613
swis2-VHDL20_DWMO_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:01 3550
swis2-VHDL20_DWMO_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 3929
swis2-VHDL20_DWMO_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3598
swis2-VHDL20_DWMP_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3013
swis2-VHDL20_DWMP_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:07 3001
swis2-VHDL20_DWMP_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3167
swis2-VHDL20_DWMP_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3092
swis2-VHDL20_DWMP_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:04 3591
swis2-VHDL20_DWMP_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:01 3692
swis2-VHDL20_DWMP_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 4192
swis2-VHDL20_DWMP_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:04 3735
swis2-VHDL20_DWPG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:01 2872
swis2-VHDL20_DWPG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 2951
swis2-VHDL20_DWPG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3438
swis2-VHDL20_DWPG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 3267
swis2-VHDL20_DWPG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 3031
swis2-VHDL20_DWPG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:11 2740
swis2-VHDL20_DWPG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 2960
swis2-VHDL20_DWPG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3174
swis2-VHDL20_DWPH_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:01 2809
swis2-VHDL20_DWPH_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:00:12 2701
swis2-VHDL20_DWPH_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:02 3118
swis2-VHDL20_DWPH_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:02 3232
swis2-VHDL20_DWPH_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 3297
swis2-VHDL20_DWPH_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:00:11 2991
swis2-VHDL20_DWPH_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 3221
swis2-VHDL20_DWPH_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 3376
swis2-VHDL20_DWSG_050200-2601050200-dsw--0-ia5 05-Jan-2026 03:45:06 3781
swis2-VHDL20_DWSG_050400-2601050400-dsw--0-ia5 05-Jan-2026 06:15:02 3821
swis2-VHDL20_DWSG_050800-2601050800-dsw--0-ia5 05-Jan-2026 09:45:07 3998
swis2-VHDL20_DWSG_050800_COR-2601050800-dsw--0-ia5 05-Jan-2026 11:42:26 3821
swis2-VHDL20_DWSG_051300-2601051300-dsw--0-ia5 05-Jan-2026 14:45:04 4135
swis2-VHDL20_DWSG_051800-2601051800-dsw--0-ia5 05-Jan-2026 19:45:06 3915
swis2-VHDL20_DWSG_060200-2601060200-dsw--0-ia5 06-Jan-2026 03:45:07 4046
swis2-VHDL20_DWSG_060400-2601060400-dsw--0-ia5 06-Jan-2026 06:15:01 3965
swis2-VHDL20_DWSG_060800-2601060800-dsw--0-ia5 06-Jan-2026 09:45:01 4204
swis2-VHDL20_DWSG_061300-2601061300-dsw--0-ia5 06-Jan-2026 14:45:06 4468
swis2-VHDL20_DWSG_061800-2601061800-dsw--0-ia5 06-Jan-2026 19:45:06 4513
wst04-VHDL20_DWEG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:12 225273
wst04-VHDL20_DWEG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:27 224960
wst04-VHDL20_DWEG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 229040
wst04-VHDL20_DWEG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:16 227844
wst04-VHDL20_DWEG_051800_COR-2601051800-omedes-..> 05-Jan-2026 19:51:57 227844
wst04-VHDL20_DWEG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:11 229226
wst04-VHDL20_DWEG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:21 228748
wst04-VHDL20_DWEG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:22 230339
wst04-VHDL20_DWEG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:12 229910
wst04-VHDL20_DWEH_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:16 226233
wst04-VHDL20_DWEH_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:21 226022
wst04-VHDL20_DWEH_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 228817
wst04-VHDL20_DWEH_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:16 227427
wst04-VHDL20_DWEH_051800_COR-2601051800-omedes-..> 05-Jan-2026 19:51:57 227626
wst04-VHDL20_DWEH_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:11 228566
wst04-VHDL20_DWEH_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:21 228249
wst04-VHDL20_DWEH_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:22 227264
wst04-VHDL20_DWEH_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:16 227437
wst04-VHDL20_DWEI_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:16 309279
wst04-VHDL20_DWEI_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:27 309027
wst04-VHDL20_DWEI_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 314284
wst04-VHDL20_DWEI_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:22 313944
wst04-VHDL20_DWEI_051800_COR-2601051800-omedes-..> 05-Jan-2026 19:51:57 313944
wst04-VHDL20_DWEI_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:17 314430
wst04-VHDL20_DWEI_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:25 314374
wst04-VHDL20_DWEI_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:22 317061
wst04-VHDL20_DWEI_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:21 317152
wst04-VHDL20_DWHG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:12 308212
wst04-VHDL20_DWHG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:12 307855
wst04-VHDL20_DWHG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:16 305106
wst04-VHDL20_DWHG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:16 302660
wst04-VHDL20_DWHG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:11 302827
wst04-VHDL20_DWHG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:11 303002
wst04-VHDL20_DWHG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:16 314550
wst04-VHDL20_DWHG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:12 311939
wst04-VHDL20_DWHH_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:12 301791
wst04-VHDL20_DWHH_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:12 301408
wst04-VHDL20_DWHH_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:16 302480
wst04-VHDL20_DWHH_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:12 300615
wst04-VHDL20_DWHH_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:11 301624
wst04-VHDL20_DWHH_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:11 301787
wst04-VHDL20_DWHH_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:16 300923
wst04-VHDL20_DWHH_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:12 298932
wst04-VHDL20_DWLG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:22 304133
wst04-VHDL20_DWLG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:41 304500
wst04-VHDL20_DWLG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:29 302668
wst04-VHDL20_DWLG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:22 302635
wst04-VHDL20_DWLG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:27 303202
wst04-VHDL20_DWLG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:41 303842
wst04-VHDL20_DWLG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:26 312497
wst04-VHDL20_DWLG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:27 312148
wst04-VHDL20_DWLH_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:26 296362
wst04-VHDL20_DWLH_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:41 296810
wst04-VHDL20_DWLH_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:31 302504
wst04-VHDL20_DWLH_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:26 302101
wst04-VHDL20_DWLH_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:27 302361
wst04-VHDL20_DWLH_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:41 302689
wst04-VHDL20_DWLH_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:32 307038
wst04-VHDL20_DWLH_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:21 307215
wst04-VHDL20_DWLI_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:22 295586
wst04-VHDL20_DWLI_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:41 296047
wst04-VHDL20_DWLI_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:31 300812
wst04-VHDL20_DWLI_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:26 300054
wst04-VHDL20_DWLI_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:21 300500
wst04-VHDL20_DWLI_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:41 300714
wst04-VHDL20_DWLI_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:32 305819
wst04-VHDL20_DWLI_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:21 306405
wst04-VHDL20_DWMG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:16 501253
wst04-VHDL20_DWMG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:21 501221
wst04-VHDL20_DWMG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 505459
wst04-VHDL20_DWMG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:12 506071
wst04-VHDL20_DWMG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:17 506569
wst04-VHDL20_DWMG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:21 505795
wst04-VHDL20_DWMG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:12 511523
wst04-VHDL20_DWMG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:16 511201
wst04-VHDL20_DWMO_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:22 405963
wst04-VHDL20_DWMO_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:17 406440
wst04-VHDL20_DWMO_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 411420
wst04-VHDL20_DWMO_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:12 410739
wst04-VHDL20_DWMO_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:23 411078
wst04-VHDL20_DWMO_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:21 411573
wst04-VHDL20_DWMO_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:12 416350
wst04-VHDL20_DWMO_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:16 415391
wst04-VHDL20_DWMP_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:22 516134
wst04-VHDL20_DWMP_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:21 517160
wst04-VHDL20_DWMP_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:29 519800
wst04-VHDL20_DWMP_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:16 519594
wst04-VHDL20_DWMP_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:17 519287
wst04-VHDL20_DWMP_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:17 519752
wst04-VHDL20_DWMP_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:16 525615
wst04-VHDL20_DWMP_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:16 524451
wst04-VHDL20_DWPG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:26 300083
wst04-VHDL20_DWPG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:31 300608
wst04-VHDL20_DWPG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:31 346600
wst04-VHDL20_DWPG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:22 301308
wst04-VHDL20_DWPG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:21 301091
wst04-VHDL20_DWPG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:32 301485
wst04-VHDL20_DWPG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:32 351680
wst04-VHDL20_DWPG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:27 307658
wst04-VHDL20_DWPH_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:26 220747
wst04-VHDL20_DWPH_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:00:31 220703
wst04-VHDL20_DWPH_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:29 264446
wst04-VHDL20_DWPH_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:22 264472
wst04-VHDL20_DWPH_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:21 219633
wst04-VHDL20_DWPH_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:00:32 219774
wst04-VHDL20_DWPH_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:26 265109
wst04-VHDL20_DWPH_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:21 265623
wst04-VHDL20_DWSG_050200-2601050200-omedes--0.pdf 05-Jan-2026 03:45:16 315253
wst04-VHDL20_DWSG_050400-2601050400-omedes--0.pdf 05-Jan-2026 06:15:17 315300
wst04-VHDL20_DWSG_050800-2601050800-omedes--0.pdf 05-Jan-2026 09:45:21 319897
wst04-VHDL20_DWSG_050800_COR-2601050800-omedes-..> 05-Jan-2026 11:42:32 319535
wst04-VHDL20_DWSG_051300-2601051300-omedes--0.pdf 05-Jan-2026 14:45:13 321005
wst04-VHDL20_DWSG_051800-2601051800-omedes--0.pdf 05-Jan-2026 19:45:12 320461
wst04-VHDL20_DWSG_060200-2601060200-omedes--0.pdf 06-Jan-2026 03:45:17 321443
wst04-VHDL20_DWSG_060400-2601060400-omedes--0.pdf 06-Jan-2026 06:15:17 321744
wst04-VHDL20_DWSG_060800-2601060800-omedes--0.pdf 06-Jan-2026 09:45:12 325737
wst04-VHDL20_DWSG_061300-2601061300-omedes--0.pdf 06-Jan-2026 14:45:12 326329
wst04-VHDL20_DWSG_061800-2601061800-omedes--0.pdf 06-Jan-2026 19:45:12 325672