Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Oct-2026 14:21:58 6238
FPDL13_DWMZ_180600 18-Oct-2026 11:40:55 4391
SXDL31_DWAV_170800 17-Oct-2026 07:20:10 10205
SXDL31_DWAV_171800 17-Oct-2026 17:01:00 7662
SXDL31_DWAV_180800 18-Oct-2026 07:12:06 12713
SXDL31_DWAV_181800 18-Oct-2026 16:40:47 7268
SXDL31_DWAV_LATEST 18-Oct-2026 16:40:47 7268
SXDL33_DWAV_170000 17-Oct-2026 10:05:24 9001
SXDL33_DWAV_180000 18-Oct-2026 09:42:26 8921
SXDL33_DWAV_LATEST 18-Oct-2026 09:42:26 8921
ber01-FWDL39_DWMS_171200-2610171200-dsw--0-ia5 17-Oct-2026 11:43:09 1359
ber01-FWDL39_DWMS_181200-2610181200-dsw--0-ia5 18-Oct-2026 10:18:32 1564
ber01-VHDL13_DWEG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:30 3026
ber01-VHDL13_DWEG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 3194
ber01-VHDL13_DWEH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:30 3233
ber01-VHDL13_DWEH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 3215
ber01-VHDL13_DWEI_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:30 2946
ber01-VHDL13_DWEI_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 2729
ber01-VHDL13_DWHG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:09 3235
ber01-VHDL13_DWHG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 2958
ber01-VHDL13_DWHH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 3477
ber01-VHDL13_DWHH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 3174
ber01-VHDL13_DWLG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:02 2471
ber01-VHDL13_DWLG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:02 2684
ber01-VHDL13_DWLH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:02 2581
ber01-VHDL13_DWLH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:02 2429
ber01-VHDL13_DWLI_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:02 2338
ber01-VHDL13_DWLI_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:02 2344
ber01-VHDL13_DWMO_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 3178
ber01-VHDL13_DWMO_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:04 3483
ber01-VHDL13_DWMP_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 3765
ber01-VHDL13_DWMP_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:04 3537
ber01-VHDL13_DWOG_170300-2610170300-dsw--0-ia5 17-Oct-2026 03:02:14 5273
ber01-VHDL13_DWOG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 4888
ber01-VHDL13_DWOG_171700-2610171700-dsw--0-ia5 17-Oct-2026 18:00:03 4861
ber01-VHDL13_DWOG_171700_COR-2610171700-dsw--0-ia5 17-Oct-2026 17:28:55 4865
ber01-VHDL13_DWOG_180300-2610180300-dsw--0-ia5 18-Oct-2026 03:01:39 4470
ber01-VHDL13_DWOG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 4080
ber01-VHDL13_DWOG_180800_COR-2610180800-dsw--0-ia5 18-Oct-2026 11:49:57 3978
ber01-VHDL13_DWOG_181700-2610181700-dsw--0-ia5 18-Oct-2026 18:00:08 3306
ber01-VHDL13_DWON_170128-2610170128-dsw--0-ia5 17-Oct-2026 01:28:20 3965
ber01-VHDL13_DWON_170252-2610170252-dsw--0-ia5 17-Oct-2026 02:53:26 3965
ber01-VHDL13_DWON_170447-2610170447-dsw--0-ia5 17-Oct-2026 04:47:48 3958
ber01-VHDL13_DWON_170645-2610170645-dsw--0-ia5 17-Oct-2026 06:45:36 4220
ber01-VHDL13_DWON_171054-2610171054-dsw--0-ia5 17-Oct-2026 10:54:22 4220
ber01-VHDL13_DWON_171420-2610171420-dsw--0-ia5 17-Oct-2026 14:20:19 3626
ber01-VHDL13_DWON_171728-2610171728-dsw--0-ia5 17-Oct-2026 17:28:08 4357
ber01-VHDL13_DWON_171933-2610171933-dsw--0-ia5 17-Oct-2026 19:33:35 4292
ber01-VHDL13_DWON_180128-2610180128-dsw--0-ia5 18-Oct-2026 01:28:24 3818
ber01-VHDL13_DWON_180256-2610180256-dsw--0-ia5 18-Oct-2026 02:57:03 3821
ber01-VHDL13_DWON_180440-2610180440-dsw--0-ia5 18-Oct-2026 04:40:18 3821
ber01-VHDL13_DWON_180520-2610180520-dsw--0-ia5 18-Oct-2026 05:20:54 4243
ber01-VHDL13_DWON_180619-2610180619-dsw--0-ia5 18-Oct-2026 06:19:33 4123
ber01-VHDL13_DWON_180814-2610180814-dsw--0-ia5 18-Oct-2026 08:14:49 4123
ber01-VHDL13_DWON_181149-2610181149-dsw--0-ia5 18-Oct-2026 11:49:28 4123
ber01-VHDL13_DWON_181449-2610181449-dsw--0-ia5 18-Oct-2026 14:50:00 3416
ber01-VHDL13_DWON_181709-2610181709-dsw--0-ia5 18-Oct-2026 17:09:58 3346
ber01-VHDL13_DWON_181944-2610181944-dsw--0-ia5 18-Oct-2026 19:44:30 3389
ber01-VHDL13_DWPG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:02 2460
ber01-VHDL13_DWPG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:02 2806
ber01-VHDL13_DWPH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:02 3668
ber01-VHDL13_DWPH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:02 2846
ber01-VHDL13_DWSG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 2689
ber01-VHDL13_DWSG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 2790
ber01-VHDL17_DWOG_171200-2610171200-dsw--0-ia5 17-Oct-2026 11:06:08 2927
ber01-VHDL17_DWOG_181200-2610181200-dsw--0-ia5 18-Oct-2026 10:59:48 2754
swis2-VHDL20_DWEG_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1087
swis2-VHDL20_DWEG_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:01:23 1244
swis2-VHDL20_DWEG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 1534
swis2-VHDL20_DWEG_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:10 959
swis2-VHDL20_DWEG_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:09 1142
swis2-VHDL20_DWEG_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:01:18 1361
swis2-VHDL20_DWEG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 1665
swis2-VHDL20_DWEG_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1302
swis2-VHDL20_DWEH_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1109
swis2-VHDL20_DWEH_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:01:23 1497
swis2-VHDL20_DWEH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 1803
swis2-VHDL20_DWEH_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:10 993
swis2-VHDL20_DWEH_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:09 1119
swis2-VHDL20_DWEH_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:01:18 1394
swis2-VHDL20_DWEH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 1721
swis2-VHDL20_DWEH_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1340
swis2-VHDL20_DWEI_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1134
swis2-VHDL20_DWEI_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:01:23 1318
swis2-VHDL20_DWEI_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 1621
swis2-VHDL20_DWEI_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:10 1005
swis2-VHDL20_DWEI_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:09 1198
swis2-VHDL20_DWEI_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:01:18 1305
swis2-VHDL20_DWEI_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 1621
swis2-VHDL20_DWEI_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1224
swis2-VHDL20_DWHG_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1603
swis2-VHDL20_DWHG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 2025
swis2-VHDL20_DWHG_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:45:09 1875
swis2-VHDL20_DWHG_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:18 1555
swis2-VHDL20_DWHG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 1969
swis2-VHDL20_DWHG_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:45:13 1832
swis2-VHDL20_DWHH_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:46:19 1972
swis2-VHDL20_DWHH_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1972
swis2-VHDL20_DWHH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 2376
swis2-VHDL20_DWHH_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:45:09 2270
swis2-VHDL20_DWHH_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:46:32 1999
swis2-VHDL20_DWHH_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:18 1699
swis2-VHDL20_DWHH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 2181
swis2-VHDL20_DWHH_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:45:13 1924
swis2-VHDL20_DWLG_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:24 1174
swis2-VHDL20_DWLG_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1174
swis2-VHDL20_DWLG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:32 1473
swis2-VHDL20_DWLG_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:31:03 1117
swis2-VHDL20_DWLG_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:23 1172
swis2-VHDL20_DWLG_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:14 1261
swis2-VHDL20_DWLG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:36 1448
swis2-VHDL20_DWLG_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:31:16 1247
swis2-VHDL20_DWLH_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:24 1254
swis2-VHDL20_DWLH_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1215
swis2-VHDL20_DWLH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:32 1570
swis2-VHDL20_DWLH_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:31:03 1222
swis2-VHDL20_DWLH_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:23 1059
swis2-VHDL20_DWLH_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:14 1171
swis2-VHDL20_DWLH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:36 1310
swis2-VHDL20_DWLH_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:31:16 1122
swis2-VHDL20_DWLI_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:24 1145
swis2-VHDL20_DWLI_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1145
swis2-VHDL20_DWLI_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:32 1443
swis2-VHDL20_DWLI_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:31:03 1186
swis2-VHDL20_DWLI_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:23 1170
swis2-VHDL20_DWLI_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:14 1253
swis2-VHDL20_DWLI_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:36 1394
swis2-VHDL20_DWLI_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:31:16 1145
swis2-VHDL20_DWMO_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1597
swis2-VHDL20_DWMO_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:04 1592
swis2-VHDL20_DWMO_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 1703
swis2-VHDL20_DWMO_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:10 1520
swis2-VHDL20_DWMO_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:03 1465
swis2-VHDL20_DWMO_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:08 1433
swis2-VHDL20_DWMO_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:04 1848
swis2-VHDL20_DWMO_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1296
swis2-VHDL20_DWMP_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1685
swis2-VHDL20_DWMP_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:04 1666
swis2-VHDL20_DWMP_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:08 1777
swis2-VHDL20_DWMP_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:10 1542
swis2-VHDL20_DWMP_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:03 1539
swis2-VHDL20_DWMP_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:08 1498
swis2-VHDL20_DWMP_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:04 1935
swis2-VHDL20_DWMP_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1482
swis2-VHDL20_DWPG_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:24 1016
swis2-VHDL20_DWPG_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1030
swis2-VHDL20_DWPG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:32 1301
swis2-VHDL20_DWPG_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:31:03 1244
swis2-VHDL20_DWPG_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:23 1251
swis2-VHDL20_DWPG_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:14 1278
swis2-VHDL20_DWPG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:36 1368
swis2-VHDL20_DWPG_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:31:16 1115
swis2-VHDL20_DWPH_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:24 1533
swis2-VHDL20_DWPH_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1518
swis2-VHDL20_DWPH_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:32 2129
swis2-VHDL20_DWPH_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:31:03 1743
swis2-VHDL20_DWPH_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:23 1702
swis2-VHDL20_DWPH_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:14 1519
swis2-VHDL20_DWPH_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:36 1551
swis2-VHDL20_DWPH_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:31:16 1155
swis2-VHDL20_DWSG_170200-2610170200-dsw--0-ia5 17-Oct-2026 02:30:04 1366
swis2-VHDL20_DWSG_170400-2610170400-dsw--0-ia5 17-Oct-2026 05:00:18 1172
swis2-VHDL20_DWSG_170800-2610170800-dsw--0-ia5 17-Oct-2026 08:30:04 1328
swis2-VHDL20_DWSG_171800-2610171800-dsw--0-ia5 17-Oct-2026 18:30:04 1351
swis2-VHDL20_DWSG_180200-2610180200-dsw--0-ia5 18-Oct-2026 02:30:09 1321
swis2-VHDL20_DWSG_180400-2610180400-dsw--0-ia5 18-Oct-2026 05:00:18 1087
swis2-VHDL20_DWSG_180800-2610180800-dsw--0-ia5 18-Oct-2026 08:30:15 1427
swis2-VHDL20_DWSG_181800-2610181800-dsw--0-ia5 18-Oct-2026 18:30:19 1289
wst04-VHDL20_DWEG_170200-2610170200-omedes--0.pdf 17-Oct-2026 02:30:14 248060
wst04-VHDL20_DWEG_170400-2610170400-omedes--0.pdf 17-Oct-2026 05:00:14 246687
wst04-VHDL20_DWEG_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:30 247879
wst04-VHDL20_DWEG_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:30:18 235775
wst04-VHDL20_DWEG_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:30:21 237774
wst04-VHDL20_DWEG_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:12 237304
wst04-VHDL20_DWEG_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:26 238475
wst04-VHDL20_DWEG_181800-2610181800-omedes--0.pdf 18-Oct-2026 18:30:19 238276
wst04-VHDL20_DWEH_170200-2610170200-omedes--0.pdf 17-Oct-2026 02:30:14 238830
wst04-VHDL20_DWEH_170400-2610170400-omedes--0.pdf 17-Oct-2026 05:00:14 237631
wst04-VHDL20_DWEH_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:30 238424
wst04-VHDL20_DWEH_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:30:18 232682
wst04-VHDL20_DWEH_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:30:21 234036
wst04-VHDL20_DWEH_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:12 233435
wst04-VHDL20_DWEH_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:26 234221
wst04-VHDL20_DWEH_181800-2610181800-omedes--0.pdf 18-Oct-2026 18:30:19 233305
wst04-VHDL20_DWEI_170200-2610170200-omedes--0.pdf 17-Oct-2026 02:30:20 351782
wst04-VHDL20_DWEI_170400-2610170400-omedes--0.pdf 17-Oct-2026 05:00:14 351628
wst04-VHDL20_DWEI_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:30 352431
wst04-VHDL20_DWEI_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:30:18 334425
wst04-VHDL20_DWEI_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:30:21 336636
wst04-VHDL20_DWEI_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:18 336469
wst04-VHDL20_DWEI_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:26 337243
wst04-VHDL20_DWEI_181800-2610181800-omedes--0.pdf 18-Oct-2026 18:30:19 338856
wst04-VHDL20_DWHG_170200-2610170200-omedes--0.pdf 17-Oct-2026 02:46:20 334858
wst04-VHDL20_DWHG_170400-2610170400-omedes--0.pdf 17-Oct-2026 05:00:18 333979
wst04-VHDL20_DWHG_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:32 336152
wst04-VHDL20_DWHG_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:45:16 331537
wst04-VHDL20_DWHG_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:46:32 330359
wst04-VHDL20_DWHG_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:18 330114
wst04-VHDL20_DWHG_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:36 331667
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wst04-VHDL20_DWHH_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:46:32 323328
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wst04-VHDL20_DWMP_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:36 553962
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wst04-VHDL20_DWPH_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:47 237798
wst04-VHDL20_DWPH_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:31:23 239926
wst04-VHDL20_DWPH_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:30:23 240288
wst04-VHDL20_DWPH_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:33 239579
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wst04-VHDL20_DWSG_170200-2610170200-omedes--0.pdf 17-Oct-2026 02:30:14 348957
wst04-VHDL20_DWSG_170400-2610170400-omedes--0.pdf 17-Oct-2026 05:00:14 347336
wst04-VHDL20_DWSG_170800-2610170800-omedes--0.pdf 17-Oct-2026 08:30:30 348347
wst04-VHDL20_DWSG_171800-2610171800-omedes--0.pdf 17-Oct-2026 18:30:18 340347
wst04-VHDL20_DWSG_180200-2610180200-omedes--0.pdf 18-Oct-2026 02:30:19 339363
wst04-VHDL20_DWSG_180400-2610180400-omedes--0.pdf 18-Oct-2026 05:00:12 339164
wst04-VHDL20_DWSG_180800-2610180800-omedes--0.pdf 18-Oct-2026 08:30:26 339190
wst04-VHDL20_DWSG_181800-2610181800-omedes--0.pdf 18-Oct-2026 18:30:19 331873