Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Jul-2026 12:30:16 3243
FPDL13_DWMZ_020600 02-Jul-2026 10:27:24 2369
SXDL31_DWAV_010800 01-Jul-2026 08:26:43 12524
SXDL31_DWAV_011800 01-Jul-2026 16:04:44 7215
SXDL31_DWAV_020800 02-Jul-2026 07:38:12 12716
SXDL31_DWAV_021800 02-Jul-2026 16:06:24 11237
SXDL31_DWAV_LATEST 02-Jul-2026 16:06:24 11237
SXDL33_DWAV_010000 01-Jul-2026 09:52:49 14036
SXDL33_DWAV_020000 02-Jul-2026 10:18:34 7212
SXDL33_DWAV_LATEST 02-Jul-2026 10:18:34 7212
ber01-FWDL39_DWMS_011200-2607011200-dsw--0-ia5 01-Jul-2026 12:14:01 1625
ber01-FWDL39_DWMS_021200-2607021200-dsw--0-ia5 02-Jul-2026 12:16:07 1553
ber01-VHDL13_DWEG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:28:18 2461
ber01-VHDL13_DWEG_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:51:21 2314
ber01-VHDL13_DWEG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:16 2353
ber01-VHDL13_DWEH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:28:18 2574
ber01-VHDL13_DWEH_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:51:41 2265
ber01-VHDL13_DWEH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:22 2621
ber01-VHDL13_DWEH_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:52:42 2622
ber01-VHDL13_DWEI_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:28:18 2134
ber01-VHDL13_DWEI_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:52:01 2059
ber01-VHDL13_DWEI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:16 2220
ber01-VHDL13_DWHG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 3861
ber01-VHDL13_DWHG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3445
ber01-VHDL13_DWHH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 3934
ber01-VHDL13_DWHH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3644
ber01-VHDL13_DWLG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 2729
ber01-VHDL13_DWLG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2378
ber01-VHDL13_DWLH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 3084
ber01-VHDL13_DWLH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2652
ber01-VHDL13_DWLI_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 2544
ber01-VHDL13_DWLI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2264
ber01-VHDL13_DWMO_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 3119
ber01-VHDL13_DWMO_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2620
ber01-VHDL13_DWMP_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 3276
ber01-VHDL13_DWMP_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2862
ber01-VHDL13_DWMP_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:16:36 2866
ber01-VHDL13_DWOG_010300-2607010300-dsw--0-ia5 01-Jul-2026 03:00:02 4215
ber01-VHDL13_DWOG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 4368
ber01-VHDL13_DWOG_011700-2607011700-dsw--0-ia5 01-Jul-2026 18:00:03 4584
ber01-VHDL13_DWOG_011700_COR-2607011700-dsw--0-ia5 01-Jul-2026 16:21:16 4346
ber01-VHDL13_DWOG_020300-2607020300-dsw--0-ia5 02-Jul-2026 03:00:07 4351
ber01-VHDL13_DWOG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 4637
ber01-VHDL13_DWOG_301700-2606301700-dsw--0-ia5 30-Jun-2026 18:00:02 4351
ber01-VHDL13_DWON_010217-2607010217-dsw--0-ia5 01-Jul-2026 02:17:07 3598
ber01-VHDL13_DWON_010528-2607010528-dsw--0-ia5 01-Jul-2026 05:29:01 3997
ber01-VHDL13_DWON_010555-2607010555-dsw--0-ia5 01-Jul-2026 05:55:57 3910
ber01-VHDL13_DWON_010807-2607010807-dsw--0-ia5 01-Jul-2026 08:07:21 3910
ber01-VHDL13_DWON_011449-2607011449-dsw--0-ia5 01-Jul-2026 14:50:01 3741
ber01-VHDL13_DWON_011458-2607011458-dsw--0-ia5 01-Jul-2026 14:58:40 3735
ber01-VHDL13_DWON_011620-2607011620-dsw--0-ia5 01-Jul-2026 16:20:56 3658
ber01-VHDL13_DWON_011703-2607011703-dsw--0-ia5 01-Jul-2026 17:03:22 4018
ber01-VHDL13_DWON_020118-2607020118-dsw--0-ia5 02-Jul-2026 01:18:31 4349
ber01-VHDL13_DWON_020233-2607020233-dsw--0-ia5 02-Jul-2026 02:33:26 4349
ber01-VHDL13_DWON_020508-2607020508-dsw--0-ia5 02-Jul-2026 05:08:37 4079
ber01-VHDL13_DWON_020540-2607020540-dsw--0-ia5 02-Jul-2026 05:40:07 4138
ber01-VHDL13_DWON_020629-2607020629-dsw--0-ia5 02-Jul-2026 06:29:56 4138
ber01-VHDL13_DWON_020810-2607020810-dsw--0-ia5 02-Jul-2026 08:10:22 4138
ber01-VHDL13_DWON_021455-2607021455-dsw--0-ia5 02-Jul-2026 14:55:50 4084
ber01-VHDL13_DWON_021630-2607021630-dsw--0-ia5 02-Jul-2026 16:30:57 3853
ber01-VHDL13_DWON_021658-2607021658-dsw--0-ia5 02-Jul-2026 16:58:42 3853
ber01-VHDL13_DWON_302343-2606302343-dsw--0-ia5 30-Jun-2026 23:44:01 3587
ber01-VHDL13_DWPG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 2833
ber01-VHDL13_DWPG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2260
ber01-VHDL13_DWPH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 3997
ber01-VHDL13_DWPH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3232
ber01-VHDL13_DWSG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 2750
ber01-VHDL13_DWSG_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 10:48:57 2764
ber01-VHDL13_DWSG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 2121
ber01-VHDL17_DWOG_011200-2607011200-dsw--0-ia5 01-Jul-2026 10:21:21 3396
ber01-VHDL17_DWOG_021200-2607021200-dsw--0-ia5 02-Jul-2026 11:49:06 3114
swis2-VHDL20_DWEG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1529
swis2-VHDL20_DWEG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 1126
swis2-VHDL20_DWEG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 1165
swis2-VHDL20_DWEG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1074
swis2-VHDL20_DWEG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 782
swis2-VHDL20_DWEG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 774
swis2-VHDL20_DWEG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 886
swis2-VHDL20_DWEG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1692
swis2-VHDL20_DWEH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1118
swis2-VHDL20_DWEH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 1102
swis2-VHDL20_DWEH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 1208
swis2-VHDL20_DWEH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1160
swis2-VHDL20_DWEH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 854
swis2-VHDL20_DWEH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 858
swis2-VHDL20_DWEH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 1131
swis2-VHDL20_DWEH_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:51:38 1135
swis2-VHDL20_DWEH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1700
swis2-VHDL20_DWEI_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 922
swis2-VHDL20_DWEI_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 963
swis2-VHDL20_DWEI_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 1075
swis2-VHDL20_DWEI_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1068
swis2-VHDL20_DWEI_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 801
swis2-VHDL20_DWEI_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 794
swis2-VHDL20_DWEI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 913
swis2-VHDL20_DWEI_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1450
swis2-VHDL20_DWHG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:45:45 1483
swis2-VHDL20_DWHG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1495
swis2-VHDL20_DWHG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:45:13 1966
swis2-VHDL20_DWHG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:45:07 1844
swis2-VHDL20_DWHG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:45:02 1450
swis2-VHDL20_DWHG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 1447
swis2-VHDL20_DWHG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:45:17 1512
swis2-VHDL20_DWHG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:45:07 1831
swis2-VHDL20_DWHH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:45:45 1760
swis2-VHDL20_DWHH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1773
swis2-VHDL20_DWHH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:45:13 2188
swis2-VHDL20_DWHH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:45:07 2117
swis2-VHDL20_DWHH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:45:02 1735
swis2-VHDL20_DWHH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 1735
swis2-VHDL20_DWHH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:45:17 1694
swis2-VHDL20_DWHH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:45:07 2157
swis2-VHDL20_DWLG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1787
swis2-VHDL20_DWLG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1639
swis2-VHDL20_DWLG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:22 1318
swis2-VHDL20_DWLG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1180
swis2-VHDL20_DWLG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 879
swis2-VHDL20_DWLG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 865
swis2-VHDL20_DWLG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1073
swis2-VHDL20_DWLG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1928
swis2-VHDL20_DWLH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1003
swis2-VHDL20_DWLH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1235
swis2-VHDL20_DWLH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:22 1659
swis2-VHDL20_DWLH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1485
swis2-VHDL20_DWLH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 1105
swis2-VHDL20_DWLH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 1103
swis2-VHDL20_DWLH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1306
swis2-VHDL20_DWLH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1601
swis2-VHDL20_DWLI_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1458
swis2-VHDL20_DWLI_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1485
swis2-VHDL20_DWLI_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:22 1151
swis2-VHDL20_DWLI_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 942
swis2-VHDL20_DWLI_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 803
swis2-VHDL20_DWLI_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 781
swis2-VHDL20_DWLI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 904
swis2-VHDL20_DWLI_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1640
swis2-VHDL20_DWMO_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1431
swis2-VHDL20_DWMO_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:01 1417
swis2-VHDL20_DWMO_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 1458
swis2-VHDL20_DWMO_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1225
swis2-VHDL20_DWMO_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:03 1106
swis2-VHDL20_DWMO_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:02 941
swis2-VHDL20_DWMO_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 862
swis2-VHDL20_DWMO_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1964
swis2-VHDL20_DWMP_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1461
swis2-VHDL20_DWMP_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:01 1445
swis2-VHDL20_DWMP_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:20 1479
swis2-VHDL20_DWMP_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1201
swis2-VHDL20_DWMP_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:03 1115
swis2-VHDL20_DWMP_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:02 949
swis2-VHDL20_DWMP_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 1050
swis2-VHDL20_DWMP_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:16:36 3364
swis2-VHDL20_DWMP_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1970
swis2-VHDL20_DWPG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1229
swis2-VHDL20_DWPG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1225
swis2-VHDL20_DWPG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:22 1480
swis2-VHDL20_DWPG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1131
swis2-VHDL20_DWPG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 985
swis2-VHDL20_DWPG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 894
swis2-VHDL20_DWPG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1000
swis2-VHDL20_DWPG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1501
swis2-VHDL20_DWPH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1526
swis2-VHDL20_DWPH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1347
swis2-VHDL20_DWPH_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:22 2540
swis2-VHDL20_DWPH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1710
swis2-VHDL20_DWPH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 1555
swis2-VHDL20_DWPH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 1303
swis2-VHDL20_DWPH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1496
swis2-VHDL20_DWPH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 2013
swis2-VHDL20_DWSG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1418
swis2-VHDL20_DWSG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1445
swis2-VHDL20_DWSG_010800-2607010800-dsw--0-ia5 01-Jul-2026 08:30:02 1239
swis2-VHDL20_DWSG_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 10:48:57 1253
swis2-VHDL20_DWSG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:07 850
swis2-VHDL20_DWSG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:07 967
swis2-VHDL20_DWSG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 790
swis2-VHDL20_DWSG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 831
swis2-VHDL20_DWSG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1854
wst04-VHDL20_DWEG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 240004
wst04-VHDL20_DWEG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 240088
wst04-VHDL20_DWEG_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:20 240482
wst04-VHDL20_DWEG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:11 240485
wst04-VHDL20_DWEG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 239270
wst04-VHDL20_DWEG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 239097
wst04-VHDL20_DWEG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:12 239876
wst04-VHDL20_DWEG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 240881
wst04-VHDL20_DWEH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 237448
wst04-VHDL20_DWEH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 238108
wst04-VHDL20_DWEH_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:20 238794
wst04-VHDL20_DWEH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:11 235995
wst04-VHDL20_DWEH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 235144
wst04-VHDL20_DWEH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 235181
wst04-VHDL20_DWEH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:12 236229
wst04-VHDL20_DWEH_020800_COR-2607020800-omedes-..> 02-Jul-2026 09:51:16 231029
wst04-VHDL20_DWEH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 239027
wst04-VHDL20_DWEI_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 341425
wst04-VHDL20_DWEI_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 341703
wst04-VHDL20_DWEI_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:20 341928
wst04-VHDL20_DWEI_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:18 337710
wst04-VHDL20_DWEI_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 337077
wst04-VHDL20_DWEI_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 336855
wst04-VHDL20_DWEI_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:18 337203
wst04-VHDL20_DWEI_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 343297
wst04-VHDL20_DWHG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:45:45 350379
wst04-VHDL20_DWHG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 350381
wst04-VHDL20_DWHG_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:45:13 351985
wst04-VHDL20_DWHG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:45:12 338601
wst04-VHDL20_DWHG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:45:12 336850
wst04-VHDL20_DWHG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:17 336630
wst04-VHDL20_DWHG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:45:17 337591
wst04-VHDL20_DWHG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:45:16 351959
wst04-VHDL20_DWHH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:45:45 334998
wst04-VHDL20_DWHH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 229800
wst04-VHDL20_DWHH_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:45:12 335975
wst04-VHDL20_DWHH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:45:12 329958
wst04-VHDL20_DWHH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:45:12 328750
wst04-VHDL20_DWHH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:17 226837
wst04-VHDL20_DWHH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:45:17 328055
wst04-VHDL20_DWHH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:45:16 336004
wst04-VHDL20_DWLG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 343468
wst04-VHDL20_DWLG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 343077
wst04-VHDL20_DWLG_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:41 342776
wst04-VHDL20_DWLG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:22 333263
wst04-VHDL20_DWLG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 332451
wst04-VHDL20_DWLG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:41 331784
wst04-VHDL20_DWLG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:40 332858
wst04-VHDL20_DWLG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 344272
wst04-VHDL20_DWLH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:31 350084
wst04-VHDL20_DWLH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 350244
wst04-VHDL20_DWLH_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:50 351218
wst04-VHDL20_DWLH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:26 330578
wst04-VHDL20_DWLH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:25 330081
wst04-VHDL20_DWLH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:41 329547
wst04-VHDL20_DWLH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:45 330202
wst04-VHDL20_DWLH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 350938
wst04-VHDL20_DWLI_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 344825
wst04-VHDL20_DWLI_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 344460
wst04-VHDL20_DWLI_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:41 389154
wst04-VHDL20_DWLI_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:22 328056
wst04-VHDL20_DWLI_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 327938
wst04-VHDL20_DWLI_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:41 327251
wst04-VHDL20_DWLI_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:40 372395
wst04-VHDL20_DWLI_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 345161
wst04-VHDL20_DWMO_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:18 464037
wst04-VHDL20_DWMO_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 463872
wst04-VHDL20_DWMO_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:20 463728
wst04-VHDL20_DWMO_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 351308
wst04-VHDL20_DWMO_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 457482
wst04-VHDL20_DWMO_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 457753
wst04-VHDL20_DWMO_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:18 457942
wst04-VHDL20_DWMO_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 357395
wst04-VHDL20_DWMP_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:18 590181
wst04-VHDL20_DWMP_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 589994
wst04-VHDL20_DWMP_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:22 478350
wst04-VHDL20_DWMP_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 465214
wst04-VHDL20_DWMP_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 570198
wst04-VHDL20_DWMP_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:17 570424
wst04-VHDL20_DWMP_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:20 465344
wst04-VHDL20_DWMP_020800_COR-2607020800-omedes-..> 02-Jul-2026 09:16:48 574910
wst04-VHDL20_DWMP_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 480820
wst04-VHDL20_DWPG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 247049
wst04-VHDL20_DWPG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:31 353451
wst04-VHDL20_DWPG_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:41 399191
wst04-VHDL20_DWPG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:22 328905
wst04-VHDL20_DWPG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 234108
wst04-VHDL20_DWPG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:31 328232
wst04-VHDL20_DWPG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:40 373269
wst04-VHDL20_DWPG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 353946
wst04-VHDL20_DWPH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 244198
wst04-VHDL20_DWPH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:31 243585
wst04-VHDL20_DWPH_010800-2607010800-omedes--0.pdf 01-Jul-2026 08:30:41 245255
wst04-VHDL20_DWPH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:22 239440
wst04-VHDL20_DWPH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 239140
wst04-VHDL20_DWPH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:31 238995
wst04-VHDL20_DWPH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:40 239162
wst04-VHDL20_DWPH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 245086
wst04-VHDL20_DWSG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 343099
wst04-VHDL20_DWSG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 343921
wst04-VHDL20_DWSG_010800-2607010800-omedes--0.pdf 01-Jul-2026 10:49:02 339741
wst04-VHDL20_DWSG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 338127
wst04-VHDL20_DWSG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 338109
wst04-VHDL20_DWSG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 337922
wst04-VHDL20_DWSG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:18 338043
wst04-VHDL20_DWSG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 345513