Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Jul-2026 12:21:29 3860
FPDL13_DWMZ_150600 15-Jul-2026 13:40:45 4034
SXDL31_DWAV_141800 14-Jul-2026 17:55:04 9654
SXDL31_DWAV_150800 15-Jul-2026 08:31:31 14528
SXDL31_DWAV_151800 15-Jul-2026 17:13:19 10555
SXDL31_DWAV_160800 16-Jul-2026 07:35:41 8891
SXDL31_DWAV_LATEST 16-Jul-2026 07:35:41 8891
SXDL33_DWAV_140000 14-Jul-2026 10:16:40 11362
SXDL33_DWAV_150000 15-Jul-2026 09:28:39 11922
SXDL33_DWAV_LATEST 15-Jul-2026 09:28:39 11922
ber01-FWDL39_DWMS_141200-2607141200-dsw--0-ia5 14-Jul-2026 10:32:45 1859
ber01-FWDL39_DWMS_151200-2607151200-dsw--0-ia5 15-Jul-2026 10:38:55 1524
ber01-VHDL13_DWEG_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:15 3902
ber01-VHDL13_DWEG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 3236
ber01-VHDL13_DWEG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3684
ber01-VHDL13_DWEH_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:31 3348
ber01-VHDL13_DWEH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 2661
ber01-VHDL13_DWEH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3286
ber01-VHDL13_DWEI_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:51 3828
ber01-VHDL13_DWEI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:28:16 3063
ber01-VHDL13_DWEI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:28:16 3676
ber01-VHDL13_DWHG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3461
ber01-VHDL13_DWHG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 4261
ber01-VHDL13_DWHH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3314
ber01-VHDL13_DWHH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 3961
ber01-VHDL13_DWLG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3127
ber01-VHDL13_DWLG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3464
ber01-VHDL13_DWLH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 2764
ber01-VHDL13_DWLH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3569
ber01-VHDL13_DWLI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 2705
ber01-VHDL13_DWLI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3315
ber01-VHDL13_DWMO_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3150
ber01-VHDL13_DWMO_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3834
ber01-VHDL13_DWMO_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 08:59:56 3843
ber01-VHDL13_DWMP_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 3214
ber01-VHDL13_DWMP_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3670
ber01-VHDL13_DWOG_141700-2607141700-dsw--0-ia5 14-Jul-2026 18:00:02 4792
ber01-VHDL13_DWOG_150300-2607150300-dsw--0-ia5 15-Jul-2026 03:00:03 4058
ber01-VHDL13_DWOG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 4119
ber01-VHDL13_DWOG_151700-2607151700-dsw--0-ia5 15-Jul-2026 18:00:01 4427
ber01-VHDL13_DWOG_160300-2607160300-dsw--0-ia5 16-Jul-2026 03:00:10 4223
ber01-VHDL13_DWOG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 5466
ber01-VHDL13_DWON_140910-2607140910-dsw--0-ia5 14-Jul-2026 09:10:42 3811
ber01-VHDL13_DWON_141502-2607141502-dsw--0-ia5 14-Jul-2026 15:02:22 3653
ber01-VHDL13_DWON_142248-2607142248-dsw--0-ia5 14-Jul-2026 22:48:16 3711
ber01-VHDL13_DWON_150058-2607150058-dsw--0-ia5 15-Jul-2026 00:58:12 3711
ber01-VHDL13_DWON_150239-2607150239-dsw--0-ia5 15-Jul-2026 02:40:00 3711
ber01-VHDL13_DWON_150529-2607150529-dsw--0-ia5 15-Jul-2026 05:30:02 3958
ber01-VHDL13_DWON_150604-2607150604-dsw--0-ia5 15-Jul-2026 06:04:46 3946
ber01-VHDL13_DWON_151443-2607151443-dsw--0-ia5 15-Jul-2026 14:43:17 3903
ber01-VHDL13_DWON_151447-2607151447-dsw--0-ia5 15-Jul-2026 14:48:40 3900
ber01-VHDL13_DWON_151718-2607151718-dsw--0-ia5 15-Jul-2026 17:18:01 3276
ber01-VHDL13_DWON_160126-2607160126-dsw--0-ia5 16-Jul-2026 01:26:22 3839
ber01-VHDL13_DWON_160232-2607160232-dsw--0-ia5 16-Jul-2026 02:32:50 3839
ber01-VHDL13_DWON_160513-2607160513-dsw--0-ia5 16-Jul-2026 05:13:37 4045
ber01-VHDL13_DWON_160531-2607160531-dsw--0-ia5 16-Jul-2026 05:31:27 4356
ber01-VHDL13_DWON_160651-2607160651-dsw--0-ia5 16-Jul-2026 06:51:07 4356
ber01-VHDL13_DWON_160823-2607160823-dsw--0-ia5 16-Jul-2026 08:23:27 4316
ber01-VHDL13_DWPG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3230
ber01-VHDL13_DWPG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3692
ber01-VHDL13_DWPH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:00 3930
ber01-VHDL13_DWPH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3973
ber01-VHDL13_DWSG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 4069
ber01-VHDL13_DWSG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 3629
ber01-VHDL17_DWOG_141200-2607141200-dsw--0-ia5 14-Jul-2026 11:30:42 2704
ber01-VHDL17_DWOG_151200-2607151200-dsw--0-ia5 15-Jul-2026 11:22:41 2858
swis2-VHDL20_DWEG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2669
swis2-VHDL20_DWEG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1193
swis2-VHDL20_DWEG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 1449
swis2-VHDL20_DWEG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1820
swis2-VHDL20_DWEG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 2002
swis2-VHDL20_DWEG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1737
swis2-VHDL20_DWEG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1699
swis2-VHDL20_DWEG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 2006
swis2-VHDL20_DWEH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2318
swis2-VHDL20_DWEH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 953
swis2-VHDL20_DWEH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 949
swis2-VHDL20_DWEH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1377
swis2-VHDL20_DWEH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1613
swis2-VHDL20_DWEH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1371
swis2-VHDL20_DWEH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1358
swis2-VHDL20_DWEH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 1525
swis2-VHDL20_DWEI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2633
swis2-VHDL20_DWEI_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1334
swis2-VHDL20_DWEI_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:01:22 1434
swis2-VHDL20_DWEI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1805
swis2-VHDL20_DWEI_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1943
swis2-VHDL20_DWEI_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1753
swis2-VHDL20_DWEI_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:01:21 1716
swis2-VHDL20_DWEI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:07 2077
swis2-VHDL20_DWHG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1616
swis2-VHDL20_DWHG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:45:01 1188
swis2-VHDL20_DWHG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1406
swis2-VHDL20_DWHG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:45:32 1706
swis2-VHDL20_DWHG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:45:06 2553
swis2-VHDL20_DWHG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:45:40 2181
swis2-VHDL20_DWHG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:16 2178
swis2-VHDL20_DWHG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:45:13 2402
swis2-VHDL20_DWHH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1301
swis2-VHDL20_DWHH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:45:01 1042
swis2-VHDL20_DWHH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1319
swis2-VHDL20_DWHH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:45:32 1586
swis2-VHDL20_DWHH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:45:06 2441
swis2-VHDL20_DWHH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:45:40 2081
swis2-VHDL20_DWHH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:16 2120
swis2-VHDL20_DWHH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:45:03 2435
swis2-VHDL20_DWLG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1667
swis2-VHDL20_DWLG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1694
swis2-VHDL20_DWLG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1049
swis2-VHDL20_DWLG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1583
swis2-VHDL20_DWLG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1678
swis2-VHDL20_DWLG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1452
swis2-VHDL20_DWLG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1509
swis2-VHDL20_DWLG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1768
swis2-VHDL20_DWLH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1469
swis2-VHDL20_DWLH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1043
swis2-VHDL20_DWLH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1020
swis2-VHDL20_DWLH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1347
swis2-VHDL20_DWLH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1521
swis2-VHDL20_DWLH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1292
swis2-VHDL20_DWLH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1506
swis2-VHDL20_DWLH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1850
swis2-VHDL20_DWLI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1388
swis2-VHDL20_DWLI_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 875
swis2-VHDL20_DWLI_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1057
swis2-VHDL20_DWLI_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1384
swis2-VHDL20_DWLI_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1527
swis2-VHDL20_DWLI_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1347
swis2-VHDL20_DWLI_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1389
swis2-VHDL20_DWLI_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1650
swis2-VHDL20_DWMO_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1857
swis2-VHDL20_DWMO_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1390
swis2-VHDL20_DWMO_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:02 1390
swis2-VHDL20_DWMO_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1622
swis2-VHDL20_DWMO_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1620
swis2-VHDL20_DWMO_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1462
swis2-VHDL20_DWMO_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:02 1540
swis2-VHDL20_DWMO_160400_COR-2607160400-dsw--0-ia5 16-Jul-2026 05:48:32 3138
swis2-VHDL20_DWMO_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 2110
swis2-VHDL20_DWMO_160800_COR-2607160800-dsw--0-ia5 16-Jul-2026 08:59:56 3623
swis2-VHDL20_DWMP_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1697
swis2-VHDL20_DWMP_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1404
swis2-VHDL20_DWMP_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:02 1417
swis2-VHDL20_DWMP_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 1626
swis2-VHDL20_DWMP_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1757
swis2-VHDL20_DWMP_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:01 1513
swis2-VHDL20_DWMP_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:02 1590
swis2-VHDL20_DWMP_160400_COR-2607160400-dsw--0-ia5 16-Jul-2026 05:57:11 3275
swis2-VHDL20_DWMP_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 2168
swis2-VHDL20_DWPG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1569
swis2-VHDL20_DWPG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1272
swis2-VHDL20_DWPG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1442
swis2-VHDL20_DWPG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 1720
swis2-VHDL20_DWPG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1573
swis2-VHDL20_DWPG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1394
swis2-VHDL20_DWPG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1592
swis2-VHDL20_DWPG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 1932
swis2-VHDL20_DWPH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1642
swis2-VHDL20_DWPH_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:21 1416
swis2-VHDL20_DWPH_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1590
swis2-VHDL20_DWPH_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:23 2185
swis2-VHDL20_DWPH_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:31:11 1579
swis2-VHDL20_DWPH_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:21 1428
swis2-VHDL20_DWPH_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:12 1681
swis2-VHDL20_DWPH_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:25 2082
swis2-VHDL20_DWSG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2273
swis2-VHDL20_DWSG_150200-2607150200-dsw--0-ia5 15-Jul-2026 02:30:12 1596
swis2-VHDL20_DWSG_150400-2607150400-dsw--0-ia5 15-Jul-2026 05:00:16 1590
swis2-VHDL20_DWSG_150800-2607150800-dsw--0-ia5 15-Jul-2026 08:30:06 2230
swis2-VHDL20_DWSG_151800-2607151800-dsw--0-ia5 15-Jul-2026 18:30:07 1894
swis2-VHDL20_DWSG_160200-2607160200-dsw--0-ia5 16-Jul-2026 02:30:07 1481
swis2-VHDL20_DWSG_160400-2607160400-dsw--0-ia5 16-Jul-2026 05:00:18 1489
swis2-VHDL20_DWSG_160800-2607160800-dsw--0-ia5 16-Jul-2026 08:30:04 1860
wst04-VHDL20_DWEG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 243699
wst04-VHDL20_DWEG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 241737
wst04-VHDL20_DWEG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 241949
wst04-VHDL20_DWEG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:12 242977
wst04-VHDL20_DWEG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:14 244029
wst04-VHDL20_DWEG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 243367
wst04-VHDL20_DWEG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 242939
wst04-VHDL20_DWEG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:11 244541
wst04-VHDL20_DWEH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 238368
wst04-VHDL20_DWEH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 236141
wst04-VHDL20_DWEH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 236266
wst04-VHDL20_DWEH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:12 237354
wst04-VHDL20_DWEH_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:14 238224
wst04-VHDL20_DWEH_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 238190
wst04-VHDL20_DWEH_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 237651
wst04-VHDL20_DWEH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:11 238406
wst04-VHDL20_DWEI_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 351459
wst04-VHDL20_DWEI_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:17 349457
wst04-VHDL20_DWEI_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 349609
wst04-VHDL20_DWEI_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:16 350733
wst04-VHDL20_DWEI_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:22 351835
wst04-VHDL20_DWEI_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:11 351769
wst04-VHDL20_DWEI_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 351334
wst04-VHDL20_DWEI_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:18 352836
wst04-VHDL20_DWHG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:45:11 344865
wst04-VHDL20_DWHG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:45:42 343689
wst04-VHDL20_DWHG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 343492
wst04-VHDL20_DWHG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:45:32 346014
wst04-VHDL20_DWHG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:45:16 353599
wst04-VHDL20_DWHG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:45:40 352569
wst04-VHDL20_DWHG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:16 352553
wst04-VHDL20_DWHG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:45:13 353564
wst04-VHDL20_DWHH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:45:11 332131
wst04-VHDL20_DWHH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:45:42 331256
wst04-VHDL20_DWHH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 225518
wst04-VHDL20_DWHH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:45:32 333461
wst04-VHDL20_DWHH_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:45:16 344394
wst04-VHDL20_DWHH_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:45:40 343671
wst04-VHDL20_DWHH_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:16 236990
wst04-VHDL20_DWHH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:45:13 343595
wst04-VHDL20_DWLG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 343013
wst04-VHDL20_DWLG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 342401
wst04-VHDL20_DWLG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:42 341618
wst04-VHDL20_DWLG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:46 343302
wst04-VHDL20_DWLG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:31:28 349581
wst04-VHDL20_DWLG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 348328
wst04-VHDL20_DWLG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:42 348897
wst04-VHDL20_DWLG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:47 349952
wst04-VHDL20_DWLH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 345546
wst04-VHDL20_DWLH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:29 344781
wst04-VHDL20_DWLH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:42 344880
wst04-VHDL20_DWLH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:44 345568
wst04-VHDL20_DWLH_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:31:28 344377
wst04-VHDL20_DWLH_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 344109
wst04-VHDL20_DWLH_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:42 344489
wst04-VHDL20_DWLH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:47 346069
wst04-VHDL20_DWLI_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:35 347161
wst04-VHDL20_DWLI_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 346036
wst04-VHDL20_DWLI_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:42 346520
wst04-VHDL20_DWLI_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:44 391802
wst04-VHDL20_DWLI_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:31:28 345729
wst04-VHDL20_DWLI_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 344746
wst04-VHDL20_DWLI_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:42 345088
wst04-VHDL20_DWLI_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:47 389992
wst04-VHDL20_DWMO_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 361906
wst04-VHDL20_DWMO_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 471421
wst04-VHDL20_DWMO_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 471594
wst04-VHDL20_DWMO_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:16 471871
wst04-VHDL20_DWMO_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:22 363138
wst04-VHDL20_DWMO_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 474088
wst04-VHDL20_DWMO_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:18 474347
wst04-VHDL20_DWMO_160400_COR-2607160400-omedes-..> 16-Jul-2026 05:48:42 478862
wst04-VHDL20_DWMO_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:18 476001
wst04-VHDL20_DWMO_160800_COR-2607160800-omedes-..> 16-Jul-2026 09:00:11 478584
wst04-VHDL20_DWMP_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 481870
wst04-VHDL20_DWMP_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:17 590785
wst04-VHDL20_DWMP_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:16 590927
wst04-VHDL20_DWMP_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:23 481293
wst04-VHDL20_DWMP_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:22 473912
wst04-VHDL20_DWMP_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 580172
wst04-VHDL20_DWMP_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:18 581145
wst04-VHDL20_DWMP_160400_COR-2607160400-omedes-..> 16-Jul-2026 05:57:17 584904
wst04-VHDL20_DWMP_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:20 475662
wst04-VHDL20_DWPG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 347925
wst04-VHDL20_DWPG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 244586
wst04-VHDL20_DWPG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:32 347954
wst04-VHDL20_DWPG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:44 393842
wst04-VHDL20_DWPG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:31:28 353812
wst04-VHDL20_DWPG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:26 246452
wst04-VHDL20_DWPG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:32 353466
wst04-VHDL20_DWPG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:47 399174
wst04-VHDL20_DWPH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 247426
wst04-VHDL20_DWPH_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:21 246902
wst04-VHDL20_DWPH_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:32 247190
wst04-VHDL20_DWPH_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:44 247809
wst04-VHDL20_DWPH_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:31:28 247569
wst04-VHDL20_DWPH_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 247197
wst04-VHDL20_DWPH_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:32 247971
wst04-VHDL20_DWPH_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:47 248319
wst04-VHDL20_DWSG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 361799
wst04-VHDL20_DWSG_150200-2607150200-omedes--0.pdf 15-Jul-2026 02:30:12 361133
wst04-VHDL20_DWSG_150400-2607150400-omedes--0.pdf 15-Jul-2026 05:00:12 360276
wst04-VHDL20_DWSG_150800-2607150800-omedes--0.pdf 15-Jul-2026 08:30:16 361304
wst04-VHDL20_DWSG_151800-2607151800-omedes--0.pdf 15-Jul-2026 18:30:22 363749
wst04-VHDL20_DWSG_160200-2607160200-omedes--0.pdf 16-Jul-2026 02:30:21 363280
wst04-VHDL20_DWSG_160400-2607160400-omedes--0.pdf 16-Jul-2026 05:00:12 363118
wst04-VHDL20_DWSG_160800-2607160800-omedes--0.pdf 16-Jul-2026 08:30:11 363662