Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Apr-2026 12:32:14 3694
FPDL13_DWMZ_310600 31-Mar-2026 13:19:00 7710
SXDL31_DWAV_010800 01-Apr-2026 07:20:20 6839
SXDL31_DWAV_011800 01-Apr-2026 16:35:16 6418
SXDL31_DWAV_310800 31-Mar-2026 06:47:28 6837
SXDL31_DWAV_311800 31-Mar-2026 15:05:24 5636
SXDL31_DWAV_LATEST 01-Apr-2026 16:35:16 6418
SXDL33_DWAV_010000 01-Apr-2026 09:46:49 8420
SXDL33_DWAV_310000 31-Mar-2026 10:37:44 13358
SXDL33_DWAV_LATEST 01-Apr-2026 09:46:49 8420
ber01-FWDL39_DWMS_011230-2604011230-dsw--0-ia5 01-Apr-2026 12:06:16 1636
ber01-FWDL39_DWMS_311230-2603311230-dsw--0-ia5 31-Mar-2026 12:09:07 1615
ber01-VHDL13_DWEH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3181
ber01-VHDL13_DWEH_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:17 2976
ber01-VHDL13_DWEH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:17 2710
ber01-VHDL13_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2644
ber01-VHDL13_DWEH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:28:11 2858
ber01-VHDL13_DWEH_310400-2603310400-dsw--0-ia5 31-Mar-2026 04:58:12 2864
ber01-VHDL13_DWEH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:28:17 2957
ber01-VHDL13_DWEH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:28:18 3059
ber01-VHDL13_DWHG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 2670
ber01-VHDL13_DWHG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2662
ber01-VHDL13_DWHG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2664
ber01-VHDL13_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 3001
ber01-VHDL13_DWHG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 3053
ber01-VHDL13_DWHG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:16 3063
ber01-VHDL13_DWHG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:07 3169
ber01-VHDL13_DWHG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:07 2931
ber01-VHDL13_DWHH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 2315
ber01-VHDL13_DWHH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2318
ber01-VHDL13_DWHH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2815
ber01-VHDL13_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:06 2997
ber01-VHDL13_DWHH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2788
ber01-VHDL13_DWHH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:16 2768
ber01-VHDL13_DWHH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:07 2795
ber01-VHDL13_DWHH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:07 2587
ber01-VHDL13_DWLG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2574
ber01-VHDL13_DWLG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2699
ber01-VHDL13_DWLG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2649
ber01-VHDL13_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2403
ber01-VHDL13_DWLG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2754
ber01-VHDL13_DWLG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2896
ber01-VHDL13_DWLG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 3043
ber01-VHDL13_DWLG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:05 2704
ber01-VHDL13_DWLH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2366
ber01-VHDL13_DWLH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2401
ber01-VHDL13_DWLH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2660
ber01-VHDL13_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2332
ber01-VHDL13_DWLH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2657
ber01-VHDL13_DWLH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2554
ber01-VHDL13_DWLH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 2660
ber01-VHDL13_DWLH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:05 2161
ber01-VHDL13_DWLI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2503
ber01-VHDL13_DWLI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2537
ber01-VHDL13_DWLI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2496
ber01-VHDL13_DWLI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2264
ber01-VHDL13_DWLI_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2553
ber01-VHDL13_DWLI_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2475
ber01-VHDL13_DWLI_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 2783
ber01-VHDL13_DWLI_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:05 2645
ber01-VHDL13_DWMG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 3361
ber01-VHDL13_DWMG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 3201
ber01-VHDL13_DWMG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2821
ber01-VHDL13_DWMG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWMG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:01 3173
ber01-VHDL13_DWMG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 3132
ber01-VHDL13_DWMG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:07 3587
ber01-VHDL13_DWMG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:07 2930
ber01-VHDL13_DWMO_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2843
ber01-VHDL13_DWMO_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 2773
ber01-VHDL13_DWMO_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2332
ber01-VHDL13_DWMO_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2143
ber01-VHDL13_DWMO_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:01 2612
ber01-VHDL13_DWMO_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2745
ber01-VHDL13_DWMO_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:07 3095
ber01-VHDL13_DWMO_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:07 2402
ber01-VHDL13_DWMP_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 3266
ber01-VHDL13_DWMP_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:02 3251
ber01-VHDL13_DWMP_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:06 2998
ber01-VHDL13_DWMP_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2615
ber01-VHDL13_DWMP_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:01 3409
ber01-VHDL13_DWMP_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 3263
ber01-VHDL13_DWMP_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:07 3687
ber01-VHDL13_DWMP_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:07 2815
ber01-VHDL13_DWOG_010300-2604010300-dsw--0-ia5 01-Apr-2026 03:00:15 3398
ber01-VHDL13_DWOG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 3994
ber01-VHDL13_DWOG_011700-2604011700-dsw--0-ia5 01-Apr-2026 18:00:01 3033
ber01-VHDL13_DWOG_310300-2603310300-dsw--0-ia5 31-Mar-2026 03:00:01 4527
ber01-VHDL13_DWOG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 4389
ber01-VHDL13_DWOG_311700-2603311700-dsw--0-ia5 31-Mar-2026 18:00:01 3585
ber01-VHDL13_DWOH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3036
ber01-VHDL13_DWOH_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:11 2824
ber01-VHDL13_DWOH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:17 2716
ber01-VHDL13_DWOH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:16 2529
ber01-VHDL13_DWOH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:28:15 2800
ber01-VHDL13_DWOH_310400-2603310400-dsw--0-ia5 31-Mar-2026 04:58:12 2862
ber01-VHDL13_DWOH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:28:11 3059
ber01-VHDL13_DWOH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:28:18 2787
ber01-VHDL13_DWOI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:28:12 3081
ber01-VHDL13_DWOI_010400-2604010400-dsw--0-ia5 01-Apr-2026 04:58:17 2697
ber01-VHDL13_DWOI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:28:11 2702
ber01-VHDL13_DWOI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:28:12 2578
ber01-VHDL13_DWOI_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:28:11 2743
ber01-VHDL13_DWOI_310400-2603310400-dsw--0-ia5 31-Mar-2026 04:58:16 2880
ber01-VHDL13_DWOI_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:28:17 2993
ber01-VHDL13_DWOI_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:28:13 2859
ber01-VHDL13_DWON_010143-2604010143-dsw--0-ia5 01-Apr-2026 01:43:51 3368
ber01-VHDL13_DWON_010530-2604010530-dsw--0-ia5 01-Apr-2026 05:30:27 3613
ber01-VHDL13_DWON_010606-2604010606-dsw--0-ia5 01-Apr-2026 06:06:21 3714
ber01-VHDL13_DWON_010704-2604010704-dsw--0-ia5 01-Apr-2026 07:04:33 4163
ber01-VHDL13_DWON_010931-2604010931-dsw--0-ia5 01-Apr-2026 09:31:31 3920
ber01-VHDL13_DWON_011455-2604011455-dsw--0-ia5 01-Apr-2026 14:55:07 3631
ber01-VHDL13_DWON_011727-2604011727-dsw--0-ia5 01-Apr-2026 17:28:01 3214
ber01-VHDL13_DWON_012126-2604012126-dsw--0-ia5 01-Apr-2026 21:26:51 3172
ber01-VHDL13_DWON_310137-2603310137-dsw--0-ia5 31-Mar-2026 01:37:52 3663
ber01-VHDL13_DWON_310248-2603310248-dsw--0-ia5 31-Mar-2026 02:48:21 3647
ber01-VHDL13_DWON_310524-2603310524-dsw--0-ia5 31-Mar-2026 05:24:13 3968
ber01-VHDL13_DWON_310617-2603310617-dsw--0-ia5 31-Mar-2026 06:17:22 4136
ber01-VHDL13_DWON_310823-2603310823-dsw--0-ia5 31-Mar-2026 08:23:37 4136
ber01-VHDL13_DWON_310854-2603310854-dsw--0-ia5 31-Mar-2026 08:54:54 4136
ber01-VHDL13_DWON_311415-2603311415-dsw--0-ia5 31-Mar-2026 14:15:26 3220
ber01-VHDL13_DWON_311630-2603311630-dsw--0-ia5 31-Mar-2026 16:30:37 3220
ber01-VHDL13_DWPG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2252
ber01-VHDL13_DWPG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2714
ber01-VHDL13_DWPG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2743
ber01-VHDL13_DWPG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2475
ber01-VHDL13_DWPG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2397
ber01-VHDL13_DWPG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2473
ber01-VHDL13_DWPG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 2777
ber01-VHDL13_DWPG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:05 2335
ber01-VHDL13_DWPH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:05 2483
ber01-VHDL13_DWPH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:06 2801
ber01-VHDL13_DWPH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2685
ber01-VHDL13_DWPH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2384
ber01-VHDL13_DWPH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2700
ber01-VHDL13_DWPH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:02 2701
ber01-VHDL13_DWPH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 3081
ber01-VHDL13_DWPH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:05 2425
ber01-VHDL13_DWSG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:30:09 3121
ber01-VHDL13_DWSG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 3225
ber01-VHDL13_DWSG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:30:02 2890
ber01-VHDL13_DWSG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:30:02 2396
ber01-VHDL13_DWSG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:30:06 2799
ber01-VHDL13_DWSG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:16 3067
ber01-VHDL13_DWSG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:30:02 3134
ber01-VHDL13_DWSG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:30:01 2564
ber01-VHDL17_DWOG_011200-2604011200-dsw--0-ia5 01-Apr-2026 11:03:56 3234
ber01-VHDL17_DWOG_311200-2603311200-dsw--0-ia5 31-Mar-2026 11:58:43 4402
swis2-VHDL20_DWEG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3516
swis2-VHDL20_DWEG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3284
swis2-VHDL20_DWEG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3331
swis2-VHDL20_DWEG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2995
swis2-VHDL20_DWEG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3141
swis2-VHDL20_DWEG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:05 3285
swis2-VHDL20_DWEG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:04 4014
swis2-VHDL20_DWEG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3392
swis2-VHDL20_DWEH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3704
swis2-VHDL20_DWEH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3448
swis2-VHDL20_DWEH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3350
swis2-VHDL20_DWEH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3141
swis2-VHDL20_DWEH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3244
swis2-VHDL20_DWEH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:05 3297
swis2-VHDL20_DWEH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:04 3850
swis2-VHDL20_DWEH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3606
swis2-VHDL20_DWEI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3573
swis2-VHDL20_DWEI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3188
swis2-VHDL20_DWEI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3364
swis2-VHDL20_DWEI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3069
swis2-VHDL20_DWEI_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3099
swis2-VHDL20_DWEI_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:05 3332
swis2-VHDL20_DWEI_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:04 3992
swis2-VHDL20_DWEI_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3486
swis2-VHDL20_DWHG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2856
swis2-VHDL20_DWHG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 2845
swis2-VHDL20_DWHG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3282
swis2-VHDL20_DWHG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3184
swis2-VHDL20_DWHG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:11 3239
swis2-VHDL20_DWHG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:16 3246
swis2-VHDL20_DWHG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:04 3838
swis2-VHDL20_DWHG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3114
swis2-VHDL20_DWHH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2501
swis2-VHDL20_DWHH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:16 2504
swis2-VHDL20_DWHH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3431
swis2-VHDL20_DWHH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3183
swis2-VHDL20_DWHH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:11 2974
swis2-VHDL20_DWHH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:16 2954
swis2-VHDL20_DWHH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:04 3486
swis2-VHDL20_DWHH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 2773
swis2-VHDL20_DWLG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2997
swis2-VHDL20_DWLG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3069
swis2-VHDL20_DWLG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3249
swis2-VHDL20_DWLG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2773
swis2-VHDL20_DWLG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3178
swis2-VHDL20_DWLG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:12 3319
swis2-VHDL20_DWLG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3625
swis2-VHDL20_DWLG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3127
swis2-VHDL20_DWLH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2789
swis2-VHDL20_DWLH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2779
swis2-VHDL20_DWLH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3263
swis2-VHDL20_DWLH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2710
swis2-VHDL20_DWLH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3088
swis2-VHDL20_DWLH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:12 2977
swis2-VHDL20_DWLH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3251
swis2-VHDL20_DWLH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 2584
swis2-VHDL20_DWLI_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2938
swis2-VHDL20_DWLI_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 2910
swis2-VHDL20_DWLI_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3100
swis2-VHDL20_DWLI_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2637
swis2-VHDL20_DWLI_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 2977
swis2-VHDL20_DWLI_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:12 2910
swis2-VHDL20_DWLI_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3376
swis2-VHDL20_DWLI_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3080
swis2-VHDL20_DWMG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3875
swis2-VHDL20_DWMG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3637
swis2-VHDL20_DWMG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3488
swis2-VHDL20_DWMG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2818
swis2-VHDL20_DWMG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:11 3656
swis2-VHDL20_DWMG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:01 3618
swis2-VHDL20_DWMG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:06 4292
swis2-VHDL20_DWMG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3465
swis2-VHDL20_DWMO_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3329
swis2-VHDL20_DWMO_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3209
swis2-VHDL20_DWMO_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 2930
swis2-VHDL20_DWMO_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2579
swis2-VHDL20_DWMO_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3067
swis2-VHDL20_DWMO_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:01 3197
swis2-VHDL20_DWMO_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:06 3770
swis2-VHDL20_DWMO_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 2913
swis2-VHDL20_DWMP_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3781
swis2-VHDL20_DWMP_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3692
swis2-VHDL20_DWMP_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:06 3676
swis2-VHDL20_DWMP_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 3032
swis2-VHDL20_DWMP_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3895
swis2-VHDL20_DWMP_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:01 3751
swis2-VHDL20_DWMP_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:06 4403
swis2-VHDL20_DWMP_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3343
swis2-VHDL20_DWPG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2637
swis2-VHDL20_DWPG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3060
swis2-VHDL20_DWPG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3222
swis2-VHDL20_DWPG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2970
swis2-VHDL20_DWPG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 2829
swis2-VHDL20_DWPG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:12 2855
swis2-VHDL20_DWPG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3312
swis2-VHDL20_DWPG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 2870
swis2-VHDL20_DWPH_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 2867
swis2-VHDL20_DWPH_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:00:12 3149
swis2-VHDL20_DWPH_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3164
swis2-VHDL20_DWPH_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:01 2879
swis2-VHDL20_DWPH_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3131
swis2-VHDL20_DWPH_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:00:12 3085
swis2-VHDL20_DWPH_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3637
swis2-VHDL20_DWPH_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 2960
swis2-VHDL20_DWSG_010200-2604010200-dsw--0-ia5 01-Apr-2026 02:45:20 3661
swis2-VHDL20_DWSG_010400-2604010400-dsw--0-ia5 01-Apr-2026 05:15:06 3659
swis2-VHDL20_DWSG_010800-2604010800-dsw--0-ia5 01-Apr-2026 08:45:02 3469
swis2-VHDL20_DWSG_011300-2604011300-dsw--0-ia5 01-Apr-2026 13:45:02 3096
swis2-VHDL20_DWSG_011800-2604011800-dsw--0-ia5 01-Apr-2026 18:45:06 2828
swis2-VHDL20_DWSG_310200-2603310200-dsw--0-ia5 31-Mar-2026 02:45:10 3311
swis2-VHDL20_DWSG_310400-2603310400-dsw--0-ia5 31-Mar-2026 05:15:01 3627
swis2-VHDL20_DWSG_310800-2603310800-dsw--0-ia5 31-Mar-2026 08:45:00 3889
swis2-VHDL20_DWSG_311300-2603311300-dsw--0-ia5 31-Mar-2026 13:45:06 3422
swis2-VHDL20_DWSG_311800-2603311800-dsw--0-ia5 31-Mar-2026 18:45:02 3105
wst04-VHDL20_DWEG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 243461
wst04-VHDL20_DWEG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 242617
wst04-VHDL20_DWEG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 243351
wst04-VHDL20_DWEG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 238984
wst04-VHDL20_DWEG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:11 242140
wst04-VHDL20_DWEG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:11 242222
wst04-VHDL20_DWEG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:13 243445
wst04-VHDL20_DWEG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:12 242690
wst04-VHDL20_DWEH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 240618
wst04-VHDL20_DWEH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 239965
wst04-VHDL20_DWEH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 239578
wst04-VHDL20_DWEH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 235894
wst04-VHDL20_DWEH_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:11 241484
wst04-VHDL20_DWEH_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:11 240778
wst04-VHDL20_DWEH_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:17 241464
wst04-VHDL20_DWEH_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:12 239996
wst04-VHDL20_DWEI_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 343856
wst04-VHDL20_DWEI_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 343369
wst04-VHDL20_DWEI_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:16 343411
wst04-VHDL20_DWEI_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 337285
wst04-VHDL20_DWEI_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:16 341716
wst04-VHDL20_DWEI_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:17 341614
wst04-VHDL20_DWEI_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:17 342463
wst04-VHDL20_DWEI_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:12 343381
wst04-VHDL20_DWHG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 339593
wst04-VHDL20_DWHG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:12 339567
wst04-VHDL20_DWHG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 340706
wst04-VHDL20_DWHG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 334524
wst04-VHDL20_DWHG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:16 335928
wst04-VHDL20_DWHG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:12 335989
wst04-VHDL20_DWHG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:21 337735
wst04-VHDL20_DWHG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:22 339921
wst04-VHDL20_DWHH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 322171
wst04-VHDL20_DWHH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:12 322294
wst04-VHDL20_DWHH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 323395
wst04-VHDL20_DWHH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 320385
wst04-VHDL20_DWHH_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:16 325896
wst04-VHDL20_DWHH_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:12 325923
wst04-VHDL20_DWHH_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:21 327072
wst04-VHDL20_DWHH_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:22 323201
wst04-VHDL20_DWLG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 325455
wst04-VHDL20_DWLG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 325522
wst04-VHDL20_DWLG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 326458
wst04-VHDL20_DWLG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 327924
wst04-VHDL20_DWLG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:29 331107
wst04-VHDL20_DWLG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:40 331420
wst04-VHDL20_DWLG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:33 332080
wst04-VHDL20_DWLG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:26 325233
wst04-VHDL20_DWLH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 337473
wst04-VHDL20_DWLH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 338292
wst04-VHDL20_DWLH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 339093
wst04-VHDL20_DWLH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 328382
wst04-VHDL20_DWLH_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:24 334610
wst04-VHDL20_DWLH_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:40 334477
wst04-VHDL20_DWLH_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:33 334966
wst04-VHDL20_DWLH_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:22 337463
wst04-VHDL20_DWLI_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 329820
wst04-VHDL20_DWLI_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:42 329855
wst04-VHDL20_DWLI_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 330118
wst04-VHDL20_DWLI_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:26 329236
wst04-VHDL20_DWLI_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:29 328924
wst04-VHDL20_DWLI_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:40 328901
wst04-VHDL20_DWLI_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:33 329843
wst04-VHDL20_DWLI_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:22 329805
wst04-VHDL20_DWMG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 536688
wst04-VHDL20_DWMG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 536521
wst04-VHDL20_DWMG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 536763
wst04-VHDL20_DWMG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 541181
wst04-VHDL20_DWMG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:24 539574
wst04-VHDL20_DWMG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:17 539324
wst04-VHDL20_DWMG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:27 539958
wst04-VHDL20_DWMG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:16 536405
wst04-VHDL20_DWMO_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 441033
wst04-VHDL20_DWMO_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:16 441319
wst04-VHDL20_DWMO_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 440737
wst04-VHDL20_DWMO_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 439947
wst04-VHDL20_DWMO_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:18 446321
wst04-VHDL20_DWMO_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:17 446798
wst04-VHDL20_DWMO_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:21 447094
wst04-VHDL20_DWMO_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:16 440721
wst04-VHDL20_DWMP_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 533174
wst04-VHDL20_DWMP_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:22 534294
wst04-VHDL20_DWMP_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:22 534220
wst04-VHDL20_DWMP_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:16 540426
wst04-VHDL20_DWMP_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:18 533929
wst04-VHDL20_DWMP_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:21 534905
wst04-VHDL20_DWMP_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:27 536424
wst04-VHDL20_DWMP_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:16 533963
wst04-VHDL20_DWPG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:27 348727
wst04-VHDL20_DWPG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:32 349082
wst04-VHDL20_DWPG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 394157
wst04-VHDL20_DWPG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:26 332658
wst04-VHDL20_DWPG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:29 338497
wst04-VHDL20_DWPG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:32 338971
wst04-VHDL20_DWPG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:33 384545
wst04-VHDL20_DWPG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:26 349062
wst04-VHDL20_DWPH_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:23 241638
wst04-VHDL20_DWPH_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:00:32 242601
wst04-VHDL20_DWPH_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:33 287403
wst04-VHDL20_DWPH_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:22 282558
wst04-VHDL20_DWPH_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:24 241825
wst04-VHDL20_DWPH_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:00:32 242018
wst04-VHDL20_DWPH_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:27 288955
wst04-VHDL20_DWPH_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:22 286664
wst04-VHDL20_DWSG_010200-2604010200-omedes--0.pdf 01-Apr-2026 02:45:20 343158
wst04-VHDL20_DWSG_010400-2604010400-omedes--0.pdf 01-Apr-2026 05:15:12 342839
wst04-VHDL20_DWSG_010800-2604010800-omedes--0.pdf 01-Apr-2026 08:45:12 342499
wst04-VHDL20_DWSG_011300-2604011300-omedes--0.pdf 01-Apr-2026 13:45:12 341028
wst04-VHDL20_DWSG_011800-2604011800-omedes--0.pdf 01-Apr-2026 18:45:12 341744
wst04-VHDL20_DWSG_310200-2603310200-omedes--0.pdf 31-Mar-2026 02:45:11 344102
wst04-VHDL20_DWSG_310400-2603310400-omedes--0.pdf 31-Mar-2026 05:15:13 344611
wst04-VHDL20_DWSG_310800-2603310800-omedes--0.pdf 31-Mar-2026 08:45:13 344675
wst04-VHDL20_DWSG_311300-2603311300-omedes--0.pdf 31-Mar-2026 13:45:10 342913
wst04-VHDL20_DWSG_311800-2603311800-omedes--0.pdf 31-Mar-2026 18:45:12 342519