Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_270600 27-Aug-2026 13:50:54 4870
FPDL13_DWMZ_280600 28-Aug-2026 11:42:00 4667
SXDL31_DWAV_270800 27-Aug-2026 08:05:38 9831
SXDL31_DWAV_271800 27-Aug-2026 16:56:15 6236
SXDL31_DWAV_280800 28-Aug-2026 08:22:35 12247
SXDL31_DWAV_281800 28-Aug-2026 14:57:04 6105
SXDL31_DWAV_LATEST 28-Aug-2026 14:57:04 6105
SXDL33_DWAV_270000 27-Aug-2026 10:08:25 6599
SXDL33_DWAV_280000 28-Aug-2026 09:22:34 8056
SXDL33_DWAV_LATEST 28-Aug-2026 09:22:34 8056
ber01-FWDL39_DWMS_271200-2608271200-dsw--0-ia5 27-Aug-2026 10:26:18 2417
ber01-FWDL39_DWMS_281200-2608281200-dsw--0-ia5 28-Aug-2026 10:47:01 2361
ber01-VHDL13_DWEG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:28:19 3694
ber01-VHDL13_DWEG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:28:13 3129
ber01-VHDL13_DWEH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:28:19 4445
ber01-VHDL13_DWEH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:28:19 3182
ber01-VHDL13_DWEI_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:28:19 4081
ber01-VHDL13_DWEI_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:28:19 3065
ber01-VHDL13_DWHG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:15 3638
ber01-VHDL13_DWHG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 3381
ber01-VHDL13_DWHH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:15 3469
ber01-VHDL13_DWHH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 3337
ber01-VHDL13_DWLG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 3194
ber01-VHDL13_DWLG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 3444
ber01-VHDL13_DWLH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 3180
ber01-VHDL13_DWLH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 3293
ber01-VHDL13_DWLI_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 3058
ber01-VHDL13_DWLI_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 3208
ber01-VHDL13_DWMO_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 3861
ber01-VHDL13_DWMO_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 3619
ber01-VHDL13_DWMP_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 4090
ber01-VHDL13_DWMP_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 4471
ber01-VHDL13_DWOG_270300-2608270300-dsw--0-ia5 27-Aug-2026 03:00:12 4531
ber01-VHDL13_DWOG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:15 4514
ber01-VHDL13_DWOG_271700-2608271700-dsw--0-ia5 27-Aug-2026 18:00:04 4102
ber01-VHDL13_DWOG_280300-2608280300-dsw--0-ia5 28-Aug-2026 03:00:28 4502
ber01-VHDL13_DWOG_280800-2608280800-dsw--0-ia5 28-Aug-2026 13:27:23 4756
ber01-VHDL13_DWOG_281700-2608281700-dsw--0-ia5 28-Aug-2026 18:00:03 4867
ber01-VHDL13_DWOG_281700_COR-2608281700-dsw--0-ia5 28-Aug-2026 16:42:24 4871
ber01-VHDL13_DWON_270259-2608270259-dsw--0-ia5 27-Aug-2026 03:00:09 4181
ber01-VHDL13_DWON_270530-2608270530-dsw--0-ia5 27-Aug-2026 05:30:16 3705
ber01-VHDL13_DWON_270615-2608270615-dsw--0-ia5 27-Aug-2026 06:15:13 3752
ber01-VHDL13_DWON_270638-2608270638-dsw--0-ia5 27-Aug-2026 06:39:07 3866
ber01-VHDL13_DWON_271430-2608271430-dsw--0-ia5 27-Aug-2026 14:30:44 3817
ber01-VHDL13_DWON_271700-2608271700-dsw--0-ia5 27-Aug-2026 17:00:15 3230
ber01-VHDL13_DWON_272120-2608272120-dsw--0-ia5 27-Aug-2026 21:20:11 3388
ber01-VHDL13_DWON_280124-2608280124-dsw--0-ia5 28-Aug-2026 01:24:28 3373
ber01-VHDL13_DWON_280249-2608280249-dsw--0-ia5 28-Aug-2026 02:50:53 3373
ber01-VHDL13_DWON_280529-2608280529-dsw--0-ia5 28-Aug-2026 05:29:09 3273
ber01-VHDL13_DWON_280623-2608280623-dsw--0-ia5 28-Aug-2026 06:23:24 3522
ber01-VHDL13_DWON_280739-2608280739-dsw--0-ia5 28-Aug-2026 07:39:27 3522
ber01-VHDL13_DWON_281035-2608281035-dsw--0-ia5 28-Aug-2026 10:36:03 3423
ber01-VHDL13_DWON_281326-2608281326-dsw--0-ia5 28-Aug-2026 13:26:39 3423
ber01-VHDL13_DWON_281341-2608281341-dsw--0-ia5 28-Aug-2026 13:41:35 3384
ber01-VHDL13_DWON_281630-2608281630-dsw--0-ia5 28-Aug-2026 16:30:30 4099
ber01-VHDL13_DWON_281641-2608281641-dsw--0-ia5 28-Aug-2026 16:41:35 4098
ber01-VHDL13_DWPG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 2834
ber01-VHDL13_DWPG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 2892
ber01-VHDL13_DWPH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 3474
ber01-VHDL13_DWPH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 3408
ber01-VHDL13_DWSG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:15 4197
ber01-VHDL13_DWSG_270800_COR-2608270800-dsw--0-ia5 27-Aug-2026 17:53:54 4177
ber01-VHDL13_DWSG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 3549
ber01-VHDL17_DWOG_271200-2608271200-dsw--0-ia5 27-Aug-2026 11:45:12 2485
ber01-VHDL17_DWOG_281200-2608281200-dsw--0-ia5 28-Aug-2026 11:48:59 3153
swis2-VHDL20_DWEG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 1796
swis2-VHDL20_DWEG_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 1548
swis2-VHDL20_DWEG_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:01:24 1711
swis2-VHDL20_DWEG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 1993
swis2-VHDL20_DWEG_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2415
swis2-VHDL20_DWEG_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:12 1311
swis2-VHDL20_DWEG_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:01:18 1402
swis2-VHDL20_DWEG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 1846
swis2-VHDL20_DWEH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2731
swis2-VHDL20_DWEH_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 2452
swis2-VHDL20_DWEH_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:01:24 2473
swis2-VHDL20_DWEH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 2640
swis2-VHDL20_DWEH_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2607
swis2-VHDL20_DWEH_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:12 1220
swis2-VHDL20_DWEH_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:01:18 1345
swis2-VHDL20_DWEH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 1831
swis2-VHDL20_DWEI_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2409
swis2-VHDL20_DWEI_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 2171
swis2-VHDL20_DWEI_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:01:24 2214
swis2-VHDL20_DWEI_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 2407
swis2-VHDL20_DWEI_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2331
swis2-VHDL20_DWEI_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:12 1304
swis2-VHDL20_DWEI_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:01:18 1417
swis2-VHDL20_DWEI_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:09 1730
swis2-VHDL20_DWHG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:45:04 1929
swis2-VHDL20_DWHG_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:46:39 1642
swis2-VHDL20_DWHG_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:24 1639
swis2-VHDL20_DWHG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:45:31 2032
swis2-VHDL20_DWHG_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:45:09 2891
swis2-VHDL20_DWHG_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:47:31 1830
swis2-VHDL20_DWHG_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:18 1827
swis2-VHDL20_DWHG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:45:40 2138
swis2-VHDL20_DWHH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:45:04 2312
swis2-VHDL20_DWHH_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:46:39 1795
swis2-VHDL20_DWHH_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:24 1795
swis2-VHDL20_DWHH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:45:31 1948
swis2-VHDL20_DWHH_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:45:07 2305
swis2-VHDL20_DWHH_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:47:31 1717
swis2-VHDL20_DWHH_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:18 1717
swis2-VHDL20_DWHH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:45:40 2109
swis2-VHDL20_DWLG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1738
swis2-VHDL20_DWLG_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:23 1489
swis2-VHDL20_DWLG_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:12 1466
swis2-VHDL20_DWLG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:23 1832
swis2-VHDL20_DWLG_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:31:15 1780
swis2-VHDL20_DWLG_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:26 1533
swis2-VHDL20_DWLG_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:14 1488
swis2-VHDL20_DWLG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:25 1881
swis2-VHDL20_DWLH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1842
swis2-VHDL20_DWLH_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:23 1566
swis2-VHDL20_DWLH_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:12 1449
swis2-VHDL20_DWLH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:23 1821
swis2-VHDL20_DWLH_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:31:15 1863
swis2-VHDL20_DWLH_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:26 1530
swis2-VHDL20_DWLH_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:14 1426
swis2-VHDL20_DWLH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:25 1791
swis2-VHDL20_DWLI_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1625
swis2-VHDL20_DWLI_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:23 1546
swis2-VHDL20_DWLI_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:12 1470
swis2-VHDL20_DWLI_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:23 1616
swis2-VHDL20_DWLI_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:31:15 1719
swis2-VHDL20_DWLI_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:26 1507
swis2-VHDL20_DWLI_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:14 1471
swis2-VHDL20_DWLI_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:25 1757
swis2-VHDL20_DWMO_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2223
swis2-VHDL20_DWMO_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 1911
swis2-VHDL20_DWMO_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:04 1921
swis2-VHDL20_DWMO_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 2085
swis2-VHDL20_DWMO_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2294
swis2-VHDL20_DWMO_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:19 1823
swis2-VHDL20_DWMO_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:08 1824
swis2-VHDL20_DWMO_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 2037
swis2-VHDL20_DWMP_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2358
swis2-VHDL20_DWMP_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 2086
swis2-VHDL20_DWMP_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:04 2086
swis2-VHDL20_DWMP_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:08 2299
swis2-VHDL20_DWMP_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2654
swis2-VHDL20_DWMP_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:19 2157
swis2-VHDL20_DWMP_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:08 2157
swis2-VHDL20_DWMP_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 2761
swis2-VHDL20_DWPG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1528
swis2-VHDL20_DWPG_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:23 1420
swis2-VHDL20_DWPG_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:12 1374
swis2-VHDL20_DWPG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:23 1610
swis2-VHDL20_DWPG_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:31:15 1612
swis2-VHDL20_DWPG_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:26 1237
swis2-VHDL20_DWPG_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:14 1231
swis2-VHDL20_DWPG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:25 1625
swis2-VHDL20_DWPH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1701
swis2-VHDL20_DWPH_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:23 1329
swis2-VHDL20_DWPH_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:12 1640
swis2-VHDL20_DWPH_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:23 1940
swis2-VHDL20_DWPH_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:31:15 1907
swis2-VHDL20_DWPH_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:26 1592
swis2-VHDL20_DWPH_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:14 1631
swis2-VHDL20_DWPH_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:25 1929
swis2-VHDL20_DWSG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2049
swis2-VHDL20_DWSG_270200-2608270200-dsw--0-ia5 27-Aug-2026 02:30:14 1754
swis2-VHDL20_DWSG_270400-2608270400-dsw--0-ia5 27-Aug-2026 05:00:18 1757
swis2-VHDL20_DWSG_270800-2608270800-dsw--0-ia5 27-Aug-2026 08:30:15 1981
swis2-VHDL20_DWSG_270800_COR-2608270800-dsw--0-ia5 27-Aug-2026 17:53:54 2370
swis2-VHDL20_DWSG_271800-2608271800-dsw--0-ia5 27-Aug-2026 18:30:13 2366
swis2-VHDL20_DWSG_280200-2608280200-dsw--0-ia5 28-Aug-2026 02:30:12 1779
swis2-VHDL20_DWSG_280400-2608280400-dsw--0-ia5 28-Aug-2026 05:00:18 1671
swis2-VHDL20_DWSG_280800-2608280800-dsw--0-ia5 28-Aug-2026 08:30:11 1779
wst04-VHDL20_DWEG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 247490
wst04-VHDL20_DWEG_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:21 246590
wst04-VHDL20_DWEG_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:14 247084
wst04-VHDL20_DWEG_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:15 247903
wst04-VHDL20_DWEG_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:13 246550
wst04-VHDL20_DWEG_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:19 244935
wst04-VHDL20_DWEG_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:14 245247
wst04-VHDL20_DWEG_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:11 246431
wst04-VHDL20_DWEH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 246642
wst04-VHDL20_DWEH_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:21 246341
wst04-VHDL20_DWEH_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:14 246098
wst04-VHDL20_DWEH_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:15 246934
wst04-VHDL20_DWEH_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:28 243680
wst04-VHDL20_DWEH_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:19 241682
wst04-VHDL20_DWEH_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:14 242686
wst04-VHDL20_DWEH_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:11 243875
wst04-VHDL20_DWEI_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 357481
wst04-VHDL20_DWEI_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:21 356544
wst04-VHDL20_DWEI_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:14 356461
wst04-VHDL20_DWEI_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:23 356788
wst04-VHDL20_DWEI_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:28 354085
wst04-VHDL20_DWEI_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:24 352447
wst04-VHDL20_DWEI_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:14 353449
wst04-VHDL20_DWEI_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:11 354687
wst04-VHDL20_DWHG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:45:30 351892
wst04-VHDL20_DWHG_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:46:39 350158
wst04-VHDL20_DWHG_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:18 349948
wst04-VHDL20_DWHG_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:45:31 352804
wst04-VHDL20_DWHG_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:45:13 353508
wst04-VHDL20_DWHG_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:47:31 351572
wst04-VHDL20_DWHG_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:18 350918
wst04-VHDL20_DWHG_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:45:40 352732
wst04-VHDL20_DWHH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:45:30 342308
wst04-VHDL20_DWHH_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:46:39 341266
wst04-VHDL20_DWHH_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:18 235228
wst04-VHDL20_DWHH_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:45:31 342318
wst04-VHDL20_DWHH_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:45:13 346356
wst04-VHDL20_DWHH_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:47:31 343282
wst04-VHDL20_DWHH_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:18 237157
wst04-VHDL20_DWHH_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:45:40 344866
wst04-VHDL20_DWLG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 342959
wst04-VHDL20_DWLG_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 341716
wst04-VHDL20_DWLG_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:44 342386
wst04-VHDL20_DWLG_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:44 343631
wst04-VHDL20_DWLG_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:31:30 339027
wst04-VHDL20_DWLG_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:26 382993
wst04-VHDL20_DWLG_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:42 337615
wst04-VHDL20_DWLG_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:43 338855
wst04-VHDL20_DWLH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 345567
wst04-VHDL20_DWLH_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 344306
wst04-VHDL20_DWLH_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:44 344924
wst04-VHDL20_DWLH_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:44 346214
wst04-VHDL20_DWLH_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:31:30 342902
wst04-VHDL20_DWLH_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:26 386809
wst04-VHDL20_DWLH_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:42 341375
wst04-VHDL20_DWLH_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:43 342628
wst04-VHDL20_DWLI_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 338952
wst04-VHDL20_DWLI_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 337488
wst04-VHDL20_DWLI_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:44 338132
wst04-VHDL20_DWLI_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:44 383688
wst04-VHDL20_DWLI_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:31:30 339419
wst04-VHDL20_DWLI_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:26 383376
wst04-VHDL20_DWLI_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:42 337975
wst04-VHDL20_DWLI_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:43 383783
wst04-VHDL20_DWMO_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 354035
wst04-VHDL20_DWMO_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 457673
wst04-VHDL20_DWMO_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:18 457886
wst04-VHDL20_DWMO_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:23 457288
wst04-VHDL20_DWMO_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:28 351463
wst04-VHDL20_DWMO_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:19 454820
wst04-VHDL20_DWMO_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:18 454673
wst04-VHDL20_DWMO_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:25 454804
wst04-VHDL20_DWMP_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 470874
wst04-VHDL20_DWMP_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 574214
wst04-VHDL20_DWMP_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:18 574396
wst04-VHDL20_DWMP_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:23 471267
wst04-VHDL20_DWMP_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:28 464369
wst04-VHDL20_DWMP_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:24 572159
wst04-VHDL20_DWMP_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:18 572326
wst04-VHDL20_DWMP_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:25 465947
wst04-VHDL20_DWPG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 348676
wst04-VHDL20_DWPG_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:30 245159
wst04-VHDL20_DWPG_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:34 348319
wst04-VHDL20_DWPG_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:54 394039
wst04-VHDL20_DWPG_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:31:30 350647
wst04-VHDL20_DWPG_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:29 244514
wst04-VHDL20_DWPG_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:34 348918
wst04-VHDL20_DWPG_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:55 394911
wst04-VHDL20_DWPH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 245414
wst04-VHDL20_DWPH_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:23 244826
wst04-VHDL20_DWPH_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:34 245377
wst04-VHDL20_DWPH_270800-2608270800-omedes--0.pdf 27-Aug-2026 08:30:44 245780
wst04-VHDL20_DWPH_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:31:30 246535
wst04-VHDL20_DWPH_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:26 291225
wst04-VHDL20_DWPH_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:34 245777
wst04-VHDL20_DWPH_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:43 246148
wst04-VHDL20_DWSG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 354857
wst04-VHDL20_DWSG_270200-2608270200-omedes--0.pdf 27-Aug-2026 02:30:21 353925
wst04-VHDL20_DWSG_270400-2608270400-omedes--0.pdf 27-Aug-2026 05:00:14 354363
wst04-VHDL20_DWSG_270800-2608270800-omedes--0.pdf 27-Aug-2026 17:54:04 359372
wst04-VHDL20_DWSG_271800-2608271800-omedes--0.pdf 27-Aug-2026 18:30:13 359370
wst04-VHDL20_DWSG_280200-2608280200-omedes--0.pdf 28-Aug-2026 02:30:19 357667
wst04-VHDL20_DWSG_280400-2608280400-omedes--0.pdf 28-Aug-2026 05:00:14 357278
wst04-VHDL20_DWSG_280800-2608280800-omedes--0.pdf 28-Aug-2026 08:30:25 358825