Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_100600 10-Jun-2026 12:13:59 6596
FPDL13_DWMZ_110600 11-Jun-2026 11:58:23 3633
SXDL31_DWAV_100800 10-Jun-2026 06:46:53 15474
SXDL31_DWAV_101800 10-Jun-2026 16:02:54 5678
SXDL31_DWAV_110800 11-Jun-2026 06:59:40 15903
SXDL31_DWAV_111800 11-Jun-2026 16:30:55 6944
SXDL31_DWAV_LATEST 11-Jun-2026 16:30:55 6944
SXDL33_DWAV_100000 10-Jun-2026 10:18:45 8455
SXDL33_DWAV_110000 11-Jun-2026 10:04:10 9967
SXDL33_DWAV_LATEST 11-Jun-2026 10:04:10 9967
ber01-FWDL39_DWMS_101200-2606101200-dsw--0-ia5 10-Jun-2026 12:04:42 1478
ber01-FWDL39_DWMS_111200-2606111200-dsw--0-ia5 11-Jun-2026 12:54:56 1845
ber01-VHDL13_DWEG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:28:16 2880
ber01-VHDL13_DWEG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2795
ber01-VHDL13_DWEH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:28:22 2993
ber01-VHDL13_DWEH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2758
ber01-VHDL13_DWEI_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:28:16 2716
ber01-VHDL13_DWEI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2671
ber01-VHDL13_DWHG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:06 3415
ber01-VHDL13_DWHG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 3038
ber01-VHDL13_DWHH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:06 3305
ber01-VHDL13_DWHH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 2861
ber01-VHDL13_DWLG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2831
ber01-VHDL13_DWLG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2783
ber01-VHDL13_DWLH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2992
ber01-VHDL13_DWLH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2869
ber01-VHDL13_DWLI_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2801
ber01-VHDL13_DWLI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2638
ber01-VHDL13_DWMO_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2995
ber01-VHDL13_DWMO_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 3121
ber01-VHDL13_DWMP_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 3344
ber01-VHDL13_DWMP_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 3679
ber01-VHDL13_DWOG_100300-2606100300-dsw--0-ia5 10-Jun-2026 03:00:03 3081
ber01-VHDL13_DWOG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:47:46 3608
ber01-VHDL13_DWOG_101700-2606101700-dsw--0-ia5 10-Jun-2026 18:00:01 3050
ber01-VHDL13_DWOG_110300-2606110300-dsw--0-ia5 11-Jun-2026 03:00:09 3261
ber01-VHDL13_DWOG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 2935
ber01-VHDL13_DWOG_111700-2606111700-dsw--0-ia5 11-Jun-2026 18:00:02 3149
ber01-VHDL13_DWON_100025-2606100025-dsw--0-ia5 10-Jun-2026 00:26:03 2879
ber01-VHDL13_DWON_100121-2606100121-dsw--0-ia5 10-Jun-2026 01:21:50 2879
ber01-VHDL13_DWON_100239-2606100239-dsw--0-ia5 10-Jun-2026 02:39:15 2879
ber01-VHDL13_DWON_100528-2606100528-dsw--0-ia5 10-Jun-2026 05:28:16 3166
ber01-VHDL13_DWON_100847-2606100847-dsw--0-ia5 10-Jun-2026 08:47:16 3166
ber01-VHDL13_DWON_101448-2606101448-dsw--0-ia5 10-Jun-2026 14:48:16 3028
ber01-VHDL13_DWON_101752-2606101752-dsw--0-ia5 10-Jun-2026 17:52:38 2578
ber01-VHDL13_DWON_101755-2606101755-dsw--0-ia5 10-Jun-2026 17:55:12 2578
ber01-VHDL13_DWON_101908-2606101908-dsw--0-ia5 10-Jun-2026 19:08:22 2534
ber01-VHDL13_DWON_102231-2606102231-dsw--0-ia5 10-Jun-2026 22:31:41 2821
ber01-VHDL13_DWON_110023-2606110023-dsw--0-ia5 11-Jun-2026 00:23:06 2821
ber01-VHDL13_DWON_110133-2606110133-dsw--0-ia5 11-Jun-2026 01:33:16 2821
ber01-VHDL13_DWON_110508-2606110508-dsw--0-ia5 11-Jun-2026 05:08:11 3085
ber01-VHDL13_DWON_110600-2606110600-dsw--0-ia5 11-Jun-2026 06:00:56 3071
ber01-VHDL13_DWON_110807-2606110807-dsw--0-ia5 11-Jun-2026 08:07:16 3199
ber01-VHDL13_DWON_110907-2606110907-dsw--0-ia5 11-Jun-2026 09:07:50 3199
ber01-VHDL13_DWON_111431-2606111431-dsw--0-ia5 11-Jun-2026 14:31:44 3139
ber01-VHDL13_DWON_111434-2606111434-dsw--0-ia5 11-Jun-2026 14:34:52 3152
ber01-VHDL13_DWON_111638-2606111638-dsw--0-ia5 11-Jun-2026 16:38:42 2717
ber01-VHDL13_DWON_111939-2606111939-dsw--0-ia5 11-Jun-2026 19:39:17 2620
ber01-VHDL13_DWPG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2720
ber01-VHDL13_DWPG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2420
ber01-VHDL13_DWPH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 2929
ber01-VHDL13_DWPH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 3013
ber01-VHDL13_DWSG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:06 3022
ber01-VHDL13_DWSG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 3398
ber01-VHDL13_DWSG_110800_COR-2606110800-dsw--0-ia5 11-Jun-2026 11:55:32 3287
ber01-VHDL17_DWOG_101200-2606101200-dsw--0-ia5 10-Jun-2026 11:54:13 2948
ber01-VHDL17_DWOG_111200-2606111200-dsw--0-ia5 11-Jun-2026 10:58:30 3347
swis2-VHDL20_DWEG_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 1115
swis2-VHDL20_DWEG_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:01:21 1092
swis2-VHDL20_DWEG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 1288
swis2-VHDL20_DWEG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1418
swis2-VHDL20_DWEG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 986
swis2-VHDL20_DWEG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 983
swis2-VHDL20_DWEG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1169
swis2-VHDL20_DWEG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1218
swis2-VHDL20_DWEH_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 1100
swis2-VHDL20_DWEH_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:01:21 1073
swis2-VHDL20_DWEH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 1270
swis2-VHDL20_DWEH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1464
swis2-VHDL20_DWEH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1007
swis2-VHDL20_DWEH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 1004
swis2-VHDL20_DWEH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1145
swis2-VHDL20_DWEH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1205
swis2-VHDL20_DWEI_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 970
swis2-VHDL20_DWEI_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:01:21 961
swis2-VHDL20_DWEI_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 1067
swis2-VHDL20_DWEI_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1301
swis2-VHDL20_DWEI_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 810
swis2-VHDL20_DWEI_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 1010
swis2-VHDL20_DWEI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1179
swis2-VHDL20_DWEI_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1174
swis2-VHDL20_DWHG_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:45:07 1391
swis2-VHDL20_DWHG_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 1501
swis2-VHDL20_DWHG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:45:02 1872
swis2-VHDL20_DWHG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:45:02 1612
swis2-VHDL20_DWHG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:45:06 1553
swis2-VHDL20_DWHG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1550
swis2-VHDL20_DWHG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:45:01 1536
swis2-VHDL20_DWHG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:45:07 1711
swis2-VHDL20_DWHH_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:45:07 1404
swis2-VHDL20_DWHH_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 1495
swis2-VHDL20_DWHH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:45:02 1862
swis2-VHDL20_DWHH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:45:02 1622
swis2-VHDL20_DWHH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:45:06 1564
swis2-VHDL20_DWHH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1564
swis2-VHDL20_DWHH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:45:01 1545
swis2-VHDL20_DWHH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:45:07 1758
swis2-VHDL20_DWLG_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:22 1034
swis2-VHDL20_DWLG_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 984
swis2-VHDL20_DWLG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:21 1157
swis2-VHDL20_DWLG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1117
swis2-VHDL20_DWLG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 969
swis2-VHDL20_DWLG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1046
swis2-VHDL20_DWLG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1232
swis2-VHDL20_DWLG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 933
swis2-VHDL20_DWLH_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:22 983
swis2-VHDL20_DWLH_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 1026
swis2-VHDL20_DWLH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:21 1177
swis2-VHDL20_DWLH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1226
swis2-VHDL20_DWLH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 1205
swis2-VHDL20_DWLH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1083
swis2-VHDL20_DWLH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1258
swis2-VHDL20_DWLH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 959
swis2-VHDL20_DWLI_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:22 1028
swis2-VHDL20_DWLI_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 1021
swis2-VHDL20_DWLI_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:21 1122
swis2-VHDL20_DWLI_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1012
swis2-VHDL20_DWLI_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 963
swis2-VHDL20_DWLI_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 935
swis2-VHDL20_DWLI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1050
swis2-VHDL20_DWLI_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 848
swis2-VHDL20_DWMO_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 1290
swis2-VHDL20_DWMO_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:02 1301
swis2-VHDL20_DWMO_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 1553
swis2-VHDL20_DWMO_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1424
swis2-VHDL20_DWMO_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1622
swis2-VHDL20_DWMO_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:02 1411
swis2-VHDL20_DWMO_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 1532
swis2-VHDL20_DWMO_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1238
swis2-VHDL20_DWMP_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 1657
swis2-VHDL20_DWMP_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:02 1667
swis2-VHDL20_DWMP_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:02 1904
swis2-VHDL20_DWMP_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1887
swis2-VHDL20_DWMP_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1876
swis2-VHDL20_DWMP_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:02 1834
swis2-VHDL20_DWMP_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 2021
swis2-VHDL20_DWMP_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1552
swis2-VHDL20_DWPG_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:22 1062
swis2-VHDL20_DWPG_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 991
swis2-VHDL20_DWPG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:21 1163
swis2-VHDL20_DWPG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1088
swis2-VHDL20_DWPG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 980
swis2-VHDL20_DWPG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 969
swis2-VHDL20_DWPG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1085
swis2-VHDL20_DWPG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 865
swis2-VHDL20_DWPH_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:22 1033
swis2-VHDL20_DWPH_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:16 1007
swis2-VHDL20_DWPH_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:21 1241
swis2-VHDL20_DWPH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1147
swis2-VHDL20_DWPH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 1100
swis2-VHDL20_DWPH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1221
swis2-VHDL20_DWPH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1495
swis2-VHDL20_DWPH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 1216
swis2-VHDL20_DWSG_100200-2606100200-dsw--0-ia5 10-Jun-2026 02:30:02 1188
swis2-VHDL20_DWSG_100400-2606100400-dsw--0-ia5 10-Jun-2026 05:00:22 1315
swis2-VHDL20_DWSG_100800-2606100800-dsw--0-ia5 10-Jun-2026 08:30:06 1540
swis2-VHDL20_DWSG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1254
swis2-VHDL20_DWSG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1324
swis2-VHDL20_DWSG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1339
swis2-VHDL20_DWSG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1548
swis2-VHDL20_DWSG_110800_COR-2606110800-dsw--0-ia5 11-Jun-2026 11:55:32 1439
swis2-VHDL20_DWSG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1239
wst04-VHDL20_DWEG_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:12 239539
wst04-VHDL20_DWEG_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:12 239373
wst04-VHDL20_DWEG_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:13 240102
wst04-VHDL20_DWEG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:11 238121
wst04-VHDL20_DWEG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 237148
wst04-VHDL20_DWEG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 236984
wst04-VHDL20_DWEG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 237765
wst04-VHDL20_DWEG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 240787
wst04-VHDL20_DWEH_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:12 236113
wst04-VHDL20_DWEH_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:12 236173
wst04-VHDL20_DWEH_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:13 237005
wst04-VHDL20_DWEH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:11 235860
wst04-VHDL20_DWEH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 235144
wst04-VHDL20_DWEH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 234709
wst04-VHDL20_DWEH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 235550
wst04-VHDL20_DWEH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:15 237440
wst04-VHDL20_DWEI_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:12 342726
wst04-VHDL20_DWEI_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:12 342517
wst04-VHDL20_DWEI_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:13 342756
wst04-VHDL20_DWEI_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 337209
wst04-VHDL20_DWEI_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 335575
wst04-VHDL20_DWEI_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 335460
wst04-VHDL20_DWEI_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 335722
wst04-VHDL20_DWEI_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 342438
wst04-VHDL20_DWHG_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:45:11 341489
wst04-VHDL20_DWHG_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:16 341064
wst04-VHDL20_DWHG_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:45:12 342915
wst04-VHDL20_DWHG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:45:12 337511
wst04-VHDL20_DWHG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:45:19 335703
wst04-VHDL20_DWHG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 335492
wst04-VHDL20_DWHG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:45:11 337281
wst04-VHDL20_DWHG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:45:11 339105
wst04-VHDL20_DWHH_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:45:11 333443
wst04-VHDL20_DWHH_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:16 232517
wst04-VHDL20_DWHH_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:45:12 334622
wst04-VHDL20_DWHH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:45:12 328202
wst04-VHDL20_DWHH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:45:19 327411
wst04-VHDL20_DWHH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 229591
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wst04-VHDL20_DWHH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:45:11 323544
wst04-VHDL20_DWLG_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:22 330937
wst04-VHDL20_DWLG_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:42 330307
wst04-VHDL20_DWLG_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:42 330734
wst04-VHDL20_DWLG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 330600
wst04-VHDL20_DWLG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 330611
wst04-VHDL20_DWLG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 330322
wst04-VHDL20_DWLG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 330576
wst04-VHDL20_DWLG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 337876
wst04-VHDL20_DWLH_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:27 332181
wst04-VHDL20_DWLH_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:42 332538
wst04-VHDL20_DWLH_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:42 333142
wst04-VHDL20_DWLH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 330035
wst04-VHDL20_DWLH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 329834
wst04-VHDL20_DWLH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 329336
wst04-VHDL20_DWLH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 329999
wst04-VHDL20_DWLH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:26 333901
wst04-VHDL20_DWLI_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:22 333272
wst04-VHDL20_DWLI_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:42 332651
wst04-VHDL20_DWLI_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:46 377500
wst04-VHDL20_DWLI_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 325415
wst04-VHDL20_DWLI_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 325564
wst04-VHDL20_DWLI_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 325106
wst04-VHDL20_DWLI_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 369943
wst04-VHDL20_DWLI_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 338395
wst04-VHDL20_DWMO_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:18 453645
wst04-VHDL20_DWMO_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:16 453542
wst04-VHDL20_DWMO_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:21 453553
wst04-VHDL20_DWMO_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 345506
wst04-VHDL20_DWMO_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 450079
wst04-VHDL20_DWMO_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 449734
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wst04-VHDL20_DWMO_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 349968
wst04-VHDL20_DWMP_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:18 576742
wst04-VHDL20_DWMP_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:22 576772
wst04-VHDL20_DWMP_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:21 471203
wst04-VHDL20_DWMP_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 469183
wst04-VHDL20_DWMP_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 572214
wst04-VHDL20_DWMP_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 572710
wst04-VHDL20_DWMP_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:24 469270
wst04-VHDL20_DWMP_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 470405
wst04-VHDL20_DWPG_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:22 237459
wst04-VHDL20_DWPG_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:30 334258
wst04-VHDL20_DWPG_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:42 379226
wst04-VHDL20_DWPG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 337932
wst04-VHDL20_DWPG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 238694
wst04-VHDL20_DWPG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:32 337555
wst04-VHDL20_DWPG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 382338
wst04-VHDL20_DWPG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 335254
wst04-VHDL20_DWPH_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:22 242462
wst04-VHDL20_DWPH_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:30 242561
wst04-VHDL20_DWPH_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:42 243417
wst04-VHDL20_DWPH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 240394
wst04-VHDL20_DWPH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 240680
wst04-VHDL20_DWPH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:32 240326
wst04-VHDL20_DWPH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 240595
wst04-VHDL20_DWPH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 239165
wst04-VHDL20_DWSG_100200-2606100200-omedes--0.pdf 10-Jun-2026 02:30:12 349322
wst04-VHDL20_DWSG_100400-2606100400-omedes--0.pdf 10-Jun-2026 05:00:12 349687
wst04-VHDL20_DWSG_100800-2606100800-omedes--0.pdf 10-Jun-2026 08:30:21 350601
wst04-VHDL20_DWSG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 347715
wst04-VHDL20_DWSG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 347675
wst04-VHDL20_DWSG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 347737
wst04-VHDL20_DWSG_110800-2606110800-omedes--0.pdf 11-Jun-2026 11:55:36 347764
wst04-VHDL20_DWSG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:15 346524