Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Apr-2026 14:13:58 13143
FPDL13_DWMZ_040600 04-Apr-2026 12:24:25 3300
SXDL31_DWAV_030800 03-Apr-2026 07:25:59 9453
SXDL31_DWAV_031800 03-Apr-2026 17:02:05 9995
SXDL31_DWAV_040800 04-Apr-2026 07:26:19 8163
SXDL31_DWAV_041800 04-Apr-2026 17:14:41 10217
SXDL31_DWAV_LATEST 04-Apr-2026 17:14:41 10217
SXDL33_DWAV_030000 03-Apr-2026 09:33:57 7188
SXDL33_DWAV_040000 04-Apr-2026 09:23:40 8864
SXDL33_DWAV_LATEST 04-Apr-2026 09:23:40 8864
ber01-FWDL39_DWMS_031230-2604031230-dsw--0-ia5 03-Apr-2026 11:17:11 1127
ber01-FWDL39_DWMS_041230-2604041230-dsw--0-ia5 04-Apr-2026 11:07:27 1186
ber01-VHDL13_DWEH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:11 2874
ber01-VHDL13_DWEH_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:13 2844
ber01-VHDL13_DWEH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:11 2947
ber01-VHDL13_DWEH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:16 2567
ber01-VHDL13_DWEH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:11 2826
ber01-VHDL13_DWEH_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:11 2702
ber01-VHDL13_DWEH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:18 3288
ber01-VHDL13_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2752
ber01-VHDL13_DWHG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:09 2900
ber01-VHDL13_DWHG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2927
ber01-VHDL13_DWHG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 3436
ber01-VHDL13_DWHG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:07 3177
ber01-VHDL13_DWHG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 3330
ber01-VHDL13_DWHG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3330
ber01-VHDL13_DWHG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:08 3448
ber01-VHDL13_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 3209
ber01-VHDL13_DWHH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:09 2689
ber01-VHDL13_DWHH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2630
ber01-VHDL13_DWHH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2987
ber01-VHDL13_DWHH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:07 2741
ber01-VHDL13_DWHH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2980
ber01-VHDL13_DWHH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 2980
ber01-VHDL13_DWHH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:08 3178
ber01-VHDL13_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2666
ber01-VHDL13_DWLG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 3212
ber01-VHDL13_DWLG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 3387
ber01-VHDL13_DWLG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 3356
ber01-VHDL13_DWLG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 3001
ber01-VHDL13_DWLG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2699
ber01-VHDL13_DWLG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2820
ber01-VHDL13_DWLG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2837
ber01-VHDL13_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2715
ber01-VHDL13_DWLH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 3335
ber01-VHDL13_DWLH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 3352
ber01-VHDL13_DWLH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 3244
ber01-VHDL13_DWLH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2933
ber01-VHDL13_DWLH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2897
ber01-VHDL13_DWLH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2783
ber01-VHDL13_DWLH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2768
ber01-VHDL13_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2772
ber01-VHDL13_DWLI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2625
ber01-VHDL13_DWLI_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2772
ber01-VHDL13_DWLI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2854
ber01-VHDL13_DWLI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2627
ber01-VHDL13_DWLI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2494
ber01-VHDL13_DWLI_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2222
ber01-VHDL13_DWLI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2222
ber01-VHDL13_DWLI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2328
ber01-VHDL13_DWMG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2592
ber01-VHDL13_DWMG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2373
ber01-VHDL13_DWMG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2475
ber01-VHDL13_DWMG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2438
ber01-VHDL13_DWMG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2612
ber01-VHDL13_DWMG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2636
ber01-VHDL13_DWMG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2966
ber01-VHDL13_DWMG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2878
ber01-VHDL13_DWMO_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2473
ber01-VHDL13_DWMO_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2391
ber01-VHDL13_DWMO_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2476
ber01-VHDL13_DWMO_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2445
ber01-VHDL13_DWMO_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2680
ber01-VHDL13_DWMO_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2608
ber01-VHDL13_DWMO_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2735
ber01-VHDL13_DWMO_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2753
ber01-VHDL13_DWMP_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2585
ber01-VHDL13_DWMP_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2375
ber01-VHDL13_DWMP_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2572
ber01-VHDL13_DWMP_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2459
ber01-VHDL13_DWMP_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2541
ber01-VHDL13_DWMP_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2530
ber01-VHDL13_DWMP_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2874
ber01-VHDL13_DWMP_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2715
ber01-VHDL13_DWOG_030300-2604030300-dsw--0-ia5 03-Apr-2026 03:00:08 4232
ber01-VHDL13_DWOG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 4076
ber01-VHDL13_DWOG_031700-2604031700-dsw--0-ia5 03-Apr-2026 18:00:06 4199
ber01-VHDL13_DWOG_040300-2604040300-dsw--0-ia5 04-Apr-2026 03:00:01 4673
ber01-VHDL13_DWOG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 4117
ber01-VHDL13_DWOG_041700-2604041700-dsw--0-ia5 04-Apr-2026 18:00:02 4843
ber01-VHDL13_DWOH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:11 2525
ber01-VHDL13_DWOH_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:17 2574
ber01-VHDL13_DWOH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:17 2672
ber01-VHDL13_DWOH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:12 2436
ber01-VHDL13_DWOH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:11 2798
ber01-VHDL13_DWOH_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:17 2856
ber01-VHDL13_DWOH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:12 2890
ber01-VHDL13_DWOH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2537
ber01-VHDL13_DWOI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:28:17 2603
ber01-VHDL13_DWOI_030400-2604030400-dsw--0-ia5 03-Apr-2026 04:58:17 2541
ber01-VHDL13_DWOI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:28:17 2624
ber01-VHDL13_DWOI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:12 2383
ber01-VHDL13_DWOI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:17 2558
ber01-VHDL13_DWOI_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:17 2501
ber01-VHDL13_DWOI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:18 2814
ber01-VHDL13_DWOI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:10 2471
ber01-VHDL13_DWON_030232-2604030232-dsw--0-ia5 03-Apr-2026 02:32:52 3718
ber01-VHDL13_DWON_030525-2604030525-dsw--0-ia5 03-Apr-2026 05:25:12 4262
ber01-VHDL13_DWON_030615-2604030615-dsw--0-ia5 03-Apr-2026 06:15:22 4262
ber01-VHDL13_DWON_030822-2604030822-dsw--0-ia5 03-Apr-2026 08:23:02 4262
ber01-VHDL13_DWON_030858-2604030858-dsw--0-ia5 03-Apr-2026 08:58:31 4262
ber01-VHDL13_DWON_031459-2604031459-dsw--0-ia5 03-Apr-2026 14:59:22 3579
ber01-VHDL13_DWON_031742-2604031742-dsw--0-ia5 03-Apr-2026 17:43:03 3890
ber01-VHDL13_DWON_031945-2604031945-dsw--0-ia5 03-Apr-2026 19:45:42 3938
ber01-VHDL13_DWON_040119-2604040119-dsw--0-ia5 04-Apr-2026 01:19:51 3946
ber01-VHDL13_DWON_040243-2604040243-dsw--0-ia5 04-Apr-2026 02:44:01 4362
ber01-VHDL13_DWON_040529-2604040529-dsw--0-ia5 04-Apr-2026 05:29:32 4200
ber01-VHDL13_DWON_040618-2604040618-dsw--0-ia5 04-Apr-2026 06:18:57 4561
ber01-VHDL13_DWON_040739-2604040739-dsw--0-ia5 04-Apr-2026 07:39:01 4461
ber01-VHDL13_DWON_041059-2604041059-dsw--0-ia5 04-Apr-2026 11:00:01 4461
ber01-VHDL13_DWON_041458-2604041458-dsw--0-ia5 04-Apr-2026 14:59:04 3826
ber01-VHDL13_DWON_041749-2604041749-dsw--0-ia5 04-Apr-2026 17:49:43 4156
ber01-VHDL13_DWPG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2293
ber01-VHDL13_DWPG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2403
ber01-VHDL13_DWPG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2583
ber01-VHDL13_DWPG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2332
ber01-VHDL13_DWPG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2446
ber01-VHDL13_DWPG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2531
ber01-VHDL13_DWPG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2532
ber01-VHDL13_DWPG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2390
ber01-VHDL13_DWPH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2433
ber01-VHDL13_DWPH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:01 2728
ber01-VHDL13_DWPH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:11 2988
ber01-VHDL13_DWPH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2710
ber01-VHDL13_DWPH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2694
ber01-VHDL13_DWPH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2632
ber01-VHDL13_DWPH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2632
ber01-VHDL13_DWPH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2711
ber01-VHDL13_DWSG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:30:03 2662
ber01-VHDL13_DWSG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2786
ber01-VHDL13_DWSG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:30:10 2588
ber01-VHDL13_DWSG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2572
ber01-VHDL13_DWSG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2862
ber01-VHDL13_DWSG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:17 2861
ber01-VHDL13_DWSG_040400_COR-2604040400-dsw--0-ia5 04-Apr-2026 05:02:07 2822
ber01-VHDL13_DWSG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 3499
ber01-VHDL13_DWSG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2622
ber01-VHDL17_DWOG_031200-2604031200-dsw--0-ia5 03-Apr-2026 10:48:57 2479
ber01-VHDL17_DWOG_041200-2604041200-dsw--0-ia5 04-Apr-2026 10:47:17 2957
swis2-VHDL20_DWEG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 2802
swis2-VHDL20_DWEG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 2894
swis2-VHDL20_DWEG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3147
swis2-VHDL20_DWEG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2762
swis2-VHDL20_DWEG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3077
swis2-VHDL20_DWEG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:03 3173
swis2-VHDL20_DWEG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:10 3569
swis2-VHDL20_DWEG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2860
swis2-VHDL20_DWEH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 3196
swis2-VHDL20_DWEH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 3176
swis2-VHDL20_DWEH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3447
swis2-VHDL20_DWEH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2921
swis2-VHDL20_DWEH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3150
swis2-VHDL20_DWEH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:07 3031
swis2-VHDL20_DWEH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3992
swis2-VHDL20_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 3103
swis2-VHDL20_DWEI_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:23 2896
swis2-VHDL20_DWEI_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:15:06 2892
swis2-VHDL20_DWEI_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3146
swis2-VHDL20_DWEI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2734
swis2-VHDL20_DWEI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 2853
swis2-VHDL20_DWEI_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:07 2849
swis2-VHDL20_DWEI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3540
swis2-VHDL20_DWEI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2819
swis2-VHDL20_DWHG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 3086
swis2-VHDL20_DWHG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 3110
swis2-VHDL20_DWHG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3964
swis2-VHDL20_DWHG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:06 3360
swis2-VHDL20_DWHG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3516
swis2-VHDL20_DWHG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3513
swis2-VHDL20_DWHG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3981
swis2-VHDL20_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 3392
swis2-VHDL20_DWHH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 2875
swis2-VHDL20_DWHH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:17 2816
swis2-VHDL20_DWHH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3527
swis2-VHDL20_DWHH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:06 2927
swis2-VHDL20_DWHH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3166
swis2-VHDL20_DWHH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3166
swis2-VHDL20_DWHH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3720
swis2-VHDL20_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 2852
swis2-VHDL20_DWLG_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 3625
swis2-VHDL20_DWLG_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:11 3728
swis2-VHDL20_DWLG_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3843
swis2-VHDL20_DWLG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 3342
swis2-VHDL20_DWLG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3040
swis2-VHDL20_DWLG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3162
swis2-VHDL20_DWLG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3328
swis2-VHDL20_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3057
swis2-VHDL20_DWLH_030200-2604030200-dsw--0-ia5 03-Apr-2026 02:45:01 3756
swis2-VHDL20_DWLH_030400-2604030400-dsw--0-ia5 03-Apr-2026 05:00:11 3700
swis2-VHDL20_DWLH_030800-2604030800-dsw--0-ia5 03-Apr-2026 08:45:12 3742
swis2-VHDL20_DWLH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 3281
swis2-VHDL20_DWLH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3245
swis2-VHDL20_DWLH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3132
swis2-VHDL20_DWLH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3270
swis2-VHDL20_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3121
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wst04-VHDL20_DWEG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:12 242711
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wst04-VHDL20_DWEG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 240830
wst04-VHDL20_DWEG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 240323
wst04-VHDL20_DWEG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 242157
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wst04-VHDL20_DWEH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 238945
wst04-VHDL20_DWEH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 239489
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wst04-VHDL20_DWEH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 239257
wst04-VHDL20_DWEH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 238707
wst04-VHDL20_DWEH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 240177
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wst04-VHDL20_DWEI_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 343514
wst04-VHDL20_DWEI_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:21 344030
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wst04-VHDL20_DWEI_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 344086
wst04-VHDL20_DWEI_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 344003
wst04-VHDL20_DWEI_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:20 345516
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wst04-VHDL20_DWHG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:17 339970
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wst04-VHDL20_DWHG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 334613
wst04-VHDL20_DWHG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:11 334736
wst04-VHDL20_DWHG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 336005
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wst04-VHDL20_DWHH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:11 325859
wst04-VHDL20_DWHH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 326203
wst04-VHDL20_DWHH_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:22 321824
wst04-VHDL20_DWHH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 321907
wst04-VHDL20_DWHH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:11 321942
wst04-VHDL20_DWHH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 322819
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wst04-VHDL20_DWLG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 329542
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wst04-VHDL20_DWLG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 324308
wst04-VHDL20_DWLG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:41 324870
wst04-VHDL20_DWLG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 325382
wst04-VHDL20_DWLG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 334708
wst04-VHDL20_DWLH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:36 328348
wst04-VHDL20_DWLH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:41 328563
wst04-VHDL20_DWLH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 328751
wst04-VHDL20_DWLH_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:22 321686
wst04-VHDL20_DWLH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 321772
wst04-VHDL20_DWLH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:41 322143
wst04-VHDL20_DWLH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 322731
wst04-VHDL20_DWLH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 331780
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wst04-VHDL20_DWLI_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:41 330379
wst04-VHDL20_DWLI_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 330905
wst04-VHDL20_DWLI_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:26 330654
wst04-VHDL20_DWLI_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 330804
wst04-VHDL20_DWLI_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:41 330634
wst04-VHDL20_DWLI_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 331022
wst04-VHDL20_DWLI_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 333437
wst04-VHDL20_DWMG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 546743
wst04-VHDL20_DWMG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:22 546370
wst04-VHDL20_DWMG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:17 546484
wst04-VHDL20_DWMG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:16 549085
wst04-VHDL20_DWMG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 549677
wst04-VHDL20_DWMG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 549620
wst04-VHDL20_DWMG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 550261
wst04-VHDL20_DWMG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 552152
wst04-VHDL20_DWMO_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 449843
wst04-VHDL20_DWMO_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 450215
wst04-VHDL20_DWMO_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:12 450025
wst04-VHDL20_DWMO_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:16 449573
wst04-VHDL20_DWMO_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 450229
wst04-VHDL20_DWMO_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 450659
wst04-VHDL20_DWMO_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 450635
wst04-VHDL20_DWMO_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 450179
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wst04-VHDL20_DWMP_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:16 537866
wst04-VHDL20_DWMP_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 537961
wst04-VHDL20_DWMP_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:16 551704
wst04-VHDL20_DWMP_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 551600
wst04-VHDL20_DWMP_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 552579
wst04-VHDL20_DWMP_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 552874
wst04-VHDL20_DWMP_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 549804
wst04-VHDL20_DWPG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:36 339165
wst04-VHDL20_DWPG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:31 339116
wst04-VHDL20_DWPG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 384665
wst04-VHDL20_DWPG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:26 337909
wst04-VHDL20_DWPG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 337910
wst04-VHDL20_DWPG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:31 338377
wst04-VHDL20_DWPG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:32 383382
wst04-VHDL20_DWPG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 336141
wst04-VHDL20_DWPH_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 238082
wst04-VHDL20_DWPH_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:00:31 237986
wst04-VHDL20_DWPH_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 284309
wst04-VHDL20_DWPH_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:22 282292
wst04-VHDL20_DWPH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 237247
wst04-VHDL20_DWPH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:31 236822
wst04-VHDL20_DWPH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 281816
wst04-VHDL20_DWPH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 280042
wst04-VHDL20_DWSG_030200-2604030200-omedes--0.pdf 03-Apr-2026 02:45:23 348684
wst04-VHDL20_DWSG_030400-2604030400-omedes--0.pdf 03-Apr-2026 05:15:12 347644
wst04-VHDL20_DWSG_030800-2604030800-omedes--0.pdf 03-Apr-2026 08:45:32 347501
wst04-VHDL20_DWSG_031300-2604031300-omedes--0.pdf 03-Apr-2026 13:45:12 348594
wst04-VHDL20_DWSG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:12 347774
wst04-VHDL20_DWSG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 349985
wst04-VHDL20_DWSG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 350379
wst04-VHDL20_DWSG_040400_COR-2604040400-omedes-..> 04-Apr-2026 05:02:11 350379
wst04-VHDL20_DWSG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:22 350971
wst04-VHDL20_DWSG_041300-2604041300-omedes--0.pdf 04-Apr-2026 13:45:12 348402
wst04-VHDL20_DWSG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:12 347019