Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_290600 29-Oct-2024 11:53 2991
FPDL13_DWMZ_300600 30-Oct-2024 13:20 6795
SXDL31_DWAV_281800 28-Oct-2024 17:38 6439
SXDL31_DWAV_290800 29-Oct-2024 07:45 13376
SXDL31_DWAV_291800 29-Oct-2024 18:22 5772
SXDL31_DWAV_300800 30-Oct-2024 07:39 8746
SXDL31_DWAV_LATEST 30-Oct-2024 07:39 8746
SXDL33_DWAV_290000 29-Oct-2024 10:26 6854
SXDL33_DWAV_300000 30-Oct-2024 09:50 6017
SXDL33_DWAV_LATEST 30-Oct-2024 09:50 6017
ber01-FWDL39_DWMS_291230-2410291230-dsw--0-ia5 29-Oct-2024 12:25 1018
ber01-FWDL39_DWMS_301230-2410301230-dsw--0-ia5 30-Oct-2024 11:50 1041
ber01-VHDL13_DWEH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:28 2370
ber01-VHDL13_DWEH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:28 2536
ber01-VHDL13_DWEH_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:58 2365
ber01-VHDL13_DWEH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:28 2390
ber01-VHDL13_DWEH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:28 2555
ber01-VHDL13_DWEH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:28 2724
ber01-VHDL13_DWEH_300400-2410300400-dsw--0-ia5 30-Oct-2024 05:58 2618
ber01-VHDL13_DWEH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:28 2631
ber01-VHDL13_DWHG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 2201
ber01-VHDL13_DWHG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2564
ber01-VHDL13_DWHG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2564
ber01-VHDL13_DWHG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2458
ber01-VHDL13_DWHG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 2301
ber01-VHDL13_DWHG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2611
ber01-VHDL13_DWHG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2611
ber01-VHDL13_DWHG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2702
ber01-VHDL13_DWHH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1976
ber01-VHDL13_DWHH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2311
ber01-VHDL13_DWHH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2311
ber01-VHDL13_DWHH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2362
ber01-VHDL13_DWHH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 2220
ber01-VHDL13_DWHH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2391
ber01-VHDL13_DWHH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2391
ber01-VHDL13_DWHH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2758
ber01-VHDL13_DWLG_281433-2410281433-dsw--0-ia5 28-Oct-2024 14:33 2173
ber01-VHDL13_DWLG_281533-2410281533-dsw--0-ia5 28-Oct-2024 15:33 2173
ber01-VHDL13_DWLG_281633-2410281633-dsw--0-ia5 28-Oct-2024 16:33 2173
ber01-VHDL13_DWLG_281733-2410281733-dsw--0-ia5 28-Oct-2024 17:33 2114
ber01-VHDL13_DWLG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1975
ber01-VHDL13_DWLG_281833-2410281833-dsw--0-ia5 28-Oct-2024 18:33 2114
ber01-VHDL13_DWLG_282033-2410282033-dsw--0-ia5 28-Oct-2024 20:33 1981
ber01-VHDL13_DWLG_282133-2410282133-dsw--0-ia5 28-Oct-2024 21:33 1981
ber01-VHDL13_DWLG_290133-2410290133-dsw--0-ia5 29-Oct-2024 01:33 2392
ber01-VHDL13_DWLG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2386
ber01-VHDL13_DWLG_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:59 2375
ber01-VHDL13_DWLG_290633-2410290633-dsw--0-ia5 29-Oct-2024 06:33 2381
ber01-VHDL13_DWLG_290733-2410290733-dsw--0-ia5 29-Oct-2024 07:33 2385
ber01-VHDL13_DWLG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2253
ber01-VHDL13_DWLG_290833-2410290833-dsw--0-ia5 29-Oct-2024 08:33 2262
ber01-VHDL13_DWLG_291033-2410291033-dsw--0-ia5 29-Oct-2024 10:33 2262
ber01-VHDL13_DWLG_291133-2410291133-dsw--0-ia5 29-Oct-2024 11:33 2262
ber01-VHDL13_DWLG_291233-2410291233-dsw--0-ia5 29-Oct-2024 12:33 2250
ber01-VHDL13_DWLG_291433-2410291433-dsw--0-ia5 29-Oct-2024 14:33 2249
ber01-VHDL13_DWLG_291533-2410291533-dsw--0-ia5 29-Oct-2024 15:33 2043
ber01-VHDL13_DWLG_291633-2410291633-dsw--0-ia5 29-Oct-2024 16:33 2043
ber01-VHDL13_DWLG_291733-2410291733-dsw--0-ia5 29-Oct-2024 17:33 2043
ber01-VHDL13_DWLG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1879
ber01-VHDL13_DWLG_291833-2410291833-dsw--0-ia5 29-Oct-2024 18:33 1885
ber01-VHDL13_DWLG_292033-2410292033-dsw--0-ia5 29-Oct-2024 20:33 1885
ber01-VHDL13_DWLG_292133-2410292133-dsw--0-ia5 29-Oct-2024 21:33 1885
ber01-VHDL13_DWLG_300133-2410300133-dsw--0-ia5 30-Oct-2024 01:33 1995
ber01-VHDL13_DWLG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2028
ber01-VHDL13_DWLG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2033
ber01-VHDL13_DWLG_300633-2410300633-dsw--0-ia5 30-Oct-2024 06:33 2039
ber01-VHDL13_DWLG_300733-2410300733-dsw--0-ia5 30-Oct-2024 07:33 2039
ber01-VHDL13_DWLG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2128
ber01-VHDL13_DWLG_300833-2410300833-dsw--0-ia5 30-Oct-2024 08:33 2174
ber01-VHDL13_DWLG_301033-2410301033-dsw--0-ia5 30-Oct-2024 10:33 2137
ber01-VHDL13_DWLG_301133-2410301133-dsw--0-ia5 30-Oct-2024 11:33 2137
ber01-VHDL13_DWLG_301233-2410301233-dsw--0-ia5 30-Oct-2024 12:33 2137
ber01-VHDL13_DWLH_281433-2410281433-dsw--0-ia5 28-Oct-2024 14:33 2403
ber01-VHDL13_DWLH_281533-2410281533-dsw--0-ia5 28-Oct-2024 15:33 2403
ber01-VHDL13_DWLH_281633-2410281633-dsw--0-ia5 28-Oct-2024 16:33 2403
ber01-VHDL13_DWLH_281733-2410281733-dsw--0-ia5 28-Oct-2024 17:33 2257
ber01-VHDL13_DWLH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 2112
ber01-VHDL13_DWLH_281833-2410281833-dsw--0-ia5 28-Oct-2024 18:33 2257
ber01-VHDL13_DWLH_282033-2410282033-dsw--0-ia5 28-Oct-2024 20:33 2121
ber01-VHDL13_DWLH_282133-2410282133-dsw--0-ia5 28-Oct-2024 21:33 2121
ber01-VHDL13_DWLH_290133-2410290133-dsw--0-ia5 29-Oct-2024 01:33 2348
ber01-VHDL13_DWLH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2339
ber01-VHDL13_DWLH_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:59 2320
ber01-VHDL13_DWLH_290633-2410290633-dsw--0-ia5 29-Oct-2024 06:33 2329
ber01-VHDL13_DWLH_290733-2410290733-dsw--0-ia5 29-Oct-2024 07:33 2329
ber01-VHDL13_DWLH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2213
ber01-VHDL13_DWLH_290833-2410290833-dsw--0-ia5 29-Oct-2024 08:33 2222
ber01-VHDL13_DWLH_291033-2410291033-dsw--0-ia5 29-Oct-2024 10:33 2222
ber01-VHDL13_DWLH_291133-2410291133-dsw--0-ia5 29-Oct-2024 11:33 2222
ber01-VHDL13_DWLH_291233-2410291233-dsw--0-ia5 29-Oct-2024 12:33 2215
ber01-VHDL13_DWLH_291433-2410291433-dsw--0-ia5 29-Oct-2024 14:33 2234
ber01-VHDL13_DWLH_291533-2410291533-dsw--0-ia5 29-Oct-2024 15:33 2090
ber01-VHDL13_DWLH_291633-2410291633-dsw--0-ia5 29-Oct-2024 16:33 2090
ber01-VHDL13_DWLH_291733-2410291733-dsw--0-ia5 29-Oct-2024 17:33 2090
ber01-VHDL13_DWLH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1920
ber01-VHDL13_DWLH_291833-2410291833-dsw--0-ia5 29-Oct-2024 18:33 1929
ber01-VHDL13_DWLH_292033-2410292033-dsw--0-ia5 29-Oct-2024 20:33 1929
ber01-VHDL13_DWLH_292133-2410292133-dsw--0-ia5 29-Oct-2024 21:33 1929
ber01-VHDL13_DWLH_300133-2410300133-dsw--0-ia5 30-Oct-2024 01:33 2097
ber01-VHDL13_DWLH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2157
ber01-VHDL13_DWLH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2162
ber01-VHDL13_DWLH_300633-2410300633-dsw--0-ia5 30-Oct-2024 06:33 2171
ber01-VHDL13_DWLH_300733-2410300733-dsw--0-ia5 30-Oct-2024 07:33 2171
ber01-VHDL13_DWLH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2122
ber01-VHDL13_DWLH_300833-2410300833-dsw--0-ia5 30-Oct-2024 08:33 2171
ber01-VHDL13_DWLH_301033-2410301033-dsw--0-ia5 30-Oct-2024 10:33 2131
ber01-VHDL13_DWLH_301133-2410301133-dsw--0-ia5 30-Oct-2024 11:33 2131
ber01-VHDL13_DWLH_301233-2410301233-dsw--0-ia5 30-Oct-2024 12:33 2131
ber01-VHDL13_DWLI_281433-2410281433-dsw--0-ia5 28-Oct-2024 14:33 2319
ber01-VHDL13_DWLI_281533-2410281533-dsw--0-ia5 28-Oct-2024 15:33 2319
ber01-VHDL13_DWLI_281633-2410281633-dsw--0-ia5 28-Oct-2024 16:33 2319
ber01-VHDL13_DWLI_281733-2410281733-dsw--0-ia5 28-Oct-2024 17:33 2312
ber01-VHDL13_DWLI_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 2134
ber01-VHDL13_DWLI_281833-2410281833-dsw--0-ia5 28-Oct-2024 18:33 2312
ber01-VHDL13_DWLI_282033-2410282033-dsw--0-ia5 28-Oct-2024 20:33 2140
ber01-VHDL13_DWLI_282133-2410282133-dsw--0-ia5 28-Oct-2024 21:33 2140
ber01-VHDL13_DWLI_290133-2410290133-dsw--0-ia5 29-Oct-2024 01:33 2442
ber01-VHDL13_DWLI_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2436
ber01-VHDL13_DWLI_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:59 2457
ber01-VHDL13_DWLI_290633-2410290633-dsw--0-ia5 29-Oct-2024 06:33 2460
ber01-VHDL13_DWLI_290733-2410290733-dsw--0-ia5 29-Oct-2024 07:33 2460
ber01-VHDL13_DWLI_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2336
ber01-VHDL13_DWLI_290833-2410290833-dsw--0-ia5 29-Oct-2024 08:33 2342
ber01-VHDL13_DWLI_291033-2410291033-dsw--0-ia5 29-Oct-2024 10:33 2342
ber01-VHDL13_DWLI_291133-2410291133-dsw--0-ia5 29-Oct-2024 11:33 2342
ber01-VHDL13_DWLI_291233-2410291233-dsw--0-ia5 29-Oct-2024 12:33 2353
ber01-VHDL13_DWLI_291433-2410291433-dsw--0-ia5 29-Oct-2024 14:33 2344
ber01-VHDL13_DWLI_291533-2410291533-dsw--0-ia5 29-Oct-2024 15:33 2267
ber01-VHDL13_DWLI_291633-2410291633-dsw--0-ia5 29-Oct-2024 16:33 2267
ber01-VHDL13_DWLI_291733-2410291733-dsw--0-ia5 29-Oct-2024 17:33 2267
ber01-VHDL13_DWLI_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 2082
ber01-VHDL13_DWLI_291833-2410291833-dsw--0-ia5 29-Oct-2024 18:33 2088
ber01-VHDL13_DWLI_292033-2410292033-dsw--0-ia5 29-Oct-2024 20:33 2088
ber01-VHDL13_DWLI_292133-2410292133-dsw--0-ia5 29-Oct-2024 21:33 2088
ber01-VHDL13_DWLI_300133-2410300133-dsw--0-ia5 30-Oct-2024 01:33 2173
ber01-VHDL13_DWLI_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2327
ber01-VHDL13_DWLI_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2338
ber01-VHDL13_DWLI_300633-2410300633-dsw--0-ia5 30-Oct-2024 06:33 2341
ber01-VHDL13_DWLI_300733-2410300733-dsw--0-ia5 30-Oct-2024 07:33 2341
ber01-VHDL13_DWLI_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2276
ber01-VHDL13_DWLI_300833-2410300833-dsw--0-ia5 30-Oct-2024 08:33 2373
ber01-VHDL13_DWLI_301033-2410301033-dsw--0-ia5 30-Oct-2024 10:33 2282
ber01-VHDL13_DWLI_301133-2410301133-dsw--0-ia5 30-Oct-2024 11:33 2205
ber01-VHDL13_DWLI_301233-2410301233-dsw--0-ia5 30-Oct-2024 12:33 2205
ber01-VHDL13_DWMG_281400-2410281400-dsw--0-ia5 28-Oct-2024 14:30 2217
ber01-VHDL13_DWMG_281500-2410281500-dsw--0-ia5 28-Oct-2024 15:30 2217
ber01-VHDL13_DWMG_281600-2410281600-dsw--0-ia5 28-Oct-2024 16:30 2217
ber01-VHDL13_DWMG_281700-2410281700-dsw--0-ia5 28-Oct-2024 17:30 2246
ber01-VHDL13_DWMG_281800-2410281800-dsw--0-ia5 28-Oct-2024 18:30 2246
ber01-VHDL13_DWMG_281900-2410281900-dsw--0-ia5 28-Oct-2024 19:30 2246
ber01-VHDL13_DWMG_282000-2410282000-dsw--0-ia5 28-Oct-2024 20:30 2268
ber01-VHDL13_DWMG_282100-2410282100-dsw--0-ia5 28-Oct-2024 21:30 2216
ber01-VHDL13_DWMG_282200-2410282200-dsw--0-ia5 28-Oct-2024 22:30 2216
ber01-VHDL13_DWMG_282300-2410282300-dsw--0-ia5 28-Oct-2024 23:30 2470
ber01-VHDL13_DWMG_290000-2410290000-dsw--0-ia5 29-Oct-2024 00:30 2470
ber01-VHDL13_DWMG_290100-2410290100-dsw--0-ia5 29-Oct-2024 01:30 2470
ber01-VHDL13_DWMG_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:30 2470
ber01-VHDL13_DWMG_290300-2410290300-dsw--0-ia5 29-Oct-2024 03:30 2470
ber01-VHDL13_DWMG_290400-2410290400-dsw--0-ia5 29-Oct-2024 04:30 2470
ber01-VHDL13_DWMG_290500-2410290500-dsw--0-ia5 29-Oct-2024 05:30 2469
ber01-VHDL13_DWMG_290600-2410290600-dsw--0-ia5 29-Oct-2024 06:30 2469
ber01-VHDL13_DWMG_290700-2410290700-dsw--0-ia5 29-Oct-2024 07:30 2456
ber01-VHDL13_DWMG_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:30 2456
ber01-VHDL13_DWMG_290900-2410290900-dsw--0-ia5 29-Oct-2024 09:30 2265
ber01-VHDL13_DWMG_291000-2410291000-dsw--0-ia5 29-Oct-2024 10:30 2265
ber01-VHDL13_DWMG_291100-2410291100-dsw--0-ia5 29-Oct-2024 11:30 2258
ber01-VHDL13_DWMG_291200-2410291200-dsw--0-ia5 29-Oct-2024 12:30 2258
ber01-VHDL13_DWMG_291300-2410291300-dsw--0-ia5 29-Oct-2024 13:30 2258
ber01-VHDL13_DWMG_291400-2410291400-dsw--0-ia5 29-Oct-2024 14:30 2258
ber01-VHDL13_DWMG_291500-2410291500-dsw--0-ia5 29-Oct-2024 15:30 2258
ber01-VHDL13_DWMG_291600-2410291600-dsw--0-ia5 29-Oct-2024 16:30 2258
ber01-VHDL13_DWMG_291700-2410291700-dsw--0-ia5 29-Oct-2024 17:30 1912
ber01-VHDL13_DWMG_291800-2410291800-dsw--0-ia5 29-Oct-2024 18:30 1912
ber01-VHDL13_DWMG_291900-2410291900-dsw--0-ia5 29-Oct-2024 19:30 2064
ber01-VHDL13_DWMG_292000-2410292000-dsw--0-ia5 29-Oct-2024 20:30 2064
ber01-VHDL13_DWMG_292100-2410292100-dsw--0-ia5 29-Oct-2024 21:30 2064
ber01-VHDL13_DWMG_292200-2410292200-dsw--0-ia5 29-Oct-2024 22:30 2092
ber01-VHDL13_DWMG_292300-2410292300-dsw--0-ia5 29-Oct-2024 23:30 2426
ber01-VHDL13_DWMG_300000-2410300000-dsw--0-ia5 30-Oct-2024 00:30 2426
ber01-VHDL13_DWMG_300100-2410300100-dsw--0-ia5 30-Oct-2024 01:30 2426
ber01-VHDL13_DWMG_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:30 2426
ber01-VHDL13_DWMG_300300-2410300300-dsw--0-ia5 30-Oct-2024 03:33 2426
ber01-VHDL13_DWMG_300400-2410300400-dsw--0-ia5 30-Oct-2024 04:30 2410
ber01-VHDL13_DWMG_300500-2410300500-dsw--0-ia5 30-Oct-2024 05:30 2409
ber01-VHDL13_DWMG_300600-2410300600-dsw--0-ia5 30-Oct-2024 06:30 2409
ber01-VHDL13_DWMG_300700-2410300700-dsw--0-ia5 30-Oct-2024 07:30 2396
ber01-VHDL13_DWMG_300800-2410300800-dsw--0-ia5 30-Oct-2024 08:30 2396
ber01-VHDL13_DWMG_300900-2410300900-dsw--0-ia5 30-Oct-2024 09:30 2247
ber01-VHDL13_DWMG_301000-2410301000-dsw--0-ia5 30-Oct-2024 10:30 2247
ber01-VHDL13_DWMG_301100-2410301100-dsw--0-ia5 30-Oct-2024 11:30 2247
ber01-VHDL13_DWMG_301200-2410301200-dsw--0-ia5 30-Oct-2024 12:30 2247
ber01-VHDL13_DWMG_301300-2410301300-dsw--0-ia5 30-Oct-2024 13:30 2247
ber01-VHDL13_DWMO_281400-2410281400-dsw--0-ia5 28-Oct-2024 14:30 2318
ber01-VHDL13_DWMO_281500-2410281500-dsw--0-ia5 28-Oct-2024 15:30 2318
ber01-VHDL13_DWMO_281600-2410281600-dsw--0-ia5 28-Oct-2024 16:30 2318
ber01-VHDL13_DWMO_281700-2410281700-dsw--0-ia5 28-Oct-2024 17:30 2318
ber01-VHDL13_DWMO_281800-2410281800-dsw--0-ia5 28-Oct-2024 18:30 2238
ber01-VHDL13_DWMO_281900-2410281900-dsw--0-ia5 28-Oct-2024 19:30 2238
ber01-VHDL13_DWMO_282000-2410282000-dsw--0-ia5 28-Oct-2024 20:30 2220
ber01-VHDL13_DWMO_282100-2410282100-dsw--0-ia5 28-Oct-2024 21:30 2177
ber01-VHDL13_DWMO_282200-2410282200-dsw--0-ia5 28-Oct-2024 22:30 2177
ber01-VHDL13_DWMO_282300-2410282300-dsw--0-ia5 28-Oct-2024 23:30 2445
ber01-VHDL13_DWMO_290000-2410290000-dsw--0-ia5 29-Oct-2024 00:30 2445
ber01-VHDL13_DWMO_290100-2410290100-dsw--0-ia5 29-Oct-2024 01:30 2445
ber01-VHDL13_DWMO_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:30 2445
ber01-VHDL13_DWMO_290300-2410290300-dsw--0-ia5 29-Oct-2024 03:30 2445
ber01-VHDL13_DWMO_290400-2410290400-dsw--0-ia5 29-Oct-2024 04:30 2445
ber01-VHDL13_DWMO_290500-2410290500-dsw--0-ia5 29-Oct-2024 05:30 2445
ber01-VHDL13_DWMO_290600-2410290600-dsw--0-ia5 29-Oct-2024 06:30 2445
ber01-VHDL13_DWMO_290700-2410290700-dsw--0-ia5 29-Oct-2024 07:30 2445
ber01-VHDL13_DWMO_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:30 2445
ber01-VHDL13_DWMO_290900-2410290900-dsw--0-ia5 29-Oct-2024 09:30 2445
ber01-VHDL13_DWMO_291000-2410291000-dsw--0-ia5 29-Oct-2024 10:30 2371
ber01-VHDL13_DWMO_291100-2410291100-dsw--0-ia5 29-Oct-2024 11:30 2371
ber01-VHDL13_DWMO_291200-2410291200-dsw--0-ia5 29-Oct-2024 12:30 2219
ber01-VHDL13_DWMO_291300-2410291300-dsw--0-ia5 29-Oct-2024 13:30 2219
ber01-VHDL13_DWMO_291400-2410291400-dsw--0-ia5 29-Oct-2024 14:30 2219
ber01-VHDL13_DWMO_291500-2410291500-dsw--0-ia5 29-Oct-2024 15:30 2219
ber01-VHDL13_DWMO_291600-2410291600-dsw--0-ia5 29-Oct-2024 16:30 2219
ber01-VHDL13_DWMO_291700-2410291700-dsw--0-ia5 29-Oct-2024 17:30 1963
ber01-VHDL13_DWMO_291800-2410291800-dsw--0-ia5 29-Oct-2024 18:30 1963
ber01-VHDL13_DWMO_291900-2410291900-dsw--0-ia5 29-Oct-2024 19:30 1963
ber01-VHDL13_DWMO_292000-2410292000-dsw--0-ia5 29-Oct-2024 20:30 1975
ber01-VHDL13_DWMO_292100-2410292100-dsw--0-ia5 29-Oct-2024 21:30 1975
ber01-VHDL13_DWMO_292200-2410292200-dsw--0-ia5 29-Oct-2024 22:30 1893
ber01-VHDL13_DWMO_292300-2410292300-dsw--0-ia5 29-Oct-2024 23:30 2259
ber01-VHDL13_DWMO_300000-2410300000-dsw--0-ia5 30-Oct-2024 00:30 2259
ber01-VHDL13_DWMO_300100-2410300100-dsw--0-ia5 30-Oct-2024 01:30 2259
ber01-VHDL13_DWMO_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:30 2259
ber01-VHDL13_DWMO_300300-2410300300-dsw--0-ia5 30-Oct-2024 03:33 2259
ber01-VHDL13_DWMO_300400-2410300400-dsw--0-ia5 30-Oct-2024 04:30 2211
ber01-VHDL13_DWMO_300500-2410300500-dsw--0-ia5 30-Oct-2024 05:30 2211
ber01-VHDL13_DWMO_300600-2410300600-dsw--0-ia5 30-Oct-2024 06:30 2211
ber01-VHDL13_DWMO_300700-2410300700-dsw--0-ia5 30-Oct-2024 07:30 2211
ber01-VHDL13_DWMO_300800-2410300800-dsw--0-ia5 30-Oct-2024 08:30 2211
ber01-VHDL13_DWMO_300900-2410300900-dsw--0-ia5 30-Oct-2024 09:30 2155
ber01-VHDL13_DWMO_301000-2410301000-dsw--0-ia5 30-Oct-2024 10:30 2155
ber01-VHDL13_DWMO_301100-2410301100-dsw--0-ia5 30-Oct-2024 11:30 2155
ber01-VHDL13_DWMO_301200-2410301200-dsw--0-ia5 30-Oct-2024 12:30 2155
ber01-VHDL13_DWMO_301300-2410301300-dsw--0-ia5 30-Oct-2024 13:30 2155
ber01-VHDL13_DWMP_281400-2410281400-dsw--0-ia5 28-Oct-2024 14:30 2244
ber01-VHDL13_DWMP_281500-2410281500-dsw--0-ia5 28-Oct-2024 15:30 2244
ber01-VHDL13_DWMP_281600-2410281600-dsw--0-ia5 28-Oct-2024 16:30 2244
ber01-VHDL13_DWMP_281700-2410281700-dsw--0-ia5 28-Oct-2024 17:30 2244
ber01-VHDL13_DWMP_281800-2410281800-dsw--0-ia5 28-Oct-2024 18:30 2103
ber01-VHDL13_DWMP_281900-2410281900-dsw--0-ia5 28-Oct-2024 19:30 2103
ber01-VHDL13_DWMP_282000-2410282000-dsw--0-ia5 28-Oct-2024 20:30 2098
ber01-VHDL13_DWMP_282100-2410282100-dsw--0-ia5 28-Oct-2024 21:30 2102
ber01-VHDL13_DWMP_282200-2410282200-dsw--0-ia5 28-Oct-2024 22:30 2102
ber01-VHDL13_DWMP_282300-2410282300-dsw--0-ia5 28-Oct-2024 23:30 2347
ber01-VHDL13_DWMP_290000-2410290000-dsw--0-ia5 29-Oct-2024 00:30 2347
ber01-VHDL13_DWMP_290100-2410290100-dsw--0-ia5 29-Oct-2024 01:30 2347
ber01-VHDL13_DWMP_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:30 2347
ber01-VHDL13_DWMP_290300-2410290300-dsw--0-ia5 29-Oct-2024 03:30 2347
ber01-VHDL13_DWMP_290400-2410290400-dsw--0-ia5 29-Oct-2024 04:30 2347
ber01-VHDL13_DWMP_290500-2410290500-dsw--0-ia5 29-Oct-2024 05:30 2344
ber01-VHDL13_DWMP_290600-2410290600-dsw--0-ia5 29-Oct-2024 06:30 2344
ber01-VHDL13_DWMP_290700-2410290700-dsw--0-ia5 29-Oct-2024 07:30 2344
ber01-VHDL13_DWMP_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:30 2344
ber01-VHDL13_DWMP_290900-2410290900-dsw--0-ia5 29-Oct-2024 09:30 2359
ber01-VHDL13_DWMP_291000-2410291000-dsw--0-ia5 29-Oct-2024 10:30 2359
ber01-VHDL13_DWMP_291100-2410291100-dsw--0-ia5 29-Oct-2024 11:30 2359
ber01-VHDL13_DWMP_291200-2410291200-dsw--0-ia5 29-Oct-2024 12:30 2332
ber01-VHDL13_DWMP_291300-2410291300-dsw--0-ia5 29-Oct-2024 13:30 2332
ber01-VHDL13_DWMP_291400-2410291400-dsw--0-ia5 29-Oct-2024 14:30 2332
ber01-VHDL13_DWMP_291500-2410291500-dsw--0-ia5 29-Oct-2024 15:30 2332
ber01-VHDL13_DWMP_291600-2410291600-dsw--0-ia5 29-Oct-2024 16:30 2332
ber01-VHDL13_DWMP_291700-2410291700-dsw--0-ia5 29-Oct-2024 17:30 2066
ber01-VHDL13_DWMP_291800-2410291800-dsw--0-ia5 29-Oct-2024 18:30 2066
ber01-VHDL13_DWMP_291900-2410291900-dsw--0-ia5 29-Oct-2024 19:30 2066
ber01-VHDL13_DWMP_292000-2410292000-dsw--0-ia5 29-Oct-2024 20:30 2079
ber01-VHDL13_DWMP_292100-2410292100-dsw--0-ia5 29-Oct-2024 21:30 2079
ber01-VHDL13_DWMP_292200-2410292200-dsw--0-ia5 29-Oct-2024 22:30 2059
ber01-VHDL13_DWMP_292300-2410292300-dsw--0-ia5 29-Oct-2024 23:30 2488
ber01-VHDL13_DWMP_300000-2410300000-dsw--0-ia5 30-Oct-2024 00:30 2488
ber01-VHDL13_DWMP_300100-2410300100-dsw--0-ia5 30-Oct-2024 01:30 2488
ber01-VHDL13_DWMP_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:30 2488
ber01-VHDL13_DWMP_300300-2410300300-dsw--0-ia5 30-Oct-2024 03:33 2488
ber01-VHDL13_DWMP_300400-2410300400-dsw--0-ia5 30-Oct-2024 04:30 2508
ber01-VHDL13_DWMP_300500-2410300500-dsw--0-ia5 30-Oct-2024 05:30 2508
ber01-VHDL13_DWMP_300600-2410300600-dsw--0-ia5 30-Oct-2024 06:30 2505
ber01-VHDL13_DWMP_300700-2410300700-dsw--0-ia5 30-Oct-2024 07:30 2505
ber01-VHDL13_DWMP_300800-2410300800-dsw--0-ia5 30-Oct-2024 08:30 2505
ber01-VHDL13_DWMP_300900-2410300900-dsw--0-ia5 30-Oct-2024 09:30 2375
ber01-VHDL13_DWMP_301000-2410301000-dsw--0-ia5 30-Oct-2024 10:30 2375
ber01-VHDL13_DWMP_301100-2410301100-dsw--0-ia5 30-Oct-2024 11:30 2375
ber01-VHDL13_DWMP_301200-2410301200-dsw--0-ia5 30-Oct-2024 12:30 2375
ber01-VHDL13_DWMP_301300-2410301300-dsw--0-ia5 30-Oct-2024 13:30 2375
ber01-VHDL13_DWOG_281700-2410281700-dsw--0-ia5 28-Oct-2024 18:30 3044
ber01-VHDL13_DWOG_290300-2410290300-dsw--0-ia5 29-Oct-2024 04:00 3489
ber01-VHDL13_DWOG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 3723
ber01-VHDL13_DWOG_291700-2410291700-dsw--0-ia5 29-Oct-2024 18:30 3420
ber01-VHDL13_DWOG_300300-2410300300-dsw--0-ia5 30-Oct-2024 04:00 4007
ber01-VHDL13_DWOG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 4465
ber01-VHDL13_DWOH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:28 2265
ber01-VHDL13_DWOH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:28 2437
ber01-VHDL13_DWOH_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:58 2415
ber01-VHDL13_DWOH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:28 2427
ber01-VHDL13_DWOH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:28 2323
ber01-VHDL13_DWOH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:28 2620
ber01-VHDL13_DWOH_300400-2410300400-dsw--0-ia5 30-Oct-2024 05:58 2528
ber01-VHDL13_DWOH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:28 2484
ber01-VHDL13_DWOI_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:28 2235
ber01-VHDL13_DWOI_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:28 2363
ber01-VHDL13_DWOI_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:58 2360
ber01-VHDL13_DWOI_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:28 2430
ber01-VHDL13_DWOI_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:28 2372
ber01-VHDL13_DWOI_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:28 2533
ber01-VHDL13_DWOI_300400-2410300400-dsw--0-ia5 30-Oct-2024 05:58 2443
ber01-VHDL13_DWOI_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:28 2405
ber01-VHDL13_DWON_281356-2410281356-dsw--0-ia5 28-Oct-2024 13:56 3308
ber01-VHDL13_DWON_281441-2410281441-dsw--0-ia5 28-Oct-2024 14:41 3308
ber01-VHDL13_DWON_281747-2410281747-dsw--0-ia5 28-Oct-2024 17:48 3311
ber01-VHDL13_DWON_281757-2410281757-dsw--0-ia5 28-Oct-2024 17:57 3320
ber01-VHDL13_DWON_282217-2410282217-dsw--0-ia5 28-Oct-2024 22:17 3321
ber01-VHDL13_DWON_290338-2410290338-dsw--0-ia5 29-Oct-2024 03:38 3746
ber01-VHDL13_DWON_290629-2410290629-dsw--0-ia5 29-Oct-2024 06:29 3947
ber01-VHDL13_DWON_290657-2410290657-dsw--0-ia5 29-Oct-2024 06:57 4091
ber01-VHDL13_DWON_290753-2410290753-dsw--0-ia5 29-Oct-2024 07:53 4091
ber01-VHDL13_DWON_291243-2410291243-dsw--0-ia5 29-Oct-2024 12:43 4045
ber01-VHDL13_DWON_291452-2410291452-dsw--0-ia5 29-Oct-2024 14:52 3423
ber01-VHDL13_DWON_291826-2410291826-dsw--0-ia5 29-Oct-2024 18:26 3423
ber01-VHDL13_DWON_292257-2410292257-dsw--0-ia5 29-Oct-2024 22:57 3548
ber01-VHDL13_DWON_300228-2410300228-dsw--0-ia5 30-Oct-2024 02:28 3689
ber01-VHDL13_DWON_300613-2410300613-dsw--0-ia5 30-Oct-2024 06:13 3686
ber01-VHDL13_DWON_300746-2410300746-dsw--0-ia5 30-Oct-2024 07:46 4124
ber01-VHDL13_DWON_300851-2410300851-dsw--0-ia5 30-Oct-2024 08:51 4124
ber01-VHDL13_DWON_301030-2410301030-dsw--0-ia5 30-Oct-2024 10:30 4124
ber01-VHDL13_DWON_301213-2410301213-dsw--0-ia5 30-Oct-2024 12:13 4028
ber01-VHDL13_DWPG_281430-2410281430-dsw--0-ia5 28-Oct-2024 14:30 1815
ber01-VHDL13_DWPG_281530-2410281530-dsw--0-ia5 28-Oct-2024 15:30 1815
ber01-VHDL13_DWPG_281630-2410281630-dsw--0-ia5 28-Oct-2024 16:30 1815
ber01-VHDL13_DWPG_281730-2410281730-dsw--0-ia5 28-Oct-2024 17:30 1717
ber01-VHDL13_DWPG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1532
ber01-VHDL13_DWPG_281830-2410281830-dsw--0-ia5 28-Oct-2024 18:30 1717
ber01-VHDL13_DWPG_282030-2410282030-dsw--0-ia5 28-Oct-2024 20:30 1531
ber01-VHDL13_DWPG_282130-2410282130-dsw--0-ia5 28-Oct-2024 21:30 1531
ber01-VHDL13_DWPG_290130-2410290130-dsw--0-ia5 29-Oct-2024 01:30 1766
ber01-VHDL13_DWPG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 1767
ber01-VHDL13_DWPG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 1975
ber01-VHDL13_DWPG_290730-2410290730-dsw--0-ia5 29-Oct-2024 07:30 1973
ber01-VHDL13_DWPG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 1989
ber01-VHDL13_DWPG_290830-2410290830-dsw--0-ia5 29-Oct-2024 08:30 1973
ber01-VHDL13_DWPG_291030-2410291030-dsw--0-ia5 29-Oct-2024 10:30 1988
ber01-VHDL13_DWPG_291130-2410291130-dsw--0-ia5 29-Oct-2024 11:30 1988
ber01-VHDL13_DWPG_291230-2410291230-dsw--0-ia5 29-Oct-2024 12:30 1988
ber01-VHDL13_DWPG_291330-2410291330-dsw--0-ia5 29-Oct-2024 13:30 1988
ber01-VHDL13_DWPG_291430-2410291430-dsw--0-ia5 29-Oct-2024 14:30 1988
ber01-VHDL13_DWPG_291530-2410291530-dsw--0-ia5 29-Oct-2024 15:30 1988
ber01-VHDL13_DWPG_291630-2410291630-dsw--0-ia5 29-Oct-2024 16:30 2006
ber01-VHDL13_DWPG_291730-2410291730-dsw--0-ia5 29-Oct-2024 17:30 2006
ber01-VHDL13_DWPG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1832
ber01-VHDL13_DWPG_291830-2410291830-dsw--0-ia5 29-Oct-2024 18:30 1831
ber01-VHDL13_DWPG_292030-2410292030-dsw--0-ia5 29-Oct-2024 20:30 1831
ber01-VHDL13_DWPG_292130-2410292130-dsw--0-ia5 29-Oct-2024 21:30 1831
ber01-VHDL13_DWPG_300130-2410300130-dsw--0-ia5 30-Oct-2024 01:30 1961
ber01-VHDL13_DWPG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2015
ber01-VHDL13_DWPG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 1809
ber01-VHDL13_DWPG_300730-2410300730-dsw--0-ia5 30-Oct-2024 07:30 1807
ber01-VHDL13_DWPG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 1838
ber01-VHDL13_DWPG_300830-2410300830-dsw--0-ia5 30-Oct-2024 08:30 1807
ber01-VHDL13_DWPG_301030-2410301030-dsw--0-ia5 30-Oct-2024 10:30 1837
ber01-VHDL13_DWPG_301130-2410301130-dsw--0-ia5 30-Oct-2024 11:30 1837
ber01-VHDL13_DWPG_301230-2410301230-dsw--0-ia5 30-Oct-2024 12:30 1837
ber01-VHDL13_DWPG_301330-2410301330-dsw--0-ia5 30-Oct-2024 13:30 1837
ber01-VHDL13_DWPH_281430-2410281430-dsw--0-ia5 28-Oct-2024 14:30 1936
ber01-VHDL13_DWPH_281530-2410281530-dsw--0-ia5 28-Oct-2024 15:30 1936
ber01-VHDL13_DWPH_281630-2410281630-dsw--0-ia5 28-Oct-2024 16:30 1936
ber01-VHDL13_DWPH_281730-2410281730-dsw--0-ia5 28-Oct-2024 17:30 1889
ber01-VHDL13_DWPH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1738
ber01-VHDL13_DWPH_281830-2410281830-dsw--0-ia5 28-Oct-2024 18:30 1889
ber01-VHDL13_DWPH_282030-2410282030-dsw--0-ia5 28-Oct-2024 20:30 1738
ber01-VHDL13_DWPH_282130-2410282130-dsw--0-ia5 28-Oct-2024 21:30 1738
ber01-VHDL13_DWPH_290130-2410290130-dsw--0-ia5 29-Oct-2024 01:30 2046
ber01-VHDL13_DWPH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2046
ber01-VHDL13_DWPH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2308
ber01-VHDL13_DWPH_290730-2410290730-dsw--0-ia5 29-Oct-2024 07:30 2308
ber01-VHDL13_DWPH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2334
ber01-VHDL13_DWPH_290830-2410290830-dsw--0-ia5 29-Oct-2024 08:30 2308
ber01-VHDL13_DWPH_291030-2410291030-dsw--0-ia5 29-Oct-2024 10:30 2334
ber01-VHDL13_DWPH_291130-2410291130-dsw--0-ia5 29-Oct-2024 11:30 2334
ber01-VHDL13_DWPH_291230-2410291230-dsw--0-ia5 29-Oct-2024 12:30 2334
ber01-VHDL13_DWPH_291330-2410291330-dsw--0-ia5 29-Oct-2024 13:30 2334
ber01-VHDL13_DWPH_291430-2410291430-dsw--0-ia5 29-Oct-2024 14:30 2334
ber01-VHDL13_DWPH_291530-2410291530-dsw--0-ia5 29-Oct-2024 15:30 2334
ber01-VHDL13_DWPH_291630-2410291630-dsw--0-ia5 29-Oct-2024 16:30 2379
ber01-VHDL13_DWPH_291730-2410291730-dsw--0-ia5 29-Oct-2024 17:30 2379
ber01-VHDL13_DWPH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 2295
ber01-VHDL13_DWPH_291830-2410291830-dsw--0-ia5 29-Oct-2024 18:30 2295
ber01-VHDL13_DWPH_292030-2410292030-dsw--0-ia5 29-Oct-2024 20:30 2295
ber01-VHDL13_DWPH_292130-2410292130-dsw--0-ia5 29-Oct-2024 21:30 2295
ber01-VHDL13_DWPH_300130-2410300130-dsw--0-ia5 30-Oct-2024 01:30 2510
ber01-VHDL13_DWPH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 2643
ber01-VHDL13_DWPH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2712
ber01-VHDL13_DWPH_300730-2410300730-dsw--0-ia5 30-Oct-2024 07:30 2712
ber01-VHDL13_DWPH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2768
ber01-VHDL13_DWPH_300830-2410300830-dsw--0-ia5 30-Oct-2024 08:30 2712
ber01-VHDL13_DWPH_301030-2410301030-dsw--0-ia5 30-Oct-2024 10:30 2768
ber01-VHDL13_DWPH_301130-2410301130-dsw--0-ia5 30-Oct-2024 11:30 2768
ber01-VHDL13_DWPH_301230-2410301230-dsw--0-ia5 30-Oct-2024 12:30 2768
ber01-VHDL13_DWPH_301330-2410301330-dsw--0-ia5 30-Oct-2024 13:30 2768
ber01-VHDL13_DWSG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 2096
ber01-VHDL13_DWSG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:30 2063
ber01-VHDL13_DWSG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2094
ber01-VHDL13_DWSG_290400_COR-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2017
ber01-VHDL13_DWSG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 2013
ber01-VHDL13_DWSG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1766
ber01-VHDL13_DWSG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:33 1957
ber01-VHDL13_DWSG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2308
ber01-VHDL13_DWSG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2382
ber01-VHDL13_DWSN_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1896
ber01-VHDL13_DWSN_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2028
ber01-VHDL13_DWSN_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 1699
ber01-VHDL13_DWSN_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1580
ber01-VHDL13_DWSN_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 1917
ber01-VHDL13_DWSN_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2014
ber01-VHDL13_DWSO_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 2013
ber01-VHDL13_DWSO_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2080
ber01-VHDL13_DWSO_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 1744
ber01-VHDL13_DWSO_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1656
ber01-VHDL13_DWSO_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2253
ber01-VHDL13_DWSO_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 2250
ber01-VHDL13_DWSP_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:30 1977
ber01-VHDL13_DWSP_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2048
ber01-VHDL13_DWSP_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:30 1770
ber01-VHDL13_DWSP_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:30 1621
ber01-VHDL13_DWSP_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 1959
ber01-VHDL13_DWSP_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:30 1957
ber01-VHDL17_DWOG_291200-2410291200-dsw--0-ia5 29-Oct-2024 12:12 2927
ber01-VHDL17_DWOG_301200-2410301200-dsw--0-ia5 30-Oct-2024 12:05 2483
swis2-VHDL20_DWEG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2592
swis2-VHDL20_DWEG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2715
swis2-VHDL20_DWEG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:15 2736
swis2-VHDL20_DWEG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2906
swis2-VHDL20_DWEG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2650
swis2-VHDL20_DWEG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2898
swis2-VHDL20_DWEG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2851
swis2-VHDL20_DWEG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2962
swis2-VHDL20_DWEH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2726
swis2-VHDL20_DWEH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2858
swis2-VHDL20_DWEH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:15 2698
swis2-VHDL20_DWEH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2894
swis2-VHDL20_DWEH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2911
swis2-VHDL20_DWEH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 3046
swis2-VHDL20_DWEH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2953
swis2-VHDL20_DWEH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 3134
swis2-VHDL20_DWEI_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2587
swis2-VHDL20_DWEI_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2655
swis2-VHDL20_DWEI_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:15 2712
swis2-VHDL20_DWEI_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2956
swis2-VHDL20_DWEI_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2724
swis2-VHDL20_DWEI_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2825
swis2-VHDL20_DWEI_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2797
swis2-VHDL20_DWEI_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2930
swis2-VHDL20_DWHG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2554
swis2-VHDL20_DWHG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2917
swis2-VHDL20_DWHG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2917
swis2-VHDL20_DWHG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2988
swis2-VHDL20_DWHG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2654
swis2-VHDL20_DWHG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2964
swis2-VHDL20_DWHG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2974
swis2-VHDL20_DWHG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 3236
swis2-VHDL20_DWHH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2337
swis2-VHDL20_DWHH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2672
swis2-VHDL20_DWHH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2672
swis2-VHDL20_DWHH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2903
swis2-VHDL20_DWHH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2581
swis2-VHDL20_DWHH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2752
swis2-VHDL20_DWHH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2760
swis2-VHDL20_DWHH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 3304
swis2-VHDL20_DWLG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2343
swis2-VHDL20_DWLG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2757
swis2-VHDL20_DWLG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2743
swis2-VHDL20_DWLG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2773
swis2-VHDL20_DWLG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2247
swis2-VHDL20_DWLG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2399
swis2-VHDL20_DWLG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2403
swis2-VHDL20_DWLG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2647
swis2-VHDL20_DWLH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2487
swis2-VHDL20_DWLH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2717
swis2-VHDL20_DWLH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2695
swis2-VHDL20_DWLH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2744
swis2-VHDL20_DWLH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2295
swis2-VHDL20_DWLH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2535
swis2-VHDL20_DWLH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2539
swis2-VHDL20_DWLH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2652
swis2-VHDL20_DWLI_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2504
swis2-VHDL20_DWLI_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2809
swis2-VHDL20_DWLI_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2824
swis2-VHDL20_DWLI_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2857
swis2-VHDL20_DWLI_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2452
swis2-VHDL20_DWLI_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2700
swis2-VHDL20_DWLI_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2707
swis2-VHDL20_DWLI_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2796
swis2-VHDL20_DWMG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2644
swis2-VHDL20_DWMG_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:45 2809
swis2-VHDL20_DWMG_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:15 2846
swis2-VHDL20_DWMG_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:45 2996
swis2-VHDL20_DWMG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2440
swis2-VHDL20_DWMG_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:45 2802
swis2-VHDL20_DWMG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2788
swis2-VHDL20_DWMG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2786
swis2-VHDL20_DWMO_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2618
swis2-VHDL20_DWMO_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:45 2826
swis2-VHDL20_DWMO_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:15 2828
swis2-VHDL20_DWMO_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:45 2996
swis2-VHDL20_DWMO_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2358
swis2-VHDL20_DWMO_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:45 2640
swis2-VHDL20_DWMO_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2599
swis2-VHDL20_DWMO_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2708
swis2-VHDL20_DWMP_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2463
swis2-VHDL20_DWMP_290200-2410290200-dsw--0-ia5 29-Oct-2024 02:45 2729
swis2-VHDL20_DWMP_290400-2410290400-dsw--0-ia5 29-Oct-2024 05:15 2726
swis2-VHDL20_DWMP_290800-2410290800-dsw--0-ia5 29-Oct-2024 08:45 2893
swis2-VHDL20_DWMP_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2449
swis2-VHDL20_DWMP_300200-2410300200-dsw--0-ia5 30-Oct-2024 02:45 2870
swis2-VHDL20_DWMP_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2886
swis2-VHDL20_DWMP_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2923
swis2-VHDL20_DWPG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 1996
swis2-VHDL20_DWPG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2100
swis2-VHDL20_DWPG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2305
swis2-VHDL20_DWPG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2455
swis2-VHDL20_DWPG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2298
swis2-VHDL20_DWPG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2348
swis2-VHDL20_DWPG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 2141
swis2-VHDL20_DWPG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2303
swis2-VHDL20_DWPH_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2202
swis2-VHDL20_DWPH_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2378
swis2-VHDL20_DWPH_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:00 2640
swis2-VHDL20_DWPH_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2800
swis2-VHDL20_DWPH_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2761
swis2-VHDL20_DWPH_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2975
swis2-VHDL20_DWPH_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:00 3046
swis2-VHDL20_DWPH_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 3233
swis2-VHDL20_DWSG_281800-2410281800-dsw--0-ia5 28-Oct-2024 19:45 2452
swis2-VHDL20_DWSG_290200-2410290200-dsw--0-ia5 29-Oct-2024 03:45 2409
swis2-VHDL20_DWSG_290400-2410290400-dsw--0-ia5 29-Oct-2024 06:15 2369
swis2-VHDL20_DWSG_290800-2410290800-dsw--0-ia5 29-Oct-2024 09:45 2515
swis2-VHDL20_DWSG_291800-2410291800-dsw--0-ia5 29-Oct-2024 19:45 2122
swis2-VHDL20_DWSG_300200-2410300200-dsw--0-ia5 30-Oct-2024 03:45 2303
swis2-VHDL20_DWSG_300400-2410300400-dsw--0-ia5 30-Oct-2024 06:15 2664
swis2-VHDL20_DWSG_300800-2410300800-dsw--0-ia5 30-Oct-2024 09:45 2883
wst04-VHDL20_DWEG_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 254441
wst04-VHDL20_DWEG_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:45 255602
wst04-VHDL20_DWEG_290400-2410290400-omedes--0.pdf 29-Oct-2024 06:15 254576
wst04-VHDL20_DWEG_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:45 253030
wst04-VHDL20_DWEG_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 252601
wst04-VHDL20_DWEG_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 252998
wst04-VHDL20_DWEG_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 252029
wst04-VHDL20_DWEG_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 255735
wst04-VHDL20_DWEH_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 257215
wst04-VHDL20_DWEH_290400-2410290400-omedes--0.pdf 29-Oct-2024 06:15 257249
wst04-VHDL20_DWEH_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:45 255673
wst04-VHDL20_DWEH_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 255200
wst04-VHDL20_DWEH_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 256392
wst04-VHDL20_DWEH_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 255825
wst04-VHDL20_DWEI_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 350965
wst04-VHDL20_DWEI_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:45 351572
wst04-VHDL20_DWEI_290400-2410290400-omedes--0.pdf 29-Oct-2024 06:15 351026
wst04-VHDL20_DWEI_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:45 347608
wst04-VHDL20_DWEI_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 347217
wst04-VHDL20_DWEI_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 347373
wst04-VHDL20_DWEI_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 346850
wst04-VHDL20_DWEI_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 350276
wst04-VHDL20_DWHG_281800-2410281800-oflxs888--0..> 28-Oct-2024 19:45 344778
wst04-VHDL20_DWHG_290200-2410290200-oflxs888--0..> 29-Oct-2024 03:45 344429
wst04-VHDL20_DWHG_290400-2410290400-oflxs888--0..> 29-Oct-2024 06:00 344366
wst04-VHDL20_DWHG_290800-2410290800-oflxs888--0..> 29-Oct-2024 09:45 343301
wst04-VHDL20_DWHG_291800-2410291800-oflxs888--0..> 29-Oct-2024 19:45 341708
wst04-VHDL20_DWHG_300200-2410300200-oflxs888--0..> 30-Oct-2024 03:45 342212
wst04-VHDL20_DWHG_300400-2410300400-oflxs888--0..> 30-Oct-2024 06:00 342372
wst04-VHDL20_DWHG_300800-2410300800-oflxs888--0..> 30-Oct-2024 09:45 354151
wst04-VHDL20_DWHH_281800-2410281800-oflxs888--0..> 28-Oct-2024 19:45 321867
wst04-VHDL20_DWHH_290200-2410290200-oflxs888--0..> 29-Oct-2024 03:45 322649
wst04-VHDL20_DWHH_290400-2410290400-oflxs888--0..> 29-Oct-2024 06:00 322676
wst04-VHDL20_DWHH_290800-2410290800-oflxs888--0..> 29-Oct-2024 09:45 330133
wst04-VHDL20_DWHH_291800-2410291800-oflxs888--0..> 29-Oct-2024 19:45 329673
wst04-VHDL20_DWHH_300200-2410300200-oflxs888--0..> 30-Oct-2024 03:45 329671
wst04-VHDL20_DWHH_300400-2410300400-oflxs888--0..> 30-Oct-2024 06:00 329699
wst04-VHDL20_DWHH_300800-2410300800-oflxs888--0..> 30-Oct-2024 09:45 333902
wst04-VHDL20_DWLG_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:40 340044
wst04-VHDL20_DWLG_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:40 341151
wst04-VHDL20_DWLG_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:59 340900
wst04-VHDL20_DWLG_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:40 340193
wst04-VHDL20_DWLG_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:40 339266
wst04-VHDL20_DWLG_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:40 339220
wst04-VHDL20_DWLG_300400-2410300400-omedes--0.pdf 30-Oct-2024 05:59 339215
wst04-VHDL20_DWLG_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:40 339036
wst04-VHDL20_DWLH_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:40 337993
wst04-VHDL20_DWLH_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:40 339147
wst04-VHDL20_DWLH_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:59 339079
wst04-VHDL20_DWLH_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:40 340771
wst04-VHDL20_DWLH_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:40 340209
wst04-VHDL20_DWLH_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:40 339875
wst04-VHDL20_DWLH_300400-2410300400-omedes--0.pdf 30-Oct-2024 05:59 340128
wst04-VHDL20_DWLH_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:40 345194
wst04-VHDL20_DWLI_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:40 337297
wst04-VHDL20_DWLI_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:40 338290
wst04-VHDL20_DWLI_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:59 338052
wst04-VHDL20_DWLI_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:40 340844
wst04-VHDL20_DWLI_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:40 340473
wst04-VHDL20_DWLI_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:40 340441
wst04-VHDL20_DWLI_300400-2410300400-omedes--0.pdf 30-Oct-2024 05:59 340431
wst04-VHDL20_DWLI_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:40 344999
wst04-VHDL20_DWMG_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 540798
wst04-VHDL20_DWMG_290200-2410290200-omedes--0.pdf 29-Oct-2024 02:45 541597
wst04-VHDL20_DWMG_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:15 541496
wst04-VHDL20_DWMG_290800-2410290800-omedes--0.pdf 29-Oct-2024 08:45 541870
wst04-VHDL20_DWMG_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 541266
wst04-VHDL20_DWMG_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 541877
wst04-VHDL20_DWMG_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 541791
wst04-VHDL20_DWMG_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 546619
wst04-VHDL20_DWMO_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 485048
wst04-VHDL20_DWMO_290200-2410290200-omedes--0.pdf 29-Oct-2024 02:45 486410
wst04-VHDL20_DWMO_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:15 487611
wst04-VHDL20_DWMO_290800-2410290800-omedes--0.pdf 29-Oct-2024 08:45 487664
wst04-VHDL20_DWMO_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 486799
wst04-VHDL20_DWMO_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 487647
wst04-VHDL20_DWMO_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 487991
wst04-VHDL20_DWMO_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 496576
wst04-VHDL20_DWMP_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 544222
wst04-VHDL20_DWMP_290200-2410290200-omedes--0.pdf 29-Oct-2024 02:45 543855
wst04-VHDL20_DWMP_290400-2410290400-omedes--0.pdf 29-Oct-2024 05:15 544797
wst04-VHDL20_DWMP_290800-2410290800-omedes--0.pdf 29-Oct-2024 08:45 545248
wst04-VHDL20_DWMP_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 540145
wst04-VHDL20_DWMP_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 539615
wst04-VHDL20_DWMP_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 540467
wst04-VHDL20_DWMP_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 541619
wst04-VHDL20_DWPG_281800-2410281800-oflxs892--0..> 28-Oct-2024 19:45 340597
wst04-VHDL20_DWPG_290200-2410290200-oflxs892--0..> 29-Oct-2024 03:45 340991
wst04-VHDL20_DWPG_290400-2410290400-oflxs892--0..> 29-Oct-2024 06:00 340247
wst04-VHDL20_DWPG_290800-2410290800-oflxs892--0..> 29-Oct-2024 09:45 387291
wst04-VHDL20_DWPG_291800-2410291800-oflxs892--0..> 29-Oct-2024 19:45 342266
wst04-VHDL20_DWPG_300200-2410300200-oflxs892--0..> 30-Oct-2024 03:45 342612
wst04-VHDL20_DWPG_300400-2410300400-oflxs892--0..> 30-Oct-2024 06:00 341677
wst04-VHDL20_DWPG_300800-2410300800-oflxs892--0..> 30-Oct-2024 09:45 392645
wst04-VHDL20_DWPH_281800-2410281800-oflxs892--0..> 28-Oct-2024 19:45 292815
wst04-VHDL20_DWPH_290200-2410290200-oflxs892--0..> 29-Oct-2024 03:45 248665
wst04-VHDL20_DWPH_290400-2410290400-oflxs892--0..> 29-Oct-2024 06:00 249078
wst04-VHDL20_DWPH_290800-2410290800-oflxs892--0..> 29-Oct-2024 09:45 293546
wst04-VHDL20_DWPH_291800-2410291800-oflxs892--0..> 29-Oct-2024 19:45 292864
wst04-VHDL20_DWPH_300200-2410300200-oflxs892--0..> 30-Oct-2024 03:45 248162
wst04-VHDL20_DWPH_300400-2410300400-oflxs892--0..> 30-Oct-2024 06:00 248245
wst04-VHDL20_DWPH_300800-2410300800-oflxs892--0..> 30-Oct-2024 09:45 295928
wst04-VHDL20_DWSG_281800-2410281800-omedes--0.pdf 28-Oct-2024 19:45 348960
wst04-VHDL20_DWSG_290200-2410290200-omedes--0.pdf 29-Oct-2024 03:45 348803
wst04-VHDL20_DWSG_290400-2410290400-omedes--0.pdf 29-Oct-2024 06:15 349379
wst04-VHDL20_DWSG_290800-2410290800-omedes--0.pdf 29-Oct-2024 09:45 354139
wst04-VHDL20_DWSG_291800-2410291800-omedes--0.pdf 29-Oct-2024 19:45 354147
wst04-VHDL20_DWSG_300200-2410300200-omedes--0.pdf 30-Oct-2024 03:45 354139
wst04-VHDL20_DWSG_300400-2410300400-omedes--0.pdf 30-Oct-2024 06:15 354852
wst04-VHDL20_DWSG_300800-2410300800-omedes--0.pdf 30-Oct-2024 09:45 349537