Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Aug-2026 14:26:05 4104
FPDL13_DWMZ_120600 12-Aug-2026 12:35:27 5392
SXDL31_DWAV_110800 11-Aug-2026 07:00:34 6469
SXDL31_DWAV_111800 11-Aug-2026 16:33:37 2105
SXDL31_DWAV_120800 12-Aug-2026 07:45:16 10904
SXDL31_DWAV_LATEST 12-Aug-2026 07:45:16 10904
SXDL33_DWAV_110000 11-Aug-2026 10:24:56 17295
SXDL33_DWAV_120000 12-Aug-2026 10:38:24 7106
SXDL33_DWAV_LATEST 12-Aug-2026 10:38:24 7106
ber01-FWDL39_DWMS_111200-2608111200-dsw--0-ia5 11-Aug-2026 11:21:39 1473
ber01-FWDL39_DWMS_121200-2608121200-dsw--0-ia5 12-Aug-2026 10:51:39 1318
ber01-VHDL13_DWEG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:28:17 2575
ber01-VHDL13_DWEG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2632
ber01-VHDL13_DWEH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:28:17 2553
ber01-VHDL13_DWEH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2599
ber01-VHDL13_DWEI_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:28:13 2352
ber01-VHDL13_DWEI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2335
ber01-VHDL13_DWHG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:12 2550
ber01-VHDL13_DWHG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 2798
ber01-VHDL13_DWHH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:12 2979
ber01-VHDL13_DWHH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 2758
ber01-VHDL13_DWLG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2172
ber01-VHDL13_DWLG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2108
ber01-VHDL13_DWLH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2319
ber01-VHDL13_DWLH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2164
ber01-VHDL13_DWLI_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2170
ber01-VHDL13_DWLI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2147
ber01-VHDL13_DWMO_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2629
ber01-VHDL13_DWMO_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2307
ber01-VHDL13_DWMP_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2440
ber01-VHDL13_DWMP_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2040
ber01-VHDL13_DWOG_101700-2608101700-dsw--0-ia5 10-Aug-2026 18:00:04 2824
ber01-VHDL13_DWOG_101700_COR-2608101700-dsw--0-ia5 10-Aug-2026 19:57:23 2838
ber01-VHDL13_DWOG_110300-2608110300-dsw--0-ia5 11-Aug-2026 03:00:04 3112
ber01-VHDL13_DWOG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:12 2846
ber01-VHDL13_DWOG_111700-2608111700-dsw--0-ia5 11-Aug-2026 18:00:04 2108
ber01-VHDL13_DWOG_120300-2608120300-dsw--0-ia5 12-Aug-2026 03:00:04 2862
ber01-VHDL13_DWOG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2753
ber01-VHDL13_DWON_101632-2608101632-dsw--0-ia5 10-Aug-2026 16:32:15 2900
ber01-VHDL13_DWON_101758-2608101758-dsw--0-ia5 10-Aug-2026 17:58:09 2900
ber01-VHDL13_DWON_101956-2608101956-dsw--0-ia5 10-Aug-2026 19:56:59 2873
ber01-VHDL13_DWON_110206-2608110206-dsw--0-ia5 11-Aug-2026 02:07:04 3234
ber01-VHDL13_DWON_110526-2608110526-dsw--0-ia5 11-Aug-2026 05:26:39 3286
ber01-VHDL13_DWON_110553-2608110553-dsw--0-ia5 11-Aug-2026 05:53:23 3078
ber01-VHDL13_DWON_110801-2608110801-dsw--0-ia5 11-Aug-2026 08:01:58 3078
ber01-VHDL13_DWON_111506-2608111506-dsw--0-ia5 11-Aug-2026 15:06:59 2891
ber01-VHDL13_DWON_111701-2608111701-dsw--0-ia5 11-Aug-2026 17:01:43 2269
ber01-VHDL13_DWON_111826-2608111826-dsw--0-ia5 11-Aug-2026 18:26:19 2474
ber01-VHDL13_DWON_112016-2608112016-dsw--0-ia5 11-Aug-2026 20:16:23 2402
ber01-VHDL13_DWON_112129-2608112129-dsw--0-ia5 11-Aug-2026 21:29:34 2396
ber01-VHDL13_DWON_120003-2608120003-dsw--0-ia5 12-Aug-2026 00:03:07 3023
ber01-VHDL13_DWON_120135-2608120135-dsw--0-ia5 12-Aug-2026 01:35:53 2999
ber01-VHDL13_DWON_120249-2608120249-dsw--0-ia5 12-Aug-2026 02:50:46 2999
ber01-VHDL13_DWON_120309-2608120309-dsw--0-ia5 12-Aug-2026 03:10:12 2999
ber01-VHDL13_DWON_120527-2608120527-dsw--0-ia5 12-Aug-2026 05:28:04 3119
ber01-VHDL13_DWON_120622-2608120622-dsw--0-ia5 12-Aug-2026 06:22:18 3116
ber01-VHDL13_DWON_121445-2608121445-dsw--0-ia5 12-Aug-2026 14:45:46 2755
ber01-VHDL13_DWPG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2316
ber01-VHDL13_DWPG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2031
ber01-VHDL13_DWPH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2393
ber01-VHDL13_DWPH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2001
ber01-VHDL13_DWSG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 2003
ber01-VHDL13_DWSG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 1687
ber01-VHDL17_DWOG_111200-2608111200-dsw--0-ia5 11-Aug-2026 11:34:18 2930
ber01-VHDL17_DWOG_121200-2608121200-dsw--0-ia5 12-Aug-2026 11:02:48 2460
swis2-VHDL20_DWEG_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:13 997
swis2-VHDL20_DWEG_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 841
swis2-VHDL20_DWEG_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:01:18 1029
swis2-VHDL20_DWEG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 1155
swis2-VHDL20_DWEG_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1066
swis2-VHDL20_DWEG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 787
swis2-VHDL20_DWEG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 787
swis2-VHDL20_DWEG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1073
swis2-VHDL20_DWEH_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:13 1006
swis2-VHDL20_DWEH_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 862
swis2-VHDL20_DWEH_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:01:18 1050
swis2-VHDL20_DWEH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 1187
swis2-VHDL20_DWEH_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1148
swis2-VHDL20_DWEH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 741
swis2-VHDL20_DWEH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 741
swis2-VHDL20_DWEH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1157
swis2-VHDL20_DWEI_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:13 965
swis2-VHDL20_DWEI_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 835
swis2-VHDL20_DWEI_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:01:18 1023
swis2-VHDL20_DWEI_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 1186
swis2-VHDL20_DWEI_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1089
swis2-VHDL20_DWEI_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 810
swis2-VHDL20_DWEI_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 810
swis2-VHDL20_DWEI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1096
swis2-VHDL20_DWHG_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:45:06 1172
swis2-VHDL20_DWHG_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:45:49 1117
swis2-VHDL20_DWHG_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:18 1128
swis2-VHDL20_DWHG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:45:30 1054
swis2-VHDL20_DWHG_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:45:19 1119
swis2-VHDL20_DWHG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:45:06 962
swis2-VHDL20_DWHG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 959
swis2-VHDL20_DWHG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:45:23 1115
swis2-VHDL20_DWHH_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:45:06 1272
swis2-VHDL20_DWHH_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:45:49 1201
swis2-VHDL20_DWHH_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:18 1221
swis2-VHDL20_DWHH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:45:30 1277
swis2-VHDL20_DWHH_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:45:19 1123
swis2-VHDL20_DWHH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:45:06 962
swis2-VHDL20_DWHH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 962
swis2-VHDL20_DWHH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:45:23 1113
swis2-VHDL20_DWLG_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:31:09 1298
swis2-VHDL20_DWLG_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:34 1091
swis2-VHDL20_DWLG_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:14 1117
swis2-VHDL20_DWLG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:29 1214
swis2-VHDL20_DWLG_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:31:17 1013
swis2-VHDL20_DWLG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 929
swis2-VHDL20_DWLG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 952
swis2-VHDL20_DWLG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1040
swis2-VHDL20_DWLH_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:31:09 1292
swis2-VHDL20_DWLH_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:34 1114
swis2-VHDL20_DWLH_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:14 1120
swis2-VHDL20_DWLH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:29 1217
swis2-VHDL20_DWLH_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:31:17 1016
swis2-VHDL20_DWLH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 932
swis2-VHDL20_DWLH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 956
swis2-VHDL20_DWLH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1044
swis2-VHDL20_DWLI_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:31:09 1292
swis2-VHDL20_DWLI_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:34 1108
swis2-VHDL20_DWLI_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:14 1101
swis2-VHDL20_DWLI_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:29 1198
swis2-VHDL20_DWLI_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:31:17 1015
swis2-VHDL20_DWLI_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 931
swis2-VHDL20_DWLI_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 954
swis2-VHDL20_DWLI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1042
swis2-VHDL20_DWMO_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:11 1057
swis2-VHDL20_DWMO_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 923
swis2-VHDL20_DWMO_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:04 942
swis2-VHDL20_DWMO_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 997
swis2-VHDL20_DWMO_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1137
swis2-VHDL20_DWMO_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 874
swis2-VHDL20_DWMO_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:03 822
swis2-VHDL20_DWMO_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1070
swis2-VHDL20_DWMP_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:11 1315
swis2-VHDL20_DWMP_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 1148
swis2-VHDL20_DWMP_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:04 1080
swis2-VHDL20_DWMP_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 1212
swis2-VHDL20_DWMP_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1025
swis2-VHDL20_DWMP_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 872
swis2-VHDL20_DWMP_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:03 819
swis2-VHDL20_DWMP_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 982
swis2-VHDL20_DWPG_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:31:09 1316
swis2-VHDL20_DWPG_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:34 1163
swis2-VHDL20_DWPG_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:14 1140
swis2-VHDL20_DWPG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:29 1240
swis2-VHDL20_DWPG_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:31:17 1030
swis2-VHDL20_DWPG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 946
swis2-VHDL20_DWPG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 970
swis2-VHDL20_DWPG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1058
swis2-VHDL20_DWPH_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:31:09 1195
swis2-VHDL20_DWPH_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:34 997
swis2-VHDL20_DWPH_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:14 999
swis2-VHDL20_DWPH_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:29 1099
swis2-VHDL20_DWPH_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:31:17 784
swis2-VHDL20_DWPH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 697
swis2-VHDL20_DWPH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 720
swis2-VHDL20_DWPH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 811
swis2-VHDL20_DWSG_101800-2608101800-dsw--0-ia5 10-Aug-2026 18:30:11 620
swis2-VHDL20_DWSG_110200-2608110200-dsw--0-ia5 11-Aug-2026 02:30:13 978
swis2-VHDL20_DWSG_110400-2608110400-dsw--0-ia5 11-Aug-2026 05:00:18 1003
swis2-VHDL20_DWSG_110800-2608110800-dsw--0-ia5 11-Aug-2026 08:30:03 972
swis2-VHDL20_DWSG_111800-2608111800-dsw--0-ia5 11-Aug-2026 18:30:04 1018
swis2-VHDL20_DWSG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 793
swis2-VHDL20_DWSG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 719
swis2-VHDL20_DWSG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 725
wst04-VHDL20_DWEG_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:30:13 245373
wst04-VHDL20_DWEG_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:18 244654
wst04-VHDL20_DWEG_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:14 244020
wst04-VHDL20_DWEG_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:18 245077
wst04-VHDL20_DWEG_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:30:23 236226
wst04-VHDL20_DWEG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 235239
wst04-VHDL20_DWEG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 234750
wst04-VHDL20_DWEG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:14 236054
wst04-VHDL20_DWEH_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:30:13 238573
wst04-VHDL20_DWEH_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:18 238118
wst04-VHDL20_DWEH_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:14 237740
wst04-VHDL20_DWEH_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:18 238954
wst04-VHDL20_DWEH_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:30:14 234556
wst04-VHDL20_DWEH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 233404
wst04-VHDL20_DWEH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 233228
wst04-VHDL20_DWEH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:14 234987
wst04-VHDL20_DWEI_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:30:21 350166
wst04-VHDL20_DWEI_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:18 350060
wst04-VHDL20_DWEI_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:14 349164
wst04-VHDL20_DWEI_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:23 349731
wst04-VHDL20_DWEI_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:30:23 339156
wst04-VHDL20_DWEI_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:27 338719
wst04-VHDL20_DWEI_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:18 338148
wst04-VHDL20_DWEI_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 339683
wst04-VHDL20_DWHG_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:45:14 338414
wst04-VHDL20_DWHG_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:45:49 337637
wst04-VHDL20_DWHG_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:18 337442
wst04-VHDL20_DWHG_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:45:30 337094
wst04-VHDL20_DWHG_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:45:21 339040
wst04-VHDL20_DWHG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:45:14 338693
wst04-VHDL20_DWHG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:20 338474
wst04-VHDL20_DWHG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:45:24 339500
wst04-VHDL20_DWHH_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:45:14 328460
wst04-VHDL20_DWHH_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:45:49 327925
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wst04-VHDL20_DWHH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:45:14 326674
wst04-VHDL20_DWHH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:20 225315
wst04-VHDL20_DWHH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:45:24 326525
wst04-VHDL20_DWLG_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:31:31 335528
wst04-VHDL20_DWLG_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:34 335598
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wst04-VHDL20_DWLG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 332507
wst04-VHDL20_DWLG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 332361
wst04-VHDL20_DWLG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 332775
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wst04-VHDL20_DWLH_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:34 335247
wst04-VHDL20_DWLH_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:42 335064
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wst04-VHDL20_DWLH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 330807
wst04-VHDL20_DWLH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 330660
wst04-VHDL20_DWLH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 331072
wst04-VHDL20_DWLI_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:31:41 339383
wst04-VHDL20_DWLI_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:34 339174
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wst04-VHDL20_DWLI_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:44 383909
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wst04-VHDL20_DWLI_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 326254
wst04-VHDL20_DWLI_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 326107
wst04-VHDL20_DWLI_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 371107
wst04-VHDL20_DWMO_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:30:21 350114
wst04-VHDL20_DWMO_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:18 457923
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wst04-VHDL20_DWMO_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 443052
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wst04-VHDL20_DWMO_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 443250
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wst04-VHDL20_DWMP_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:20 574485
wst04-VHDL20_DWMP_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:18 574229
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wst04-VHDL20_DWMP_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:27 573767
wst04-VHDL20_DWMP_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:18 573606
wst04-VHDL20_DWMP_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:26 470739
wst04-VHDL20_DWPG_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:31:31 336688
wst04-VHDL20_DWPG_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:34 238637
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wst04-VHDL20_DWPG_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:31:37 337080
wst04-VHDL20_DWPG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 237565
wst04-VHDL20_DWPG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:34 336890
wst04-VHDL20_DWPG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:49 381868
wst04-VHDL20_DWPH_101800-2608101800-omedes--0.pdf 10-Aug-2026 18:31:31 239956
wst04-VHDL20_DWPH_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:34 239238
wst04-VHDL20_DWPH_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:34 239316
wst04-VHDL20_DWPH_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:44 239491
wst04-VHDL20_DWPH_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:31:37 237960
wst04-VHDL20_DWPH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 237910
wst04-VHDL20_DWPH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:34 237679
wst04-VHDL20_DWPH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 238142
wst04-VHDL20_DWSG_110200-2608110200-omedes--0.pdf 11-Aug-2026 02:30:20 349071
wst04-VHDL20_DWSG_110400-2608110400-omedes--0.pdf 11-Aug-2026 05:00:14 348861
wst04-VHDL20_DWSG_110800-2608110800-omedes--0.pdf 11-Aug-2026 08:30:23 348905
wst04-VHDL20_DWSG_111800-2608111800-omedes--0.pdf 11-Aug-2026 18:30:14 345818
wst04-VHDL20_DWSG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 344757
wst04-VHDL20_DWSG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 344476
wst04-VHDL20_DWSG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 344369