Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_290600 29-Jan-2026 13:29:24 9455
FPDL13_DWMZ_300600 30-Jan-2026 16:05:55 6198
SXDL31_DWAV_290800 29-Jan-2026 08:41:34 8096
SXDL31_DWAV_291800 29-Jan-2026 17:03:09 6996
SXDL31_DWAV_300800 30-Jan-2026 09:14:24 13765
SXDL31_DWAV_301800 30-Jan-2026 18:19:33 7133
SXDL31_DWAV_LATEST 30-Jan-2026 18:19:33 7133
SXDL33_DWAV_290000 29-Jan-2026 11:00:09 8763
SXDL33_DWAV_300000 30-Jan-2026 10:43:28 10467
SXDL33_DWAV_LATEST 30-Jan-2026 10:43:28 10467
ber01-FWDL39_DWMS_291230-2601291230-dsw--0-ia5 29-Jan-2026 12:26:52 1787
ber01-FWDL39_DWMS_301230-2601301230-dsw--0-ia5 30-Jan-2026 12:16:21 1437
ber01-VHDL13_DWEH_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:17 3736
ber01-VHDL13_DWEH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:17 3785
ber01-VHDL13_DWEH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:28:17 3347
ber01-VHDL13_DWEH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:11 3468
ber01-VHDL13_DWEH_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:12 3436
ber01-VHDL13_DWEH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:17 3412
ber01-VHDL13_DWEH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:17 3148
ber01-VHDL13_DWEH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 3059
ber01-VHDL13_DWHG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4454
ber01-VHDL13_DWHG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 4565
ber01-VHDL13_DWHG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 3739
ber01-VHDL13_DWHG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3585
ber01-VHDL13_DWHG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:08 3709
ber01-VHDL13_DWHG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3876
ber01-VHDL13_DWHG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:07 3698
ber01-VHDL13_DWHG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 4089
ber01-VHDL13_DWHH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 3910
ber01-VHDL13_DWHH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 4145
ber01-VHDL13_DWHH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 3689
ber01-VHDL13_DWHH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3859
ber01-VHDL13_DWHH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3858
ber01-VHDL13_DWHH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3895
ber01-VHDL13_DWHH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:07 3252
ber01-VHDL13_DWHH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3737
ber01-VHDL13_DWLG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2418
ber01-VHDL13_DWLG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2441
ber01-VHDL13_DWLG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 1995
ber01-VHDL13_DWLG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 1982
ber01-VHDL13_DWLG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1984
ber01-VHDL13_DWLG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2254
ber01-VHDL13_DWLG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2643
ber01-VHDL13_DWLG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2741
ber01-VHDL13_DWLH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2244
ber01-VHDL13_DWLH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2271
ber01-VHDL13_DWLH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 1890
ber01-VHDL13_DWLH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 1928
ber01-VHDL13_DWLH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1943
ber01-VHDL13_DWLH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2017
ber01-VHDL13_DWLH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2275
ber01-VHDL13_DWLH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2365
ber01-VHDL13_DWLI_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2292
ber01-VHDL13_DWLI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2234
ber01-VHDL13_DWLI_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 1872
ber01-VHDL13_DWLI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:00 1838
ber01-VHDL13_DWLI_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 1866
ber01-VHDL13_DWLI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 1936
ber01-VHDL13_DWLI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2307
ber01-VHDL13_DWLI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2389
ber01-VHDL13_DWMG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3383
ber01-VHDL13_DWMG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3564
ber01-VHDL13_DWMG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:03 3108
ber01-VHDL13_DWMG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3506
ber01-VHDL13_DWMG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3413
ber01-VHDL13_DWMG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3358
ber01-VHDL13_DWMG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3289
ber01-VHDL13_DWMG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3204
ber01-VHDL13_DWMO_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3277
ber01-VHDL13_DWMO_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3438
ber01-VHDL13_DWMO_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:03 2709
ber01-VHDL13_DWMO_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3247
ber01-VHDL13_DWMO_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3173
ber01-VHDL13_DWMO_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3074
ber01-VHDL13_DWMO_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3160
ber01-VHDL13_DWMO_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3111
ber01-VHDL13_DWMP_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3160
ber01-VHDL13_DWMP_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3519
ber01-VHDL13_DWMP_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:03 2911
ber01-VHDL13_DWMP_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3271
ber01-VHDL13_DWMP_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:02 3267
ber01-VHDL13_DWMP_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:06 3455
ber01-VHDL13_DWMP_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3162
ber01-VHDL13_DWMP_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3315
ber01-VHDL13_DWOG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:01 5261
ber01-VHDL13_DWOG_291700-2601291700-dsw--0-ia5 29-Jan-2026 19:00:08 5093
ber01-VHDL13_DWOG_300300-2601300300-dsw--0-ia5 30-Jan-2026 04:00:05 5457
ber01-VHDL13_DWOG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 5542
ber01-VHDL13_DWOG_301700-2601301700-dsw--0-ia5 30-Jan-2026 19:00:01 4748
ber01-VHDL13_DWOG_310300-2601310300-dsw--0-ia5 31-Jan-2026 04:00:01 5605
ber01-VHDL13_DWOH_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:11 3319
ber01-VHDL13_DWOH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:11 3456
ber01-VHDL13_DWOH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:28:11 3040
ber01-VHDL13_DWOH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:11 3709
ber01-VHDL13_DWOH_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:12 3778
ber01-VHDL13_DWOH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:17 3675
ber01-VHDL13_DWOH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:17 3369
ber01-VHDL13_DWOH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 3220
ber01-VHDL13_DWOI_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:17 3090
ber01-VHDL13_DWOI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:11 3169
ber01-VHDL13_DWOI_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:28:11 2677
ber01-VHDL13_DWOI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:28:15 3306
ber01-VHDL13_DWOI_300400-2601300400-dsw--0-ia5 30-Jan-2026 05:58:18 3405
ber01-VHDL13_DWOI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:28:11 3225
ber01-VHDL13_DWOI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:28:11 2868
ber01-VHDL13_DWOI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:28:11 2652
ber01-VHDL13_DWON_290625-2601290625-dsw--0-ia5 29-Jan-2026 06:25:47 4430
ber01-VHDL13_DWON_290718-2601290718-dsw--0-ia5 29-Jan-2026 07:18:10 4430
ber01-VHDL13_DWON_290916-2601290916-dsw--0-ia5 29-Jan-2026 09:16:58 4430
ber01-VHDL13_DWON_290921-2601290921-dsw--0-ia5 29-Jan-2026 09:21:06 4430
ber01-VHDL13_DWON_291548-2601291548-dsw--0-ia5 29-Jan-2026 15:48:57 4050
ber01-VHDL13_DWON_291822-2601291822-dsw--0-ia5 29-Jan-2026 18:22:47 3613
ber01-VHDL13_DWON_292233-2601292233-dsw--0-ia5 29-Jan-2026 22:33:52 3613
ber01-VHDL13_DWON_292342-2601292342-dsw--0-ia5 29-Jan-2026 23:42:52 4195
ber01-VHDL13_DWON_292352-2601292352-dsw--0-ia5 29-Jan-2026 23:53:02 4195
ber01-VHDL13_DWON_292353-2601292353-dsw--0-ia5 29-Jan-2026 23:53:22 4195
ber01-VHDL13_DWON_300629-2601300629-dsw--0-ia5 30-Jan-2026 06:29:22 5077
ber01-VHDL13_DWON_300723-2601300723-dsw--0-ia5 30-Jan-2026 07:24:01 5127
ber01-VHDL13_DWON_301544-2601301544-dsw--0-ia5 30-Jan-2026 15:44:27 4595
ber01-VHDL13_DWON_301844-2601301844-dsw--0-ia5 30-Jan-2026 18:44:16 4033
ber01-VHDL13_DWON_302256-2601302256-dsw--0-ia5 30-Jan-2026 22:56:31 4097
ber01-VHDL13_DWON_310152-2601310152-dsw--0-ia5 31-Jan-2026 01:52:57 4431
ber01-VHDL13_DWON_310422-2601310422-dsw--0-ia5 31-Jan-2026 04:22:47 4431
ber01-VHDL13_DWPG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2363
ber01-VHDL13_DWPG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2506
ber01-VHDL13_DWPG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 2012
ber01-VHDL13_DWPG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 2078
ber01-VHDL13_DWPG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 2212
ber01-VHDL13_DWPG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2372
ber01-VHDL13_DWPG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2113
ber01-VHDL13_DWPG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 2522
ber01-VHDL13_DWPH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2491
ber01-VHDL13_DWPH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2727
ber01-VHDL13_DWPH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:10 2300
ber01-VHDL13_DWPH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 2547
ber01-VHDL13_DWPH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 2687
ber01-VHDL13_DWPH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 2770
ber01-VHDL13_DWPH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 2642
ber01-VHDL13_DWPH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3079
ber01-VHDL13_DWSG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 3449
ber01-VHDL13_DWSG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:01 3818
ber01-VHDL13_DWSG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:30:03 3531
ber01-VHDL13_DWSG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:30:05 3929
ber01-VHDL13_DWSG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3939
ber01-VHDL13_DWSG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:30:03 3704
ber01-VHDL13_DWSG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:30:03 3223
ber01-VHDL13_DWSG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:30:13 3358
ber01-VHDL17_DWOG_291200-2601291200-dsw--0-ia5 29-Jan-2026 13:04:22 3279
ber01-VHDL17_DWOG_301200-2601301200-dsw--0-ia5 30-Jan-2026 12:29:26 3593
swis2-VHDL20_DWEG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3717
swis2-VHDL20_DWEG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4058
swis2-VHDL20_DWEG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3580
swis2-VHDL20_DWEG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4199
swis2-VHDL20_DWEG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 4156
swis2-VHDL20_DWEG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4290
swis2-VHDL20_DWEG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3793
swis2-VHDL20_DWEG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3533
swis2-VHDL20_DWEH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 4131
swis2-VHDL20_DWEH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4402
swis2-VHDL20_DWEH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3927
swis2-VHDL20_DWEH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4015
swis2-VHDL20_DWEH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3826
swis2-VHDL20_DWEH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4039
swis2-VHDL20_DWEH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3585
swis2-VHDL20_DWEH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3412
swis2-VHDL20_DWEI_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3491
swis2-VHDL20_DWEI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 3804
swis2-VHDL20_DWEI_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3241
swis2-VHDL20_DWEI_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3811
swis2-VHDL20_DWEI_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 3814
swis2-VHDL20_DWEI_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3931
swis2-VHDL20_DWEI_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3302
swis2-VHDL20_DWEI_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2985
swis2-VHDL20_DWHG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4637
swis2-VHDL20_DWHG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 5432
swis2-VHDL20_DWHG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3922
swis2-VHDL20_DWHG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3771
swis2-VHDL20_DWHG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 3892
swis2-VHDL20_DWHG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4842
swis2-VHDL20_DWHG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3881
swis2-VHDL20_DWHG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:06 4275
swis2-VHDL20_DWHH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4096
swis2-VHDL20_DWHH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 5050
swis2-VHDL20_DWHH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3875
swis2-VHDL20_DWHH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 4045
swis2-VHDL20_DWHH_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:06 4044
swis2-VHDL20_DWHH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4691
swis2-VHDL20_DWHH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3438
swis2-VHDL20_DWHH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:06 3923
swis2-VHDL20_DWLG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2820
swis2-VHDL20_DWLG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 3034
swis2-VHDL20_DWLG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 2397
swis2-VHDL20_DWLG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2384
swis2-VHDL20_DWLG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2371
swis2-VHDL20_DWLG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2848
swis2-VHDL20_DWLG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3061
swis2-VHDL20_DWLG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3159
swis2-VHDL20_DWLH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2654
swis2-VHDL20_DWLH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 2876
swis2-VHDL20_DWLH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 2300
swis2-VHDL20_DWLH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2338
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swis2-VHDL20_DWLH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2606
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swis2-VHDL20_DWMG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3800
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swis2-VHDL20_DWMG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:06 3528
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swis2-VHDL20_DWMO_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3698
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swis2-VHDL20_DWMO_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3764
swis2-VHDL20_DWMO_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3631
swis2-VHDL20_DWMO_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3632
swis2-VHDL20_DWMP_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3559
swis2-VHDL20_DWMP_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 4159
swis2-VHDL20_DWMP_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:06 3322
swis2-VHDL20_DWMP_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 3694
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swis2-VHDL20_DWMP_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 4145
swis2-VHDL20_DWMP_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3747
swis2-VHDL20_DWMP_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3835
swis2-VHDL20_DWPG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2891
swis2-VHDL20_DWPG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 3255
swis2-VHDL20_DWPG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 2761
swis2-VHDL20_DWPG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 2614
swis2-VHDL20_DWPG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:00:12 2626
swis2-VHDL20_DWPG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 2961
swis2-VHDL20_DWPG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 2702
swis2-VHDL20_DWPG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 2941
swis2-VHDL20_DWPH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2977
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swis2-VHDL20_DWPH_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3036
swis2-VHDL20_DWPH_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:06 3038
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swis2-VHDL20_DWPH_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:07 3392
swis2-VHDL20_DWPH_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3263
swis2-VHDL20_DWPH_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3528
swis2-VHDL20_DWSG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:06 3858
swis2-VHDL20_DWSG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4538
swis2-VHDL20_DWSG_291300-2601291300-dsw--0-ia5 29-Jan-2026 14:45:12 4266
swis2-VHDL20_DWSG_291800-2601291800-dsw--0-ia5 29-Jan-2026 19:45:04 3949
swis2-VHDL20_DWSG_300200-2601300200-dsw--0-ia5 30-Jan-2026 03:45:02 4326
swis2-VHDL20_DWSG_300400-2601300400-dsw--0-ia5 30-Jan-2026 06:15:01 4373
swis2-VHDL20_DWSG_300800-2601300800-dsw--0-ia5 30-Jan-2026 09:45:01 4361
swis2-VHDL20_DWSG_301300-2601301300-dsw--0-ia5 30-Jan-2026 14:45:07 4172
swis2-VHDL20_DWSG_301800-2601301800-dsw--0-ia5 30-Jan-2026 19:45:03 3696
swis2-VHDL20_DWSG_310200-2601310200-dsw--0-ia5 31-Jan-2026 03:45:02 3755
wst04-VHDL20_DWEG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:23 225222
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wst04-VHDL20_DWEG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 230142
wst04-VHDL20_DWEH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 229209
wst04-VHDL20_DWEH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 233039
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wst04-VHDL20_DWEH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:11 229447
wst04-VHDL20_DWEH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 228769
wst04-VHDL20_DWEH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 229738
wst04-VHDL20_DWEI_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:23 313308
wst04-VHDL20_DWEI_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 326233
wst04-VHDL20_DWEI_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:13 325258
wst04-VHDL20_DWEI_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 326731
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wst04-VHDL20_DWEI_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 320248
wst04-VHDL20_DWEI_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 320109
wst04-VHDL20_DWHG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:12 301018
wst04-VHDL20_DWHG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 297911
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wst04-VHDL20_DWHG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 297880
wst04-VHDL20_DWHH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:16 297566
wst04-VHDL20_DWHH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 298303
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wst04-VHDL20_DWHH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 296915
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wst04-VHDL20_DWHH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 300376
wst04-VHDL20_DWHH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 298411
wst04-VHDL20_DWHH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:17 298885
wst04-VHDL20_DWLG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 292471
wst04-VHDL20_DWLG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 297582
wst04-VHDL20_DWLG_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:21 296543
wst04-VHDL20_DWLG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 296505
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wst04-VHDL20_DWLG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 292960
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wst04-VHDL20_DWLG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 292826
wst04-VHDL20_DWLH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 294969
wst04-VHDL20_DWLH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 290755
wst04-VHDL20_DWLH_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:21 290182
wst04-VHDL20_DWLH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 289636
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wst04-VHDL20_DWLH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 291111
wst04-VHDL20_DWLH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 291035
wst04-VHDL20_DWLH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 290914
wst04-VHDL20_DWLI_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 301459
wst04-VHDL20_DWLI_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 296396
wst04-VHDL20_DWLI_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:21 295418
wst04-VHDL20_DWLI_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 294772
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wst04-VHDL20_DWLI_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 297991
wst04-VHDL20_DWLI_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 298062
wst04-VHDL20_DWLI_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 297951
wst04-VHDL20_DWMG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 512542
wst04-VHDL20_DWMG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:22 523663
wst04-VHDL20_DWMG_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:17 521625
wst04-VHDL20_DWMG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 521699
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wst04-VHDL20_DWMG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 518998
wst04-VHDL20_DWMG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 519143
wst04-VHDL20_DWMG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 518768
wst04-VHDL20_DWMO_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 409751
wst04-VHDL20_DWMO_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 415140
wst04-VHDL20_DWMO_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:17 413437
wst04-VHDL20_DWMO_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 413620
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wst04-VHDL20_DWMO_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:17 412895
wst04-VHDL20_DWMO_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 412397
wst04-VHDL20_DWMO_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 412555
wst04-VHDL20_DWMP_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 549679
wst04-VHDL20_DWMP_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:22 559982
wst04-VHDL20_DWMP_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:17 557536
wst04-VHDL20_DWMP_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:17 556736
wst04-VHDL20_DWMP_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:17 557875
wst04-VHDL20_DWMP_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 553312
wst04-VHDL20_DWMP_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:16 552371
wst04-VHDL20_DWMP_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:12 550392
wst04-VHDL20_DWPG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:32 304404
wst04-VHDL20_DWPG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:32 346850
wst04-VHDL20_DWPG_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:27 300974
wst04-VHDL20_DWPG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:27 300711
wst04-VHDL20_DWPG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:32 300334
wst04-VHDL20_DWPG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:28 349120
wst04-VHDL20_DWPG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:26 304321
wst04-VHDL20_DWPG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:27 304360
wst04-VHDL20_DWPH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:32 222817
wst04-VHDL20_DWPH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 265305
wst04-VHDL20_DWPH_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:21 264246
wst04-VHDL20_DWPH_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:21 218852
wst04-VHDL20_DWPH_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:00:32 218762
wst04-VHDL20_DWPH_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:22 267292
wst04-VHDL20_DWPH_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:22 266477
wst04-VHDL20_DWPH_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:21 222316
wst04-VHDL20_DWSG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:12 329277
wst04-VHDL20_DWSG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:12 343401
wst04-VHDL20_DWSG_291300-2601291300-omedes--0.pdf 29-Jan-2026 14:45:12 343298
wst04-VHDL20_DWSG_291800-2601291800-omedes--0.pdf 29-Jan-2026 19:45:11 342634
wst04-VHDL20_DWSG_300200-2601300200-omedes--0.pdf 30-Jan-2026 03:45:13 342846
wst04-VHDL20_DWSG_300400-2601300400-omedes--0.pdf 30-Jan-2026 06:15:11 342946
wst04-VHDL20_DWSG_300800-2601300800-omedes--0.pdf 30-Jan-2026 09:45:11 341164
wst04-VHDL20_DWSG_301300-2601301300-omedes--0.pdf 30-Jan-2026 14:45:11 341137
wst04-VHDL20_DWSG_301800-2601301800-omedes--0.pdf 30-Jan-2026 19:45:12 340655
wst04-VHDL20_DWSG_310200-2601310200-omedes--0.pdf 31-Jan-2026 03:45:15 340180