Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Jun-2026 07:40:34 2508
FPDL13_DWMZ_040600 04-Jun-2026 13:46:39 4085
SXDL31_DWAV_021800 02-Jun-2026 15:33:43 8654
SXDL31_DWAV_030800 03-Jun-2026 08:05:19 11952
SXDL31_DWAV_031800 03-Jun-2026 17:01:46 13100
SXDL31_DWAV_040800 04-Jun-2026 07:42:14 8344
SXDL31_DWAV_LATEST 04-Jun-2026 07:42:14 8344
SXDL33_DWAV_030000 03-Jun-2026 09:58:49 7947
SXDL33_DWAV_040000 04-Jun-2026 10:14:04 7985
SXDL33_DWAV_LATEST 04-Jun-2026 10:14:04 7985
ber01-FWDL39_DWMS_031230-2606031230-dsw--0-ia5 03-Jun-2026 12:01:02 2223
ber01-FWDL39_DWMS_041200-2606041200-dsw--0-ia5 04-Jun-2026 10:27:06 2081
ber01-VHDL13_DWEG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:28:16 3493
ber01-VHDL13_DWEG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:12 4178
ber01-VHDL13_DWEH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:28:16 3773
ber01-VHDL13_DWEH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:12 4284
ber01-VHDL13_DWEI_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:28:23 4108
ber01-VHDL13_DWEI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:18 4155
ber01-VHDL13_DWHG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:07 3648
ber01-VHDL13_DWHG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3536
ber01-VHDL13_DWHG_040800_COR-2606040800-dsw--0-ia5 04-Jun-2026 10:49:56 3543
ber01-VHDL13_DWHH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:07 3438
ber01-VHDL13_DWHH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3435
ber01-VHDL13_DWLG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2695
ber01-VHDL13_DWLG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2892
ber01-VHDL13_DWLH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 3036
ber01-VHDL13_DWLH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3202
ber01-VHDL13_DWLI_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2931
ber01-VHDL13_DWLI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3171
ber01-VHDL13_DWMO_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 3668
ber01-VHDL13_DWMO_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3637
ber01-VHDL13_DWMP_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 3849
ber01-VHDL13_DWMP_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3600
ber01-VHDL13_DWOG_021700-2606021700-dsw--0-ia5 02-Jun-2026 18:00:06 3607
ber01-VHDL13_DWOG_021700_COR-2606021700-dsw--0-ia5 02-Jun-2026 19:54:51 4005
ber01-VHDL13_DWOG_030300-2606030300-dsw--0-ia5 03-Jun-2026 03:00:01 4613
ber01-VHDL13_DWOG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:57:26 4429
ber01-VHDL13_DWOG_031700-2606031700-dsw--0-ia5 03-Jun-2026 18:00:02 4472
ber01-VHDL13_DWOG_040300-2606040300-dsw--0-ia5 04-Jun-2026 03:00:02 4201
ber01-VHDL13_DWOG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 4644
ber01-VHDL13_DWON_021707-2606021707-dsw--0-ia5 02-Jun-2026 17:07:26 2790
ber01-VHDL13_DWON_021954-2606021954-dsw--0-ia5 02-Jun-2026 19:54:27 3733
ber01-VHDL13_DWON_030144-2606030144-dsw--0-ia5 03-Jun-2026 01:44:12 4392
ber01-VHDL13_DWON_030529-2606030529-dsw--0-ia5 03-Jun-2026 05:29:22 3883
ber01-VHDL13_DWON_030603-2606030603-dsw--0-ia5 03-Jun-2026 06:03:12 3940
ber01-VHDL13_DWON_030618-2606030618-dsw--0-ia5 03-Jun-2026 06:18:22 3940
ber01-VHDL13_DWON_030627-2606030627-dsw--0-ia5 03-Jun-2026 06:27:15 3940
ber01-VHDL13_DWON_030639-2606030639-dsw--0-ia5 03-Jun-2026 06:39:42 3981
ber01-VHDL13_DWON_030805-2606030805-dsw--0-ia5 03-Jun-2026 08:05:31 3981
ber01-VHDL13_DWON_030854-2606030854-dsw--0-ia5 03-Jun-2026 08:54:11 3981
ber01-VHDL13_DWON_030855-2606030855-dsw--0-ia5 03-Jun-2026 08:55:57 3981
ber01-VHDL13_DWON_031457-2606031457-dsw--0-ia5 03-Jun-2026 14:57:17 3867
ber01-VHDL13_DWON_031705-2606031705-dsw--0-ia5 03-Jun-2026 17:05:51 3373
ber01-VHDL13_DWON_032017-2606032017-dsw--0-ia5 03-Jun-2026 20:17:32 2994
ber01-VHDL13_DWON_040008-2606040008-dsw--0-ia5 04-Jun-2026 00:08:48 2747
ber01-VHDL13_DWON_040239-2606040239-dsw--0-ia5 04-Jun-2026 02:39:41 2747
ber01-VHDL13_DWON_040527-2606040527-dsw--0-ia5 04-Jun-2026 05:27:21 3154
ber01-VHDL13_DWON_040558-2606040558-dsw--0-ia5 04-Jun-2026 05:58:47 3322
ber01-VHDL13_DWON_040806-2606040806-dsw--0-ia5 04-Jun-2026 08:06:47 3415
ber01-VHDL13_DWON_040935-2606040935-dsw--0-ia5 04-Jun-2026 09:35:26 3415
ber01-VHDL13_DWON_041457-2606041457-dsw--0-ia5 04-Jun-2026 14:57:42 3469
ber01-VHDL13_DWPG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2906
ber01-VHDL13_DWPG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3023
ber01-VHDL13_DWPH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2959
ber01-VHDL13_DWPH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3074
ber01-VHDL13_DWSG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 3333
ber01-VHDL13_DWSG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3861
ber01-VHDL17_DWOG_031200-2606031200-dsw--0-ia5 03-Jun-2026 11:25:51 2859
ber01-VHDL17_DWOG_041200-2606041200-dsw--0-ia5 04-Jun-2026 11:55:21 3105
swis2-VHDL20_DWEG_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:01 1717
swis2-VHDL20_DWEG_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1610
swis2-VHDL20_DWEG_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:01:17 1614
swis2-VHDL20_DWEG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2057
swis2-VHDL20_DWEG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1903
swis2-VHDL20_DWEG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1803
swis2-VHDL20_DWEG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1927
swis2-VHDL20_DWEG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2192
swis2-VHDL20_DWEH_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:01 1944
swis2-VHDL20_DWEH_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1926
swis2-VHDL20_DWEH_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:01:17 1780
swis2-VHDL20_DWEH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2253
swis2-VHDL20_DWEH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2108
swis2-VHDL20_DWEH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1827
swis2-VHDL20_DWEH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1931
swis2-VHDL20_DWEH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2180
swis2-VHDL20_DWEI_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:01 2038
swis2-VHDL20_DWEI_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1994
swis2-VHDL20_DWEI_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:01:17 1995
swis2-VHDL20_DWEI_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 2480
swis2-VHDL20_DWEI_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2180
swis2-VHDL20_DWEI_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1846
swis2-VHDL20_DWEI_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1924
swis2-VHDL20_DWEI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2189
swis2-VHDL20_DWHG_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:45:01 2292
swis2-VHDL20_DWHG_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:45:24 1679
swis2-VHDL20_DWHG_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:16 1676
swis2-VHDL20_DWHG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:45:01 2389
swis2-VHDL20_DWHG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:45:02 2383
swis2-VHDL20_DWHG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:46:28 2063
swis2-VHDL20_DWHG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 2057
swis2-VHDL20_DWHG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:45:08 2115
swis2-VHDL20_DWHG_040800_COR-2606040800-dsw--0-ia5 04-Jun-2026 10:50:57 2122
swis2-VHDL20_DWHH_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:45:01 1918
swis2-VHDL20_DWHH_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:45:24 1475
swis2-VHDL20_DWHH_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:16 1475
swis2-VHDL20_DWHH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:45:01 2158
swis2-VHDL20_DWHH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:45:02 2350
swis2-VHDL20_DWHH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:46:28 2063
swis2-VHDL20_DWHH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 2083
swis2-VHDL20_DWHH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:45:08 2120
swis2-VHDL20_DWLG_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:31:01 1518
swis2-VHDL20_DWLG_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:22 1066
swis2-VHDL20_DWLG_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:12 1130
swis2-VHDL20_DWLG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:22 1395
swis2-VHDL20_DWLG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1194
swis2-VHDL20_DWLG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 997
swis2-VHDL20_DWLG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1212
swis2-VHDL20_DWLG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1626
swis2-VHDL20_DWLH_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:31:01 1488
swis2-VHDL20_DWLH_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:22 1052
swis2-VHDL20_DWLH_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:12 1114
swis2-VHDL20_DWLH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:22 1878
swis2-VHDL20_DWLH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1578
swis2-VHDL20_DWLH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1494
swis2-VHDL20_DWLH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1608
swis2-VHDL20_DWLH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1912
swis2-VHDL20_DWLI_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:31:01 1472
swis2-VHDL20_DWLI_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:22 1045
swis2-VHDL20_DWLI_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:12 1109
swis2-VHDL20_DWLI_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:22 1796
swis2-VHDL20_DWLI_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1512
swis2-VHDL20_DWLI_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1458
swis2-VHDL20_DWLI_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1571
swis2-VHDL20_DWLI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1871
swis2-VHDL20_DWMO_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:01 1684
swis2-VHDL20_DWMO_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1191
swis2-VHDL20_DWMO_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:02 1120
swis2-VHDL20_DWMO_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 1592
swis2-VHDL20_DWMO_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1638
swis2-VHDL20_DWMO_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1562
swis2-VHDL20_DWMO_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:06 1500
swis2-VHDL20_DWMO_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2052
swis2-VHDL20_DWMP_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:07 1975
swis2-VHDL20_DWMP_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1393
swis2-VHDL20_DWMP_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:02 1331
swis2-VHDL20_DWMP_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 1791
swis2-VHDL20_DWMP_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1922
swis2-VHDL20_DWMP_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1705
swis2-VHDL20_DWMP_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:06 1660
swis2-VHDL20_DWMP_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2039
swis2-VHDL20_DWPG_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:31:01 1292
swis2-VHDL20_DWPG_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:22 1028
swis2-VHDL20_DWPG_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:12 1090
swis2-VHDL20_DWPG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:22 1724
swis2-VHDL20_DWPG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1507
swis2-VHDL20_DWPG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1323
swis2-VHDL20_DWPG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1483
swis2-VHDL20_DWPG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1829
swis2-VHDL20_DWPH_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:31:01 1474
swis2-VHDL20_DWPH_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:22 1066
swis2-VHDL20_DWPH_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:12 1241
swis2-VHDL20_DWPH_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:22 1776
swis2-VHDL20_DWPH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1492
swis2-VHDL20_DWPH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1335
swis2-VHDL20_DWPH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1487
swis2-VHDL20_DWPH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1833
swis2-VHDL20_DWSG_021800-2606021800-dsw--0-ia5 02-Jun-2026 18:30:01 1471
swis2-VHDL20_DWSG_030200-2606030200-dsw--0-ia5 03-Jun-2026 02:30:06 1417
swis2-VHDL20_DWSG_030400-2606030400-dsw--0-ia5 03-Jun-2026 05:00:16 1398
swis2-VHDL20_DWSG_030800-2606030800-dsw--0-ia5 03-Jun-2026 08:30:01 1423
swis2-VHDL20_DWSG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2178
swis2-VHDL20_DWSG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1988
swis2-VHDL20_DWSG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 1754
swis2-VHDL20_DWSG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2182
wst04-VHDL20_DWEG_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:11 245718
wst04-VHDL20_DWEG_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:12 245221
wst04-VHDL20_DWEG_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:12 245410
wst04-VHDL20_DWEG_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:12 246540
wst04-VHDL20_DWEG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 240189
wst04-VHDL20_DWEG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 239446
wst04-VHDL20_DWEG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 239557
wst04-VHDL20_DWEG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 240603
wst04-VHDL20_DWEH_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:11 243190
wst04-VHDL20_DWEH_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:12 243339
wst04-VHDL20_DWEH_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:12 243322
wst04-VHDL20_DWEH_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:12 244475
wst04-VHDL20_DWEH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:12 242937
wst04-VHDL20_DWEH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 242396
wst04-VHDL20_DWEH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 242811
wst04-VHDL20_DWEH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 243862
wst04-VHDL20_DWEI_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:17 351354
wst04-VHDL20_DWEI_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:16 351493
wst04-VHDL20_DWEI_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:16 351611
wst04-VHDL20_DWEI_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:16 352266
wst04-VHDL20_DWEI_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 342566
wst04-VHDL20_DWEI_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 342205
wst04-VHDL20_DWEI_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 342293
wst04-VHDL20_DWEI_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 342802
wst04-VHDL20_DWHG_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:45:12 361120
wst04-VHDL20_DWHG_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:45:24 360166
wst04-VHDL20_DWHG_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:22 359955
wst04-VHDL20_DWHG_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:45:12 361934
wst04-VHDL20_DWHG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:45:12 356650
wst04-VHDL20_DWHG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:46:28 355030
wst04-VHDL20_DWHG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:22 355033
wst04-VHDL20_DWHG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:45:28 356430
wst04-VHDL20_DWHH_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:45:12 347809
wst04-VHDL20_DWHH_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:45:24 346738
wst04-VHDL20_DWHH_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:16 233387
wst04-VHDL20_DWHH_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:45:12 348317
wst04-VHDL20_DWHH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:45:12 343636
wst04-VHDL20_DWHH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:46:28 343453
wst04-VHDL20_DWHH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 236522
wst04-VHDL20_DWHH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:45:28 343844
wst04-VHDL20_DWLG_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:31:24 349927
wst04-VHDL20_DWLG_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:22 349419
wst04-VHDL20_DWLG_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:42 349287
wst04-VHDL20_DWLG_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:41 349604
wst04-VHDL20_DWLG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:28 349621
wst04-VHDL20_DWLG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 348724
wst04-VHDL20_DWLG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 349680
wst04-VHDL20_DWLG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 350147
wst04-VHDL20_DWLH_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:31:29 354539
wst04-VHDL20_DWLH_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:22 354028
wst04-VHDL20_DWLH_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:42 353840
wst04-VHDL20_DWLH_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:41 355505
wst04-VHDL20_DWLH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 343394
wst04-VHDL20_DWLH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 342503
wst04-VHDL20_DWLH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 343280
wst04-VHDL20_DWLH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 344543
wst04-VHDL20_DWLI_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:31:24 348251
wst04-VHDL20_DWLI_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:22 347769
wst04-VHDL20_DWLI_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:42 347603
wst04-VHDL20_DWLI_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:41 393782
wst04-VHDL20_DWLI_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 336805
wst04-VHDL20_DWLI_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 335885
wst04-VHDL20_DWLI_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 336660
wst04-VHDL20_DWLI_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 382520
wst04-VHDL20_DWMO_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:17 356081
wst04-VHDL20_DWMO_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:16 467868
wst04-VHDL20_DWMO_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:16 467268
wst04-VHDL20_DWMO_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:22 468450
wst04-VHDL20_DWMO_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 356934
wst04-VHDL20_DWMO_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:17 469181
wst04-VHDL20_DWMO_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 468988
wst04-VHDL20_DWMO_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:23 469700
wst04-VHDL20_DWMP_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:21 478986
wst04-VHDL20_DWMP_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:16 598795
wst04-VHDL20_DWMP_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:16 598197
wst04-VHDL20_DWMP_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:22 478027
wst04-VHDL20_DWMP_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:21 482147
wst04-VHDL20_DWMP_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:17 598726
wst04-VHDL20_DWMP_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 599002
wst04-VHDL20_DWMP_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:23 482528
wst04-VHDL20_DWPG_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:31:24 353472
wst04-VHDL20_DWPG_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:26 247566
wst04-VHDL20_DWPG_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:30 352909
wst04-VHDL20_DWPG_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:47 398994
wst04-VHDL20_DWPG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:28 348957
wst04-VHDL20_DWPG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:28 243413
wst04-VHDL20_DWPG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:32 348851
wst04-VHDL20_DWPG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 394673
wst04-VHDL20_DWPH_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:31:24 248925
wst04-VHDL20_DWPH_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:22 248407
wst04-VHDL20_DWPH_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:30 248430
wst04-VHDL20_DWPH_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:41 249106
wst04-VHDL20_DWPH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 251736
wst04-VHDL20_DWPH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 250723
wst04-VHDL20_DWPH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:32 251601
wst04-VHDL20_DWPH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 252096
wst04-VHDL20_DWSG_021800-2606021800-omedes--0.pdf 02-Jun-2026 18:30:17 354735
wst04-VHDL20_DWSG_030200-2606030200-omedes--0.pdf 03-Jun-2026 02:30:12 355651
wst04-VHDL20_DWSG_030400-2606030400-omedes--0.pdf 03-Jun-2026 05:00:12 354989
wst04-VHDL20_DWSG_030800-2606030800-omedes--0.pdf 03-Jun-2026 08:30:16 355184
wst04-VHDL20_DWSG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 349986
wst04-VHDL20_DWSG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 349643
wst04-VHDL20_DWSG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 349606
wst04-VHDL20_DWSG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:17 350514