Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-May-2026 13:49:54 4788
FPDL13_DWMZ_240600 24-May-2026 09:52:20 7234
SXDL31_DWAV_230800 23-May-2026 06:43:44 5761
SXDL31_DWAV_231800 23-May-2026 15:03:25 5866
SXDL31_DWAV_240800 24-May-2026 07:42:19 6726
SXDL31_DWAV_241800 24-May-2026 16:41:15 6055
SXDL31_DWAV_LATEST 24-May-2026 16:41:15 6055
SXDL33_DWAV_230000 23-May-2026 09:54:31 10130
SXDL33_DWAV_240000 24-May-2026 09:34:46 10733
SXDL33_DWAV_LATEST 24-May-2026 09:34:46 10733
ber01-FWDL39_DWMS_231230-2605231230-dsw--0-ia5 23-May-2026 11:29:17 964
ber01-FWDL39_DWMS_241230-2605241230-dsw--0-ia5 24-May-2026 12:23:41 961
ber01-VHDL13_DWEG_230800-2605230800-dsw--0-ia5 23-May-2026 08:28:16 2003
ber01-VHDL13_DWEG_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2666
ber01-VHDL13_DWEH_230800-2605230800-dsw--0-ia5 23-May-2026 08:28:16 1987
ber01-VHDL13_DWEH_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2249
ber01-VHDL13_DWEH_240800_COR-2605240800-dsw--0-ia5 24-May-2026 09:13:22 2084
ber01-VHDL13_DWEI_230800-2605230800-dsw--0-ia5 23-May-2026 08:28:16 1929
ber01-VHDL13_DWEI_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2445
ber01-VHDL13_DWHG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:08 2099
ber01-VHDL13_DWHG_230800_COR-2605230800-dsw--0-ia5 23-May-2026 10:19:06 2291
ber01-VHDL13_DWHG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 2002
ber01-VHDL13_DWHH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:08 2296
ber01-VHDL13_DWHH_230800_COR-2605230800-dsw--0-ia5 23-May-2026 10:19:32 2370
ber01-VHDL13_DWHH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 2021
ber01-VHDL13_DWLG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 1979
ber01-VHDL13_DWLG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1936
ber01-VHDL13_DWLH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2125
ber01-VHDL13_DWLH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1819
ber01-VHDL13_DWLI_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2014
ber01-VHDL13_DWLI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1889
ber01-VHDL13_DWMO_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2130
ber01-VHDL13_DWMO_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2354
ber01-VHDL13_DWMP_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2005
ber01-VHDL13_DWMP_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2296
ber01-VHDL13_DWOG_230300-2605230300-dsw--0-ia5 23-May-2026 03:00:01 2665
ber01-VHDL13_DWOG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2609
ber01-VHDL13_DWOG_230800_COR-2605230800-dsw--0-ia5 23-May-2026 08:34:23 2613
ber01-VHDL13_DWOG_231700-2605231700-dsw--0-ia5 23-May-2026 18:00:02 2514
ber01-VHDL13_DWOG_240300-2605240300-dsw--0-ia5 24-May-2026 03:00:06 2628
ber01-VHDL13_DWOG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 3124
ber01-VHDL13_DWOG_241700-2605241700-dsw--0-ia5 24-May-2026 18:00:01 3065
ber01-VHDL13_DWON_230248-2605230248-dsw--0-ia5 23-May-2026 02:48:40 2715
ber01-VHDL13_DWON_230517-2605230517-dsw--0-ia5 23-May-2026 05:17:41 3074
ber01-VHDL13_DWON_230603-2605230603-dsw--0-ia5 23-May-2026 06:03:41 3074
ber01-VHDL13_DWON_230613-2605230613-dsw--0-ia5 23-May-2026 06:13:37 3186
ber01-VHDL13_DWON_230644-2605230644-dsw--0-ia5 23-May-2026 06:44:07 3186
ber01-VHDL13_DWON_230726-2605230726-dsw--0-ia5 23-May-2026 07:26:32 3186
ber01-VHDL13_DWON_230833-2605230833-dsw--0-ia5 23-May-2026 08:33:42 3186
ber01-VHDL13_DWON_231442-2605231442-dsw--0-ia5 23-May-2026 14:43:01 2995
ber01-VHDL13_DWON_231557-2605231557-dsw--0-ia5 23-May-2026 15:57:37 2602
ber01-VHDL13_DWON_231743-2605231743-dsw--0-ia5 23-May-2026 17:43:16 2602
ber01-VHDL13_DWON_232049-2605232049-dsw--0-ia5 23-May-2026 20:49:06 2605
ber01-VHDL13_DWON_240217-2605240217-dsw--0-ia5 24-May-2026 02:17:17 2653
ber01-VHDL13_DWON_240237-2605240237-dsw--0-ia5 24-May-2026 02:37:22 2653
ber01-VHDL13_DWON_240254-2605240254-dsw--0-ia5 24-May-2026 02:54:30 2653
ber01-VHDL13_DWON_240329-2605240329-dsw--0-ia5 24-May-2026 03:29:31 2587
ber01-VHDL13_DWON_240530-2605240530-dsw--0-ia5 24-May-2026 05:30:21 3060
ber01-VHDL13_DWON_240541-2605240541-dsw--0-ia5 24-May-2026 05:41:07 3408
ber01-VHDL13_DWON_241037-2605241037-dsw--0-ia5 24-May-2026 10:37:56 3408
ber01-VHDL13_DWON_241206-2605241206-dsw--0-ia5 24-May-2026 12:06:23 3408
ber01-VHDL13_DWON_241428-2605241428-dsw--0-ia5 24-May-2026 14:28:27 3708
ber01-VHDL13_DWON_241653-2605241653-dsw--0-ia5 24-May-2026 16:53:23 2988
ber01-VHDL13_DWON_241844-2605241844-dsw--0-ia5 24-May-2026 18:45:02 2883
ber01-VHDL13_DWON_250016-2605250016-dsw--0-ia5 25-May-2026 00:16:22 3095
ber01-VHDL13_DWPG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 1951
ber01-VHDL13_DWPG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1938
ber01-VHDL13_DWPH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2021
ber01-VHDL13_DWPH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1894
ber01-VHDL13_DWSG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 2299
ber01-VHDL13_DWSG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2375
ber01-VHDL13_DWSG_240800_COR-2605240800-dsw--0-ia5 24-May-2026 16:33:55 2347
ber01-VHDL17_DWOG_231200-2605231200-dsw--0-ia5 23-May-2026 09:44:22 1884
ber01-VHDL17_DWOG_241200-2605241200-dsw--0-ia5 24-May-2026 11:53:52 3150
swis2-VHDL20_DWEG_230400-2605230400-dsw--0-ia5 23-May-2026 05:01:27 766
swis2-VHDL20_DWEG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 878
swis2-VHDL20_DWEG_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 1085
swis2-VHDL20_DWEG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 848
swis2-VHDL20_DWEG_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 849
swis2-VHDL20_DWEG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 1128
swis2-VHDL20_DWEG_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 895
swis2-VHDL20_DWEG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 750
swis2-VHDL20_DWEH_230400-2605230400-dsw--0-ia5 23-May-2026 05:01:27 775
swis2-VHDL20_DWEH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 822
swis2-VHDL20_DWEH_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 916
swis2-VHDL20_DWEH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 665
swis2-VHDL20_DWEH_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 665
swis2-VHDL20_DWEH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 935
swis2-VHDL20_DWEH_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 921
swis2-VHDL20_DWEH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 764
swis2-VHDL20_DWEI_230400-2605230400-dsw--0-ia5 23-May-2026 05:01:27 788
swis2-VHDL20_DWEI_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 911
swis2-VHDL20_DWEI_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 1084
swis2-VHDL20_DWEI_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 890
swis2-VHDL20_DWEI_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 891
swis2-VHDL20_DWEI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 1165
swis2-VHDL20_DWEI_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 788
swis2-VHDL20_DWEI_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 667
swis2-VHDL20_DWHG_230200-2605230200-dsw--0-ia5 23-May-2026 02:45:06 1044
swis2-VHDL20_DWHG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 1025
swis2-VHDL20_DWHG_230800-2605230800-dsw--0-ia5 23-May-2026 08:45:02 1091
swis2-VHDL20_DWHG_231800-2605231800-dsw--0-ia5 23-May-2026 18:45:02 1135
swis2-VHDL20_DWHG_240200-2605240200-dsw--0-ia5 24-May-2026 02:45:13 1020
swis2-VHDL20_DWHG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 987
swis2-VHDL20_DWHG_240800-2605240800-dsw--0-ia5 24-May-2026 08:45:09 1057
swis2-VHDL20_DWHG_241800-2605241800-dsw--0-ia5 24-May-2026 18:45:06 1053
swis2-VHDL20_DWHG_241800_COR-2605241800-dsw--0-ia5 24-May-2026 18:59:42 1104
swis2-VHDL20_DWHH_230200-2605230200-dsw--0-ia5 23-May-2026 02:45:01 1208
swis2-VHDL20_DWHH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 1192
swis2-VHDL20_DWHH_230800-2605230800-dsw--0-ia5 23-May-2026 08:45:02 1261
swis2-VHDL20_DWHH_231800-2605231800-dsw--0-ia5 23-May-2026 18:45:02 1189
swis2-VHDL20_DWHH_240200-2605240200-dsw--0-ia5 24-May-2026 02:45:13 1031
swis2-VHDL20_DWHH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 1005
swis2-VHDL20_DWHH_240800-2605240800-dsw--0-ia5 24-May-2026 08:45:09 1176
swis2-VHDL20_DWHH_241800-2605241800-dsw--0-ia5 24-May-2026 18:45:06 1169
swis2-VHDL20_DWHH_241800_COR-2605241800-dsw--0-ia5 24-May-2026 18:59:27 1121
swis2-VHDL20_DWLG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 757
swis2-VHDL20_DWLG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:24 851
swis2-VHDL20_DWLG_231800-2605231800-dsw--0-ia5 23-May-2026 18:31:06 859
swis2-VHDL20_DWLG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 851
swis2-VHDL20_DWLG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 789
swis2-VHDL20_DWLG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 883
swis2-VHDL20_DWLG_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 799
swis2-VHDL20_DWLG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 711
swis2-VHDL20_DWLH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 736
swis2-VHDL20_DWLH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:24 830
swis2-VHDL20_DWLH_231800-2605231800-dsw--0-ia5 23-May-2026 18:31:06 839
swis2-VHDL20_DWLH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 760
swis2-VHDL20_DWLH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 737
swis2-VHDL20_DWLH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 825
swis2-VHDL20_DWLH_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 806
swis2-VHDL20_DWLH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 718
swis2-VHDL20_DWLI_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 731
swis2-VHDL20_DWLI_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:24 839
swis2-VHDL20_DWLI_231800-2605231800-dsw--0-ia5 23-May-2026 18:31:06 848
swis2-VHDL20_DWLI_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 793
swis2-VHDL20_DWLI_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 810
swis2-VHDL20_DWLI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 904
swis2-VHDL20_DWLI_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 800
swis2-VHDL20_DWLI_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 712
swis2-VHDL20_DWMO_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:01 798
swis2-VHDL20_DWMO_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 936
swis2-VHDL20_DWMO_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 1062
swis2-VHDL20_DWMO_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 986
swis2-VHDL20_DWMO_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:02 995
swis2-VHDL20_DWMO_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1094
swis2-VHDL20_DWMO_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:05 1048
swis2-VHDL20_DWMO_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 731
swis2-VHDL20_DWMP_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:01 787
swis2-VHDL20_DWMP_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 910
swis2-VHDL20_DWMP_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 1044
swis2-VHDL20_DWMP_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 964
swis2-VHDL20_DWMP_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:02 971
swis2-VHDL20_DWMP_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1073
swis2-VHDL20_DWMP_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:05 1361
swis2-VHDL20_DWMP_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 762
swis2-VHDL20_DWPG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 747
swis2-VHDL20_DWPG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:24 841
swis2-VHDL20_DWPG_231800-2605231800-dsw--0-ia5 23-May-2026 18:31:06 850
swis2-VHDL20_DWPG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 911
swis2-VHDL20_DWPG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 832
swis2-VHDL20_DWPG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 926
swis2-VHDL20_DWPG_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 817
swis2-VHDL20_DWPG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 729
swis2-VHDL20_DWPH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 741
swis2-VHDL20_DWPH_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:24 845
swis2-VHDL20_DWPH_231800-2605231800-dsw--0-ia5 23-May-2026 18:31:06 855
swis2-VHDL20_DWPH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 766
swis2-VHDL20_DWPH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 743
swis2-VHDL20_DWPH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 847
swis2-VHDL20_DWPH_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 865
swis2-VHDL20_DWPH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 1071
swis2-VHDL20_DWSG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 847
swis2-VHDL20_DWSG_230800-2605230800-dsw--0-ia5 23-May-2026 08:30:01 1031
swis2-VHDL20_DWSG_231800-2605231800-dsw--0-ia5 23-May-2026 18:30:04 1027
swis2-VHDL20_DWSG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 965
swis2-VHDL20_DWSG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:22 962
swis2-VHDL20_DWSG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1023
swis2-VHDL20_DWSG_240800_COR-2605240800-dsw--0-ia5 24-May-2026 16:33:55 1090
swis2-VHDL20_DWSG_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 1037
swis2-VHDL20_DWSG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 851
wst04-VHDL20_DWEG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 236161
wst04-VHDL20_DWEG_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:11 236944
wst04-VHDL20_DWEG_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:11 237389
wst04-VHDL20_DWEG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 236016
wst04-VHDL20_DWEG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 236072
wst04-VHDL20_DWEG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 236833
wst04-VHDL20_DWEG_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:11 231913
wst04-VHDL20_DWEG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 231315
wst04-VHDL20_DWEH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 232306
wst04-VHDL20_DWEH_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:11 232147
wst04-VHDL20_DWEH_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:11 231188
wst04-VHDL20_DWEH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 230217
wst04-VHDL20_DWEH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 230168
wst04-VHDL20_DWEH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 231135
wst04-VHDL20_DWEH_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 230448
wst04-VHDL20_DWEH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 230163
wst04-VHDL20_DWEI_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 334772
wst04-VHDL20_DWEI_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:16 335064
wst04-VHDL20_DWEI_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:17 339375
wst04-VHDL20_DWEI_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 338796
wst04-VHDL20_DWEI_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 338808
wst04-VHDL20_DWEI_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 339093
wst04-VHDL20_DWEI_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 329208
wst04-VHDL20_DWEI_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 329170
wst04-VHDL20_DWHG_230200-2605230200-omedes--0.pdf 23-May-2026 02:45:12 337687
wst04-VHDL20_DWHG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 337434
wst04-VHDL20_DWHG_230800-2605230800-omedes--0.pdf 23-May-2026 08:45:12 338208
wst04-VHDL20_DWHG_230800_COR-2605230800-omedes-..> 23-May-2026 10:17:42 334237
wst04-VHDL20_DWHG_231800-2605231800-omedes--0.pdf 23-May-2026 18:45:12 333248
wst04-VHDL20_DWHG_240200-2605240200-omedes--0.pdf 24-May-2026 02:45:13 332213
wst04-VHDL20_DWHG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 332196
wst04-VHDL20_DWHG_240800-2605240800-omedes--0.pdf 24-May-2026 08:45:13 332915
wst04-VHDL20_DWHG_241800-2605241800-omedes--0.pdf 24-May-2026 18:45:10 326695
wst04-VHDL20_DWHH_230200-2605230200-omedes--0.pdf 23-May-2026 02:45:12 323396
wst04-VHDL20_DWHH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 223985
wst04-VHDL20_DWHH_230800-2605230800-omedes--0.pdf 23-May-2026 08:45:12 323546
wst04-VHDL20_DWHH_230800_COR-2605230800-omedes-..> 23-May-2026 10:18:26 327884
wst04-VHDL20_DWHH_231800-2605231800-omedes--0.pdf 23-May-2026 18:45:12 327287
wst04-VHDL20_DWHH_240200-2605240200-omedes--0.pdf 24-May-2026 02:45:13 326374
wst04-VHDL20_DWHH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 222890
wst04-VHDL20_DWHH_240800-2605240800-omedes--0.pdf 24-May-2026 08:45:13 327019
wst04-VHDL20_DWHH_241800-2605241800-omedes--0.pdf 24-May-2026 18:45:10 326850
wst04-VHDL20_DWLG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 324178
wst04-VHDL20_DWLG_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:41 324251
wst04-VHDL20_DWLG_231800-2605231800-omedes--0.pdf 23-May-2026 18:31:24 325553
wst04-VHDL20_DWLG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 326296
wst04-VHDL20_DWLG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 326048
wst04-VHDL20_DWLG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 326274
wst04-VHDL20_DWLG_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:26 322155
wst04-VHDL20_DWLG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 322156
wst04-VHDL20_DWLH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 324703
wst04-VHDL20_DWLH_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:41 324727
wst04-VHDL20_DWLH_231800-2605231800-omedes--0.pdf 23-May-2026 18:31:24 320717
wst04-VHDL20_DWLH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 320932
wst04-VHDL20_DWLH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 320686
wst04-VHDL20_DWLH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 320710
wst04-VHDL20_DWLH_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 322935
wst04-VHDL20_DWLH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:29 322933
wst04-VHDL20_DWLI_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 330594
wst04-VHDL20_DWLI_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:41 375642
wst04-VHDL20_DWLI_231800-2605231800-omedes--0.pdf 23-May-2026 18:31:24 328948
wst04-VHDL20_DWLI_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 329113
wst04-VHDL20_DWLI_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 329442
wst04-VHDL20_DWLI_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:47 374225
wst04-VHDL20_DWLI_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 328968
wst04-VHDL20_DWLI_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 328968
wst04-VHDL20_DWMO_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 442334
wst04-VHDL20_DWMO_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:18 441721
wst04-VHDL20_DWMO_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:17 338606
wst04-VHDL20_DWMO_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:16 444960
wst04-VHDL20_DWMO_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 444870
wst04-VHDL20_DWMO_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:17 444157
wst04-VHDL20_DWMO_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 336468
wst04-VHDL20_DWMO_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:16 442061
wst04-VHDL20_DWMP_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 545657
wst04-VHDL20_DWMP_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:24 447809
wst04-VHDL20_DWMP_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:17 453873
wst04-VHDL20_DWMP_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:16 560402
wst04-VHDL20_DWMP_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 560380
wst04-VHDL20_DWMP_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:22 454372
wst04-VHDL20_DWMP_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 449543
wst04-VHDL20_DWMP_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:16 547197
wst04-VHDL20_DWPG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:31 331620
wst04-VHDL20_DWPG_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:46 376154
wst04-VHDL20_DWPG_231800-2605231800-omedes--0.pdf 23-May-2026 18:31:34 326831
wst04-VHDL20_DWPG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:27 233680
wst04-VHDL20_DWPG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:32 327847
wst04-VHDL20_DWPG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 372582
wst04-VHDL20_DWPG_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 322378
wst04-VHDL20_DWPG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 229891
wst04-VHDL20_DWPH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:31 236803
wst04-VHDL20_DWPH_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:41 237324
wst04-VHDL20_DWPH_231800-2605231800-omedes--0.pdf 23-May-2026 18:31:24 234044
wst04-VHDL20_DWPH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 233698
wst04-VHDL20_DWPH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:32 233487
wst04-VHDL20_DWPH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 234006
wst04-VHDL20_DWPH_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 235541
wst04-VHDL20_DWPH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 236362
wst04-VHDL20_DWSG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 335700
wst04-VHDL20_DWSG_230800-2605230800-omedes--0.pdf 23-May-2026 08:30:11 335845
wst04-VHDL20_DWSG_231800-2605231800-omedes--0.pdf 23-May-2026 18:30:17 345160
wst04-VHDL20_DWSG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 345935
wst04-VHDL20_DWSG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 345954
wst04-VHDL20_DWSG_240800-2605240800-omedes--0.pdf 24-May-2026 16:33:55 335950
wst04-VHDL20_DWSG_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:11 335474
wst04-VHDL20_DWSG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 335548