Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Oct-2026 13:40:30 4504
SXDL31_DWAV_031800 03-Oct-2026 16:08:32 6665
SXDL31_DWAV_040800 04-Oct-2026 07:54:59 6664
SXDL31_DWAV_041800 04-Oct-2026 15:23:04 6630
SXDL31_DWAV_050800 05-Oct-2026 07:26:09 7200
SXDL31_DWAV_LATEST 05-Oct-2026 07:26:09 7200
SXDL33_DWAV_030000 03-Oct-2026 11:34:18 10777
SXDL33_DWAV_040000 04-Oct-2026 09:49:37 5929
SXDL33_DWAV_050000 05-Oct-2026 10:21:54 8314
SXDL33_DWAV_LATEST 05-Oct-2026 10:21:54 8314
ber01-FWDL39_DWMS_031200-2610031200-dsw--0-ia5 03-Oct-2026 11:52:59 1128
ber01-FWDL39_DWMS_041200-2610041200-dsw--0-ia5 04-Oct-2026 11:23:13 1332
ber01-FWDL39_DWMS_051200-2610051200-dsw--0-ia5 05-Oct-2026 10:15:05 1503
ber01-VHDL13_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:14 2420
ber01-VHDL13_DWEG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:24 2657
ber01-VHDL13_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:18 2507
ber01-VHDL13_DWEH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:24 2910
ber01-VHDL13_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:24 2519
ber01-VHDL13_DWEI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:18 2783
ber01-VHDL13_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2940
ber01-VHDL13_DWHG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 2993
ber01-VHDL13_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2848
ber01-VHDL13_DWHH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 2945
ber01-VHDL13_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1894
ber01-VHDL13_DWLG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2258
ber01-VHDL13_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2072
ber01-VHDL13_DWLH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2369
ber01-VHDL13_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1945
ber01-VHDL13_DWLI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2246
ber01-VHDL13_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2717
ber01-VHDL13_DWMO_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2425
ber01-VHDL13_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 3018
ber01-VHDL13_DWMP_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 3002
ber01-VHDL13_DWOG_031700-2610031700-dsw--0-ia5 03-Oct-2026 18:00:14 3029
ber01-VHDL13_DWOG_040300-2610040300-dsw--0-ia5 04-Oct-2026 03:00:23 3827
ber01-VHDL13_DWOG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:12 3554
ber01-VHDL13_DWOG_041700-2610041700-dsw--0-ia5 04-Oct-2026 18:00:05 3101
ber01-VHDL13_DWOG_050300-2610050300-dsw--0-ia5 05-Oct-2026 03:00:07 4019
ber01-VHDL13_DWOG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 3687
ber01-VHDL13_DWON_031320-2610031320-dsw--0-ia5 03-Oct-2026 13:21:03 3037
ber01-VHDL13_DWON_031649-2610031649-dsw--0-ia5 03-Oct-2026 16:50:10 3180
ber01-VHDL13_DWON_031849-2610031849-dsw--0-ia5 03-Oct-2026 18:49:49 3477
ber01-VHDL13_DWON_032143-2610032143-dsw--0-ia5 03-Oct-2026 21:43:51 3459
ber01-VHDL13_DWON_032144-2610032144-dsw--0-ia5 03-Oct-2026 21:44:31 3459
ber01-VHDL13_DWON_040004-2610040004-dsw--0-ia5 04-Oct-2026 00:04:48 4032
ber01-VHDL13_DWON_040142-2610040142-dsw--0-ia5 04-Oct-2026 01:42:32 4010
ber01-VHDL13_DWON_040252-2610040252-dsw--0-ia5 04-Oct-2026 02:52:30 4010
ber01-VHDL13_DWON_040529-2610040529-dsw--0-ia5 04-Oct-2026 05:29:58 4277
ber01-VHDL13_DWON_040628-2610040628-dsw--0-ia5 04-Oct-2026 06:28:53 4016
ber01-VHDL13_DWON_040649-2610040649-dsw--0-ia5 04-Oct-2026 06:49:49 4016
ber01-VHDL13_DWON_040802-2610040802-dsw--0-ia5 04-Oct-2026 08:03:13 4016
ber01-VHDL13_DWON_041455-2610041455-dsw--0-ia5 04-Oct-2026 14:55:45 3823
ber01-VHDL13_DWON_041625-2610041625-dsw--0-ia5 04-Oct-2026 16:25:34 3227
ber01-VHDL13_DWON_041814-2610041814-dsw--0-ia5 04-Oct-2026 18:14:49 3460
ber01-VHDL13_DWON_042155-2610042155-dsw--0-ia5 04-Oct-2026 21:56:14 3479
ber01-VHDL13_DWON_050000-2610050000-dsw--0-ia5 05-Oct-2026 00:00:30 4148
ber01-VHDL13_DWON_050137-2610050137-dsw--0-ia5 05-Oct-2026 01:38:06 4094
ber01-VHDL13_DWON_050245-2610050245-dsw--0-ia5 05-Oct-2026 02:46:58 4094
ber01-VHDL13_DWON_050526-2610050526-dsw--0-ia5 05-Oct-2026 05:26:13 3433
ber01-VHDL13_DWON_050555-2610050555-dsw--0-ia5 05-Oct-2026 05:56:05 3592
ber01-VHDL13_DWON_050753-2610050753-dsw--0-ia5 05-Oct-2026 07:53:25 3756
ber01-VHDL13_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1940
ber01-VHDL13_DWPG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2305
ber01-VHDL13_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1995
ber01-VHDL13_DWPH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2268
ber01-VHDL13_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 3036
ber01-VHDL13_DWSG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2685
ber01-VHDL17_DWOG_031200-2610031200-dsw--0-ia5 03-Oct-2026 11:00:43 2726
ber01-VHDL17_DWOG_041200-2610041200-dsw--0-ia5 04-Oct-2026 11:22:03 2932
swis2-VHDL20_DWEG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1071
swis2-VHDL20_DWEG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 793
swis2-VHDL20_DWEG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 793
swis2-VHDL20_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1052
swis2-VHDL20_DWEG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1326
swis2-VHDL20_DWEG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 838
swis2-VHDL20_DWEG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 824
swis2-VHDL20_DWEG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1349
swis2-VHDL20_DWEH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1087
swis2-VHDL20_DWEH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 805
swis2-VHDL20_DWEH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 805
swis2-VHDL20_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1063
swis2-VHDL20_DWEH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1403
swis2-VHDL20_DWEH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 845
swis2-VHDL20_DWEH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 838
swis2-VHDL20_DWEH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1471
swis2-VHDL20_DWEI_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:03 1102
swis2-VHDL20_DWEI_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 816
swis2-VHDL20_DWEI_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:01:15 816
swis2-VHDL20_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1080
swis2-VHDL20_DWEI_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1320
swis2-VHDL20_DWEI_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 860
swis2-VHDL20_DWEI_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 846
swis2-VHDL20_DWEI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1372
swis2-VHDL20_DWHG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:45:20 1363
swis2-VHDL20_DWHG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:45:35 1127
swis2-VHDL20_DWHG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1124
swis2-VHDL20_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1370
swis2-VHDL20_DWHG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:45:18 1495
swis2-VHDL20_DWHG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:45:44 1204
swis2-VHDL20_DWHG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1189
swis2-VHDL20_DWHG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:45:17 1441
swis2-VHDL20_DWHH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:45:20 1424
swis2-VHDL20_DWHH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:45:35 1213
swis2-VHDL20_DWHH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1213
swis2-VHDL20_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1371
swis2-VHDL20_DWHH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:45:18 1741
swis2-VHDL20_DWHH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:45:44 1396
swis2-VHDL20_DWHH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1366
swis2-VHDL20_DWHH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:45:17 1547
swis2-VHDL20_DWLG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 821
swis2-VHDL20_DWLG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 771
swis2-VHDL20_DWLG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 785
swis2-VHDL20_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 810
swis2-VHDL20_DWLG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1104
swis2-VHDL20_DWLG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 797
swis2-VHDL20_DWLG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 877
swis2-VHDL20_DWLG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 972
swis2-VHDL20_DWLH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 828
swis2-VHDL20_DWLH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 778
swis2-VHDL20_DWLH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 792
swis2-VHDL20_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 817
swis2-VHDL20_DWLH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1124
swis2-VHDL20_DWLH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 790
swis2-VHDL20_DWLH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 884
swis2-VHDL20_DWLH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 1016
swis2-VHDL20_DWLI_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 823
swis2-VHDL20_DWLI_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 773
swis2-VHDL20_DWLI_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 787
swis2-VHDL20_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 812
swis2-VHDL20_DWLI_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1079
swis2-VHDL20_DWLI_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 785
swis2-VHDL20_DWLI_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 879
swis2-VHDL20_DWLI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 977
swis2-VHDL20_DWMO_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1136
swis2-VHDL20_DWMO_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1061
swis2-VHDL20_DWMO_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:09 1078
swis2-VHDL20_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1234
swis2-VHDL20_DWMO_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1202
swis2-VHDL20_DWMO_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 969
swis2-VHDL20_DWMO_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:03 976
swis2-VHDL20_DWMO_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1145
swis2-VHDL20_DWMP_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1417
swis2-VHDL20_DWMP_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1353
swis2-VHDL20_DWMP_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:07 1365
swis2-VHDL20_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1417
swis2-VHDL20_DWMP_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1546
swis2-VHDL20_DWMP_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 1278
swis2-VHDL20_DWMP_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:03 1272
swis2-VHDL20_DWMP_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1422
swis2-VHDL20_DWPG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 839
swis2-VHDL20_DWPG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 789
swis2-VHDL20_DWPG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 803
swis2-VHDL20_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 828
swis2-VHDL20_DWPG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1050
swis2-VHDL20_DWPG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 815
swis2-VHDL20_DWPG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 888
swis2-VHDL20_DWPG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 961
swis2-VHDL20_DWPH_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:31:12 881
swis2-VHDL20_DWPH_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:25 779
swis2-VHDL20_DWPH_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:13 775
swis2-VHDL20_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 803
swis2-VHDL20_DWPH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1138
swis2-VHDL20_DWPH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 788
swis2-VHDL20_DWPH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 878
swis2-VHDL20_DWPH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 962
swis2-VHDL20_DWSG_031800-2610031800-dsw--0-ia5 03-Oct-2026 18:30:12 1409
swis2-VHDL20_DWSG_040200-2610040200-dsw--0-ia5 04-Oct-2026 02:30:04 1257
swis2-VHDL20_DWSG_040400-2610040400-dsw--0-ia5 04-Oct-2026 05:00:19 1250
swis2-VHDL20_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 1308
swis2-VHDL20_DWSG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1399
swis2-VHDL20_DWSG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 1234
swis2-VHDL20_DWSG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1196
swis2-VHDL20_DWSG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1050
wst04-VHDL20_DWEG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:12 242247
wst04-VHDL20_DWEG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 240224
wst04-VHDL20_DWEG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 240260
wst04-VHDL20_DWEG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 242050
wst04-VHDL20_DWEG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:17 243049
wst04-VHDL20_DWEG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 240241
wst04-VHDL20_DWEG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 240056
wst04-VHDL20_DWEG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:13 242652
wst04-VHDL20_DWEH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:12 235087
wst04-VHDL20_DWEH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 233374
wst04-VHDL20_DWEH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 233727
wst04-VHDL20_DWEH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 235539
wst04-VHDL20_DWEH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:17 236088
wst04-VHDL20_DWEH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 233400
wst04-VHDL20_DWEH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 233517
wst04-VHDL20_DWEH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:13 236283
wst04-VHDL20_DWEI_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 347972
wst04-VHDL20_DWEI_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:22 346509
wst04-VHDL20_DWEI_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 346496
wst04-VHDL20_DWEI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 347746
wst04-VHDL20_DWEI_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 349478
wst04-VHDL20_DWEI_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 346552
wst04-VHDL20_DWEI_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 346301
wst04-VHDL20_DWEI_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:18 349042
wst04-VHDL20_DWHG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:45:20 348057
wst04-VHDL20_DWHG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:45:35 347028
wst04-VHDL20_DWHG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 347031
wst04-VHDL20_DWHG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 348375
wst04-VHDL20_DWHG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:45:18 348002
wst04-VHDL20_DWHG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:45:45 347391
wst04-VHDL20_DWHG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:23 347136
wst04-VHDL20_DWHG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:45:20 348384
wst04-VHDL20_DWHH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:45:20 334068
wst04-VHDL20_DWHH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:45:35 333153
wst04-VHDL20_DWHH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:23 229245
wst04-VHDL20_DWHH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 333809
wst04-VHDL20_DWHH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:45:18 335402
wst04-VHDL20_DWHH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:45:45 334213
wst04-VHDL20_DWHH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 230135
wst04-VHDL20_DWHH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:45:20 334593
wst04-VHDL20_DWLG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:41 332988
wst04-VHDL20_DWLG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 332410
wst04-VHDL20_DWLG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 332473
wst04-VHDL20_DWLG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 332978
wst04-VHDL20_DWLG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 333949
wst04-VHDL20_DWLG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 333449
wst04-VHDL20_DWLG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 332608
wst04-VHDL20_DWLG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 333553
wst04-VHDL20_DWLH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 337010
wst04-VHDL20_DWLH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:27 336421
wst04-VHDL20_DWLH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 336479
wst04-VHDL20_DWLH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 337007
wst04-VHDL20_DWLH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 337743
wst04-VHDL20_DWLH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 337432
wst04-VHDL20_DWLH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 336623
wst04-VHDL20_DWLH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:53 337601
wst04-VHDL20_DWLI_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:41 338068
wst04-VHDL20_DWLI_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 337502
wst04-VHDL20_DWLI_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:45 337527
wst04-VHDL20_DWLI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 382640
wst04-VHDL20_DWLI_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 338809
wst04-VHDL20_DWLI_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 338508
wst04-VHDL20_DWLI_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 337672
wst04-VHDL20_DWLI_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 383256
wst04-VHDL20_DWMO_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 353579
wst04-VHDL20_DWMO_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 455560
wst04-VHDL20_DWMO_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 454724
wst04-VHDL20_DWMO_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 454807
wst04-VHDL20_DWMO_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 353087
wst04-VHDL20_DWMO_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:20 455069
wst04-VHDL20_DWMO_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 454928
wst04-VHDL20_DWMO_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:31 455136
wst04-VHDL20_DWMP_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:32 461653
wst04-VHDL20_DWMP_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 562656
wst04-VHDL20_DWMP_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:19 562410
wst04-VHDL20_DWMP_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 460720
wst04-VHDL20_DWMP_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:36 460898
wst04-VHDL20_DWMP_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:20 562348
wst04-VHDL20_DWMP_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 562592
wst04-VHDL20_DWMP_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:31 461081
wst04-VHDL20_DWPG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 347424
wst04-VHDL20_DWPG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 243304
wst04-VHDL20_DWPG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:34 346967
wst04-VHDL20_DWPG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 391996
wst04-VHDL20_DWPG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 347868
wst04-VHDL20_DWPG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 244341
wst04-VHDL20_DWPG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:33 346840
wst04-VHDL20_DWPG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 391815
wst04-VHDL20_DWPH_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:31:22 242349
wst04-VHDL20_DWPH_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 241764
wst04-VHDL20_DWPH_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:34 241832
wst04-VHDL20_DWPH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 242279
wst04-VHDL20_DWPH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 243716
wst04-VHDL20_DWPH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 242998
wst04-VHDL20_DWPH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:33 241724
wst04-VHDL20_DWPH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 243097
wst04-VHDL20_DWSG_031800-2610031800-omedes--0.pdf 03-Oct-2026 18:30:26 349477
wst04-VHDL20_DWSG_040200-2610040200-omedes--0.pdf 04-Oct-2026 02:30:25 347707
wst04-VHDL20_DWSG_040400-2610040400-omedes--0.pdf 04-Oct-2026 05:00:15 347435
wst04-VHDL20_DWSG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 347632
wst04-VHDL20_DWSG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 347520
wst04-VHDL20_DWSG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 347747
wst04-VHDL20_DWSG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 347519
wst04-VHDL20_DWSG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:18 347070