Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_200600 20-Apr-2026 13:15:00 2769
FPDL13_DWMZ_210600 21-Apr-2026 12:07:15 3622
SXDL31_DWAV_200800 20-Apr-2026 07:18:53 6643
SXDL31_DWAV_201800 20-Apr-2026 16:02:49 8292
SXDL31_DWAV_210800 21-Apr-2026 07:59:14 12150
SXDL31_DWAV_211800 21-Apr-2026 16:00:19 9104
SXDL31_DWAV_LATEST 21-Apr-2026 16:00:19 9104
SXDL33_DWAV_200000 20-Apr-2026 10:19:49 11008
SXDL33_DWAV_210000 21-Apr-2026 09:17:16 5761
SXDL33_DWAV_LATEST 21-Apr-2026 09:17:16 5761
ber01-FWDL39_DWMS_201230-2604201230-dsw--0-ia5 20-Apr-2026 11:22:13 1069
ber01-FWDL39_DWMS_211230-2604211230-dsw--0-ia5 21-Apr-2026 11:32:47 1458
ber01-VHDL13_DWEG_210800-2604210800-dsw--0-ia5 21-Apr-2026 09:03:52 2707
ber01-VHDL13_DWEG_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:31 2717
ber01-VHDL13_DWEH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:28:11 2625
ber01-VHDL13_DWEH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:28:17 2273
ber01-VHDL13_DWEH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:28:12 2610
ber01-VHDL13_DWEH_210400-2604210400-dsw--0-ia5 21-Apr-2026 04:58:11 2610
ber01-VHDL13_DWEH_210800-2604210800-dsw--0-ia5 21-Apr-2026 09:03:52 2885
ber01-VHDL13_DWEH_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:37 2895
ber01-VHDL13_DWEI_210800-2604210800-dsw--0-ia5 21-Apr-2026 09:03:52 2498
ber01-VHDL13_DWEI_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:37 2508
ber01-VHDL13_DWHG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 3217
ber01-VHDL13_DWHG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:08 2400
ber01-VHDL13_DWHG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:17 2399
ber01-VHDL13_DWHG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:07 2789
ber01-VHDL13_DWHG_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 08:44:03 2935
ber01-VHDL13_DWHG_211800-2604211800-dsw--0-ia5 21-Apr-2026 20:13:17 2494
ber01-VHDL13_DWHG_220200_COR-2604220200-dsw--0-ia5 22-Apr-2026 02:56:01 2542
ber01-VHDL13_DWHH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2655
ber01-VHDL13_DWHH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:08 2203
ber01-VHDL13_DWHH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:17 2212
ber01-VHDL13_DWHH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:07 2773
ber01-VHDL13_DWHH_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 08:44:41 2919
ber01-VHDL13_DWHH_211800-2604211800-dsw--0-ia5 21-Apr-2026 20:13:51 2436
ber01-VHDL13_DWHH_220200_COR-2604220200-dsw--0-ia5 22-Apr-2026 02:57:10 2495
ber01-VHDL13_DWLG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2267
ber01-VHDL13_DWLG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 1817
ber01-VHDL13_DWLG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2038
ber01-VHDL13_DWLG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2028
ber01-VHDL13_DWLG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2412
ber01-VHDL13_DWLH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2206
ber01-VHDL13_DWLH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 1857
ber01-VHDL13_DWLH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2128
ber01-VHDL13_DWLH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2048
ber01-VHDL13_DWLH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2202
ber01-VHDL13_DWLI_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2042
ber01-VHDL13_DWLI_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 1751
ber01-VHDL13_DWLI_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2050
ber01-VHDL13_DWLI_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2029
ber01-VHDL13_DWLI_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2373
ber01-VHDL13_DWMG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2285
ber01-VHDL13_DWMG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 2115
ber01-VHDL13_DWMG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2196
ber01-VHDL13_DWMG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2177
ber01-VHDL13_DWMO_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2343
ber01-VHDL13_DWMO_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 2203
ber01-VHDL13_DWMO_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2380
ber01-VHDL13_DWMO_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2361
ber01-VHDL13_DWMO_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2932
ber01-VHDL13_DWMP_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2529
ber01-VHDL13_DWMP_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 2321
ber01-VHDL13_DWMP_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2482
ber01-VHDL13_DWMP_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2484
ber01-VHDL13_DWMP_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 3091
ber01-VHDL13_DWOG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 3986
ber01-VHDL13_DWOG_201700-2604201700-dsw--0-ia5 20-Apr-2026 18:00:01 3380
ber01-VHDL13_DWOG_210300-2604210300-dsw--0-ia5 21-Apr-2026 03:00:11 3894
ber01-VHDL13_DWOG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 3502
ber01-VHDL13_DWOG_211700-2604211700-dsw--0-ia5 21-Apr-2026 18:00:07 3661
ber01-VHDL13_DWOG_220300-2604220300-dsw--0-ia5 22-Apr-2026 03:00:14 4732
ber01-VHDL13_DWOH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:28:17 2488
ber01-VHDL13_DWOH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:28:11 2217
ber01-VHDL13_DWOH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:28:12 2557
ber01-VHDL13_DWOH_210400-2604210400-dsw--0-ia5 21-Apr-2026 04:58:17 2568
ber01-VHDL13_DWOI_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:28:17 2403
ber01-VHDL13_DWOI_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:28:17 2332
ber01-VHDL13_DWOI_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:28:16 2399
ber01-VHDL13_DWOI_210400-2604210400-dsw--0-ia5 21-Apr-2026 04:58:17 2339
ber01-VHDL13_DWON_200548-2604200548-dsw--0-ia5 20-Apr-2026 05:48:21 3872
ber01-VHDL13_DWON_201502-2604201502-dsw--0-ia5 20-Apr-2026 15:02:18 3067
ber01-VHDL13_DWON_201552-2604201552-dsw--0-ia5 20-Apr-2026 15:53:01 3067
ber01-VHDL13_DWON_201635-2604201635-dsw--0-ia5 20-Apr-2026 16:35:14 3067
ber01-VHDL13_DWON_210055-2604210055-dsw--0-ia5 21-Apr-2026 00:55:21 3557
ber01-VHDL13_DWON_210230-2604210230-dsw--0-ia5 21-Apr-2026 02:31:01 3552
ber01-VHDL13_DWON_210236-2604210236-dsw--0-ia5 21-Apr-2026 02:36:38 3552
ber01-VHDL13_DWON_210455-2604210455-dsw--0-ia5 21-Apr-2026 04:55:32 3818
ber01-VHDL13_DWON_210548-2604210548-dsw--0-ia5 21-Apr-2026 05:48:26 3818
ber01-VHDL13_DWON_210758-2604210758-dsw--0-ia5 21-Apr-2026 07:58:26 3818
ber01-VHDL13_DWON_210857-2604210857-dsw--0-ia5 21-Apr-2026 08:57:52 3818
ber01-VHDL13_DWON_211420-2604211420-dsw--0-ia5 21-Apr-2026 14:21:01 3448
ber01-VHDL13_DWON_211630-2604211630-dsw--0-ia5 21-Apr-2026 16:30:51 3166
ber01-VHDL13_DWON_211631-2604211631-dsw--0-ia5 21-Apr-2026 16:31:16 3166
ber01-VHDL13_DWON_212028-2604212028-dsw--0-ia5 21-Apr-2026 20:28:56 3229
ber01-VHDL13_DWON_220141-2604220141-dsw--0-ia5 22-Apr-2026 01:41:41 3874
ber01-VHDL13_DWON_220237-2604220237-dsw--0-ia5 22-Apr-2026 02:38:03 3874
ber01-VHDL13_DWON_220529-2604220529-dsw--0-ia5 22-Apr-2026 05:29:32 4108
ber01-VHDL13_DWPG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2362
ber01-VHDL13_DWPG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 1970
ber01-VHDL13_DWPG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2232
ber01-VHDL13_DWPG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2208
ber01-VHDL13_DWPG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2432
ber01-VHDL13_DWPH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2631
ber01-VHDL13_DWPH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 2174
ber01-VHDL13_DWPH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2193
ber01-VHDL13_DWPH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:01 2249
ber01-VHDL13_DWPH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 2456
ber01-VHDL13_DWSG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:30:08 2441
ber01-VHDL13_DWSG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:30:01 2241
ber01-VHDL13_DWSG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:30:03 2685
ber01-VHDL13_DWSG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:17 3071
ber01-VHDL13_DWSG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 3572
ber01-VHDL17_DWOG_201200-2604201200-dsw--0-ia5 20-Apr-2026 11:59:11 2895
ber01-VHDL17_DWOG_211200-2604211200-dsw--0-ia5 21-Apr-2026 11:31:12 2683
swis2-VHDL20_DWEG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2965
swis2-VHDL20_DWEG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:06 2544
swis2-VHDL20_DWEG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2837
swis2-VHDL20_DWEG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2886
swis2-VHDL20_DWEG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:07 668
swis2-VHDL20_DWEG_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:27 1189
swis2-VHDL20_DWEG_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:02 1265
swis2-VHDL20_DWEG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1191
swis2-VHDL20_DWEG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1246
swis2-VHDL20_DWEH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 3127
swis2-VHDL20_DWEH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:06 2629
swis2-VHDL20_DWEH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2935
swis2-VHDL20_DWEH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2940
swis2-VHDL20_DWEH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:07 696
swis2-VHDL20_DWEH_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:27 1362
swis2-VHDL20_DWEH_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:02 1456
swis2-VHDL20_DWEH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1363
swis2-VHDL20_DWEH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1440
swis2-VHDL20_DWEI_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2927
swis2-VHDL20_DWEI_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:06 2684
swis2-VHDL20_DWEI_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2694
swis2-VHDL20_DWEI_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2688
swis2-VHDL20_DWEI_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:07 702
swis2-VHDL20_DWEI_210800_COR-2604210800-dsw--0-ia5 21-Apr-2026 14:07:27 1093
swis2-VHDL20_DWEI_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:02 1349
swis2-VHDL20_DWEI_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1148
swis2-VHDL20_DWEI_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1158
swis2-VHDL20_DWHG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:02 3822
swis2-VHDL20_DWHG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:06 3090
swis2-VHDL20_DWHG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:07 2586
swis2-VHDL20_DWHG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:17 2582
swis2-VHDL20_DWHG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:45:04 1393
swis2-VHDL20_DWHG_211800-2604211800-dsw--0-ia5 21-Apr-2026 19:57:22 1451
swis2-VHDL20_DWHG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:45:07 1333
swis2-VHDL20_DWHG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:16 1416
swis2-VHDL20_DWHH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:02 3195
swis2-VHDL20_DWHH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:06 2593
swis2-VHDL20_DWHH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:07 2389
swis2-VHDL20_DWHH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:17 2398
swis2-VHDL20_DWHH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:45:04 1448
swis2-VHDL20_DWHH_211800-2604211800-dsw--0-ia5 21-Apr-2026 19:57:51 1467
swis2-VHDL20_DWHH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:45:07 1191
swis2-VHDL20_DWHH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:16 1277
swis2-VHDL20_DWLG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2761
swis2-VHDL20_DWLG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2160
swis2-VHDL20_DWLG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2381
swis2-VHDL20_DWLG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:11 2375
swis2-VHDL20_DWLG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:28 1030
swis2-VHDL20_DWLG_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:31:01 946
swis2-VHDL20_DWLG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 1092
swis2-VHDL20_DWLG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1022
swis2-VHDL20_DWLH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:05 2711
swis2-VHDL20_DWLH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2207
swis2-VHDL20_DWLH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2478
swis2-VHDL20_DWLH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:11 2402
swis2-VHDL20_DWLH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:28 996
swis2-VHDL20_DWLH_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:31:01 969
swis2-VHDL20_DWLH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 900
swis2-VHDL20_DWLH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 827
swis2-VHDL20_DWLI_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2537
swis2-VHDL20_DWLI_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2096
swis2-VHDL20_DWLI_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2395
swis2-VHDL20_DWLI_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:11 2378
swis2-VHDL20_DWLI_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:28 1012
swis2-VHDL20_DWLI_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:31:01 906
swis2-VHDL20_DWLI_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 879
swis2-VHDL20_DWLI_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 826
swis2-VHDL20_DWMG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2814
swis2-VHDL20_DWMG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2487
swis2-VHDL20_DWMG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2569
swis2-VHDL20_DWMG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2549
swis2-VHDL20_DWMO_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2880
swis2-VHDL20_DWMO_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2579
swis2-VHDL20_DWMO_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2756
swis2-VHDL20_DWMO_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2737
swis2-VHDL20_DWMO_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:45:04 1289
swis2-VHDL20_DWMO_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:06 980
swis2-VHDL20_DWMO_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 954
swis2-VHDL20_DWMO_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:06 952
swis2-VHDL20_DWMP_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 3064
swis2-VHDL20_DWMP_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2655
swis2-VHDL20_DWMP_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2857
swis2-VHDL20_DWMP_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:07 2856
swis2-VHDL20_DWMP_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:45:04 1436
swis2-VHDL20_DWMP_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:06 1083
swis2-VHDL20_DWMP_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1105
swis2-VHDL20_DWMP_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:06 1102
swis2-VHDL20_DWPG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:07 2823
swis2-VHDL20_DWPG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2431
swis2-VHDL20_DWPG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2562
swis2-VHDL20_DWPG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:11 2535
swis2-VHDL20_DWPG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:28 964
swis2-VHDL20_DWPG_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:31:01 911
swis2-VHDL20_DWPG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 784
swis2-VHDL20_DWPG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 779
swis2-VHDL20_DWPH_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:05 3092
swis2-VHDL20_DWPH_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2635
swis2-VHDL20_DWPH_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 2522
swis2-VHDL20_DWPH_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:00:11 2578
swis2-VHDL20_DWPH_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:28 961
swis2-VHDL20_DWPH_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:31:01 907
swis2-VHDL20_DWPH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 780
swis2-VHDL20_DWPH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 783
swis2-VHDL20_DWSG_200800-2604200800-dsw--0-ia5 20-Apr-2026 08:45:02 2941
swis2-VHDL20_DWSG_201800-2604201800-dsw--0-ia5 20-Apr-2026 18:45:02 2597
swis2-VHDL20_DWSG_210200-2604210200-dsw--0-ia5 21-Apr-2026 02:45:05 3031
swis2-VHDL20_DWSG_210400-2604210400-dsw--0-ia5 21-Apr-2026 05:15:01 3425
swis2-VHDL20_DWSG_210800-2604210800-dsw--0-ia5 21-Apr-2026 08:30:02 1617
swis2-VHDL20_DWSG_211800-2604211800-dsw--0-ia5 21-Apr-2026 18:30:06 1519
swis2-VHDL20_DWSG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1212
swis2-VHDL20_DWSG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:18 1225
wst04-VHDL20_DWEG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:12 238391
wst04-VHDL20_DWEG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:12 241016
wst04-VHDL20_DWEG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:19 241778
wst04-VHDL20_DWEG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:11 241253
wst04-VHDL20_DWEG_210800-2604210800-omedes--0.pdf 21-Apr-2026 09:45:22 238554
wst04-VHDL20_DWEG_210800_COR-2604210800-omedes-..> 21-Apr-2026 14:07:31 233183
wst04-VHDL20_DWEG_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:16 233235
wst04-VHDL20_DWEG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 232558
wst04-VHDL20_DWEG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 137269
wst04-VHDL20_DWEH_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:12 242832
wst04-VHDL20_DWEH_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:12 238048
wst04-VHDL20_DWEH_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:11 239548
wst04-VHDL20_DWEH_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:11 238353
wst04-VHDL20_DWEH_210800-2604210800-omedes--0.pdf 21-Apr-2026 09:45:22 236394
wst04-VHDL20_DWEH_210800_COR-2604210800-omedes-..> 21-Apr-2026 14:07:31 229625
wst04-VHDL20_DWEH_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:12 229649
wst04-VHDL20_DWEH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 229156
wst04-VHDL20_DWEH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 229391
wst04-VHDL20_DWEI_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:16 342753
wst04-VHDL20_DWEI_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:12 343177
wst04-VHDL20_DWEI_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:19 343406
wst04-VHDL20_DWEI_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:17 343243
wst04-VHDL20_DWEI_210800-2604210800-omedes--0.pdf 21-Apr-2026 09:45:22 340163
wst04-VHDL20_DWEI_210800_COR-2604210800-omedes-..> 21-Apr-2026 14:07:37 329616
wst04-VHDL20_DWEI_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:16 330969
wst04-VHDL20_DWEI_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 330241
wst04-VHDL20_DWEI_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 329997
wst04-VHDL20_DWHG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:22 349965
wst04-VHDL20_DWHG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:16 392552
wst04-VHDL20_DWHG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:16 346789
wst04-VHDL20_DWHG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:11 346799
wst04-VHDL20_DWHG_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:45:16 345757
wst04-VHDL20_DWHG_211800-2604211800-omedes--0.pdf 21-Apr-2026 19:56:31 326185
wst04-VHDL20_DWHG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:45:11 325334
wst04-VHDL20_DWHG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 325402
wst04-VHDL20_DWHH_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:22 336875
wst04-VHDL20_DWHH_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:22 376502
wst04-VHDL20_DWHH_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:16 331410
wst04-VHDL20_DWHH_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:11 331394
wst04-VHDL20_DWHH_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:45:11 329881
wst04-VHDL20_DWHH_211800-2604211800-omedes--0.pdf 21-Apr-2026 19:57:02 316371
wst04-VHDL20_DWHH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:45:11 315720
wst04-VHDL20_DWHH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 220125
wst04-VHDL20_DWLG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:32 337003
wst04-VHDL20_DWLG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:26 330082
wst04-VHDL20_DWLG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:31 329899
wst04-VHDL20_DWLG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:41 330302
wst04-VHDL20_DWLG_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:42 328316
wst04-VHDL20_DWLG_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:31:22 318141
wst04-VHDL20_DWLG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:28 318546
wst04-VHDL20_DWLG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 318205
wst04-VHDL20_DWLH_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:27 344435
wst04-VHDL20_DWLH_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:22 333165
wst04-VHDL20_DWLH_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:25 333191
wst04-VHDL20_DWLH_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:41 333647
wst04-VHDL20_DWLH_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:46 331598
wst04-VHDL20_DWLH_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:31:22 321180
wst04-VHDL20_DWLH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 320617
wst04-VHDL20_DWLH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 320247
wst04-VHDL20_DWLI_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:27 331538
wst04-VHDL20_DWLI_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:22 328596
wst04-VHDL20_DWLI_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:25 329457
wst04-VHDL20_DWLI_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:41 329900
wst04-VHDL20_DWLI_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:42 372005
wst04-VHDL20_DWLI_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:31:22 316177
wst04-VHDL20_DWLI_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 316448
wst04-VHDL20_DWLI_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 316076
wst04-VHDL20_DWMG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:22 552153
wst04-VHDL20_DWMG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:18 542586
wst04-VHDL20_DWMG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:25 542531
wst04-VHDL20_DWMG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:17 542464
wst04-VHDL20_DWMO_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:16 448885
wst04-VHDL20_DWMO_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:18 443373
wst04-VHDL20_DWMO_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:11 444175
wst04-VHDL20_DWMO_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:17 444735
wst04-VHDL20_DWMO_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:45:13 441167
wst04-VHDL20_DWMO_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:16 333823
wst04-VHDL20_DWMO_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:16 429588
wst04-VHDL20_DWMO_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 429802
wst04-VHDL20_DWMP_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:22 554446
wst04-VHDL20_DWMP_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:18 537589
wst04-VHDL20_DWMP_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:25 536079
wst04-VHDL20_DWMP_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:21 537178
wst04-VHDL20_DWMP_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:45:13 439532
wst04-VHDL20_DWMP_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:16 436090
wst04-VHDL20_DWMP_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:16 528831
wst04-VHDL20_DWMP_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 529099
wst04-VHDL20_DWPG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:32 402554
wst04-VHDL20_DWPG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:26 344848
wst04-VHDL20_DWPG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:30 345116
wst04-VHDL20_DWPG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:31 345951
wst04-VHDL20_DWPG_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:42 387836
wst04-VHDL20_DWPG_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:31:22 327905
wst04-VHDL20_DWPG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 233687
wst04-VHDL20_DWPG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:32 327765
wst04-VHDL20_DWPH_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:27 293825
wst04-VHDL20_DWPH_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:22 288125
wst04-VHDL20_DWPH_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:25 243130
wst04-VHDL20_DWPH_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:00:31 243556
wst04-VHDL20_DWPH_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:42 242114
wst04-VHDL20_DWPH_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:31:22 235509
wst04-VHDL20_DWPH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 235661
wst04-VHDL20_DWPH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:32 235376
wst04-VHDL20_DWSG_200800-2604200800-omedes--0.pdf 20-Apr-2026 08:45:12 342815
wst04-VHDL20_DWSG_201800-2604201800-omedes--0.pdf 20-Apr-2026 18:45:12 341943
wst04-VHDL20_DWSG_210200-2604210200-omedes--0.pdf 21-Apr-2026 02:45:11 342493
wst04-VHDL20_DWSG_210400-2604210400-omedes--0.pdf 21-Apr-2026 05:15:11 337925
wst04-VHDL20_DWSG_210800-2604210800-omedes--0.pdf 21-Apr-2026 08:30:17 340333
wst04-VHDL20_DWSG_211800-2604211800-omedes--0.pdf 21-Apr-2026 18:30:12 330173
wst04-VHDL20_DWSG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 328785
wst04-VHDL20_DWSG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 329556