Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Jan-2026 14:08:44 2637
FPDL13_DWMZ_130600 13-Jan-2026 15:00:41 6589
SXDL31_DWAV_111800 11-Jan-2026 17:57:43 9990
SXDL31_DWAV_120800 12-Jan-2026 10:14:58 8522
SXDL31_DWAV_121800 12-Jan-2026 16:13:15 11323
SXDL31_DWAV_130800 13-Jan-2026 08:01:59 14718
SXDL31_DWAV_LATEST 13-Jan-2026 08:01:59 14718
SXDL33_DWAV_120000 12-Jan-2026 11:27:29 6347
SXDL33_DWAV_130000 13-Jan-2026 10:27:03 6393
SXDL33_DWAV_LATEST 13-Jan-2026 10:27:03 6393
ber01-FWDL39_DWMS_121230-2601121230-dsw--0-ia5 12-Jan-2026 12:29:01 2010
ber01-FWDL39_DWMS_131230-2601131230-dsw--0-ia5 13-Jan-2026 12:34:11 1994
ber01-VHDL13_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 4021
ber01-VHDL13_DWEH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3924
ber01-VHDL13_DWEH_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:12 3684
ber01-VHDL13_DWEH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:16 2912
ber01-VHDL13_DWEH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:28:16 2198
ber01-VHDL13_DWEH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2667
ber01-VHDL13_DWEH_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:17 2689
ber01-VHDL13_DWEH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:15 2562
ber01-VHDL13_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4635
ber01-VHDL13_DWHG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4318
ber01-VHDL13_DWHG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4000
ber01-VHDL13_DWHG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3712
ber01-VHDL13_DWHG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2759
ber01-VHDL13_DWHG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2524
ber01-VHDL13_DWHG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2448
ber01-VHDL13_DWHG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 3141
ber01-VHDL13_DWHG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:56:28 3303
ber01-VHDL13_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:06 4090
ber01-VHDL13_DWHH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4174
ber01-VHDL13_DWHH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3974
ber01-VHDL13_DWHH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3936
ber01-VHDL13_DWHH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2508
ber01-VHDL13_DWHH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2340
ber01-VHDL13_DWHH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2349
ber01-VHDL13_DWHH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 2524
ber01-VHDL13_DWHH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:56:42 2818
ber01-VHDL13_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2815
ber01-VHDL13_DWLG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3383
ber01-VHDL13_DWLG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3296
ber01-VHDL13_DWLG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3258
ber01-VHDL13_DWLG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 3020
ber01-VHDL13_DWLG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2683
ber01-VHDL13_DWLG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2442
ber01-VHDL13_DWLG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2431
ber01-VHDL13_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2928
ber01-VHDL13_DWLH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3293
ber01-VHDL13_DWLH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3217
ber01-VHDL13_DWLH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 3078
ber01-VHDL13_DWLH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2686
ber01-VHDL13_DWLH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2389
ber01-VHDL13_DWLH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2222
ber01-VHDL13_DWLH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2232
ber01-VHDL13_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2798
ber01-VHDL13_DWLI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3044
ber01-VHDL13_DWLI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 2928
ber01-VHDL13_DWLI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2921
ber01-VHDL13_DWLI_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2436
ber01-VHDL13_DWLI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2341
ber01-VHDL13_DWLI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2030
ber01-VHDL13_DWLI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2148
ber01-VHDL13_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3285
ber01-VHDL13_DWMG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3400
ber01-VHDL13_DWMG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3400
ber01-VHDL13_DWMG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 4048
ber01-VHDL13_DWMG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 3172
ber01-VHDL13_DWMG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 4071
ber01-VHDL13_DWMG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4099
ber01-VHDL13_DWMG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 3673
ber01-VHDL13_DWMG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:56:02 3752
ber01-VHDL13_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3292
ber01-VHDL13_DWMO_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3530
ber01-VHDL13_DWMO_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3530
ber01-VHDL13_DWMO_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 3718
ber01-VHDL13_DWMO_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 3687
ber01-VHDL13_DWMO_121800_COR-2601121800-dsw--0-ia5 12-Jan-2026 19:39:37 2603
ber01-VHDL13_DWMO_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 3997
ber01-VHDL13_DWMO_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4145
ber01-VHDL13_DWMO_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 4145
ber01-VHDL13_DWMO_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:56:43 3834
ber01-VHDL13_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 3551
ber01-VHDL13_DWMP_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 3723
ber01-VHDL13_DWMP_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 3723
ber01-VHDL13_DWMP_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 4178
ber01-VHDL13_DWMP_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 3353
ber01-VHDL13_DWMP_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 4063
ber01-VHDL13_DWMP_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 4075
ber01-VHDL13_DWMP_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 4075
ber01-VHDL13_DWMP_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 11:57:36 3394
ber01-VHDL13_DWOG_111700-2601111700-dsw--0-ia5 11-Jan-2026 19:00:01 5442
ber01-VHDL13_DWOG_120300-2601120300-dsw--0-ia5 12-Jan-2026 04:00:04 5098
ber01-VHDL13_DWOG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 5559
ber01-VHDL13_DWOG_121700-2601121700-dsw--0-ia5 12-Jan-2026 19:00:07 4642
ber01-VHDL13_DWOG_130300-2601130300-dsw--0-ia5 13-Jan-2026 06:52:37 5144
ber01-VHDL13_DWOG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:07 4697
ber01-VHDL13_DWOH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:17 3596
ber01-VHDL13_DWOH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3406
ber01-VHDL13_DWOH_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:12 3327
ber01-VHDL13_DWOH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:16 2957
ber01-VHDL13_DWOH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:28:16 2249
ber01-VHDL13_DWOH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2446
ber01-VHDL13_DWOH_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:12 2223
ber01-VHDL13_DWOH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:15 2150
ber01-VHDL13_DWOH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:55:57 2467
ber01-VHDL13_DWOI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:28:11 3118
ber01-VHDL13_DWOI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:28:11 3062
ber01-VHDL13_DWOI_120400-2601120400-dsw--0-ia5 12-Jan-2026 05:58:16 2981
ber01-VHDL13_DWOI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:28:12 2590
ber01-VHDL13_DWOI_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:28:12 2124
ber01-VHDL13_DWOI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:28:12 2114
ber01-VHDL13_DWOI_130400-2601130400-dsw--0-ia5 13-Jan-2026 05:58:17 2152
ber01-VHDL13_DWOI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:28:11 2194
ber01-VHDL13_DWON_111852-2601111852-dsw--0-ia5 11-Jan-2026 18:52:26 3768
ber01-VHDL13_DWON_112238-2601112238-dsw--0-ia5 11-Jan-2026 22:38:31 3859
ber01-VHDL13_DWON_112357-2601112357-dsw--0-ia5 11-Jan-2026 23:57:46 3615
ber01-VHDL13_DWON_120620-2601120620-dsw--0-ia5 12-Jan-2026 06:20:47 3583
ber01-VHDL13_DWON_120718-2601120718-dsw--0-ia5 12-Jan-2026 07:18:37 3712
ber01-VHDL13_DWON_120911-2601120911-dsw--0-ia5 12-Jan-2026 09:11:57 3712
ber01-VHDL13_DWON_121537-2601121537-dsw--0-ia5 12-Jan-2026 15:37:52 3643
ber01-VHDL13_DWON_121756-2601121756-dsw--0-ia5 12-Jan-2026 17:56:12 3613
ber01-VHDL13_DWON_121841-2601121841-dsw--0-ia5 12-Jan-2026 18:41:21 3613
ber01-VHDL13_DWON_130222-2601130222-dsw--0-ia5 13-Jan-2026 02:22:21 3922
ber01-VHDL13_DWON_130409-2601130409-dsw--0-ia5 13-Jan-2026 04:09:17 3922
ber01-VHDL13_DWON_130629-2601130629-dsw--0-ia5 13-Jan-2026 06:29:46 4124
ber01-VHDL13_DWON_130719-2601130719-dsw--0-ia5 13-Jan-2026 07:19:52 4136
ber01-VHDL13_DWON_130923-2601130923-dsw--0-ia5 13-Jan-2026 09:23:06 4123
ber01-VHDL13_DWON_131211-2601131211-dsw--0-ia5 13-Jan-2026 12:11:57 3775
ber01-VHDL13_DWON_131524-2601131524-dsw--0-ia5 13-Jan-2026 15:24:12 3450
ber01-VHDL13_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2546
ber01-VHDL13_DWPG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 2789
ber01-VHDL13_DWPG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3101
ber01-VHDL13_DWPG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2964
ber01-VHDL13_DWPG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:25:46 3121
ber01-VHDL13_DWPG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2998
ber01-VHDL13_DWPG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2665
ber01-VHDL13_DWPG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2597
ber01-VHDL13_DWPG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2500
ber01-VHDL13_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:00 2466
ber01-VHDL13_DWPH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:02 2709
ber01-VHDL13_DWPH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:01 3056
ber01-VHDL13_DWPH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:13 2919
ber01-VHDL13_DWPH_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:26:31 3165
ber01-VHDL13_DWPH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:07 2941
ber01-VHDL13_DWPH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:06 2633
ber01-VHDL13_DWPH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:02 2623
ber01-VHDL13_DWPH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:01 2567
ber01-VHDL13_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:30:02 4093
ber01-VHDL13_DWSG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:30:08 4102
ber01-VHDL13_DWSG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4160
ber01-VHDL13_DWSG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:30:01 3731
ber01-VHDL13_DWSG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 12:21:21 3230
ber01-VHDL13_DWSG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:30:01 3178
ber01-VHDL13_DWSG_121800_COR-2601121800-dsw--0-ia5 12-Jan-2026 19:30:43 3182
ber01-VHDL13_DWSG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:30:07 3741
ber01-VHDL13_DWSG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2661
ber01-VHDL13_DWSG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:30:04 3103
ber01-VHDL17_DWOG_121200-2601121200-dsw--0-ia5 12-Jan-2026 12:23:26 2344
ber01-VHDL17_DWOG_131200-2601131200-dsw--0-ia5 13-Jan-2026 12:03:31 2354
swis2-VHDL20_DWEG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4211
swis2-VHDL20_DWEG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3951
swis2-VHDL20_DWEG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3733
swis2-VHDL20_DWEG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3521
swis2-VHDL20_DWEG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:04 2661
swis2-VHDL20_DWEG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2847
swis2-VHDL20_DWEG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 2543
swis2-VHDL20_DWEG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 2632
swis2-VHDL20_DWEG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:17 3074
swis2-VHDL20_DWEH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4647
swis2-VHDL20_DWEH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 4414
swis2-VHDL20_DWEH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4082
swis2-VHDL20_DWEH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3480
swis2-VHDL20_DWEH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:04 2682
swis2-VHDL20_DWEH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3101
swis2-VHDL20_DWEH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 3023
swis2-VHDL20_DWEH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 3068
swis2-VHDL20_DWEI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3741
swis2-VHDL20_DWEI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3525
swis2-VHDL20_DWEI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3335
swis2-VHDL20_DWEI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 3117
swis2-VHDL20_DWEI_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:04 2478
swis2-VHDL20_DWEI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2408
swis2-VHDL20_DWEI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 2505
swis2-VHDL20_DWEI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:06 2722
swis2-VHDL20_DWHG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4818
swis2-VHDL20_DWHG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4504
swis2-VHDL20_DWHG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4183
swis2-VHDL20_DWHG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4248
swis2-VHDL20_DWHG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:04 2942
swis2-VHDL20_DWHG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 2710
swis2-VHDL20_DWHG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2631
swis2-VHDL20_DWHG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4021
swis2-VHDL20_DWHG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:34 4296
swis2-VHDL20_DWHH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:01 4276
swis2-VHDL20_DWHH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4360
swis2-VHDL20_DWHH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:05 4160
swis2-VHDL20_DWHH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:06 4479
swis2-VHDL20_DWHH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:04 2694
swis2-VHDL20_DWHH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 2526
swis2-VHDL20_DWHH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:06 2535
swis2-VHDL20_DWHH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3204
swis2-VHDL20_DWHH_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 14:57:55 3790
swis2-VHDL20_DWLG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3230
swis2-VHDL20_DWLG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3885
swis2-VHDL20_DWLG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3774
swis2-VHDL20_DWLG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3868
swis2-VHDL20_DWLG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3543
swis2-VHDL20_DWLG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3211
swis2-VHDL20_DWLG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2811
swis2-VHDL20_DWLG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3066
swis2-VHDL20_DWLH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3334
swis2-VHDL20_DWLH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3808
swis2-VHDL20_DWLH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3726
swis2-VHDL20_DWLH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3723
swis2-VHDL20_DWLH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3163
swis2-VHDL20_DWLH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2831
swis2-VHDL20_DWLH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2599
swis2-VHDL20_DWLH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 2881
swis2-VHDL20_DWLI_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3199
swis2-VHDL20_DWLI_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3554
swis2-VHDL20_DWLI_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3408
swis2-VHDL20_DWLI_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3532
swis2-VHDL20_DWLI_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 2908
swis2-VHDL20_DWLI_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 2780
swis2-VHDL20_DWLI_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2402
swis2-VHDL20_DWLI_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 2785
swis2-VHDL20_DWMG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3870
swis2-VHDL20_DWMG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 3982
swis2-VHDL20_DWMG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 3911
swis2-VHDL20_DWMG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4828
swis2-VHDL20_DWMG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3702
swis2-VHDL20_DWMG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4631
swis2-VHDL20_DWMG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4627
swis2-VHDL20_DWMG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4455
swis2-VHDL20_DWMG_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:03:23 4534
swis2-VHDL20_DWMO_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3888
swis2-VHDL20_DWMO_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4118
swis2-VHDL20_DWMO_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4048
swis2-VHDL20_DWMO_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4525
swis2-VHDL20_DWMO_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3084
swis2-VHDL20_DWMO_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4557
swis2-VHDL20_DWMO_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4665
swis2-VHDL20_DWMO_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4569
swis2-VHDL20_DWMO_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:03:50 4590
swis2-VHDL20_DWMP_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 4114
swis2-VHDL20_DWMP_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:06 4312
swis2-VHDL20_DWMP_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:07 4236
swis2-VHDL20_DWMP_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 5165
swis2-VHDL20_DWMP_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3879
swis2-VHDL20_DWMP_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:07 4589
swis2-VHDL20_DWMP_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:06 4504
swis2-VHDL20_DWMP_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 4058
swis2-VHDL20_DWMP_130800_COR-2601130800-dsw--0-ia5 13-Jan-2026 12:05:27 4086
swis2-VHDL20_DWPG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3096
swis2-VHDL20_DWPG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3127
swis2-VHDL20_DWPG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3666
swis2-VHDL20_DWPG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3718
swis2-VHDL20_DWPG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:31:22 3875
swis2-VHDL20_DWPG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3628
swis2-VHDL20_DWPG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3121
swis2-VHDL20_DWPG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2950
swis2-VHDL20_DWPG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3249
swis2-VHDL20_DWPH_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:07 3015
swis2-VHDL20_DWPH_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 3046
swis2-VHDL20_DWPH_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:00:11 3617
swis2-VHDL20_DWPH_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 3644
swis2-VHDL20_DWPH_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 14:31:50 3890
swis2-VHDL20_DWPH_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3549
swis2-VHDL20_DWPH_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 3088
swis2-VHDL20_DWPH_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:00:12 2985
swis2-VHDL20_DWPH_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3168
swis2-VHDL20_DWSG_111800-2601111800-dsw--0-ia5 11-Jan-2026 19:45:03 4619
swis2-VHDL20_DWSG_120200-2601120200-dsw--0-ia5 12-Jan-2026 03:45:02 4618
swis2-VHDL20_DWSG_120400-2601120400-dsw--0-ia5 12-Jan-2026 06:15:02 4561
swis2-VHDL20_DWSG_120800-2601120800-dsw--0-ia5 12-Jan-2026 09:45:02 4330
swis2-VHDL20_DWSG_120800_COR-2601120800-dsw--0-ia5 12-Jan-2026 12:21:21 3811
swis2-VHDL20_DWSG_121300-2601121300-dsw--0-ia5 12-Jan-2026 14:45:09 3689
swis2-VHDL20_DWSG_121800-2601121800-dsw--0-ia5 12-Jan-2026 19:45:06 3615
swis2-VHDL20_DWSG_121800_COR-2601121800-dsw--0-ia5 12-Jan-2026 19:30:43 3619
swis2-VHDL20_DWSG_130200-2601130200-dsw--0-ia5 13-Jan-2026 03:45:02 4191
swis2-VHDL20_DWSG_130400-2601130400-dsw--0-ia5 13-Jan-2026 06:15:03 3766
swis2-VHDL20_DWSG_130800-2601130800-dsw--0-ia5 13-Jan-2026 09:45:01 3758
swis2-VHDL20_DWSG_131300-2601131300-dsw--0-ia5 13-Jan-2026 14:45:02 3529
wst04-VHDL20_DWEG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 230426
wst04-VHDL20_DWEG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 231007
wst04-VHDL20_DWEG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:26 230571
wst04-VHDL20_DWEG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 240378
wst04-VHDL20_DWEG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:16 237606
wst04-VHDL20_DWEG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 238438
wst04-VHDL20_DWEG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 236860
wst04-VHDL20_DWEG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:22 238128
wst04-VHDL20_DWEH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 233710
wst04-VHDL20_DWEH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 233772
wst04-VHDL20_DWEH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 232437
wst04-VHDL20_DWEH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 232516
wst04-VHDL20_DWEH_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:12 230165
wst04-VHDL20_DWEH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 231678
wst04-VHDL20_DWEH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 230971
wst04-VHDL20_DWEH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 230893
wst04-VHDL20_DWEI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:11 318758
wst04-VHDL20_DWEI_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:15 318680
wst04-VHDL20_DWEI_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:26 317981
wst04-VHDL20_DWEI_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:22 334392
wst04-VHDL20_DWEI_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:16 333009
wst04-VHDL20_DWEI_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 332794
wst04-VHDL20_DWEI_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:28 332313
wst04-VHDL20_DWEI_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:22 332422
wst04-VHDL20_DWHG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 309251
wst04-VHDL20_DWHG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 309134
wst04-VHDL20_DWHG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:11 308103
wst04-VHDL20_DWHG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 314108
wst04-VHDL20_DWHG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:21 311240
wst04-VHDL20_DWHG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 310686
wst04-VHDL20_DWHG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:12 310592
wst04-VHDL20_DWHG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:18 312698
wst04-VHDL20_DWHH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 301685
wst04-VHDL20_DWHH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 301620
wst04-VHDL20_DWHH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:11 301445
wst04-VHDL20_DWHH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 307493
wst04-VHDL20_DWHH_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:16 304218
wst04-VHDL20_DWHH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 303695
wst04-VHDL20_DWHH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:12 303691
wst04-VHDL20_DWHH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:18 304276
wst04-VHDL20_DWLG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 304475
wst04-VHDL20_DWLG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 305713
wst04-VHDL20_DWLG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 305574
wst04-VHDL20_DWLG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:36 310289
wst04-VHDL20_DWLG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:27 309405
wst04-VHDL20_DWLG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 309726
wst04-VHDL20_DWLG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 309465
wst04-VHDL20_DWLG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 309818
wst04-VHDL20_DWLH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 303368
wst04-VHDL20_DWLH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 304046
wst04-VHDL20_DWLH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 303919
wst04-VHDL20_DWLH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:32 311581
wst04-VHDL20_DWLH_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:21 310434
wst04-VHDL20_DWLH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:26 310175
wst04-VHDL20_DWLH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 310177
wst04-VHDL20_DWLH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 310553
wst04-VHDL20_DWLI_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 307672
wst04-VHDL20_DWLI_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 307919
wst04-VHDL20_DWLI_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:42 307709
wst04-VHDL20_DWLI_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:32 318897
wst04-VHDL20_DWLI_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:21 317461
wst04-VHDL20_DWLI_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 317647
wst04-VHDL20_DWLI_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:41 317623
wst04-VHDL20_DWLI_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 318194
wst04-VHDL20_DWMG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 516689
wst04-VHDL20_DWMG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 516640
wst04-VHDL20_DWMG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 516563
wst04-VHDL20_DWMG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 522652
wst04-VHDL20_DWMG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:16 520309
wst04-VHDL20_DWMG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 521752
wst04-VHDL20_DWMG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:21 521071
wst04-VHDL20_DWMG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 520848
wst04-VHDL20_DWMG_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:01:16 520712
wst04-VHDL20_DWMO_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 418583
wst04-VHDL20_DWMO_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:17 418508
wst04-VHDL20_DWMO_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:16 418906
wst04-VHDL20_DWMO_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:12 421098
wst04-VHDL20_DWMO_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:12 418601
wst04-VHDL20_DWMO_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:16 420426
wst04-VHDL20_DWMO_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 421391
wst04-VHDL20_DWMO_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 420643
wst04-VHDL20_DWMO_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:01:52 416440
wst04-VHDL20_DWMP_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:17 543939
wst04-VHDL20_DWMP_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:17 541939
wst04-VHDL20_DWMP_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:22 543723
wst04-VHDL20_DWMP_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:16 558286
wst04-VHDL20_DWMP_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:16 555949
wst04-VHDL20_DWMP_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 555155
wst04-VHDL20_DWMP_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 557127
wst04-VHDL20_DWMP_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:16 556297
wst04-VHDL20_DWMP_130800_COR-2601130800-omedes-..> 13-Jan-2026 12:06:02 545355
wst04-VHDL20_DWPG_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:27 306905
wst04-VHDL20_DWPG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:25 306879
wst04-VHDL20_DWPG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:31 307095
wst04-VHDL20_DWPG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:26 356558
wst04-VHDL20_DWPG_120800_COR-2601120800-omedes-..> 12-Jan-2026 14:30:45 356673
wst04-VHDL20_DWPG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:27 311395
wst04-VHDL20_DWPG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:26 311145
wst04-VHDL20_DWPG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:31 311326
wst04-VHDL20_DWPG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:31 356167
wst04-VHDL20_DWPH_111800-2601111800-omedes--0.pdf 11-Jan-2026 19:45:21 267645
wst04-VHDL20_DWPH_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:21 222938
wst04-VHDL20_DWPH_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:00:31 223309
wst04-VHDL20_DWPH_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:26 268248
wst04-VHDL20_DWPH_120800_COR-2601120800-omedes-..> 12-Jan-2026 14:29:22 268528
wst04-VHDL20_DWPH_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:21 267968
wst04-VHDL20_DWPH_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:22 222305
wst04-VHDL20_DWPH_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:00:31 222649
wst04-VHDL20_DWPH_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:26 267514
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wst04-VHDL20_DWSG_120200-2601120200-omedes--0.pdf 12-Jan-2026 03:45:11 337465
wst04-VHDL20_DWSG_120400-2601120400-omedes--0.pdf 12-Jan-2026 06:15:16 337463
wst04-VHDL20_DWSG_120800-2601120800-omedes--0.pdf 12-Jan-2026 09:45:12 344350
wst04-VHDL20_DWSG_120800_COR-2601120800-omedes-..> 12-Jan-2026 12:21:31 342980
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wst04-VHDL20_DWSG_121800-2601121800-omedes--0.pdf 12-Jan-2026 19:45:12 342893
wst04-VHDL20_DWSG_121800_COR-2601121800-omedes-..> 12-Jan-2026 19:30:43 342893
wst04-VHDL20_DWSG_130200-2601130200-omedes--0.pdf 13-Jan-2026 03:45:12 343173
wst04-VHDL20_DWSG_130400-2601130400-omedes--0.pdf 13-Jan-2026 06:15:17 342787
wst04-VHDL20_DWSG_130800-2601130800-omedes--0.pdf 13-Jan-2026 09:45:12 342568
wst04-VHDL20_DWSG_131300-2601131300-omedes--0.pdf 13-Jan-2026 14:45:11 325692