Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Sep-2026 12:52:49 3543
FPDL13_DWMZ_180600 18-Sep-2026 11:46:09 3783
SXDL31_DWAV_170800 17-Sep-2026 07:13:04 14433
SXDL31_DWAV_171800 17-Sep-2026 16:31:12 6051
SXDL31_DWAV_180800 18-Sep-2026 07:13:54 14979
SXDL31_DWAV_181800 18-Sep-2026 17:05:45 6129
SXDL31_DWAV_LATEST 18-Sep-2026 17:05:45 6129
SXDL33_DWAV_170000 17-Sep-2026 10:47:50 7412
SXDL33_DWAV_180000 18-Sep-2026 10:03:20 5102
SXDL33_DWAV_LATEST 18-Sep-2026 10:03:20 5102
ber01-FWDL39_DWMS_171200-2609171200-dsw--0-ia5 17-Sep-2026 10:35:33 1882
ber01-FWDL39_DWMS_181200-2609181200-dsw--0-ia5 18-Sep-2026 11:07:25 1195
ber01-VHDL13_DWEG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:28:18 2644
ber01-VHDL13_DWEG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:18 2621
ber01-VHDL13_DWEH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:28:14 2556
ber01-VHDL13_DWEH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:14 2596
ber01-VHDL13_DWEI_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:28:14 2706
ber01-VHDL13_DWEI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:18 2550
ber01-VHDL13_DWHG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:12 3617
ber01-VHDL13_DWHG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 3538
ber01-VHDL13_DWHH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:12 3710
ber01-VHDL13_DWHH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 3604
ber01-VHDL13_DWLG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2364
ber01-VHDL13_DWLG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2424
ber01-VHDL13_DWLH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2844
ber01-VHDL13_DWLH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2686
ber01-VHDL13_DWLI_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2438
ber01-VHDL13_DWLI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2440
ber01-VHDL13_DWMO_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 3026
ber01-VHDL13_DWMO_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 2844
ber01-VHDL13_DWMP_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2635
ber01-VHDL13_DWMP_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 2795
ber01-VHDL13_DWOG_170300-2609170300-dsw--0-ia5 17-Sep-2026 03:00:46 3523
ber01-VHDL13_DWOG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:12 4067
ber01-VHDL13_DWOG_170800_COR-2609170800-dsw--0-ia5 17-Sep-2026 08:53:29 4008
ber01-VHDL13_DWOG_171700-2609171700-dsw--0-ia5 17-Sep-2026 18:00:04 3606
ber01-VHDL13_DWOG_180300-2609180300-dsw--0-ia5 18-Sep-2026 03:00:03 3615
ber01-VHDL13_DWOG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:11 3950
ber01-VHDL13_DWOG_181700-2609181700-dsw--0-ia5 18-Sep-2026 18:00:06 3889
ber01-VHDL13_DWON_170141-2609170141-dsw--0-ia5 17-Sep-2026 01:41:33 3021
ber01-VHDL13_DWON_170529-2609170529-dsw--0-ia5 17-Sep-2026 05:29:33 3255
ber01-VHDL13_DWON_170540-2609170540-dsw--0-ia5 17-Sep-2026 05:41:03 3879
ber01-VHDL13_DWON_170559-2609170559-dsw--0-ia5 17-Sep-2026 05:59:09 4052
ber01-VHDL13_DWON_170848-2609170848-dsw--0-ia5 17-Sep-2026 08:49:28 4052
ber01-VHDL13_DWON_171447-2609171447-dsw--0-ia5 17-Sep-2026 14:47:50 3494
ber01-VHDL13_DWON_171744-2609171744-dsw--0-ia5 17-Sep-2026 17:44:32 3514
ber01-VHDL13_DWON_180130-2609180130-dsw--0-ia5 18-Sep-2026 01:30:29 3301
ber01-VHDL13_DWON_180419-2609180419-dsw--0-ia5 18-Sep-2026 04:20:25 3301
ber01-VHDL13_DWON_180523-2609180523-dsw--0-ia5 18-Sep-2026 05:23:22 3964
ber01-VHDL13_DWON_180839-2609180839-dsw--0-ia5 18-Sep-2026 08:39:23 3911
ber01-VHDL13_DWON_181357-2609181357-dsw--0-ia5 18-Sep-2026 13:57:29 3798
ber01-VHDL13_DWON_181710-2609181710-dsw--0-ia5 18-Sep-2026 17:10:53 3361
ber01-VHDL13_DWPG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2286
ber01-VHDL13_DWPG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2254
ber01-VHDL13_DWPH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 2649
ber01-VHDL13_DWPH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2411
ber01-VHDL13_DWSG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:12 2323
ber01-VHDL13_DWSG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2585
ber01-VHDL17_DWOG_171200-2609171200-dsw--0-ia5 17-Sep-2026 11:45:34 2351
ber01-VHDL17_DWOG_181200-2609181200-dsw--0-ia5 18-Sep-2026 12:03:24 2068
swis2-VHDL20_DWEG_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 1188
swis2-VHDL20_DWEG_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:01:30 1031
swis2-VHDL20_DWEG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 1280
swis2-VHDL20_DWEG_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:04 1298
swis2-VHDL20_DWEG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1101
swis2-VHDL20_DWEG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1078
swis2-VHDL20_DWEG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1293
swis2-VHDL20_DWEG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1388
swis2-VHDL20_DWEH_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 1199
swis2-VHDL20_DWEH_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:01:30 1045
swis2-VHDL20_DWEH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 1288
swis2-VHDL20_DWEH_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:04 1324
swis2-VHDL20_DWEH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1115
swis2-VHDL20_DWEH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1092
swis2-VHDL20_DWEH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1230
swis2-VHDL20_DWEH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1445
swis2-VHDL20_DWEI_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 1199
swis2-VHDL20_DWEI_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:01:30 1053
swis2-VHDL20_DWEI_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 1276
swis2-VHDL20_DWEI_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:04 1295
swis2-VHDL20_DWEI_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1123
swis2-VHDL20_DWEI_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1100
swis2-VHDL20_DWEI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1284
swis2-VHDL20_DWEI_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1334
swis2-VHDL20_DWHG_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:45:11 1367
swis2-VHDL20_DWHG_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 1466
swis2-VHDL20_DWHG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:45:51 1805
swis2-VHDL20_DWHG_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:45:06 2461
swis2-VHDL20_DWHG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:46:01 1585
swis2-VHDL20_DWHG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 1582
swis2-VHDL20_DWHG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:45:13 2028
swis2-VHDL20_DWHG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:45:10 2560
swis2-VHDL20_DWHH_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:45:11 1586
swis2-VHDL20_DWHH_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 1699
swis2-VHDL20_DWHH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:45:51 2101
swis2-VHDL20_DWHH_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:45:06 3178
swis2-VHDL20_DWHH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:46:01 2027
swis2-VHDL20_DWHH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 2027
swis2-VHDL20_DWHH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:45:13 2386
swis2-VHDL20_DWHH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:45:10 3192
swis2-VHDL20_DWLG_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:31 862
swis2-VHDL20_DWLG_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 850
swis2-VHDL20_DWLG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:31 938
swis2-VHDL20_DWLG_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:31:14 936
swis2-VHDL20_DWLG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 880
swis2-VHDL20_DWLG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 834
swis2-VHDL20_DWLG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 980
swis2-VHDL20_DWLG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 883
swis2-VHDL20_DWLH_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:31 998
swis2-VHDL20_DWLH_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 1049
swis2-VHDL20_DWLH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:31 1318
swis2-VHDL20_DWLH_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:31:14 1236
swis2-VHDL20_DWLH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 1067
swis2-VHDL20_DWLH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 982
swis2-VHDL20_DWLH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1287
swis2-VHDL20_DWLH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1117
swis2-VHDL20_DWLI_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:31 864
swis2-VHDL20_DWLI_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 874
swis2-VHDL20_DWLI_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:31 962
swis2-VHDL20_DWLI_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:31:14 899
swis2-VHDL20_DWLI_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 882
swis2-VHDL20_DWLI_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 836
swis2-VHDL20_DWLI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 914
swis2-VHDL20_DWLI_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 776
swis2-VHDL20_DWMO_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 918
swis2-VHDL20_DWMO_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:10 886
swis2-VHDL20_DWMO_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 1050
swis2-VHDL20_DWMO_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:04 1358
swis2-VHDL20_DWMO_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1060
swis2-VHDL20_DWMO_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:15 1037
swis2-VHDL20_DWMO_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 1330
swis2-VHDL20_DWMO_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1243
swis2-VHDL20_DWMP_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 921
swis2-VHDL20_DWMP_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:10 888
swis2-VHDL20_DWMP_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:03 1059
swis2-VHDL20_DWMP_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:04 1336
swis2-VHDL20_DWMP_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1075
swis2-VHDL20_DWMP_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:15 1043
swis2-VHDL20_DWMP_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 1278
swis2-VHDL20_DWMP_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1177
swis2-VHDL20_DWPG_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:31 912
swis2-VHDL20_DWPG_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 880
swis2-VHDL20_DWPG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:31 984
swis2-VHDL20_DWPG_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:31:14 990
swis2-VHDL20_DWPG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 901
swis2-VHDL20_DWPG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 853
swis2-VHDL20_DWPG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1119
swis2-VHDL20_DWPG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1023
swis2-VHDL20_DWPH_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:31 1125
swis2-VHDL20_DWPH_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 1172
swis2-VHDL20_DWPH_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:31 1329
swis2-VHDL20_DWPH_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:31:14 1241
swis2-VHDL20_DWPH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 1076
swis2-VHDL20_DWPH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 895
swis2-VHDL20_DWPH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1201
swis2-VHDL20_DWPH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1114
swis2-VHDL20_DWSG_170200-2609170200-dsw--0-ia5 17-Sep-2026 02:30:13 918
swis2-VHDL20_DWSG_170400-2609170400-dsw--0-ia5 17-Sep-2026 05:00:17 889
swis2-VHDL20_DWSG_170800-2609170800-dsw--0-ia5 17-Sep-2026 08:30:12 954
swis2-VHDL20_DWSG_171800-2609171800-dsw--0-ia5 17-Sep-2026 18:30:02 1076
swis2-VHDL20_DWSG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1031
swis2-VHDL20_DWSG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 1031
swis2-VHDL20_DWSG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1083
swis2-VHDL20_DWSG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 941
wst04-VHDL20_DWEG_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:18 245012
wst04-VHDL20_DWEG_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 245009
wst04-VHDL20_DWEG_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:13 246579
wst04-VHDL20_DWEG_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:22 243941
wst04-VHDL20_DWEG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 242912
wst04-VHDL20_DWEG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 242823
wst04-VHDL20_DWEG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 243753
wst04-VHDL20_DWEG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 244169
wst04-VHDL20_DWEH_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:18 236300
wst04-VHDL20_DWEH_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 236508
wst04-VHDL20_DWEH_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:13 238089
wst04-VHDL20_DWEH_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:22 234489
wst04-VHDL20_DWEH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 233748
wst04-VHDL20_DWEH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 233879
wst04-VHDL20_DWEH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 234723
wst04-VHDL20_DWEH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 234009
wst04-VHDL20_DWEI_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:25 347467
wst04-VHDL20_DWEI_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 347386
wst04-VHDL20_DWEI_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:13 348408
wst04-VHDL20_DWEI_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:30 345852
wst04-VHDL20_DWEI_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 345429
wst04-VHDL20_DWEI_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 345255
wst04-VHDL20_DWEI_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 345658
wst04-VHDL20_DWEI_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 348484
wst04-VHDL20_DWHG_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:46:16 336451
wst04-VHDL20_DWHG_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 336740
wst04-VHDL20_DWHG_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:45:51 337671
wst04-VHDL20_DWHG_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:45:14 327019
wst04-VHDL20_DWHG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:46:18 325071
wst04-VHDL20_DWHG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 324865
wst04-VHDL20_DWHG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:45:41 326622
wst04-VHDL20_DWHG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:45:14 332698
wst04-VHDL20_DWHH_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:46:16 331190
wst04-VHDL20_DWHH_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 231117
wst04-VHDL20_DWHH_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:45:51 332237
wst04-VHDL20_DWHH_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:45:14 330589
wst04-VHDL20_DWHH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:46:18 329328
wst04-VHDL20_DWHH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 230561
wst04-VHDL20_DWHH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:45:41 329501
wst04-VHDL20_DWHH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:45:14 330407
wst04-VHDL20_DWLG_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:31 338381
wst04-VHDL20_DWLG_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:44 338653
wst04-VHDL20_DWLG_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:52 339120
wst04-VHDL20_DWLG_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:31:25 327698
wst04-VHDL20_DWLG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 327255
wst04-VHDL20_DWLG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 327307
wst04-VHDL20_DWLG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:51 327843
wst04-VHDL20_DWLG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 329464
wst04-VHDL20_DWLH_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:31 333292
wst04-VHDL20_DWLH_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:44 333558
wst04-VHDL20_DWLH_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:52 333892
wst04-VHDL20_DWLH_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:31:25 327065
wst04-VHDL20_DWLH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 326425
wst04-VHDL20_DWLH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 326413
wst04-VHDL20_DWLH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 327222
wst04-VHDL20_DWLH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 328306
wst04-VHDL20_DWLI_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:31 336675
wst04-VHDL20_DWLI_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:44 336922
wst04-VHDL20_DWLI_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:52 381973
wst04-VHDL20_DWLI_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:31:29 329965
wst04-VHDL20_DWLI_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 329540
wst04-VHDL20_DWLI_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 329574
wst04-VHDL20_DWLI_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 374651
wst04-VHDL20_DWLI_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 330112
wst04-VHDL20_DWMO_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:18 446004
wst04-VHDL20_DWMO_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 446152
wst04-VHDL20_DWMO_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:19 446395
wst04-VHDL20_DWMO_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:30 336290
wst04-VHDL20_DWMO_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:22 434347
wst04-VHDL20_DWMO_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 434263
wst04-VHDL20_DWMO_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:18 434268
wst04-VHDL20_DWMO_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 340289
wst04-VHDL20_DWMP_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:25 572669
wst04-VHDL20_DWMP_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 572716
wst04-VHDL20_DWMP_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:31 465883
wst04-VHDL20_DWMP_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:30 448129
wst04-VHDL20_DWMP_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:22 550282
wst04-VHDL20_DWMP_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 550223
wst04-VHDL20_DWMP_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:24 448023
wst04-VHDL20_DWMP_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 452411
wst04-VHDL20_DWPG_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:31 242297
wst04-VHDL20_DWPG_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:36 347464
wst04-VHDL20_DWPG_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:31:02 392525
wst04-VHDL20_DWPG_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:31:25 325754
wst04-VHDL20_DWPG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:29 232417
wst04-VHDL20_DWPG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:33 324877
wst04-VHDL20_DWPG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 370562
wst04-VHDL20_DWPG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:28 332530
wst04-VHDL20_DWPH_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:31 242245
wst04-VHDL20_DWPH_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:36 243039
wst04-VHDL20_DWPH_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:52 243256
wst04-VHDL20_DWPH_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:31:25 235553
wst04-VHDL20_DWPH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 234719
wst04-VHDL20_DWPH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:33 234184
wst04-VHDL20_DWPH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 234931
wst04-VHDL20_DWPH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 239379
wst04-VHDL20_DWSG_170200-2609170200-omedes--0.pdf 17-Sep-2026 02:30:18 342999
wst04-VHDL20_DWSG_170400-2609170400-omedes--0.pdf 17-Sep-2026 05:00:17 342816
wst04-VHDL20_DWSG_170800-2609170800-omedes--0.pdf 17-Sep-2026 08:30:19 343528
wst04-VHDL20_DWSG_171800-2609171800-omedes--0.pdf 17-Sep-2026 18:30:30 334438
wst04-VHDL20_DWSG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 334522
wst04-VHDL20_DWSG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 334339
wst04-VHDL20_DWSG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:18 334363
wst04-VHDL20_DWSG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 341655