Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_170600                                 17-Oct-2025 13:17:49                3401
FPDL13_DWMZ_180600                                 18-Oct-2025 09:25:53                6045
SXDL31_DWAV_170800                                 17-Oct-2025 06:58:59                5809
SXDL31_DWAV_171800                                 17-Oct-2025 16:11:43                4355
SXDL31_DWAV_180800                                 18-Oct-2025 07:02:13                6673
SXDL31_DWAV_181800                                 18-Oct-2025 15:41:31                4937
SXDL31_DWAV_LATEST                                 18-Oct-2025 15:41:31                4937
SXDL33_DWAV_170000                                 17-Oct-2025 09:22:54                8273
SXDL33_DWAV_180000                                 18-Oct-2025 10:04:09               14144
SXDL33_DWAV_LATEST                                 18-Oct-2025 10:04:09               14144
ber01-FWDL39_DWMS_171230-2510171230-dsw--0-ia5     17-Oct-2025 11:16:41                1733
ber01-FWDL39_DWMS_181230-2510181230-dsw--0-ia5     18-Oct-2025 11:23:27                1910
ber01-VHDL13_DWEH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:28:13                2632
ber01-VHDL13_DWEH_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:58:12                2684
ber01-VHDL13_DWEH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:28:16                2638
ber01-VHDL13_DWEH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:28:16                2597
ber01-VHDL13_DWEH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:28:12                2943
ber01-VHDL13_DWEH_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:58:12                2910
ber01-VHDL13_DWEH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:28:16                2860
ber01-VHDL13_DWEH_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:28:17                2840
ber01-VHDL13_DWHG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:06                3077
ber01-VHDL13_DWHG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:12                3077
ber01-VHDL13_DWHG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:09                3192
ber01-VHDL13_DWHG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:07                2915
ber01-VHDL13_DWHG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:06                2795
ber01-VHDL13_DWHG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:17                2801
ber01-VHDL13_DWHG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:08                2789
ber01-VHDL13_DWHG_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:07                2716
ber01-VHDL13_DWHH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:06                2804
ber01-VHDL13_DWHH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:12                2804
ber01-VHDL13_DWHH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:09                2926
ber01-VHDL13_DWHH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:07                2622
ber01-VHDL13_DWHH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:06                2518
ber01-VHDL13_DWHH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:17                2522
ber01-VHDL13_DWHH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:08                2563
ber01-VHDL13_DWHH_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:07                2490
ber01-VHDL13_DWLG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2305
ber01-VHDL13_DWLG_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:59:56                2423
ber01-VHDL13_DWLG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2601
ber01-VHDL13_DWLG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2271
ber01-VHDL13_DWLG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2552
ber01-VHDL13_DWLG_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:59:56                2376
ber01-VHDL13_DWLG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2384
ber01-VHDL13_DWLG_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                2197
ber01-VHDL13_DWLH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2050
ber01-VHDL13_DWLH_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:59:56                2084
ber01-VHDL13_DWLH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2266
ber01-VHDL13_DWLH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                1990
ber01-VHDL13_DWLH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2242
ber01-VHDL13_DWLH_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:59:56                2198
ber01-VHDL13_DWLH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2135
ber01-VHDL13_DWLH_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                1961
ber01-VHDL13_DWLI_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2080
ber01-VHDL13_DWLI_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:59:56                2104
ber01-VHDL13_DWLI_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2279
ber01-VHDL13_DWLI_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2005
ber01-VHDL13_DWLI_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2287
ber01-VHDL13_DWLI_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:59:56                2162
ber01-VHDL13_DWLI_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2113
ber01-VHDL13_DWLI_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                1924
ber01-VHDL13_DWMG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2773
ber01-VHDL13_DWMG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2786
ber01-VHDL13_DWMG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2990
ber01-VHDL13_DWMG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2763
ber01-VHDL13_DWMG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2629
ber01-VHDL13_DWMG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2636
ber01-VHDL13_DWMG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2817
ber01-VHDL13_DWMG_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                2498
ber01-VHDL13_DWMO_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2391
ber01-VHDL13_DWMO_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2428
ber01-VHDL13_DWMO_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2763
ber01-VHDL13_DWMO_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2473
ber01-VHDL13_DWMO_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2366
ber01-VHDL13_DWMO_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2384
ber01-VHDL13_DWMO_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2464
ber01-VHDL13_DWMO_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                2140
ber01-VHDL13_DWMP_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2897
ber01-VHDL13_DWMP_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2937
ber01-VHDL13_DWMP_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                3234
ber01-VHDL13_DWMP_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                3027
ber01-VHDL13_DWMP_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2712
ber01-VHDL13_DWMP_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2729
ber01-VHDL13_DWMP_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                3074
ber01-VHDL13_DWMP_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                2702
ber01-VHDL13_DWOG_170300-2510170300-dsw--0-ia5     17-Oct-2025 03:00:07                4194
ber01-VHDL13_DWOG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:01                3682
ber01-VHDL13_DWOG_170800_COR-2510170800-dsw--0-ia5 17-Oct-2025 12:46:27                3724
ber01-VHDL13_DWOG_171700-2510171700-dsw--0-ia5     17-Oct-2025 18:00:06                3705
ber01-VHDL13_DWOG_180300-2510180300-dsw--0-ia5     18-Oct-2025 03:00:11                3206
ber01-VHDL13_DWOG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                3602
ber01-VHDL13_DWOG_181700-2510181700-dsw--0-ia5     18-Oct-2025 18:00:01                3282
ber01-VHDL13_DWOH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:28:17                2488
ber01-VHDL13_DWOH_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:58:12                2443
ber01-VHDL13_DWOH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:28:16                2413
ber01-VHDL13_DWOH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:28:12                2347
ber01-VHDL13_DWOH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:28:16                2821
ber01-VHDL13_DWOH_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:58:16                2705
ber01-VHDL13_DWOH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:28:16                2592
ber01-VHDL13_DWOH_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:28:17                2583
ber01-VHDL13_DWOI_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:28:17                2353
ber01-VHDL13_DWOI_170400-2510170400-dsw--0-ia5     17-Oct-2025 04:58:17                2307
ber01-VHDL13_DWOI_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:28:16                2276
ber01-VHDL13_DWOI_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:28:12                2238
ber01-VHDL13_DWOI_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:28:16                2574
ber01-VHDL13_DWOI_180400-2510180400-dsw--0-ia5     18-Oct-2025 04:58:16                2424
ber01-VHDL13_DWOI_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:28:12                2366
ber01-VHDL13_DWOI_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:28:11                2464
ber01-VHDL13_DWON_170140-2510170140-dsw--0-ia5     17-Oct-2025 01:40:31                3625
ber01-VHDL13_DWON_170258-2510170258-dsw--0-ia5     17-Oct-2025 02:58:31                3625
ber01-VHDL13_DWON_170525-2510170525-dsw--0-ia5     17-Oct-2025 05:25:51                3870
ber01-VHDL13_DWON_170603-2510170603-dsw--0-ia5     17-Oct-2025 06:03:16                3845
ber01-VHDL13_DWON_170803-2510170803-dsw--0-ia5     17-Oct-2025 08:03:42                3845
ber01-VHDL13_DWON_171239-2510171239-dsw--0-ia5     17-Oct-2025 12:39:47                3845
ber01-VHDL13_DWON_171245-2510171245-dsw--0-ia5     17-Oct-2025 12:45:42                3845
ber01-VHDL13_DWON_171501-2510171501-dsw--0-ia5     17-Oct-2025 15:01:06                3814
ber01-VHDL13_DWON_171503-2510171503-dsw--0-ia5     17-Oct-2025 15:03:07                3858
ber01-VHDL13_DWON_171736-2510171736-dsw--0-ia5     17-Oct-2025 17:37:04                3505
ber01-VHDL13_DWON_180141-2510180141-dsw--0-ia5     18-Oct-2025 01:42:01                3483
ber01-VHDL13_DWON_180253-2510180253-dsw--0-ia5     18-Oct-2025 02:53:20                3483
ber01-VHDL13_DWON_180528-2510180528-dsw--0-ia5     18-Oct-2025 05:28:37                3555
ber01-VHDL13_DWON_180546-2510180546-dsw--0-ia5     18-Oct-2025 05:46:47                3924
ber01-VHDL13_DWON_180827-2510180827-dsw--0-ia5     18-Oct-2025 08:27:07                3924
ber01-VHDL13_DWON_181043-2510181043-dsw--0-ia5     18-Oct-2025 10:43:06                3924
ber01-VHDL13_DWON_181143-2510181143-dsw--0-ia5     18-Oct-2025 11:43:32                3924
ber01-VHDL13_DWON_181437-2510181437-dsw--0-ia5     18-Oct-2025 14:37:59                3683
ber01-VHDL13_DWON_181655-2510181655-dsw--0-ia5     18-Oct-2025 16:55:57                3551
ber01-VHDL13_DWPG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                1954
ber01-VHDL13_DWPG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2172
ber01-VHDL13_DWPG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2250
ber01-VHDL13_DWPG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                1933
ber01-VHDL13_DWPG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2047
ber01-VHDL13_DWPG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                1961
ber01-VHDL13_DWPG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2014
ber01-VHDL13_DWPG_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                1830
ber01-VHDL13_DWPH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2275
ber01-VHDL13_DWPH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2688
ber01-VHDL13_DWPH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                3037
ber01-VHDL13_DWPH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2398
ber01-VHDL13_DWPH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                2307
ber01-VHDL13_DWPH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2190
ber01-VHDL13_DWPH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:02                2130
ber01-VHDL13_DWPH_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                1867
ber01-VHDL13_DWSG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:30:02                2890
ber01-VHDL13_DWSG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:08                2830
ber01-VHDL13_DWSG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:30:03                2712
ber01-VHDL13_DWSG_170800_COR-2510170800-dsw--0-ia5 17-Oct-2025 11:12:41                2838
ber01-VHDL13_DWSG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:30:02                2564
ber01-VHDL13_DWSG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:30:02                3010
ber01-VHDL13_DWSG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:13                3109
ber01-VHDL13_DWSG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:30:08                3024
ber01-VHDL13_DWSG_181800-2510181800-dsw--0-ia5     18-Oct-2025 18:30:02                2797
ber01-VHDL17_DWOG_171200-2510171200-dsw--0-ia5     17-Oct-2025 10:56:48                3264
ber01-VHDL17_DWOG_181200-2510181200-dsw--0-ia5     18-Oct-2025 11:21:07                3755
swis2-VHDL20_DWEG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2502
swis2-VHDL20_DWEG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2746
swis2-VHDL20_DWEG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:02                2744
swis2-VHDL20_DWEG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:09                2850
swis2-VHDL20_DWEG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                2654
swis2-VHDL20_DWEG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                3079
swis2-VHDL20_DWEG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:07                3006
swis2-VHDL20_DWEG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3028
swis2-VHDL20_DWEH_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:16                2611
swis2-VHDL20_DWEH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:16                2934
swis2-VHDL20_DWEH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:22                2998
swis2-VHDL20_DWEH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:23                3101
swis2-VHDL20_DWEH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:16                2933
swis2-VHDL20_DWEH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:14                3246
swis2-VHDL20_DWEH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:21                3223
swis2-VHDL20_DWEH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:22                3321
swis2-VHDL20_DWEI_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2490
swis2-VHDL20_DWEI_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2626
swis2-VHDL20_DWEI_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:22                2639
swis2-VHDL20_DWEI_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:09                2760
swis2-VHDL20_DWEI_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                2570
swis2-VHDL20_DWEI_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2847
swis2-VHDL20_DWEI_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:21                2756
swis2-VHDL20_DWEI_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                2849
swis2-VHDL20_DWHG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2718
swis2-VHDL20_DWHG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                3263
swis2-VHDL20_DWHG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:12                3260
swis2-VHDL20_DWHG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:09                3729
swis2-VHDL20_DWHG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                3098
swis2-VHDL20_DWHG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:07                2981
swis2-VHDL20_DWHG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:17                2984
swis2-VHDL20_DWHG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3325
swis2-VHDL20_DWHH_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2685
swis2-VHDL20_DWHH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2990
swis2-VHDL20_DWHH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:12                2990
swis2-VHDL20_DWHH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:09                3472
swis2-VHDL20_DWHH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                2808
swis2-VHDL20_DWHH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:07                2704
swis2-VHDL20_DWHH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:17                2708
swis2-VHDL20_DWHH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3108
swis2-VHDL20_DWLG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2683
swis2-VHDL20_DWLG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2675
swis2-VHDL20_DWLG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:22                2791
swis2-VHDL20_DWLG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3118
swis2-VHDL20_DWLG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2639
swis2-VHDL20_DWLG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2923
swis2-VHDL20_DWLG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:23                2742
swis2-VHDL20_DWLG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:04                2898
swis2-VHDL20_DWLH_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2323
swis2-VHDL20_DWLH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:13                2428
swis2-VHDL20_DWLH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:22                2459
swis2-VHDL20_DWLH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                2793
swis2-VHDL20_DWLH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2365
swis2-VHDL20_DWLH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2620
swis2-VHDL20_DWLH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:23                2570
swis2-VHDL20_DWLH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:04                2657
swis2-VHDL20_DWLI_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2449
swis2-VHDL20_DWLI_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2453
swis2-VHDL20_DWLI_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:22                2471
swis2-VHDL20_DWLI_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                2797
swis2-VHDL20_DWLI_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2375
swis2-VHDL20_DWLI_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2660
swis2-VHDL20_DWLI_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:23                2527
swis2-VHDL20_DWLI_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:04                2628
swis2-VHDL20_DWMG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2744
swis2-VHDL20_DWMG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                3143
swis2-VHDL20_DWMG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:02                3327
swis2-VHDL20_DWMG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3701
swis2-VHDL20_DWMG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                3137
swis2-VHDL20_DWMG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                3056
swis2-VHDL20_DWMG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:01                3138
swis2-VHDL20_DWMG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3474
swis2-VHDL20_DWMO_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2662
swis2-VHDL20_DWMO_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2767
swis2-VHDL20_DWMO_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:02                2802
swis2-VHDL20_DWMO_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3360
swis2-VHDL20_DWMO_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                2853
swis2-VHDL20_DWMO_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2742
swis2-VHDL20_DWMO_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:01                2889
swis2-VHDL20_DWMO_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3129
swis2-VHDL20_DWMP_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2876
swis2-VHDL20_DWMP_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:13                3272
swis2-VHDL20_DWMP_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:02                3477
swis2-VHDL20_DWMP_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3955
swis2-VHDL20_DWMP_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:06                3393
swis2-VHDL20_DWMP_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                3144
swis2-VHDL20_DWMP_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:01                3231
swis2-VHDL20_DWMP_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3737
swis2-VHDL20_DWPG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2284
swis2-VHDL20_DWPG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:13                2285
swis2-VHDL20_DWPG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                2500
swis2-VHDL20_DWPG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                2713
swis2-VHDL20_DWPG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2396
swis2-VHDL20_DWPG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:06                2378
swis2-VHDL20_DWPG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2288
swis2-VHDL20_DWPG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:04                2474
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swis2-VHDL20_DWPH_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:12                2605
swis2-VHDL20_DWPH_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:00:02                3018
swis2-VHDL20_DWPH_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3500
swis2-VHDL20_DWPH_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2861
swis2-VHDL20_DWPH_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:07                2637
swis2-VHDL20_DWPH_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:00:03                2519
swis2-VHDL20_DWPH_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:04                2590
swis2-VHDL20_DWSG_161800-2510161800-dsw--0-ia5     16-Oct-2025 18:45:02                2859
swis2-VHDL20_DWSG_170200-2510170200-dsw--0-ia5     17-Oct-2025 02:45:13                3238
swis2-VHDL20_DWSG_170400-2510170400-dsw--0-ia5     17-Oct-2025 05:15:02                3368
swis2-VHDL20_DWSG_170800-2510170800-dsw--0-ia5     17-Oct-2025 08:45:05                3212
swis2-VHDL20_DWSG_171300-2510171300-dsw--0-ia5     17-Oct-2025 13:45:04                3077
swis2-VHDL20_DWSG_171800-2510171800-dsw--0-ia5     17-Oct-2025 18:45:02                2921
swis2-VHDL20_DWSG_180200-2510180200-dsw--0-ia5     18-Oct-2025 02:45:07                3494
swis2-VHDL20_DWSG_180400-2510180400-dsw--0-ia5     18-Oct-2025 05:15:01                3464
swis2-VHDL20_DWSG_180800-2510180800-dsw--0-ia5     18-Oct-2025 08:45:06                3523
swis2-VHDL20_DWSG_181300-2510181300-dsw--0-ia5     18-Oct-2025 13:45:04                3385
wst04-VHDL20_DWEG_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:22              258129
wst04-VHDL20_DWEG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:25              259828
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wst04-VHDL20_DWEG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:20              255171
wst04-VHDL20_DWEG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              256560
wst04-VHDL20_DWEG_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:17              256488
wst04-VHDL20_DWEG_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:26              257859
wst04-VHDL20_DWEH_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:16              256896
wst04-VHDL20_DWEH_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:23              258515
wst04-VHDL20_DWEH_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:16              257699
wst04-VHDL20_DWEH_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:27              258155
wst04-VHDL20_DWEH_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:20              255189
wst04-VHDL20_DWEH_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              256665
wst04-VHDL20_DWEH_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:17              256846
wst04-VHDL20_DWEH_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:22              257211
wst04-VHDL20_DWEI_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:22              355246
wst04-VHDL20_DWEI_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:25              355560
wst04-VHDL20_DWEI_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:22              355527
wst04-VHDL20_DWEI_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:27              355907
wst04-VHDL20_DWEI_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:20              350548
wst04-VHDL20_DWEI_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              350743
wst04-VHDL20_DWEI_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:17              351086
wst04-VHDL20_DWEI_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:26              351512
wst04-VHDL20_DWHG_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:26              355432
wst04-VHDL20_DWHG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:23              356010
wst04-VHDL20_DWHG_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:00:18              356040
wst04-VHDL20_DWHG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:26              353694
wst04-VHDL20_DWHG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:14              353092
wst04-VHDL20_DWHG_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:00:11              353193
wst04-VHDL20_DWHH_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:20              339628
wst04-VHDL20_DWHH_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:23              340213
wst04-VHDL20_DWHH_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:00:12              340161
wst04-VHDL20_DWHH_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:20              339239
wst04-VHDL20_DWHH_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:14              338860
wst04-VHDL20_DWHH_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:00:11              338950
wst04-VHDL20_DWLG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:40:42              335684
wst04-VHDL20_DWLG_170400-2510170400-omedes--0.pdf  17-Oct-2025 04:59:42              335042
wst04-VHDL20_DWLG_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:40:31              335444
wst04-VHDL20_DWLG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:40:31              335717
wst04-VHDL20_DWLG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:40:37              335920
wst04-VHDL20_DWLG_180400-2510180400-omedes--0.pdf  18-Oct-2025 04:59:42              335669
wst04-VHDL20_DWLG_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:40:32              336001
wst04-VHDL20_DWLG_181800-2510181800-omedes--0.pdf  18-Oct-2025 18:40:32              334491
wst04-VHDL20_DWLH_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:40:42              345521
wst04-VHDL20_DWLH_170400-2510170400-omedes--0.pdf  17-Oct-2025 04:59:42              345031
wst04-VHDL20_DWLH_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:40:23              345561
wst04-VHDL20_DWLH_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:40:21              340557
wst04-VHDL20_DWLH_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:40:37              340770
wst04-VHDL20_DWLH_180400-2510180400-omedes--0.pdf  18-Oct-2025 04:59:42              340946
wst04-VHDL20_DWLH_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:40:21              341273
wst04-VHDL20_DWLH_181800-2510181800-omedes--0.pdf  18-Oct-2025 18:40:22              339017
wst04-VHDL20_DWLI_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:40:42              336300
wst04-VHDL20_DWLI_170400-2510170400-omedes--0.pdf  17-Oct-2025 04:59:42              335848
wst04-VHDL20_DWLI_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:40:43              336710
wst04-VHDL20_DWLI_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:40:41              333524
wst04-VHDL20_DWLI_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:40:48              333709
wst04-VHDL20_DWLI_180400-2510180400-omedes--0.pdf  18-Oct-2025 04:59:42              333551
wst04-VHDL20_DWLI_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:40:42              333882
wst04-VHDL20_DWLI_181800-2510181800-omedes--0.pdf  18-Oct-2025 18:40:41              335557
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wst04-VHDL20_DWMG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:16              530078
wst04-VHDL20_DWMG_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:16              529923
wst04-VHDL20_DWMG_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:16              530475
wst04-VHDL20_DWMG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:16              529563
wst04-VHDL20_DWMG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              529435
wst04-VHDL20_DWMG_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:11              529202
wst04-VHDL20_DWMG_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:16              530392
wst04-VHDL20_DWMO_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:12              428121
wst04-VHDL20_DWMO_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:12              428870
wst04-VHDL20_DWMO_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:12              429075
wst04-VHDL20_DWMO_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:16              430260
wst04-VHDL20_DWMO_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:16              426217
wst04-VHDL20_DWMO_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              425688
wst04-VHDL20_DWMO_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:11              426331
wst04-VHDL20_DWMO_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:16              427374
wst04-VHDL20_DWMP_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:16              542974
wst04-VHDL20_DWMP_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:13              543474
wst04-VHDL20_DWMP_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:16              544363
wst04-VHDL20_DWMP_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:23              545070
wst04-VHDL20_DWMP_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:16              545718
wst04-VHDL20_DWMP_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              544201
wst04-VHDL20_DWMP_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:11              545009
wst04-VHDL20_DWMP_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:22              546016
wst04-VHDL20_DWPG_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:12              351744
wst04-VHDL20_DWPG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:18              352141
wst04-VHDL20_DWPG_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:00:12              351893
wst04-VHDL20_DWPG_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:14              397310
wst04-VHDL20_DWPG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:12              344362
wst04-VHDL20_DWPG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              344163
wst04-VHDL20_DWPG_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:00:11              344044
wst04-VHDL20_DWPG_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:12              388617
wst04-VHDL20_DWPH_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:12              299787
wst04-VHDL20_DWPH_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:18              255875
wst04-VHDL20_DWPH_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:00:12              255709
wst04-VHDL20_DWPH_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:16              301360
wst04-VHDL20_DWPH_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:12              300557
wst04-VHDL20_DWPH_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:31              255808
wst04-VHDL20_DWPH_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:00:11              255725
wst04-VHDL20_DWPH_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:12              300609
wst04-VHDL20_DWSG_161800-2510161800-omedes--0.pdf  16-Oct-2025 18:45:12              352436
wst04-VHDL20_DWSG_170200-2510170200-omedes--0.pdf  17-Oct-2025 02:45:12              353415
wst04-VHDL20_DWSG_170400-2510170400-omedes--0.pdf  17-Oct-2025 05:15:12              353087
wst04-VHDL20_DWSG_170800-2510170800-omedes--0.pdf  17-Oct-2025 08:45:14              352909
wst04-VHDL20_DWSG_171300-2510171300-omedes--0.pdf  17-Oct-2025 13:45:12              352044
wst04-VHDL20_DWSG_171800-2510171800-omedes--0.pdf  17-Oct-2025 18:45:12              351469
wst04-VHDL20_DWSG_180200-2510180200-omedes--0.pdf  18-Oct-2025 02:45:14              353166
wst04-VHDL20_DWSG_180400-2510180400-omedes--0.pdf  18-Oct-2025 05:15:17              352485
wst04-VHDL20_DWSG_180800-2510180800-omedes--0.pdf  18-Oct-2025 08:45:16              352155
wst04-VHDL20_DWSG_181300-2510181300-omedes--0.pdf  18-Oct-2025 13:45:12              356731