Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Oct-2026 13:38:13 3789
FPDL13_DWMZ_130600 13-Oct-2026 13:47:31 4081
SXDL31_DWAV_121800 12-Oct-2026 16:47:52 5801
SXDL31_DWAV_130800 13-Oct-2026 07:24:55 8104
SXDL31_DWAV_131800 13-Oct-2026 18:30:31 5408
SXDL31_DWAV_140800 14-Oct-2026 07:16:15 9177
SXDL31_DWAV_LATEST 14-Oct-2026 07:16:15 9177
SXDL33_DWAV_120000 12-Oct-2026 09:45:06 13816
SXDL33_DWAV_130000 13-Oct-2026 10:27:10 12123
SXDL33_DWAV_LATEST 13-Oct-2026 10:27:10 12123
ber01-FWDL39_DWMS_121200-2610121200-dsw--0-ia5 12-Oct-2026 10:33:46 1169
ber01-FWDL39_DWMS_131200-2610131200-dsw--0-ia5 13-Oct-2026 10:26:57 1306
ber01-VHDL13_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:24 2613
ber01-VHDL13_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2429
ber01-VHDL13_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2639
ber01-VHDL13_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 2677
ber01-VHDL13_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2545
ber01-VHDL13_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2455
ber01-VHDL13_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3666
ber01-VHDL13_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3831
ber01-VHDL13_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3539
ber01-VHDL13_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3616
ber01-VHDL13_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2906
ber01-VHDL13_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2604
ber01-VHDL13_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2996
ber01-VHDL13_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2878
ber01-VHDL13_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2696
ber01-VHDL13_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2649
ber01-VHDL13_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 2807
ber01-VHDL13_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3145
ber01-VHDL13_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2726
ber01-VHDL13_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3082
ber01-VHDL13_DWOG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 3714
ber01-VHDL13_DWOG_121700-2610121700-dsw--0-ia5 12-Oct-2026 18:00:12 3536
ber01-VHDL13_DWOG_130300-2610130300-dsw--0-ia5 13-Oct-2026 03:00:31 4586
ber01-VHDL13_DWOG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 4182
ber01-VHDL13_DWOG_131700-2610131700-dsw--0-ia5 13-Oct-2026 18:00:05 4054
ber01-VHDL13_DWOG_140300-2610140300-dsw--0-ia5 14-Oct-2026 03:02:09 4189
ber01-VHDL13_DWON_121232-2610121232-dsw--0-ia5 12-Oct-2026 12:32:28 3602
ber01-VHDL13_DWON_121428-2610121428-dsw--0-ia5 12-Oct-2026 14:28:19 3744
ber01-VHDL13_DWON_121709-2610121709-dsw--0-ia5 12-Oct-2026 17:09:24 3313
ber01-VHDL13_DWON_121829-2610121829-dsw--0-ia5 12-Oct-2026 18:29:19 3296
ber01-VHDL13_DWON_122121-2610122121-dsw--0-ia5 12-Oct-2026 21:21:19 3332
ber01-VHDL13_DWON_130000-2610130000-dsw--0-ia5 13-Oct-2026 00:00:59 3885
ber01-VHDL13_DWON_130131-2610130131-dsw--0-ia5 13-Oct-2026 01:31:55 3843
ber01-VHDL13_DWON_130242-2610130242-dsw--0-ia5 13-Oct-2026 02:42:20 3843
ber01-VHDL13_DWON_130257-2610130257-dsw--0-ia5 13-Oct-2026 02:57:27 3815
ber01-VHDL13_DWON_130258-2610130258-dsw--0-ia5 13-Oct-2026 03:00:31 3839
ber01-VHDL13_DWON_130529-2610130529-dsw--0-ia5 13-Oct-2026 05:29:14 3908
ber01-VHDL13_DWON_130630-2610130630-dsw--0-ia5 13-Oct-2026 06:30:46 3789
ber01-VHDL13_DWON_131042-2610131042-dsw--0-ia5 13-Oct-2026 10:43:19 3874
ber01-VHDL13_DWON_131441-2610131441-dsw--0-ia5 13-Oct-2026 14:41:38 4171
ber01-VHDL13_DWON_131733-2610131733-dsw--0-ia5 13-Oct-2026 17:33:59 3482
ber01-VHDL13_DWON_131842-2610131842-dsw--0-ia5 13-Oct-2026 18:42:35 3722
ber01-VHDL13_DWON_132045-2610132045-dsw--0-ia5 13-Oct-2026 20:45:28 3437
ber01-VHDL13_DWON_132134-2610132134-dsw--0-ia5 13-Oct-2026 21:34:48 3440
ber01-VHDL13_DWON_140006-2610140006-dsw--0-ia5 14-Oct-2026 00:06:14 4255
ber01-VHDL13_DWON_140144-2610140144-dsw--0-ia5 14-Oct-2026 01:44:14 4231
ber01-VHDL13_DWON_140248-2610140248-dsw--0-ia5 14-Oct-2026 02:50:19 4231
ber01-VHDL13_DWON_140353-2610140353-dsw--0-ia5 14-Oct-2026 03:53:45 4231
ber01-VHDL13_DWON_140527-2610140527-dsw--0-ia5 14-Oct-2026 05:28:04 4427
ber01-VHDL13_DWON_140611-2610140611-dsw--0-ia5 14-Oct-2026 06:11:48 4421
ber01-VHDL13_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2624
ber01-VHDL13_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2997
ber01-VHDL13_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3127
ber01-VHDL13_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 3377
ber01-VHDL13_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3007
ber01-VHDL13_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 2799
ber01-VHDL17_DWOG_121200-2610121200-dsw--0-ia5 12-Oct-2026 11:20:28 3235
ber01-VHDL17_DWOG_131200-2610131200-dsw--0-ia5 13-Oct-2026 11:46:12 4159
swis2-VHDL20_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 1114
swis2-VHDL20_DWEG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1160
swis2-VHDL20_DWEG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1082
swis2-VHDL20_DWEG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 986
swis2-VHDL20_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 951
swis2-VHDL20_DWEG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 917
swis2-VHDL20_DWEG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 830
swis2-VHDL20_DWEG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 830
swis2-VHDL20_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 954
swis2-VHDL20_DWEH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1095
swis2-VHDL20_DWEH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 971
swis2-VHDL20_DWEH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 915
swis2-VHDL20_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1037
swis2-VHDL20_DWEH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 1021
swis2-VHDL20_DWEH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 857
swis2-VHDL20_DWEH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 857
swis2-VHDL20_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 995
swis2-VHDL20_DWEI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1024
swis2-VHDL20_DWEI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 982
swis2-VHDL20_DWEI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 873
swis2-VHDL20_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 973
swis2-VHDL20_DWEI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:04 939
swis2-VHDL20_DWEI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 852
swis2-VHDL20_DWEI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:01:24 852
swis2-VHDL20_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1534
swis2-VHDL20_DWHG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1847
swis2-VHDL20_DWHG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1545
swis2-VHDL20_DWHG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1475
swis2-VHDL20_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1765
swis2-VHDL20_DWHG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 1808
swis2-VHDL20_DWHG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1360
swis2-VHDL20_DWHG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1357
swis2-VHDL20_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1626
swis2-VHDL20_DWHH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1796
swis2-VHDL20_DWHH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1492
swis2-VHDL20_DWHH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1425
swis2-VHDL20_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1612
swis2-VHDL20_DWHH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:45:11 2027
swis2-VHDL20_DWHH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:47:16 1505
swis2-VHDL20_DWHH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1505
swis2-VHDL20_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1019
swis2-VHDL20_DWLG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1058
swis2-VHDL20_DWLG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 893
swis2-VHDL20_DWLG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1060
swis2-VHDL20_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 955
swis2-VHDL20_DWLG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 827
swis2-VHDL20_DWLG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 860
swis2-VHDL20_DWLG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 866
swis2-VHDL20_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1128
swis2-VHDL20_DWLH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1174
swis2-VHDL20_DWLH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1003
swis2-VHDL20_DWLH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1155
swis2-VHDL20_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1019
swis2-VHDL20_DWLH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 991
swis2-VHDL20_DWLH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1020
swis2-VHDL20_DWLH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1003
swis2-VHDL20_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 987
swis2-VHDL20_DWLI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1111
swis2-VHDL20_DWLI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 874
swis2-VHDL20_DWLI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1085
swis2-VHDL20_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1017
swis2-VHDL20_DWLI_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 898
swis2-VHDL20_DWLI_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 843
swis2-VHDL20_DWLI_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 849
swis2-VHDL20_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1406
swis2-VHDL20_DWMO_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1524
swis2-VHDL20_DWMO_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1194
swis2-VHDL20_DWMO_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1152
swis2-VHDL20_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1394
swis2-VHDL20_DWMO_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1322
swis2-VHDL20_DWMO_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1113
swis2-VHDL20_DWMO_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1301
swis2-VHDL20_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1271
swis2-VHDL20_DWMP_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1332
swis2-VHDL20_DWMP_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1244
swis2-VHDL20_DWMP_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1216
swis2-VHDL20_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1323
swis2-VHDL20_DWMP_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:06 1250
swis2-VHDL20_DWMP_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1173
swis2-VHDL20_DWMP_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1260
swis2-VHDL20_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1045
swis2-VHDL20_DWPG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1205
swis2-VHDL20_DWPG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 969
swis2-VHDL20_DWPG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1295
swis2-VHDL20_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1204
swis2-VHDL20_DWPG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1081
swis2-VHDL20_DWPG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1010
swis2-VHDL20_DWPG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1016
swis2-VHDL20_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1125
swis2-VHDL20_DWPH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1396
swis2-VHDL20_DWPH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1240
swis2-VHDL20_DWPH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1575
swis2-VHDL20_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1351
swis2-VHDL20_DWPH_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:31:08 1265
swis2-VHDL20_DWPH_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:32 1130
swis2-VHDL20_DWPH_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:14 1148
swis2-VHDL20_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1283
swis2-VHDL20_DWSG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1472
swis2-VHDL20_DWSG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:03 1317
swis2-VHDL20_DWSG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1233
swis2-VHDL20_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1243
swis2-VHDL20_DWSG_131800-2610131800-dsw--0-ia5 13-Oct-2026 18:30:08 1333
swis2-VHDL20_DWSG_140200-2610140200-dsw--0-ia5 14-Oct-2026 02:30:04 1019
swis2-VHDL20_DWSG_140400-2610140400-dsw--0-ia5 14-Oct-2026 05:00:21 1149
wst04-VHDL20_DWEG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 240159
wst04-VHDL20_DWEG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 236868
wst04-VHDL20_DWEG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 235744
wst04-VHDL20_DWEG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 235516
wst04-VHDL20_DWEG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 235091
wst04-VHDL20_DWEG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 236727
wst04-VHDL20_DWEG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:20 236005
wst04-VHDL20_DWEG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 236037
wst04-VHDL20_DWEH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 233869
wst04-VHDL20_DWEH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 233914
wst04-VHDL20_DWEH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 233432
wst04-VHDL20_DWEH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 233227
wst04-VHDL20_DWEH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 233931
wst04-VHDL20_DWEH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 237578
wst04-VHDL20_DWEH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 237030
wst04-VHDL20_DWEH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:14 237380
wst04-VHDL20_DWEI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 342769
wst04-VHDL20_DWEI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 338625
wst04-VHDL20_DWEI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 338074
wst04-VHDL20_DWEI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 337814
wst04-VHDL20_DWEI_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 337979
wst04-VHDL20_DWEI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 336757
wst04-VHDL20_DWEI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 336627
wst04-VHDL20_DWEI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 336618
wst04-VHDL20_DWHG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:45:19 337001
wst04-VHDL20_DWHG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:45:18 338453
wst04-VHDL20_DWHG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 336662
wst04-VHDL20_DWHG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 336418
wst04-VHDL20_DWHG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:41 338776
wst04-VHDL20_DWHG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 340801
wst04-VHDL20_DWHG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 339169
wst04-VHDL20_DWHG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 339183
wst04-VHDL20_DWHH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:45:19 329372
wst04-VHDL20_DWHH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:45:18 319833
wst04-VHDL20_DWHH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 318469
wst04-VHDL20_DWHH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:18 225099
wst04-VHDL20_DWHH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:41 318801
wst04-VHDL20_DWHH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:45:14 318801
wst04-VHDL20_DWHH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:47:16 317440
wst04-VHDL20_DWHH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 221673
wst04-VHDL20_DWLG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 326801
wst04-VHDL20_DWLG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 324514
wst04-VHDL20_DWLG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 323947
wst04-VHDL20_DWLG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 324574
wst04-VHDL20_DWLG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:49 368608
wst04-VHDL20_DWLG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 328240
wst04-VHDL20_DWLG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 328457
wst04-VHDL20_DWLG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 327802
wst04-VHDL20_DWLH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 326809
wst04-VHDL20_DWLH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 325841
wst04-VHDL20_DWLH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 325126
wst04-VHDL20_DWLH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 325751
wst04-VHDL20_DWLH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 369816
wst04-VHDL20_DWLH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324791
wst04-VHDL20_DWLH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325285
wst04-VHDL20_DWLH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324645
wst04-VHDL20_DWLI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 373071
wst04-VHDL20_DWLI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 326451
wst04-VHDL20_DWLI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 326291
wst04-VHDL20_DWLI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 326939
wst04-VHDL20_DWLI_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 371090
wst04-VHDL20_DWLI_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 324643
wst04-VHDL20_DWLI_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 325286
wst04-VHDL20_DWLI_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:43 324608
wst04-VHDL20_DWMO_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 443598
wst04-VHDL20_DWMO_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 347149
wst04-VHDL20_DWMO_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 447482
wst04-VHDL20_DWMO_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:18 447603
wst04-VHDL20_DWMO_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:39 447796
wst04-VHDL20_DWMO_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:20 343284
wst04-VHDL20_DWMO_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 446202
wst04-VHDL20_DWMO_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 445428
wst04-VHDL20_DWMP_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 446440
wst04-VHDL20_DWMP_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 443945
wst04-VHDL20_DWMP_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 537776
wst04-VHDL20_DWMP_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 538041
wst04-VHDL20_DWMP_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:39 443300
wst04-VHDL20_DWMP_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:31 444927
wst04-VHDL20_DWMP_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:18 542884
wst04-VHDL20_DWMP_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 542024
wst04-VHDL20_DWPG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 383475
wst04-VHDL20_DWPG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:39 334999
wst04-VHDL20_DWPG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236347
wst04-VHDL20_DWPG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 335542
wst04-VHDL20_DWPG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:49 379952
wst04-VHDL20_DWPG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 334118
wst04-VHDL20_DWPG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 236974
wst04-VHDL20_DWPG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 333994
wst04-VHDL20_DWPH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 238521
wst04-VHDL20_DWPH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 236735
wst04-VHDL20_DWPH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236589
wst04-VHDL20_DWPH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 237433
wst04-VHDL20_DWPH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 281393
wst04-VHDL20_DWPH_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:31:30 239153
wst04-VHDL20_DWPH_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:32 238906
wst04-VHDL20_DWPH_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:33 238997
wst04-VHDL20_DWSG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 339560
wst04-VHDL20_DWSG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:13 335263
wst04-VHDL20_DWSG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 334829
wst04-VHDL20_DWSG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 334851
wst04-VHDL20_DWSG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 334211
wst04-VHDL20_DWSG_131800-2610131800-omedes--0.pdf 13-Oct-2026 18:30:12 333812
wst04-VHDL20_DWSG_140200-2610140200-omedes--0.pdf 14-Oct-2026 02:30:14 333590
wst04-VHDL20_DWSG_140400-2610140400-omedes--0.pdf 14-Oct-2026 05:00:21 333909