Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Jul-2026 14:25:45 7250
FPDL13_DWMZ_220600 22-Jul-2026 11:41:43 4057
SXDL31_DWAV_210800 21-Jul-2026 08:03:59 11202
SXDL31_DWAV_211800 21-Jul-2026 15:54:43 4954
SXDL31_DWAV_220800 22-Jul-2026 07:28:34 12549
SXDL31_DWAV_221800 22-Jul-2026 16:12:15 5855
SXDL31_DWAV_LATEST 22-Jul-2026 16:12:15 5855
SXDL33_DWAV_210000 21-Jul-2026 10:03:08 6150
SXDL33_DWAV_220000 22-Jul-2026 10:51:43 12094
SXDL33_DWAV_LATEST 22-Jul-2026 10:51:43 12094
ber01-FWDL39_DWMS_211200-2607211200-dsw--0-ia5 21-Jul-2026 10:17:46 1141
ber01-FWDL39_DWMS_221200-2607221200-dsw--0-ia5 22-Jul-2026 10:41:27 1202
ber01-VHDL13_DWEG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2742
ber01-VHDL13_DWEG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:28:16 2450
ber01-VHDL13_DWEH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2768
ber01-VHDL13_DWEH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:28:22 2730
ber01-VHDL13_DWEI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2525
ber01-VHDL13_DWEI_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:28:10 2301
ber01-VHDL13_DWHG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3739
ber01-VHDL13_DWHG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 3878
ber01-VHDL13_DWHH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3867
ber01-VHDL13_DWHH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 4026
ber01-VHDL13_DWLG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2501
ber01-VHDL13_DWLG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2899
ber01-VHDL13_DWLH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2588
ber01-VHDL13_DWLH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2708
ber01-VHDL13_DWLI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2296
ber01-VHDL13_DWLI_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2358
ber01-VHDL13_DWMO_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2415
ber01-VHDL13_DWMO_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2543
ber01-VHDL13_DWMP_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2587
ber01-VHDL13_DWMP_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2508
ber01-VHDL13_DWOG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3165
ber01-VHDL13_DWOG_211700-2607211700-dsw--0-ia5 21-Jul-2026 18:00:01 3717
ber01-VHDL13_DWOG_211700_COR-2607211700-dsw--0-ia5 21-Jul-2026 19:54:25 4268
ber01-VHDL13_DWOG_220300-2607220300-dsw--0-ia5 22-Jul-2026 03:00:14 5090
ber01-VHDL13_DWOG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 4611
ber01-VHDL13_DWOG_221700-2607221700-dsw--0-ia5 22-Jul-2026 18:00:03 3753
ber01-VHDL13_DWOG_230300-2607230300-dsw--0-ia5 23-Jul-2026 03:00:03 3714
ber01-VHDL13_DWON_210854-2607210854-dsw--0-ia5 21-Jul-2026 08:54:27 3957
ber01-VHDL13_DWON_211048-2607211048-dsw--0-ia5 21-Jul-2026 10:48:57 3957
ber01-VHDL13_DWON_211530-2607211530-dsw--0-ia5 21-Jul-2026 15:30:39 3705
ber01-VHDL13_DWON_211555-2607211555-dsw--0-ia5 21-Jul-2026 15:55:42 3705
ber01-VHDL13_DWON_211702-2607211702-dsw--0-ia5 21-Jul-2026 17:02:46 3255
ber01-VHDL13_DWON_211953-2607211953-dsw--0-ia5 21-Jul-2026 19:53:56 4251
ber01-VHDL13_DWON_220207-2607220207-dsw--0-ia5 22-Jul-2026 02:07:52 5048
ber01-VHDL13_DWON_220508-2607220508-dsw--0-ia5 22-Jul-2026 05:08:36 4386
ber01-VHDL13_DWON_220558-2607220558-dsw--0-ia5 22-Jul-2026 05:58:21 4386
ber01-VHDL13_DWON_221102-2607221102-dsw--0-ia5 22-Jul-2026 11:02:52 4386
ber01-VHDL13_DWON_221218-2607221218-dsw--0-ia5 22-Jul-2026 12:18:17 4199
ber01-VHDL13_DWON_221313-2607221313-dsw--0-ia5 22-Jul-2026 13:13:35 3640
ber01-VHDL13_DWON_221431-2607221431-dsw--0-ia5 22-Jul-2026 14:31:20 3640
ber01-VHDL13_DWON_221654-2607221654-dsw--0-ia5 22-Jul-2026 16:54:10 3643
ber01-VHDL13_DWON_222019-2607222019-dsw--0-ia5 22-Jul-2026 20:19:36 3643
ber01-VHDL13_DWON_230011-2607230011-dsw--0-ia5 23-Jul-2026 00:11:41 3815
ber01-VHDL13_DWON_230330-2607230330-dsw--0-ia5 23-Jul-2026 03:30:38 3815
ber01-VHDL13_DWON_230356-2607230356-dsw--0-ia5 23-Jul-2026 03:56:56 3815
ber01-VHDL13_DWON_230522-2607230522-dsw--0-ia5 23-Jul-2026 05:22:17 3801
ber01-VHDL13_DWON_230618-2607230618-dsw--0-ia5 23-Jul-2026 06:18:11 3714
ber01-VHDL13_DWPG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2561
ber01-VHDL13_DWPG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2591
ber01-VHDL13_DWPH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3289
ber01-VHDL13_DWPH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 3485
ber01-VHDL13_DWSG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2190
ber01-VHDL13_DWSG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 2430
ber01-VHDL17_DWOG_211200-2607211200-dsw--0-ia5 21-Jul-2026 11:13:01 2727
ber01-VHDL17_DWOG_221200-2607221200-dsw--0-ia5 22-Jul-2026 12:02:57 2851
swis2-VHDL20_DWEG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1017
swis2-VHDL20_DWEG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1045
swis2-VHDL20_DWEG_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:11 870
swis2-VHDL20_DWEG_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:01:27 748
swis2-VHDL20_DWEG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 862
swis2-VHDL20_DWEG_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:02 1005
swis2-VHDL20_DWEG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 799
swis2-VHDL20_DWEG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 795
swis2-VHDL20_DWEH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1022
swis2-VHDL20_DWEH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1093
swis2-VHDL20_DWEH_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:11 903
swis2-VHDL20_DWEH_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:01:27 747
swis2-VHDL20_DWEH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 988
swis2-VHDL20_DWEH_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:02 1074
swis2-VHDL20_DWEH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 817
swis2-VHDL20_DWEH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 819
swis2-VHDL20_DWEI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1036
swis2-VHDL20_DWEI_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1068
swis2-VHDL20_DWEI_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:11 893
swis2-VHDL20_DWEI_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:01:27 770
swis2-VHDL20_DWEI_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 884
swis2-VHDL20_DWEI_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:02 1027
swis2-VHDL20_DWEI_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:08 821
swis2-VHDL20_DWEI_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:01:26 817
swis2-VHDL20_DWHG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:45:21 1662
swis2-VHDL20_DWHG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:45:08 1600
swis2-VHDL20_DWHG_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:45:15 1507
swis2-VHDL20_DWHG_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:16 1507
swis2-VHDL20_DWHG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:45:17 1718
swis2-VHDL20_DWHG_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:45:07 1470
swis2-VHDL20_DWHG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:45:32 1258
swis2-VHDL20_DWHG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 1080
swis2-VHDL20_DWHH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:45:21 2023
swis2-VHDL20_DWHH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:45:08 1937
swis2-VHDL20_DWHH_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:45:15 1877
swis2-VHDL20_DWHH_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:16 1880
swis2-VHDL20_DWHH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:45:17 2001
swis2-VHDL20_DWHH_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:45:07 1785
swis2-VHDL20_DWHH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:45:32 1551
swis2-VHDL20_DWHH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 1214
swis2-VHDL20_DWLG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 993
swis2-VHDL20_DWLG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1027
swis2-VHDL20_DWLG_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:26 941
swis2-VHDL20_DWLG_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:12 1042
swis2-VHDL20_DWLG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:25 1322
swis2-VHDL20_DWLG_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:31:03 1216
swis2-VHDL20_DWLG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 1048
swis2-VHDL20_DWLG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1197
swis2-VHDL20_DWLH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1181
swis2-VHDL20_DWLH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1224
swis2-VHDL20_DWLH_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:26 1077
swis2-VHDL20_DWLH_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:12 1052
swis2-VHDL20_DWLH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:25 1159
swis2-VHDL20_DWLH_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:31:03 1163
swis2-VHDL20_DWLH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 842
swis2-VHDL20_DWLH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1016
swis2-VHDL20_DWLI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 975
swis2-VHDL20_DWLI_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 974
swis2-VHDL20_DWLI_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:26 874
swis2-VHDL20_DWLI_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:12 869
swis2-VHDL20_DWLI_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:25 985
swis2-VHDL20_DWLI_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:31:03 957
swis2-VHDL20_DWLI_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 837
swis2-VHDL20_DWLI_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1036
swis2-VHDL20_DWMO_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 964
swis2-VHDL20_DWMO_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1060
swis2-VHDL20_DWMO_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:00 924
swis2-VHDL20_DWMO_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:01 869
swis2-VHDL20_DWMO_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 942
swis2-VHDL20_DWMO_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:08 862
swis2-VHDL20_DWMO_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 922
swis2-VHDL20_DWMO_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:02 923
swis2-VHDL20_DWMP_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1070
swis2-VHDL20_DWMP_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1102
swis2-VHDL20_DWMP_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:00 933
swis2-VHDL20_DWMP_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:01 868
swis2-VHDL20_DWMP_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 1058
swis2-VHDL20_DWMP_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:08 976
swis2-VHDL20_DWMP_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 919
swis2-VHDL20_DWMP_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:02 915
swis2-VHDL20_DWPG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1095
swis2-VHDL20_DWPG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1178
swis2-VHDL20_DWPG_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:26 949
swis2-VHDL20_DWPG_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:12 1062
swis2-VHDL20_DWPG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:25 1235
swis2-VHDL20_DWPG_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:31:03 1186
swis2-VHDL20_DWPG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 1053
swis2-VHDL20_DWPG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1250
swis2-VHDL20_DWPH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1594
swis2-VHDL20_DWPH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1631
swis2-VHDL20_DWPH_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:26 1605
swis2-VHDL20_DWPH_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:12 1754
swis2-VHDL20_DWPH_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:25 1871
swis2-VHDL20_DWPH_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:31:03 1203
swis2-VHDL20_DWPH_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:28 955
swis2-VHDL20_DWPH_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:12 1063
swis2-VHDL20_DWSG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 869
swis2-VHDL20_DWSG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1080
swis2-VHDL20_DWSG_220200-2607220200-dsw--0-ia5 22-Jul-2026 02:30:11 791
swis2-VHDL20_DWSG_220400-2607220400-dsw--0-ia5 22-Jul-2026 05:00:22 772
swis2-VHDL20_DWSG_220800-2607220800-dsw--0-ia5 22-Jul-2026 08:30:07 904
swis2-VHDL20_DWSG_221800-2607221800-dsw--0-ia5 22-Jul-2026 18:30:08 877
swis2-VHDL20_DWSG_230200-2607230200-dsw--0-ia5 23-Jul-2026 02:30:05 879
swis2-VHDL20_DWSG_230400-2607230400-dsw--0-ia5 23-Jul-2026 05:00:16 876
wst04-VHDL20_DWEG_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 234453
wst04-VHDL20_DWEG_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:13 238513
wst04-VHDL20_DWEG_220200-2607220200-omedes--0.pdf 22-Jul-2026 02:30:11 237625
wst04-VHDL20_DWEG_220400-2607220400-omedes--0.pdf 22-Jul-2026 05:00:12 237317
wst04-VHDL20_DWEG_220800-2607220800-omedes--0.pdf 22-Jul-2026 08:30:17 238022
wst04-VHDL20_DWEG_221800-2607221800-omedes--0.pdf 22-Jul-2026 18:30:16 239007
wst04-VHDL20_DWEG_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 238328
wst04-VHDL20_DWEG_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 237386
wst04-VHDL20_DWEH_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 233430
wst04-VHDL20_DWEH_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:13 231838
wst04-VHDL20_DWEH_220200-2607220200-omedes--0.pdf 22-Jul-2026 02:30:11 231247
wst04-VHDL20_DWEH_220400-2607220400-omedes--0.pdf 22-Jul-2026 05:00:12 231239
wst04-VHDL20_DWEH_220800-2607220800-omedes--0.pdf 22-Jul-2026 08:30:17 232329
wst04-VHDL20_DWEH_221800-2607221800-omedes--0.pdf 22-Jul-2026 18:30:16 234945
wst04-VHDL20_DWEH_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 235110
wst04-VHDL20_DWEH_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 234146
wst04-VHDL20_DWEI_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 335415
wst04-VHDL20_DWEI_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:20 340627
wst04-VHDL20_DWEI_220200-2607220200-omedes--0.pdf 22-Jul-2026 02:30:11 340339
wst04-VHDL20_DWEI_220400-2607220400-omedes--0.pdf 22-Jul-2026 05:00:12 339929
wst04-VHDL20_DWEI_220800-2607220800-omedes--0.pdf 22-Jul-2026 08:30:17 340140
wst04-VHDL20_DWEI_221800-2607221800-omedes--0.pdf 22-Jul-2026 18:30:16 337917
wst04-VHDL20_DWEI_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:30:10 337802
wst04-VHDL20_DWEI_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:12 336813
wst04-VHDL20_DWHG_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:45:21 338308
wst04-VHDL20_DWHG_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:45:13 343957
wst04-VHDL20_DWHG_220200-2607220200-omedes--0.pdf 22-Jul-2026 02:45:15 343921
wst04-VHDL20_DWHG_220400-2607220400-omedes--0.pdf 22-Jul-2026 05:00:16 343739
wst04-VHDL20_DWHG_220800-2607220800-omedes--0.pdf 22-Jul-2026 08:45:17 344753
wst04-VHDL20_DWHG_221800-2607221800-omedes--0.pdf 22-Jul-2026 18:45:17 343180
wst04-VHDL20_DWHG_230200-2607230200-omedes--0.pdf 23-Jul-2026 02:45:32 341583
wst04-VHDL20_DWHG_230400-2607230400-omedes--0.pdf 23-Jul-2026 05:00:16 340464
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