Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Nov-2026 13:59:35 3609
FPDL13_DWMZ_120600 12-Nov-2026 14:01:49 4228
SXDL31_DWAV_110810 11-Nov-2026 09:00:39 14854
SXDL31_DWAV_111810 11-Nov-2026 17:01:08 8545
SXDL31_DWAV_120810 12-Nov-2026 08:39:19 8057
SXDL31_DWAV_LATEST 12-Nov-2026 08:39:19 8057
SXDL33_DWAV_110000 11-Nov-2026 10:50:44 5698
SXDL33_DWAV_120000 12-Nov-2026 11:19:49 6690
SXDL33_DWAV_LATEST 12-Nov-2026 11:19:49 6690
ber01-FWDL39_DWMS_111200-2611111200-dsw--0-ia5 11-Nov-2026 12:46:23 1382
ber01-FWDL39_DWMS_121200-2611121200-dsw--0-ia5 12-Nov-2026 12:14:38 1430
ber01-VHDL13_DWEG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:24 3260
ber01-VHDL13_DWEG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:13 2982
ber01-VHDL13_DWEH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:24 3665
ber01-VHDL13_DWEH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:13 3030
ber01-VHDL13_DWEI_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:24 3138
ber01-VHDL13_DWEI_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:13 2712
ber01-VHDL13_DWHG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 4210
ber01-VHDL13_DWHG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 4009
ber01-VHDL13_DWHG_120800_COR-2611120800-dsw--0-ia5 12-Nov-2026 15:13:03 4019
ber01-VHDL13_DWHH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 4258
ber01-VHDL13_DWHH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 3770
ber01-VHDL13_DWHH_120800_COR-2611120800-dsw--0-ia5 12-Nov-2026 15:13:31 3819
ber01-VHDL13_DWLG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2959
ber01-VHDL13_DWLG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 3176
ber01-VHDL13_DWLH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2935
ber01-VHDL13_DWLH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 2905
ber01-VHDL13_DWLI_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2545
ber01-VHDL13_DWLI_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 2562
ber01-VHDL13_DWMO_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2996
ber01-VHDL13_DWMO_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 3376
ber01-VHDL13_DWMP_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 3623
ber01-VHDL13_DWMP_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 3922
ber01-VHDL13_DWOG_101700-2611101700-dsw--0-ia5 10-Nov-2026 19:00:07 4395
ber01-VHDL13_DWOG_110300-2611110300-dsw--0-ia5 11-Nov-2026 04:00:17 4890
ber01-VHDL13_DWOG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 4777
ber01-VHDL13_DWOG_111700-2611111700-dsw--0-ia5 11-Nov-2026 19:00:17 4667
ber01-VHDL13_DWOG_111700_COR-2611111700-dsw--0-ia5 11-Nov-2026 21:21:44 5142
ber01-VHDL13_DWOG_120300-2611120300-dsw--0-ia5 12-Nov-2026 04:00:15 5435
ber01-VHDL13_DWOG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 5320
ber01-VHDL13_DWON_101649-2611101649-dsw--0-ia5 10-Nov-2026 16:49:34 4067
ber01-VHDL13_DWON_101948-2611101948-dsw--0-ia5 10-Nov-2026 19:48:58 4504
ber01-VHDL13_DWON_102254-2611102254-dsw--0-ia5 10-Nov-2026 22:54:38 4481
ber01-VHDL13_DWON_110146-2611110146-dsw--0-ia5 11-Nov-2026 01:46:08 4816
ber01-VHDL13_DWON_110352-2611110352-dsw--0-ia5 11-Nov-2026 03:52:32 4758
ber01-VHDL13_DWON_110404-2611110404-dsw--0-ia5 11-Nov-2026 04:04:24 4758
ber01-VHDL13_DWON_110629-2611110629-dsw--0-ia5 11-Nov-2026 06:29:44 5021
ber01-VHDL13_DWON_110724-2611110724-dsw--0-ia5 11-Nov-2026 07:24:27 4637
ber01-VHDL13_DWON_110842-2611110842-dsw--0-ia5 11-Nov-2026 08:42:38 4636
ber01-VHDL13_DWON_110930-2611110930-dsw--0-ia5 11-Nov-2026 09:31:10 4636
ber01-VHDL13_DWON_111524-2611111524-dsw--0-ia5 11-Nov-2026 15:24:24 4328
ber01-VHDL13_DWON_111755-2611111755-dsw--0-ia5 11-Nov-2026 17:55:19 3818
ber01-VHDL13_DWON_111820-2611111820-dsw--0-ia5 11-Nov-2026 18:20:44 3818
ber01-VHDL13_DWON_112121-2611112121-dsw--0-ia5 11-Nov-2026 21:21:28 3820
ber01-VHDL13_DWON_120218-2611120218-dsw--0-ia5 12-Nov-2026 02:18:12 3870
ber01-VHDL13_DWON_120629-2611120629-dsw--0-ia5 12-Nov-2026 06:29:45 4308
ber01-VHDL13_DWON_120705-2611120705-dsw--0-ia5 12-Nov-2026 07:06:17 4315
ber01-VHDL13_DWON_121117-2611121117-dsw--0-ia5 12-Nov-2026 11:17:14 4253
ber01-VHDL13_DWON_121521-2611121521-dsw--0-ia5 12-Nov-2026 15:21:54 3625
ber01-VHDL13_DWON_121556-2611121556-dsw--0-ia5 12-Nov-2026 15:57:16 3625
ber01-VHDL13_DWPG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2652
ber01-VHDL13_DWPG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 2686
ber01-VHDL13_DWPH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 3141
ber01-VHDL13_DWPH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 3755
ber01-VHDL13_DWSG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 3873
ber01-VHDL13_DWSG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 3775
ber01-VHDL17_DWOG_111200-2611111200-dsw--0-ia5 11-Nov-2026 12:00:23 2779
ber01-VHDL17_DWOG_121200-2611121200-dsw--0-ia5 12-Nov-2026 12:32:54 2771
swis2-VHDL20_DWEG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1992
swis2-VHDL20_DWEG_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1222
swis2-VHDL20_DWEG_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:01:06 1213
swis2-VHDL20_DWEG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 1979
swis2-VHDL20_DWEG_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:04 1639
swis2-VHDL20_DWEG_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:08 1674
swis2-VHDL20_DWEG_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:01:05 1423
swis2-VHDL20_DWEG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2096
swis2-VHDL20_DWEH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1863
swis2-VHDL20_DWEH_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1105
swis2-VHDL20_DWEH_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:01:07 1481
swis2-VHDL20_DWEH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2271
swis2-VHDL20_DWEH_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:04 2164
swis2-VHDL20_DWEH_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:08 1262
swis2-VHDL20_DWEH_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:01:05 1488
swis2-VHDL20_DWEH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2177
swis2-VHDL20_DWEI_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1883
swis2-VHDL20_DWEI_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1172
swis2-VHDL20_DWEI_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:01:07 1267
swis2-VHDL20_DWEI_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 1903
swis2-VHDL20_DWEI_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:04 1890
swis2-VHDL20_DWEI_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:08 1653
swis2-VHDL20_DWEI_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:01:05 1447
swis2-VHDL20_DWEI_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2009
swis2-VHDL20_DWHG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:45:08 2595
swis2-VHDL20_DWHG_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 2172
swis2-VHDL20_DWHG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 3066
swis2-VHDL20_DWHG_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:45:08 3765
swis2-VHDL20_DWHG_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 2573
swis2-VHDL20_DWHG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 2922
swis2-VHDL20_DWHH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:45:08 2367
swis2-VHDL20_DWHH_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:45:28 1954
swis2-VHDL20_DWHH_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1971
swis2-VHDL20_DWHH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 2793
swis2-VHDL20_DWHH_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:45:08 3893
swis2-VHDL20_DWHH_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:45:12 2934
swis2-VHDL20_DWHH_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 2537
swis2-VHDL20_DWHH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:09 2548
swis2-VHDL20_DWLG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1846
swis2-VHDL20_DWLG_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:05:32 2183
swis2-VHDL20_DWLG_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:23 1642
swis2-VHDL20_DWLG_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1349
swis2-VHDL20_DWLG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:26 1759
swis2-VHDL20_DWLG_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:31:04 1576
swis2-VHDL20_DWLG_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:29 1772
swis2-VHDL20_DWLG_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1827
swis2-VHDL20_DWLG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:22 2269
swis2-VHDL20_DWLH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1604
swis2-VHDL20_DWLH_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:05:08 1934
swis2-VHDL20_DWLH_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:23 1530
swis2-VHDL20_DWLH_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1302
swis2-VHDL20_DWLH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:26 1654
swis2-VHDL20_DWLH_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:31:04 1642
swis2-VHDL20_DWLH_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:29 1513
swis2-VHDL20_DWLH_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1468
swis2-VHDL20_DWLH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:22 2013
swis2-VHDL20_DWLI_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1614
swis2-VHDL20_DWLI_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 21:06:33 1916
swis2-VHDL20_DWLI_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:23 1475
swis2-VHDL20_DWLI_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1045
swis2-VHDL20_DWLI_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:26 1395
swis2-VHDL20_DWLI_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:31:04 1388
swis2-VHDL20_DWLI_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:29 1193
swis2-VHDL20_DWLI_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1313
swis2-VHDL20_DWLI_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:22 1733
swis2-VHDL20_DWMO_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1303
swis2-VHDL20_DWMO_101800_COR-2611101800-dsw--0-ia5 10-Nov-2026 22:52:03 1586
swis2-VHDL20_DWMO_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1623
swis2-VHDL20_DWMO_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:08 1468
swis2-VHDL20_DWMO_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 1906
swis2-VHDL20_DWMO_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:10 1747
swis2-VHDL20_DWMO_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:02 1678
swis2-VHDL20_DWMO_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:11 1710
swis2-VHDL20_DWMO_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2242
swis2-VHDL20_DWMP_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:07 1693
swis2-VHDL20_DWMP_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1934
swis2-VHDL20_DWMP_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:08 1856
swis2-VHDL20_DWMP_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:04 2463
swis2-VHDL20_DWMP_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:10 2298
swis2-VHDL20_DWMP_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:02 2058
swis2-VHDL20_DWMP_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:11 2112
swis2-VHDL20_DWMP_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2747
swis2-VHDL20_DWPG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1501
swis2-VHDL20_DWPG_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:23 1201
swis2-VHDL20_DWPG_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1183
swis2-VHDL20_DWPG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:26 1457
swis2-VHDL20_DWPG_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:31:04 1432
swis2-VHDL20_DWPG_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:29 1394
swis2-VHDL20_DWPG_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1270
swis2-VHDL20_DWPG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:22 1554
swis2-VHDL20_DWPH_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:31:11 1587
swis2-VHDL20_DWPH_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:23 1318
swis2-VHDL20_DWPH_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:14 1294
swis2-VHDL20_DWPH_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:26 1656
swis2-VHDL20_DWPH_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:31:04 1797
swis2-VHDL20_DWPH_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:29 1819
swis2-VHDL20_DWPH_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1634
swis2-VHDL20_DWPH_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:22 1919
swis2-VHDL20_DWSG_101800-2611101800-dsw--0-ia5 10-Nov-2026 19:30:10 1534
swis2-VHDL20_DWSG_110200-2611110200-dsw--0-ia5 11-Nov-2026 03:30:07 1486
swis2-VHDL20_DWSG_110400-2611110400-dsw--0-ia5 11-Nov-2026 06:00:08 1725
swis2-VHDL20_DWSG_110800-2611110800-dsw--0-ia5 11-Nov-2026 09:30:08 2214
swis2-VHDL20_DWSG_111800-2611111800-dsw--0-ia5 11-Nov-2026 19:30:10 1830
swis2-VHDL20_DWSG_120200-2611120200-dsw--0-ia5 12-Nov-2026 03:30:08 1688
swis2-VHDL20_DWSG_120400-2611120400-dsw--0-ia5 12-Nov-2026 06:00:20 1870
swis2-VHDL20_DWSG_120800-2611120800-dsw--0-ia5 12-Nov-2026 09:30:03 2310
wst04-VHDL20_DWEG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 236898
wst04-VHDL20_DWEG_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:13 236810
wst04-VHDL20_DWEG_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:14 236121
wst04-VHDL20_DWEG_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:26 237614
wst04-VHDL20_DWEG_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:41 233506
wst04-VHDL20_DWEG_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:22 234313
wst04-VHDL20_DWEG_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 233197
wst04-VHDL20_DWEG_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:18 237941
wst04-VHDL20_DWEH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:25 232975
wst04-VHDL20_DWEH_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:13 233906
wst04-VHDL20_DWEH_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:14 232877
wst04-VHDL20_DWEH_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:26 234606
wst04-VHDL20_DWEH_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:29 229135
wst04-VHDL20_DWEH_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:15 230939
wst04-VHDL20_DWEH_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 229641
wst04-VHDL20_DWEH_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:18 234698
wst04-VHDL20_DWEI_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:25 334389
wst04-VHDL20_DWEI_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:19 333248
wst04-VHDL20_DWEI_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:18 333153
wst04-VHDL20_DWEI_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:30 334901
wst04-VHDL20_DWEI_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:29 329572
wst04-VHDL20_DWEI_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:22 329905
wst04-VHDL20_DWEI_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 329162
wst04-VHDL20_DWEI_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:18 336007
wst04-VHDL20_DWHG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:45:13 325757
wst04-VHDL20_DWHG_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:45:28 324000
wst04-VHDL20_DWHG_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:18 323823
wst04-VHDL20_DWHG_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:34 326451
wst04-VHDL20_DWHG_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:45:14 324029
wst04-VHDL20_DWHG_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:45:17 322657
wst04-VHDL20_DWHG_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 321381
wst04-VHDL20_DWHG_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:37 326651
wst04-VHDL20_DWHH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:45:13 314248
wst04-VHDL20_DWHH_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:45:28 312869
wst04-VHDL20_DWHH_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:26 222255
wst04-VHDL20_DWHH_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:34 314487
wst04-VHDL20_DWHH_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:45:14 317868
wst04-VHDL20_DWHH_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:45:17 316937
wst04-VHDL20_DWHH_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 225941
wst04-VHDL20_DWHH_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:37 318313
wst04-VHDL20_DWLG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:37 321457
wst04-VHDL20_DWLG_101800_COR-2611101800-omedes-..> 10-Nov-2026 20:58:54 321896
wst04-VHDL20_DWLG_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:29 320608
wst04-VHDL20_DWLG_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:56 320582
wst04-VHDL20_DWLG_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:44 322004
wst04-VHDL20_DWLG_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:31:24 314125
wst04-VHDL20_DWLG_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:29 358683
wst04-VHDL20_DWLG_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:43 314193
wst04-VHDL20_DWLG_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:59 317315
wst04-VHDL20_DWLH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 316317
wst04-VHDL20_DWLH_101800_COR-2611101800-omedes-..> 10-Nov-2026 20:57:45 316506
wst04-VHDL20_DWLH_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:23 315168
wst04-VHDL20_DWLH_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:56 315819
wst04-VHDL20_DWLH_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:44 316685
wst04-VHDL20_DWLH_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:31:24 313788
wst04-VHDL20_DWLH_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:24 358266
wst04-VHDL20_DWLH_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:43 313082
wst04-VHDL20_DWLH_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:59 321007
wst04-VHDL20_DWLI_101800-2611101800-omedes--0.pdf 10-Nov-2026 20:59:35 316548
wst04-VHDL20_DWLI_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:29 315623
wst04-VHDL20_DWLI_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:56 314675
wst04-VHDL20_DWLI_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:50 360664
wst04-VHDL20_DWLI_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:31:35 319627
wst04-VHDL20_DWLI_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:24 363319
wst04-VHDL20_DWLI_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:43 318324
wst04-VHDL20_DWLI_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:59 369005
wst04-VHDL20_DWMO_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:14 441780
wst04-VHDL20_DWMO_101800_COR-2611101800-omedes-..> 10-Nov-2026 22:52:27 442756
wst04-VHDL20_DWMO_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:19 443527
wst04-VHDL20_DWMO_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:18 443642
wst04-VHDL20_DWMO_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:14 443334
wst04-VHDL20_DWMO_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:29 440646
wst04-VHDL20_DWMO_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:15 441234
wst04-VHDL20_DWMO_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 441772
wst04-VHDL20_DWMO_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:24 430695
wst04-VHDL20_DWMP_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 557505
wst04-VHDL20_DWMP_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:19 558211
wst04-VHDL20_DWMP_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:18 557510
wst04-VHDL20_DWMP_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:14 560044
wst04-VHDL20_DWMP_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:29 565661
wst04-VHDL20_DWMP_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:24 565533
wst04-VHDL20_DWMP_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 565395
wst04-VHDL20_DWMP_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:24 555112
wst04-VHDL20_DWPG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 319306
wst04-VHDL20_DWPG_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:23 228581
wst04-VHDL20_DWPG_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:45 317937
wst04-VHDL20_DWPG_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:44 363872
wst04-VHDL20_DWPG_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:31:24 313454
wst04-VHDL20_DWPG_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:29 225760
wst04-VHDL20_DWPG_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:41 312112
wst04-VHDL20_DWPG_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:59 363981
wst04-VHDL20_DWPH_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:31:35 231519
wst04-VHDL20_DWPH_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:23 231105
wst04-VHDL20_DWPH_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:45 231487
wst04-VHDL20_DWPH_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:44 232128
wst04-VHDL20_DWPH_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:31:24 227373
wst04-VHDL20_DWPH_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:24 272055
wst04-VHDL20_DWPH_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:41 226639
wst04-VHDL20_DWPH_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:59 228382
wst04-VHDL20_DWSG_101800-2611101800-omedes--0.pdf 10-Nov-2026 19:30:18 342559
wst04-VHDL20_DWSG_110200-2611110200-omedes--0.pdf 11-Nov-2026 03:30:13 342589
wst04-VHDL20_DWSG_110400-2611110400-omedes--0.pdf 11-Nov-2026 06:00:14 342941
wst04-VHDL20_DWSG_110800-2611110800-omedes--0.pdf 11-Nov-2026 09:30:28 343428
wst04-VHDL20_DWSG_111800-2611111800-omedes--0.pdf 11-Nov-2026 19:30:18 348436
wst04-VHDL20_DWSG_120200-2611120200-omedes--0.pdf 12-Nov-2026 03:30:15 348416
wst04-VHDL20_DWSG_120400-2611120400-omedes--0.pdf 12-Nov-2026 06:00:20 348340
wst04-VHDL20_DWSG_120800-2611120800-omedes--0.pdf 12-Nov-2026 09:30:18 346222