Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Jun-2026 11:49:54 4499
FPDL13_DWMZ_150600 15-Jun-2026 13:16:05 4046
SXDL31_DWAV_140800 14-Jun-2026 07:08:34 5892
SXDL31_DWAV_141800 14-Jun-2026 16:37:37 7280
SXDL31_DWAV_150800 15-Jun-2026 07:37:43 8179
SXDL31_DWAV_151800 15-Jun-2026 16:50:04 7815
SXDL31_DWAV_LATEST 15-Jun-2026 16:50:04 7815
SXDL33_DWAV_140000 14-Jun-2026 10:44:30 8894
SXDL33_DWAV_150000 15-Jun-2026 09:57:19 11847
SXDL33_DWAV_LATEST 15-Jun-2026 09:57:19 11847
ber01-FWDL39_DWMS_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:35:09 1268
ber01-FWDL39_DWMS_151200-2606151200-dsw--0-ia5 15-Jun-2026 10:53:20 1126
ber01-VHDL13_DWEG_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:16 2411
ber01-VHDL13_DWEG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:18 2997
ber01-VHDL13_DWEH_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:36 2297
ber01-VHDL13_DWEH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:12 2935
ber01-VHDL13_DWEI_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:52 2333
ber01-VHDL13_DWEI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:16 2811
ber01-VHDL13_DWHG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 3040
ber01-VHDL13_DWHG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 3469
ber01-VHDL13_DWHH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 3236
ber01-VHDL13_DWHH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 2867
ber01-VHDL13_DWLG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 3020
ber01-VHDL13_DWLG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3088
ber01-VHDL13_DWLH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2874
ber01-VHDL13_DWLH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3131
ber01-VHDL13_DWLI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2337
ber01-VHDL13_DWLI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2722
ber01-VHDL13_DWMO_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2835
ber01-VHDL13_DWMO_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2890
ber01-VHDL13_DWMP_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2892
ber01-VHDL13_DWMP_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2536
ber01-VHDL13_DWOG_131700-2606131700-dsw--0-ia5 13-Jun-2026 18:00:02 4061
ber01-VHDL13_DWOG_140300-2606140300-dsw--0-ia5 14-Jun-2026 03:00:06 4526
ber01-VHDL13_DWOG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 4351
ber01-VHDL13_DWOG_141700-2606141700-dsw--0-ia5 14-Jun-2026 18:00:02 3580
ber01-VHDL13_DWOG_150300-2606150300-dsw--0-ia5 15-Jun-2026 03:00:03 3506
ber01-VHDL13_DWOG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 4136
ber01-VHDL13_DWON_131826-2606131826-dsw--0-ia5 13-Jun-2026 18:26:37 3516
ber01-VHDL13_DWON_132128-2606132128-dsw--0-ia5 13-Jun-2026 21:28:36 3500
ber01-VHDL13_DWON_140133-2606140133-dsw--0-ia5 14-Jun-2026 01:33:46 3980
ber01-VHDL13_DWON_140231-2606140231-dsw--0-ia5 14-Jun-2026 02:31:42 3980
ber01-VHDL13_DWON_140523-2606140523-dsw--0-ia5 14-Jun-2026 05:23:36 3744
ber01-VHDL13_DWON_141325-2606141325-dsw--0-ia5 14-Jun-2026 13:26:03 4154
ber01-VHDL13_DWON_141728-2606141728-dsw--0-ia5 14-Jun-2026 17:28:27 3385
ber01-VHDL13_DWON_141741-2606141741-dsw--0-ia5 14-Jun-2026 17:41:47 3385
ber01-VHDL13_DWON_150035-2606150035-dsw--0-ia5 15-Jun-2026 00:35:08 3832
ber01-VHDL13_DWON_150149-2606150149-dsw--0-ia5 15-Jun-2026 01:49:46 3812
ber01-VHDL13_DWON_150517-2606150517-dsw--0-ia5 15-Jun-2026 05:17:11 3876
ber01-VHDL13_DWON_150611-2606150611-dsw--0-ia5 15-Jun-2026 06:11:57 3952
ber01-VHDL13_DWON_150811-2606150811-dsw--0-ia5 15-Jun-2026 08:11:31 4056
ber01-VHDL13_DWON_150910-2606150910-dsw--0-ia5 15-Jun-2026 09:10:52 4056
ber01-VHDL13_DWON_151017-2606151017-dsw--0-ia5 15-Jun-2026 10:17:51 4064
ber01-VHDL13_DWON_151440-2606151440-dsw--0-ia5 15-Jun-2026 14:40:32 3790
ber01-VHDL13_DWON_151703-2606151703-dsw--0-ia5 15-Jun-2026 17:03:11 3399
ber01-VHDL13_DWPG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 2708
ber01-VHDL13_DWPG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3104
ber01-VHDL13_DWPH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 3160
ber01-VHDL13_DWPH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2872
ber01-VHDL13_DWSG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 2665
ber01-VHDL13_DWSG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2363
ber01-VHDL17_DWOG_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:36:53 3479
ber01-VHDL17_DWOG_151200-2606151200-dsw--0-ia5 15-Jun-2026 10:54:11 3600
swis2-VHDL20_DWEG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 983
swis2-VHDL20_DWEG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 840
swis2-VHDL20_DWEG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 819
swis2-VHDL20_DWEG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 935
swis2-VHDL20_DWEG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1113
swis2-VHDL20_DWEG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 985
swis2-VHDL20_DWEG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1067
swis2-VHDL20_DWEG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:14 1296
swis2-VHDL20_DWEH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1000
swis2-VHDL20_DWEH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 844
swis2-VHDL20_DWEH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 823
swis2-VHDL20_DWEH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 933
swis2-VHDL20_DWEH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1185
swis2-VHDL20_DWEH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 1000
swis2-VHDL20_DWEH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1102
swis2-VHDL20_DWEH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:14 1313
swis2-VHDL20_DWEI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 970
swis2-VHDL20_DWEI_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 826
swis2-VHDL20_DWEI_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:01:21 826
swis2-VHDL20_DWEI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 942
swis2-VHDL20_DWEI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1181
swis2-VHDL20_DWEI_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 942
swis2-VHDL20_DWEI_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1118
swis2-VHDL20_DWEI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 1335
swis2-VHDL20_DWHG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 1795
swis2-VHDL20_DWHG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:45:06 1630
swis2-VHDL20_DWHG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1627
swis2-VHDL20_DWHG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:45:05 1446
swis2-VHDL20_DWHG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1538
swis2-VHDL20_DWHG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:45:08 1575
swis2-VHDL20_DWHG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1552
swis2-VHDL20_DWHG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:45:02 1818
swis2-VHDL20_DWHH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:45:01 2029
swis2-VHDL20_DWHH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:45:06 1568
swis2-VHDL20_DWHH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1641
swis2-VHDL20_DWHH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:45:05 1669
swis2-VHDL20_DWHH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1721
swis2-VHDL20_DWHH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:45:08 1516
swis2-VHDL20_DWHH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1248
swis2-VHDL20_DWHH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:45:02 1358
swis2-VHDL20_DWLG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1111
swis2-VHDL20_DWLG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1106
swis2-VHDL20_DWLG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1371
swis2-VHDL20_DWLG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1649
swis2-VHDL20_DWLG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1234
swis2-VHDL20_DWLG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1451
swis2-VHDL20_DWLG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1409
swis2-VHDL20_DWLG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1475
swis2-VHDL20_DWLH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1392
swis2-VHDL20_DWLH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1308
swis2-VHDL20_DWLH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1296
swis2-VHDL20_DWLH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1574
swis2-VHDL20_DWLH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1261
swis2-VHDL20_DWLH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1408
swis2-VHDL20_DWLH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1391
swis2-VHDL20_DWLH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1484
swis2-VHDL20_DWLI_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 937
swis2-VHDL20_DWLI_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 965
swis2-VHDL20_DWLI_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 959
swis2-VHDL20_DWLI_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1237
swis2-VHDL20_DWLI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1015
swis2-VHDL20_DWLI_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1183
swis2-VHDL20_DWLI_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1099
swis2-VHDL20_DWLI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1165
swis2-VHDL20_DWMO_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1301
swis2-VHDL20_DWMO_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 1228
swis2-VHDL20_DWMO_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:06 1244
swis2-VHDL20_DWMO_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 1251
swis2-VHDL20_DWMO_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1113
swis2-VHDL20_DWMO_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 989
swis2-VHDL20_DWMO_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:03 1002
swis2-VHDL20_DWMO_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1236
swis2-VHDL20_DWMP_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1551
swis2-VHDL20_DWMP_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:08 1461
swis2-VHDL20_DWMP_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:06 1476
swis2-VHDL20_DWMP_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:01 1351
swis2-VHDL20_DWMP_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1244
swis2-VHDL20_DWMP_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 933
swis2-VHDL20_DWMP_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:03 941
swis2-VHDL20_DWMP_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1110
swis2-VHDL20_DWPG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1291
swis2-VHDL20_DWPG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1161
swis2-VHDL20_DWPG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1240
swis2-VHDL20_DWPG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1353
swis2-VHDL20_DWPG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1177
swis2-VHDL20_DWPG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1171
swis2-VHDL20_DWPG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1288
swis2-VHDL20_DWPG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1427
swis2-VHDL20_DWPH_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:31:04 1492
swis2-VHDL20_DWPH_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:29 1380
swis2-VHDL20_DWPH_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:12 1492
swis2-VHDL20_DWPH_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:28 1578
swis2-VHDL20_DWPH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1690
swis2-VHDL20_DWPH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1392
swis2-VHDL20_DWPH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1308
swis2-VHDL20_DWPH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1308
swis2-VHDL20_DWSG_131800-2606131800-dsw--0-ia5 13-Jun-2026 18:30:02 1381
swis2-VHDL20_DWSG_140200-2606140200-dsw--0-ia5 14-Jun-2026 02:30:02 1155
swis2-VHDL20_DWSG_140400-2606140400-dsw--0-ia5 14-Jun-2026 05:00:16 1154
swis2-VHDL20_DWSG_140800-2606140800-dsw--0-ia5 14-Jun-2026 08:30:07 1200
swis2-VHDL20_DWSG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1102
swis2-VHDL20_DWSG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:01 844
swis2-VHDL20_DWSG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:17 909
swis2-VHDL20_DWSG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1109
wst04-VHDL20_DWEG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 238572
wst04-VHDL20_DWEG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 237721
wst04-VHDL20_DWEG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 237257
wst04-VHDL20_DWEG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 238010
wst04-VHDL20_DWEG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 241683
wst04-VHDL20_DWEG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 240407
wst04-VHDL20_DWEG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 240318
wst04-VHDL20_DWEG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:15 241264
wst04-VHDL20_DWEH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 236082
wst04-VHDL20_DWEH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 235563
wst04-VHDL20_DWEH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 235371
wst04-VHDL20_DWEH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 236119
wst04-VHDL20_DWEH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 239515
wst04-VHDL20_DWEH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 238461
wst04-VHDL20_DWEH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 238704
wst04-VHDL20_DWEH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:14 239615
wst04-VHDL20_DWEI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 338034
wst04-VHDL20_DWEI_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 337767
wst04-VHDL20_DWEI_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 337773
wst04-VHDL20_DWEI_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:18 338040
wst04-VHDL20_DWEI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343740
wst04-VHDL20_DWEI_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 343131
wst04-VHDL20_DWEI_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 343016
wst04-VHDL20_DWEI_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 343400
wst04-VHDL20_DWHG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 337810
wst04-VHDL20_DWHG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:45:12 337626
wst04-VHDL20_DWHG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 337621
wst04-VHDL20_DWHG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:45:16 336880
wst04-VHDL20_DWHG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 336568
wst04-VHDL20_DWHG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:45:20 336513
wst04-VHDL20_DWHG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 336126
wst04-VHDL20_DWHG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:45:12 337709
wst04-VHDL20_DWHH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:45:11 326363
wst04-VHDL20_DWHH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:45:12 325557
wst04-VHDL20_DWHH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 229095
wst04-VHDL20_DWHH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:45:16 325154
wst04-VHDL20_DWHH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 326497
wst04-VHDL20_DWHH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:45:20 326290
wst04-VHDL20_DWHH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 225991
wst04-VHDL20_DWHH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:45:12 324728
wst04-VHDL20_DWLG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 340325
wst04-VHDL20_DWLG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 340226
wst04-VHDL20_DWLG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 340578
wst04-VHDL20_DWLG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 341330
wst04-VHDL20_DWLG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337538
wst04-VHDL20_DWLG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 337712
wst04-VHDL20_DWLG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 337947
wst04-VHDL20_DWLG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:47 338131
wst04-VHDL20_DWLH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 331737
wst04-VHDL20_DWLH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 330448
wst04-VHDL20_DWLH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 330559
wst04-VHDL20_DWLH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 331355
wst04-VHDL20_DWLH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 333101
wst04-VHDL20_DWLH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 333270
wst04-VHDL20_DWLH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 333510
wst04-VHDL20_DWLH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 333714
wst04-VHDL20_DWLI_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 335223
wst04-VHDL20_DWLI_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 334906
wst04-VHDL20_DWLI_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:42 334940
wst04-VHDL20_DWLI_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 380650
wst04-VHDL20_DWLI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 341239
wst04-VHDL20_DWLI_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:32 341936
wst04-VHDL20_DWLI_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 342013
wst04-VHDL20_DWLI_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 386811
wst04-VHDL20_DWMO_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 347509
wst04-VHDL20_DWMO_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 451652
wst04-VHDL20_DWMO_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 451528
wst04-VHDL20_DWMO_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:18 451352
wst04-VHDL20_DWMO_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 353665
wst04-VHDL20_DWMO_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:17 460301
wst04-VHDL20_DWMO_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 460207
wst04-VHDL20_DWMO_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 460759
wst04-VHDL20_DWMP_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:17 464262
wst04-VHDL20_DWMP_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 570548
wst04-VHDL20_DWMP_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:16 570360
wst04-VHDL20_DWMP_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:28 463874
wst04-VHDL20_DWMP_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 459630
wst04-VHDL20_DWMP_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:17 570178
wst04-VHDL20_DWMP_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 570095
wst04-VHDL20_DWMP_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 459641
wst04-VHDL20_DWPG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 341820
wst04-VHDL20_DWPG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 240610
wst04-VHDL20_DWPG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:32 341436
wst04-VHDL20_DWPG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 386206
wst04-VHDL20_DWPG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337780
wst04-VHDL20_DWPG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 238368
wst04-VHDL20_DWPG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:31 338075
wst04-VHDL20_DWPG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 384516
wst04-VHDL20_DWPH_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:31:27 241359
wst04-VHDL20_DWPH_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:29 240805
wst04-VHDL20_DWPH_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:32 241091
wst04-VHDL20_DWPH_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:49 241179
wst04-VHDL20_DWPH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 243201
wst04-VHDL20_DWPH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 241998
wst04-VHDL20_DWPH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:31 242065
wst04-VHDL20_DWPH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 242537
wst04-VHDL20_DWSG_131800-2606131800-omedes--0.pdf 13-Jun-2026 18:30:13 347303
wst04-VHDL20_DWSG_140200-2606140200-omedes--0.pdf 14-Jun-2026 02:30:14 346529
wst04-VHDL20_DWSG_140400-2606140400-omedes--0.pdf 14-Jun-2026 05:00:12 346545
wst04-VHDL20_DWSG_140800-2606140800-omedes--0.pdf 14-Jun-2026 08:30:12 347288
wst04-VHDL20_DWSG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343341
wst04-VHDL20_DWSG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 341628
wst04-VHDL20_DWSG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:11 342218
wst04-VHDL20_DWSG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 342815