Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_200600 20-Jul-2026 13:54:54 4470
FPDL13_DWMZ_210600 21-Jul-2026 14:25:45 7250
SXDL31_DWAV_200800 20-Jul-2026 06:55:29 7288
SXDL31_DWAV_201800 20-Jul-2026 15:05:58 3853
SXDL31_DWAV_210800 21-Jul-2026 08:03:59 11202
SXDL31_DWAV_211800 21-Jul-2026 15:54:43 4954
SXDL31_DWAV_LATEST 21-Jul-2026 15:54:43 4954
SXDL33_DWAV_200000 20-Jul-2026 10:47:19 5204
SXDL33_DWAV_210000 21-Jul-2026 10:03:08 6150
SXDL33_DWAV_LATEST 21-Jul-2026 10:03:08 6150
ber01-FWDL39_DWMS_201200-2607201200-dsw--0-ia5 20-Jul-2026 11:13:26 1471
ber01-FWDL39_DWMS_211200-2607211200-dsw--0-ia5 21-Jul-2026 10:17:46 1141
ber01-VHDL13_DWEG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:11 2773
ber01-VHDL13_DWEG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2742
ber01-VHDL13_DWEH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:17 2649
ber01-VHDL13_DWEH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2768
ber01-VHDL13_DWEI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:17 2533
ber01-VHDL13_DWEI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:28:17 2525
ber01-VHDL13_DWHG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 3769
ber01-VHDL13_DWHG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3739
ber01-VHDL13_DWHH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 3630
ber01-VHDL13_DWHH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3867
ber01-VHDL13_DWLG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2266
ber01-VHDL13_DWLG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2501
ber01-VHDL13_DWLH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2498
ber01-VHDL13_DWLH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2588
ber01-VHDL13_DWLI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2151
ber01-VHDL13_DWLI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2296
ber01-VHDL13_DWMO_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2863
ber01-VHDL13_DWMO_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2415
ber01-VHDL13_DWMP_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2814
ber01-VHDL13_DWMP_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2587
ber01-VHDL13_DWOG_200300-2607200300-dsw--0-ia5 20-Jul-2026 03:00:01 4402
ber01-VHDL13_DWOG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 4173
ber01-VHDL13_DWOG_201700-2607201700-dsw--0-ia5 20-Jul-2026 18:00:02 3545
ber01-VHDL13_DWOG_210300-2607210300-dsw--0-ia5 21-Jul-2026 03:00:07 3431
ber01-VHDL13_DWOG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3165
ber01-VHDL13_DWOG_211700-2607211700-dsw--0-ia5 21-Jul-2026 18:00:01 3717
ber01-VHDL13_DWOG_211700_COR-2607211700-dsw--0-ia5 21-Jul-2026 19:54:25 4268
ber01-VHDL13_DWON_200002-2607200002-dsw--0-ia5 20-Jul-2026 00:02:27 4284
ber01-VHDL13_DWON_200149-2607200149-dsw--0-ia5 20-Jul-2026 01:49:13 4344
ber01-VHDL13_DWON_200255-2607200255-dsw--0-ia5 20-Jul-2026 02:55:57 4341
ber01-VHDL13_DWON_200312-2607200312-dsw--0-ia5 20-Jul-2026 03:12:47 4341
ber01-VHDL13_DWON_200528-2607200528-dsw--0-ia5 20-Jul-2026 05:28:52 4071
ber01-VHDL13_DWON_200607-2607200607-dsw--0-ia5 20-Jul-2026 06:07:16 4071
ber01-VHDL13_DWON_200807-2607200807-dsw--0-ia5 20-Jul-2026 08:07:57 4071
ber01-VHDL13_DWON_201044-2607201044-dsw--0-ia5 20-Jul-2026 10:45:04 4071
ber01-VHDL13_DWON_201441-2607201441-dsw--0-ia5 20-Jul-2026 14:41:24 3495
ber01-VHDL13_DWON_201745-2607201745-dsw--0-ia5 20-Jul-2026 17:45:37 3522
ber01-VHDL13_DWON_201804-2607201804-dsw--0-ia5 20-Jul-2026 18:05:02 3522
ber01-VHDL13_DWON_201847-2607201847-dsw--0-ia5 20-Jul-2026 18:47:56 3421
ber01-VHDL13_DWON_201849-2607201849-dsw--0-ia5 20-Jul-2026 18:50:02 3421
ber01-VHDL13_DWON_202059-2607202059-dsw--0-ia5 20-Jul-2026 20:59:38 3388
ber01-VHDL13_DWON_202109-2607202109-dsw--0-ia5 20-Jul-2026 21:09:41 3388
ber01-VHDL13_DWON_210003-2607210003-dsw--0-ia5 21-Jul-2026 00:03:11 3913
ber01-VHDL13_DWON_210140-2607210140-dsw--0-ia5 21-Jul-2026 01:40:39 3879
ber01-VHDL13_DWON_210243-2607210243-dsw--0-ia5 21-Jul-2026 02:44:09 3879
ber01-VHDL13_DWON_210530-2607210530-dsw--0-ia5 21-Jul-2026 05:30:11 3389
ber01-VHDL13_DWON_210603-2607210603-dsw--0-ia5 21-Jul-2026 06:03:33 3957
ber01-VHDL13_DWON_210854-2607210854-dsw--0-ia5 21-Jul-2026 08:54:27 3957
ber01-VHDL13_DWON_211048-2607211048-dsw--0-ia5 21-Jul-2026 10:48:57 3957
ber01-VHDL13_DWON_211530-2607211530-dsw--0-ia5 21-Jul-2026 15:30:39 3705
ber01-VHDL13_DWON_211555-2607211555-dsw--0-ia5 21-Jul-2026 15:55:42 3705
ber01-VHDL13_DWON_211702-2607211702-dsw--0-ia5 21-Jul-2026 17:02:46 3255
ber01-VHDL13_DWON_211953-2607211953-dsw--0-ia5 21-Jul-2026 19:53:56 4251
ber01-VHDL13_DWPG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2359
ber01-VHDL13_DWPG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2561
ber01-VHDL13_DWPH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 3196
ber01-VHDL13_DWPH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 3289
ber01-VHDL13_DWSG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2202
ber01-VHDL13_DWSG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 2190
ber01-VHDL17_DWOG_201200-2607201200-dsw--0-ia5 20-Jul-2026 12:10:52 3384
ber01-VHDL17_DWOG_211200-2607211200-dsw--0-ia5 21-Jul-2026 11:13:01 2727
swis2-VHDL20_DWEG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 807
swis2-VHDL20_DWEG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 723
swis2-VHDL20_DWEG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1024
swis2-VHDL20_DWEG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1059
swis2-VHDL20_DWEG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:01 967
swis2-VHDL20_DWEG_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:01:17 900
swis2-VHDL20_DWEG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1017
swis2-VHDL20_DWEG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1045
swis2-VHDL20_DWEH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 821
swis2-VHDL20_DWEH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 738
swis2-VHDL20_DWEH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1033
swis2-VHDL20_DWEH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1062
swis2-VHDL20_DWEH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:02 975
swis2-VHDL20_DWEH_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:01:17 911
swis2-VHDL20_DWEH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1022
swis2-VHDL20_DWEH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1093
swis2-VHDL20_DWEI_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 829
swis2-VHDL20_DWEI_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 745
swis2-VHDL20_DWEI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 945
swis2-VHDL20_DWEI_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 865
swis2-VHDL20_DWEI_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:01 958
swis2-VHDL20_DWEI_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:01:17 919
swis2-VHDL20_DWEI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1036
swis2-VHDL20_DWEI_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:07 1068
swis2-VHDL20_DWHG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:45:16 1778
swis2-VHDL20_DWHG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:16 1775
swis2-VHDL20_DWHG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:45:24 2068
swis2-VHDL20_DWHG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:45:10 1546
swis2-VHDL20_DWHG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:46:07 1684
swis2-VHDL20_DWHG_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:17 1681
swis2-VHDL20_DWHG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:45:21 1662
swis2-VHDL20_DWHG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:45:08 1600
swis2-VHDL20_DWHH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:45:16 1770
swis2-VHDL20_DWHH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:16 1770
swis2-VHDL20_DWHH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:45:24 2386
swis2-VHDL20_DWHH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:45:10 2080
swis2-VHDL20_DWHH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:46:07 2092
swis2-VHDL20_DWHH_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:17 2092
swis2-VHDL20_DWHH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:45:21 2023
swis2-VHDL20_DWHH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:45:08 1937
swis2-VHDL20_DWLG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 850
swis2-VHDL20_DWLG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 849
swis2-VHDL20_DWLG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 954
swis2-VHDL20_DWLG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1005
swis2-VHDL20_DWLG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 858
swis2-VHDL20_DWLG_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:11 862
swis2-VHDL20_DWLG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 993
swis2-VHDL20_DWLG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1027
swis2-VHDL20_DWLH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1100
swis2-VHDL20_DWLH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1017
swis2-VHDL20_DWLH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1181
swis2-VHDL20_DWLH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1274
swis2-VHDL20_DWLH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1277
swis2-VHDL20_DWLH_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:11 1244
swis2-VHDL20_DWLH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1181
swis2-VHDL20_DWLH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1224
swis2-VHDL20_DWLI_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 843
swis2-VHDL20_DWLI_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 849
swis2-VHDL20_DWLI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 954
swis2-VHDL20_DWLI_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 960
swis2-VHDL20_DWLI_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 857
swis2-VHDL20_DWLI_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:11 861
swis2-VHDL20_DWLI_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 975
swis2-VHDL20_DWLI_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 974
swis2-VHDL20_DWMO_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:01 751
swis2-VHDL20_DWMO_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:02 811
swis2-VHDL20_DWMO_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1010
swis2-VHDL20_DWMO_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1073
swis2-VHDL20_DWMO_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:02 863
swis2-VHDL20_DWMO_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:07 865
swis2-VHDL20_DWMO_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 964
swis2-VHDL20_DWMO_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1060
swis2-VHDL20_DWMP_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:01 750
swis2-VHDL20_DWMP_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:02 809
swis2-VHDL20_DWMP_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1075
swis2-VHDL20_DWMP_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1169
swis2-VHDL20_DWMP_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:11 862
swis2-VHDL20_DWMP_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:07 863
swis2-VHDL20_DWMP_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 1070
swis2-VHDL20_DWMP_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1102
swis2-VHDL20_DWPG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1108
swis2-VHDL20_DWPG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1102
swis2-VHDL20_DWPG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1078
swis2-VHDL20_DWPG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1019
swis2-VHDL20_DWPG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1025
swis2-VHDL20_DWPG_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:11 987
swis2-VHDL20_DWPG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1095
swis2-VHDL20_DWPG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1178
swis2-VHDL20_DWPH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1395
swis2-VHDL20_DWPH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1427
swis2-VHDL20_DWPH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1711
swis2-VHDL20_DWPH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1217
swis2-VHDL20_DWPH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1297
swis2-VHDL20_DWPH_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:11 1351
swis2-VHDL20_DWPH_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:28 1594
swis2-VHDL20_DWPH_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:31:03 1631
swis2-VHDL20_DWSG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 713
swis2-VHDL20_DWSG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:18 782
swis2-VHDL20_DWSG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 853
swis2-VHDL20_DWSG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:13 862
swis2-VHDL20_DWSG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:11 814
swis2-VHDL20_DWSG_210400-2607210400-dsw--0-ia5 21-Jul-2026 05:00:21 804
swis2-VHDL20_DWSG_210800-2607210800-dsw--0-ia5 21-Jul-2026 08:30:06 869
swis2-VHDL20_DWSG_211800-2607211800-dsw--0-ia5 21-Jul-2026 18:30:01 1080
wst04-VHDL20_DWEG_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:30:12 236853
wst04-VHDL20_DWEG_200400-2607200400-omedes--0.pdf 20-Jul-2026 05:00:12 235635
wst04-VHDL20_DWEG_200800-2607200800-omedes--0.pdf 20-Jul-2026 08:30:15 236802
wst04-VHDL20_DWEG_201800-2607201800-omedes--0.pdf 20-Jul-2026 18:30:13 234546
wst04-VHDL20_DWEG_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:13 234436
wst04-VHDL20_DWEG_210400-2607210400-omedes--0.pdf 21-Jul-2026 05:00:11 233679
wst04-VHDL20_DWEG_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 234453
wst04-VHDL20_DWEG_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:13 238513
wst04-VHDL20_DWEH_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:30:12 234568
wst04-VHDL20_DWEH_200400-2607200400-omedes--0.pdf 20-Jul-2026 05:00:12 233660
wst04-VHDL20_DWEH_200800-2607200800-omedes--0.pdf 20-Jul-2026 08:30:15 234789
wst04-VHDL20_DWEH_201800-2607201800-omedes--0.pdf 20-Jul-2026 18:30:13 232880
wst04-VHDL20_DWEH_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:13 233089
wst04-VHDL20_DWEH_210400-2607210400-omedes--0.pdf 21-Jul-2026 05:00:11 232677
wst04-VHDL20_DWEH_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 233430
wst04-VHDL20_DWEH_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:13 231838
wst04-VHDL20_DWEI_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:30:12 341334
wst04-VHDL20_DWEI_200400-2607200400-omedes--0.pdf 20-Jul-2026 05:00:12 340085
wst04-VHDL20_DWEI_200800-2607200800-omedes--0.pdf 20-Jul-2026 08:30:15 340360
wst04-VHDL20_DWEI_201800-2607201800-omedes--0.pdf 20-Jul-2026 18:30:13 335094
wst04-VHDL20_DWEI_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:13 335964
wst04-VHDL20_DWEI_210400-2607210400-omedes--0.pdf 21-Jul-2026 05:00:11 335154
wst04-VHDL20_DWEI_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:15 335415
wst04-VHDL20_DWEI_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:20 340627
wst04-VHDL20_DWHG_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:45:16 347489
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wst04-VHDL20_DWSG_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:11 338913
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wst04-VHDL20_DWSG_210800-2607210800-omedes--0.pdf 21-Jul-2026 08:30:23 339175
wst04-VHDL20_DWSG_211800-2607211800-omedes--0.pdf 21-Jul-2026 18:30:13 340433