Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_260600 26-Dec-2025 13:22:59 1807
FPDL13_DWMZ_270600 27-Dec-2025 12:51:05 4781
SXDL31_DWAV_260800 26-Dec-2025 08:33:04 9993
SXDL31_DWAV_261800 26-Dec-2025 17:26:23 5318
SXDL31_DWAV_270800 27-Dec-2025 08:30:40 7978
SXDL31_DWAV_271800 27-Dec-2025 18:12:59 6272
SXDL31_DWAV_LATEST 27-Dec-2025 18:12:59 6272
SXDL33_DWAV_260000 26-Dec-2025 10:55:44 5445
SXDL33_DWAV_270000 27-Dec-2025 11:04:02 14242
SXDL33_DWAV_LATEST 27-Dec-2025 11:04:02 14242
ber01-FWDL39_DWMS_261230-2512261230-dsw--0-ia5 26-Dec-2025 12:05:46 1069
ber01-FWDL39_DWMS_271230-2512271230-dsw--0-ia5 27-Dec-2025 12:40:52 1529
ber01-FWDL39_DWMS_271230_COR-2512271230-dsw--0-ia5 27-Dec-2025 12:46:11 1533
ber01-VHDL13_DWEH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:16 3351
ber01-VHDL13_DWEH_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:11 3309
ber01-VHDL13_DWEH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:16 3180
ber01-VHDL13_DWEH_261800-2512261800-dsw--0-ia5 26-Dec-2025 22:05:36 3129
ber01-VHDL13_DWEH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:28:17 3857
ber01-VHDL13_DWEH_270400-2512270400-dsw--0-ia5 27-Dec-2025 05:58:13 3590
ber01-VHDL13_DWEH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:28:16 3502
ber01-VHDL13_DWEH_270800_COR-2512270800-dsw--0-ia5 27-Dec-2025 13:59:32 3608
ber01-VHDL13_DWEH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:17 3394
ber01-VHDL13_DWHG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:09 3394
ber01-VHDL13_DWHG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3402
ber01-VHDL13_DWHG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 3385
ber01-VHDL13_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:58:23 3269
ber01-VHDL13_DWHG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:12 3184
ber01-VHDL13_DWHG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:01:11 3156
ber01-VHDL13_DWHG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 3482
ber01-VHDL13_DWHG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 3825
ber01-VHDL13_DWHG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 3872
ber01-VHDL13_DWHG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:06 3517
ber01-VHDL13_DWHH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:09 3041
ber01-VHDL13_DWHH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3009
ber01-VHDL13_DWHH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2836
ber01-VHDL13_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:58:57 2732
ber01-VHDL13_DWHH_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:12 2778
ber01-VHDL13_DWHH_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:02:01 2834
ber01-VHDL13_DWHH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 3461
ber01-VHDL13_DWHH_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 3631
ber01-VHDL13_DWHH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 3505
ber01-VHDL13_DWHH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:06 3337
ber01-VHDL13_DWLG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2063
ber01-VHDL13_DWLG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2130
ber01-VHDL13_DWLG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2303
ber01-VHDL13_DWLG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1938
ber01-VHDL13_DWLG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2523
ber01-VHDL13_DWLG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 2531
ber01-VHDL13_DWLG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 2438
ber01-VHDL13_DWLG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2139
ber01-VHDL13_DWLH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 1972
ber01-VHDL13_DWLH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2105
ber01-VHDL13_DWLH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2629
ber01-VHDL13_DWLH_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1830
ber01-VHDL13_DWLH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2374
ber01-VHDL13_DWLH_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 2402
ber01-VHDL13_DWLH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 2217
ber01-VHDL13_DWLH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2000
ber01-VHDL13_DWLI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 1763
ber01-VHDL13_DWLI_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2061
ber01-VHDL13_DWLI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2529
ber01-VHDL13_DWLI_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1551
ber01-VHDL13_DWLI_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2129
ber01-VHDL13_DWLI_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 2373
ber01-VHDL13_DWLI_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 2100
ber01-VHDL13_DWLI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1904
ber01-VHDL13_DWMG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 3184
ber01-VHDL13_DWMG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 3202
ber01-VHDL13_DWMG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2885
ber01-VHDL13_DWMG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 2934
ber01-VHDL13_DWMG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:18 2938
ber01-VHDL13_DWMG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 3475
ber01-VHDL13_DWMG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:02 3243
ber01-VHDL13_DWMG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 3115
ber01-VHDL13_DWMG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2919
ber01-VHDL13_DWMO_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2530
ber01-VHDL13_DWMO_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2548
ber01-VHDL13_DWMO_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 2311
ber01-VHDL13_DWMO_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1726
ber01-VHDL13_DWMO_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:36 2175
ber01-VHDL13_DWMO_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2946
ber01-VHDL13_DWMO_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:02 2759
ber01-VHDL13_DWMO_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 2786
ber01-VHDL13_DWMO_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 2661
ber01-VHDL13_DWMP_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 3338
ber01-VHDL13_DWMP_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 3356
ber01-VHDL13_DWMP_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 3151
ber01-VHDL13_DWMP_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 3265
ber01-VHDL13_DWMP_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:26 3269
ber01-VHDL13_DWMP_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 3777
ber01-VHDL13_DWMP_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:02 3570
ber01-VHDL13_DWMP_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 3338
ber01-VHDL13_DWMP_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 3045
ber01-VHDL13_DWOG_260300-2512260300-dsw--0-ia5 26-Dec-2025 04:00:02 4631
ber01-VHDL13_DWOG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:06 4507
ber01-VHDL13_DWOG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 12:23:57 5146
ber01-VHDL13_DWOG_261700-2512261700-dsw--0-ia5 26-Dec-2025 19:00:02 4530
ber01-VHDL13_DWOG_270300-2512270300-dsw--0-ia5 27-Dec-2025 04:00:01 4879
ber01-VHDL13_DWOG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:08 4755
ber01-VHDL13_DWOG_271700-2512271700-dsw--0-ia5 27-Dec-2025 19:00:02 4361
ber01-VHDL13_DWOH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:12 2664
ber01-VHDL13_DWOH_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:17 2622
ber01-VHDL13_DWOH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:16 2632
ber01-VHDL13_DWOH_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:28:12 2483
ber01-VHDL13_DWOH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:28:11 3502
ber01-VHDL13_DWOH_270400-2512270400-dsw--0-ia5 27-Dec-2025 05:58:13 3338
ber01-VHDL13_DWOH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:28:16 3512
ber01-VHDL13_DWOH_270800_COR-2512270800-dsw--0-ia5 27-Dec-2025 18:22:27 3514
ber01-VHDL13_DWOH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:17 3506
ber01-VHDL13_DWOI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:28:12 2303
ber01-VHDL13_DWOI_260400-2512260400-dsw--0-ia5 26-Dec-2025 05:58:17 2256
ber01-VHDL13_DWOI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:28:13 2290
ber01-VHDL13_DWOI_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:28:12 2105
ber01-VHDL13_DWOI_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:28:17 2687
ber01-VHDL13_DWOI_270400-2512270400-dsw--0-ia5 27-Dec-2025 05:58:17 2503
ber01-VHDL13_DWOI_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:28:12 2711
ber01-VHDL13_DWOI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:28:11 2803
ber01-VHDL13_DWON_252259-2512252259-dsw--0-ia5 25-Dec-2025 22:59:17 3561
ber01-VHDL13_DWON_252312-2512252312-dsw--0-ia5 25-Dec-2025 23:12:13 4315
ber01-VHDL13_DWON_260254-2512260254-dsw--0-ia5 26-Dec-2025 02:55:03 3792
ber01-VHDL13_DWON_260629-2512260629-dsw--0-ia5 26-Dec-2025 06:29:53 4238
ber01-VHDL13_DWON_260702-2512260702-dsw--0-ia5 26-Dec-2025 07:02:16 4274
ber01-VHDL13_DWON_261222-2512261222-dsw--0-ia5 26-Dec-2025 12:22:42 4352
ber01-VHDL13_DWON_261533-2512261533-dsw--0-ia5 26-Dec-2025 15:34:04 4127
ber01-VHDL13_DWON_261741-2512261741-dsw--0-ia5 26-Dec-2025 17:41:42 4084
ber01-VHDL13_DWON_262221-2512262221-dsw--0-ia5 26-Dec-2025 22:21:07 4029
ber01-VHDL13_DWON_270350-2512270350-dsw--0-ia5 27-Dec-2025 03:50:35 4459
ber01-VHDL13_DWON_270351-2512270351-dsw--0-ia5 27-Dec-2025 03:51:39 4459
ber01-VHDL13_DWON_270610-2512270610-dsw--0-ia5 27-Dec-2025 06:10:37 4804
ber01-VHDL13_DWON_270659-2512270659-dsw--0-ia5 27-Dec-2025 07:00:01 4804
ber01-VHDL13_DWON_270822-2512270822-dsw--0-ia5 27-Dec-2025 08:22:17 4804
ber01-VHDL13_DWON_270951-2512270951-dsw--0-ia5 27-Dec-2025 09:51:22 4804
ber01-VHDL13_DWON_271557-2512271557-dsw--0-ia5 27-Dec-2025 15:57:22 4078
ber01-VHDL13_DWON_271824-2512271824-dsw--0-ia5 27-Dec-2025 18:24:41 4103
ber01-VHDL13_DWON_272003-2512272003-dsw--0-ia5 27-Dec-2025 20:03:41 4438
ber01-VHDL13_DWON_272215-2512272215-dsw--0-ia5 27-Dec-2025 22:15:36 4455
ber01-VHDL13_DWPG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2326
ber01-VHDL13_DWPG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2197
ber01-VHDL13_DWPG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2149
ber01-VHDL13_DWPG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1695
ber01-VHDL13_DWPG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2157
ber01-VHDL13_DWPG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 2114
ber01-VHDL13_DWPG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 2043
ber01-VHDL13_DWPG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1808
ber01-VHDL13_DWPH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:02 2136
ber01-VHDL13_DWPH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:01 2177
ber01-VHDL13_DWPH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 2486
ber01-VHDL13_DWPH_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 1921
ber01-VHDL13_DWPH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:07 2723
ber01-VHDL13_DWPH_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 2436
ber01-VHDL13_DWPH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 2276
ber01-VHDL13_DWPH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 1996
ber01-VHDL13_DWSG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:30:00 2980
ber01-VHDL13_DWSG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:07 2992
ber01-VHDL13_DWSG_260400_COR-2512260400-dsw--0-ia5 26-Dec-2025 06:17:51 3248
ber01-VHDL13_DWSG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:30:01 3245
ber01-VHDL13_DWSG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:30:02 2913
ber01-VHDL13_DWSG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:30:01 2919
ber01-VHDL13_DWSG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 3076
ber01-VHDL13_DWSG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:30:03 3372
ber01-VHDL13_DWSG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:30:02 3103
ber01-VHDL17_DWOG_261200-2512261200-dsw--0-ia5 26-Dec-2025 12:33:10 3947
ber01-VHDL17_DWOG_271200-2512271200-dsw--0-ia5 27-Dec-2025 11:56:26 3524
swis2-VHDL20_DWEG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3035
swis2-VHDL20_DWEG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 3043
swis2-VHDL20_DWEG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3382
swis2-VHDL20_DWEG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:45:02 2910
swis2-VHDL20_DWEG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:45:38 3880
swis2-VHDL20_DWEG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:15:02 4015
swis2-VHDL20_DWEG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:45:06 4400
swis2-VHDL20_DWEG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 4083
swis2-VHDL20_DWEH_260200-2512260200-dsw--0-ia5 26-Dec-2025 21:33:42 3335
swis2-VHDL20_DWEH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 3935
swis2-VHDL20_DWEH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 4165
swis2-VHDL20_DWEH_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:45:02 3755
swis2-VHDL20_DWEH_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:45:38 4424
swis2-VHDL20_DWEH_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:15:02 4279
swis2-VHDL20_DWEH_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:45:06 4406
swis2-VHDL20_DWEH_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 4140
swis2-VHDL20_DWEI_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 2690
swis2-VHDL20_DWEI_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:15:06 2708
swis2-VHDL20_DWEI_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 2934
swis2-VHDL20_DWEI_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:45:02 2557
swis2-VHDL20_DWEI_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:45:38 3081
swis2-VHDL20_DWEI_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:15:02 3144
swis2-VHDL20_DWEI_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:45:06 3611
swis2-VHDL20_DWEI_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3444
swis2-VHDL20_DWHG_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3580
swis2-VHDL20_DWHG_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3585
swis2-VHDL20_DWHG_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 4164
swis2-VHDL20_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:59:31 4062
swis2-VHDL20_DWHG_261800-2512261800-dsw--0-ia5 26-Dec-2025 19:45:02 3367
swis2-VHDL20_DWHG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:02:37 3339
swis2-VHDL20_DWHG_270200-2512270200-dsw--0-ia5 27-Dec-2025 03:45:40 3668
swis2-VHDL20_DWHG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:00:06 4008
swis2-VHDL20_DWHG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:45:02 4504
swis2-VHDL20_DWHG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:06 3700
swis2-VHDL20_DWHH_260200-2512260200-dsw--0-ia5 26-Dec-2025 03:45:06 3227
swis2-VHDL20_DWHH_260400-2512260400-dsw--0-ia5 26-Dec-2025 06:00:11 3195
swis2-VHDL20_DWHH_260800-2512260800-dsw--0-ia5 26-Dec-2025 09:45:02 3532
swis2-VHDL20_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:59:53 3413
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swis2-VHDL20_DWSG_270400-2512270400-dsw--0-ia5 27-Dec-2025 06:15:02 3485
swis2-VHDL20_DWSG_270800-2512270800-dsw--0-ia5 27-Dec-2025 09:45:02 4056
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swis2-VHDL20_DWSG_271800-2512271800-dsw--0-ia5 27-Dec-2025 19:45:02 3514
wst04-VHDL20_DWEG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 217593
wst04-VHDL20_DWEG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 217041
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wst04-VHDL20_DWEG_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:16 224835
wst04-VHDL20_DWEG_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 227691
wst04-VHDL20_DWEG_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:27 227202
wst04-VHDL20_DWEG_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:22 224745
wst04-VHDL20_DWEG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 223503
wst04-VHDL20_DWEH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 217582
wst04-VHDL20_DWEH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:26 217406
wst04-VHDL20_DWEH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:22 225450
wst04-VHDL20_DWEH_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:16 224483
wst04-VHDL20_DWEH_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 224886
wst04-VHDL20_DWEH_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:21 224848
wst04-VHDL20_DWEH_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:22 222825
wst04-VHDL20_DWEH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 221302
wst04-VHDL20_DWEI_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:16 289607
wst04-VHDL20_DWEI_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:26 289502
wst04-VHDL20_DWEI_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:26 309233
wst04-VHDL20_DWEI_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:16 308532
wst04-VHDL20_DWEI_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 309233
wst04-VHDL20_DWEI_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:27 309390
wst04-VHDL20_DWEI_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:26 302475
wst04-VHDL20_DWEI_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:18 300939
wst04-VHDL20_DWHG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 306726
wst04-VHDL20_DWHG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:11 306804
wst04-VHDL20_DWHG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 311638
wst04-VHDL20_DWHG_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:16 309115
wst04-VHDL20_DWHG_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 309937
wst04-VHDL20_DWHG_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:11 310232
wst04-VHDL20_DWHG_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:16 315234
wst04-VHDL20_DWHG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:12 313036
wst04-VHDL20_DWHH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 302081
wst04-VHDL20_DWHH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:11 302162
wst04-VHDL20_DWHH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:22 305922
wst04-VHDL20_DWHH_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:22 305856
wst04-VHDL20_DWHH_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 307323
wst04-VHDL20_DWHH_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:11 307014
wst04-VHDL20_DWHH_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:16 306212
wst04-VHDL20_DWHH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:16 305857
wst04-VHDL20_DWLG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 294178
wst04-VHDL20_DWLG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 293819
wst04-VHDL20_DWLG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 295621
wst04-VHDL20_DWLG_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:26 294801
wst04-VHDL20_DWLG_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 295694
wst04-VHDL20_DWLG_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:41 295564
wst04-VHDL20_DWLG_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:32 300256
wst04-VHDL20_DWLG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:20 300060
wst04-VHDL20_DWLH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:26 297730
wst04-VHDL20_DWLH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 297884
wst04-VHDL20_DWLH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 300213
wst04-VHDL20_DWLH_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:20 298721
wst04-VHDL20_DWLH_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 299282
wst04-VHDL20_DWLH_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:41 299496
wst04-VHDL20_DWLH_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:32 303723
wst04-VHDL20_DWLH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 303651
wst04-VHDL20_DWLI_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 290051
wst04-VHDL20_DWLI_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:41 290292
wst04-VHDL20_DWLI_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 300816
wst04-VHDL20_DWLI_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:26 299906
wst04-VHDL20_DWLI_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 300735
wst04-VHDL20_DWLI_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:41 301249
wst04-VHDL20_DWLI_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:32 293124
wst04-VHDL20_DWLI_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 292279
wst04-VHDL20_DWMG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 476302
wst04-VHDL20_DWMG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 476195
wst04-VHDL20_DWMG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 486489
wst04-VHDL20_DWMG_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:16 486024
wst04-VHDL20_DWMG_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:26 486024
wst04-VHDL20_DWMG_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 486759
wst04-VHDL20_DWMG_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:21 486443
wst04-VHDL20_DWMG_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:16 490607
wst04-VHDL20_DWMG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:22 489560
wst04-VHDL20_DWMO_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:18 390898
wst04-VHDL20_DWMO_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 391384
wst04-VHDL20_DWMO_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:12 397869
wst04-VHDL20_DWMO_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:12 396067
wst04-VHDL20_DWMO_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:42 396067
wst04-VHDL20_DWMO_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 397720
wst04-VHDL20_DWMO_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:21 398114
wst04-VHDL20_DWMO_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:12 397689
wst04-VHDL20_DWMO_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:16 396091
wst04-VHDL20_DWMP_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:18 490318
wst04-VHDL20_DWMP_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:22 491523
wst04-VHDL20_DWMP_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:17 492902
wst04-VHDL20_DWMP_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:12 492496
wst04-VHDL20_DWMP_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:32 492496
wst04-VHDL20_DWMP_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:38 491836
wst04-VHDL20_DWMP_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:15:17 492884
wst04-VHDL20_DWMP_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:16 500124
wst04-VHDL20_DWMP_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:16 499361
wst04-VHDL20_DWPG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:26 303324
wst04-VHDL20_DWPG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:31 303183
wst04-VHDL20_DWPG_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:30 355557
wst04-VHDL20_DWPG_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:26 310197
wst04-VHDL20_DWPG_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 310547
wst04-VHDL20_DWPG_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:31 310582
wst04-VHDL20_DWPG_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:32 351955
wst04-VHDL20_DWPG_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:26 307578
wst04-VHDL20_DWPH_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:22 226467
wst04-VHDL20_DWPH_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:00:31 225685
wst04-VHDL20_DWPH_260800-2512260800-omedes--0.pdf 26-Dec-2025 09:45:26 268530
wst04-VHDL20_DWPH_261800-2512261800-omedes--0.pdf 26-Dec-2025 19:45:20 267673
wst04-VHDL20_DWPH_270200-2512270200-omedes--0.pdf 27-Dec-2025 03:45:40 224610
wst04-VHDL20_DWPH_270400-2512270400-omedes--0.pdf 27-Dec-2025 06:00:31 224112
wst04-VHDL20_DWPH_270800-2512270800-omedes--0.pdf 27-Dec-2025 09:45:26 268830
wst04-VHDL20_DWPH_271800-2512271800-omedes--0.pdf 27-Dec-2025 19:45:20 268655
wst04-VHDL20_DWSG_260200-2512260200-omedes--0.pdf 26-Dec-2025 03:45:12 302504
wst04-VHDL20_DWSG_260400-2512260400-omedes--0.pdf 26-Dec-2025 06:15:16 303072
wst04-VHDL20_DWSG_260400_COR-2512260400-omedes-..> 26-Dec-2025 06:18:01 303883
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