Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Jan-2026 13:47:54 7753
FPDL13_DWMZ_160600 16-Jan-2026 14:03:34 8327
SXDL31_DWAV_150800 15-Jan-2026 09:00:51 12772
SXDL31_DWAV_151800 15-Jan-2026 16:42:54 11067
SXDL31_DWAV_160800 16-Jan-2026 08:40:53 12076
SXDL31_DWAV_161800 16-Jan-2026 15:01:26 7333
SXDL31_DWAV_LATEST 16-Jan-2026 15:01:26 7333
SXDL33_DWAV_150000 15-Jan-2026 09:27:35 7611
SXDL33_DWAV_160000 16-Jan-2026 09:46:19 5877
SXDL33_DWAV_LATEST 16-Jan-2026 09:46:19 5877
ber01-FWDL39_DWMS_151230-2601151230-dsw--0-ia5 15-Jan-2026 12:30:08 1540
ber01-FWDL39_DWMS_161230-2601161230-dsw--0-ia5 16-Jan-2026 13:02:07 944
ber01-VHDL13_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 2305
ber01-VHDL13_DWEH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:14 2429
ber01-VHDL13_DWEH_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:11 2474
ber01-VHDL13_DWEH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:13 2685
ber01-VHDL13_DWEH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:17 2812
ber01-VHDL13_DWEH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:28:12 3068
ber01-VHDL13_DWEH_160400-2601160400-dsw--0-ia5 16-Jan-2026 05:58:16 3204
ber01-VHDL13_DWEH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:28:16 3614
ber01-VHDL13_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 3017
ber01-VHDL13_DWHG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 3132
ber01-VHDL13_DWHG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 3043
ber01-VHDL13_DWHG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 3362
ber01-VHDL13_DWHG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:08 3131
ber01-VHDL13_DWHG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:07 3695
ber01-VHDL13_DWHG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:08 3906
ber01-VHDL13_DWHG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 3915
ber01-VHDL13_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:06 2563
ber01-VHDL13_DWHH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2544
ber01-VHDL13_DWHH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2476
ber01-VHDL13_DWHH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 2606
ber01-VHDL13_DWHH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:08 2506
ber01-VHDL13_DWHH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:07 3067
ber01-VHDL13_DWHH_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:08 3414
ber01-VHDL13_DWHH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 3371
ber01-VHDL13_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2581
ber01-VHDL13_DWLG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2988
ber01-VHDL13_DWLG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2988
ber01-VHDL13_DWLG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2941
ber01-VHDL13_DWLG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2780
ber01-VHDL13_DWLG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2902
ber01-VHDL13_DWLG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 3050
ber01-VHDL13_DWLG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 3224
ber01-VHDL13_DWLH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2843
ber01-VHDL13_DWLH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2872
ber01-VHDL13_DWLH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2906
ber01-VHDL13_DWLH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2508
ber01-VHDL13_DWLH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2331
ber01-VHDL13_DWLH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2441
ber01-VHDL13_DWLH_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 2330
ber01-VHDL13_DWLH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 2423
ber01-VHDL13_DWLI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2393
ber01-VHDL13_DWLI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2544
ber01-VHDL13_DWLI_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2506
ber01-VHDL13_DWLI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2490
ber01-VHDL13_DWLI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2271
ber01-VHDL13_DWLI_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2127
ber01-VHDL13_DWLI_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 2012
ber01-VHDL13_DWLI_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 2084
ber01-VHDL13_DWMG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 3175
ber01-VHDL13_DWMG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3527
ber01-VHDL13_DWMG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3529
ber01-VHDL13_DWMG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3470
ber01-VHDL13_DWMG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2994
ber01-VHDL13_DWMG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 3378
ber01-VHDL13_DWMG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 3384
ber01-VHDL13_DWMG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:01 2682
ber01-VHDL13_DWMO_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2966
ber01-VHDL13_DWMO_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3205
ber01-VHDL13_DWMO_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3223
ber01-VHDL13_DWMO_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3270
ber01-VHDL13_DWMO_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2943
ber01-VHDL13_DWMO_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 3291
ber01-VHDL13_DWMO_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 3306
ber01-VHDL13_DWMO_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:01 2691
ber01-VHDL13_DWMP_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2945
ber01-VHDL13_DWMP_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3403
ber01-VHDL13_DWMP_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:01 3458
ber01-VHDL13_DWMP_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 3260
ber01-VHDL13_DWMP_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 3141
ber01-VHDL13_DWMP_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 3619
ber01-VHDL13_DWMP_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 3623
ber01-VHDL13_DWMP_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:01 3049
ber01-VHDL13_DWOG_141700-2601141700-dsw--0-ia5 14-Jan-2026 19:00:04 3307
ber01-VHDL13_DWOG_150300-2601150300-dsw--0-ia5 15-Jan-2026 04:00:10 4062
ber01-VHDL13_DWOG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 4317
ber01-VHDL13_DWOG_151700-2601151700-dsw--0-ia5 15-Jan-2026 19:00:06 3933
ber01-VHDL13_DWOG_160300-2601160300-dsw--0-ia5 16-Jan-2026 04:00:08 4486
ber01-VHDL13_DWOG_160300_COR-2601160300-dsw--0-ia5 16-Jan-2026 04:18:47 4495
ber01-VHDL13_DWOG_160800-2601160800-dsw--0-ia5 16-Jan-2026 15:44:56 4337
ber01-VHDL13_DWOH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:16 1954
ber01-VHDL13_DWOH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:14 2229
ber01-VHDL13_DWOH_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:11 2169
ber01-VHDL13_DWOH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:17 2527
ber01-VHDL13_DWOH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:11 2845
ber01-VHDL13_DWOH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:28:12 3117
ber01-VHDL13_DWOH_160400-2601160400-dsw--0-ia5 16-Jan-2026 05:58:11 3078
ber01-VHDL13_DWOH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:28:12 2955
ber01-VHDL13_DWOI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:28:12 1989
ber01-VHDL13_DWOI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:28:16 2146
ber01-VHDL13_DWOI_150400-2601150400-dsw--0-ia5 15-Jan-2026 05:58:16 2164
ber01-VHDL13_DWOI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:28:13 2167
ber01-VHDL13_DWOI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:28:11 2305
ber01-VHDL13_DWOI_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:28:16 2722
ber01-VHDL13_DWOI_160400-2601160400-dsw--0-ia5 16-Jan-2026 05:58:11 2778
ber01-VHDL13_DWOI_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:28:12 3138
ber01-VHDL13_DWON_141947-2601141947-dsw--0-ia5 14-Jan-2026 19:47:51 3209
ber01-VHDL13_DWON_142000-2601142000-dsw--0-ia5 14-Jan-2026 20:00:36 3209
ber01-VHDL13_DWON_150013-2601150013-dsw--0-ia5 15-Jan-2026 00:13:32 3258
ber01-VHDL13_DWON_150353-2601150353-dsw--0-ia5 15-Jan-2026 03:53:57 3258
ber01-VHDL13_DWON_150621-2601150621-dsw--0-ia5 15-Jan-2026 06:21:17 3664
ber01-VHDL13_DWON_150751-2601150751-dsw--0-ia5 15-Jan-2026 07:51:07 4193
ber01-VHDL13_DWON_150957-2601150957-dsw--0-ia5 15-Jan-2026 09:57:11 4178
ber01-VHDL13_DWON_151245-2601151245-dsw--0-ia5 15-Jan-2026 12:45:43 4181
ber01-VHDL13_DWON_151548-2601151548-dsw--0-ia5 15-Jan-2026 15:48:07 3597
ber01-VHDL13_DWON_151734-2601151734-dsw--0-ia5 15-Jan-2026 17:34:22 3542
ber01-VHDL13_DWON_160151-2601160151-dsw--0-ia5 16-Jan-2026 01:51:11 4198
ber01-VHDL13_DWON_160337-2601160337-dsw--0-ia5 16-Jan-2026 03:38:02 4198
ber01-VHDL13_DWON_160418-2601160418-dsw--0-ia5 16-Jan-2026 04:18:17 4198
ber01-VHDL13_DWON_160630-2601160630-dsw--0-ia5 16-Jan-2026 06:30:51 3710
ber01-VHDL13_DWON_160728-2601160728-dsw--0-ia5 16-Jan-2026 07:28:15 4177
ber01-VHDL13_DWON_160946-2601160946-dsw--0-ia5 16-Jan-2026 09:46:31 4177
ber01-VHDL13_DWON_161422-2601161422-dsw--0-ia5 16-Jan-2026 14:23:01 4286
ber01-VHDL13_DWON_161544-2601161544-dsw--0-ia5 16-Jan-2026 15:44:26 3414
ber01-VHDL13_DWON_161819-2601161819-dsw--0-ia5 16-Jan-2026 18:19:52 3531
ber01-VHDL13_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2116
ber01-VHDL13_DWPG_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:11 2339
ber01-VHDL13_DWPG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2529
ber01-VHDL13_DWPG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2620
ber01-VHDL13_DWPG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2237
ber01-VHDL13_DWPG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 1959
ber01-VHDL13_DWPG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2005
ber01-VHDL13_DWPG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 2136
ber01-VHDL13_DWPG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 2172
ber01-VHDL13_DWPH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2054
ber01-VHDL13_DWPH_141800_COR-2601141800-dsw--0-ia5 14-Jan-2026 20:14:27 2194
ber01-VHDL13_DWPH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:08 2348
ber01-VHDL13_DWPH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2434
ber01-VHDL13_DWPH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:01 2251
ber01-VHDL13_DWPH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2029
ber01-VHDL13_DWPH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2017
ber01-VHDL13_DWPH_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:01 2098
ber01-VHDL13_DWPH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 2196
ber01-VHDL13_DWSG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:30:03 2586
ber01-VHDL13_DWSG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:30:02 3252
ber01-VHDL13_DWSG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2947
ber01-VHDL13_DWSG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:30:07 2673
ber01-VHDL13_DWSG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:30:02 2283
ber01-VHDL13_DWSG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:30:01 2576
ber01-VHDL13_DWSG_160200_COR-2601160200-dsw--0-ia5 16-Jan-2026 03:35:27 2577
ber01-VHDL13_DWSG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:07 2586
ber01-VHDL13_DWSG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:30:12 2785
ber01-VHDL17_DWOG_151200-2601151200-dsw--0-ia5 15-Jan-2026 11:48:57 2200
ber01-VHDL17_DWOG_161200-2601161200-dsw--0-ia5 16-Jan-2026 12:06:03 2356
swis2-VHDL20_DWEG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2284
swis2-VHDL20_DWEG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2509
swis2-VHDL20_DWEG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2493
swis2-VHDL20_DWEG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3104
swis2-VHDL20_DWEG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3175
swis2-VHDL20_DWEG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3397
swis2-VHDL20_DWEG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:15:06 3496
swis2-VHDL20_DWEG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:03 3607
swis2-VHDL20_DWEH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2666
swis2-VHDL20_DWEH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2754
swis2-VHDL20_DWEH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2810
swis2-VHDL20_DWEH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3331
swis2-VHDL20_DWEH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3170
swis2-VHDL20_DWEH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3393
swis2-VHDL20_DWEH_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:15:06 3678
swis2-VHDL20_DWEH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:03 4345
swis2-VHDL20_DWEI_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2344
swis2-VHDL20_DWEI_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2439
swis2-VHDL20_DWEI_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:07 2519
swis2-VHDL20_DWEI_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 2801
swis2-VHDL20_DWEI_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 2660
swis2-VHDL20_DWEI_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3018
swis2-VHDL20_DWEI_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:15:06 3237
swis2-VHDL20_DWEI_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:03 3857
swis2-VHDL20_DWHG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 3200
swis2-VHDL20_DWHG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 3318
swis2-VHDL20_DWHG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 3226
swis2-VHDL20_DWHG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:19 4039
swis2-VHDL20_DWHG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 3314
swis2-VHDL20_DWHG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3881
swis2-VHDL20_DWHG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:07 4089
swis2-VHDL20_DWHG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:07 4624
swis2-VHDL20_DWHH_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:06 2749
swis2-VHDL20_DWHH_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 2730
swis2-VHDL20_DWHH_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:07 2662
swis2-VHDL20_DWHH_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3231
swis2-VHDL20_DWHH_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:06 2692
swis2-VHDL20_DWHH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3253
swis2-VHDL20_DWHH_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:00:08 3600
swis2-VHDL20_DWHH_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:07 3996
swis2-VHDL20_DWLG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 3056
swis2-VHDL20_DWLG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:06 3466
swis2-VHDL20_DWLG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:00:11 3389
swis2-VHDL20_DWLG_150800-2601150800-dsw--0-ia5 15-Jan-2026 09:45:18 3502
swis2-VHDL20_DWLG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 3178
swis2-VHDL20_DWLG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 3303
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swis2-VHDL20_DWPG_141800-2601141800-dsw--0-ia5 14-Jan-2026 19:45:02 2695
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swis2-VHDL20_DWPH_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 2455
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swis2-VHDL20_DWSG_150200-2601150200-dsw--0-ia5 15-Jan-2026 03:45:01 3765
swis2-VHDL20_DWSG_150400-2601150400-dsw--0-ia5 15-Jan-2026 06:15:03 3397
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swis2-VHDL20_DWSG_151800-2601151800-dsw--0-ia5 15-Jan-2026 19:45:03 2694
swis2-VHDL20_DWSG_160200-2601160200-dsw--0-ia5 16-Jan-2026 03:45:02 2972
swis2-VHDL20_DWSG_160400-2601160400-dsw--0-ia5 16-Jan-2026 06:15:02 2998
swis2-VHDL20_DWSG_160800-2601160800-dsw--0-ia5 16-Jan-2026 09:45:07 3448
swis2-VHDL20_DWSG_161300-2601161300-dsw--0-ia5 16-Jan-2026 14:45:03 3278
wst04-VHDL20_DWEG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 226572
wst04-VHDL20_DWEG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 227348
wst04-VHDL20_DWEG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 226584
wst04-VHDL20_DWEG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 224658
wst04-VHDL20_DWEG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 226122
wst04-VHDL20_DWEG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:12 227873
wst04-VHDL20_DWEG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:21 227263
wst04-VHDL20_DWEG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:21 227472
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wst04-VHDL20_DWEH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 229759
wst04-VHDL20_DWEH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 229805
wst04-VHDL20_DWEH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 224229
wst04-VHDL20_DWEH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 226944
wst04-VHDL20_DWEH_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:12 228133
wst04-VHDL20_DWEH_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:21 227559
wst04-VHDL20_DWEH_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:21 225868
wst04-VHDL20_DWEI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 321181
wst04-VHDL20_DWEI_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 321324
wst04-VHDL20_DWEI_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:27 321190
wst04-VHDL20_DWEI_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 225492
wst04-VHDL20_DWEI_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 317007
wst04-VHDL20_DWEI_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:18 318164
wst04-VHDL20_DWEI_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:27 318005
wst04-VHDL20_DWEI_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:25 318045
wst04-VHDL20_DWHG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 316370
wst04-VHDL20_DWHG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 316813
wst04-VHDL20_DWHG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:11 316711
wst04-VHDL20_DWHG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 308706
wst04-VHDL20_DWHG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 305193
wst04-VHDL20_DWHG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:12 305951
wst04-VHDL20_DWHG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:12 306043
wst04-VHDL20_DWHG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:15 306541
wst04-VHDL20_DWHH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 301223
wst04-VHDL20_DWHH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 301402
wst04-VHDL20_DWHH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:11 301141
wst04-VHDL20_DWHH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 307816
wst04-VHDL20_DWHH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 291192
wst04-VHDL20_DWHH_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:18 291924
wst04-VHDL20_DWHH_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:12 292367
wst04-VHDL20_DWHH_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:15 292975
wst04-VHDL20_DWLG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 300079
wst04-VHDL20_DWLG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 300434
wst04-VHDL20_DWLG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 299820
wst04-VHDL20_DWLG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 298912
wst04-VHDL20_DWLG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 296856
wst04-VHDL20_DWLG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:26 297700
wst04-VHDL20_DWLG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:41 297406
wst04-VHDL20_DWLG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:31 301847
wst04-VHDL20_DWLH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 320411
wst04-VHDL20_DWLH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:26 321317
wst04-VHDL20_DWLH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 320741
wst04-VHDL20_DWLH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 297823
wst04-VHDL20_DWLH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 301383
wst04-VHDL20_DWLH_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:20 302046
wst04-VHDL20_DWLH_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:41 301583
wst04-VHDL20_DWLH_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:25 302231
wst04-VHDL20_DWLI_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 310272
wst04-VHDL20_DWLI_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 311048
wst04-VHDL20_DWLI_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:42 310511
wst04-VHDL20_DWLI_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 298041
wst04-VHDL20_DWLI_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 306582
wst04-VHDL20_DWLI_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:20 307078
wst04-VHDL20_DWLI_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:41 306915
wst04-VHDL20_DWLI_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:31 308985
wst04-VHDL20_DWMG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 518542
wst04-VHDL20_DWMG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 519093
wst04-VHDL20_DWMG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 518869
wst04-VHDL20_DWMG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:19 395613
wst04-VHDL20_DWMG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 523747
wst04-VHDL20_DWMG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:18 525230
wst04-VHDL20_DWMG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:17 524882
wst04-VHDL20_DWMG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:17 524608
wst04-VHDL20_DWMO_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:16 419975
wst04-VHDL20_DWMO_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 420201
wst04-VHDL20_DWMO_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:17 420624
wst04-VHDL20_DWMO_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 313398
wst04-VHDL20_DWMO_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:16 418581
wst04-VHDL20_DWMO_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:18 419163
wst04-VHDL20_DWMO_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:17 419394
wst04-VHDL20_DWMO_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:11 417532
wst04-VHDL20_DWMP_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:22 542122
wst04-VHDL20_DWMP_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:17 541524
wst04-VHDL20_DWMP_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:21 542580
wst04-VHDL20_DWMP_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 395214
wst04-VHDL20_DWMP_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 553238
wst04-VHDL20_DWMP_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:22 552962
wst04-VHDL20_DWMP_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:17 553926
wst04-VHDL20_DWMP_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:17 546758
wst04-VHDL20_DWPG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:26 317641
wst04-VHDL20_DWPG_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:14:47 317768
wst04-VHDL20_DWPG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:26 318244
wst04-VHDL20_DWPG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:31 317346
wst04-VHDL20_DWPG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 350658
wst04-VHDL20_DWPG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:26 296687
wst04-VHDL20_DWPG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:26 297024
wst04-VHDL20_DWPG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:32 297371
wst04-VHDL20_DWPG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:31 346133
wst04-VHDL20_DWPH_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:20 269755
wst04-VHDL20_DWPH_141800_COR-2601141800-omedes-..> 14-Jan-2026 20:15:01 269520
wst04-VHDL20_DWPH_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:21 225443
wst04-VHDL20_DWPH_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:00:31 224465
wst04-VHDL20_DWPH_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:32 267420
wst04-VHDL20_DWPH_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:22 268262
wst04-VHDL20_DWPH_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:20 224279
wst04-VHDL20_DWPH_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:00:32 224511
wst04-VHDL20_DWPH_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:25 267298
wst04-VHDL20_DWSG_141800-2601141800-omedes--0.pdf 14-Jan-2026 19:45:12 330822
wst04-VHDL20_DWSG_150200-2601150200-omedes--0.pdf 15-Jan-2026 03:45:14 331677
wst04-VHDL20_DWSG_150400-2601150400-omedes--0.pdf 15-Jan-2026 06:15:17 331470
wst04-VHDL20_DWSG_150800-2601150800-omedes--0.pdf 15-Jan-2026 09:45:18 309057
wst04-VHDL20_DWSG_151300-2601151300-omedes--0.pdf 15-Jan-2026 14:45:16 307894
wst04-VHDL20_DWSG_151800-2601151800-omedes--0.pdf 15-Jan-2026 19:45:12 331221
wst04-VHDL20_DWSG_160200-2601160200-omedes--0.pdf 16-Jan-2026 03:45:12 332672
wst04-VHDL20_DWSG_160400-2601160400-omedes--0.pdf 16-Jan-2026 06:15:11 332798
wst04-VHDL20_DWSG_160800-2601160800-omedes--0.pdf 16-Jan-2026 09:45:11 335806
wst04-VHDL20_DWSG_161300-2601161300-omedes--0.pdf 16-Jan-2026 14:45:11 335757