Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jul-2026 12:58:04 3910
FPDL13_DWMZ_200600 20-Jul-2026 13:54:54 4470
SXDL31_DWAV_190800 19-Jul-2026 07:17:08 7622
SXDL31_DWAV_191800 19-Jul-2026 15:32:54 7312
SXDL31_DWAV_200800 20-Jul-2026 06:55:29 7288
SXDL31_DWAV_201800 20-Jul-2026 15:05:58 3853
SXDL31_DWAV_LATEST 20-Jul-2026 15:05:58 3853
SXDL33_DWAV_190000 19-Jul-2026 10:07:24 8080
SXDL33_DWAV_200000 20-Jul-2026 10:47:19 5204
SXDL33_DWAV_LATEST 20-Jul-2026 10:47:19 5204
ber01-FWDL39_DWMS_191200-2607191200-dsw--0-ia5 19-Jul-2026 10:17:32 1279
ber01-FWDL39_DWMS_201200-2607201200-dsw--0-ia5 20-Jul-2026 11:13:26 1471
ber01-VHDL13_DWEG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:17 3050
ber01-VHDL13_DWEG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:11 2773
ber01-VHDL13_DWEH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:17 3008
ber01-VHDL13_DWEH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:17 2649
ber01-VHDL13_DWEI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:28:12 2202
ber01-VHDL13_DWEI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:28:17 2533
ber01-VHDL13_DWHG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3637
ber01-VHDL13_DWHG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 3769
ber01-VHDL13_DWHH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3362
ber01-VHDL13_DWHH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 3630
ber01-VHDL13_DWLG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2582
ber01-VHDL13_DWLG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2266
ber01-VHDL13_DWLH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2823
ber01-VHDL13_DWLH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2498
ber01-VHDL13_DWLI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2284
ber01-VHDL13_DWLI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2151
ber01-VHDL13_DWMO_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2466
ber01-VHDL13_DWMO_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2863
ber01-VHDL13_DWMP_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2963
ber01-VHDL13_DWMP_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2814
ber01-VHDL13_DWOG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 4312
ber01-VHDL13_DWOG_191700-2607191700-dsw--0-ia5 19-Jul-2026 18:00:02 3981
ber01-VHDL13_DWOG_191700_COR-2607191700-dsw--0-ia5 19-Jul-2026 17:43:36 3985
ber01-VHDL13_DWOG_200300-2607200300-dsw--0-ia5 20-Jul-2026 03:00:01 4402
ber01-VHDL13_DWOG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:09 4173
ber01-VHDL13_DWOG_201700-2607201700-dsw--0-ia5 20-Jul-2026 18:00:02 3545
ber01-VHDL13_DWOG_210300-2607210300-dsw--0-ia5 21-Jul-2026 03:00:07 3431
ber01-VHDL13_DWON_190529-2607190529-dsw--0-ia5 19-Jul-2026 05:29:22 3913
ber01-VHDL13_DWON_190616-2607190616-dsw--0-ia5 19-Jul-2026 06:16:57 3932
ber01-VHDL13_DWON_190642-2607190642-dsw--0-ia5 19-Jul-2026 06:42:19 3854
ber01-VHDL13_DWON_190756-2607190756-dsw--0-ia5 19-Jul-2026 07:56:47 3867
ber01-VHDL13_DWON_191052-2607191052-dsw--0-ia5 19-Jul-2026 10:52:37 3742
ber01-VHDL13_DWON_191322-2607191322-dsw--0-ia5 19-Jul-2026 13:22:06 3715
ber01-VHDL13_DWON_191458-2607191458-dsw--0-ia5 19-Jul-2026 14:58:27 3727
ber01-VHDL13_DWON_191502-2607191502-dsw--0-ia5 19-Jul-2026 15:02:54 3712
ber01-VHDL13_DWON_191742-2607191742-dsw--0-ia5 19-Jul-2026 17:43:05 3711
ber01-VHDL13_DWON_191848-2607191848-dsw--0-ia5 19-Jul-2026 18:48:38 3819
ber01-VHDL13_DWON_192130-2607192130-dsw--0-ia5 19-Jul-2026 21:30:24 3827
ber01-VHDL13_DWON_192336-2607192336-dsw--0-ia5 19-Jul-2026 23:36:22 4284
ber01-VHDL13_DWON_200002-2607200002-dsw--0-ia5 20-Jul-2026 00:02:27 4284
ber01-VHDL13_DWON_200149-2607200149-dsw--0-ia5 20-Jul-2026 01:49:13 4344
ber01-VHDL13_DWON_200255-2607200255-dsw--0-ia5 20-Jul-2026 02:55:57 4341
ber01-VHDL13_DWON_200312-2607200312-dsw--0-ia5 20-Jul-2026 03:12:47 4341
ber01-VHDL13_DWON_200528-2607200528-dsw--0-ia5 20-Jul-2026 05:28:52 4071
ber01-VHDL13_DWON_200607-2607200607-dsw--0-ia5 20-Jul-2026 06:07:16 4071
ber01-VHDL13_DWON_200807-2607200807-dsw--0-ia5 20-Jul-2026 08:07:57 4071
ber01-VHDL13_DWON_201044-2607201044-dsw--0-ia5 20-Jul-2026 10:45:04 4071
ber01-VHDL13_DWON_201441-2607201441-dsw--0-ia5 20-Jul-2026 14:41:24 3495
ber01-VHDL13_DWON_201745-2607201745-dsw--0-ia5 20-Jul-2026 17:45:37 3522
ber01-VHDL13_DWON_201804-2607201804-dsw--0-ia5 20-Jul-2026 18:05:02 3522
ber01-VHDL13_DWON_201847-2607201847-dsw--0-ia5 20-Jul-2026 18:47:56 3421
ber01-VHDL13_DWON_201849-2607201849-dsw--0-ia5 20-Jul-2026 18:50:02 3421
ber01-VHDL13_DWON_202059-2607202059-dsw--0-ia5 20-Jul-2026 20:59:38 3388
ber01-VHDL13_DWON_202109-2607202109-dsw--0-ia5 20-Jul-2026 21:09:41 3388
ber01-VHDL13_DWON_210003-2607210003-dsw--0-ia5 21-Jul-2026 00:03:11 3913
ber01-VHDL13_DWON_210140-2607210140-dsw--0-ia5 21-Jul-2026 01:40:39 3879
ber01-VHDL13_DWON_210243-2607210243-dsw--0-ia5 21-Jul-2026 02:44:09 3879
ber01-VHDL13_DWPG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2791
ber01-VHDL13_DWPG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2359
ber01-VHDL13_DWPH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 3515
ber01-VHDL13_DWPH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 3196
ber01-VHDL13_DWSG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 2594
ber01-VHDL13_DWSG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 2202
ber01-VHDL17_DWOG_191200-2607191200-dsw--0-ia5 19-Jul-2026 11:03:16 2932
ber01-VHDL17_DWOG_201200-2607201200-dsw--0-ia5 20-Jul-2026 12:10:52 3384
swis2-VHDL20_DWEG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:17 1102
swis2-VHDL20_DWEG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1191
swis2-VHDL20_DWEG_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:03 983
swis2-VHDL20_DWEG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 807
swis2-VHDL20_DWEG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 723
swis2-VHDL20_DWEG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1024
swis2-VHDL20_DWEG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1059
swis2-VHDL20_DWEG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:01 967
swis2-VHDL20_DWEH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:21 1207
swis2-VHDL20_DWEH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1333
swis2-VHDL20_DWEH_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:03 1006
swis2-VHDL20_DWEH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 821
swis2-VHDL20_DWEH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 738
swis2-VHDL20_DWEH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1033
swis2-VHDL20_DWEH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1062
swis2-VHDL20_DWEH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:02 975
swis2-VHDL20_DWEI_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:01:21 739
swis2-VHDL20_DWEI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 828
swis2-VHDL20_DWEI_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:03 1002
swis2-VHDL20_DWEI_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 829
swis2-VHDL20_DWEI_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:01:22 745
swis2-VHDL20_DWEI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 945
swis2-VHDL20_DWEI_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 865
swis2-VHDL20_DWEI_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:01 958
swis2-VHDL20_DWHG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1886
swis2-VHDL20_DWHG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:45:18 1740
swis2-VHDL20_DWHG_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:45:09 2436
swis2-VHDL20_DWHG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:45:16 1778
swis2-VHDL20_DWHG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:16 1775
swis2-VHDL20_DWHG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:45:24 2068
swis2-VHDL20_DWHG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:45:10 1546
swis2-VHDL20_DWHG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:46:07 1684
swis2-VHDL20_DWHH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1746
swis2-VHDL20_DWHH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:45:18 1635
swis2-VHDL20_DWHH_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:45:09 2974
swis2-VHDL20_DWHH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:45:16 1770
swis2-VHDL20_DWHH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:16 1770
swis2-VHDL20_DWHH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:45:24 2386
swis2-VHDL20_DWHH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:45:10 2080
swis2-VHDL20_DWHH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:46:07 2092
swis2-VHDL20_DWLG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 942
swis2-VHDL20_DWLG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1060
swis2-VHDL20_DWLG_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:31:05 938
swis2-VHDL20_DWLG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 850
swis2-VHDL20_DWLG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 849
swis2-VHDL20_DWLG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 954
swis2-VHDL20_DWLG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1005
swis2-VHDL20_DWLG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 858
swis2-VHDL20_DWLH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1246
swis2-VHDL20_DWLH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1362
swis2-VHDL20_DWLH_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:31:05 1154
swis2-VHDL20_DWLH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1100
swis2-VHDL20_DWLH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1017
swis2-VHDL20_DWLH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1181
swis2-VHDL20_DWLH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1274
swis2-VHDL20_DWLH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1277
swis2-VHDL20_DWLI_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 928
swis2-VHDL20_DWLI_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1046
swis2-VHDL20_DWLI_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:31:05 929
swis2-VHDL20_DWLI_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 843
swis2-VHDL20_DWLI_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 849
swis2-VHDL20_DWLI_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 954
swis2-VHDL20_DWLI_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 960
swis2-VHDL20_DWLI_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 857
swis2-VHDL20_DWMO_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:03 1010
swis2-VHDL20_DWMO_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 884
swis2-VHDL20_DWMO_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:07 1110
swis2-VHDL20_DWMO_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:01 751
swis2-VHDL20_DWMO_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:02 811
swis2-VHDL20_DWMO_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1010
swis2-VHDL20_DWMO_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1073
swis2-VHDL20_DWMO_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:02 863
swis2-VHDL20_DWMP_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:03 1256
swis2-VHDL20_DWMP_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1384
swis2-VHDL20_DWMP_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:07 1198
swis2-VHDL20_DWMP_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:01 750
swis2-VHDL20_DWMP_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:02 809
swis2-VHDL20_DWMP_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 1075
swis2-VHDL20_DWMP_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:04 1169
swis2-VHDL20_DWMP_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:11 862
swis2-VHDL20_DWPG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1236
swis2-VHDL20_DWPG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1324
swis2-VHDL20_DWPG_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:31:05 1075
swis2-VHDL20_DWPG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1108
swis2-VHDL20_DWPG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1102
swis2-VHDL20_DWPG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1078
swis2-VHDL20_DWPG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1019
swis2-VHDL20_DWPG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1025
swis2-VHDL20_DWPH_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1719
swis2-VHDL20_DWPH_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:23 1908
swis2-VHDL20_DWPH_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:31:05 1483
swis2-VHDL20_DWPH_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:23 1395
swis2-VHDL20_DWPH_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:10 1427
swis2-VHDL20_DWPH_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:21 1711
swis2-VHDL20_DWPH_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:31:09 1217
swis2-VHDL20_DWPH_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:29 1297
swis2-VHDL20_DWSG_190400-2607190400-dsw--0-ia5 19-Jul-2026 05:00:17 1043
swis2-VHDL20_DWSG_190800-2607190800-dsw--0-ia5 19-Jul-2026 08:30:12 1096
swis2-VHDL20_DWSG_191800-2607191800-dsw--0-ia5 19-Jul-2026 18:30:03 945
swis2-VHDL20_DWSG_200200-2607200200-dsw--0-ia5 20-Jul-2026 02:30:07 713
swis2-VHDL20_DWSG_200400-2607200400-dsw--0-ia5 20-Jul-2026 05:00:18 782
swis2-VHDL20_DWSG_200800-2607200800-dsw--0-ia5 20-Jul-2026 08:30:03 853
swis2-VHDL20_DWSG_201800-2607201800-dsw--0-ia5 20-Jul-2026 18:30:13 862
swis2-VHDL20_DWSG_210200-2607210200-dsw--0-ia5 21-Jul-2026 02:30:11 814
wst04-VHDL20_DWEG_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 240478
wst04-VHDL20_DWEG_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:12 241196
wst04-VHDL20_DWEG_191800-2607191800-omedes--0.pdf 19-Jul-2026 18:30:20 238164
wst04-VHDL20_DWEG_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:30:12 236853
wst04-VHDL20_DWEG_200400-2607200400-omedes--0.pdf 20-Jul-2026 05:00:12 235635
wst04-VHDL20_DWEG_200800-2607200800-omedes--0.pdf 20-Jul-2026 08:30:15 236802
wst04-VHDL20_DWEG_201800-2607201800-omedes--0.pdf 20-Jul-2026 18:30:13 234546
wst04-VHDL20_DWEG_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:13 234436
wst04-VHDL20_DWEH_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 236917
wst04-VHDL20_DWEH_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:12 237678
wst04-VHDL20_DWEH_191800-2607191800-omedes--0.pdf 19-Jul-2026 18:30:12 235519
wst04-VHDL20_DWEH_200200-2607200200-omedes--0.pdf 20-Jul-2026 02:30:12 234568
wst04-VHDL20_DWEH_200400-2607200400-omedes--0.pdf 20-Jul-2026 05:00:12 233660
wst04-VHDL20_DWEH_200800-2607200800-omedes--0.pdf 20-Jul-2026 08:30:15 234789
wst04-VHDL20_DWEH_201800-2607201800-omedes--0.pdf 20-Jul-2026 18:30:13 232880
wst04-VHDL20_DWEH_210200-2607210200-omedes--0.pdf 21-Jul-2026 02:30:13 233089
wst04-VHDL20_DWEI_190400-2607190400-omedes--0.pdf 19-Jul-2026 05:00:11 340560
wst04-VHDL20_DWEI_190800-2607190800-omedes--0.pdf 19-Jul-2026 08:30:20 340786
wst04-VHDL20_DWEI_191800-2607191800-omedes--0.pdf 19-Jul-2026 18:30:20 342012
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