Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Oct-2026 13:38:13 3789
SXDL31_DWAV_111800 11-Oct-2026 16:18:45 5288
SXDL31_DWAV_120800 12-Oct-2026 07:44:35 9252
SXDL31_DWAV_121800 12-Oct-2026 16:47:52 5801
SXDL31_DWAV_130800 13-Oct-2026 07:24:55 8104
SXDL31_DWAV_LATEST 13-Oct-2026 07:24:55 8104
SXDL33_DWAV_120000 12-Oct-2026 09:45:06 13816
SXDL33_DWAV_130000 13-Oct-2026 10:27:10 12123
SXDL33_DWAV_LATEST 13-Oct-2026 10:27:10 12123
ber01-FWDL39_DWMS_121200-2610121200-dsw--0-ia5 12-Oct-2026 10:33:46 1169
ber01-FWDL39_DWMS_131200-2610131200-dsw--0-ia5 13-Oct-2026 10:26:57 1306
ber01-VHDL13_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:24 2613
ber01-VHDL13_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2429
ber01-VHDL13_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2639
ber01-VHDL13_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 2677
ber01-VHDL13_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:28:18 2545
ber01-VHDL13_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:22 2455
ber01-VHDL13_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3666
ber01-VHDL13_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3831
ber01-VHDL13_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3539
ber01-VHDL13_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3616
ber01-VHDL13_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2906
ber01-VHDL13_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2604
ber01-VHDL13_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2996
ber01-VHDL13_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2878
ber01-VHDL13_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2696
ber01-VHDL13_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2649
ber01-VHDL13_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 2807
ber01-VHDL13_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3145
ber01-VHDL13_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2726
ber01-VHDL13_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 3082
ber01-VHDL13_DWOG_111700-2610111700-dsw--0-ia5 11-Oct-2026 18:00:04 3151
ber01-VHDL13_DWOG_120300-2610120300-dsw--0-ia5 12-Oct-2026 03:01:56 3574
ber01-VHDL13_DWOG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 3714
ber01-VHDL13_DWOG_121700-2610121700-dsw--0-ia5 12-Oct-2026 18:00:12 3536
ber01-VHDL13_DWOG_130300-2610130300-dsw--0-ia5 13-Oct-2026 03:00:31 4586
ber01-VHDL13_DWOG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 4182
ber01-VHDL13_DWON_111451-2610111451-dsw--0-ia5 11-Oct-2026 14:52:34 3288
ber01-VHDL13_DWON_111714-2610111714-dsw--0-ia5 11-Oct-2026 17:14:14 3240
ber01-VHDL13_DWON_120115-2610120115-dsw--0-ia5 12-Oct-2026 01:15:08 3487
ber01-VHDL13_DWON_120245-2610120245-dsw--0-ia5 12-Oct-2026 02:46:26 3610
ber01-VHDL13_DWON_120529-2610120529-dsw--0-ia5 12-Oct-2026 05:29:45 3610
ber01-VHDL13_DWON_120556-2610120556-dsw--0-ia5 12-Oct-2026 05:56:09 3749
ber01-VHDL13_DWON_121232-2610121232-dsw--0-ia5 12-Oct-2026 12:32:28 3602
ber01-VHDL13_DWON_121428-2610121428-dsw--0-ia5 12-Oct-2026 14:28:19 3744
ber01-VHDL13_DWON_121709-2610121709-dsw--0-ia5 12-Oct-2026 17:09:24 3313
ber01-VHDL13_DWON_121829-2610121829-dsw--0-ia5 12-Oct-2026 18:29:19 3296
ber01-VHDL13_DWON_122121-2610122121-dsw--0-ia5 12-Oct-2026 21:21:19 3332
ber01-VHDL13_DWON_130000-2610130000-dsw--0-ia5 13-Oct-2026 00:00:59 3885
ber01-VHDL13_DWON_130131-2610130131-dsw--0-ia5 13-Oct-2026 01:31:55 3843
ber01-VHDL13_DWON_130242-2610130242-dsw--0-ia5 13-Oct-2026 02:42:20 3843
ber01-VHDL13_DWON_130257-2610130257-dsw--0-ia5 13-Oct-2026 02:57:27 3815
ber01-VHDL13_DWON_130258-2610130258-dsw--0-ia5 13-Oct-2026 03:00:31 3839
ber01-VHDL13_DWON_130529-2610130529-dsw--0-ia5 13-Oct-2026 05:29:14 3908
ber01-VHDL13_DWON_130630-2610130630-dsw--0-ia5 13-Oct-2026 06:30:46 3789
ber01-VHDL13_DWON_131042-2610131042-dsw--0-ia5 13-Oct-2026 10:43:19 3874
ber01-VHDL13_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 2624
ber01-VHDL13_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 2997
ber01-VHDL13_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3127
ber01-VHDL13_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:03 3377
ber01-VHDL13_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 3007
ber01-VHDL13_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 2799
ber01-VHDL17_DWOG_121200-2610121200-dsw--0-ia5 12-Oct-2026 11:20:28 3235
ber01-VHDL17_DWOG_131200-2610131200-dsw--0-ia5 13-Oct-2026 11:46:12 4159
swis2-VHDL20_DWEG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 943
swis2-VHDL20_DWEG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 993
swis2-VHDL20_DWEG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 994
swis2-VHDL20_DWEG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:08 1114
swis2-VHDL20_DWEG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1160
swis2-VHDL20_DWEG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1082
swis2-VHDL20_DWEG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 986
swis2-VHDL20_DWEG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 951
swis2-VHDL20_DWEH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 1050
swis2-VHDL20_DWEH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 870
swis2-VHDL20_DWEH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 871
swis2-VHDL20_DWEH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 954
swis2-VHDL20_DWEH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1095
swis2-VHDL20_DWEH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 971
swis2-VHDL20_DWEH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 915
swis2-VHDL20_DWEH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1037
swis2-VHDL20_DWEI_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:12 962
swis2-VHDL20_DWEI_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:07 875
swis2-VHDL20_DWEI_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:01:19 875
swis2-VHDL20_DWEI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 995
swis2-VHDL20_DWEI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1024
swis2-VHDL20_DWEI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 982
swis2-VHDL20_DWEI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:01:24 873
swis2-VHDL20_DWEI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 973
swis2-VHDL20_DWHG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:45:25 1559
swis2-VHDL20_DWHG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:46:34 1512
swis2-VHDL20_DWHG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1561
swis2-VHDL20_DWHG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1534
swis2-VHDL20_DWHG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1847
swis2-VHDL20_DWHG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1545
swis2-VHDL20_DWHG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1475
swis2-VHDL20_DWHG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1765
swis2-VHDL20_DWHH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:45:25 1598
swis2-VHDL20_DWHH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:46:34 1557
swis2-VHDL20_DWHH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1595
swis2-VHDL20_DWHH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:45:19 1626
swis2-VHDL20_DWHH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:45:18 1796
swis2-VHDL20_DWHH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:47:51 1492
swis2-VHDL20_DWHH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1425
swis2-VHDL20_DWHH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1612
swis2-VHDL20_DWLG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1098
swis2-VHDL20_DWLG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 892
swis2-VHDL20_DWLG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 922
swis2-VHDL20_DWLG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1019
swis2-VHDL20_DWLG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1058
swis2-VHDL20_DWLG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 893
swis2-VHDL20_DWLG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1060
swis2-VHDL20_DWLG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 955
swis2-VHDL20_DWLH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1229
swis2-VHDL20_DWLH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 953
swis2-VHDL20_DWLH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 1031
swis2-VHDL20_DWLH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1128
swis2-VHDL20_DWLH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1174
swis2-VHDL20_DWLH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1003
swis2-VHDL20_DWLH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1155
swis2-VHDL20_DWLH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1019
swis2-VHDL20_DWLI_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 939
swis2-VHDL20_DWLI_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 860
swis2-VHDL20_DWLI_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 890
swis2-VHDL20_DWLI_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 987
swis2-VHDL20_DWLI_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1111
swis2-VHDL20_DWLI_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 874
swis2-VHDL20_DWLI_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1085
swis2-VHDL20_DWLI_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:29 1017
swis2-VHDL20_DWMO_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1562
swis2-VHDL20_DWMO_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1398
swis2-VHDL20_DWMO_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:05 1316
swis2-VHDL20_DWMO_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1406
swis2-VHDL20_DWMO_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1524
swis2-VHDL20_DWMO_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1194
swis2-VHDL20_DWMO_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1152
swis2-VHDL20_DWMO_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1394
swis2-VHDL20_DWMP_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1577
swis2-VHDL20_DWMP_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1248
swis2-VHDL20_DWMP_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:05 1166
swis2-VHDL20_DWMP_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1271
swis2-VHDL20_DWMP_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1332
swis2-VHDL20_DWMP_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:09 1244
swis2-VHDL20_DWMP_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:04 1216
swis2-VHDL20_DWMP_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:14 1323
swis2-VHDL20_DWPG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1011
swis2-VHDL20_DWPG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 932
swis2-VHDL20_DWPG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 948
swis2-VHDL20_DWPG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1045
swis2-VHDL20_DWPG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1205
swis2-VHDL20_DWPG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 969
swis2-VHDL20_DWPG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1295
swis2-VHDL20_DWPG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1204
swis2-VHDL20_DWPH_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:31:16 1168
swis2-VHDL20_DWPH_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:25 1065
swis2-VHDL20_DWPH_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:13 1028
swis2-VHDL20_DWPH_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:31 1125
swis2-VHDL20_DWPH_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:31:12 1396
swis2-VHDL20_DWPH_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:31 1240
swis2-VHDL20_DWPH_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:14 1575
swis2-VHDL20_DWPH_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:39 1351
swis2-VHDL20_DWSG_111800-2610111800-dsw--0-ia5 11-Oct-2026 18:30:04 1339
swis2-VHDL20_DWSG_120200-2610120200-dsw--0-ia5 12-Oct-2026 02:30:16 1313
swis2-VHDL20_DWSG_120400-2610120400-dsw--0-ia5 12-Oct-2026 05:00:19 1142
swis2-VHDL20_DWSG_120800-2610120800-dsw--0-ia5 12-Oct-2026 08:30:07 1283
swis2-VHDL20_DWSG_121800-2610121800-dsw--0-ia5 12-Oct-2026 18:30:03 1472
swis2-VHDL20_DWSG_130200-2610130200-dsw--0-ia5 13-Oct-2026 02:30:03 1317
swis2-VHDL20_DWSG_130400-2610130400-dsw--0-ia5 13-Oct-2026 05:00:18 1233
swis2-VHDL20_DWSG_130800-2610130800-dsw--0-ia5 13-Oct-2026 08:30:15 1243
wst04-VHDL20_DWEG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 239275
wst04-VHDL20_DWEG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 239621
wst04-VHDL20_DWEG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 239463
wst04-VHDL20_DWEG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 240159
wst04-VHDL20_DWEG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 236868
wst04-VHDL20_DWEG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 235744
wst04-VHDL20_DWEG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 235516
wst04-VHDL20_DWEG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 235091
wst04-VHDL20_DWEH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 233627
wst04-VHDL20_DWEH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 233124
wst04-VHDL20_DWEH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 233242
wst04-VHDL20_DWEH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:23 233869
wst04-VHDL20_DWEH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 233914
wst04-VHDL20_DWEH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 233432
wst04-VHDL20_DWEH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 233227
wst04-VHDL20_DWEH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 233931
wst04-VHDL20_DWEI_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:19 342950
wst04-VHDL20_DWEI_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 342863
wst04-VHDL20_DWEI_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 342630
wst04-VHDL20_DWEI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 342769
wst04-VHDL20_DWEI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 338625
wst04-VHDL20_DWEI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 338074
wst04-VHDL20_DWEI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 337814
wst04-VHDL20_DWEI_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:29 337979
wst04-VHDL20_DWHG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:45:25 336222
wst04-VHDL20_DWHG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:46:34 335748
wst04-VHDL20_DWHG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 335544
wst04-VHDL20_DWHG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:45:19 337001
wst04-VHDL20_DWHG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:45:18 338453
wst04-VHDL20_DWHG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 336662
wst04-VHDL20_DWHG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 336418
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wst04-VHDL20_DWHH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:45:25 328867
wst04-VHDL20_DWHH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:46:34 328849
wst04-VHDL20_DWHH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 227249
wst04-VHDL20_DWHH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:45:19 329372
wst04-VHDL20_DWHH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:45:18 319833
wst04-VHDL20_DWHH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:47:51 318469
wst04-VHDL20_DWHH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:18 225099
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wst04-VHDL20_DWLG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:22 327024
wst04-VHDL20_DWLG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 326571
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wst04-VHDL20_DWLG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 323947
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wst04-VHDL20_DWLH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:39 326403
wst04-VHDL20_DWLH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:43 326583
wst04-VHDL20_DWLH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 326809
wst04-VHDL20_DWLH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 325841
wst04-VHDL20_DWLH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 325126
wst04-VHDL20_DWLH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 325751
wst04-VHDL20_DWLH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 369816
wst04-VHDL20_DWLI_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:28 328062
wst04-VHDL20_DWLI_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 328241
wst04-VHDL20_DWLI_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:43 328363
wst04-VHDL20_DWLI_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 373071
wst04-VHDL20_DWLI_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 326451
wst04-VHDL20_DWLI_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 326291
wst04-VHDL20_DWLI_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:42 326939
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wst04-VHDL20_DWMO_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 443807
wst04-VHDL20_DWMO_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 443620
wst04-VHDL20_DWMO_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 443598
wst04-VHDL20_DWMO_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:20 347149
wst04-VHDL20_DWMO_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 447482
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wst04-VHDL20_DWMP_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 540899
wst04-VHDL20_DWMP_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:19 540844
wst04-VHDL20_DWMP_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 446440
wst04-VHDL20_DWMP_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:32 443945
wst04-VHDL20_DWMP_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:29 537776
wst04-VHDL20_DWMP_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:24 538041
wst04-VHDL20_DWMP_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:39 443300
wst04-VHDL20_DWPG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:28 338516
wst04-VHDL20_DWPG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 239342
wst04-VHDL20_DWPG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:33 338856
wst04-VHDL20_DWPG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:51 383475
wst04-VHDL20_DWPG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:39 334999
wst04-VHDL20_DWPG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236347
wst04-VHDL20_DWPG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 335542
wst04-VHDL20_DWPG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:49 379952
wst04-VHDL20_DWPH_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:31:22 238270
wst04-VHDL20_DWPH_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:25 238196
wst04-VHDL20_DWPH_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:33 238322
wst04-VHDL20_DWPH_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:45 238521
wst04-VHDL20_DWPH_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:31:32 236735
wst04-VHDL20_DWPH_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:31 236589
wst04-VHDL20_DWPH_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:34 237433
wst04-VHDL20_DWPH_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:43 281393
wst04-VHDL20_DWSG_111800-2610111800-omedes--0.pdf 11-Oct-2026 18:30:15 339734
wst04-VHDL20_DWSG_120200-2610120200-omedes--0.pdf 12-Oct-2026 02:30:23 340350
wst04-VHDL20_DWSG_120400-2610120400-omedes--0.pdf 12-Oct-2026 05:00:13 339445
wst04-VHDL20_DWSG_120800-2610120800-omedes--0.pdf 12-Oct-2026 08:30:31 339560
wst04-VHDL20_DWSG_121800-2610121800-omedes--0.pdf 12-Oct-2026 18:30:13 335263
wst04-VHDL20_DWSG_130200-2610130200-omedes--0.pdf 13-Oct-2026 02:30:13 334829
wst04-VHDL20_DWSG_130400-2610130400-omedes--0.pdf 13-Oct-2026 05:00:14 334851
wst04-VHDL20_DWSG_130800-2610130800-omedes--0.pdf 13-Oct-2026 08:30:22 334211