Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_220600 22-Apr-2026 14:04:05 6944
FPDL13_DWMZ_230600 23-Apr-2026 12:23:44 3851
SXDL31_DWAV_220800 22-Apr-2026 07:15:29 6475
SXDL31_DWAV_221800 22-Apr-2026 16:47:00 7843
SXDL31_DWAV_230800 23-Apr-2026 07:08:29 6555
SXDL31_DWAV_231800 23-Apr-2026 16:15:05 8383
SXDL31_DWAV_LATEST 23-Apr-2026 16:15:05 8383
SXDL33_DWAV_220000 22-Apr-2026 09:16:39 6334
SXDL33_DWAV_230000 23-Apr-2026 09:40:49 10940
SXDL33_DWAV_LATEST 23-Apr-2026 09:40:49 10940
ber01-FWDL39_DWMS_221230-2604221230-dsw--0-ia5 22-Apr-2026 10:28:27 1738
ber01-FWDL39_DWMS_231230-2604231230-dsw--0-ia5 23-Apr-2026 11:27:02 1032
ber01-VHDL13_DWEG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:28:16 2791
ber01-VHDL13_DWEG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:28:17 2951
ber01-VHDL13_DWEG_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:37:01 2847
ber01-VHDL13_DWEH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:28:16 2985
ber01-VHDL13_DWEH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:28:17 2942
ber01-VHDL13_DWEH_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:36:56 2838
ber01-VHDL13_DWEI_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:28:16 2651
ber01-VHDL13_DWEI_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:28:17 2707
ber01-VHDL13_DWEI_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:37:01 2681
ber01-VHDL13_DWHG_220200_COR-2604220200-dsw--0-ia5 22-Apr-2026 02:56:01 2542
ber01-VHDL13_DWHG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:07 3429
ber01-VHDL13_DWHG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 3090
ber01-VHDL13_DWHH_220200_COR-2604220200-dsw--0-ia5 22-Apr-2026 02:57:10 2495
ber01-VHDL13_DWHH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:07 3221
ber01-VHDL13_DWHH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 3159
ber01-VHDL13_DWLG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2383
ber01-VHDL13_DWLG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2437
ber01-VHDL13_DWLH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2133
ber01-VHDL13_DWLH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2213
ber01-VHDL13_DWLI_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2162
ber01-VHDL13_DWLI_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2166
ber01-VHDL13_DWMO_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2743
ber01-VHDL13_DWMO_220800_COR-2604220800-dsw--0-ia5 22-Apr-2026 09:23:22 2690
ber01-VHDL13_DWMO_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 2506
ber01-VHDL13_DWMP_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2545
ber01-VHDL13_DWMP_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 2121
ber01-VHDL13_DWOG_220300-2604220300-dsw--0-ia5 22-Apr-2026 03:00:14 4732
ber01-VHDL13_DWOG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 4449
ber01-VHDL13_DWOG_221700-2604221700-dsw--0-ia5 22-Apr-2026 18:00:02 4040
ber01-VHDL13_DWOG_230300-2604230300-dsw--0-ia5 23-Apr-2026 03:00:06 4098
ber01-VHDL13_DWOG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 3726
ber01-VHDL13_DWOG_231700-2604231700-dsw--0-ia5 23-Apr-2026 18:00:02 3371
ber01-VHDL13_DWON_220141-2604220141-dsw--0-ia5 22-Apr-2026 01:41:41 3874
ber01-VHDL13_DWON_220237-2604220237-dsw--0-ia5 22-Apr-2026 02:38:03 3874
ber01-VHDL13_DWON_220529-2604220529-dsw--0-ia5 22-Apr-2026 05:29:32 4108
ber01-VHDL13_DWON_220545-2604220545-dsw--0-ia5 22-Apr-2026 05:45:36 3991
ber01-VHDL13_DWON_220850-2604220850-dsw--0-ia5 22-Apr-2026 08:50:28 3991
ber01-VHDL13_DWON_221500-2604221500-dsw--0-ia5 22-Apr-2026 15:00:32 3800
ber01-VHDL13_DWON_221728-2604221728-dsw--0-ia5 22-Apr-2026 17:28:22 3536
ber01-VHDL13_DWON_221822-2604221822-dsw--0-ia5 22-Apr-2026 18:23:01 3598
ber01-VHDL13_DWON_222215-2604222215-dsw--0-ia5 22-Apr-2026 22:15:30 4046
ber01-VHDL13_DWON_230002-2604230002-dsw--0-ia5 23-Apr-2026 00:02:21 4046
ber01-VHDL13_DWON_230130-2604230130-dsw--0-ia5 23-Apr-2026 01:30:47 4005
ber01-VHDL13_DWON_230251-2604230251-dsw--0-ia5 23-Apr-2026 02:51:49 4005
ber01-VHDL13_DWON_230509-2604230509-dsw--0-ia5 23-Apr-2026 05:09:17 4221
ber01-VHDL13_DWON_230606-2604230606-dsw--0-ia5 23-Apr-2026 06:06:27 4221
ber01-VHDL13_DWON_230650-2604230650-dsw--0-ia5 23-Apr-2026 06:50:57 4113
ber01-VHDL13_DWON_230743-2604230743-dsw--0-ia5 23-Apr-2026 07:43:11 4113
ber01-VHDL13_DWON_230846-2604230846-dsw--0-ia5 23-Apr-2026 08:46:58 4113
ber01-VHDL13_DWON_231454-2604231454-dsw--0-ia5 23-Apr-2026 14:54:12 3610
ber01-VHDL13_DWON_231648-2604231648-dsw--0-ia5 23-Apr-2026 16:48:17 3375
ber01-VHDL13_DWON_231919-2604231919-dsw--0-ia5 23-Apr-2026 19:19:53 3348
ber01-VHDL13_DWPG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2319
ber01-VHDL13_DWPG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2214
ber01-VHDL13_DWPG_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 09:20:47 2322
ber01-VHDL13_DWPH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 2358
ber01-VHDL13_DWPH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2396
ber01-VHDL13_DWPH_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 09:21:11 2791
ber01-VHDL13_DWSG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:07 2848
ber01-VHDL13_DWSG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 2343
ber01-VHDL17_DWOG_221200-2604221200-dsw--0-ia5 22-Apr-2026 11:29:17 2624
ber01-VHDL17_DWOG_231200-2604231200-dsw--0-ia5 23-Apr-2026 11:28:41 3203
swis2-VHDL20_DWEG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1191
swis2-VHDL20_DWEG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1246
swis2-VHDL20_DWEG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1376
swis2-VHDL20_DWEG_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:02 1487
swis2-VHDL20_DWEG_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 1209
swis2-VHDL20_DWEG_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 1379
swis2-VHDL20_DWEG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 1446
swis2-VHDL20_DWEG_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:36:47 1342
swis2-VHDL20_DWEG_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1403
swis2-VHDL20_DWEH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1363
swis2-VHDL20_DWEH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1440
swis2-VHDL20_DWEH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1561
swis2-VHDL20_DWEH_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:02 1692
swis2-VHDL20_DWEH_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 1364
swis2-VHDL20_DWEH_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 1485
swis2-VHDL20_DWEH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 1518
swis2-VHDL20_DWEH_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:36:47 1265
swis2-VHDL20_DWEH_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1423
swis2-VHDL20_DWEI_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1148
swis2-VHDL20_DWEI_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1158
swis2-VHDL20_DWEI_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1275
swis2-VHDL20_DWEI_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:02 1274
swis2-VHDL20_DWEI_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 1132
swis2-VHDL20_DWEI_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 1161
swis2-VHDL20_DWEI_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 1260
swis2-VHDL20_DWEI_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 08:36:47 1234
swis2-VHDL20_DWEI_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1279
swis2-VHDL20_DWHG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:45:07 1333
swis2-VHDL20_DWHG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:16 1416
swis2-VHDL20_DWHG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:45:02 1698
swis2-VHDL20_DWHG_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:45:02 1710
swis2-VHDL20_DWHG_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:45:11 1321
swis2-VHDL20_DWHG_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:17 1322
swis2-VHDL20_DWHG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:45:02 1340
swis2-VHDL20_DWHG_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:45:01 1310
swis2-VHDL20_DWHH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:45:07 1191
swis2-VHDL20_DWHH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:16 1277
swis2-VHDL20_DWHH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:45:02 1492
swis2-VHDL20_DWHH_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:45:02 1668
swis2-VHDL20_DWHH_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:45:11 1286
swis2-VHDL20_DWHH_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:17 1262
swis2-VHDL20_DWHH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:45:02 1431
swis2-VHDL20_DWHH_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:45:01 1353
swis2-VHDL20_DWLG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 1092
swis2-VHDL20_DWLG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 1022
swis2-VHDL20_DWLG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:21 1125
swis2-VHDL20_DWLG_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:31:03 1190
swis2-VHDL20_DWLG_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:21 1108
swis2-VHDL20_DWLG_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 904
swis2-VHDL20_DWLG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:22 1063
swis2-VHDL20_DWLG_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:31:01 1229
swis2-VHDL20_DWLH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 900
swis2-VHDL20_DWLH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 827
swis2-VHDL20_DWLH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:21 1008
swis2-VHDL20_DWLH_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:31:03 1003
swis2-VHDL20_DWLH_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:21 928
swis2-VHDL20_DWLH_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 863
swis2-VHDL20_DWLH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:22 1029
swis2-VHDL20_DWLH_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:31:01 1173
swis2-VHDL20_DWLI_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 879
swis2-VHDL20_DWLI_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 826
swis2-VHDL20_DWLI_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:21 894
swis2-VHDL20_DWLI_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:31:03 914
swis2-VHDL20_DWLI_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:21 900
swis2-VHDL20_DWLI_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 797
swis2-VHDL20_DWLI_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:22 890
swis2-VHDL20_DWLI_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:31:01 888
swis2-VHDL20_DWMO_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 954
swis2-VHDL20_DWMO_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:06 952
swis2-VHDL20_DWMO_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1198
swis2-VHDL20_DWMO_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:06 1069
swis2-VHDL20_DWMO_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 951
swis2-VHDL20_DWMO_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:01 946
swis2-VHDL20_DWMO_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 970
swis2-VHDL20_DWMO_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1146
swis2-VHDL20_DWMP_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1105
swis2-VHDL20_DWMP_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:06 1102
swis2-VHDL20_DWMP_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1268
swis2-VHDL20_DWMP_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:06 1107
swis2-VHDL20_DWMP_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 953
swis2-VHDL20_DWMP_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:01 952
swis2-VHDL20_DWMP_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:08 970
swis2-VHDL20_DWMP_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1051
swis2-VHDL20_DWPG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 784
swis2-VHDL20_DWPG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 779
swis2-VHDL20_DWPG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:21 878
swis2-VHDL20_DWPG_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:31:03 1017
swis2-VHDL20_DWPG_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:21 999
swis2-VHDL20_DWPG_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 813
swis2-VHDL20_DWPG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:22 975
swis2-VHDL20_DWPG_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 09:23:26 975
swis2-VHDL20_DWPG_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:31:01 1055
swis2-VHDL20_DWPH_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:20 780
swis2-VHDL20_DWPH_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:12 783
swis2-VHDL20_DWPH_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:21 925
swis2-VHDL20_DWPH_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:31:03 967
swis2-VHDL20_DWPH_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:21 855
swis2-VHDL20_DWPH_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:11 893
swis2-VHDL20_DWPH_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:22 1088
swis2-VHDL20_DWPH_230800_COR-2604230800-dsw--0-ia5 23-Apr-2026 09:22:57 1092
swis2-VHDL20_DWPH_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:31:01 1192
swis2-VHDL20_DWSG_220200-2604220200-dsw--0-ia5 22-Apr-2026 02:30:02 1212
swis2-VHDL20_DWSG_220400-2604220400-dsw--0-ia5 22-Apr-2026 05:00:18 1225
swis2-VHDL20_DWSG_220800-2604220800-dsw--0-ia5 22-Apr-2026 08:30:02 1550
swis2-VHDL20_DWSG_221800-2604221800-dsw--0-ia5 22-Apr-2026 18:30:02 1194
swis2-VHDL20_DWSG_230200-2604230200-dsw--0-ia5 23-Apr-2026 02:30:03 1039
swis2-VHDL20_DWSG_230400-2604230400-dsw--0-ia5 23-Apr-2026 05:00:17 1008
swis2-VHDL20_DWSG_230800-2604230800-dsw--0-ia5 23-Apr-2026 08:30:04 1120
swis2-VHDL20_DWSG_231800-2604231800-dsw--0-ia5 23-Apr-2026 18:30:02 1021
wst04-VHDL20_DWEG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 232558
wst04-VHDL20_DWEG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 137269
wst04-VHDL20_DWEG_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:11 233616
wst04-VHDL20_DWEG_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:17 235504
wst04-VHDL20_DWEG_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:11 234496
wst04-VHDL20_DWEG_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:11 137194
wst04-VHDL20_DWEG_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:18 235507
wst04-VHDL20_DWEG_230800_COR-2604230800-omedes-..> 23-Apr-2026 08:37:09 235383
wst04-VHDL20_DWEG_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:12 238378
wst04-VHDL20_DWEH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 229156
wst04-VHDL20_DWEH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 229391
wst04-VHDL20_DWEH_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:11 229968
wst04-VHDL20_DWEH_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:12 232758
wst04-VHDL20_DWEH_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:11 232315
wst04-VHDL20_DWEH_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:11 231932
wst04-VHDL20_DWEH_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:11 232593
wst04-VHDL20_DWEH_230800_COR-2604230800-omedes-..> 23-Apr-2026 08:37:01 232303
wst04-VHDL20_DWEH_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:16 231806
wst04-VHDL20_DWEI_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 330241
wst04-VHDL20_DWEI_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 329997
wst04-VHDL20_DWEI_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:17 329829
wst04-VHDL20_DWEI_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:17 335071
wst04-VHDL20_DWEI_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:17 334668
wst04-VHDL20_DWEI_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:11 334170
wst04-VHDL20_DWEI_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:18 334366
wst04-VHDL20_DWEI_230800_COR-2604230800-omedes-..> 23-Apr-2026 08:37:09 334332
wst04-VHDL20_DWEI_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:16 339010
wst04-VHDL20_DWHG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:45:11 325334
wst04-VHDL20_DWHG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 325402
wst04-VHDL20_DWHG_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:45:12 326889
wst04-VHDL20_DWHG_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:45:12 328343
wst04-VHDL20_DWHG_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:45:11 327189
wst04-VHDL20_DWHG_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:17 327190
wst04-VHDL20_DWHG_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:45:12 327241
wst04-VHDL20_DWHG_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:45:11 328479
wst04-VHDL20_DWHH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:45:11 315720
wst04-VHDL20_DWHH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 220125
wst04-VHDL20_DWHH_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:45:12 314744
wst04-VHDL20_DWHH_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:45:12 311804
wst04-VHDL20_DWHH_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:45:11 311655
wst04-VHDL20_DWHH_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:17 217679
wst04-VHDL20_DWHH_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:45:12 311941
wst04-VHDL20_DWHH_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:45:11 312973
wst04-VHDL20_DWLG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:28 318546
wst04-VHDL20_DWLG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 318205
wst04-VHDL20_DWLG_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:47 318374
wst04-VHDL20_DWLG_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:31:27 318036
wst04-VHDL20_DWLG_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:21 317798
wst04-VHDL20_DWLG_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:42 317500
wst04-VHDL20_DWLG_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:41 317738
wst04-VHDL20_DWLG_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:31:21 323007
wst04-VHDL20_DWLH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 320617
wst04-VHDL20_DWLH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 320247
wst04-VHDL20_DWLH_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:41 320780
wst04-VHDL20_DWLH_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:31:22 320822
wst04-VHDL20_DWLH_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:21 320307
wst04-VHDL20_DWLH_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:42 320475
wst04-VHDL20_DWLH_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:41 320734
wst04-VHDL20_DWLH_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:31:21 318337
wst04-VHDL20_DWLI_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 316448
wst04-VHDL20_DWLI_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:42 316076
wst04-VHDL20_DWLI_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:41 360655
wst04-VHDL20_DWLI_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:31:22 321225
wst04-VHDL20_DWLI_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:21 321224
wst04-VHDL20_DWLI_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:42 321071
wst04-VHDL20_DWLI_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:47 365722
wst04-VHDL20_DWLI_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:31:27 321754
wst04-VHDL20_DWMO_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:16 429588
wst04-VHDL20_DWMO_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 429802
wst04-VHDL20_DWMO_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:17 429980
wst04-VHDL20_DWMO_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:17 339041
wst04-VHDL20_DWMO_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:11 437253
wst04-VHDL20_DWMO_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:17 438202
wst04-VHDL20_DWMO_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:18 437868
wst04-VHDL20_DWMO_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:18 344481
wst04-VHDL20_DWMP_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:16 528831
wst04-VHDL20_DWMP_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:16 529099
wst04-VHDL20_DWMP_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:21 436458
wst04-VHDL20_DWMP_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:17 438612
wst04-VHDL20_DWMP_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:17 530420
wst04-VHDL20_DWMP_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:17 531405
wst04-VHDL20_DWMP_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:22 438525
wst04-VHDL20_DWMP_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:18 439590
wst04-VHDL20_DWPG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 233687
wst04-VHDL20_DWPG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:32 327765
wst04-VHDL20_DWPG_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:41 372416
wst04-VHDL20_DWPG_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:31:22 333933
wst04-VHDL20_DWPG_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:28 236438
wst04-VHDL20_DWPG_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:32 333319
wst04-VHDL20_DWPG_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:41 378405
wst04-VHDL20_DWPG_230800_COR-2604230800-omedes-..> 23-Apr-2026 09:24:17 378378
wst04-VHDL20_DWPG_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:31:21 327916
wst04-VHDL20_DWPH_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:20 235661
wst04-VHDL20_DWPH_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:32 235376
wst04-VHDL20_DWPH_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:41 235469
wst04-VHDL20_DWPH_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:31:22 235539
wst04-VHDL20_DWPH_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:21 234928
wst04-VHDL20_DWPH_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:32 236059
wst04-VHDL20_DWPH_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:41 236607
wst04-VHDL20_DWPH_230800_COR-2604230800-omedes-..> 23-Apr-2026 09:23:57 236607
wst04-VHDL20_DWPH_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:31:21 234284
wst04-VHDL20_DWSG_220200-2604220200-omedes--0.pdf 22-Apr-2026 02:30:12 328785
wst04-VHDL20_DWSG_220400-2604220400-omedes--0.pdf 22-Apr-2026 05:00:12 329556
wst04-VHDL20_DWSG_220800-2604220800-omedes--0.pdf 22-Apr-2026 08:30:11 331065
wst04-VHDL20_DWSG_221800-2604221800-omedes--0.pdf 22-Apr-2026 18:30:12 333451
wst04-VHDL20_DWSG_230200-2604230200-omedes--0.pdf 23-Apr-2026 02:30:11 332790
wst04-VHDL20_DWSG_230400-2604230400-omedes--0.pdf 23-Apr-2026 05:00:11 332923
wst04-VHDL20_DWSG_230800-2604230800-omedes--0.pdf 23-Apr-2026 08:30:18 333311
wst04-VHDL20_DWSG_231800-2604231800-omedes--0.pdf 23-Apr-2026 18:30:12 336744