Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_290600 29-Dec-2025 13:49:46 3138
FPDL13_DWMZ_300600 30-Dec-2025 14:14:30 4240
SXDL31_DWAV_290800 29-Dec-2025 09:23:38 16595
SXDL31_DWAV_291800 29-Dec-2025 18:02:34 10886
SXDL31_DWAV_300800 30-Dec-2025 08:39:20 10007
SXDL31_DWAV_LATEST 30-Dec-2025 08:39:20 10007
SXDL33_DWAV_290000 29-Dec-2025 11:37:51 13371
SXDL33_DWAV_300000 30-Dec-2025 11:03:24 9721
SXDL33_DWAV_LATEST 30-Dec-2025 11:03:24 9721
ber01-FWDL39_DWMS_291230-2512291230-dsw--0-ia5 29-Dec-2025 13:28:17 1654
ber01-FWDL39_DWMS_291230_COR-2512291230-dsw--0-ia5 29-Dec-2025 14:16:07 1663
ber01-FWDL39_DWMS_301230-2512301230-dsw--0-ia5 30-Dec-2025 12:43:02 1716
ber01-VHDL13_DWEH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:17 4135
ber01-VHDL13_DWEH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 4316
ber01-VHDL13_DWEH_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:17 4181
ber01-VHDL13_DWEH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:15 4181
ber01-VHDL13_DWEH_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:41 3689
ber01-VHDL13_DWEH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:28:17 3419
ber01-VHDL13_DWEH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:28:11 3910
ber01-VHDL13_DWEH_300400-2512300400-dsw--0-ia5 30-Dec-2025 05:58:12 3940
ber01-VHDL13_DWEH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:28:17 3959
ber01-VHDL13_DWEH_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:42 3811
ber01-VHDL13_DWHG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3473
ber01-VHDL13_DWHG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3870
ber01-VHDL13_DWHG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 3870
ber01-VHDL13_DWHG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:10 3855
ber01-VHDL13_DWHG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:11 3894
ber01-VHDL13_DWHG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:09 3457
ber01-VHDL13_DWHG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3377
ber01-VHDL13_DWHG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:06 3670
ber01-VHDL13_DWHH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3290
ber01-VHDL13_DWHH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3393
ber01-VHDL13_DWHH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:07 3393
ber01-VHDL13_DWHH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:10 3222
ber01-VHDL13_DWHH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:11 3857
ber01-VHDL13_DWHH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:09 3289
ber01-VHDL13_DWHH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3260
ber01-VHDL13_DWHH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:06 3216
ber01-VHDL13_DWLG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3285
ber01-VHDL13_DWLG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3974
ber01-VHDL13_DWLG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3685
ber01-VHDL13_DWLG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3311
ber01-VHDL13_DWLG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:00 3170
ber01-VHDL13_DWLG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 2957
ber01-VHDL13_DWLG_300200_COR-2512300200-dsw--0-ia5 30-Dec-2025 03:50:11 2921
ber01-VHDL13_DWLG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:02 3288
ber01-VHDL13_DWLG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3657
ber01-VHDL13_DWLH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2954
ber01-VHDL13_DWLH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3431
ber01-VHDL13_DWLH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3141
ber01-VHDL13_DWLH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3011
ber01-VHDL13_DWLH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:00 2989
ber01-VHDL13_DWLH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 3009
ber01-VHDL13_DWLH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:02 3239
ber01-VHDL13_DWLH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3390
ber01-VHDL13_DWLI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2618
ber01-VHDL13_DWLI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3129
ber01-VHDL13_DWLI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 2940
ber01-VHDL13_DWLI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 2679
ber01-VHDL13_DWLI_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:00 2591
ber01-VHDL13_DWLI_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 2770
ber01-VHDL13_DWLI_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:02 2998
ber01-VHDL13_DWLI_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3124
ber01-VHDL13_DWMG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3081
ber01-VHDL13_DWMG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3574
ber01-VHDL13_DWMG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3768
ber01-VHDL13_DWMG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3800
ber01-VHDL13_DWMG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:02 3460
ber01-VHDL13_DWMG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:06 4077
ber01-VHDL13_DWMG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 4045
ber01-VHDL13_DWMG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 4014
ber01-VHDL13_DWMO_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3217
ber01-VHDL13_DWMO_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3423
ber01-VHDL13_DWMO_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3423
ber01-VHDL13_DWMO_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3423
ber01-VHDL13_DWMO_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 09:42:57 3556
ber01-VHDL13_DWMO_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:02 3029
ber01-VHDL13_DWMO_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:06 3452
ber01-VHDL13_DWMO_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3452
ber01-VHDL13_DWMO_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3463
ber01-VHDL13_DWMO_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:36:56 3496
ber01-VHDL13_DWMP_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3093
ber01-VHDL13_DWMP_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3619
ber01-VHDL13_DWMP_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3619
ber01-VHDL13_DWMP_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3619
ber01-VHDL13_DWMP_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 09:43:11 3498
ber01-VHDL13_DWMP_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:02 3150
ber01-VHDL13_DWMP_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:06 3723
ber01-VHDL13_DWMP_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3593
ber01-VHDL13_DWMP_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3593
ber01-VHDL13_DWMP_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:18 3735
ber01-VHDL13_DWOG_281700-2512281700-dsw--0-ia5 28-Dec-2025 19:00:01 5551
ber01-VHDL13_DWOG_281700_COR-2512281700-dsw--0-ia5 28-Dec-2025 19:35:27 5256
ber01-VHDL13_DWOG_290300-2512290300-dsw--0-ia5 29-Dec-2025 04:00:07 5820
ber01-VHDL13_DWOG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 5360
ber01-VHDL13_DWOG_291700-2512291700-dsw--0-ia5 29-Dec-2025 19:00:01 4917
ber01-VHDL13_DWOG_300300-2512300300-dsw--0-ia5 30-Dec-2025 04:00:01 5604
ber01-VHDL13_DWOG_300800-2512300800-dsw--0-ia5 30-Dec-2025 10:38:21 6227
ber01-VHDL13_DWOH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:13 3842
ber01-VHDL13_DWOH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 4098
ber01-VHDL13_DWOH_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:12 4026
ber01-VHDL13_DWOH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:15 4026
ber01-VHDL13_DWOH_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:41 3779
ber01-VHDL13_DWOH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:28:17 3188
ber01-VHDL13_DWOH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:28:11 3712
ber01-VHDL13_DWOH_300400-2512300400-dsw--0-ia5 30-Dec-2025 05:58:12 3735
ber01-VHDL13_DWOH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:28:17 3755
ber01-VHDL13_DWOH_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:42 3642
ber01-VHDL13_DWOI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:28:13 3121
ber01-VHDL13_DWOI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:28:12 3585
ber01-VHDL13_DWOI_290400-2512290400-dsw--0-ia5 29-Dec-2025 05:58:17 3661
ber01-VHDL13_DWOI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:28:12 3667
ber01-VHDL13_DWOI_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:37 3763
ber01-VHDL13_DWOI_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:28:11 3100
ber01-VHDL13_DWOI_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:28:17 3369
ber01-VHDL13_DWOI_300400-2512300400-dsw--0-ia5 30-Dec-2025 05:58:15 3635
ber01-VHDL13_DWOI_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:28:11 3661
ber01-VHDL13_DWOI_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:42 3471
ber01-VHDL13_DWON_281904-2512281904-dsw--0-ia5 28-Dec-2025 19:04:44 4331
ber01-VHDL13_DWON_281934-2512281934-dsw--0-ia5 28-Dec-2025 19:34:46 4724
ber01-VHDL13_DWON_281935-2512281935-dsw--0-ia5 28-Dec-2025 19:35:41 4724
ber01-VHDL13_DWON_282034-2512282034-dsw--0-ia5 28-Dec-2025 20:34:29 4790
ber01-VHDL13_DWON_290017-2512290017-dsw--0-ia5 29-Dec-2025 00:17:11 4796
ber01-VHDL13_DWON_290355-2512290355-dsw--0-ia5 29-Dec-2025 03:55:27 4796
ber01-VHDL13_DWON_290630-2512290630-dsw--0-ia5 29-Dec-2025 06:30:11 4676
ber01-VHDL13_DWON_290642-2512290642-dsw--0-ia5 29-Dec-2025 06:42:51 4696
ber01-VHDL13_DWON_290759-2512290759-dsw--0-ia5 29-Dec-2025 07:59:13 5029
ber01-VHDL13_DWON_291150-2512291150-dsw--0-ia5 29-Dec-2025 11:51:02 5029
ber01-VHDL13_DWON_291605-2512291605-dsw--0-ia5 29-Dec-2025 16:05:32 4246
ber01-VHDL13_DWON_291826-2512291826-dsw--0-ia5 29-Dec-2025 18:26:27 4246
ber01-VHDL13_DWON_300159-2512300159-dsw--0-ia5 30-Dec-2025 01:59:36 4562
ber01-VHDL13_DWON_300338-2512300338-dsw--0-ia5 30-Dec-2025 03:38:35 4565
ber01-VHDL13_DWON_300631-2512300631-dsw--0-ia5 30-Dec-2025 06:31:09 4334
ber01-VHDL13_DWON_300733-2512300733-dsw--0-ia5 30-Dec-2025 07:33:24 5058
ber01-VHDL13_DWON_301037-2512301037-dsw--0-ia5 30-Dec-2025 10:37:57 5016
ber01-VHDL13_DWON_301547-2512301547-dsw--0-ia5 30-Dec-2025 15:47:21 4423
ber01-VHDL13_DWPG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 2585
ber01-VHDL13_DWPG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 2716
ber01-VHDL13_DWPG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 2674
ber01-VHDL13_DWPG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 2370
ber01-VHDL13_DWPG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:00 2356
ber01-VHDL13_DWPG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 2500
ber01-VHDL13_DWPG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:02 2651
ber01-VHDL13_DWPG_300400_COR-2512300400-dsw--0-ia5 30-Dec-2025 08:46:12 2862
ber01-VHDL13_DWPG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3068
ber01-VHDL13_DWPH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:06 3317
ber01-VHDL13_DWPH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:03 3466
ber01-VHDL13_DWPH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:01 3110
ber01-VHDL13_DWPH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3061
ber01-VHDL13_DWPH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:00 3113
ber01-VHDL13_DWPH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 3260
ber01-VHDL13_DWPH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:02 3568
ber01-VHDL13_DWPH_300400_COR-2512300400-dsw--0-ia5 30-Dec-2025 08:47:13 3955
ber01-VHDL13_DWPH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3944
ber01-VHDL13_DWSG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:30:02 3074
ber01-VHDL13_DWSG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:30:09 3400
ber01-VHDL13_DWSG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 3325
ber01-VHDL13_DWSG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:30:03 3326
ber01-VHDL13_DWSG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:30:02 2870
ber01-VHDL13_DWSG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:30:01 3431
ber01-VHDL13_DWSG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3444
ber01-VHDL13_DWSG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:30:04 3152
ber01-VHDL17_DWOG_291200-2512291200-dsw--0-ia5 29-Dec-2025 12:31:59 3602
ber01-VHDL17_DWOG_301200-2512301200-dsw--0-ia5 30-Dec-2025 12:56:23 3014
swis2-VHDL20_DWEG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 4534
swis2-VHDL20_DWEG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 4733
swis2-VHDL20_DWEG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4525
swis2-VHDL20_DWEG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4735
swis2-VHDL20_DWEG_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:31 4598
swis2-VHDL20_DWEG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:06 3611
swis2-VHDL20_DWEG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 4085
swis2-VHDL20_DWEG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 4293
swis2-VHDL20_DWEG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 4537
swis2-VHDL20_DWEG_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:28 3821
swis2-VHDL20_DWEH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 4978
swis2-VHDL20_DWEH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 5086
swis2-VHDL20_DWEH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4714
swis2-VHDL20_DWEH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4687
swis2-VHDL20_DWEH_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:31 4534
swis2-VHDL20_DWEH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:06 4004
swis2-VHDL20_DWEH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 4461
swis2-VHDL20_DWEH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 4458
swis2-VHDL20_DWEH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 4732
swis2-VHDL20_DWEH_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:28 3989
swis2-VHDL20_DWEI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3568
swis2-VHDL20_DWEI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 3975
swis2-VHDL20_DWEI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:06 4201
swis2-VHDL20_DWEI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4431
swis2-VHDL20_DWEI_290800_COR-2512290800-dsw--0-ia5 29-Dec-2025 15:16:31 4650
swis2-VHDL20_DWEI_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:06 3548
swis2-VHDL20_DWEI_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 3757
swis2-VHDL20_DWEI_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 4174
swis2-VHDL20_DWEI_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 4379
swis2-VHDL20_DWEI_300800_COR-2512300800-dsw--0-ia5 30-Dec-2025 09:37:28 3650
swis2-VHDL20_DWHG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3656
swis2-VHDL20_DWHG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4056
swis2-VHDL20_DWHG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:08 4053
swis2-VHDL20_DWHG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4752
swis2-VHDL20_DWHG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 4077
swis2-VHDL20_DWHG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3643
swis2-VHDL20_DWHG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3560
swis2-VHDL20_DWHG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 4407
swis2-VHDL20_DWHH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3476
swis2-VHDL20_DWHH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3579
swis2-VHDL20_DWHH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:07 3579
swis2-VHDL20_DWHH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:09 4032
swis2-VHDL20_DWHH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 4043
swis2-VHDL20_DWHH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3475
swis2-VHDL20_DWHH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:06 3446
swis2-VHDL20_DWHH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 3877
swis2-VHDL20_DWLG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3688
swis2-VHDL20_DWLG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4380
swis2-VHDL20_DWLG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 4142
swis2-VHDL20_DWLG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3967
swis2-VHDL20_DWLG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3627
swis2-VHDL20_DWLG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3417
swis2-VHDL20_DWLG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:12 3683
swis2-VHDL20_DWLG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 4303
swis2-VHDL20_DWLH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3364
swis2-VHDL20_DWLH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3844
swis2-VHDL20_DWLH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3565
swis2-VHDL20_DWLH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3638
swis2-VHDL20_DWLH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3413
swis2-VHDL20_DWLH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3436
swis2-VHDL20_DWLH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:12 3641
swis2-VHDL20_DWLH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 4149
swis2-VHDL20_DWLI_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3023
swis2-VHDL20_DWLI_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3537
swis2-VHDL20_DWLI_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3363
swis2-VHDL20_DWLI_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3300
swis2-VHDL20_DWLI_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3014
swis2-VHDL20_DWLI_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3196
swis2-VHDL20_DWLI_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:12 3395
swis2-VHDL20_DWLI_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 3734
swis2-VHDL20_DWMG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3463
swis2-VHDL20_DWMG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4010
swis2-VHDL20_DWMG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4251
swis2-VHDL20_DWMG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4548
swis2-VHDL20_DWMG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3900
swis2-VHDL20_DWMG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 4453
swis2-VHDL20_DWMG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 4527
swis2-VHDL20_DWMG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:06 4843
swis2-VHDL20_DWMO_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3344
swis2-VHDL20_DWMO_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3817
swis2-VHDL20_DWMO_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 3827
swis2-VHDL20_DWMO_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4263
swis2-VHDL20_DWMO_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3472
swis2-VHDL20_DWMO_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 3921
swis2-VHDL20_DWMO_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 3934
swis2-VHDL20_DWMO_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 4334
swis2-VHDL20_DWMP_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3467
swis2-VHDL20_DWMP_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4012
swis2-VHDL20_DWMP_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 4089
swis2-VHDL20_DWMP_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 4218
swis2-VHDL20_DWMP_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3596
swis2-VHDL20_DWMP_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:06 4191
swis2-VHDL20_DWMP_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:06 4075
swis2-VHDL20_DWMP_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 4531
swis2-VHDL20_DWPG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 3316
swis2-VHDL20_DWPG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 3242
swis2-VHDL20_DWPG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3049
swis2-VHDL20_DWPG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 2949
swis2-VHDL20_DWPG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 2935
swis2-VHDL20_DWPG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 2878
swis2-VHDL20_DWPG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:12 3048
swis2-VHDL20_DWPG_300400_COR-2512300400-dsw--0-ia5 30-Dec-2025 08:12:38 3263
swis2-VHDL20_DWPG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 3886
swis2-VHDL20_DWPH_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:06 4056
swis2-VHDL20_DWPH_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:07 4012
swis2-VHDL20_DWPH_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:00:12 3487
swis2-VHDL20_DWPH_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3639
swis2-VHDL20_DWPH_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:06 3691
swis2-VHDL20_DWPH_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3637
swis2-VHDL20_DWPH_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:00:12 3958
swis2-VHDL20_DWPH_300400_COR-2512300400-dsw--0-ia5 30-Dec-2025 08:14:25 4349
swis2-VHDL20_DWPH_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 4695
swis2-VHDL20_DWSG_281800-2512281800-dsw--0-ia5 28-Dec-2025 19:45:02 3484
swis2-VHDL20_DWSG_290200-2512290200-dsw--0-ia5 29-Dec-2025 03:45:05 3771
swis2-VHDL20_DWSG_290400-2512290400-dsw--0-ia5 29-Dec-2025 06:15:02 3842
swis2-VHDL20_DWSG_290800-2512290800-dsw--0-ia5 29-Dec-2025 09:45:02 3848
swis2-VHDL20_DWSG_291300-2512291300-dsw--0-ia5 29-Dec-2025 14:45:06 3857
swis2-VHDL20_DWSG_291800-2512291800-dsw--0-ia5 29-Dec-2025 19:45:01 3325
swis2-VHDL20_DWSG_300200-2512300200-dsw--0-ia5 30-Dec-2025 03:45:02 3916
swis2-VHDL20_DWSG_300400-2512300400-dsw--0-ia5 30-Dec-2025 06:15:01 3854
swis2-VHDL20_DWSG_300800-2512300800-dsw--0-ia5 30-Dec-2025 09:45:02 3766
swis2-VHDL20_DWSG_301300-2512301300-dsw--0-ia5 30-Dec-2025 14:45:02 3451
wst04-VHDL20_DWEG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 224793
wst04-VHDL20_DWEG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 225738
wst04-VHDL20_DWEG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:27 225190
wst04-VHDL20_DWEG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:22 228288
wst04-VHDL20_DWEG_290800_COR-2512290800-omedes-..> 29-Dec-2025 15:16:41 228083
wst04-VHDL20_DWEG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:22 226594
wst04-VHDL20_DWEG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:16 227460
wst04-VHDL20_DWEG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:16 227307
wst04-VHDL20_DWEG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:21 228791
wst04-VHDL20_DWEG_300800_COR-2512300800-omedes-..> 30-Dec-2025 09:37:42 227212
wst04-VHDL20_DWEH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 223647
wst04-VHDL20_DWEH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 224502
wst04-VHDL20_DWEH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:21 223972
wst04-VHDL20_DWEH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:22 225293
wst04-VHDL20_DWEH_290800_COR-2512290800-omedes-..> 29-Dec-2025 15:16:41 225240
wst04-VHDL20_DWEH_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:16 224311
wst04-VHDL20_DWEH_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:16 225186
wst04-VHDL20_DWEH_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:22 224556
wst04-VHDL20_DWEH_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:21 223119
wst04-VHDL20_DWEH_300800_COR-2512300800-omedes-..> 30-Dec-2025 09:37:42 221981
wst04-VHDL20_DWEI_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 305473
wst04-VHDL20_DWEI_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 306445
wst04-VHDL20_DWEI_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:27 306577
wst04-VHDL20_DWEI_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 307938
wst04-VHDL20_DWEI_290800_COR-2512290800-omedes-..> 29-Dec-2025 15:16:47 308048
wst04-VHDL20_DWEI_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:22 306899
wst04-VHDL20_DWEI_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:16 307231
wst04-VHDL20_DWEI_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:26 307159
wst04-VHDL20_DWEI_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:27 309557
wst04-VHDL20_DWEI_300800_COR-2512300800-omedes-..> 30-Dec-2025 09:37:42 308379
wst04-VHDL20_DWHG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 297752
wst04-VHDL20_DWHG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 298747
wst04-VHDL20_DWHG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:12 298707
wst04-VHDL20_DWHG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 313645
wst04-VHDL20_DWHG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:12 311830
wst04-VHDL20_DWHG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:13 310956
wst04-VHDL20_DWHG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:12 310800
wst04-VHDL20_DWHG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:17 312225
wst04-VHDL20_DWHH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 300714
wst04-VHDL20_DWHH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 301475
wst04-VHDL20_DWHH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:12 301586
wst04-VHDL20_DWHH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 305042
wst04-VHDL20_DWHH_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:12 305037
wst04-VHDL20_DWHH_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:13 303998
wst04-VHDL20_DWHH_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:12 303930
wst04-VHDL20_DWHH_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:12 307295
wst04-VHDL20_DWLG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:26 297613
wst04-VHDL20_DWLG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 298740
wst04-VHDL20_DWLG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 297842
wst04-VHDL20_DWLG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 305877
wst04-VHDL20_DWLG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:26 306106
wst04-VHDL20_DWLG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:21 305741
wst04-VHDL20_DWLG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:44 305853
wst04-VHDL20_DWLG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:27 305937
wst04-VHDL20_DWLH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 294264
wst04-VHDL20_DWLH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 295793
wst04-VHDL20_DWLH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 295049
wst04-VHDL20_DWLH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 300762
wst04-VHDL20_DWLH_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:26 300394
wst04-VHDL20_DWLH_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:27 300979
wst04-VHDL20_DWLH_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:44 301225
wst04-VHDL20_DWLH_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:31 299268
wst04-VHDL20_DWLI_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 291905
wst04-VHDL20_DWLI_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 292815
wst04-VHDL20_DWLI_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:42 292144
wst04-VHDL20_DWLI_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 298801
wst04-VHDL20_DWLI_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:22 298636
wst04-VHDL20_DWLI_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:21 299439
wst04-VHDL20_DWLI_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:44 299856
wst04-VHDL20_DWLI_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:31 298773
wst04-VHDL20_DWMG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 491780
wst04-VHDL20_DWMG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 493694
wst04-VHDL20_DWMG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 493732
wst04-VHDL20_DWMG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 499639
wst04-VHDL20_DWMG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:16 498763
wst04-VHDL20_DWMG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:21 499224
wst04-VHDL20_DWMG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:22 498877
wst04-VHDL20_DWMG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:17 503253
wst04-VHDL20_DWMO_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 393069
wst04-VHDL20_DWMO_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:21 394787
wst04-VHDL20_DWMO_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 395332
wst04-VHDL20_DWMO_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:15 401778
wst04-VHDL20_DWMO_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:12 400480
wst04-VHDL20_DWMO_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:16 400803
wst04-VHDL20_DWMO_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:16 401340
wst04-VHDL20_DWMO_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:12 402275
wst04-VHDL20_DWMP_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:16 507919
wst04-VHDL20_DWMP_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:17 508331
wst04-VHDL20_DWMP_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:17 509555
wst04-VHDL20_DWMP_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:19 518559
wst04-VHDL20_DWMP_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:16 517371
wst04-VHDL20_DWMP_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:21 516786
wst04-VHDL20_DWMP_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:22 517839
wst04-VHDL20_DWMP_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:17 520887
wst04-VHDL20_DWPG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:26 302052
wst04-VHDL20_DWPG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:27 302189
wst04-VHDL20_DWPG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:31 301747
wst04-VHDL20_DWPG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:27 355809
wst04-VHDL20_DWPG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:22 311424
wst04-VHDL20_DWPG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:27 311730
wst04-VHDL20_DWPG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:32 310577
wst04-VHDL20_DWPG_300400_COR-2512300400-omedes-..> 30-Dec-2025 08:49:01 310972
wst04-VHDL20_DWPG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:31 346001
wst04-VHDL20_DWPH_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:22 271505
wst04-VHDL20_DWPH_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:27 226494
wst04-VHDL20_DWPH_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:00:31 225088
wst04-VHDL20_DWPH_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:33 272605
wst04-VHDL20_DWPH_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:22 272833
wst04-VHDL20_DWPH_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:21 226799
wst04-VHDL20_DWPH_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:00:32 226899
wst04-VHDL20_DWPH_300400_COR-2512300400-omedes-..> 30-Dec-2025 08:49:43 228323
wst04-VHDL20_DWPH_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:27 273275
wst04-VHDL20_DWSG_281800-2512281800-omedes--0.pdf 28-Dec-2025 19:45:12 318651
wst04-VHDL20_DWSG_290200-2512290200-omedes--0.pdf 29-Dec-2025 03:45:11 319767
wst04-VHDL20_DWSG_290400-2512290400-omedes--0.pdf 29-Dec-2025 06:15:11 319912
wst04-VHDL20_DWSG_290800-2512290800-omedes--0.pdf 29-Dec-2025 09:45:15 315300
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wst04-VHDL20_DWSG_291800-2512291800-omedes--0.pdf 29-Dec-2025 19:45:12 315078
wst04-VHDL20_DWSG_300200-2512300200-omedes--0.pdf 30-Dec-2025 03:45:13 314715
wst04-VHDL20_DWSG_300400-2512300400-omedes--0.pdf 30-Dec-2025 06:15:16 314746
wst04-VHDL20_DWSG_300800-2512300800-omedes--0.pdf 30-Dec-2025 09:45:12 322309
wst04-VHDL20_DWSG_301300-2512301300-omedes--0.pdf 30-Dec-2025 14:45:12 322131