Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-May-2026 11:10:08 2739
FPDL13_DWMZ_200600 20-May-2026 13:25:19 3337
SXDL31_DWAV_190800 19-May-2026 08:00:54 10803
SXDL31_DWAV_191800 19-May-2026 16:40:15 4426
SXDL31_DWAV_200800 20-May-2026 07:44:35 11517
SXDL31_DWAV_201800 20-May-2026 15:47:31 5638
SXDL31_DWAV_LATEST 20-May-2026 15:47:31 5638
SXDL33_DWAV_190000 19-May-2026 10:46:25 9000
SXDL33_DWAV_200000 20-May-2026 10:00:07 9329
SXDL33_DWAV_LATEST 20-May-2026 10:00:07 9329
ber01-FWDL39_DWMS_191230-2605191230-dsw--0-ia5 19-May-2026 11:14:22 1444
ber01-FWDL39_DWMS_201230-2605201230-dsw--0-ia5 20-May-2026 07:45:56 1306
ber01-VHDL13_DWEG_190800-2605190800-dsw--0-ia5 19-May-2026 08:28:17 3369
ber01-VHDL13_DWEG_200800-2605200800-dsw--0-ia5 20-May-2026 08:28:17 2953
ber01-VHDL13_DWEH_190800-2605190800-dsw--0-ia5 19-May-2026 08:28:17 3170
ber01-VHDL13_DWEH_200800-2605200800-dsw--0-ia5 20-May-2026 08:28:11 2913
ber01-VHDL13_DWEI_190800-2605190800-dsw--0-ia5 19-May-2026 08:28:17 3047
ber01-VHDL13_DWEI_200800-2605200800-dsw--0-ia5 20-May-2026 08:28:17 2873
ber01-VHDL13_DWHG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:06 2832
ber01-VHDL13_DWHG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 2706
ber01-VHDL13_DWHH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:06 2816
ber01-VHDL13_DWHH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 2878
ber01-VHDL13_DWLG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2373
ber01-VHDL13_DWLG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2120
ber01-VHDL13_DWLH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2276
ber01-VHDL13_DWLH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2197
ber01-VHDL13_DWLI_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2287
ber01-VHDL13_DWLI_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2129
ber01-VHDL13_DWMO_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2902
ber01-VHDL13_DWMO_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 2660
ber01-VHDL13_DWMP_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 3118
ber01-VHDL13_DWMP_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 2841
ber01-VHDL13_DWOG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 3370
ber01-VHDL13_DWOG_191700-2605191700-dsw--0-ia5 19-May-2026 18:00:01 3346
ber01-VHDL13_DWOG_191700_COR-2605191700-dsw--0-ia5 19-May-2026 20:08:31 2903
ber01-VHDL13_DWOG_200300-2605200300-dsw--0-ia5 20-May-2026 03:00:06 3427
ber01-VHDL13_DWOG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 3027
ber01-VHDL13_DWOG_201700-2605201700-dsw--0-ia5 20-May-2026 18:00:00 2505
ber01-VHDL13_DWOG_210300-2605210300-dsw--0-ia5 21-May-2026 03:00:02 2533
ber01-VHDL13_DWON_190529-2605190529-dsw--0-ia5 19-May-2026 05:29:51 3521
ber01-VHDL13_DWON_190620-2605190620-dsw--0-ia5 19-May-2026 06:20:21 3331
ber01-VHDL13_DWON_190747-2605190747-dsw--0-ia5 19-May-2026 07:47:57 3331
ber01-VHDL13_DWON_191055-2605191055-dsw--0-ia5 19-May-2026 10:55:52 3194
ber01-VHDL13_DWON_191421-2605191421-dsw--0-ia5 19-May-2026 14:21:26 3395
ber01-VHDL13_DWON_191424-2605191424-dsw--0-ia5 19-May-2026 14:24:36 3413
ber01-VHDL13_DWON_191643-2605191643-dsw--0-ia5 19-May-2026 16:43:42 3412
ber01-VHDL13_DWON_192008-2605192008-dsw--0-ia5 19-May-2026 20:08:07 2939
ber01-VHDL13_DWON_200159-2605200159-dsw--0-ia5 20-May-2026 01:59:31 3570
ber01-VHDL13_DWON_200529-2605200529-dsw--0-ia5 20-May-2026 05:29:27 3253
ber01-VHDL13_DWON_200607-2605200607-dsw--0-ia5 20-May-2026 06:07:17 3159
ber01-VHDL13_DWON_201227-2605201227-dsw--0-ia5 20-May-2026 12:27:27 2891
ber01-VHDL13_DWON_201425-2605201425-dsw--0-ia5 20-May-2026 14:25:26 3193
ber01-VHDL13_DWON_201427-2605201427-dsw--0-ia5 20-May-2026 14:27:37 3191
ber01-VHDL13_DWON_201703-2605201703-dsw--0-ia5 20-May-2026 17:03:11 2729
ber01-VHDL13_DWON_202155-2605202155-dsw--0-ia5 20-May-2026 21:55:54 2715
ber01-VHDL13_DWON_202212-2605202212-dsw--0-ia5 20-May-2026 22:12:11 3076
ber01-VHDL13_DWON_210037-2605210037-dsw--0-ia5 21-May-2026 00:37:58 2714
ber01-VHDL13_DWON_210038-2605210038-dsw--0-ia5 21-May-2026 00:38:56 2714
ber01-VHDL13_DWPG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2412
ber01-VHDL13_DWPG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2094
ber01-VHDL13_DWPH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2540
ber01-VHDL13_DWPH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2214
ber01-VHDL13_DWSG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 2893
ber01-VHDL13_DWSG_190800_COR-2605190800-dsw--0-ia5 19-May-2026 09:12:52 2809
ber01-VHDL13_DWSG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 2805
ber01-VHDL17_DWOG_191200-2605191200-dsw--0-ia5 19-May-2026 11:06:47 2306
ber01-VHDL17_DWOG_201200-2605201200-dsw--0-ia5 20-May-2026 11:20:27 2529
swis2-VHDL20_DWEG_190400-2605190400-dsw--0-ia5 19-May-2026 05:01:22 1583
swis2-VHDL20_DWEG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:03 1735
swis2-VHDL20_DWEG_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1409
swis2-VHDL20_DWEG_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:06 1288
swis2-VHDL20_DWEG_200400-2605200400-dsw--0-ia5 20-May-2026 05:01:21 1297
swis2-VHDL20_DWEG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 1491
swis2-VHDL20_DWEG_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 1006
swis2-VHDL20_DWEG_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:07 821
swis2-VHDL20_DWEH_190400-2605190400-dsw--0-ia5 19-May-2026 05:01:22 1270
swis2-VHDL20_DWEH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:03 1261
swis2-VHDL20_DWEH_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1357
swis2-VHDL20_DWEH_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:06 1143
swis2-VHDL20_DWEH_200400-2605200400-dsw--0-ia5 20-May-2026 05:01:21 1161
swis2-VHDL20_DWEH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 1325
swis2-VHDL20_DWEH_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 1027
swis2-VHDL20_DWEH_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:07 761
swis2-VHDL20_DWEI_190400-2605190400-dsw--0-ia5 19-May-2026 05:01:22 1477
swis2-VHDL20_DWEI_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:03 1608
swis2-VHDL20_DWEI_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1457
swis2-VHDL20_DWEI_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:06 1336
swis2-VHDL20_DWEI_200400-2605200400-dsw--0-ia5 20-May-2026 05:01:21 1346
swis2-VHDL20_DWEI_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 1540
swis2-VHDL20_DWEI_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 1031
swis2-VHDL20_DWEI_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:07 846
swis2-VHDL20_DWHG_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:17 1348
swis2-VHDL20_DWHG_190800-2605190800-dsw--0-ia5 19-May-2026 08:45:17 1516
swis2-VHDL20_DWHG_191800-2605191800-dsw--0-ia5 19-May-2026 18:45:07 1514
swis2-VHDL20_DWHG_200200-2605200200-dsw--0-ia5 20-May-2026 02:45:21 1339
swis2-VHDL20_DWHG_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:17 1336
swis2-VHDL20_DWHG_200800-2605200800-dsw--0-ia5 20-May-2026 08:45:07 1719
swis2-VHDL20_DWHG_201800-2605201800-dsw--0-ia5 20-May-2026 18:45:02 1483
swis2-VHDL20_DWHG_210200-2605210200-dsw--0-ia5 21-May-2026 02:45:07 983
swis2-VHDL20_DWHH_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:17 1360
swis2-VHDL20_DWHH_190800-2605190800-dsw--0-ia5 19-May-2026 08:45:17 1481
swis2-VHDL20_DWHH_191800-2605191800-dsw--0-ia5 19-May-2026 18:45:07 1519
swis2-VHDL20_DWHH_200200-2605200200-dsw--0-ia5 20-May-2026 02:45:21 1341
swis2-VHDL20_DWHH_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:17 1341
swis2-VHDL20_DWHH_200800-2605200800-dsw--0-ia5 20-May-2026 08:45:07 1688
swis2-VHDL20_DWHH_201800-2605201800-dsw--0-ia5 20-May-2026 18:45:02 1455
swis2-VHDL20_DWHH_210200-2605210200-dsw--0-ia5 21-May-2026 02:45:07 984
swis2-VHDL20_DWLG_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:11 985
swis2-VHDL20_DWLG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:25 1118
swis2-VHDL20_DWLG_191800-2605191800-dsw--0-ia5 19-May-2026 18:31:03 953
swis2-VHDL20_DWLG_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:22 910
swis2-VHDL20_DWLG_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:11 846
swis2-VHDL20_DWLG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:22 917
swis2-VHDL20_DWLG_201800-2605201800-dsw--0-ia5 20-May-2026 18:31:07 837
swis2-VHDL20_DWLG_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:21 925
swis2-VHDL20_DWLH_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:11 948
swis2-VHDL20_DWLH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:25 1081
swis2-VHDL20_DWLH_191800-2605191800-dsw--0-ia5 19-May-2026 18:31:03 961
swis2-VHDL20_DWLH_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:22 918
swis2-VHDL20_DWLH_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:11 854
swis2-VHDL20_DWLH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:22 925
swis2-VHDL20_DWLH_201800-2605201800-dsw--0-ia5 20-May-2026 18:31:07 844
swis2-VHDL20_DWLH_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:21 930
swis2-VHDL20_DWLI_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:11 943
swis2-VHDL20_DWLI_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:25 1076
swis2-VHDL20_DWLI_191800-2605191800-dsw--0-ia5 19-May-2026 18:31:03 956
swis2-VHDL20_DWLI_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:22 913
swis2-VHDL20_DWLI_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:11 849
swis2-VHDL20_DWLI_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:22 920
swis2-VHDL20_DWLI_201800-2605201800-dsw--0-ia5 20-May-2026 18:31:07 839
swis2-VHDL20_DWLI_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:21 930
swis2-VHDL20_DWMO_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:07 1308
swis2-VHDL20_DWMO_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 1342
swis2-VHDL20_DWMO_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1316
swis2-VHDL20_DWMO_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:06 1065
swis2-VHDL20_DWMO_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:07 1060
swis2-VHDL20_DWMO_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 1229
swis2-VHDL20_DWMO_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 1107
swis2-VHDL20_DWMO_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:01 913
swis2-VHDL20_DWMP_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:07 1298
swis2-VHDL20_DWMP_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 1361
swis2-VHDL20_DWMP_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1319
swis2-VHDL20_DWMP_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:06 1140
swis2-VHDL20_DWMP_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:07 1119
swis2-VHDL20_DWMP_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:07 1303
swis2-VHDL20_DWMP_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 1229
swis2-VHDL20_DWMP_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:01 907
swis2-VHDL20_DWPG_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:11 1064
swis2-VHDL20_DWPG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:25 1197
swis2-VHDL20_DWPG_191800-2605191800-dsw--0-ia5 19-May-2026 18:31:03 974
swis2-VHDL20_DWPG_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:22 928
swis2-VHDL20_DWPG_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:11 864
swis2-VHDL20_DWPG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:22 935
swis2-VHDL20_DWPG_201800-2605201800-dsw--0-ia5 20-May-2026 18:31:07 1026
swis2-VHDL20_DWPG_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:21 821
swis2-VHDL20_DWPH_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:11 1072
swis2-VHDL20_DWPH_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:25 1205
swis2-VHDL20_DWPH_191800-2605191800-dsw--0-ia5 19-May-2026 18:31:03 973
swis2-VHDL20_DWPH_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:22 930
swis2-VHDL20_DWPH_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:11 866
swis2-VHDL20_DWPH_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:22 937
swis2-VHDL20_DWPH_201800-2605201800-dsw--0-ia5 20-May-2026 18:31:07 995
swis2-VHDL20_DWPH_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:21 824
swis2-VHDL20_DWSG_190400-2605190400-dsw--0-ia5 19-May-2026 05:00:17 1359
swis2-VHDL20_DWSG_190800-2605190800-dsw--0-ia5 19-May-2026 08:30:01 1322
swis2-VHDL20_DWSG_190800_COR-2605190800-dsw--0-ia5 19-May-2026 09:12:52 1277
swis2-VHDL20_DWSG_191800-2605191800-dsw--0-ia5 19-May-2026 18:30:02 1222
swis2-VHDL20_DWSG_200200-2605200200-dsw--0-ia5 20-May-2026 02:30:01 1115
swis2-VHDL20_DWSG_200400-2605200400-dsw--0-ia5 20-May-2026 05:00:17 1255
swis2-VHDL20_DWSG_200800-2605200800-dsw--0-ia5 20-May-2026 08:30:03 1378
swis2-VHDL20_DWSG_201800-2605201800-dsw--0-ia5 20-May-2026 18:30:04 917
swis2-VHDL20_DWSG_210200-2605210200-dsw--0-ia5 21-May-2026 02:30:07 831
wst04-VHDL20_DWEG_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:11 236357
wst04-VHDL20_DWEG_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:11 237893
wst04-VHDL20_DWEG_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:13 236471
wst04-VHDL20_DWEG_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:12 235295
wst04-VHDL20_DWEG_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:11 235131
wst04-VHDL20_DWEG_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:12 235648
wst04-VHDL20_DWEG_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:17 235644
wst04-VHDL20_DWEG_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:11 234401
wst04-VHDL20_DWEH_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:11 238226
wst04-VHDL20_DWEH_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:11 238922
wst04-VHDL20_DWEH_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:13 235401
wst04-VHDL20_DWEH_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:12 234461
wst04-VHDL20_DWEH_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:11 234599
wst04-VHDL20_DWEH_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:12 235139
wst04-VHDL20_DWEH_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:17 234571
wst04-VHDL20_DWEH_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:11 233200
wst04-VHDL20_DWEI_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:11 336618
wst04-VHDL20_DWEI_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:11 338768
wst04-VHDL20_DWEI_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:18 335030
wst04-VHDL20_DWEI_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:12 333738
wst04-VHDL20_DWEI_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:17 333517
wst04-VHDL20_DWEI_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:16 334209
wst04-VHDL20_DWEI_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:17 334027
wst04-VHDL20_DWEI_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:16 333306
wst04-VHDL20_DWHG_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:17 345735
wst04-VHDL20_DWHG_190800-2605190800-omedes--0.pdf 19-May-2026 08:45:17 346887
wst04-VHDL20_DWHG_191800-2605191800-omedes--0.pdf 19-May-2026 18:45:11 341257
wst04-VHDL20_DWHG_200200-2605200200-omedes--0.pdf 20-May-2026 02:45:21 339406
wst04-VHDL20_DWHG_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:17 339212
wst04-VHDL20_DWHG_200800-2605200800-omedes--0.pdf 20-May-2026 08:45:10 341394
wst04-VHDL20_DWHG_201800-2605201800-omedes--0.pdf 20-May-2026 18:45:12 344964
wst04-VHDL20_DWHG_210200-2605210200-omedes--0.pdf 21-May-2026 02:45:11 342974
wst04-VHDL20_DWHH_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:17 228471
wst04-VHDL20_DWHH_190800-2605190800-omedes--0.pdf 19-May-2026 08:45:17 338139
wst04-VHDL20_DWHH_191800-2605191800-omedes--0.pdf 19-May-2026 18:45:11 329523
wst04-VHDL20_DWHH_200200-2605200200-omedes--0.pdf 20-May-2026 02:45:21 328657
wst04-VHDL20_DWHH_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:17 226351
wst04-VHDL20_DWHH_200800-2605200800-omedes--0.pdf 20-May-2026 08:45:10 329975
wst04-VHDL20_DWHH_201800-2605201800-omedes--0.pdf 20-May-2026 18:45:12 330766
wst04-VHDL20_DWHH_210200-2605210200-omedes--0.pdf 21-May-2026 02:45:11 329625
wst04-VHDL20_DWLG_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:41 340877
wst04-VHDL20_DWLG_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:50 341097
wst04-VHDL20_DWLG_191800-2605191800-omedes--0.pdf 19-May-2026 18:31:22 340152
wst04-VHDL20_DWLG_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:22 339331
wst04-VHDL20_DWLG_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:41 339284
wst04-VHDL20_DWLG_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:42 339469
wst04-VHDL20_DWLG_201800-2605201800-omedes--0.pdf 20-May-2026 18:31:27 331552
wst04-VHDL20_DWLG_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:21 332227
wst04-VHDL20_DWLH_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:41 341247
wst04-VHDL20_DWLH_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:44 341479
wst04-VHDL20_DWLH_191800-2605191800-omedes--0.pdf 19-May-2026 18:31:22 334949
wst04-VHDL20_DWLH_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:22 334153
wst04-VHDL20_DWLH_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:41 334081
wst04-VHDL20_DWLH_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:42 334277
wst04-VHDL20_DWLH_201800-2605201800-omedes--0.pdf 20-May-2026 18:31:22 329297
wst04-VHDL20_DWLH_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:21 329995
wst04-VHDL20_DWLI_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:41 341319
wst04-VHDL20_DWLI_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:44 386137
wst04-VHDL20_DWLI_191800-2605191800-omedes--0.pdf 19-May-2026 18:31:25 340318
wst04-VHDL20_DWLI_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:28 339513
wst04-VHDL20_DWLI_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:41 339430
wst04-VHDL20_DWLI_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:42 384205
wst04-VHDL20_DWLI_201800-2605201800-omedes--0.pdf 20-May-2026 18:31:27 333669
wst04-VHDL20_DWLI_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:21 334380
wst04-VHDL20_DWMO_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:17 460473
wst04-VHDL20_DWMO_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:17 460740
wst04-VHDL20_DWMO_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:15 357439
wst04-VHDL20_DWMO_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:17 467178
wst04-VHDL20_DWMO_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:17 467164
wst04-VHDL20_DWMO_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:16 467047
wst04-VHDL20_DWMO_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:22 340977
wst04-VHDL20_DWMO_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:16 449570
wst04-VHDL20_DWMP_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:17 586969
wst04-VHDL20_DWMP_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:21 480638
wst04-VHDL20_DWMP_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:15 477400
wst04-VHDL20_DWMP_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:17 583326
wst04-VHDL20_DWMP_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:21 582524
wst04-VHDL20_DWMP_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:22 476494
wst04-VHDL20_DWMP_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:22 474905
wst04-VHDL20_DWMP_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:16 573893
wst04-VHDL20_DWPG_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:31 344650
wst04-VHDL20_DWPG_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:44 389426
wst04-VHDL20_DWPG_191800-2605191800-omedes--0.pdf 19-May-2026 18:31:22 341188
wst04-VHDL20_DWPG_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:22 240189
wst04-VHDL20_DWPG_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:31 340350
wst04-VHDL20_DWPG_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:50 385049
wst04-VHDL20_DWPG_201800-2605201800-omedes--0.pdf 20-May-2026 18:31:22 339990
wst04-VHDL20_DWPG_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:27 240000
wst04-VHDL20_DWPH_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:31 244081
wst04-VHDL20_DWPH_190800-2605190800-omedes--0.pdf 19-May-2026 08:30:44 244275
wst04-VHDL20_DWPH_191800-2605191800-omedes--0.pdf 19-May-2026 18:31:22 240794
wst04-VHDL20_DWPH_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:22 240025
wst04-VHDL20_DWPH_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:31 240002
wst04-VHDL20_DWPH_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:42 240096
wst04-VHDL20_DWPH_201800-2605201800-omedes--0.pdf 20-May-2026 18:31:22 237092
wst04-VHDL20_DWPH_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:21 236538
wst04-VHDL20_DWSG_190400-2605190400-omedes--0.pdf 19-May-2026 05:00:11 346385
wst04-VHDL20_DWSG_190800-2605190800-omedes--0.pdf 19-May-2026 09:12:56 346552
wst04-VHDL20_DWSG_191800-2605191800-omedes--0.pdf 19-May-2026 18:30:18 346586
wst04-VHDL20_DWSG_200200-2605200200-omedes--0.pdf 20-May-2026 02:30:12 345965
wst04-VHDL20_DWSG_200400-2605200400-omedes--0.pdf 20-May-2026 05:00:11 346351
wst04-VHDL20_DWSG_200800-2605200800-omedes--0.pdf 20-May-2026 08:30:16 346178
wst04-VHDL20_DWSG_201800-2605201800-omedes--0.pdf 20-May-2026 18:30:17 336030
wst04-VHDL20_DWSG_210200-2605210200-omedes--0.pdf 21-May-2026 02:30:11 335986