Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Jun-2026 11:58:23 3633
FPDL13_DWMZ_120600 12-Jun-2026 12:43:44 4546
SXDL31_DWAV_110800 11-Jun-2026 06:59:40 15903
SXDL31_DWAV_111800 11-Jun-2026 16:30:55 6944
SXDL31_DWAV_120800 12-Jun-2026 08:05:50 13214
SXDL31_DWAV_121800 12-Jun-2026 16:56:23 4838
SXDL31_DWAV_LATEST 12-Jun-2026 16:56:23 4838
SXDL33_DWAV_110000 11-Jun-2026 10:04:10 9967
SXDL33_DWAV_120000 12-Jun-2026 09:56:59 10435
SXDL33_DWAV_LATEST 12-Jun-2026 09:56:59 10435
ber01-FWDL39_DWMS_111200-2606111200-dsw--0-ia5 11-Jun-2026 12:54:56 1845
ber01-FWDL39_DWMS_121200-2606121200-dsw--0-ia5 12-Jun-2026 11:06:37 1648
ber01-VHDL13_DWEG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2795
ber01-VHDL13_DWEG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:16 2808
ber01-VHDL13_DWEH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2758
ber01-VHDL13_DWEH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:12 2695
ber01-VHDL13_DWEI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:28:17 2671
ber01-VHDL13_DWEI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:28:16 2644
ber01-VHDL13_DWHG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 3038
ber01-VHDL13_DWHG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:08 3125
ber01-VHDL13_DWHH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 2861
ber01-VHDL13_DWHH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:08 3102
ber01-VHDL13_DWLG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2783
ber01-VHDL13_DWLG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2393
ber01-VHDL13_DWLH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2869
ber01-VHDL13_DWLH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2689
ber01-VHDL13_DWLI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2638
ber01-VHDL13_DWLI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2240
ber01-VHDL13_DWMO_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 3121
ber01-VHDL13_DWMO_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3207
ber01-VHDL13_DWMP_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 3679
ber01-VHDL13_DWMP_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3445
ber01-VHDL13_DWOG_101700-2606101700-dsw--0-ia5 10-Jun-2026 18:00:01 3050
ber01-VHDL13_DWOG_110300-2606110300-dsw--0-ia5 11-Jun-2026 03:00:09 3261
ber01-VHDL13_DWOG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:07 2935
ber01-VHDL13_DWOG_111700-2606111700-dsw--0-ia5 11-Jun-2026 18:00:02 3149
ber01-VHDL13_DWOG_120300-2606120300-dsw--0-ia5 12-Jun-2026 03:00:06 3498
ber01-VHDL13_DWOG_120800-2606120800-dsw--0-ia5 12-Jun-2026 09:28:11 4759
ber01-VHDL13_DWON_101752-2606101752-dsw--0-ia5 10-Jun-2026 17:52:38 2578
ber01-VHDL13_DWON_101755-2606101755-dsw--0-ia5 10-Jun-2026 17:55:12 2578
ber01-VHDL13_DWON_101908-2606101908-dsw--0-ia5 10-Jun-2026 19:08:22 2534
ber01-VHDL13_DWON_102231-2606102231-dsw--0-ia5 10-Jun-2026 22:31:41 2821
ber01-VHDL13_DWON_110023-2606110023-dsw--0-ia5 11-Jun-2026 00:23:06 2821
ber01-VHDL13_DWON_110133-2606110133-dsw--0-ia5 11-Jun-2026 01:33:16 2821
ber01-VHDL13_DWON_110508-2606110508-dsw--0-ia5 11-Jun-2026 05:08:11 3085
ber01-VHDL13_DWON_110600-2606110600-dsw--0-ia5 11-Jun-2026 06:00:56 3071
ber01-VHDL13_DWON_110807-2606110807-dsw--0-ia5 11-Jun-2026 08:07:16 3199
ber01-VHDL13_DWON_110907-2606110907-dsw--0-ia5 11-Jun-2026 09:07:50 3199
ber01-VHDL13_DWON_111431-2606111431-dsw--0-ia5 11-Jun-2026 14:31:44 3139
ber01-VHDL13_DWON_111434-2606111434-dsw--0-ia5 11-Jun-2026 14:34:52 3152
ber01-VHDL13_DWON_111638-2606111638-dsw--0-ia5 11-Jun-2026 16:38:42 2717
ber01-VHDL13_DWON_111939-2606111939-dsw--0-ia5 11-Jun-2026 19:39:17 2620
ber01-VHDL13_DWON_120130-2606120130-dsw--0-ia5 12-Jun-2026 01:30:51 2914
ber01-VHDL13_DWON_120251-2606120251-dsw--0-ia5 12-Jun-2026 02:51:32 2914
ber01-VHDL13_DWON_120530-2606120530-dsw--0-ia5 12-Jun-2026 05:30:14 3296
ber01-VHDL13_DWON_120559-2606120559-dsw--0-ia5 12-Jun-2026 05:59:26 3936
ber01-VHDL13_DWON_120624-2606120624-dsw--0-ia5 12-Jun-2026 06:25:02 3962
ber01-VHDL13_DWON_120926-2606120926-dsw--0-ia5 12-Jun-2026 09:26:36 3938
ber01-VHDL13_DWON_121430-2606121430-dsw--0-ia5 12-Jun-2026 14:30:22 3866
ber01-VHDL13_DWON_121702-2606121702-dsw--0-ia5 12-Jun-2026 17:02:16 3855
ber01-VHDL13_DWPG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 2420
ber01-VHDL13_DWPG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2334
ber01-VHDL13_DWPH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 3013
ber01-VHDL13_DWPH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 2741
ber01-VHDL13_DWSG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 3398
ber01-VHDL13_DWSG_110800_COR-2606110800-dsw--0-ia5 11-Jun-2026 11:55:32 3287
ber01-VHDL13_DWSG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 3123
ber01-VHDL17_DWOG_111200-2606111200-dsw--0-ia5 11-Jun-2026 10:58:30 3347
ber01-VHDL17_DWOG_121200-2606121200-dsw--0-ia5 12-Jun-2026 11:57:22 3430
swis2-VHDL20_DWEG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1418
swis2-VHDL20_DWEG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 986
swis2-VHDL20_DWEG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 983
swis2-VHDL20_DWEG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1169
swis2-VHDL20_DWEG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1218
swis2-VHDL20_DWEG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1009
swis2-VHDL20_DWEG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1141
swis2-VHDL20_DWEG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1323
swis2-VHDL20_DWEH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1464
swis2-VHDL20_DWEH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1007
swis2-VHDL20_DWEH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 1004
swis2-VHDL20_DWEH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1145
swis2-VHDL20_DWEH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1205
swis2-VHDL20_DWEH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1010
swis2-VHDL20_DWEH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1132
swis2-VHDL20_DWEH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1282
swis2-VHDL20_DWEI_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1301
swis2-VHDL20_DWEI_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 810
swis2-VHDL20_DWEI_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:01:22 1010
swis2-VHDL20_DWEI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1179
swis2-VHDL20_DWEI_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1174
swis2-VHDL20_DWEI_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:07 1034
swis2-VHDL20_DWEI_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:01:16 1135
swis2-VHDL20_DWEI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1248
swis2-VHDL20_DWHG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:45:02 1612
swis2-VHDL20_DWHG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:45:06 1553
swis2-VHDL20_DWHG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1550
swis2-VHDL20_DWHG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:45:01 1536
swis2-VHDL20_DWHG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:45:07 1711
swis2-VHDL20_DWHG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:45:01 1560
swis2-VHDL20_DWHG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1513
swis2-VHDL20_DWHG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:45:14 1513
swis2-VHDL20_DWHH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:45:02 1622
swis2-VHDL20_DWHH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:45:06 1564
swis2-VHDL20_DWHH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1564
swis2-VHDL20_DWHH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:45:01 1545
swis2-VHDL20_DWHH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:45:07 1758
swis2-VHDL20_DWHH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:45:01 1579
swis2-VHDL20_DWHH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1535
swis2-VHDL20_DWHH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:45:14 1568
swis2-VHDL20_DWLG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1117
swis2-VHDL20_DWLG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 969
swis2-VHDL20_DWLG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1046
swis2-VHDL20_DWLG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1232
swis2-VHDL20_DWLG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 933
swis2-VHDL20_DWLG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 723
swis2-VHDL20_DWLG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 711
swis2-VHDL20_DWLG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1085
swis2-VHDL20_DWLH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1226
swis2-VHDL20_DWLH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 1205
swis2-VHDL20_DWLH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1083
swis2-VHDL20_DWLH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1258
swis2-VHDL20_DWLH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 959
swis2-VHDL20_DWLH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 733
swis2-VHDL20_DWLH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1119
swis2-VHDL20_DWLH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1361
swis2-VHDL20_DWLI_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1012
swis2-VHDL20_DWLI_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 963
swis2-VHDL20_DWLI_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 935
swis2-VHDL20_DWLI_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1050
swis2-VHDL20_DWLI_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 848
swis2-VHDL20_DWLI_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 703
swis2-VHDL20_DWLI_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 810
swis2-VHDL20_DWLI_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 929
swis2-VHDL20_DWMO_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1424
swis2-VHDL20_DWMO_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1622
swis2-VHDL20_DWMO_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:02 1411
swis2-VHDL20_DWMO_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 1532
swis2-VHDL20_DWMO_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1238
swis2-VHDL20_DWMO_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1215
swis2-VHDL20_DWMO_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:07 1255
swis2-VHDL20_DWMO_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1361
swis2-VHDL20_DWMP_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1887
swis2-VHDL20_DWMP_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1876
swis2-VHDL20_DWMP_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:02 1834
swis2-VHDL20_DWMP_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:03 2021
swis2-VHDL20_DWMP_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1552
swis2-VHDL20_DWMP_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1414
swis2-VHDL20_DWMP_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:07 1478
swis2-VHDL20_DWMP_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1654
swis2-VHDL20_DWPG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1088
swis2-VHDL20_DWPG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 980
swis2-VHDL20_DWPG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 969
swis2-VHDL20_DWPG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1085
swis2-VHDL20_DWPG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 865
swis2-VHDL20_DWPG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 719
swis2-VHDL20_DWPG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 997
swis2-VHDL20_DWPG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1293
swis2-VHDL20_DWPH_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:31:01 1147
swis2-VHDL20_DWPH_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:22 1100
swis2-VHDL20_DWPH_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:12 1221
swis2-VHDL20_DWPH_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:24 1495
swis2-VHDL20_DWPH_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:31:00 1216
swis2-VHDL20_DWPH_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:24 925
swis2-VHDL20_DWPH_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1146
swis2-VHDL20_DWPH_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:23 1545
swis2-VHDL20_DWSG_101800-2606101800-dsw--0-ia5 10-Jun-2026 18:30:03 1254
swis2-VHDL20_DWSG_110200-2606110200-dsw--0-ia5 11-Jun-2026 02:30:02 1324
swis2-VHDL20_DWSG_110400-2606110400-dsw--0-ia5 11-Jun-2026 05:00:16 1339
swis2-VHDL20_DWSG_110800-2606110800-dsw--0-ia5 11-Jun-2026 08:30:01 1548
swis2-VHDL20_DWSG_110800_COR-2606110800-dsw--0-ia5 11-Jun-2026 11:55:32 1439
swis2-VHDL20_DWSG_111800-2606111800-dsw--0-ia5 11-Jun-2026 18:30:01 1239
swis2-VHDL20_DWSG_120200-2606120200-dsw--0-ia5 12-Jun-2026 02:30:01 1250
swis2-VHDL20_DWSG_120400-2606120400-dsw--0-ia5 12-Jun-2026 05:00:17 1252
swis2-VHDL20_DWSG_120800-2606120800-dsw--0-ia5 12-Jun-2026 08:30:02 1355
wst04-VHDL20_DWEG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:11 238121
wst04-VHDL20_DWEG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 237148
wst04-VHDL20_DWEG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 236984
wst04-VHDL20_DWEG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 237765
wst04-VHDL20_DWEG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 240787
wst04-VHDL20_DWEG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 239809
wst04-VHDL20_DWEG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 239754
wst04-VHDL20_DWEG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 240548
wst04-VHDL20_DWEH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:11 235860
wst04-VHDL20_DWEH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 235144
wst04-VHDL20_DWEH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 234709
wst04-VHDL20_DWEH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 235550
wst04-VHDL20_DWEH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:15 237440
wst04-VHDL20_DWEH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 236779
wst04-VHDL20_DWEH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 236924
wst04-VHDL20_DWEH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 237785
wst04-VHDL20_DWEI_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 337209
wst04-VHDL20_DWEI_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 335575
wst04-VHDL20_DWEI_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 335460
wst04-VHDL20_DWEI_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:11 335722
wst04-VHDL20_DWEI_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 342438
wst04-VHDL20_DWEI_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 342126
wst04-VHDL20_DWEI_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 341987
wst04-VHDL20_DWEI_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:13 342205
wst04-VHDL20_DWHG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:45:12 337511
wst04-VHDL20_DWHG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:45:19 335703
wst04-VHDL20_DWHG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 335492
wst04-VHDL20_DWHG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:45:11 337281
wst04-VHDL20_DWHG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:45:11 339105
wst04-VHDL20_DWHG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:45:11 337769
wst04-VHDL20_DWHG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 337492
wst04-VHDL20_DWHG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:45:14 338453
wst04-VHDL20_DWHH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:45:12 328202
wst04-VHDL20_DWHH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:45:19 327411
wst04-VHDL20_DWHH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 229591
wst04-VHDL20_DWHH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:45:11 327832
wst04-VHDL20_DWHH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:45:11 323544
wst04-VHDL20_DWHH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:45:11 322534
wst04-VHDL20_DWHH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 225554
wst04-VHDL20_DWHH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:45:14 322515
wst04-VHDL20_DWLG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 330600
wst04-VHDL20_DWLG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 330611
wst04-VHDL20_DWLG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 330322
wst04-VHDL20_DWLG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 330576
wst04-VHDL20_DWLG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 337876
wst04-VHDL20_DWLG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 337072
wst04-VHDL20_DWLG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 336629
wst04-VHDL20_DWLG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 337054
wst04-VHDL20_DWLH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 330035
wst04-VHDL20_DWLH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 329834
wst04-VHDL20_DWLH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 329336
wst04-VHDL20_DWLH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 329999
wst04-VHDL20_DWLH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:26 333901
wst04-VHDL20_DWLH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 332772
wst04-VHDL20_DWLH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 333064
wst04-VHDL20_DWLH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:46 333349
wst04-VHDL20_DWLI_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 325415
wst04-VHDL20_DWLI_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 325564
wst04-VHDL20_DWLI_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:41 325106
wst04-VHDL20_DWLI_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 369943
wst04-VHDL20_DWLI_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 338395
wst04-VHDL20_DWLI_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:30 337321
wst04-VHDL20_DWLI_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:41 337272
wst04-VHDL20_DWLI_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 382129
wst04-VHDL20_DWMO_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 345506
wst04-VHDL20_DWMO_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 450079
wst04-VHDL20_DWMO_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 449734
wst04-VHDL20_DWMO_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:17 449679
wst04-VHDL20_DWMO_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 349968
wst04-VHDL20_DWMO_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:17 456818
wst04-VHDL20_DWMO_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 457496
wst04-VHDL20_DWMO_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:19 457357
wst04-VHDL20_DWMP_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 469183
wst04-VHDL20_DWMP_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 572214
wst04-VHDL20_DWMP_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:16 572710
wst04-VHDL20_DWMP_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:24 469270
wst04-VHDL20_DWMP_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:20 470405
wst04-VHDL20_DWMP_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:17 579105
wst04-VHDL20_DWMP_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:17 579261
wst04-VHDL20_DWMP_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:23 471236
wst04-VHDL20_DWPG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 337932
wst04-VHDL20_DWPG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 238694
wst04-VHDL20_DWPG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:32 337555
wst04-VHDL20_DWPG_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 382338
wst04-VHDL20_DWPG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 335254
wst04-VHDL20_DWPG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 236917
wst04-VHDL20_DWPG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:31 335226
wst04-VHDL20_DWPG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 380155
wst04-VHDL20_DWPH_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:31:26 240394
wst04-VHDL20_DWPH_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:22 240680
wst04-VHDL20_DWPH_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:32 240326
wst04-VHDL20_DWPH_110800-2606110800-omedes--0.pdf 11-Jun-2026 08:30:46 240595
wst04-VHDL20_DWPH_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:31:21 239165
wst04-VHDL20_DWPH_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:24 238713
wst04-VHDL20_DWPH_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:31 239019
wst04-VHDL20_DWPH_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:43 239418
wst04-VHDL20_DWSG_101800-2606101800-omedes--0.pdf 10-Jun-2026 18:30:19 347715
wst04-VHDL20_DWSG_110200-2606110200-omedes--0.pdf 11-Jun-2026 02:30:18 347675
wst04-VHDL20_DWSG_110400-2606110400-omedes--0.pdf 11-Jun-2026 05:00:12 347737
wst04-VHDL20_DWSG_110800-2606110800-omedes--0.pdf 11-Jun-2026 11:55:36 347764
wst04-VHDL20_DWSG_111800-2606111800-omedes--0.pdf 11-Jun-2026 18:30:15 346524
wst04-VHDL20_DWSG_120200-2606120200-omedes--0.pdf 12-Jun-2026 02:30:12 346625
wst04-VHDL20_DWSG_120400-2606120400-omedes--0.pdf 12-Jun-2026 05:00:11 346651
wst04-VHDL20_DWSG_120800-2606120800-omedes--0.pdf 12-Jun-2026 08:30:19 346866