Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Mar-2026 11:56:35 2692
FPDL13_DWMZ_150600 15-Mar-2026 14:54:19 9442
SXDL31_DWAV_140800 14-Mar-2026 08:52:01 8044
SXDL31_DWAV_141800 14-Mar-2026 17:29:39 7365
SXDL31_DWAV_150800 15-Mar-2026 08:06:49 6881
SXDL31_DWAV_151800 15-Mar-2026 17:55:10 7760
SXDL31_DWAV_LATEST 15-Mar-2026 17:55:10 7760
SXDL33_DWAV_140000 14-Mar-2026 10:27:35 5585
SXDL33_DWAV_150000 15-Mar-2026 11:03:29 16330
SXDL33_DWAV_LATEST 15-Mar-2026 11:03:29 16330
ber01-FWDL39_DWMS_141230-2603141230-dsw--0-ia5 14-Mar-2026 12:52:23 1814
ber01-FWDL39_DWMS_151230-2603151230-dsw--0-ia5 15-Mar-2026 12:30:49 1360
ber01-VHDL13_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 3160
ber01-VHDL13_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:16 3115
ber01-VHDL13_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 3274
ber01-VHDL13_DWEH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:17 3256
ber01-VHDL13_DWEH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:17 3821
ber01-VHDL13_DWEH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:16 3679
ber01-VHDL13_DWEH_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:17 3136
ber01-VHDL13_DWEH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:17 3075
ber01-VHDL13_DWEH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:16 2782
ber01-VHDL13_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2869
ber01-VHDL13_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 2940
ber01-VHDL13_DWHG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2956
ber01-VHDL13_DWHG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2706
ber01-VHDL13_DWHG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 3565
ber01-VHDL13_DWHG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3565
ber01-VHDL13_DWHG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:10 4629
ber01-VHDL13_DWHG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:01:17 3882
ber01-VHDL13_DWHG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 3363
ber01-VHDL13_DWHH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2202
ber01-VHDL13_DWHH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:06 2236
ber01-VHDL13_DWHH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2273
ber01-VHDL13_DWHH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2301
ber01-VHDL13_DWHH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2804
ber01-VHDL13_DWHH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2804
ber01-VHDL13_DWHH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:10 3716
ber01-VHDL13_DWHH_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:01:41 3269
ber01-VHDL13_DWHH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2696
ber01-VHDL13_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2420
ber01-VHDL13_DWLG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2287
ber01-VHDL13_DWLG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2223
ber01-VHDL13_DWLG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1952
ber01-VHDL13_DWLG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2158
ber01-VHDL13_DWLG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2923
ber01-VHDL13_DWLG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3131
ber01-VHDL13_DWLG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2828
ber01-VHDL13_DWLH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2577
ber01-VHDL13_DWLH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2474
ber01-VHDL13_DWLH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2474
ber01-VHDL13_DWLH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2018
ber01-VHDL13_DWLH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2638
ber01-VHDL13_DWLH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2923
ber01-VHDL13_DWLH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3221
ber01-VHDL13_DWLH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2947
ber01-VHDL13_DWLI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2493
ber01-VHDL13_DWLI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2319
ber01-VHDL13_DWLI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2308
ber01-VHDL13_DWLI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2058
ber01-VHDL13_DWLI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2621
ber01-VHDL13_DWLI_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 2862
ber01-VHDL13_DWLI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2921
ber01-VHDL13_DWLI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2587
ber01-VHDL13_DWMG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3524
ber01-VHDL13_DWMG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3370
ber01-VHDL13_DWMG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 3370
ber01-VHDL13_DWMG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 3034
ber01-VHDL13_DWMG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2861
ber01-VHDL13_DWMG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2826
ber01-VHDL13_DWMG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2827
ber01-VHDL13_DWMG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2955
ber01-VHDL13_DWMO_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2937
ber01-VHDL13_DWMO_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2937
ber01-VHDL13_DWMO_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2861
ber01-VHDL13_DWMO_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2662
ber01-VHDL13_DWMO_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2580
ber01-VHDL13_DWMO_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2839
ber01-VHDL13_DWMO_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2890
ber01-VHDL13_DWMO_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2912
ber01-VHDL13_DWMP_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3613
ber01-VHDL13_DWMP_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 3593
ber01-VHDL13_DWMP_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 3240
ber01-VHDL13_DWMP_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 2865
ber01-VHDL13_DWMP_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 2837
ber01-VHDL13_DWMP_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2799
ber01-VHDL13_DWMP_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2717
ber01-VHDL13_DWMP_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2668
ber01-VHDL13_DWOG_140300-2603140300-dsw--0-ia5 14-Mar-2026 04:00:05 4603
ber01-VHDL13_DWOG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 4336
ber01-VHDL13_DWOG_141700-2603141700-dsw--0-ia5 14-Mar-2026 19:00:02 4064
ber01-VHDL13_DWOG_150300-2603150300-dsw--0-ia5 15-Mar-2026 04:00:06 4315
ber01-VHDL13_DWOG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3945
ber01-VHDL13_DWOG_151700-2603151700-dsw--0-ia5 15-Mar-2026 19:00:01 3605
ber01-VHDL13_DWOH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2819
ber01-VHDL13_DWOH_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:21 2676
ber01-VHDL13_DWOH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:13 2501
ber01-VHDL13_DWOH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:17 3396
ber01-VHDL13_DWOH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:12 3340
ber01-VHDL13_DWOH_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:11 3064
ber01-VHDL13_DWOH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:17 3025
ber01-VHDL13_DWOH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:16 2807
ber01-VHDL13_DWOI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:28:12 2824
ber01-VHDL13_DWOI_140400-2603140400-dsw--0-ia5 14-Mar-2026 05:58:12 2777
ber01-VHDL13_DWOI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:17 2723
ber01-VHDL13_DWOI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:28:13 2597
ber01-VHDL13_DWOI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:28:11 3558
ber01-VHDL13_DWOI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:28:12 3354
ber01-VHDL13_DWOI_150400-2603150400-dsw--0-ia5 15-Mar-2026 05:58:17 3062
ber01-VHDL13_DWOI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:11 3073
ber01-VHDL13_DWOI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:12 2861
ber01-VHDL13_DWON_140240-2603140240-dsw--0-ia5 14-Mar-2026 02:40:14 3438
ber01-VHDL13_DWON_140613-2603140613-dsw--0-ia5 14-Mar-2026 06:13:53 4314
ber01-VHDL13_DWON_140655-2603140655-dsw--0-ia5 14-Mar-2026 06:55:27 4314
ber01-VHDL13_DWON_140848-2603140848-dsw--0-ia5 14-Mar-2026 08:48:16 4192
ber01-VHDL13_DWON_140953-2603140953-dsw--0-ia5 14-Mar-2026 09:53:16 4192
ber01-VHDL13_DWON_141554-2603141554-dsw--0-ia5 14-Mar-2026 15:54:31 3733
ber01-VHDL13_DWON_141802-2603141802-dsw--0-ia5 14-Mar-2026 18:02:21 3496
ber01-VHDL13_DWON_150131-2603150131-dsw--0-ia5 15-Mar-2026 01:31:59 4068
ber01-VHDL13_DWON_150341-2603150341-dsw--0-ia5 15-Mar-2026 03:41:36 4068
ber01-VHDL13_DWON_150621-2603150621-dsw--0-ia5 15-Mar-2026 06:21:27 3742
ber01-VHDL13_DWON_150710-2603150710-dsw--0-ia5 15-Mar-2026 07:10:37 3741
ber01-VHDL13_DWON_150927-2603150927-dsw--0-ia5 15-Mar-2026 09:28:01 3741
ber01-VHDL13_DWON_150958-2603150958-dsw--0-ia5 15-Mar-2026 09:58:57 3741
ber01-VHDL13_DWON_151557-2603151557-dsw--0-ia5 15-Mar-2026 15:57:08 3818
ber01-VHDL13_DWON_151828-2603151828-dsw--0-ia5 15-Mar-2026 18:28:38 3164
ber01-VHDL13_DWPG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:15 2173
ber01-VHDL13_DWPG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2129
ber01-VHDL13_DWPG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2128
ber01-VHDL13_DWPG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1599
ber01-VHDL13_DWPG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 1946
ber01-VHDL13_DWPG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 1835
ber01-VHDL13_DWPG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2398
ber01-VHDL13_DWPG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2117
ber01-VHDL13_DWPH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 2130
ber01-VHDL13_DWPH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:01 2125
ber01-VHDL13_DWPH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:09 2125
ber01-VHDL13_DWPH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 1642
ber01-VHDL13_DWPH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 1924
ber01-VHDL13_DWPH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:02 1832
ber01-VHDL13_DWPH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2407
ber01-VHDL13_DWPH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2149
ber01-VHDL13_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:30:14 3628
ber01-VHDL13_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3780
ber01-VHDL13_DWSG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:30:02 3466
ber01-VHDL13_DWSG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:30:07 3094
ber01-VHDL13_DWSG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:30:07 3532
ber01-VHDL13_DWSG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3619
ber01-VHDL13_DWSG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3237
ber01-VHDL13_DWSG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 13:56:35 3641
ber01-VHDL13_DWSG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 3371
ber01-VHDL17_DWOG_141200-2603141200-dsw--0-ia5 14-Mar-2026 12:14:36 2747
ber01-VHDL17_DWOG_151200-2603151200-dsw--0-ia5 15-Mar-2026 13:11:17 3039
swis2-VHDL20_DWEG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3184
swis2-VHDL20_DWEG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3109
swis2-VHDL20_DWEG_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3113
swis2-VHDL20_DWEG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3214
swis2-VHDL20_DWEG_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:03:36 4211
swis2-VHDL20_DWEG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3817
swis2-VHDL20_DWEG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3711
swis2-VHDL20_DWEG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3498
swis2-VHDL20_DWEG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3670
swis2-VHDL20_DWEG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3247
swis2-VHDL20_DWEH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3568
swis2-VHDL20_DWEH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3701
swis2-VHDL20_DWEH_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3705
swis2-VHDL20_DWEH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 4035
swis2-VHDL20_DWEH_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:03:52 4646
swis2-VHDL20_DWEH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 4364
swis2-VHDL20_DWEH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 4189
swis2-VHDL20_DWEH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3593
swis2-VHDL20_DWEH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3699
swis2-VHDL20_DWEH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3257
swis2-VHDL20_DWEI_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 3205
swis2-VHDL20_DWEI_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 3166
swis2-VHDL20_DWEI_140400_COR-2603140400-dsw--0-ia5 14-Mar-2026 06:04:11 3170
swis2-VHDL20_DWEI_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3416
swis2-VHDL20_DWEI_140800_COR-2603140800-dsw--0-ia5 14-Mar-2026 19:04:02 4454
swis2-VHDL20_DWEI_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:06 4088
swis2-VHDL20_DWEI_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3825
swis2-VHDL20_DWEI_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:05 3517
swis2-VHDL20_DWEI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3700
swis2-VHDL20_DWEI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3316
swis2-VHDL20_DWHG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:07 3055
swis2-VHDL20_DWHG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 3123
swis2-VHDL20_DWHG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 3637
swis2-VHDL20_DWHG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2889
swis2-VHDL20_DWHG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3751
swis2-VHDL20_DWHG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 3748
swis2-VHDL20_DWHG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:06 5560
swis2-VHDL20_DWHG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:02:07 4813
swis2-VHDL20_DWHG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3546
swis2-VHDL20_DWHH_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:07 2388
swis2-VHDL20_DWHH_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:00:07 2422
swis2-VHDL20_DWHH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2822
swis2-VHDL20_DWHH_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 2487
swis2-VHDL20_DWHH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 2990
swis2-VHDL20_DWHH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:06 2990
swis2-VHDL20_DWHH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:06 4258
swis2-VHDL20_DWHH_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:02:37 3811
swis2-VHDL20_DWHH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 2882
swis2-VHDL20_DWLG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 2762
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swis2-VHDL20_DWMG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3335
swis2-VHDL20_DWMG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3324
swis2-VHDL20_DWMG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3571
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swis2-VHDL20_DWMO_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:07 3009
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swis2-VHDL20_DWMP_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3288
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swis2-VHDL20_DWPG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 2160
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swis2-VHDL20_DWPH_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:06 2583
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swis2-VHDL20_DWPH_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 2252
swis2-VHDL20_DWPH_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:00:12 2159
swis2-VHDL20_DWPH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 2926
swis2-VHDL20_DWPH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 2668
swis2-VHDL20_DWSG_140200-2603140200-dsw--0-ia5 14-Mar-2026 03:45:05 4036
swis2-VHDL20_DWSG_140400-2603140400-dsw--0-ia5 14-Mar-2026 06:15:01 4215
swis2-VHDL20_DWSG_140800-2603140800-dsw--0-ia5 14-Mar-2026 09:45:02 4112
swis2-VHDL20_DWSG_141300-2603141300-dsw--0-ia5 14-Mar-2026 14:45:07 3947
swis2-VHDL20_DWSG_141800-2603141800-dsw--0-ia5 14-Mar-2026 19:45:04 3531
swis2-VHDL20_DWSG_150200-2603150200-dsw--0-ia5 15-Mar-2026 03:45:04 3962
swis2-VHDL20_DWSG_150400-2603150400-dsw--0-ia5 15-Mar-2026 06:15:02 3996
swis2-VHDL20_DWSG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3789
swis2-VHDL20_DWSG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 13:56:35 4224
swis2-VHDL20_DWSG_151300-2603151300-dsw--0-ia5 15-Mar-2026 14:45:01 4056
swis2-VHDL20_DWSG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3764
wst04-VHDL20_DWEG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:15 251482
wst04-VHDL20_DWEG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:11 250097
wst04-VHDL20_DWEG_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250097
wst04-VHDL20_DWEG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:12 250633
wst04-VHDL20_DWEG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:12 249403
wst04-VHDL20_DWEG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:11 250547
wst04-VHDL20_DWEG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:21 250342
wst04-VHDL20_DWEG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:18 248071
wst04-VHDL20_DWEG_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:12 245432
wst04-VHDL20_DWEH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 251353
wst04-VHDL20_DWEH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:17 250927
wst04-VHDL20_DWEH_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 250927
wst04-VHDL20_DWEH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:17 251316
wst04-VHDL20_DWEH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:12 250986
wst04-VHDL20_DWEH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 251607
wst04-VHDL20_DWEH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 250682
wst04-VHDL20_DWEH_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:12 249327
wst04-VHDL20_DWEH_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:12 247824
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wst04-VHDL20_DWEI_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:23 357689
wst04-VHDL20_DWEI_140400_COR-2603140400-omedes-..> 14-Mar-2026 06:04:21 357689
wst04-VHDL20_DWEI_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:17 354880
wst04-VHDL20_DWEI_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 354102
wst04-VHDL20_DWEI_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:11 354568
wst04-VHDL20_DWEI_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:27 354837
wst04-VHDL20_DWEI_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:18 351984
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wst04-VHDL20_DWHG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 359687
wst04-VHDL20_DWHG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 359933
wst04-VHDL20_DWHG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:27 360249
wst04-VHDL20_DWHG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 358907
wst04-VHDL20_DWHG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 359590
wst04-VHDL20_DWHG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:12 359391
wst04-VHDL20_DWHG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:26 357929
wst04-VHDL20_DWHG_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:22 355044
wst04-VHDL20_DWHH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:17 341715
wst04-VHDL20_DWHH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:11 341468
wst04-VHDL20_DWHH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:27 328678
wst04-VHDL20_DWHH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 328309
wst04-VHDL20_DWHH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 328771
wst04-VHDL20_DWHH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:16 328747
wst04-VHDL20_DWHH_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:26 338314
wst04-VHDL20_DWHH_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:22 335810
wst04-VHDL20_DWLG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:27 343715
wst04-VHDL20_DWLG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:41 343606
wst04-VHDL20_DWLG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 346218
wst04-VHDL20_DWLG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 344886
wst04-VHDL20_DWLG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:26 344989
wst04-VHDL20_DWLG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 346016
wst04-VHDL20_DWLG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:32 338319
wst04-VHDL20_DWLG_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:26 337796
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wst04-VHDL20_DWLH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 346592
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wst04-VHDL20_DWLH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 345835
wst04-VHDL20_DWLH_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:26 343840
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wst04-VHDL20_DWLI_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 345062
wst04-VHDL20_DWLI_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:42 345441
wst04-VHDL20_DWLI_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:32 343633
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wst04-VHDL20_DWMG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 566048
wst04-VHDL20_DWMG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:21 568166
wst04-VHDL20_DWMG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 567541
wst04-VHDL20_DWMG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 567865
wst04-VHDL20_DWMG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:21 567800
wst04-VHDL20_DWMG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:22 558722
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wst04-VHDL20_DWMO_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 462517
wst04-VHDL20_DWMO_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 463634
wst04-VHDL20_DWMO_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:12 456294
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wst04-VHDL20_DWMP_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:21 565258
wst04-VHDL20_DWMP_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:21 561156
wst04-VHDL20_DWMP_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:16 560495
wst04-VHDL20_DWMP_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:17 559824
wst04-VHDL20_DWMP_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 560825
wst04-VHDL20_DWMP_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:22 563192
wst04-VHDL20_DWMP_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:16 561956
wst04-VHDL20_DWPG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 353093
wst04-VHDL20_DWPG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 353564
wst04-VHDL20_DWPG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:31 404545
wst04-VHDL20_DWPG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:26 358558
wst04-VHDL20_DWPG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:26 358799
wst04-VHDL20_DWPG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:32 358735
wst04-VHDL20_DWPG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:32 401081
wst04-VHDL20_DWPG_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:26 356224
wst04-VHDL20_DWPH_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:21 250352
wst04-VHDL20_DWPH_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:00:31 250897
wst04-VHDL20_DWPH_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:25 295412
wst04-VHDL20_DWPH_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:22 293995
wst04-VHDL20_DWPH_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:21 249383
wst04-VHDL20_DWPH_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:00:32 249334
wst04-VHDL20_DWPH_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:26 292350
wst04-VHDL20_DWPH_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:20 292083
wst04-VHDL20_DWSG_140200-2603140200-omedes--0.pdf 14-Mar-2026 03:45:11 361932
wst04-VHDL20_DWSG_140400-2603140400-omedes--0.pdf 14-Mar-2026 06:15:17 361665
wst04-VHDL20_DWSG_140800-2603140800-omedes--0.pdf 14-Mar-2026 09:45:12 355435
wst04-VHDL20_DWSG_141300-2603141300-omedes--0.pdf 14-Mar-2026 14:45:21 355572
wst04-VHDL20_DWSG_141800-2603141800-omedes--0.pdf 14-Mar-2026 19:45:12 354536
wst04-VHDL20_DWSG_150200-2603150200-omedes--0.pdf 15-Mar-2026 03:45:11 354044
wst04-VHDL20_DWSG_150400-2603150400-omedes--0.pdf 15-Mar-2026 06:15:17 355013
wst04-VHDL20_DWSG_150800-2603150800-omedes--0.pdf 15-Mar-2026 09:45:12 352699
wst04-VHDL20_DWSG_150800_COR-2603150800-omedes-..> 15-Mar-2026 13:56:41 352957
wst04-VHDL20_DWSG_151300-2603151300-omedes--0.pdf 15-Mar-2026 14:45:13 352905
wst04-VHDL20_DWSG_151800-2603151800-omedes--0.pdf 15-Mar-2026 19:45:12 352550