Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Apr-2026 13:08:45 6829
FPDL13_DWMZ_250600 25-Apr-2026 11:05:59 2623
SXDL31_DWAV_240800 24-Apr-2026 08:09:38 13308
SXDL31_DWAV_241800 24-Apr-2026 16:27:39 5999
SXDL31_DWAV_250800 25-Apr-2026 07:28:09 9439
SXDL31_DWAV_251800 25-Apr-2026 16:57:20 7762
SXDL31_DWAV_LATEST 25-Apr-2026 16:57:20 7762
SXDL33_DWAV_240000 24-Apr-2026 11:33:36 11279
SXDL33_DWAV_250000 25-Apr-2026 10:20:23 11684
SXDL33_DWAV_LATEST 25-Apr-2026 10:20:23 11684
ber01-FWDL39_DWMS_241230-2604241230-dsw--0-ia5 24-Apr-2026 10:50:21 1569
ber01-FWDL39_DWMS_251230-2604251230-dsw--0-ia5 25-Apr-2026 11:57:11 1080
ber01-VHDL13_DWEG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:28:16 2586
ber01-VHDL13_DWEG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:28:16 2459
ber01-VHDL13_DWEH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:28:16 2540
ber01-VHDL13_DWEH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:28:16 2612
ber01-VHDL13_DWEI_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:28:16 2678
ber01-VHDL13_DWEI_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:28:16 2395
ber01-VHDL13_DWHG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:08 3047
ber01-VHDL13_DWHG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 3232
ber01-VHDL13_DWHH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:07 3104
ber01-VHDL13_DWHH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 3157
ber01-VHDL13_DWLG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:07 2540
ber01-VHDL13_DWLG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2202
ber01-VHDL13_DWLH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:07 2636
ber01-VHDL13_DWLH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2277
ber01-VHDL13_DWLI_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:07 2502
ber01-VHDL13_DWLI_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1974
ber01-VHDL13_DWMO_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 2909
ber01-VHDL13_DWMO_240800_COR-2604240800-dsw--0-ia5 24-Apr-2026 08:42:42 2898
ber01-VHDL13_DWMO_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2353
ber01-VHDL13_DWMP_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 2284
ber01-VHDL13_DWMP_240800_COR-2604240800-dsw--0-ia5 24-Apr-2026 10:17:17 2404
ber01-VHDL13_DWMP_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2109
ber01-VHDL13_DWOG_240300-2604240300-dsw--0-ia5 24-Apr-2026 03:00:06 3764
ber01-VHDL13_DWOG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 3458
ber01-VHDL13_DWOG_241700-2604241700-dsw--0-ia5 24-Apr-2026 18:00:02 3673
ber01-VHDL13_DWOG_250300-2604250300-dsw--0-ia5 25-Apr-2026 03:00:04 3750
ber01-VHDL13_DWOG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 3511
ber01-VHDL13_DWOG_251700-2604251700-dsw--0-ia5 25-Apr-2026 18:00:02 3610
ber01-VHDL13_DWON_240253-2604240253-dsw--0-ia5 24-Apr-2026 02:53:42 3368
ber01-VHDL13_DWON_240530-2604240530-dsw--0-ia5 24-Apr-2026 05:30:17 3451
ber01-VHDL13_DWON_240549-2604240549-dsw--0-ia5 24-Apr-2026 05:49:21 3446
ber01-VHDL13_DWON_240751-2604240751-dsw--0-ia5 24-Apr-2026 07:51:21 3444
ber01-VHDL13_DWON_240826-2604240826-dsw--0-ia5 24-Apr-2026 08:27:03 3444
ber01-VHDL13_DWON_240848-2604240848-dsw--0-ia5 24-Apr-2026 08:48:18 3602
ber01-VHDL13_DWON_241445-2604241445-dsw--0-ia5 24-Apr-2026 14:45:11 2887
ber01-VHDL13_DWON_241642-2604241642-dsw--0-ia5 24-Apr-2026 16:42:02 2903
ber01-VHDL13_DWON_241647-2604241647-dsw--0-ia5 24-Apr-2026 16:47:41 2903
ber01-VHDL13_DWON_250227-2604250227-dsw--0-ia5 25-Apr-2026 02:28:01 3471
ber01-VHDL13_DWON_250521-2604250521-dsw--0-ia5 25-Apr-2026 05:21:35 3691
ber01-VHDL13_DWON_250628-2604250628-dsw--0-ia5 25-Apr-2026 06:28:27 3628
ber01-VHDL13_DWON_250818-2604250818-dsw--0-ia5 25-Apr-2026 08:18:51 3607
ber01-VHDL13_DWON_250953-2604250953-dsw--0-ia5 25-Apr-2026 09:53:46 3607
ber01-VHDL13_DWON_251439-2604251439-dsw--0-ia5 25-Apr-2026 14:40:21 3351
ber01-VHDL13_DWON_251723-2604251723-dsw--0-ia5 25-Apr-2026 17:23:52 3105
ber01-VHDL13_DWON_260013-2604260013-dsw--0-ia5 26-Apr-2026 00:13:16 3804
ber01-VHDL13_DWPG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:08 2442
ber01-VHDL13_DWPG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2100
ber01-VHDL13_DWPH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:07 3075
ber01-VHDL13_DWPH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2444
ber01-VHDL13_DWPH_250800_COR-2604250800-dsw--0-ia5 25-Apr-2026 18:58:47 3260
ber01-VHDL13_DWSG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 2200
ber01-VHDL13_DWSG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 2190
ber01-VHDL17_DWOG_241200-2604241200-dsw--0-ia5 24-Apr-2026 11:56:51 3174
ber01-VHDL17_DWOG_251200-2604251200-dsw--0-ia5 25-Apr-2026 12:01:01 3085
swis2-VHDL20_DWEG_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1251
swis2-VHDL20_DWEG_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 1256
swis2-VHDL20_DWEG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 1187
swis2-VHDL20_DWEG_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1201
swis2-VHDL20_DWEG_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 1019
swis2-VHDL20_DWEG_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1158
swis2-VHDL20_DWEG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1083
swis2-VHDL20_DWEG_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:09 959
swis2-VHDL20_DWEH_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1372
swis2-VHDL20_DWEH_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 1384
swis2-VHDL20_DWEH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 1232
swis2-VHDL20_DWEH_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1266
swis2-VHDL20_DWEH_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 1070
swis2-VHDL20_DWEH_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1196
swis2-VHDL20_DWEH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1087
swis2-VHDL20_DWEH_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:09 991
swis2-VHDL20_DWEI_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1097
swis2-VHDL20_DWEI_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 1102
swis2-VHDL20_DWEI_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 1295
swis2-VHDL20_DWEI_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1292
swis2-VHDL20_DWEI_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 1118
swis2-VHDL20_DWEI_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:17 1233
swis2-VHDL20_DWEI_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1111
swis2-VHDL20_DWEI_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:09 995
swis2-VHDL20_DWHG_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:45:06 1112
swis2-VHDL20_DWHG_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:17 1153
swis2-VHDL20_DWHG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:45:02 1467
swis2-VHDL20_DWHG_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:45:04 1466
swis2-VHDL20_DWHG_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:45:08 1174
swis2-VHDL20_DWHG_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:17 1171
swis2-VHDL20_DWHG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:45:16 1579
swis2-VHDL20_DWHG_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:45:02 1726
swis2-VHDL20_DWHH_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:45:06 1144
swis2-VHDL20_DWHH_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:17 1221
swis2-VHDL20_DWHH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:45:02 1488
swis2-VHDL20_DWHH_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:45:04 1457
swis2-VHDL20_DWHH_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:45:08 1307
swis2-VHDL20_DWHH_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:17 1307
swis2-VHDL20_DWHH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:45:16 1628
swis2-VHDL20_DWHH_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:45:02 1694
swis2-VHDL20_DWLG_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:28 1022
swis2-VHDL20_DWLG_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 1000
swis2-VHDL20_DWLG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:21 1101
swis2-VHDL20_DWLG_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:31:01 1090
swis2-VHDL20_DWLG_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:21 1109
swis2-VHDL20_DWLG_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1036
swis2-VHDL20_DWLG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:22 1137
swis2-VHDL20_DWLG_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:31:01 1171
swis2-VHDL20_DWLH_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:28 1070
swis2-VHDL20_DWLH_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 988
swis2-VHDL20_DWLH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:21 1110
swis2-VHDL20_DWLH_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:31:01 1155
swis2-VHDL20_DWLH_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:21 1248
swis2-VHDL20_DWLH_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1177
swis2-VHDL20_DWLH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:22 1215
swis2-VHDL20_DWLH_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:31:01 1228
swis2-VHDL20_DWLI_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:28 780
swis2-VHDL20_DWLI_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 783
swis2-VHDL20_DWLI_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:21 884
swis2-VHDL20_DWLI_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:31:01 882
swis2-VHDL20_DWLI_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:21 908
swis2-VHDL20_DWLI_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 841
swis2-VHDL20_DWLI_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:22 919
swis2-VHDL20_DWLI_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:31:01 921
swis2-VHDL20_DWMO_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1095
swis2-VHDL20_DWMO_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:01 1058
swis2-VHDL20_DWMO_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 1253
swis2-VHDL20_DWMO_240800_COR-2604240800-dsw--0-ia5 24-Apr-2026 08:42:42 1254
swis2-VHDL20_DWMO_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1008
swis2-VHDL20_DWMO_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 956
swis2-VHDL20_DWMO_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:06 960
swis2-VHDL20_DWMO_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1052
swis2-VHDL20_DWMO_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:04 1079
swis2-VHDL20_DWMP_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1012
swis2-VHDL20_DWMP_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:01 971
swis2-VHDL20_DWMP_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 1096
swis2-VHDL20_DWMP_240800_COR-2604240800-dsw--0-ia5 24-Apr-2026 10:17:17 1116
swis2-VHDL20_DWMP_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1011
swis2-VHDL20_DWMP_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 953
swis2-VHDL20_DWMP_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:06 956
swis2-VHDL20_DWMP_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 1035
swis2-VHDL20_DWMP_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:04 1046
swis2-VHDL20_DWPG_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:28 959
swis2-VHDL20_DWPG_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 930
swis2-VHDL20_DWPG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:21 1034
swis2-VHDL20_DWPG_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:31:01 1262
swis2-VHDL20_DWPG_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:21 1261
swis2-VHDL20_DWPG_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1175
swis2-VHDL20_DWPG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:22 1128
swis2-VHDL20_DWPG_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:31:01 1183
swis2-VHDL20_DWPH_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:28 1269
swis2-VHDL20_DWPH_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:11 1256
swis2-VHDL20_DWPH_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:21 1346
swis2-VHDL20_DWPH_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:31:01 1461
swis2-VHDL20_DWPH_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:21 1413
swis2-VHDL20_DWPH_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:11 1309
swis2-VHDL20_DWPH_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:22 1219
swis2-VHDL20_DWPH_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:31:01 1233
swis2-VHDL20_DWSG_240200-2604240200-dsw--0-ia5 24-Apr-2026 02:30:02 1009
swis2-VHDL20_DWSG_240400-2604240400-dsw--0-ia5 24-Apr-2026 05:00:17 847
swis2-VHDL20_DWSG_240800-2604240800-dsw--0-ia5 24-Apr-2026 08:30:02 912
swis2-VHDL20_DWSG_241800-2604241800-dsw--0-ia5 24-Apr-2026 18:30:02 1011
swis2-VHDL20_DWSG_250200-2604250200-dsw--0-ia5 25-Apr-2026 02:30:03 843
swis2-VHDL20_DWSG_250400-2604250400-dsw--0-ia5 25-Apr-2026 05:00:17 788
swis2-VHDL20_DWSG_250800-2604250800-dsw--0-ia5 25-Apr-2026 08:30:07 928
swis2-VHDL20_DWSG_251800-2604251800-dsw--0-ia5 25-Apr-2026 18:30:04 968
wst04-VHDL20_DWEG_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:12 237544
wst04-VHDL20_DWEG_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:11 137119
wst04-VHDL20_DWEG_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:17 238213
wst04-VHDL20_DWEG_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:17 235483
wst04-VHDL20_DWEG_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:15 234496
wst04-VHDL20_DWEG_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:11 137035
wst04-VHDL20_DWEG_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:13 235258
wst04-VHDL20_DWEG_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:14 234772
wst04-VHDL20_DWEH_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:12 231289
wst04-VHDL20_DWEH_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:11 231403
wst04-VHDL20_DWEH_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:17 231520
wst04-VHDL20_DWEH_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:13 232791
wst04-VHDL20_DWEH_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:15 232081
wst04-VHDL20_DWEH_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:11 232331
wst04-VHDL20_DWEH_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:13 232626
wst04-VHDL20_DWEH_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:14 236328
wst04-VHDL20_DWEI_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:12 339161
wst04-VHDL20_DWEI_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:11 338904
wst04-VHDL20_DWEI_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:17 339781
wst04-VHDL20_DWEI_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:17 343105
wst04-VHDL20_DWEI_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:19 342520
wst04-VHDL20_DWEI_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:17 342404
wst04-VHDL20_DWEI_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:17 342144
wst04-VHDL20_DWEI_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:14 335925
wst04-VHDL20_DWHG_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:45:13 326701
wst04-VHDL20_DWHG_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:17 326743
wst04-VHDL20_DWHG_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:45:11 328687
wst04-VHDL20_DWHG_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:45:11 330974
wst04-VHDL20_DWHG_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:45:11 330137
wst04-VHDL20_DWHG_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:17 330137
wst04-VHDL20_DWHG_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:45:16 332823
wst04-VHDL20_DWHG_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:45:12 330569
wst04-VHDL20_DWHH_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:45:13 311405
wst04-VHDL20_DWHH_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:17 217979
wst04-VHDL20_DWHH_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:45:11 313113
wst04-VHDL20_DWHH_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:45:11 309376
wst04-VHDL20_DWHH_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:45:11 309884
wst04-VHDL20_DWHH_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:17 214973
wst04-VHDL20_DWHH_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:45:16 310551
wst04-VHDL20_DWHH_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:45:12 312279
wst04-VHDL20_DWLG_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:28 323086
wst04-VHDL20_DWLG_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:41 322339
wst04-VHDL20_DWLG_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:45 322916
wst04-VHDL20_DWLG_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:31:23 323407
wst04-VHDL20_DWLG_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:21 323884
wst04-VHDL20_DWLG_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:42 323878
wst04-VHDL20_DWLG_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:42 324083
wst04-VHDL20_DWLG_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:31:24 320519
wst04-VHDL20_DWLH_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:20 318750
wst04-VHDL20_DWLH_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:41 318197
wst04-VHDL20_DWLH_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:45 318813
wst04-VHDL20_DWLH_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:31:26 321714
wst04-VHDL20_DWLH_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:27 322220
wst04-VHDL20_DWLH_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:42 322208
wst04-VHDL20_DWLH_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:42 322404
wst04-VHDL20_DWLH_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:31:24 317017
wst04-VHDL20_DWLI_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:20 322335
wst04-VHDL20_DWLI_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:41 321791
wst04-VHDL20_DWLI_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:45 366846
wst04-VHDL20_DWLI_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:31:23 326125
wst04-VHDL20_DWLI_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:21 326628
wst04-VHDL20_DWLI_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:42 326571
wst04-VHDL20_DWLI_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:42 371320
wst04-VHDL20_DWLI_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:31:24 318236
wst04-VHDL20_DWMO_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:17 441955
wst04-VHDL20_DWMO_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:17 442537
wst04-VHDL20_DWMO_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:17 442645
wst04-VHDL20_DWMO_240800_COR-2604240800-omedes-..> 24-Apr-2026 08:42:46 442614
wst04-VHDL20_DWMO_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:17 349363
wst04-VHDL20_DWMO_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:15 448114
wst04-VHDL20_DWMO_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:11 448039
wst04-VHDL20_DWMO_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:17 448558
wst04-VHDL20_DWMO_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:18 333981
wst04-VHDL20_DWMP_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:17 532568
wst04-VHDL20_DWMP_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:17 533195
wst04-VHDL20_DWMP_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:21 440011
wst04-VHDL20_DWMP_240800_COR-2604240800-omedes-..> 24-Apr-2026 10:17:21 454715
wst04-VHDL20_DWMP_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:17 454707
wst04-VHDL20_DWMP_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:19 550332
wst04-VHDL20_DWMP_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:17 550308
wst04-VHDL20_DWMP_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:22 454446
wst04-VHDL20_DWMP_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:18 454110
wst04-VHDL20_DWPG_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:20 234068
wst04-VHDL20_DWPG_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:31 327811
wst04-VHDL20_DWPG_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:49 372932
wst04-VHDL20_DWPG_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:31:23 331085
wst04-VHDL20_DWPG_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:21 236270
wst04-VHDL20_DWPG_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:32 331524
wst04-VHDL20_DWPG_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:46 376212
wst04-VHDL20_DWPG_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:31:29 322692
wst04-VHDL20_DWPH_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:20 234562
wst04-VHDL20_DWPH_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:31 234642
wst04-VHDL20_DWPH_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:45 235354
wst04-VHDL20_DWPH_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:31:23 236152
wst04-VHDL20_DWPH_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:21 236383
wst04-VHDL20_DWPH_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:32 236412
wst04-VHDL20_DWPH_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:42 235832
wst04-VHDL20_DWPH_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:31:24 234857
wst04-VHDL20_DWPH_251800_COR-2604251800-omedes-..> 25-Apr-2026 19:00:31 235029
wst04-VHDL20_DWSG_240200-2604240200-omedes--0.pdf 24-Apr-2026 02:30:12 336515
wst04-VHDL20_DWSG_240400-2604240400-omedes--0.pdf 24-Apr-2026 05:00:13 336385
wst04-VHDL20_DWSG_240800-2604240800-omedes--0.pdf 24-Apr-2026 08:30:11 336409
wst04-VHDL20_DWSG_241800-2604241800-omedes--0.pdf 24-Apr-2026 18:30:13 337730
wst04-VHDL20_DWSG_250200-2604250200-omedes--0.pdf 25-Apr-2026 02:30:15 337297
wst04-VHDL20_DWSG_250400-2604250400-omedes--0.pdf 25-Apr-2026 05:00:11 337274
wst04-VHDL20_DWSG_250800-2604250800-omedes--0.pdf 25-Apr-2026 08:30:17 337403
wst04-VHDL20_DWSG_251800-2604251800-omedes--0.pdf 25-Apr-2026 18:30:14 338711