Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Dec-2025 14:40:49 3028
FPDL13_DWMZ_130600 13-Dec-2025 14:06:25 5388
SXDL31_DWAV_111800 11-Dec-2025 17:35:14 5861
SXDL31_DWAV_120800 12-Dec-2025 08:49:59 10930
SXDL31_DWAV_121800 12-Dec-2025 16:57:47 4033
SXDL31_DWAV_130800 13-Dec-2025 08:34:25 9721
SXDL31_DWAV_LATEST 13-Dec-2025 08:34:25 9721
SXDL33_DWAV_120000 12-Dec-2025 10:27:50 7916
SXDL33_DWAV_130000 13-Dec-2025 10:20:09 7061
SXDL33_DWAV_LATEST 13-Dec-2025 10:20:09 7061
ber01-FWDL39_DWMS_121230-2512121230-dsw--0-ia5 12-Dec-2025 12:46:21 1502
ber01-FWDL39_DWMS_131230-2512131230-dsw--0-ia5 13-Dec-2025 12:04:00 1080
ber01-VHDL13_DWEH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:28:16 2721
ber01-VHDL13_DWEH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:28:12 2844
ber01-VHDL13_DWEH_120400-2512120400-dsw--0-ia5 12-Dec-2025 05:58:13 2958
ber01-VHDL13_DWEH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:28:17 2905
ber01-VHDL13_DWEH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:28:18 2461
ber01-VHDL13_DWEH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:28:11 2792
ber01-VHDL13_DWEH_130400-2512130400-dsw--0-ia5 13-Dec-2025 05:58:17 2557
ber01-VHDL13_DWEH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:28:19 2602
ber01-VHDL13_DWHG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:06 2194
ber01-VHDL13_DWHG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:10 2693
ber01-VHDL13_DWHG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:07 2833
ber01-VHDL13_DWHG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 2717
ber01-VHDL13_DWHG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 2588
ber01-VHDL13_DWHG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:06 2761
ber01-VHDL13_DWHG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:06 2761
ber01-VHDL13_DWHG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:12 2945
ber01-VHDL13_DWHH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:06 2404
ber01-VHDL13_DWHH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:10 2590
ber01-VHDL13_DWHH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:07 2590
ber01-VHDL13_DWHH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 2440
ber01-VHDL13_DWHH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 2330
ber01-VHDL13_DWHH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:06 2511
ber01-VHDL13_DWHH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:06 2511
ber01-VHDL13_DWHH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:12 2782
ber01-VHDL13_DWLG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 1829
ber01-VHDL13_DWLG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 2014
ber01-VHDL13_DWLG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 1881
ber01-VHDL13_DWLG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:16 2035
ber01-VHDL13_DWLG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 1980
ber01-VHDL13_DWLG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2652
ber01-VHDL13_DWLG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:01 2521
ber01-VHDL13_DWLG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2530
ber01-VHDL13_DWLH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 1812
ber01-VHDL13_DWLH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 1971
ber01-VHDL13_DWLH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 2032
ber01-VHDL13_DWLH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 2386
ber01-VHDL13_DWLH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 2300
ber01-VHDL13_DWLH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2480
ber01-VHDL13_DWLH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:01 2320
ber01-VHDL13_DWLH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2279
ber01-VHDL13_DWLI_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 2094
ber01-VHDL13_DWLI_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 2177
ber01-VHDL13_DWLI_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 1937
ber01-VHDL13_DWLI_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 2125
ber01-VHDL13_DWLI_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 2075
ber01-VHDL13_DWLI_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2286
ber01-VHDL13_DWLI_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:01 2236
ber01-VHDL13_DWLI_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2195
ber01-VHDL13_DWMG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:03 2622
ber01-VHDL13_DWMG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:10 3238
ber01-VHDL13_DWMG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 3250
ber01-VHDL13_DWMG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:55:32 3235
ber01-VHDL13_DWMG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:02 2802
ber01-VHDL13_DWMG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:06 3051
ber01-VHDL13_DWMG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:03 3062
ber01-VHDL13_DWMG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2898
ber01-VHDL13_DWMO_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:03 2106
ber01-VHDL13_DWMO_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:10 2587
ber01-VHDL13_DWMO_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 2561
ber01-VHDL13_DWMO_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:55:46 2660
ber01-VHDL13_DWMO_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:02 2314
ber01-VHDL13_DWMO_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:06 2790
ber01-VHDL13_DWMO_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:03 2802
ber01-VHDL13_DWMO_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2677
ber01-VHDL13_DWMP_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:03 2723
ber01-VHDL13_DWMP_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:10 3154
ber01-VHDL13_DWMP_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 3114
ber01-VHDL13_DWMP_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:55:56 3276
ber01-VHDL13_DWMP_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:02 2821
ber01-VHDL13_DWMP_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:06 3282
ber01-VHDL13_DWMP_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:03 3293
ber01-VHDL13_DWMP_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 3113
ber01-VHDL13_DWOG_111700-2512111700-dsw--0-ia5 11-Dec-2025 19:00:02 3470
ber01-VHDL13_DWOG_120300-2512120300-dsw--0-ia5 12-Dec-2025 04:00:01 4197
ber01-VHDL13_DWOG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 4079
ber01-VHDL13_DWOG_121700-2512121700-dsw--0-ia5 12-Dec-2025 19:00:02 3344
ber01-VHDL13_DWOG_130300-2512130300-dsw--0-ia5 13-Dec-2025 04:00:01 4415
ber01-VHDL13_DWOG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 4151
ber01-VHDL13_DWOH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:28:16 1977
ber01-VHDL13_DWOH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:28:12 2340
ber01-VHDL13_DWOH_120400-2512120400-dsw--0-ia5 12-Dec-2025 05:58:11 2484
ber01-VHDL13_DWOH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:28:17 2368
ber01-VHDL13_DWOH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:28:18 1997
ber01-VHDL13_DWOH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:28:17 2185
ber01-VHDL13_DWOH_130400-2512130400-dsw--0-ia5 13-Dec-2025 05:58:13 1999
ber01-VHDL13_DWOH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:28:19 1990
ber01-VHDL13_DWOI_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:28:12 2115
ber01-VHDL13_DWOI_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:28:16 2376
ber01-VHDL13_DWOI_120400-2512120400-dsw--0-ia5 12-Dec-2025 05:58:17 2499
ber01-VHDL13_DWOI_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:28:11 2422
ber01-VHDL13_DWOI_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:28:12 1881
ber01-VHDL13_DWOI_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:28:11 2231
ber01-VHDL13_DWOI_130400-2512130400-dsw--0-ia5 13-Dec-2025 05:58:13 2061
ber01-VHDL13_DWOI_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:28:11 2081
ber01-VHDL13_DWON_111818-2512111818-dsw--0-ia5 11-Dec-2025 18:18:27 3416
ber01-VHDL13_DWON_112219-2512112219-dsw--0-ia5 11-Dec-2025 22:19:41 3375
ber01-VHDL13_DWON_120351-2512120351-dsw--0-ia5 12-Dec-2025 03:51:43 3906
ber01-VHDL13_DWON_120627-2512120627-dsw--0-ia5 12-Dec-2025 06:27:41 3813
ber01-VHDL13_DWON_120648-2512120648-dsw--0-ia5 12-Dec-2025 06:48:21 3808
ber01-VHDL13_DWON_120650-2512120650-dsw--0-ia5 12-Dec-2025 06:50:47 3845
ber01-VHDL13_DWON_121132-2512121132-dsw--0-ia5 12-Dec-2025 11:32:33 3845
ber01-VHDL13_DWON_121627-2512121627-dsw--0-ia5 12-Dec-2025 16:27:42 3325
ber01-VHDL13_DWON_121739-2512121739-dsw--0-ia5 12-Dec-2025 17:39:37 3293
ber01-VHDL13_DWON_121904-2512121904-dsw--0-ia5 12-Dec-2025 19:04:42 3449
ber01-VHDL13_DWON_122039-2512122039-dsw--0-ia5 12-Dec-2025 20:40:09 3449
ber01-VHDL13_DWON_122226-2512122226-dsw--0-ia5 12-Dec-2025 22:26:32 3449
ber01-VHDL13_DWON_130002-2512130002-dsw--0-ia5 13-Dec-2025 00:02:23 4038
ber01-VHDL13_DWON_130142-2512130142-dsw--0-ia5 13-Dec-2025 01:42:36 4030
ber01-VHDL13_DWON_130345-2512130345-dsw--0-ia5 13-Dec-2025 03:45:16 4089
ber01-VHDL13_DWON_130623-2512130623-dsw--0-ia5 13-Dec-2025 06:24:00 3630
ber01-VHDL13_DWON_130714-2512130714-dsw--0-ia5 13-Dec-2025 07:14:51 4212
ber01-VHDL13_DWON_130850-2512130850-dsw--0-ia5 13-Dec-2025 08:50:47 4212
ber01-VHDL13_DWON_131533-2512131533-dsw--0-ia5 13-Dec-2025 15:33:34 3552
ber01-VHDL13_DWPG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 2362
ber01-VHDL13_DWPG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 2270
ber01-VHDL13_DWPG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 2295
ber01-VHDL13_DWPG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:15 2176
ber01-VHDL13_DWPG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 1817
ber01-VHDL13_DWPG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2063
ber01-VHDL13_DWPG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:01 1897
ber01-VHDL13_DWPG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 1947
ber01-VHDL13_DWPH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 1768
ber01-VHDL13_DWPH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 1729
ber01-VHDL13_DWPH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:01 1812
ber01-VHDL13_DWPH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:16 1936
ber01-VHDL13_DWPH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:07 1754
ber01-VHDL13_DWPH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2032
ber01-VHDL13_DWPH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:01 2047
ber01-VHDL13_DWPH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2088
ber01-VHDL13_DWSG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:30:01 2848
ber01-VHDL13_DWSG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:30:01 3098
ber01-VHDL13_DWSG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:07 2931
ber01-VHDL13_DWSG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:30:16 3107
ber01-VHDL13_DWSG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:30:02 2618
ber01-VHDL13_DWSG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:30:02 2654
ber01-VHDL13_DWSG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:06 2759
ber01-VHDL13_DWSG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:30:02 2874
ber01-VHDL17_DWOG_121200-2512121200-dsw--0-ia5 12-Dec-2025 12:56:57 3668
ber01-VHDL17_DWOG_131200-2512131200-dsw--0-ia5 13-Dec-2025 12:02:36 2621
swis2-VHDL20_DWEG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2303
swis2-VHDL20_DWEG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:06 2616
swis2-VHDL20_DWEG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:07 2807
swis2-VHDL20_DWEG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2849
swis2-VHDL20_DWEG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 2326
swis2-VHDL20_DWEG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 2461
swis2-VHDL20_DWEG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 2322
swis2-VHDL20_DWEG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 2467
swis2-VHDL20_DWEH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 3075
swis2-VHDL20_DWEH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:06 3165
swis2-VHDL20_DWEH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:07 3293
swis2-VHDL20_DWEH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 3411
swis2-VHDL20_DWEH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 2818
swis2-VHDL20_DWEH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 3116
swis2-VHDL20_DWEH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 2892
swis2-VHDL20_DWEH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 3104
swis2-VHDL20_DWEI_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2466
swis2-VHDL20_DWEI_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:06 2668
swis2-VHDL20_DWEI_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:07 2853
swis2-VHDL20_DWEI_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2950
swis2-VHDL20_DWEI_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 2235
swis2-VHDL20_DWEI_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 2523
swis2-VHDL20_DWEI_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 2415
swis2-VHDL20_DWEI_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 2605
swis2-VHDL20_DWHG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:07 2377
swis2-VHDL20_DWHG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:06 2879
swis2-VHDL20_DWHG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:07 3016
swis2-VHDL20_DWHG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:02 3254
swis2-VHDL20_DWHG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2771
swis2-VHDL20_DWHG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 2947
swis2-VHDL20_DWHG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:06 2944
swis2-VHDL20_DWHG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 3481
swis2-VHDL20_DWHH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:07 2590
swis2-VHDL20_DWHH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:06 2776
swis2-VHDL20_DWHH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:07 2776
swis2-VHDL20_DWHH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:02 2986
swis2-VHDL20_DWHH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2516
swis2-VHDL20_DWHH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 2697
swis2-VHDL20_DWHH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:06 2697
swis2-VHDL20_DWHH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 3327
swis2-VHDL20_DWLG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2171
swis2-VHDL20_DWLG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2359
swis2-VHDL20_DWLG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:11 2223
swis2-VHDL20_DWLG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2519
swis2-VHDL20_DWLG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2322
swis2-VHDL20_DWLG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 2997
swis2-VHDL20_DWLG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:12 2859
swis2-VHDL20_DWLG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 3010
swis2-VHDL20_DWLH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2161
swis2-VHDL20_DWLH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2323
swis2-VHDL20_DWLH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:11 2381
swis2-VHDL20_DWLH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2881
swis2-VHDL20_DWLH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2649
swis2-VHDL20_DWLH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 2832
swis2-VHDL20_DWLH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:12 2665
swis2-VHDL20_DWLH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 2770
swis2-VHDL20_DWLI_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2438
swis2-VHDL20_DWLI_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2524
swis2-VHDL20_DWLI_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:11 2281
swis2-VHDL20_DWLI_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2610
swis2-VHDL20_DWLI_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2419
swis2-VHDL20_DWLI_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 2633
swis2-VHDL20_DWLI_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:12 2576
swis2-VHDL20_DWLI_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 2676
swis2-VHDL20_DWMG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 3421
swis2-VHDL20_DWMG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 3716
swis2-VHDL20_DWMG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:02 3738
swis2-VHDL20_DWMG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:57:46 3969
swis2-VHDL20_DWMG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 3300
swis2-VHDL20_DWMG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 3532
swis2-VHDL20_DWMG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 3534
swis2-VHDL20_DWMG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 3584
swis2-VHDL20_DWMO_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2480
swis2-VHDL20_DWMO_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2961
swis2-VHDL20_DWMO_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:02 2935
swis2-VHDL20_DWMO_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:58:02 3194
swis2-VHDL20_DWMO_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 2760
swis2-VHDL20_DWMO_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 3227
swis2-VHDL20_DWMO_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 3241
swis2-VHDL20_DWMO_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 3332
swis2-VHDL20_DWMP_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 3169
swis2-VHDL20_DWMP_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 3608
swis2-VHDL20_DWMP_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:02 3543
swis2-VHDL20_DWMP_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:58:16 3955
swis2-VHDL20_DWMP_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 3312
swis2-VHDL20_DWMP_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 3769
swis2-VHDL20_DWMP_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 3778
swis2-VHDL20_DWMP_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:06 3815
swis2-VHDL20_DWPG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2822
swis2-VHDL20_DWPG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2599
swis2-VHDL20_DWPG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:11 2622
swis2-VHDL20_DWPG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2636
swis2-VHDL20_DWPG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2277
swis2-VHDL20_DWPG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 2393
swis2-VHDL20_DWPG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:12 2220
swis2-VHDL20_DWPG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 2399
swis2-VHDL20_DWPH_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 2228
swis2-VHDL20_DWPH_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 2057
swis2-VHDL20_DWPH_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:00:11 2141
swis2-VHDL20_DWPH_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:06 2396
swis2-VHDL20_DWPH_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:06 2214
swis2-VHDL20_DWPH_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:02 2361
swis2-VHDL20_DWPH_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:00:12 2372
swis2-VHDL20_DWPH_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 2540
swis2-VHDL20_DWSG_111800-2512111800-dsw--0-ia5 11-Dec-2025 19:45:03 3236
swis2-VHDL20_DWSG_120200-2512120200-dsw--0-ia5 12-Dec-2025 03:45:04 3509
swis2-VHDL20_DWSG_120400-2512120400-dsw--0-ia5 12-Dec-2025 06:15:02 3350
swis2-VHDL20_DWSG_120800-2512120800-dsw--0-ia5 12-Dec-2025 09:45:02 3767
swis2-VHDL20_DWSG_121300-2512121300-dsw--0-ia5 12-Dec-2025 14:45:10 3551
swis2-VHDL20_DWSG_121800-2512121800-dsw--0-ia5 12-Dec-2025 19:45:01 3055
swis2-VHDL20_DWSG_130200-2512130200-dsw--0-ia5 13-Dec-2025 03:45:06 3074
swis2-VHDL20_DWSG_130400-2512130400-dsw--0-ia5 13-Dec-2025 06:15:02 3188
swis2-VHDL20_DWSG_130800-2512130800-dsw--0-ia5 13-Dec-2025 09:45:02 3503
swis2-VHDL20_DWSG_131300-2512131300-dsw--0-ia5 13-Dec-2025 14:45:04 3552
wst04-VHDL20_DWEG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:11 223029
wst04-VHDL20_DWEG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:11 224351
wst04-VHDL20_DWEG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:27 223933
wst04-VHDL20_DWEG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:22 224979
wst04-VHDL20_DWEG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:12 223814
wst04-VHDL20_DWEG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:16 224941
wst04-VHDL20_DWEG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:21 224297
wst04-VHDL20_DWEG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:22 225007
wst04-VHDL20_DWEH_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:11 229147
wst04-VHDL20_DWEH_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:17 230428
wst04-VHDL20_DWEH_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:21 229579
wst04-VHDL20_DWEH_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:22 229695
wst04-VHDL20_DWEH_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:12 227294
wst04-VHDL20_DWEH_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:16 229784
wst04-VHDL20_DWEH_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:27 229608
wst04-VHDL20_DWEH_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:22 230135
wst04-VHDL20_DWEI_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:17 310894
wst04-VHDL20_DWEI_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:17 312041
wst04-VHDL20_DWEI_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:27 311689
wst04-VHDL20_DWEI_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:26 316446
wst04-VHDL20_DWEI_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:16 315650
wst04-VHDL20_DWEI_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:16 316682
wst04-VHDL20_DWEI_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:27 316476
wst04-VHDL20_DWEI_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:26 316895
wst04-VHDL20_DWHG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:21 311472
wst04-VHDL20_DWHG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:11 311889
wst04-VHDL20_DWHG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:11 312106
wst04-VHDL20_DWHG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:22 312494
wst04-VHDL20_DWHG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:22 311311
wst04-VHDL20_DWHG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:12 311646
wst04-VHDL20_DWHG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:12 311670
wst04-VHDL20_DWHG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:16 312722
wst04-VHDL20_DWHH_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:17 299143
wst04-VHDL20_DWHH_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:11 298472
wst04-VHDL20_DWHH_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:11 298494
wst04-VHDL20_DWHH_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:16 302471
wst04-VHDL20_DWHH_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:16 301316
wst04-VHDL20_DWHH_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:12 302157
wst04-VHDL20_DWHH_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:12 302231
wst04-VHDL20_DWHH_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:16 303176
wst04-VHDL20_DWLG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:21 321926
wst04-VHDL20_DWLG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:21 322126
wst04-VHDL20_DWLG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:42 321405
wst04-VHDL20_DWLG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:32 319624
wst04-VHDL20_DWLG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:22 319244
wst04-VHDL20_DWLG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:26 320160
wst04-VHDL20_DWLG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:41 320147
wst04-VHDL20_DWLG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:26 320313
wst04-VHDL20_DWLH_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:27 315712
wst04-VHDL20_DWLH_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:27 316247
wst04-VHDL20_DWLH_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:42 315329
wst04-VHDL20_DWLH_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:32 317338
wst04-VHDL20_DWLH_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:22 316644
wst04-VHDL20_DWLH_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:26 316803
wst04-VHDL20_DWLH_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:41 317250
wst04-VHDL20_DWLH_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:30 317500
wst04-VHDL20_DWLI_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:27 310764
wst04-VHDL20_DWLI_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:27 311441
wst04-VHDL20_DWLI_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:42 310473
wst04-VHDL20_DWLI_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:32 308687
wst04-VHDL20_DWLI_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:26 308439
wst04-VHDL20_DWLI_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:22 308936
wst04-VHDL20_DWLI_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:41 309115
wst04-VHDL20_DWLI_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:30 309199
wst04-VHDL20_DWMG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:17 536555
wst04-VHDL20_DWMG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:21 537101
wst04-VHDL20_DWMG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:21 537319
wst04-VHDL20_DWMG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:56:26 515888
wst04-VHDL20_DWMG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:18 515157
wst04-VHDL20_DWMG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:22 515187
wst04-VHDL20_DWMG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:21 515178
wst04-VHDL20_DWMG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:16 515265
wst04-VHDL20_DWMO_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:11 426916
wst04-VHDL20_DWMO_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:17 428341
wst04-VHDL20_DWMO_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:21 429070
wst04-VHDL20_DWMO_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:56:56 416570
wst04-VHDL20_DWMO_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:18 414782
wst04-VHDL20_DWMO_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:16 416030
wst04-VHDL20_DWMO_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:21 416517
wst04-VHDL20_DWMO_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:12 416112
wst04-VHDL20_DWMP_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:17 551617
wst04-VHDL20_DWMP_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:21 551095
wst04-VHDL20_DWMP_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:21 552512
wst04-VHDL20_DWMP_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:57:22 523425
wst04-VHDL20_DWMP_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:18 522781
wst04-VHDL20_DWMP_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:22 521693
wst04-VHDL20_DWMP_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:21 522976
wst04-VHDL20_DWMP_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:22 523254
wst04-VHDL20_DWPG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:21 314239
wst04-VHDL20_DWPG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:27 314348
wst04-VHDL20_DWPG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:32 313882
wst04-VHDL20_DWPG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:32 352433
wst04-VHDL20_DWPG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:26 307690
wst04-VHDL20_DWPG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:26 307152
wst04-VHDL20_DWPG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:31 308213
wst04-VHDL20_DWPG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:30 353364
wst04-VHDL20_DWPH_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:21 267610
wst04-VHDL20_DWPH_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:21 223041
wst04-VHDL20_DWPH_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:00:32 222139
wst04-VHDL20_DWPH_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:26 271397
wst04-VHDL20_DWPH_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:22 271484
wst04-VHDL20_DWPH_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:22 226688
wst04-VHDL20_DWPH_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:00:31 226900
wst04-VHDL20_DWPH_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:26 271324
wst04-VHDL20_DWSG_111800-2512111800-omedes--0.pdf 11-Dec-2025 19:45:11 338526
wst04-VHDL20_DWSG_120200-2512120200-omedes--0.pdf 12-Dec-2025 03:45:17 338952
wst04-VHDL20_DWSG_120400-2512120400-omedes--0.pdf 12-Dec-2025 06:15:11 339452
wst04-VHDL20_DWSG_120800-2512120800-omedes--0.pdf 12-Dec-2025 09:45:12 330212
wst04-VHDL20_DWSG_121300-2512121300-omedes--0.pdf 12-Dec-2025 14:45:18 330406
wst04-VHDL20_DWSG_121800-2512121800-omedes--0.pdf 12-Dec-2025 19:45:12 329460
wst04-VHDL20_DWSG_130200-2512130200-omedes--0.pdf 13-Dec-2025 03:45:12 329403
wst04-VHDL20_DWSG_130400-2512130400-omedes--0.pdf 13-Dec-2025 06:15:17 329647
wst04-VHDL20_DWSG_130800-2512130800-omedes--0.pdf 13-Dec-2025 09:45:12 329597
wst04-VHDL20_DWSG_131300-2512131300-omedes--0.pdf 13-Dec-2025 14:45:12 341135