Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Jul-2026 12:28:20 17491
FPDL13_DWMZ_130600 13-Jul-2026 11:15:00 3908
SXDL31_DWAV_120800 12-Jul-2026 07:11:05 9143
SXDL31_DWAV_121800 12-Jul-2026 15:45:51 6741
SXDL31_DWAV_130800 13-Jul-2026 08:46:02 12682
SXDL31_DWAV_131800 13-Jul-2026 17:11:43 7983
SXDL31_DWAV_LATEST 13-Jul-2026 17:11:43 7983
SXDL33_DWAV_120000 12-Jul-2026 09:59:45 8275
SXDL33_DWAV_130000 13-Jul-2026 10:33:15 8260
SXDL33_DWAV_LATEST 13-Jul-2026 10:33:15 8260
ber01-FWDL39_DWMS_121200-2607121200-dsw--0-ia5 12-Jul-2026 11:31:51 1224
ber01-FWDL39_DWMS_131200-2607131200-dsw--0-ia5 13-Jul-2026 10:48:27 1343
ber01-VHDL13_DWEG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:17 2682
ber01-VHDL13_DWEG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:16 3456
ber01-VHDL13_DWEH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:11 2469
ber01-VHDL13_DWEH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:16 3399
ber01-VHDL13_DWEI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:28:17 2481
ber01-VHDL13_DWEI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:11 3238
ber01-VHDL13_DWHG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3348
ber01-VHDL13_DWHG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3346
ber01-VHDL13_DWHH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 3321
ber01-VHDL13_DWHH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3223
ber01-VHDL13_DWLG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2172
ber01-VHDL13_DWLG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3178
ber01-VHDL13_DWLG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:51:03 3448
ber01-VHDL13_DWLH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2215
ber01-VHDL13_DWLH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3252
ber01-VHDL13_DWLI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2068
ber01-VHDL13_DWLI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 2890
ber01-VHDL13_DWMO_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 2575
ber01-VHDL13_DWMO_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3226
ber01-VHDL13_DWMP_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2631
ber01-VHDL13_DWMP_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3215
ber01-VHDL13_DWOG_120300-2607120300-dsw--0-ia5 12-Jul-2026 03:00:23 3914
ber01-VHDL13_DWOG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3910
ber01-VHDL13_DWOG_121700-2607121700-dsw--0-ia5 12-Jul-2026 18:00:07 3359
ber01-VHDL13_DWOG_130300-2607130300-dsw--0-ia5 13-Jul-2026 03:00:02 4000
ber01-VHDL13_DWOG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3872
ber01-VHDL13_DWOG_131700-2607131700-dsw--0-ia5 13-Jul-2026 18:00:02 4468
ber01-VHDL13_DWON_112329-2607112329-dsw--0-ia5 11-Jul-2026 23:29:51 4171
ber01-VHDL13_DWON_120000-2607120000-dsw--0-ia5 12-Jul-2026 00:00:23 4171
ber01-VHDL13_DWON_120135-2607120135-dsw--0-ia5 12-Jul-2026 01:35:27 4135
ber01-VHDL13_DWON_120235-2607120235-dsw--0-ia5 12-Jul-2026 02:36:11 4135
ber01-VHDL13_DWON_120520-2607120520-dsw--0-ia5 12-Jul-2026 05:20:51 4351
ber01-VHDL13_DWON_120620-2607120620-dsw--0-ia5 12-Jul-2026 06:20:18 4351
ber01-VHDL13_DWON_120808-2607120808-dsw--0-ia5 12-Jul-2026 08:08:32 4351
ber01-VHDL13_DWON_120852-2607120852-dsw--0-ia5 12-Jul-2026 08:52:32 4351
ber01-VHDL13_DWON_121457-2607121457-dsw--0-ia5 12-Jul-2026 14:57:06 3528
ber01-VHDL13_DWON_121721-2607121721-dsw--0-ia5 12-Jul-2026 17:21:26 3229
ber01-VHDL13_DWON_122257-2607122257-dsw--0-ia5 12-Jul-2026 22:57:31 3430
ber01-VHDL13_DWON_130220-2607130220-dsw--0-ia5 13-Jul-2026 02:20:27 3450
ber01-VHDL13_DWON_130516-2607130516-dsw--0-ia5 13-Jul-2026 05:16:31 3460
ber01-VHDL13_DWON_130735-2607130735-dsw--0-ia5 13-Jul-2026 07:35:21 3377
ber01-VHDL13_DWON_131054-2607131054-dsw--0-ia5 13-Jul-2026 10:54:27 3442
ber01-VHDL13_DWON_131403-2607131403-dsw--0-ia5 13-Jul-2026 14:03:17 3984
ber01-VHDL13_DWON_131742-2607131742-dsw--0-ia5 13-Jul-2026 17:43:04 3845
ber01-VHDL13_DWON_132022-2607132022-dsw--0-ia5 13-Jul-2026 20:22:46 3687
ber01-VHDL13_DWPG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2304
ber01-VHDL13_DWPG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3614
ber01-VHDL13_DWPH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 2433
ber01-VHDL13_DWPH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 2828
ber01-VHDL13_DWPH_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:07:36 3224
ber01-VHDL13_DWSG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 3172
ber01-VHDL13_DWSG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 4152
ber01-VHDL13_DWSG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 09:16:06 4156
ber01-VHDL17_DWOG_121200-2607121200-dsw--0-ia5 12-Jul-2026 11:43:22 3183
ber01-VHDL17_DWOG_131200-2607131200-dsw--0-ia5 13-Jul-2026 12:12:11 2688
swis2-VHDL20_DWEG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1005
swis2-VHDL20_DWEG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 1009
swis2-VHDL20_DWEG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1272
swis2-VHDL20_DWEG_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:08 1481
swis2-VHDL20_DWEG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1208
swis2-VHDL20_DWEG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1622
swis2-VHDL20_DWEG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1902
swis2-VHDL20_DWEG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2340
swis2-VHDL20_DWEH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 923
swis2-VHDL20_DWEH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 911
swis2-VHDL20_DWEH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1172
swis2-VHDL20_DWEH_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:08 1373
swis2-VHDL20_DWEH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1096
swis2-VHDL20_DWEH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1583
swis2-VHDL20_DWEH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1969
swis2-VHDL20_DWEH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2374
swis2-VHDL20_DWEI_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 969
swis2-VHDL20_DWEI_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:01:22 1100
swis2-VHDL20_DWEI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1242
swis2-VHDL20_DWEI_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:08 1452
swis2-VHDL20_DWEI_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1177
swis2-VHDL20_DWEI_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1587
swis2-VHDL20_DWEI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1869
swis2-VHDL20_DWEI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2366
swis2-VHDL20_DWHG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:45:40 1398
swis2-VHDL20_DWHG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1395
swis2-VHDL20_DWHG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:45:01 1719
swis2-VHDL20_DWHG_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:45:09 1929
swis2-VHDL20_DWHG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:45:12 1621
swis2-VHDL20_DWHG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1448
swis2-VHDL20_DWHG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:45:19 1565
swis2-VHDL20_DWHG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1680
swis2-VHDL20_DWHH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:45:40 1504
swis2-VHDL20_DWHH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1504
swis2-VHDL20_DWHH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:45:01 1580
swis2-VHDL20_DWHH_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:45:09 1808
swis2-VHDL20_DWHH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:45:12 1532
swis2-VHDL20_DWHH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1379
swis2-VHDL20_DWHH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:45:19 1496
swis2-VHDL20_DWHH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1612
swis2-VHDL20_DWLG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1019
swis2-VHDL20_DWLG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1009
swis2-VHDL20_DWLG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1319
swis2-VHDL20_DWLG_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:31:03 1537
swis2-VHDL20_DWLG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1159
swis2-VHDL20_DWLG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1527
swis2-VHDL20_DWLG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1647
swis2-VHDL20_DWLG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:52:07 1780
swis2-VHDL20_DWLG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1508
swis2-VHDL20_DWLH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1028
swis2-VHDL20_DWLH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1133
swis2-VHDL20_DWLH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1471
swis2-VHDL20_DWLH_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:31:03 1821
swis2-VHDL20_DWLH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1427
swis2-VHDL20_DWLH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1658
swis2-VHDL20_DWLH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1954
swis2-VHDL20_DWLH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2032
swis2-VHDL20_DWLI_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1021
swis2-VHDL20_DWLI_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1011
swis2-VHDL20_DWLI_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1321
swis2-VHDL20_DWLI_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:31:03 1622
swis2-VHDL20_DWLI_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1224
swis2-VHDL20_DWLI_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1527
swis2-VHDL20_DWLI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1801
swis2-VHDL20_DWLI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1680
swis2-VHDL20_DWMO_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 832
swis2-VHDL20_DWMO_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:02 833
swis2-VHDL20_DWMO_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 993
swis2-VHDL20_DWMO_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:02 1425
swis2-VHDL20_DWMO_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1433
swis2-VHDL20_DWMO_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:06 1396
swis2-VHDL20_DWMO_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1620
swis2-VHDL20_DWMO_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1836
swis2-VHDL20_DWMP_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1023
swis2-VHDL20_DWMP_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:02 1025
swis2-VHDL20_DWMP_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:22 1212
swis2-VHDL20_DWMP_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:02 1494
swis2-VHDL20_DWMP_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1607
swis2-VHDL20_DWMP_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:06 1596
swis2-VHDL20_DWMP_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1627
swis2-VHDL20_DWMP_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1966
swis2-VHDL20_DWPG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1145
swis2-VHDL20_DWPG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1148
swis2-VHDL20_DWPG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1410
swis2-VHDL20_DWPG_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:31:03 1714
swis2-VHDL20_DWPG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1420
swis2-VHDL20_DWPG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1610
swis2-VHDL20_DWPG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1908
swis2-VHDL20_DWPG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2012
swis2-VHDL20_DWPH_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:29 1318
swis2-VHDL20_DWPH_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:12 1218
swis2-VHDL20_DWPH_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:29 1295
swis2-VHDL20_DWPH_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:31:03 1513
swis2-VHDL20_DWPH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1099
swis2-VHDL20_DWPH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1393
swis2-VHDL20_DWPH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1714
swis2-VHDL20_DWPH_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:08:21 1886
swis2-VHDL20_DWPH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1501
swis2-VHDL20_DWSG_120200-2607120200-dsw--0-ia5 12-Jul-2026 02:30:11 1039
swis2-VHDL20_DWSG_120400-2607120400-dsw--0-ia5 12-Jul-2026 05:00:16 1036
swis2-VHDL20_DWSG_120800-2607120800-dsw--0-ia5 12-Jul-2026 08:30:21 1401
swis2-VHDL20_DWSG_121800-2607121800-dsw--0-ia5 12-Jul-2026 18:30:02 1598
swis2-VHDL20_DWSG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:04 1548
swis2-VHDL20_DWSG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1638
swis2-VHDL20_DWSG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1884
swis2-VHDL20_DWSG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 09:16:06 1888
swis2-VHDL20_DWSG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2014
wst04-VHDL20_DWEG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 237268
wst04-VHDL20_DWEG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 236825
wst04-VHDL20_DWEG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:22 237708
wst04-VHDL20_DWEG_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:14 237233
wst04-VHDL20_DWEG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 236700
wst04-VHDL20_DWEG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 237388
wst04-VHDL20_DWEG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:12 238203
wst04-VHDL20_DWEG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 250466
wst04-VHDL20_DWEH_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 234671
wst04-VHDL20_DWEH_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 234216
wst04-VHDL20_DWEH_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:21 235166
wst04-VHDL20_DWEH_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:14 239855
wst04-VHDL20_DWEH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 239829
wst04-VHDL20_DWEH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 240857
wst04-VHDL20_DWEH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:12 241961
wst04-VHDL20_DWEH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 245588
wst04-VHDL20_DWEI_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 336665
wst04-VHDL20_DWEI_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 336337
wst04-VHDL20_DWEI_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:22 337311
wst04-VHDL20_DWEI_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:19 342986
wst04-VHDL20_DWEI_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 342281
wst04-VHDL20_DWEI_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 343629
wst04-VHDL20_DWEI_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:16 343974
wst04-VHDL20_DWEI_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 359237
wst04-VHDL20_DWHG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:45:40 341542
wst04-VHDL20_DWHG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:16 341344
wst04-VHDL20_DWHG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:45:21 342760
wst04-VHDL20_DWHG_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:45:21 346266
wst04-VHDL20_DWHG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:45:12 345367
wst04-VHDL20_DWHG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 344999
wst04-VHDL20_DWHG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:45:19 345744
wst04-VHDL20_DWHG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:45:11 350556
wst04-VHDL20_DWHH_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:45:40 329846
wst04-VHDL20_DWHH_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:16 225506
wst04-VHDL20_DWHH_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:45:21 330201
wst04-VHDL20_DWHH_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:45:21 335721
wst04-VHDL20_DWHH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:45:12 335576
wst04-VHDL20_DWHH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 226162
wst04-VHDL20_DWHH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:45:19 335360
wst04-VHDL20_DWHH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:45:11 332372
wst04-VHDL20_DWLG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:29 338343
wst04-VHDL20_DWLG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:41 338128
wst04-VHDL20_DWLG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:46 339243
wst04-VHDL20_DWLG_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:31:26 347724
wst04-VHDL20_DWLG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 346598
wst04-VHDL20_DWLG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:42 347336
wst04-VHDL20_DWLG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:40 348512
wst04-VHDL20_DWLG_130800_COR-2607130800-omedes-..> 13-Jul-2026 15:51:45 348285
wst04-VHDL20_DWLG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 347717
wst04-VHDL20_DWLH_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:29 339867
wst04-VHDL20_DWLH_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:41 340609
wst04-VHDL20_DWLH_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:46 340872
wst04-VHDL20_DWLH_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:31:26 345779
wst04-VHDL20_DWLH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:29 343881
wst04-VHDL20_DWLH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:42 344476
wst04-VHDL20_DWLH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:48 345852
wst04-VHDL20_DWLH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 351305
wst04-VHDL20_DWLI_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:29 336273
wst04-VHDL20_DWLI_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:41 336033
wst04-VHDL20_DWLI_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:46 381751
wst04-VHDL20_DWLI_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:31:26 340277
wst04-VHDL20_DWLI_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 338331
wst04-VHDL20_DWLI_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:42 339003
wst04-VHDL20_DWLI_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:42 384938
wst04-VHDL20_DWLI_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 348939
wst04-VHDL20_DWMO_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:20 460885
wst04-VHDL20_DWMO_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:16 459742
wst04-VHDL20_DWMO_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:21 459941
wst04-VHDL20_DWMO_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:19 351222
wst04-VHDL20_DWMO_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:19 465653
wst04-VHDL20_DWMO_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 465828
wst04-VHDL20_DWMO_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:16 464139
wst04-VHDL20_DWMO_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 355746
wst04-VHDL20_DWMP_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:20 566304
wst04-VHDL20_DWMP_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:16 565667
wst04-VHDL20_DWMP_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:21 465479
wst04-VHDL20_DWMP_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:19 473303
wst04-VHDL20_DWMP_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:19 579558
wst04-VHDL20_DWMP_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 579694
wst04-VHDL20_DWMP_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:22 472481
wst04-VHDL20_DWMP_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 461312
wst04-VHDL20_DWPG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:29 242546
wst04-VHDL20_DWPG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:32 345944
wst04-VHDL20_DWPG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:46 390731
wst04-VHDL20_DWPG_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:31:26 350610
wst04-VHDL20_DWPG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 243535
wst04-VHDL20_DWPG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:30 349729
wst04-VHDL20_DWPG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:40 395564
wst04-VHDL20_DWPG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 354333
wst04-VHDL20_DWPH_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:29 244077
wst04-VHDL20_DWPH_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:32 243821
wst04-VHDL20_DWPH_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:46 243968
wst04-VHDL20_DWPH_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:31:26 246691
wst04-VHDL20_DWPH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 245623
wst04-VHDL20_DWPH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:30 246349
wst04-VHDL20_DWPH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:42 246743
wst04-VHDL20_DWPH_130800_COR-2607130800-omedes-..> 13-Jul-2026 15:08:07 251260
wst04-VHDL20_DWPH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 250131
wst04-VHDL20_DWSG_120200-2607120200-omedes--0.pdf 12-Jul-2026 02:30:11 338776
wst04-VHDL20_DWSG_120400-2607120400-omedes--0.pdf 12-Jul-2026 05:00:12 338927
wst04-VHDL20_DWSG_120800-2607120800-omedes--0.pdf 12-Jul-2026 08:30:22 339409
wst04-VHDL20_DWSG_121800-2607121800-omedes--0.pdf 12-Jul-2026 18:30:19 351982
wst04-VHDL20_DWSG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 352578
wst04-VHDL20_DWSG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 352130
wst04-VHDL20_DWSG_130800-2607130800-omedes--0.pdf 13-Jul-2026 09:16:17 352360
wst04-VHDL20_DWSG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 355294