Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-Jul-2026 10:27:24 2369
FPDL13_DWMZ_030600 03-Jul-2026 12:41:08 4353
SXDL31_DWAV_011800 01-Jul-2026 16:04:44 7215
SXDL31_DWAV_020800 02-Jul-2026 07:38:12 12716
SXDL31_DWAV_021800 02-Jul-2026 16:06:24 11237
SXDL31_DWAV_030800 03-Jul-2026 06:42:06 7487
SXDL31_DWAV_LATEST 03-Jul-2026 06:42:06 7487
SXDL33_DWAV_020000 02-Jul-2026 10:18:34 7212
SXDL33_DWAV_030000 03-Jul-2026 10:46:19 7996
SXDL33_DWAV_LATEST 03-Jul-2026 10:46:19 7996
ber01-FWDL39_DWMS_021200-2607021200-dsw--0-ia5 02-Jul-2026 12:16:07 1553
ber01-FWDL39_DWMS_031200-2607031200-dsw--0-ia5 03-Jul-2026 11:23:07 1736
ber01-VHDL13_DWEG_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:51:21 2314
ber01-VHDL13_DWEG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:16 2353
ber01-VHDL13_DWEG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2395
ber01-VHDL13_DWEH_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:51:41 2265
ber01-VHDL13_DWEH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:22 2621
ber01-VHDL13_DWEH_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:52:42 2622
ber01-VHDL13_DWEH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2360
ber01-VHDL13_DWEI_010800_COR-2607010800-dsw--0-ia5 01-Jul-2026 18:52:01 2059
ber01-VHDL13_DWEI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:28:16 2220
ber01-VHDL13_DWEI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2057
ber01-VHDL13_DWHG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3445
ber01-VHDL13_DWHG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:07 3701
ber01-VHDL13_DWHH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3644
ber01-VHDL13_DWHH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:07 3365
ber01-VHDL13_DWLG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2378
ber01-VHDL13_DWLG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2145
ber01-VHDL13_DWLH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2652
ber01-VHDL13_DWLH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2258
ber01-VHDL13_DWLI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2264
ber01-VHDL13_DWLI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2072
ber01-VHDL13_DWMO_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2620
ber01-VHDL13_DWMO_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 2884
ber01-VHDL13_DWMP_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2862
ber01-VHDL13_DWMP_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:16:36 2866
ber01-VHDL13_DWMP_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 2851
ber01-VHDL13_DWOG_011700-2607011700-dsw--0-ia5 01-Jul-2026 18:00:03 4584
ber01-VHDL13_DWOG_011700_COR-2607011700-dsw--0-ia5 01-Jul-2026 16:21:16 4346
ber01-VHDL13_DWOG_020300-2607020300-dsw--0-ia5 02-Jul-2026 03:00:07 4351
ber01-VHDL13_DWOG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 4637
ber01-VHDL13_DWOG_021700-2607021700-dsw--0-ia5 02-Jul-2026 18:00:02 4071
ber01-VHDL13_DWOG_030300-2607030300-dsw--0-ia5 03-Jul-2026 03:00:20 3915
ber01-VHDL13_DWOG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 3867
ber01-VHDL13_DWON_011449-2607011449-dsw--0-ia5 01-Jul-2026 14:50:01 3741
ber01-VHDL13_DWON_011458-2607011458-dsw--0-ia5 01-Jul-2026 14:58:40 3735
ber01-VHDL13_DWON_011620-2607011620-dsw--0-ia5 01-Jul-2026 16:20:56 3658
ber01-VHDL13_DWON_011703-2607011703-dsw--0-ia5 01-Jul-2026 17:03:22 4018
ber01-VHDL13_DWON_020118-2607020118-dsw--0-ia5 02-Jul-2026 01:18:31 4349
ber01-VHDL13_DWON_020233-2607020233-dsw--0-ia5 02-Jul-2026 02:33:26 4349
ber01-VHDL13_DWON_020508-2607020508-dsw--0-ia5 02-Jul-2026 05:08:37 4079
ber01-VHDL13_DWON_020540-2607020540-dsw--0-ia5 02-Jul-2026 05:40:07 4138
ber01-VHDL13_DWON_020629-2607020629-dsw--0-ia5 02-Jul-2026 06:29:56 4138
ber01-VHDL13_DWON_020810-2607020810-dsw--0-ia5 02-Jul-2026 08:10:22 4138
ber01-VHDL13_DWON_021455-2607021455-dsw--0-ia5 02-Jul-2026 14:55:50 4084
ber01-VHDL13_DWON_021630-2607021630-dsw--0-ia5 02-Jul-2026 16:30:57 3853
ber01-VHDL13_DWON_021658-2607021658-dsw--0-ia5 02-Jul-2026 16:58:42 3853
ber01-VHDL13_DWON_030122-2607030122-dsw--0-ia5 03-Jul-2026 01:22:47 4157
ber01-VHDL13_DWON_030234-2607030234-dsw--0-ia5 03-Jul-2026 02:34:16 4157
ber01-VHDL13_DWON_030519-2607030519-dsw--0-ia5 03-Jul-2026 05:20:01 4059
ber01-VHDL13_DWON_030652-2607030652-dsw--0-ia5 03-Jul-2026 06:53:02 4059
ber01-VHDL13_DWON_031124-2607031124-dsw--0-ia5 03-Jul-2026 11:24:22 3977
ber01-VHDL13_DWPG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 2260
ber01-VHDL13_DWPG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2223
ber01-VHDL13_DWPH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 3232
ber01-VHDL13_DWPH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2464
ber01-VHDL13_DWSG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 2121
ber01-VHDL13_DWSG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2416
ber01-VHDL17_DWOG_021200-2607021200-dsw--0-ia5 02-Jul-2026 11:49:06 3114
ber01-VHDL17_DWOG_031200-2607031200-dsw--0-ia5 03-Jul-2026 11:40:11 3173
swis2-VHDL20_DWEG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1074
swis2-VHDL20_DWEG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 782
swis2-VHDL20_DWEG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 774
swis2-VHDL20_DWEG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 886
swis2-VHDL20_DWEG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 859
swis2-VHDL20_DWEG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 739
swis2-VHDL20_DWEG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 740
swis2-VHDL20_DWEG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 839
swis2-VHDL20_DWEH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1160
swis2-VHDL20_DWEH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 854
swis2-VHDL20_DWEH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 858
swis2-VHDL20_DWEH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 1131
swis2-VHDL20_DWEH_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:51:38 1135
swis2-VHDL20_DWEH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 976
swis2-VHDL20_DWEH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 838
swis2-VHDL20_DWEH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 841
swis2-VHDL20_DWEH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 936
swis2-VHDL20_DWEI_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1068
swis2-VHDL20_DWEI_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:01 801
swis2-VHDL20_DWEI_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:01:22 794
swis2-VHDL20_DWEI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 913
swis2-VHDL20_DWEI_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 894
swis2-VHDL20_DWEI_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 758
swis2-VHDL20_DWEI_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 759
swis2-VHDL20_DWEI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 914
swis2-VHDL20_DWHG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:45:07 1844
swis2-VHDL20_DWHG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:45:02 1450
swis2-VHDL20_DWHG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 1447
swis2-VHDL20_DWHG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:45:17 1512
swis2-VHDL20_DWHG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:45:06 1353
swis2-VHDL20_DWHG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:45:14 1377
swis2-VHDL20_DWHG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 1376
swis2-VHDL20_DWHG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:45:09 1844
swis2-VHDL20_DWHH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:45:07 2117
swis2-VHDL20_DWHH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:45:02 1735
swis2-VHDL20_DWHH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 1735
swis2-VHDL20_DWHH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:45:17 1694
swis2-VHDL20_DWHH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:45:06 1578
swis2-VHDL20_DWHH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:45:14 1447
swis2-VHDL20_DWHH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 1449
swis2-VHDL20_DWHH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:45:09 1733
swis2-VHDL20_DWLG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1180
swis2-VHDL20_DWLG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 879
swis2-VHDL20_DWLG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 865
swis2-VHDL20_DWLG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1073
swis2-VHDL20_DWLG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1394
swis2-VHDL20_DWLG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 984
swis2-VHDL20_DWLG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 917
swis2-VHDL20_DWLG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1117
swis2-VHDL20_DWLH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1485
swis2-VHDL20_DWLH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 1105
swis2-VHDL20_DWLH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 1103
swis2-VHDL20_DWLH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1306
swis2-VHDL20_DWLH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1550
swis2-VHDL20_DWLH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1083
swis2-VHDL20_DWLH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 990
swis2-VHDL20_DWLH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1256
swis2-VHDL20_DWLI_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 942
swis2-VHDL20_DWLI_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 803
swis2-VHDL20_DWLI_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 781
swis2-VHDL20_DWLI_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 904
swis2-VHDL20_DWLI_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1173
swis2-VHDL20_DWLI_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 865
swis2-VHDL20_DWLI_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 826
swis2-VHDL20_DWLI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1019
swis2-VHDL20_DWMO_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1225
swis2-VHDL20_DWMO_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:03 1106
swis2-VHDL20_DWMO_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:02 941
swis2-VHDL20_DWMO_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 862
swis2-VHDL20_DWMO_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:05 859
swis2-VHDL20_DWMO_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:06 1000
swis2-VHDL20_DWMO_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:03 897
swis2-VHDL20_DWMO_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 1133
swis2-VHDL20_DWMP_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:02 1201
swis2-VHDL20_DWMP_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:03 1115
swis2-VHDL20_DWMP_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:02 949
swis2-VHDL20_DWMP_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:06 1050
swis2-VHDL20_DWMP_020800_COR-2607020800-dsw--0-ia5 02-Jul-2026 09:16:36 3364
swis2-VHDL20_DWMP_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:05 1143
swis2-VHDL20_DWMP_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:06 1061
swis2-VHDL20_DWMP_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:03 953
swis2-VHDL20_DWMP_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 1082
swis2-VHDL20_DWPG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1131
swis2-VHDL20_DWPG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 985
swis2-VHDL20_DWPG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 894
swis2-VHDL20_DWPG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1000
swis2-VHDL20_DWPG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1415
swis2-VHDL20_DWPG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1044
swis2-VHDL20_DWPG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 979
swis2-VHDL20_DWPG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1126
swis2-VHDL20_DWPH_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:31:01 1710
swis2-VHDL20_DWPH_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:20 1555
swis2-VHDL20_DWPH_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:11 1303
swis2-VHDL20_DWPH_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:20 1496
swis2-VHDL20_DWPH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1878
swis2-VHDL20_DWPH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1881
swis2-VHDL20_DWPH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 1022
swis2-VHDL20_DWPH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1193
swis2-VHDL20_DWSG_011800-2607011800-dsw--0-ia5 01-Jul-2026 18:30:07 850
swis2-VHDL20_DWSG_020200-2607020200-dsw--0-ia5 02-Jul-2026 02:30:07 967
swis2-VHDL20_DWSG_020400-2607020400-dsw--0-ia5 02-Jul-2026 05:00:17 790
swis2-VHDL20_DWSG_020800-2607020800-dsw--0-ia5 02-Jul-2026 08:30:02 831
swis2-VHDL20_DWSG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 986
swis2-VHDL20_DWSG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 895
swis2-VHDL20_DWSG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 830
swis2-VHDL20_DWSG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 1050
wst04-VHDL20_DWEG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:11 240485
wst04-VHDL20_DWEG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 239270
wst04-VHDL20_DWEG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 239097
wst04-VHDL20_DWEG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:12 239876
wst04-VHDL20_DWEG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 234423
wst04-VHDL20_DWEG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 232895
wst04-VHDL20_DWEG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 232750
wst04-VHDL20_DWEG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 233529
wst04-VHDL20_DWEH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:11 235995
wst04-VHDL20_DWEH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 235144
wst04-VHDL20_DWEH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 235181
wst04-VHDL20_DWEH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:12 236229
wst04-VHDL20_DWEH_020800_COR-2607020800-omedes-..> 02-Jul-2026 09:51:16 231029
wst04-VHDL20_DWEH_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 231063
wst04-VHDL20_DWEH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 230051
wst04-VHDL20_DWEH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 229897
wst04-VHDL20_DWEH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 230678
wst04-VHDL20_DWEI_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:18 337710
wst04-VHDL20_DWEI_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 337077
wst04-VHDL20_DWEI_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 336855
wst04-VHDL20_DWEI_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:18 337203
wst04-VHDL20_DWEI_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:27 330492
wst04-VHDL20_DWEI_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 329419
wst04-VHDL20_DWEI_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 329274
wst04-VHDL20_DWEI_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 329581
wst04-VHDL20_DWHG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:45:12 338601
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wst04-VHDL20_DWHH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:45:12 328750
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wst04-VHDL20_DWHH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:45:17 328055
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wst04-VHDL20_DWLH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:45 330202
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wst04-VHDL20_DWLH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:27 326408
wst04-VHDL20_DWLH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:41 326120
wst04-VHDL20_DWLH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:48 326458
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wst04-VHDL20_DWLI_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 373656
wst04-VHDL20_DWMO_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 351308
wst04-VHDL20_DWMO_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 457482
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wst04-VHDL20_DWMO_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:16 439037
wst04-VHDL20_DWMO_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 438474
wst04-VHDL20_DWMO_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:17 438668
wst04-VHDL20_DWMP_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 465214
wst04-VHDL20_DWMP_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 570198
wst04-VHDL20_DWMP_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:17 570424
wst04-VHDL20_DWMP_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:20 465344
wst04-VHDL20_DWMP_020800_COR-2607020800-omedes-..> 02-Jul-2026 09:16:48 574910
wst04-VHDL20_DWMP_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:27 458306
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wst04-VHDL20_DWMP_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 560297
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wst04-VHDL20_DWPG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 234813
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wst04-VHDL20_DWPG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 375696
wst04-VHDL20_DWPH_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:31:22 239440
wst04-VHDL20_DWPH_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:20 239140
wst04-VHDL20_DWPH_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:31 238995
wst04-VHDL20_DWPH_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:40 239162
wst04-VHDL20_DWPH_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:20 237780
wst04-VHDL20_DWPH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 237695
wst04-VHDL20_DWPH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:31 235410
wst04-VHDL20_DWPH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 235663
wst04-VHDL20_DWSG_011800-2607011800-omedes--0.pdf 01-Jul-2026 18:30:15 338127
wst04-VHDL20_DWSG_020200-2607020200-omedes--0.pdf 02-Jul-2026 02:30:11 338109
wst04-VHDL20_DWSG_020400-2607020400-omedes--0.pdf 02-Jul-2026 05:00:11 337922
wst04-VHDL20_DWSG_020800-2607020800-omedes--0.pdf 02-Jul-2026 08:30:18 338043
wst04-VHDL20_DWSG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 337171
wst04-VHDL20_DWSG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 336924
wst04-VHDL20_DWSG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 336006
wst04-VHDL20_DWSG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:17 336814