Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-May-2026 13:47:58 3611
FPDL13_DWMZ_220600 22-May-2026 13:46:08 5067
SXDL31_DWAV_210800 21-May-2026 07:10:59 5360
SXDL31_DWAV_211800 21-May-2026 16:34:04 4850
SXDL31_DWAV_220800 22-May-2026 07:22:04 6334
SXDL31_DWAV_221800 22-May-2026 16:35:20 4859
SXDL31_DWAV_LATEST 22-May-2026 16:35:20 4859
SXDL33_DWAV_210000 21-May-2026 09:34:54 4733
SXDL33_DWAV_220000 22-May-2026 09:17:29 10379
SXDL33_DWAV_LATEST 22-May-2026 09:17:29 10379
ber01-FWDL39_DWMS_211230-2605211230-dsw--0-ia5 21-May-2026 10:07:07 1861
ber01-FWDL39_DWMS_221230-2605221230-dsw--0-ia5 22-May-2026 11:01:17 1427
ber01-VHDL13_DWEG_210800-2605210800-dsw--0-ia5 21-May-2026 08:28:17 2313
ber01-VHDL13_DWEG_220800-2605220800-dsw--0-ia5 22-May-2026 08:28:12 1935
ber01-VHDL13_DWEH_210800-2605210800-dsw--0-ia5 21-May-2026 08:28:21 2452
ber01-VHDL13_DWEH_220800-2605220800-dsw--0-ia5 22-May-2026 08:28:16 2009
ber01-VHDL13_DWEI_210800-2605210800-dsw--0-ia5 21-May-2026 08:28:11 2134
ber01-VHDL13_DWEI_220800-2605220800-dsw--0-ia5 22-May-2026 08:28:16 1943
ber01-VHDL13_DWHG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 2303
ber01-VHDL13_DWHG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:16 2311
ber01-VHDL13_DWHH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 2309
ber01-VHDL13_DWHH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:16 2284
ber01-VHDL13_DWLG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:00 1968
ber01-VHDL13_DWLG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2041
ber01-VHDL13_DWLH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:00 1965
ber01-VHDL13_DWLH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2278
ber01-VHDL13_DWLI_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:00 1972
ber01-VHDL13_DWLI_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2074
ber01-VHDL13_DWMO_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:16 2508
ber01-VHDL13_DWMO_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2445
ber01-VHDL13_DWMP_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 2487
ber01-VHDL13_DWMP_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2157
ber01-VHDL13_DWOG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 2616
ber01-VHDL13_DWOG_211700-2605211700-dsw--0-ia5 21-May-2026 18:00:00 2194
ber01-VHDL13_DWOG_220300-2605220300-dsw--0-ia5 22-May-2026 03:00:07 2405
ber01-VHDL13_DWOG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2606
ber01-VHDL13_DWOG_221700-2605221700-dsw--0-ia5 22-May-2026 18:00:02 2241
ber01-VHDL13_DWOG_230300-2605230300-dsw--0-ia5 23-May-2026 03:00:01 2665
ber01-VHDL13_DWON_210530-2605210530-dsw--0-ia5 21-May-2026 05:30:27 2889
ber01-VHDL13_DWON_210613-2605210613-dsw--0-ia5 21-May-2026 06:13:21 2917
ber01-VHDL13_DWON_210700-2605210700-dsw--0-ia5 21-May-2026 07:00:22 2923
ber01-VHDL13_DWON_211031-2605211031-dsw--0-ia5 21-May-2026 10:32:03 2923
ber01-VHDL13_DWON_211400-2605211400-dsw--0-ia5 21-May-2026 14:00:17 2765
ber01-VHDL13_DWON_211711-2605211711-dsw--0-ia5 21-May-2026 17:11:31 2309
ber01-VHDL13_DWON_212104-2605212104-dsw--0-ia5 21-May-2026 21:04:57 2299
ber01-VHDL13_DWON_220132-2605220132-dsw--0-ia5 22-May-2026 01:32:28 2439
ber01-VHDL13_DWON_220244-2605220244-dsw--0-ia5 22-May-2026 02:44:17 2439
ber01-VHDL13_DWON_220443-2605220443-dsw--0-ia5 22-May-2026 04:43:51 2443
ber01-VHDL13_DWON_220504-2605220504-dsw--0-ia5 22-May-2026 05:04:21 3045
ber01-VHDL13_DWON_220637-2605220637-dsw--0-ia5 22-May-2026 06:37:57 3045
ber01-VHDL13_DWON_220725-2605220725-dsw--0-ia5 22-May-2026 07:25:16 3045
ber01-VHDL13_DWON_221152-2605221152-dsw--0-ia5 22-May-2026 11:52:31 3029
ber01-VHDL13_DWON_221409-2605221409-dsw--0-ia5 22-May-2026 14:09:47 2781
ber01-VHDL13_DWON_221639-2605221639-dsw--0-ia5 22-May-2026 16:40:06 2471
ber01-VHDL13_DWON_222244-2605222244-dsw--0-ia5 22-May-2026 22:44:07 2706
ber01-VHDL13_DWON_230248-2605230248-dsw--0-ia5 23-May-2026 02:48:40 2715
ber01-VHDL13_DWPG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:00 2095
ber01-VHDL13_DWPG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2055
ber01-VHDL13_DWPH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:00 2166
ber01-VHDL13_DWPH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 2154
ber01-VHDL13_DWSG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 2160
ber01-VHDL13_DWSG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:16 2280
ber01-VHDL17_DWOG_211200-2605211200-dsw--0-ia5 21-May-2026 11:31:18 2290
ber01-VHDL17_DWOG_221200-2605221200-dsw--0-ia5 22-May-2026 11:48:27 2402
swis2-VHDL20_DWEG_210400-2605210400-dsw--0-ia5 21-May-2026 05:01:27 793
swis2-VHDL20_DWEG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 1002
swis2-VHDL20_DWEG_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 969
swis2-VHDL20_DWEG_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:02 846
swis2-VHDL20_DWEG_220400-2605220400-dsw--0-ia5 22-May-2026 05:01:25 723
swis2-VHDL20_DWEG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 869
swis2-VHDL20_DWEG_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 1038
swis2-VHDL20_DWEG_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 905
swis2-VHDL20_DWEH_210400-2605210400-dsw--0-ia5 21-May-2026 05:01:27 761
swis2-VHDL20_DWEH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 847
swis2-VHDL20_DWEH_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 832
swis2-VHDL20_DWEH_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:07 831
swis2-VHDL20_DWEH_220400-2605220400-dsw--0-ia5 22-May-2026 05:01:25 737
swis2-VHDL20_DWEH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 877
swis2-VHDL20_DWEH_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 1064
swis2-VHDL20_DWEH_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 919
swis2-VHDL20_DWEI_210400-2605210400-dsw--0-ia5 21-May-2026 05:01:27 814
swis2-VHDL20_DWEI_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 906
swis2-VHDL20_DWEI_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 991
swis2-VHDL20_DWEI_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:07 869
swis2-VHDL20_DWEI_220400-2605220400-dsw--0-ia5 22-May-2026 05:01:25 745
swis2-VHDL20_DWEI_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 891
swis2-VHDL20_DWEI_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 1060
swis2-VHDL20_DWEI_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 927
swis2-VHDL20_DWHG_210800-2605210800-dsw--0-ia5 21-May-2026 08:45:04 1164
swis2-VHDL20_DWHG_211800-2605211800-dsw--0-ia5 21-May-2026 18:45:04 1134
swis2-VHDL20_DWHG_220200-2605220200-dsw--0-ia5 22-May-2026 02:45:07 1122
swis2-VHDL20_DWHG_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:16 1119
swis2-VHDL20_DWHG_220800-2605220800-dsw--0-ia5 22-May-2026 08:45:07 1251
swis2-VHDL20_DWHG_221800-2605221800-dsw--0-ia5 22-May-2026 18:45:02 1124
swis2-VHDL20_DWHG_230200-2605230200-dsw--0-ia5 23-May-2026 02:45:06 1044
swis2-VHDL20_DWHG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 1025
swis2-VHDL20_DWHH_210800-2605210800-dsw--0-ia5 21-May-2026 08:45:04 1171
swis2-VHDL20_DWHH_211800-2605211800-dsw--0-ia5 21-May-2026 18:45:04 1140
swis2-VHDL20_DWHH_220200-2605220200-dsw--0-ia5 22-May-2026 02:45:07 1117
swis2-VHDL20_DWHH_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:16 1117
swis2-VHDL20_DWHH_220800-2605220800-dsw--0-ia5 22-May-2026 08:45:07 1252
swis2-VHDL20_DWHH_221800-2605221800-dsw--0-ia5 22-May-2026 18:45:02 1317
swis2-VHDL20_DWHH_230200-2605230200-dsw--0-ia5 23-May-2026 02:45:01 1208
swis2-VHDL20_DWHH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 1192
swis2-VHDL20_DWLG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:21 994
swis2-VHDL20_DWLG_211800-2605211800-dsw--0-ia5 21-May-2026 18:31:02 938
swis2-VHDL20_DWLG_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:22 797
swis2-VHDL20_DWLG_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:10 805
swis2-VHDL20_DWLG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:20 885
swis2-VHDL20_DWLG_221800-2605221800-dsw--0-ia5 22-May-2026 18:31:03 801
swis2-VHDL20_DWLG_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:21 916
swis2-VHDL20_DWLG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 757
swis2-VHDL20_DWLH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:21 1000
swis2-VHDL20_DWLH_211800-2605211800-dsw--0-ia5 21-May-2026 18:31:02 945
swis2-VHDL20_DWLH_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:22 804
swis2-VHDL20_DWLH_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:10 802
swis2-VHDL20_DWLH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:20 882
swis2-VHDL20_DWLH_221800-2605221800-dsw--0-ia5 22-May-2026 18:31:03 807
swis2-VHDL20_DWLH_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:21 771
swis2-VHDL20_DWLH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 736
swis2-VHDL20_DWLI_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:21 996
swis2-VHDL20_DWLI_211800-2605211800-dsw--0-ia5 21-May-2026 18:31:02 940
swis2-VHDL20_DWLI_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:22 799
swis2-VHDL20_DWLI_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:10 797
swis2-VHDL20_DWLI_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:20 877
swis2-VHDL20_DWLI_221800-2605221800-dsw--0-ia5 22-May-2026 18:31:03 802
swis2-VHDL20_DWLI_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:21 766
swis2-VHDL20_DWLI_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 731
swis2-VHDL20_DWMO_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:16 948
swis2-VHDL20_DWMO_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 856
swis2-VHDL20_DWMO_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:02 756
swis2-VHDL20_DWMO_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:06 777
swis2-VHDL20_DWMO_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 947
swis2-VHDL20_DWMO_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 900
swis2-VHDL20_DWMO_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 781
swis2-VHDL20_DWMO_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:01 798
swis2-VHDL20_DWMP_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 936
swis2-VHDL20_DWMP_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 878
swis2-VHDL20_DWMP_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:02 755
swis2-VHDL20_DWMP_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:06 793
swis2-VHDL20_DWMP_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 927
swis2-VHDL20_DWMP_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 881
swis2-VHDL20_DWMP_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 771
swis2-VHDL20_DWMP_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:01 787
swis2-VHDL20_DWPG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:21 1012
swis2-VHDL20_DWPG_211800-2605211800-dsw--0-ia5 21-May-2026 18:31:02 956
swis2-VHDL20_DWPG_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:22 815
swis2-VHDL20_DWPG_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:10 823
swis2-VHDL20_DWPG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:20 903
swis2-VHDL20_DWPG_221800-2605221800-dsw--0-ia5 22-May-2026 18:31:03 818
swis2-VHDL20_DWPG_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:21 860
swis2-VHDL20_DWPG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 747
swis2-VHDL20_DWPH_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:21 1012
swis2-VHDL20_DWPH_211800-2605211800-dsw--0-ia5 21-May-2026 18:31:02 956
swis2-VHDL20_DWPH_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:22 887
swis2-VHDL20_DWPH_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:10 823
swis2-VHDL20_DWPH_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:20 903
swis2-VHDL20_DWPH_221800-2605221800-dsw--0-ia5 22-May-2026 18:31:03 829
swis2-VHDL20_DWPH_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:21 854
swis2-VHDL20_DWPH_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 741
swis2-VHDL20_DWSG_210800-2605210800-dsw--0-ia5 21-May-2026 08:30:17 899
swis2-VHDL20_DWSG_211800-2605211800-dsw--0-ia5 21-May-2026 18:30:02 817
swis2-VHDL20_DWSG_220200-2605220200-dsw--0-ia5 22-May-2026 02:30:02 759
swis2-VHDL20_DWSG_220400-2605220400-dsw--0-ia5 22-May-2026 05:00:18 794
swis2-VHDL20_DWSG_220800-2605220800-dsw--0-ia5 22-May-2026 08:30:01 859
swis2-VHDL20_DWSG_221800-2605221800-dsw--0-ia5 22-May-2026 18:30:06 831
swis2-VHDL20_DWSG_230200-2605230200-dsw--0-ia5 23-May-2026 02:30:07 748
swis2-VHDL20_DWSG_230400-2605230400-dsw--0-ia5 23-May-2026 05:00:17 847
wst04-VHDL20_DWEG_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:16 234981
wst04-VHDL20_DWEG_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:14 236503
wst04-VHDL20_DWEG_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:12 235722
wst04-VHDL20_DWEG_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:12 235368
wst04-VHDL20_DWEG_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:16 236347
wst04-VHDL20_DWEG_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:11 237135
wst04-VHDL20_DWEG_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:13 236269
wst04-VHDL20_DWEG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 236161
wst04-VHDL20_DWEH_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:17 233913
wst04-VHDL20_DWEH_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:14 228112
wst04-VHDL20_DWEH_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:12 227808
wst04-VHDL20_DWEH_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:12 227905
wst04-VHDL20_DWEH_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:16 228905
wst04-VHDL20_DWEH_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:11 232678
wst04-VHDL20_DWEH_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:13 232481
wst04-VHDL20_DWEH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 232306
wst04-VHDL20_DWEI_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:16 333184
wst04-VHDL20_DWEI_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:16 335160
wst04-VHDL20_DWEI_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:12 334965
wst04-VHDL20_DWEI_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:12 334537
wst04-VHDL20_DWEI_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:16 335033
wst04-VHDL20_DWEI_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:16 335233
wst04-VHDL20_DWEI_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:13 334960
wst04-VHDL20_DWEI_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 334772
wst04-VHDL20_DWHG_210800-2605210800-omedes--0.pdf 21-May-2026 08:45:12 343273
wst04-VHDL20_DWHG_211800-2605211800-omedes--0.pdf 21-May-2026 18:45:12 337752
wst04-VHDL20_DWHG_220200-2605220200-omedes--0.pdf 22-May-2026 02:45:36 338287
wst04-VHDL20_DWHG_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:16 338100
wst04-VHDL20_DWHG_220800-2605220800-omedes--0.pdf 22-May-2026 08:45:12 339461
wst04-VHDL20_DWHG_221800-2605221800-omedes--0.pdf 22-May-2026 18:45:12 337916
wst04-VHDL20_DWHG_230200-2605230200-omedes--0.pdf 23-May-2026 02:45:12 337687
wst04-VHDL20_DWHG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 337434
wst04-VHDL20_DWHH_210800-2605210800-omedes--0.pdf 21-May-2026 08:45:12 329394
wst04-VHDL20_DWHH_211800-2605211800-omedes--0.pdf 21-May-2026 18:45:12 326206
wst04-VHDL20_DWHH_220200-2605220200-omedes--0.pdf 22-May-2026 02:45:36 327026
wst04-VHDL20_DWHH_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:16 225594
wst04-VHDL20_DWHH_220800-2605220800-omedes--0.pdf 22-May-2026 08:45:12 327516
wst04-VHDL20_DWHH_221800-2605221800-omedes--0.pdf 22-May-2026 18:45:12 323580
wst04-VHDL20_DWHH_230200-2605230200-omedes--0.pdf 23-May-2026 02:45:12 323396
wst04-VHDL20_DWHH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 223985
wst04-VHDL20_DWLG_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:47 332483
wst04-VHDL20_DWLG_211800-2605211800-omedes--0.pdf 21-May-2026 18:31:21 326317
wst04-VHDL20_DWLG_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:22 325440
wst04-VHDL20_DWLG_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:42 324712
wst04-VHDL20_DWLG_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:47 324770
wst04-VHDL20_DWLG_221800-2605221800-omedes--0.pdf 22-May-2026 18:31:22 324033
wst04-VHDL20_DWLG_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:33 324824
wst04-VHDL20_DWLG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 324178
wst04-VHDL20_DWLH_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:42 330250
wst04-VHDL20_DWLH_211800-2605211800-omedes--0.pdf 21-May-2026 18:31:29 328431
wst04-VHDL20_DWLH_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:22 327541
wst04-VHDL20_DWLH_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:42 326832
wst04-VHDL20_DWLH_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:43 326880
wst04-VHDL20_DWLH_221800-2605221800-omedes--0.pdf 22-May-2026 18:31:22 324942
wst04-VHDL20_DWLH_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:21 325164
wst04-VHDL20_DWLH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 324703
wst04-VHDL20_DWLI_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:42 379212
wst04-VHDL20_DWLI_211800-2605211800-omedes--0.pdf 21-May-2026 18:31:21 327751
wst04-VHDL20_DWLI_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:27 326867
wst04-VHDL20_DWLI_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:42 326119
wst04-VHDL20_DWLI_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:43 370768
wst04-VHDL20_DWLI_221800-2605221800-omedes--0.pdf 22-May-2026 18:31:31 330857
wst04-VHDL20_DWLI_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:21 331074
wst04-VHDL20_DWLI_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:41 330594
wst04-VHDL20_DWMO_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:21 450136
wst04-VHDL20_DWMO_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:16 341918
wst04-VHDL20_DWMO_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:15 446998
wst04-VHDL20_DWMO_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:16 446901
wst04-VHDL20_DWMO_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:16 447196
wst04-VHDL20_DWMO_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:16 339182
wst04-VHDL20_DWMO_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:18 442115
wst04-VHDL20_DWMO_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 442334
wst04-VHDL20_DWMP_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:21 474981
wst04-VHDL20_DWMP_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:16 450972
wst04-VHDL20_DWMP_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:15 553389
wst04-VHDL20_DWMP_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:16 553343
wst04-VHDL20_DWMP_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:23 451192
wst04-VHDL20_DWMP_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:16 447761
wst04-VHDL20_DWMP_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:18 545398
wst04-VHDL20_DWMP_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:17 545657
wst04-VHDL20_DWPG_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:42 384147
wst04-VHDL20_DWPG_211800-2605211800-omedes--0.pdf 21-May-2026 18:31:21 330453
wst04-VHDL20_DWPG_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:22 234138
wst04-VHDL20_DWPG_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:32 328920
wst04-VHDL20_DWPG_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:43 373478
wst04-VHDL20_DWPG_221800-2605221800-omedes--0.pdf 22-May-2026 18:31:22 331817
wst04-VHDL20_DWPG_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:21 235755
wst04-VHDL20_DWPG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:31 331620
wst04-VHDL20_DWPH_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:42 236869
wst04-VHDL20_DWPH_211800-2605211800-omedes--0.pdf 21-May-2026 18:31:21 238861
wst04-VHDL20_DWPH_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:22 238136
wst04-VHDL20_DWPH_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:32 237321
wst04-VHDL20_DWPH_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:43 237288
wst04-VHDL20_DWPH_221800-2605221800-omedes--0.pdf 22-May-2026 18:31:22 237535
wst04-VHDL20_DWPH_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:21 237489
wst04-VHDL20_DWPH_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:31 236803
wst04-VHDL20_DWSG_210800-2605210800-omedes--0.pdf 21-May-2026 08:30:17 335729
wst04-VHDL20_DWSG_211800-2605211800-omedes--0.pdf 21-May-2026 18:30:16 337744
wst04-VHDL20_DWSG_220200-2605220200-omedes--0.pdf 22-May-2026 02:30:12 337484
wst04-VHDL20_DWSG_220400-2605220400-omedes--0.pdf 22-May-2026 05:00:12 337351
wst04-VHDL20_DWSG_220800-2605220800-omedes--0.pdf 22-May-2026 08:30:16 337347
wst04-VHDL20_DWSG_221800-2605221800-omedes--0.pdf 22-May-2026 18:30:19 334987
wst04-VHDL20_DWSG_230200-2605230200-omedes--0.pdf 23-May-2026 02:30:13 335495
wst04-VHDL20_DWSG_230400-2605230400-omedes--0.pdf 23-May-2026 05:00:11 335700