Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_230600                                 23-Sep-2026 13:51:54                2996
FPDL13_DWMZ_240600                                 24-Sep-2026 12:20:19                4791
FPDL13_DWMZ_250600                                 25-Sep-2026 12:47:13                5662
SXDL31_DWAV_231800                                 23-Sep-2026 18:37:30                4215
SXDL31_DWAV_240800                                 24-Sep-2026 07:28:28                6541
SXDL31_DWAV_241800                                 24-Sep-2026 16:46:37                3715
SXDL31_DWAV_250800                                 25-Sep-2026 07:58:56                8834
SXDL31_DWAV_LATEST                                 25-Sep-2026 07:58:56                8834
SXDL33_DWAV_240000                                 24-Sep-2026 09:49:55                5823
SXDL33_DWAV_250000                                 25-Sep-2026 08:28:24                8042
SXDL33_DWAV_LATEST                                 25-Sep-2026 08:28:24                8042
ber01-FWDL39_DWMS_241200-2609241200-dsw--0-ia5     24-Sep-2026 11:22:13                1691
ber01-FWDL39_DWMS_251200-2609251200-dsw--0-ia5     25-Sep-2026 11:02:14                1247
ber01-VHDL13_DWEG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:28:14                3279
ber01-VHDL13_DWEG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:28:18                2658
ber01-VHDL13_DWEH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:28:18                3322
ber01-VHDL13_DWEH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:28:18                2852
ber01-VHDL13_DWEI_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:28:18                2626
ber01-VHDL13_DWEI_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:28:18                2589
ber01-VHDL13_DWHG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                3222
ber01-VHDL13_DWHG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:16                2716
ber01-VHDL13_DWHH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2991
ber01-VHDL13_DWHH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:16                2633
ber01-VHDL13_DWLG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2269
ber01-VHDL13_DWLG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                2511
ber01-VHDL13_DWLH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2295
ber01-VHDL13_DWLH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                2599
ber01-VHDL13_DWLI_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2064
ber01-VHDL13_DWLI_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                2365
ber01-VHDL13_DWMO_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                3219
ber01-VHDL13_DWMO_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                2966
ber01-VHDL13_DWMP_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                3488
ber01-VHDL13_DWMP_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                2751
ber01-VHDL13_DWOG_231700-2609231700-dsw--0-ia5     23-Sep-2026 18:00:03                3771
ber01-VHDL13_DWOG_240300-2609240300-dsw--0-ia5     24-Sep-2026 03:00:10                3763
ber01-VHDL13_DWOG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                3728
ber01-VHDL13_DWOG_241700-2609241700-dsw--0-ia5     24-Sep-2026 18:00:06                2857
ber01-VHDL13_DWOG_250300-2609250300-dsw--0-ia5     25-Sep-2026 03:00:27                3215
ber01-VHDL13_DWOG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                3215
ber01-VHDL13_DWON_231432-2609231432-dsw--0-ia5     23-Sep-2026 14:33:18                4273
ber01-VHDL13_DWON_231456-2609231456-dsw--0-ia5     23-Sep-2026 14:58:02                4273
ber01-VHDL13_DWON_231729-2609231729-dsw--0-ia5     23-Sep-2026 17:30:09                3422
ber01-VHDL13_DWON_231838-2609231838-dsw--0-ia5     23-Sep-2026 18:38:36                3409
ber01-VHDL13_DWON_231943-2609231943-dsw--0-ia5     23-Sep-2026 19:43:44                3409
ber01-VHDL13_DWON_240003-2609240003-dsw--0-ia5     24-Sep-2026 00:03:58                3932
ber01-VHDL13_DWON_240201-2609240201-dsw--0-ia5     24-Sep-2026 02:01:49                3982
ber01-VHDL13_DWON_240326-2609240326-dsw--0-ia5     24-Sep-2026 03:27:03                3982
ber01-VHDL13_DWON_240525-2609240525-dsw--0-ia5     24-Sep-2026 05:25:28                4104
ber01-VHDL13_DWON_240611-2609240611-dsw--0-ia5     24-Sep-2026 06:11:14                4066
ber01-VHDL13_DWON_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:00:38                4066
ber01-VHDL13_DWON_241456-2609241456-dsw--0-ia5     24-Sep-2026 14:58:02                3755
ber01-VHDL13_DWON_241654-2609241654-dsw--0-ia5     24-Sep-2026 16:54:48                3122
ber01-VHDL13_DWON_242030-2609242030-dsw--0-ia5     24-Sep-2026 20:30:44                3118
ber01-VHDL13_DWON_250119-2609250119-dsw--0-ia5     25-Sep-2026 01:19:28                3043
ber01-VHDL13_DWON_250238-2609250238-dsw--0-ia5     25-Sep-2026 02:40:34                3296
ber01-VHDL13_DWON_250529-2609250529-dsw--0-ia5     25-Sep-2026 05:29:29                3136
ber01-VHDL13_DWON_250535-2609250535-dsw--0-ia5     25-Sep-2026 05:35:13                3173
ber01-VHDL13_DWON_250811-2609250811-dsw--0-ia5     25-Sep-2026 08:11:39                3173
ber01-VHDL13_DWPG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2077
ber01-VHDL13_DWPG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                2708
ber01-VHDL13_DWPH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2366
ber01-VHDL13_DWPH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:04                2666
ber01-VHDL13_DWSG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                2557
ber01-VHDL13_DWSG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                2170
ber01-VHDL17_DWOG_241200-2609241200-dsw--0-ia5     24-Sep-2026 11:46:45                2492
ber01-VHDL17_DWOG_251200-2609251200-dsw--0-ia5     25-Sep-2026 09:16:08                3149
swis2-VHDL20_DWEG_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:03                1210
swis2-VHDL20_DWEG_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                 970
swis2-VHDL20_DWEG_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:01:23                1011
swis2-VHDL20_DWEG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                1406
swis2-VHDL20_DWEG_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                1113
swis2-VHDL20_DWEG_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:04                 980
swis2-VHDL20_DWEG_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:01:22                 942
swis2-VHDL20_DWEG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                1193
swis2-VHDL20_DWEH_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:09                1242
swis2-VHDL20_DWEH_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                 989
swis2-VHDL20_DWEH_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:01:23                1030
swis2-VHDL20_DWEH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                1404
swis2-VHDL20_DWEH_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                1128
swis2-VHDL20_DWEH_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:04                 961
swis2-VHDL20_DWEH_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:01:22                 959
swis2-VHDL20_DWEH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                1189
swis2-VHDL20_DWEI_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:03                1027
swis2-VHDL20_DWEI_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                 783
swis2-VHDL20_DWEI_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:01:23                 824
swis2-VHDL20_DWEI_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                 989
swis2-VHDL20_DWEI_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                 967
swis2-VHDL20_DWEI_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:04                 828
swis2-VHDL20_DWEI_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:01:22                 777
swis2-VHDL20_DWEI_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                1059
swis2-VHDL20_DWHG_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:45:19                1645
swis2-VHDL20_DWHG_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:47:22                1461
swis2-VHDL20_DWHG_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                1195
swis2-VHDL20_DWHG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:45:24                1398
swis2-VHDL20_DWHG_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:45:22                1262
swis2-VHDL20_DWHG_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:06                1162
swis2-VHDL20_DWHG_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:47:34                1141
swis2-VHDL20_DWHG_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:18                1138
swis2-VHDL20_DWHG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:45:21                1075
swis2-VHDL20_DWHH_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:45:19                1902
swis2-VHDL20_DWHH_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:47:22                1649
swis2-VHDL20_DWHH_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                1383
swis2-VHDL20_DWHH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:45:24                1502
swis2-VHDL20_DWHH_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:45:22                1116
swis2-VHDL20_DWHH_241800_COR-2609241800-dsw--0-ia5 24-Sep-2026 19:06:29                1011
swis2-VHDL20_DWHH_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:47:34                 972
swis2-VHDL20_DWHH_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:18                 972
swis2-VHDL20_DWHH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:45:21                1085
swis2-VHDL20_DWLG_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:31:26                1091
swis2-VHDL20_DWLG_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:30                 845
swis2-VHDL20_DWLG_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                1033
swis2-VHDL20_DWLG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:32                1182
swis2-VHDL20_DWLG_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:31:14                1032
swis2-VHDL20_DWLG_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:35                 871
swis2-VHDL20_DWLG_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:14                 921
swis2-VHDL20_DWLG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:26                 996
swis2-VHDL20_DWLH_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:31:26                1141
swis2-VHDL20_DWLH_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:31                 884
swis2-VHDL20_DWLH_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                 951
swis2-VHDL20_DWLH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:32                1033
swis2-VHDL20_DWLH_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:31:14                 972
swis2-VHDL20_DWLH_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:35                 878
swis2-VHDL20_DWLH_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:14                 901
swis2-VHDL20_DWLH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:26                 976
swis2-VHDL20_DWLI_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:31:26                 898
swis2-VHDL20_DWLI_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:31                 778
swis2-VHDL20_DWLI_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                 909
swis2-VHDL20_DWLI_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:32                 983
swis2-VHDL20_DWLI_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:31:14                 969
swis2-VHDL20_DWLI_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:35                 967
swis2-VHDL20_DWLI_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:14                 941
swis2-VHDL20_DWLI_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:26                 995
swis2-VHDL20_DWMO_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:09                1466
swis2-VHDL20_DWMO_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                1360
swis2-VHDL20_DWMO_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:03                1359
swis2-VHDL20_DWMO_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                1494
swis2-VHDL20_DWMO_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                1211
swis2-VHDL20_DWMO_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:02                1101
swis2-VHDL20_DWMO_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:04                1124
swis2-VHDL20_DWMO_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                1276
swis2-VHDL20_DWMP_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:09                1735
swis2-VHDL20_DWMP_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                1608
swis2-VHDL20_DWMP_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:03                1743
swis2-VHDL20_DWMP_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                1850
swis2-VHDL20_DWMP_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                1254
swis2-VHDL20_DWMP_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:02                1070
swis2-VHDL20_DWMP_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:04                1098
swis2-VHDL20_DWMP_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                1320
swis2-VHDL20_DWPG_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:31:26                1039
swis2-VHDL20_DWPG_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:30                 799
swis2-VHDL20_DWPG_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                 913
swis2-VHDL20_DWPG_240400_COR-2609240400-dsw--0-ia5 24-Sep-2026 05:09:08                 917
swis2-VHDL20_DWPG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:32                1060
swis2-VHDL20_DWPG_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:31:14                1046
swis2-VHDL20_DWPG_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:35                 905
swis2-VHDL20_DWPG_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:14                 921
swis2-VHDL20_DWPG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:26                1019
swis2-VHDL20_DWPH_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:31:26                1153
swis2-VHDL20_DWPH_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:30                 942
swis2-VHDL20_DWPH_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:14                1003
swis2-VHDL20_DWPH_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:32                1152
swis2-VHDL20_DWPH_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:31:14                1048
swis2-VHDL20_DWPH_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:35                 792
swis2-VHDL20_DWPH_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:14                 943
swis2-VHDL20_DWPH_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:26                1042
swis2-VHDL20_DWSG_231800-2609231800-dsw--0-ia5     23-Sep-2026 18:30:09                1246
swis2-VHDL20_DWSG_240200-2609240200-dsw--0-ia5     24-Sep-2026 02:30:04                1124
swis2-VHDL20_DWSG_240400-2609240400-dsw--0-ia5     24-Sep-2026 05:00:18                1165
swis2-VHDL20_DWSG_240800-2609240800-dsw--0-ia5     24-Sep-2026 08:30:09                1232
swis2-VHDL20_DWSG_241800-2609241800-dsw--0-ia5     24-Sep-2026 18:30:04                1053
swis2-VHDL20_DWSG_250200-2609250200-dsw--0-ia5     25-Sep-2026 02:30:04                1028
swis2-VHDL20_DWSG_250400-2609250400-dsw--0-ia5     25-Sep-2026 05:00:20                 869
swis2-VHDL20_DWSG_250800-2609250800-dsw--0-ia5     25-Sep-2026 08:30:06                 930
wst04-VHDL20_DWEG_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:19              242877
wst04-VHDL20_DWEG_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:21              241678
wst04-VHDL20_DWEG_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:14              241756
wst04-VHDL20_DWEG_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:20              243602
wst04-VHDL20_DWEG_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              242333
wst04-VHDL20_DWEG_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:14              241400
wst04-VHDL20_DWEG_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:14              241019
wst04-VHDL20_DWEG_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              241929
wst04-VHDL20_DWEH_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:13              235291
wst04-VHDL20_DWEH_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:21              234385
wst04-VHDL20_DWEH_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:14              234669
wst04-VHDL20_DWEH_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:20              236531
wst04-VHDL20_DWEH_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              235220
wst04-VHDL20_DWEH_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:14              234546
wst04-VHDL20_DWEH_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:14              234472
wst04-VHDL20_DWEH_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              235272
wst04-VHDL20_DWEI_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:19              347158
wst04-VHDL20_DWEI_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:30              346416
wst04-VHDL20_DWEI_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:20              346440
wst04-VHDL20_DWEI_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:20              346658
wst04-VHDL20_DWEI_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              346768
wst04-VHDL20_DWEI_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:14              346446
wst04-VHDL20_DWEI_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:20              346173
wst04-VHDL20_DWEI_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              346995
wst04-VHDL20_DWHG_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:45:19              349964
wst04-VHDL20_DWHG_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:47:22              349474
wst04-VHDL20_DWHG_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:18              348663
wst04-VHDL20_DWHG_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:45:25              349314
wst04-VHDL20_DWHG_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:45:22              347754
wst04-VHDL20_DWHG_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:47:34              347802
wst04-VHDL20_DWHG_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:18              347582
wst04-VHDL20_DWHG_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:45:21              347763
wst04-VHDL20_DWHH_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:45:19              336288
wst04-VHDL20_DWHH_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:47:22              335357
wst04-VHDL20_DWHH_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:18              230610
wst04-VHDL20_DWHH_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:45:24              334601
wst04-VHDL20_DWHH_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:45:22              332929
wst04-VHDL20_DWHH_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:47:34              333134
wst04-VHDL20_DWHH_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:18              228990
wst04-VHDL20_DWHH_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:45:21              332906
wst04-VHDL20_DWLG_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:31:28              334185
wst04-VHDL20_DWLG_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:31              333726
wst04-VHDL20_DWLG_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:44              334349
wst04-VHDL20_DWLG_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:56              334584
wst04-VHDL20_DWLG_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:31:24              333054
wst04-VHDL20_DWLG_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:35              333583
wst04-VHDL20_DWLG_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:44              333166
wst04-VHDL20_DWLG_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:54              333223
wst04-VHDL20_DWLH_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:31:28              338171
wst04-VHDL20_DWLH_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:31              337759
wst04-VHDL20_DWLH_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:44              337870
wst04-VHDL20_DWLH_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:51              338093
wst04-VHDL20_DWLH_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:31:24              337005
wst04-VHDL20_DWLH_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:35              337606
wst04-VHDL20_DWLH_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:44              337204
wst04-VHDL20_DWLH_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:54              337247
wst04-VHDL20_DWLI_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:31:28              338729
wst04-VHDL20_DWLI_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:40              338706
wst04-VHDL20_DWLI_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:44              338883
wst04-VHDL20_DWLI_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:56              383653
wst04-VHDL20_DWLI_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:31:24              338031
wst04-VHDL20_DWLI_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:35              338795
wst04-VHDL20_DWLI_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:44              338288
wst04-VHDL20_DWLI_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:54              382924
wst04-VHDL20_DWMO_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:19              354421
wst04-VHDL20_DWMO_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:21              456408
wst04-VHDL20_DWMO_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:14              456369
wst04-VHDL20_DWMO_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:20              456575
wst04-VHDL20_DWMO_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              354194
wst04-VHDL20_DWMO_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:24              455872
wst04-VHDL20_DWMO_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:14              455831
wst04-VHDL20_DWMO_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              455864
wst04-VHDL20_DWMP_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:19              461462
wst04-VHDL20_DWMP_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:31              563818
wst04-VHDL20_DWMP_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:18              564391
wst04-VHDL20_DWMP_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:32              462952
wst04-VHDL20_DWMP_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              461094
wst04-VHDL20_DWMP_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:24              562232
wst04-VHDL20_DWMP_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:18              562245
wst04-VHDL20_DWMP_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              461126
wst04-VHDL20_DWPG_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:31:28              348567
wst04-VHDL20_DWPG_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:31              244510
wst04-VHDL20_DWPG_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:34              348292
wst04-VHDL20_DWPG_240400_COR-2609240400-omedes-..> 24-Sep-2026 05:08:54              348293
wst04-VHDL20_DWPG_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:51              393061
wst04-VHDL20_DWPG_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:31:28              347451
wst04-VHDL20_DWPG_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:35              244427
wst04-VHDL20_DWPG_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:34              347664
wst04-VHDL20_DWPG_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:54              392265
wst04-VHDL20_DWPH_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:31:28              243501
wst04-VHDL20_DWPH_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:31              243172
wst04-VHDL20_DWPH_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:34              243699
wst04-VHDL20_DWPH_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:51              243946
wst04-VHDL20_DWPH_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:31:24              242383
wst04-VHDL20_DWPH_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:35              242692
wst04-VHDL20_DWPH_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:34              242558
wst04-VHDL20_DWPH_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:54              242554
wst04-VHDL20_DWSG_231800-2609231800-omedes--0.pdf  23-Sep-2026 18:30:13              347477
wst04-VHDL20_DWSG_240200-2609240200-omedes--0.pdf  24-Sep-2026 02:30:21              347211
wst04-VHDL20_DWSG_240400-2609240400-omedes--0.pdf  24-Sep-2026 05:00:14              347590
wst04-VHDL20_DWSG_240800-2609240800-omedes--0.pdf  24-Sep-2026 08:30:20              347806
wst04-VHDL20_DWSG_241800-2609241800-omedes--0.pdf  24-Sep-2026 18:30:25              347685
wst04-VHDL20_DWSG_250200-2609250200-omedes--0.pdf  25-Sep-2026 02:30:12              347591
wst04-VHDL20_DWSG_250400-2609250400-omedes--0.pdf  25-Sep-2026 05:00:14              346350
wst04-VHDL20_DWSG_250800-2609250800-omedes--0.pdf  25-Sep-2026 08:30:26              346364