Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-May-2026 08:56:09 2451
FPDL13_DWMZ_030600 03-May-2026 12:30:17 17108
SXDL31_DWAV_020800 02-May-2026 07:33:29 8938
SXDL31_DWAV_021800 02-May-2026 17:22:13 8270
SXDL31_DWAV_030800 03-May-2026 09:04:56 7848
SXDL31_DWAV_031800 03-May-2026 15:22:35 8449
SXDL31_DWAV_LATEST 03-May-2026 15:22:35 8449
SXDL33_DWAV_020000 02-May-2026 10:05:43 15310
SXDL33_DWAV_030000 03-May-2026 10:04:56 9348
SXDL33_DWAV_LATEST 03-May-2026 10:04:56 9348
ber01-FWDL39_DWMS_021230-2605021230-dsw--0-ia5 02-May-2026 11:13:01 1251
ber01-FWDL39_DWMS_031230-2605031230-dsw--0-ia5 03-May-2026 11:38:31 929
ber01-VHDL13_DWEG_020800-2605020800-dsw--0-ia5 02-May-2026 08:28:26 2925
ber01-VHDL13_DWEG_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:33:06 2929
ber01-VHDL13_DWEG_030800-2605030800-dsw--0-ia5 03-May-2026 08:28:27 2775
ber01-VHDL13_DWEH_020800-2605020800-dsw--0-ia5 02-May-2026 08:28:22 3172
ber01-VHDL13_DWEH_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:33:06 3176
ber01-VHDL13_DWEH_030800-2605030800-dsw--0-ia5 03-May-2026 08:28:23 2977
ber01-VHDL13_DWEI_020800-2605020800-dsw--0-ia5 02-May-2026 08:28:26 3219
ber01-VHDL13_DWEI_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:33:06 3273
ber01-VHDL13_DWEI_030800-2605030800-dsw--0-ia5 03-May-2026 08:28:27 2711
ber01-VHDL13_DWHG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 3907
ber01-VHDL13_DWHG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 3612
ber01-VHDL13_DWHG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 11:18:21 3907
ber01-VHDL13_DWHH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 3841
ber01-VHDL13_DWHH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 3412
ber01-VHDL13_DWLG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 2451
ber01-VHDL13_DWLG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 2430
ber01-VHDL13_DWLH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 2769
ber01-VHDL13_DWLH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 2658
ber01-VHDL13_DWLI_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 2666
ber01-VHDL13_DWLI_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 2470
ber01-VHDL13_DWMO_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 3045
ber01-VHDL13_DWMO_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 3587
ber01-VHDL13_DWMP_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 3112
ber01-VHDL13_DWMP_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 3389
ber01-VHDL13_DWOG_020300-2605020300-dsw--0-ia5 02-May-2026 03:00:12 4056
ber01-VHDL13_DWOG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 4464
ber01-VHDL13_DWOG_021700-2605021700-dsw--0-ia5 02-May-2026 18:00:06 4005
ber01-VHDL13_DWOG_021700_COR-2605021700-dsw--0-ia5 02-May-2026 20:37:20 4312
ber01-VHDL13_DWOG_030300-2605030300-dsw--0-ia5 03-May-2026 03:00:06 4679
ber01-VHDL13_DWOG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 4641
ber01-VHDL13_DWOG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 13:24:11 5434
ber01-VHDL13_DWOG_031700-2605031700-dsw--0-ia5 03-May-2026 18:00:07 5038
ber01-VHDL13_DWOG_031700_COR-2605031700-dsw--0-ia5 03-May-2026 17:39:47 5041
ber01-VHDL13_DWON_020241-2605020241-dsw--0-ia5 02-May-2026 02:41:50 4159
ber01-VHDL13_DWON_020529-2605020529-dsw--0-ia5 02-May-2026 05:29:46 4159
ber01-VHDL13_DWON_020541-2605020541-dsw--0-ia5 02-May-2026 05:41:41 3919
ber01-VHDL13_DWON_020609-2605020609-dsw--0-ia5 02-May-2026 06:09:31 4385
ber01-VHDL13_DWON_021219-2605021219-dsw--0-ia5 02-May-2026 12:19:57 4385
ber01-VHDL13_DWON_021500-2605021500-dsw--0-ia5 02-May-2026 15:00:47 3474
ber01-VHDL13_DWON_021743-2605021743-dsw--0-ia5 02-May-2026 17:43:16 3530
ber01-VHDL13_DWON_022036-2605022036-dsw--0-ia5 02-May-2026 20:37:05 3633
ber01-VHDL13_DWON_030014-2605030014-dsw--0-ia5 03-May-2026 00:14:36 3898
ber01-VHDL13_DWON_030245-2605030245-dsw--0-ia5 03-May-2026 02:45:47 3898
ber01-VHDL13_DWON_030522-2605030522-dsw--0-ia5 03-May-2026 05:22:17 4598
ber01-VHDL13_DWON_030623-2605030623-dsw--0-ia5 03-May-2026 06:23:08 4598
ber01-VHDL13_DWON_030828-2605030828-dsw--0-ia5 03-May-2026 08:28:41 4598
ber01-VHDL13_DWON_030853-2605030853-dsw--0-ia5 03-May-2026 08:53:49 4598
ber01-VHDL13_DWON_031321-2605031321-dsw--0-ia5 03-May-2026 13:21:57 4640
ber01-VHDL13_DWON_031455-2605031455-dsw--0-ia5 03-May-2026 14:55:20 4616
ber01-VHDL13_DWON_031627-2605031627-dsw--0-ia5 03-May-2026 16:28:01 4536
ber01-VHDL13_DWON_031739-2605031739-dsw--0-ia5 03-May-2026 17:39:33 4536
ber01-VHDL13_DWPG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 2505
ber01-VHDL13_DWPG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 2918
ber01-VHDL13_DWPH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:01 2932
ber01-VHDL13_DWPH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 3151
ber01-VHDL13_DWSG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 2653
ber01-VHDL13_DWSG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 2879
ber01-VHDL13_DWSG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 15:17:51 2979
ber01-VHDL17_DWOG_021200-2605021200-dsw--0-ia5 02-May-2026 11:45:22 3520
ber01-VHDL17_DWOG_031200-2605031200-dsw--0-ia5 03-May-2026 11:47:57 3054
swis2-VHDL20_DWEG_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:07 1274
swis2-VHDL20_DWEG_020400-2605020400-dsw--0-ia5 02-May-2026 05:02:12 1271
swis2-VHDL20_DWEG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1527
swis2-VHDL20_DWEG_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:32:51 1531
swis2-VHDL20_DWEG_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:08 1466
swis2-VHDL20_DWEG_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:10 1278
swis2-VHDL20_DWEG_030400-2605030400-dsw--0-ia5 03-May-2026 05:02:12 1298
swis2-VHDL20_DWEG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1582
swis2-VHDL20_DWEG_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1491
swis2-VHDL20_DWEH_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:07 1422
swis2-VHDL20_DWEH_020400-2605020400-dsw--0-ia5 02-May-2026 05:02:12 1497
swis2-VHDL20_DWEH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1748
swis2-VHDL20_DWEH_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:32:48 1752
swis2-VHDL20_DWEH_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:08 1901
swis2-VHDL20_DWEH_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:10 1494
swis2-VHDL20_DWEH_030400-2605030400-dsw--0-ia5 03-May-2026 05:02:16 1611
swis2-VHDL20_DWEH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1966
swis2-VHDL20_DWEH_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1799
swis2-VHDL20_DWEI_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:07 1548
swis2-VHDL20_DWEI_020400-2605020400-dsw--0-ia5 02-May-2026 05:02:12 1545
swis2-VHDL20_DWEI_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1851
swis2-VHDL20_DWEI_020800_COR-2605020800-dsw--0-ia5 02-May-2026 08:32:40 1855
swis2-VHDL20_DWEI_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:08 1531
swis2-VHDL20_DWEI_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:10 1180
swis2-VHDL20_DWEI_030400-2605030400-dsw--0-ia5 03-May-2026 05:02:16 1246
swis2-VHDL20_DWEI_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1526
swis2-VHDL20_DWEI_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1488
swis2-VHDL20_DWHG_020200-2605020200-dsw--0-ia5 02-May-2026 02:45:21 1862
swis2-VHDL20_DWHG_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:06 1755
swis2-VHDL20_DWHG_020800-2605020800-dsw--0-ia5 02-May-2026 08:45:01 2252
swis2-VHDL20_DWHG_021800-2605021800-dsw--0-ia5 02-May-2026 18:45:02 2381
swis2-VHDL20_DWHG_030200-2605030200-dsw--0-ia5 03-May-2026 02:45:09 1759
swis2-VHDL20_DWHG_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:07 1854
swis2-VHDL20_DWHG_030800-2605030800-dsw--0-ia5 03-May-2026 08:45:01 2474
swis2-VHDL20_DWHG_031800-2605031800-dsw--0-ia5 03-May-2026 18:45:01 2062
swis2-VHDL20_DWHH_020200-2605020200-dsw--0-ia5 02-May-2026 02:45:21 1774
swis2-VHDL20_DWHH_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:06 1749
swis2-VHDL20_DWHH_020800-2605020800-dsw--0-ia5 02-May-2026 08:45:01 1948
swis2-VHDL20_DWHH_021800-2605021800-dsw--0-ia5 02-May-2026 18:45:02 1916
swis2-VHDL20_DWHH_030200-2605030200-dsw--0-ia5 03-May-2026 02:45:09 1504
swis2-VHDL20_DWHH_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:07 1590
swis2-VHDL20_DWHH_030800-2605030800-dsw--0-ia5 03-May-2026 08:45:01 1665
swis2-VHDL20_DWHH_031800-2605031800-dsw--0-ia5 03-May-2026 18:45:01 1433
swis2-VHDL20_DWLG_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:27 849
swis2-VHDL20_DWLG_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:12 869
swis2-VHDL20_DWLG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:27 1203
swis2-VHDL20_DWLG_021800-2605021800-dsw--0-ia5 02-May-2026 18:31:02 1480
swis2-VHDL20_DWLG_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:24 1087
swis2-VHDL20_DWLG_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:11 1121
swis2-VHDL20_DWLG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:21 1322
swis2-VHDL20_DWLG_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1142
swis2-VHDL20_DWLH_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:27 948
swis2-VHDL20_DWLH_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:12 926
swis2-VHDL20_DWLH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:27 1221
swis2-VHDL20_DWLH_021800-2605021800-dsw--0-ia5 02-May-2026 18:31:02 1487
swis2-VHDL20_DWLH_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:24 1094
swis2-VHDL20_DWLH_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:11 1285
swis2-VHDL20_DWLH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:21 1400
swis2-VHDL20_DWLH_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1217
swis2-VHDL20_DWLI_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:27 851
swis2-VHDL20_DWLI_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:12 871
swis2-VHDL20_DWLI_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:27 1205
swis2-VHDL20_DWLI_021800-2605021800-dsw--0-ia5 02-May-2026 18:31:02 1482
swis2-VHDL20_DWLI_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:24 1089
swis2-VHDL20_DWLI_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:11 1074
swis2-VHDL20_DWLI_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:21 1324
swis2-VHDL20_DWLI_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1161
swis2-VHDL20_DWMO_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:07 1161
swis2-VHDL20_DWMO_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:06 1090
swis2-VHDL20_DWMO_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1106
swis2-VHDL20_DWMO_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:05 1305
swis2-VHDL20_DWMO_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:10 1131
swis2-VHDL20_DWMO_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:07 1211
swis2-VHDL20_DWMO_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1589
swis2-VHDL20_DWMO_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:06 1446
swis2-VHDL20_DWMP_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:07 1103
swis2-VHDL20_DWMP_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:06 1067
swis2-VHDL20_DWMP_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1121
swis2-VHDL20_DWMP_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:05 1253
swis2-VHDL20_DWMP_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:05 1069
swis2-VHDL20_DWMP_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:07 1077
swis2-VHDL20_DWMP_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1477
swis2-VHDL20_DWMP_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:06 1706
swis2-VHDL20_DWPG_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:27 960
swis2-VHDL20_DWPG_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:12 884
swis2-VHDL20_DWPG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:27 1231
swis2-VHDL20_DWPG_021800-2605021800-dsw--0-ia5 02-May-2026 18:31:02 1498
swis2-VHDL20_DWPG_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:24 1119
swis2-VHDL20_DWPG_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:11 1140
swis2-VHDL20_DWPG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:21 1512
swis2-VHDL20_DWPG_030800_COR-2605030800-dsw--0-ia5 03-May-2026 08:38:05 1691
swis2-VHDL20_DWPG_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1237
swis2-VHDL20_DWPH_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:27 979
swis2-VHDL20_DWPH_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:12 1152
swis2-VHDL20_DWPH_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:27 1304
swis2-VHDL20_DWPH_021800-2605021800-dsw--0-ia5 02-May-2026 18:31:02 1295
swis2-VHDL20_DWPH_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:24 1081
swis2-VHDL20_DWPH_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:11 1303
swis2-VHDL20_DWPH_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:21 1404
swis2-VHDL20_DWPH_031800-2605031800-dsw--0-ia5 03-May-2026 18:31:04 1295
swis2-VHDL20_DWSG_020200-2605020200-dsw--0-ia5 02-May-2026 02:30:02 1127
swis2-VHDL20_DWSG_020400-2605020400-dsw--0-ia5 02-May-2026 05:00:18 1026
swis2-VHDL20_DWSG_020800-2605020800-dsw--0-ia5 02-May-2026 08:30:08 1172
swis2-VHDL20_DWSG_021800-2605021800-dsw--0-ia5 02-May-2026 18:30:01 1158
swis2-VHDL20_DWSG_030200-2605030200-dsw--0-ia5 03-May-2026 02:30:05 1113
swis2-VHDL20_DWSG_030400-2605030400-dsw--0-ia5 03-May-2026 05:00:19 1191
swis2-VHDL20_DWSG_030800-2605030800-dsw--0-ia5 03-May-2026 08:30:09 1376
swis2-VHDL20_DWSG_031800-2605031800-dsw--0-ia5 03-May-2026 18:30:02 1442
wst04-VHDL20_DWEG_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:17 240688
wst04-VHDL20_DWEG_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:12 240070
wst04-VHDL20_DWEG_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:11 240889
wst04-VHDL20_DWEG_020800_COR-2605020800-omedes-..> 02-May-2026 08:33:06 240889
wst04-VHDL20_DWEG_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:12 245513
wst04-VHDL20_DWEG_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:12 244376
wst04-VHDL20_DWEG_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:17 244632
wst04-VHDL20_DWEG_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:11 245744
wst04-VHDL20_DWEG_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:22 242185
wst04-VHDL20_DWEH_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:12 237682
wst04-VHDL20_DWEH_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:16 237016
wst04-VHDL20_DWEH_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:11 237949
wst04-VHDL20_DWEH_020800_COR-2605020800-omedes-..> 02-May-2026 08:33:06 237949
wst04-VHDL20_DWEH_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:12 245678
wst04-VHDL20_DWEH_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:17 244794
wst04-VHDL20_DWEH_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:11 244735
wst04-VHDL20_DWEH_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:11 246084
wst04-VHDL20_DWEH_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:12 238825
wst04-VHDL20_DWEI_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:17 341478
wst04-VHDL20_DWEI_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:22 340744
wst04-VHDL20_DWEI_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:21 341815
wst04-VHDL20_DWEI_020800_COR-2605020800-omedes-..> 02-May-2026 08:33:06 341815
wst04-VHDL20_DWEI_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:22 347619
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wst04-VHDL20_DWEI_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:21 345955
wst04-VHDL20_DWEI_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:17 347308
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wst04-VHDL20_DWHG_020800-2605020800-omedes--0.pdf 02-May-2026 08:45:17 344030
wst04-VHDL20_DWHG_021800-2605021800-omedes--0.pdf 02-May-2026 18:45:12 346237
wst04-VHDL20_DWHG_030200-2605030200-omedes--0.pdf 03-May-2026 02:45:28 343886
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wst04-VHDL20_DWHG_030800-2605030800-omedes--0.pdf 03-May-2026 08:45:12 347207
wst04-VHDL20_DWHG_031800-2605031800-omedes--0.pdf 03-May-2026 18:45:12 343809
wst04-VHDL20_DWHH_020200-2605020200-omedes--0.pdf 02-May-2026 02:45:21 329592
wst04-VHDL20_DWHH_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:12 226879
wst04-VHDL20_DWHH_020800-2605020800-omedes--0.pdf 02-May-2026 08:45:17 330828
wst04-VHDL20_DWHH_021800-2605021800-omedes--0.pdf 02-May-2026 18:45:12 332306
wst04-VHDL20_DWHH_030200-2605030200-omedes--0.pdf 03-May-2026 02:45:28 330700
wst04-VHDL20_DWHH_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:13 230069
wst04-VHDL20_DWHH_030800-2605030800-omedes--0.pdf 03-May-2026 08:45:12 332053
wst04-VHDL20_DWHH_031800-2605031800-omedes--0.pdf 03-May-2026 18:45:12 333286
wst04-VHDL20_DWLG_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:27 332770
wst04-VHDL20_DWLG_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:42 332128
wst04-VHDL20_DWLG_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:49 333658
wst04-VHDL20_DWLG_021800-2605021800-omedes--0.pdf 02-May-2026 18:31:27 337542
wst04-VHDL20_DWLG_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:26 337295
wst04-VHDL20_DWLG_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:47 337302
wst04-VHDL20_DWLG_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:43 337398
wst04-VHDL20_DWLG_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 341766
wst04-VHDL20_DWLH_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:27 331070
wst04-VHDL20_DWLH_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:42 330431
wst04-VHDL20_DWLH_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:44 331705
wst04-VHDL20_DWLH_021800-2605021800-omedes--0.pdf 02-May-2026 18:31:27 335509
wst04-VHDL20_DWLH_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:26 335267
wst04-VHDL20_DWLH_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:41 335528
wst04-VHDL20_DWLH_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:49 335565
wst04-VHDL20_DWLH_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:21 337548
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wst04-VHDL20_DWLI_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:46 329321
wst04-VHDL20_DWLI_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:49 375474
wst04-VHDL20_DWLI_021800-2605021800-omedes--0.pdf 02-May-2026 18:31:21 338561
wst04-VHDL20_DWLI_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:34 338316
wst04-VHDL20_DWLI_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:41 338316
wst04-VHDL20_DWLI_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:49 382969
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wst04-VHDL20_DWMO_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:22 442259
wst04-VHDL20_DWMO_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:16 441505
wst04-VHDL20_DWMO_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:27 440842
wst04-VHDL20_DWMO_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:26 347397
wst04-VHDL20_DWMO_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:24 452297
wst04-VHDL20_DWMO_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:17 452564
wst04-VHDL20_DWMO_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:30 452328
wst04-VHDL20_DWMO_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:27 350726
wst04-VHDL20_DWMP_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:22 540689
wst04-VHDL20_DWMP_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:22 540045
wst04-VHDL20_DWMP_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:27 440815
wst04-VHDL20_DWMP_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:26 458880
wst04-VHDL20_DWMP_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:24 563802
wst04-VHDL20_DWMP_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:21 564055
wst04-VHDL20_DWMP_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:35 459614
wst04-VHDL20_DWMP_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:27 468793
wst04-VHDL20_DWPG_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:32 240196
wst04-VHDL20_DWPG_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:32 341663
wst04-VHDL20_DWPG_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:55 387815
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wst04-VHDL20_DWPG_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:34 241470
wst04-VHDL20_DWPG_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:31 341851
wst04-VHDL20_DWPG_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:54 387452
wst04-VHDL20_DWPG_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 334438
wst04-VHDL20_DWPH_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:27 236376
wst04-VHDL20_DWPH_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:32 236610
wst04-VHDL20_DWPH_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:44 237084
wst04-VHDL20_DWPH_021800-2605021800-omedes--0.pdf 02-May-2026 18:31:21 239418
wst04-VHDL20_DWPH_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:26 239719
wst04-VHDL20_DWPH_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:31 239564
wst04-VHDL20_DWPH_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:43 239746
wst04-VHDL20_DWPH_031800-2605031800-omedes--0.pdf 03-May-2026 18:31:27 241401
wst04-VHDL20_DWSG_020200-2605020200-omedes--0.pdf 02-May-2026 02:30:12 334996
wst04-VHDL20_DWSG_020400-2605020400-omedes--0.pdf 02-May-2026 05:00:12 333827
wst04-VHDL20_DWSG_020800-2605020800-omedes--0.pdf 02-May-2026 08:30:21 334281
wst04-VHDL20_DWSG_021800-2605021800-omedes--0.pdf 02-May-2026 18:30:16 346909
wst04-VHDL20_DWSG_030200-2605030200-omedes--0.pdf 03-May-2026 02:30:12 346612
wst04-VHDL20_DWSG_030400-2605030400-omedes--0.pdf 03-May-2026 05:00:11 346161
wst04-VHDL20_DWSG_030800-2605030800-omedes--0.pdf 03-May-2026 08:30:30 346669
wst04-VHDL20_DWSG_031800-2605031800-omedes--0.pdf 03-May-2026 18:30:22 356514