Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-May-2026 09:52:20 7234
FPDL13_DWMZ_250600 25-May-2026 12:33:17 16142
SXDL31_DWAV_240800 24-May-2026 07:42:19 6726
SXDL31_DWAV_241800 24-May-2026 16:41:15 6055
SXDL31_DWAV_250800 25-May-2026 07:54:09 7333
SXDL31_DWAV_251800 25-May-2026 16:15:45 6151
SXDL31_DWAV_LATEST 25-May-2026 16:15:45 6151
SXDL33_DWAV_240000 24-May-2026 09:34:46 10733
SXDL33_DWAV_250000 25-May-2026 09:41:15 6531
SXDL33_DWAV_LATEST 25-May-2026 09:41:15 6531
ber01-FWDL39_DWMS_241230-2605241230-dsw--0-ia5 24-May-2026 12:23:41 961
ber01-FWDL39_DWMS_251230-2605251230-dsw--0-ia5 25-May-2026 11:42:16 999
ber01-VHDL13_DWEG_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2666
ber01-VHDL13_DWEG_250800-2605250800-dsw--0-ia5 25-May-2026 08:28:17 2116
ber01-VHDL13_DWEG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:30:43 2412
ber01-VHDL13_DWEH_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2249
ber01-VHDL13_DWEH_240800_COR-2605240800-dsw--0-ia5 24-May-2026 09:13:22 2084
ber01-VHDL13_DWEH_250800-2605250800-dsw--0-ia5 25-May-2026 08:28:21 1974
ber01-VHDL13_DWEH_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:30:57 2039
ber01-VHDL13_DWEI_240800-2605240800-dsw--0-ia5 24-May-2026 08:28:18 2445
ber01-VHDL13_DWEI_250800-2605250800-dsw--0-ia5 25-May-2026 08:28:17 1927
ber01-VHDL13_DWEI_250800_COR-2605250800-dsw--0-ia5 25-May-2026 18:31:19 2188
ber01-VHDL13_DWHG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 2002
ber01-VHDL13_DWHG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 2452
ber01-VHDL13_DWHH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 2021
ber01-VHDL13_DWHH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 2625
ber01-VHDL13_DWLG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1936
ber01-VHDL13_DWLG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 1946
ber01-VHDL13_DWLH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1819
ber01-VHDL13_DWLH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 1908
ber01-VHDL13_DWLI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1889
ber01-VHDL13_DWLI_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 1883
ber01-VHDL13_DWMO_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2354
ber01-VHDL13_DWMO_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 2044
ber01-VHDL13_DWMP_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2296
ber01-VHDL13_DWMP_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 2211
ber01-VHDL13_DWOG_240300-2605240300-dsw--0-ia5 24-May-2026 03:00:06 2628
ber01-VHDL13_DWOG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 3124
ber01-VHDL13_DWOG_241700-2605241700-dsw--0-ia5 24-May-2026 18:00:01 3065
ber01-VHDL13_DWOG_250300-2605250300-dsw--0-ia5 25-May-2026 03:00:19 2967
ber01-VHDL13_DWOG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 2978
ber01-VHDL13_DWOG_251700-2605251700-dsw--0-ia5 25-May-2026 18:00:01 3023
ber01-VHDL13_DWOG_251700_COR-2605251700-dsw--0-ia5 25-May-2026 19:59:31 2905
ber01-VHDL13_DWON_240217-2605240217-dsw--0-ia5 24-May-2026 02:17:17 2653
ber01-VHDL13_DWON_240237-2605240237-dsw--0-ia5 24-May-2026 02:37:22 2653
ber01-VHDL13_DWON_240254-2605240254-dsw--0-ia5 24-May-2026 02:54:30 2653
ber01-VHDL13_DWON_240329-2605240329-dsw--0-ia5 24-May-2026 03:29:31 2587
ber01-VHDL13_DWON_240530-2605240530-dsw--0-ia5 24-May-2026 05:30:21 3060
ber01-VHDL13_DWON_240541-2605240541-dsw--0-ia5 24-May-2026 05:41:07 3408
ber01-VHDL13_DWON_241037-2605241037-dsw--0-ia5 24-May-2026 10:37:56 3408
ber01-VHDL13_DWON_241206-2605241206-dsw--0-ia5 24-May-2026 12:06:23 3408
ber01-VHDL13_DWON_241428-2605241428-dsw--0-ia5 24-May-2026 14:28:27 3708
ber01-VHDL13_DWON_241653-2605241653-dsw--0-ia5 24-May-2026 16:53:23 2988
ber01-VHDL13_DWON_241844-2605241844-dsw--0-ia5 24-May-2026 18:45:02 2883
ber01-VHDL13_DWON_250016-2605250016-dsw--0-ia5 25-May-2026 00:16:22 3095
ber01-VHDL13_DWON_250242-2605250242-dsw--0-ia5 25-May-2026 02:42:18 3095
ber01-VHDL13_DWON_250527-2605250527-dsw--0-ia5 25-May-2026 05:27:57 3678
ber01-VHDL13_DWON_250624-2605250624-dsw--0-ia5 25-May-2026 06:24:12 3678
ber01-VHDL13_DWON_250801-2605250801-dsw--0-ia5 25-May-2026 08:01:31 3678
ber01-VHDL13_DWON_251444-2605251444-dsw--0-ia5 25-May-2026 14:44:14 3096
ber01-VHDL13_DWON_251633-2605251633-dsw--0-ia5 25-May-2026 16:33:21 3510
ber01-VHDL13_DWON_251958-2605251958-dsw--0-ia5 25-May-2026 19:58:57 3482
ber01-VHDL13_DWPG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1938
ber01-VHDL13_DWPG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 1917
ber01-VHDL13_DWPH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1894
ber01-VHDL13_DWPH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 2316
ber01-VHDL13_DWSG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 2375
ber01-VHDL13_DWSG_240800_COR-2605240800-dsw--0-ia5 24-May-2026 16:33:55 2347
ber01-VHDL13_DWSG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 2335
ber01-VHDL13_DWSG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 12:36:03 2285
ber01-VHDL17_DWOG_241200-2605241200-dsw--0-ia5 24-May-2026 11:53:52 3150
ber01-VHDL17_DWOG_251200-2605251200-dsw--0-ia5 25-May-2026 11:54:02 2623
swis2-VHDL20_DWEG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 848
swis2-VHDL20_DWEG_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 849
swis2-VHDL20_DWEG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 1128
swis2-VHDL20_DWEG_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 895
swis2-VHDL20_DWEG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 750
swis2-VHDL20_DWEG_250400-2605250400-dsw--0-ia5 25-May-2026 05:01:27 645
swis2-VHDL20_DWEG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 743
swis2-VHDL20_DWEG_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 906
swis2-VHDL20_DWEH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 665
swis2-VHDL20_DWEH_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 665
swis2-VHDL20_DWEH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 935
swis2-VHDL20_DWEH_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 921
swis2-VHDL20_DWEH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 764
swis2-VHDL20_DWEH_250400-2605250400-dsw--0-ia5 25-May-2026 05:01:27 659
swis2-VHDL20_DWEH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 753
swis2-VHDL20_DWEH_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 810
swis2-VHDL20_DWEI_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 890
swis2-VHDL20_DWEI_240400-2605240400-dsw--0-ia5 24-May-2026 05:01:31 891
swis2-VHDL20_DWEI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:09 1165
swis2-VHDL20_DWEI_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 788
swis2-VHDL20_DWEI_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 667
swis2-VHDL20_DWEI_250400-2605250400-dsw--0-ia5 25-May-2026 05:01:27 667
swis2-VHDL20_DWEI_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 765
swis2-VHDL20_DWEI_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 932
swis2-VHDL20_DWHG_240200-2605240200-dsw--0-ia5 24-May-2026 02:45:13 1020
swis2-VHDL20_DWHG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 987
swis2-VHDL20_DWHG_240800-2605240800-dsw--0-ia5 24-May-2026 08:45:09 1057
swis2-VHDL20_DWHG_241800-2605241800-dsw--0-ia5 24-May-2026 18:45:06 1053
swis2-VHDL20_DWHG_241800_COR-2605241800-dsw--0-ia5 24-May-2026 18:59:42 1104
swis2-VHDL20_DWHG_250200-2605250200-dsw--0-ia5 25-May-2026 02:45:28 965
swis2-VHDL20_DWHG_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:16 966
swis2-VHDL20_DWHG_250800-2605250800-dsw--0-ia5 25-May-2026 08:45:15 1101
swis2-VHDL20_DWHG_251800-2605251800-dsw--0-ia5 25-May-2026 18:45:06 1076
swis2-VHDL20_DWHH_240200-2605240200-dsw--0-ia5 24-May-2026 02:45:13 1031
swis2-VHDL20_DWHH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 1005
swis2-VHDL20_DWHH_240800-2605240800-dsw--0-ia5 24-May-2026 08:45:09 1176
swis2-VHDL20_DWHH_241800-2605241800-dsw--0-ia5 24-May-2026 18:45:06 1169
swis2-VHDL20_DWHH_241800_COR-2605241800-dsw--0-ia5 24-May-2026 18:59:27 1121
swis2-VHDL20_DWHH_250200-2605250200-dsw--0-ia5 25-May-2026 02:45:28 960
swis2-VHDL20_DWHH_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:16 964
swis2-VHDL20_DWHH_250800-2605250800-dsw--0-ia5 25-May-2026 08:45:15 1111
swis2-VHDL20_DWHH_251800-2605251800-dsw--0-ia5 25-May-2026 18:45:06 1083
swis2-VHDL20_DWLG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 851
swis2-VHDL20_DWLG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 789
swis2-VHDL20_DWLG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 883
swis2-VHDL20_DWLG_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 799
swis2-VHDL20_DWLG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 711
swis2-VHDL20_DWLG_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:12 713
swis2-VHDL20_DWLG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:21 875
swis2-VHDL20_DWLG_251800-2605251800-dsw--0-ia5 25-May-2026 18:31:03 812
swis2-VHDL20_DWLH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 760
swis2-VHDL20_DWLH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 737
swis2-VHDL20_DWLH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 825
swis2-VHDL20_DWLH_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 806
swis2-VHDL20_DWLH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 718
swis2-VHDL20_DWLH_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:12 720
swis2-VHDL20_DWLH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:21 814
swis2-VHDL20_DWLH_251800-2605251800-dsw--0-ia5 25-May-2026 18:31:03 819
swis2-VHDL20_DWLI_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 793
swis2-VHDL20_DWLI_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 810
swis2-VHDL20_DWLI_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 904
swis2-VHDL20_DWLI_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 800
swis2-VHDL20_DWLI_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 712
swis2-VHDL20_DWLI_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:12 714
swis2-VHDL20_DWLI_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:21 808
swis2-VHDL20_DWLI_251800-2605251800-dsw--0-ia5 25-May-2026 18:31:03 814
swis2-VHDL20_DWMO_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 986
swis2-VHDL20_DWMO_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:02 995
swis2-VHDL20_DWMO_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1094
swis2-VHDL20_DWMO_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:05 1048
swis2-VHDL20_DWMO_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 731
swis2-VHDL20_DWMO_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:02 739
swis2-VHDL20_DWMO_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:08 888
swis2-VHDL20_DWMO_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 1409
swis2-VHDL20_DWMP_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 964
swis2-VHDL20_DWMP_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:02 971
swis2-VHDL20_DWMP_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1073
swis2-VHDL20_DWMP_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:05 1361
swis2-VHDL20_DWMP_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 762
swis2-VHDL20_DWMP_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:02 770
swis2-VHDL20_DWMP_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 1031
swis2-VHDL20_DWMP_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 1543
swis2-VHDL20_DWPG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 911
swis2-VHDL20_DWPG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 832
swis2-VHDL20_DWPG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 926
swis2-VHDL20_DWPG_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 817
swis2-VHDL20_DWPG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 729
swis2-VHDL20_DWPG_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:12 731
swis2-VHDL20_DWPG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:21 850
swis2-VHDL20_DWPG_251800-2605251800-dsw--0-ia5 25-May-2026 18:31:03 830
swis2-VHDL20_DWPH_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:23 766
swis2-VHDL20_DWPH_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:16 743
swis2-VHDL20_DWPH_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:22 847
swis2-VHDL20_DWPH_241800-2605241800-dsw--0-ia5 24-May-2026 18:31:07 865
swis2-VHDL20_DWPH_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:21 1071
swis2-VHDL20_DWPH_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:12 909
swis2-VHDL20_DWPH_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:21 1014
swis2-VHDL20_DWPH_251800-2605251800-dsw--0-ia5 25-May-2026 18:31:03 858
swis2-VHDL20_DWSG_240200-2605240200-dsw--0-ia5 24-May-2026 02:30:06 965
swis2-VHDL20_DWSG_240400-2605240400-dsw--0-ia5 24-May-2026 05:00:22 962
swis2-VHDL20_DWSG_240800-2605240800-dsw--0-ia5 24-May-2026 08:30:01 1023
swis2-VHDL20_DWSG_240800_COR-2605240800-dsw--0-ia5 24-May-2026 16:33:55 1090
swis2-VHDL20_DWSG_241800-2605241800-dsw--0-ia5 24-May-2026 18:30:03 1037
swis2-VHDL20_DWSG_250200-2605250200-dsw--0-ia5 25-May-2026 02:30:05 851
swis2-VHDL20_DWSG_250400-2605250400-dsw--0-ia5 25-May-2026 05:00:18 830
swis2-VHDL20_DWSG_250800-2605250800-dsw--0-ia5 25-May-2026 08:30:09 1055
swis2-VHDL20_DWSG_250800_COR-2605250800-dsw--0-ia5 25-May-2026 12:36:03 964
swis2-VHDL20_DWSG_251800-2605251800-dsw--0-ia5 25-May-2026 18:30:01 1226
wst04-VHDL20_DWEG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 236016
wst04-VHDL20_DWEG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 236072
wst04-VHDL20_DWEG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 236833
wst04-VHDL20_DWEG_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:11 231913
wst04-VHDL20_DWEG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 231315
wst04-VHDL20_DWEG_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:12 230706
wst04-VHDL20_DWEG_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:11 231311
wst04-VHDL20_DWEG_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:11 243082
wst04-VHDL20_DWEH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 230217
wst04-VHDL20_DWEH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 230168
wst04-VHDL20_DWEH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 231135
wst04-VHDL20_DWEH_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 230448
wst04-VHDL20_DWEH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 230163
wst04-VHDL20_DWEH_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:12 229763
wst04-VHDL20_DWEH_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:11 230461
wst04-VHDL20_DWEH_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:11 236942
wst04-VHDL20_DWEI_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 338796
wst04-VHDL20_DWEI_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 338808
wst04-VHDL20_DWEI_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:13 339093
wst04-VHDL20_DWEI_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 329208
wst04-VHDL20_DWEI_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 329170
wst04-VHDL20_DWEI_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:18 328647
wst04-VHDL20_DWEI_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:11 328788
wst04-VHDL20_DWEI_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:18 345305
wst04-VHDL20_DWHG_240200-2605240200-omedes--0.pdf 24-May-2026 02:45:13 332213
wst04-VHDL20_DWHG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 332196
wst04-VHDL20_DWHG_240800-2605240800-omedes--0.pdf 24-May-2026 08:45:13 332915
wst04-VHDL20_DWHG_241800-2605241800-omedes--0.pdf 24-May-2026 18:45:10 326695
wst04-VHDL20_DWHG_250200-2605250200-omedes--0.pdf 25-May-2026 02:45:28 326076
wst04-VHDL20_DWHG_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:16 325846
wst04-VHDL20_DWHG_250800-2605250800-omedes--0.pdf 25-May-2026 08:45:15 326558
wst04-VHDL20_DWHG_251800-2605251800-omedes--0.pdf 25-May-2026 18:45:12 341379
wst04-VHDL20_DWHH_240200-2605240200-omedes--0.pdf 24-May-2026 02:45:13 326374
wst04-VHDL20_DWHH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 222890
wst04-VHDL20_DWHH_240800-2605240800-omedes--0.pdf 24-May-2026 08:45:13 327019
wst04-VHDL20_DWHH_241800-2605241800-omedes--0.pdf 24-May-2026 18:45:10 326850
wst04-VHDL20_DWHH_250200-2605250200-omedes--0.pdf 25-May-2026 02:45:28 325791
wst04-VHDL20_DWHH_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:16 225815
wst04-VHDL20_DWHH_250800-2605250800-omedes--0.pdf 25-May-2026 08:45:15 326267
wst04-VHDL20_DWHH_251800-2605251800-omedes--0.pdf 25-May-2026 18:45:12 334876
wst04-VHDL20_DWLG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 326296
wst04-VHDL20_DWLG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 326048
wst04-VHDL20_DWLG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 326274
wst04-VHDL20_DWLG_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:26 322155
wst04-VHDL20_DWLG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 322156
wst04-VHDL20_DWLG_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:42 321972
wst04-VHDL20_DWLG_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:42 322579
wst04-VHDL20_DWLG_251800-2605251800-omedes--0.pdf 25-May-2026 18:31:24 325745
wst04-VHDL20_DWLH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 320932
wst04-VHDL20_DWLH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 320686
wst04-VHDL20_DWLH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 320710
wst04-VHDL20_DWLH_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 322935
wst04-VHDL20_DWLH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:29 322933
wst04-VHDL20_DWLH_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:42 322738
wst04-VHDL20_DWLH_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:42 322759
wst04-VHDL20_DWLH_251800-2605251800-omedes--0.pdf 25-May-2026 18:31:24 326204
wst04-VHDL20_DWLI_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 329113
wst04-VHDL20_DWLI_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:42 329442
wst04-VHDL20_DWLI_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:47 374225
wst04-VHDL20_DWLI_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 328968
wst04-VHDL20_DWLI_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 328968
wst04-VHDL20_DWLI_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:42 328769
wst04-VHDL20_DWLI_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:48 373361
wst04-VHDL20_DWLI_251800-2605251800-omedes--0.pdf 25-May-2026 18:31:24 335366
wst04-VHDL20_DWMO_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:16 444960
wst04-VHDL20_DWMO_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 444870
wst04-VHDL20_DWMO_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:17 444157
wst04-VHDL20_DWMO_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 336468
wst04-VHDL20_DWMO_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:16 442061
wst04-VHDL20_DWMO_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:12 442009
wst04-VHDL20_DWMO_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:17 441266
wst04-VHDL20_DWMO_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:18 349432
wst04-VHDL20_DWMP_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:16 560402
wst04-VHDL20_DWMP_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:16 560380
wst04-VHDL20_DWMP_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:22 454372
wst04-VHDL20_DWMP_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:17 449543
wst04-VHDL20_DWMP_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:16 547197
wst04-VHDL20_DWMP_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:16 547138
wst04-VHDL20_DWMP_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:21 448219
wst04-VHDL20_DWMP_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:18 471660
wst04-VHDL20_DWPG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:27 233680
wst04-VHDL20_DWPG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:32 327847
wst04-VHDL20_DWPG_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 372582
wst04-VHDL20_DWPG_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 322378
wst04-VHDL20_DWPG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 229891
wst04-VHDL20_DWPG_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:32 322240
wst04-VHDL20_DWPG_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:42 367312
wst04-VHDL20_DWPG_251800-2605251800-omedes--0.pdf 25-May-2026 18:31:26 333976
wst04-VHDL20_DWPH_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:23 233698
wst04-VHDL20_DWPH_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:32 233487
wst04-VHDL20_DWPH_240800-2605240800-omedes--0.pdf 24-May-2026 08:30:41 234006
wst04-VHDL20_DWPH_241800-2605241800-omedes--0.pdf 24-May-2026 18:31:21 235541
wst04-VHDL20_DWPH_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:21 236362
wst04-VHDL20_DWPH_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:32 235594
wst04-VHDL20_DWPH_250800-2605250800-omedes--0.pdf 25-May-2026 08:30:42 235742
wst04-VHDL20_DWPH_251800-2605251800-omedes--0.pdf 25-May-2026 18:31:24 240384
wst04-VHDL20_DWSG_240200-2605240200-omedes--0.pdf 24-May-2026 02:30:11 345935
wst04-VHDL20_DWSG_240400-2605240400-omedes--0.pdf 24-May-2026 05:00:12 345954
wst04-VHDL20_DWSG_240800-2605240800-omedes--0.pdf 24-May-2026 16:33:55 335950
wst04-VHDL20_DWSG_241800-2605241800-omedes--0.pdf 24-May-2026 18:30:11 335474
wst04-VHDL20_DWSG_250200-2605250200-omedes--0.pdf 25-May-2026 02:30:12 335548
wst04-VHDL20_DWSG_250400-2605250400-omedes--0.pdf 25-May-2026 05:00:12 334525
wst04-VHDL20_DWSG_250800-2605250800-omedes--0.pdf 25-May-2026 12:36:03 343699
wst04-VHDL20_DWSG_251800-2605251800-omedes--0.pdf 25-May-2026 18:30:18 345234