Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Oct-2025 12:34:38 3133
FPDL13_DWMZ_070600 07-Oct-2025 13:35:55 4709
SXDL31_DWAV_060800 06-Oct-2025 07:30:59 8938
SXDL31_DWAV_061800 06-Oct-2025 16:04:39 10925
SXDL31_DWAV_070800 07-Oct-2025 07:42:24 5497
SXDL31_DWAV_071800 07-Oct-2025 16:14:34 6636
SXDL31_DWAV_LATEST 07-Oct-2025 16:14:34 6636
SXDL33_DWAV_060000 06-Oct-2025 09:23:40 5932
SXDL33_DWAV_070000 07-Oct-2025 09:30:37 6653
SXDL33_DWAV_LATEST 07-Oct-2025 09:30:37 6653
ber01-FWDL39_DWMS_061230-2510061230-dsw--0-ia5 06-Oct-2025 12:32:56 1955
ber01-FWDL39_DWMS_071230-2510071230-dsw--0-ia5 07-Oct-2025 11:41:01 1438
ber01-VHDL13_DWEH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:28:17 2850
ber01-VHDL13_DWEH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:28:15 2248
ber01-VHDL13_DWEH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:28:17 2279
ber01-VHDL13_DWEH_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:58:16 2127
ber01-VHDL13_DWEH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:28:16 2142
ber01-VHDL13_DWEH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:28:18 1858
ber01-VHDL13_DWEH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:28:17 2009
ber01-VHDL13_DWEH_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:58:16 1967
ber01-VHDL13_DWHG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:08 2879
ber01-VHDL13_DWHG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:08 2282
ber01-VHDL13_DWHG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2682
ber01-VHDL13_DWHG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:12 2649
ber01-VHDL13_DWHG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:11 2677
ber01-VHDL13_DWHG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:08 2302
ber01-VHDL13_DWHG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:07 2302
ber01-VHDL13_DWHG_080200_COR-2510080200-dsw--0-ia5 08-Oct-2025 03:01:57 2448
ber01-VHDL13_DWHG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:12 2423
ber01-VHDL13_DWHH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:08 2926
ber01-VHDL13_DWHH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:08 2327
ber01-VHDL13_DWHH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2742
ber01-VHDL13_DWHH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:12 2719
ber01-VHDL13_DWHH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:11 2742
ber01-VHDL13_DWHH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:08 2313
ber01-VHDL13_DWHH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:07 2313
ber01-VHDL13_DWHH_080200_COR-2510080200-dsw--0-ia5 08-Oct-2025 03:02:22 2521
ber01-VHDL13_DWHH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:12 2493
ber01-VHDL13_DWLG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2627
ber01-VHDL13_DWLG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 2170
ber01-VHDL13_DWLG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2258
ber01-VHDL13_DWLG_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:59:58 2308
ber01-VHDL13_DWLG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 2370
ber01-VHDL13_DWLG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:01 2166
ber01-VHDL13_DWLG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:07 2183
ber01-VHDL13_DWLG_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:59:58 2185
ber01-VHDL13_DWLH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2301
ber01-VHDL13_DWLH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 1853
ber01-VHDL13_DWLH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2037
ber01-VHDL13_DWLH_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:59:58 1989
ber01-VHDL13_DWLH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 2048
ber01-VHDL13_DWLH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:01 1997
ber01-VHDL13_DWLH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:07 2015
ber01-VHDL13_DWLH_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:59:58 2093
ber01-VHDL13_DWLI_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 1961
ber01-VHDL13_DWLI_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 1895
ber01-VHDL13_DWLI_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2083
ber01-VHDL13_DWLI_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:59:58 1930
ber01-VHDL13_DWLI_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 2022
ber01-VHDL13_DWLI_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:01 1907
ber01-VHDL13_DWLI_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:07 1955
ber01-VHDL13_DWLI_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:59:58 1987
ber01-VHDL13_DWMG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2889
ber01-VHDL13_DWMG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 2652
ber01-VHDL13_DWMG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2672
ber01-VHDL13_DWMG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2672
ber01-VHDL13_DWMG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 3048
ber01-VHDL13_DWMG_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:17 2488
ber01-VHDL13_DWMG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:08 2135
ber01-VHDL13_DWMG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 2598
ber01-VHDL13_DWMG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2540
ber01-VHDL13_DWMO_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2355
ber01-VHDL13_DWMO_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 1992
ber01-VHDL13_DWMO_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2185
ber01-VHDL13_DWMO_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2185
ber01-VHDL13_DWMO_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 2577
ber01-VHDL13_DWMO_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:37 2411
ber01-VHDL13_DWMO_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:08 2175
ber01-VHDL13_DWMO_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 2445
ber01-VHDL13_DWMO_080200_COR-2510080200-dsw--0-ia5 08-Oct-2025 02:42:28 2683
ber01-VHDL13_DWMO_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2611
ber01-VHDL13_DWMP_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 3084
ber01-VHDL13_DWMP_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 2737
ber01-VHDL13_DWMP_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:06 2859
ber01-VHDL13_DWMP_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2859
ber01-VHDL13_DWMP_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 3078
ber01-VHDL13_DWMP_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:27 2422
ber01-VHDL13_DWMP_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:08 2092
ber01-VHDL13_DWMP_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 2437
ber01-VHDL13_DWMP_080200_COR-2510080200-dsw--0-ia5 08-Oct-2025 02:42:47 2696
ber01-VHDL13_DWMP_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2634
ber01-VHDL13_DWOG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 4558
ber01-VHDL13_DWOG_060800_COR-2510060800-dsw--0-ia5 06-Oct-2025 14:59:56 3606
ber01-VHDL13_DWOG_061700-2510061700-dsw--0-ia5 06-Oct-2025 18:00:02 3638
ber01-VHDL13_DWOG_061700_COR-2510061700-dsw--0-ia5 06-Oct-2025 22:00:12 3474
ber01-VHDL13_DWOG_070300-2510070300-dsw--0-ia5 07-Oct-2025 03:00:08 3465
ber01-VHDL13_DWOG_070800-2510070800-dsw--0-ia5 07-Oct-2025 09:14:16 3690
ber01-VHDL13_DWOG_071700-2510071700-dsw--0-ia5 07-Oct-2025 18:00:01 3243
ber01-VHDL13_DWOG_080300-2510080300-dsw--0-ia5 08-Oct-2025 03:00:02 3420
ber01-VHDL13_DWOH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:28:13 2495
ber01-VHDL13_DWOH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:28:15 2157
ber01-VHDL13_DWOH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:28:11 2163
ber01-VHDL13_DWOH_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:58:12 2135
ber01-VHDL13_DWOH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:28:16 2164
ber01-VHDL13_DWOH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:28:18 1842
ber01-VHDL13_DWOH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:28:12 2011
ber01-VHDL13_DWOH_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:58:12 2082
ber01-VHDL13_DWOI_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:28:13 2534
ber01-VHDL13_DWOI_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:28:15 2084
ber01-VHDL13_DWOI_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:28:17 2034
ber01-VHDL13_DWOI_070400-2510070400-dsw--0-ia5 07-Oct-2025 04:58:16 2139
ber01-VHDL13_DWOI_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:28:12 2171
ber01-VHDL13_DWOI_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:28:12 1928
ber01-VHDL13_DWOI_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:28:17 2101
ber01-VHDL13_DWOI_080400-2510080400-dsw--0-ia5 08-Oct-2025 04:58:16 2261
ber01-VHDL13_DWON_060744-2510060744-dsw--0-ia5 06-Oct-2025 07:44:56 3789
ber01-VHDL13_DWON_060815-2510060815-dsw--0-ia5 06-Oct-2025 08:15:17 3789
ber01-VHDL13_DWON_061432-2510061432-dsw--0-ia5 06-Oct-2025 14:32:50 3186
ber01-VHDL13_DWON_061630-2510061630-dsw--0-ia5 06-Oct-2025 16:30:16 3123
ber01-VHDL13_DWON_062159-2510062159-dsw--0-ia5 06-Oct-2025 21:59:52 3067
ber01-VHDL13_DWON_062200_COR-2510062200-dsw--0-ia5 06-Oct-2025 22:00:22 3071
ber01-VHDL13_DWON_070201-2510070201-dsw--0-ia5 07-Oct-2025 02:01:11 3109
ber01-VHDL13_DWON_070530-2510070530-dsw--0-ia5 07-Oct-2025 05:30:52 3667
ber01-VHDL13_DWON_070613-2510070613-dsw--0-ia5 07-Oct-2025 06:13:22 3817
ber01-VHDL13_DWON_070643-2510070643-dsw--0-ia5 07-Oct-2025 06:43:06 3817
ber01-VHDL13_DWON_070913-2510070913-dsw--0-ia5 07-Oct-2025 09:13:46 3673
ber01-VHDL13_DWON_071436-2510071436-dsw--0-ia5 07-Oct-2025 14:36:36 3353
ber01-VHDL13_DWON_071615-2510071615-dsw--0-ia5 07-Oct-2025 16:15:11 3353
ber01-VHDL13_DWON_071747-2510071747-dsw--0-ia5 07-Oct-2025 17:47:06 3353
ber01-VHDL13_DWON_071855-2510071855-dsw--0-ia5 07-Oct-2025 18:56:01 3353
ber01-VHDL13_DWON_080036-2510080036-dsw--0-ia5 08-Oct-2025 00:36:51 3531
ber01-VHDL13_DWON_080517-2510080517-dsw--0-ia5 08-Oct-2025 05:17:37 3514
ber01-VHDL13_DWPG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2061
ber01-VHDL13_DWPG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 1868
ber01-VHDL13_DWPG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:02 1893
ber01-VHDL13_DWPG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 1834
ber01-VHDL13_DWPG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 1903
ber01-VHDL13_DWPG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:03 1816
ber01-VHDL13_DWPG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 1835
ber01-VHDL13_DWPG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2073
ber01-VHDL13_DWPH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2498
ber01-VHDL13_DWPH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 2097
ber01-VHDL13_DWPH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:02 2276
ber01-VHDL13_DWPH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2230
ber01-VHDL13_DWPH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:01 2317
ber01-VHDL13_DWPH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:03 2074
ber01-VHDL13_DWPH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 2263
ber01-VHDL13_DWPH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2456
ber01-VHDL13_DWSG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:30:01 2215
ber01-VHDL13_DWSG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:30:01 2022
ber01-VHDL13_DWSG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:30:02 2181
ber01-VHDL13_DWSG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:06 2181
ber01-VHDL13_DWSG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:30:11 2249
ber01-VHDL13_DWSG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:30:01 1846
ber01-VHDL13_DWSG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:30:02 2262
ber01-VHDL13_DWSG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:06 2249
ber01-VHDL17_DWOG_061200-2510061200-dsw--0-ia5 06-Oct-2025 10:42:17 2339
ber01-VHDL17_DWOG_071200-2510071200-dsw--0-ia5 07-Oct-2025 11:22:16 2027
swis2-VHDL20_DWEG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:07 2674
swis2-VHDL20_DWEG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:06 2342
swis2-VHDL20_DWEG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2295
swis2-VHDL20_DWEG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:15:07 2343
swis2-VHDL20_DWEG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2343
swis2-VHDL20_DWEG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:06 2027
swis2-VHDL20_DWEG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2143
swis2-VHDL20_DWEG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:15:06 2290
swis2-VHDL20_DWEH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:11 3028
swis2-VHDL20_DWEH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:16 2449
swis2-VHDL20_DWEH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:26 2443
swis2-VHDL20_DWEH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:15:17 2305
swis2-VHDL20_DWEH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:13 2320
swis2-VHDL20_DWEH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:13 2059
swis2-VHDL20_DWEH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:19 2173
swis2-VHDL20_DWEH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:15:16 2145
swis2-VHDL20_DWEI_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:07 2713
swis2-VHDL20_DWEI_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:06 2269
swis2-VHDL20_DWEI_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2167
swis2-VHDL20_DWEI_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:15:17 2324
swis2-VHDL20_DWEI_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2350
swis2-VHDL20_DWEI_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:06 2113
swis2-VHDL20_DWEI_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2234
swis2-VHDL20_DWEI_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:15:22 2446
swis2-VHDL20_DWHG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:07 3062
swis2-VHDL20_DWHG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:06 2465
swis2-VHDL20_DWHG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2868
swis2-VHDL20_DWHG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:12 2832
swis2-VHDL20_DWHG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:07 2860
swis2-VHDL20_DWHG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2485
swis2-VHDL20_DWHG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2630
swis2-VHDL20_DWHG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:12 2606
swis2-VHDL20_DWHH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:07 3112
swis2-VHDL20_DWHH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:06 2513
swis2-VHDL20_DWHH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2928
swis2-VHDL20_DWHH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:12 2905
swis2-VHDL20_DWHH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:07 2928
swis2-VHDL20_DWHH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2499
swis2-VHDL20_DWHH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2703
swis2-VHDL20_DWHH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:12 2679
swis2-VHDL20_DWLG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2851
swis2-VHDL20_DWLG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2391
swis2-VHDL20_DWLG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2479
swis2-VHDL20_DWLG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:22 2529
swis2-VHDL20_DWLG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2594
swis2-VHDL20_DWLG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2387
swis2-VHDL20_DWLG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:05 2404
swis2-VHDL20_DWLG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:26 2406
swis2-VHDL20_DWLH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2522
swis2-VHDL20_DWLH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2074
swis2-VHDL20_DWLH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2258
swis2-VHDL20_DWLH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:22 2210
swis2-VHDL20_DWLH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2269
swis2-VHDL20_DWLH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2218
swis2-VHDL20_DWLH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2236
swis2-VHDL20_DWLH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:26 2314
swis2-VHDL20_DWLI_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2182
swis2-VHDL20_DWLI_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2116
swis2-VHDL20_DWLI_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2304
swis2-VHDL20_DWLI_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:22 2148
swis2-VHDL20_DWLI_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2243
swis2-VHDL20_DWLI_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2128
swis2-VHDL20_DWLI_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2176
swis2-VHDL20_DWLI_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:26 2205
swis2-VHDL20_DWMG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 3100
swis2-VHDL20_DWMG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2863
swis2-VHDL20_DWMG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2883
swis2-VHDL20_DWMG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2883
swis2-VHDL20_DWMG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:07 3259
swis2-VHDL20_DWMG_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:17 3022
swis2-VHDL20_DWMG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:06 2346
swis2-VHDL20_DWMG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:09 2832
swis2-VHDL20_DWMG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2751
swis2-VHDL20_DWMO_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2567
swis2-VHDL20_DWMO_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2204
swis2-VHDL20_DWMO_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2400
swis2-VHDL20_DWMO_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2400
swis2-VHDL20_DWMO_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:07 2789
swis2-VHDL20_DWMO_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:37 2953
swis2-VHDL20_DWMO_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:06 2387
swis2-VHDL20_DWMO_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:09 2894
swis2-VHDL20_DWMO_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2826
swis2-VHDL20_DWMP_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 3296
swis2-VHDL20_DWMP_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2938
swis2-VHDL20_DWMP_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 3071
swis2-VHDL20_DWMP_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 3071
swis2-VHDL20_DWMP_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:07 3290
swis2-VHDL20_DWMP_070800_COR-2510070800-dsw--0-ia5 07-Oct-2025 12:42:27 2961
swis2-VHDL20_DWMP_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:06 2278
swis2-VHDL20_DWMP_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:09 2904
swis2-VHDL20_DWMP_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2846
swis2-VHDL20_DWPG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2258
swis2-VHDL20_DWPG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2065
swis2-VHDL20_DWPG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2090
swis2-VHDL20_DWPG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2029
swis2-VHDL20_DWPG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2100
swis2-VHDL20_DWPG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2013
swis2-VHDL20_DWPG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2032
swis2-VHDL20_DWPG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2268
swis2-VHDL20_DWPH_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2695
swis2-VHDL20_DWPH_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:04 2294
swis2-VHDL20_DWPH_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2473
swis2-VHDL20_DWPH_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:00:02 2427
swis2-VHDL20_DWPH_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2514
swis2-VHDL20_DWPH_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2271
swis2-VHDL20_DWPH_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:05 2460
swis2-VHDL20_DWPH_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:00:02 2653
swis2-VHDL20_DWSG_060800-2510060800-dsw--0-ia5 06-Oct-2025 08:45:02 2445
swis2-VHDL20_DWSG_061300-2510061300-dsw--0-ia5 06-Oct-2025 13:45:03 2436
swis2-VHDL20_DWSG_061800-2510061800-dsw--0-ia5 06-Oct-2025 18:45:06 2254
swis2-VHDL20_DWSG_070200-2510070200-dsw--0-ia5 07-Oct-2025 02:45:06 2415
swis2-VHDL20_DWSG_070400-2510070400-dsw--0-ia5 07-Oct-2025 05:15:01 2415
swis2-VHDL20_DWSG_070800-2510070800-dsw--0-ia5 07-Oct-2025 08:45:04 2479
swis2-VHDL20_DWSG_071300-2510071300-dsw--0-ia5 07-Oct-2025 13:45:04 2479
swis2-VHDL20_DWSG_071800-2510071800-dsw--0-ia5 07-Oct-2025 18:45:01 2078
swis2-VHDL20_DWSG_080200-2510080200-dsw--0-ia5 08-Oct-2025 02:45:06 2496
swis2-VHDL20_DWSG_080400-2510080400-dsw--0-ia5 08-Oct-2025 05:15:02 2480
wst04-VHDL20_DWEG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:22 261310
wst04-VHDL20_DWEG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:22 260132
wst04-VHDL20_DWEG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 259738
wst04-VHDL20_DWEG_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:15:11 260948
wst04-VHDL20_DWEG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:18 260951
wst04-VHDL20_DWEG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:21 259736
wst04-VHDL20_DWEG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 259287
wst04-VHDL20_DWEG_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:15:16 260191
wst04-VHDL20_DWEH_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:17 260792
wst04-VHDL20_DWEH_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:22 256005
wst04-VHDL20_DWEH_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 255561
wst04-VHDL20_DWEH_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:15:17 255672
wst04-VHDL20_DWEH_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:13 255645
wst04-VHDL20_DWEH_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:21 255951
wst04-VHDL20_DWEH_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:21 256522
wst04-VHDL20_DWEH_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:15:16 256312
wst04-VHDL20_DWEI_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:30 364375
wst04-VHDL20_DWEI_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:22 357021
wst04-VHDL20_DWEI_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 357106
wst04-VHDL20_DWEI_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:15:17 357435
wst04-VHDL20_DWEI_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:22 356647
wst04-VHDL20_DWEI_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:21 358453
wst04-VHDL20_DWEI_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:21 359566
wst04-VHDL20_DWEI_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:15:16 360272
wst04-VHDL20_DWHG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:30 349857
wst04-VHDL20_DWHG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:26 351324
wst04-VHDL20_DWHG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 351189
wst04-VHDL20_DWHG_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:12 351161
wst04-VHDL20_DWHG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:18 351305
wst04-VHDL20_DWHG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:21 346332
wst04-VHDL20_DWHG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 346448
wst04-VHDL20_DWHG_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:16 346494
wst04-VHDL20_DWHH_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:22 347750
wst04-VHDL20_DWHH_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:22 339755
wst04-VHDL20_DWHH_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 339873
wst04-VHDL20_DWHH_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:12 339809
wst04-VHDL20_DWHH_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:18 339871
wst04-VHDL20_DWHH_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:27 338832
wst04-VHDL20_DWHH_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 338661
wst04-VHDL20_DWHH_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:12 338641
wst04-VHDL20_DWLG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:40:38 345678
wst04-VHDL20_DWLG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:40:32 345299
wst04-VHDL20_DWLG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:40:32 345064
wst04-VHDL20_DWLG_070400-2510070400-omedes--0.pdf 07-Oct-2025 04:59:41 344872
wst04-VHDL20_DWLG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:40:32 345411
wst04-VHDL20_DWLG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:40:31 339942
wst04-VHDL20_DWLG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:40:39 338468
wst04-VHDL20_DWLG_080400-2510080400-omedes--0.pdf 08-Oct-2025 04:59:42 338988
wst04-VHDL20_DWLH_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:40:24 346661
wst04-VHDL20_DWLH_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:40:22 344605
wst04-VHDL20_DWLH_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:40:27 344861
wst04-VHDL20_DWLH_070400-2510070400-omedes--0.pdf 07-Oct-2025 04:59:41 344867
wst04-VHDL20_DWLH_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:40:20 344631
wst04-VHDL20_DWLH_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:40:22 335632
wst04-VHDL20_DWLH_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:40:24 334440
wst04-VHDL20_DWLH_080400-2510080400-omedes--0.pdf 08-Oct-2025 04:59:42 334751
wst04-VHDL20_DWLI_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:40:41 349450
wst04-VHDL20_DWLI_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:40:41 343754
wst04-VHDL20_DWLI_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:40:42 343514
wst04-VHDL20_DWLI_070400-2510070400-omedes--0.pdf 07-Oct-2025 04:59:41 343624
wst04-VHDL20_DWLI_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:40:41 343385
wst04-VHDL20_DWLI_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:40:41 338130
wst04-VHDL20_DWLI_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:40:41 337503
wst04-VHDL20_DWLI_080400-2510080400-omedes--0.pdf 08-Oct-2025 04:59:42 337680
wst04-VHDL20_DWMG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:22 559597
wst04-VHDL20_DWMG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:16 554457
wst04-VHDL20_DWMG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 554963
wst04-VHDL20_DWMG_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:16 554385
wst04-VHDL20_DWMG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:26 554945
wst04-VHDL20_DWMG_070800_COR-2510070800-omedes-..> 07-Oct-2025 12:42:21 541772
wst04-VHDL20_DWMG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:17 539690
wst04-VHDL20_DWMG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:21 540589
wst04-VHDL20_DWMG_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:16 539958
wst04-VHDL20_DWMO_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:17 453238
wst04-VHDL20_DWMO_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:12 450597
wst04-VHDL20_DWMO_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 450876
wst04-VHDL20_DWMO_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:16 451328
wst04-VHDL20_DWMO_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:22 452016
wst04-VHDL20_DWMO_070800_COR-2510070800-omedes-..> 07-Oct-2025 12:42:41 449944
wst04-VHDL20_DWMO_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:17 447983
wst04-VHDL20_DWMO_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:21 448934
wst04-VHDL20_DWMO_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:16 449053
wst04-VHDL20_DWMP_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:22 566681
wst04-VHDL20_DWMP_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:16 566509
wst04-VHDL20_DWMP_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 566619
wst04-VHDL20_DWMP_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:16 566986
wst04-VHDL20_DWMP_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:26 567780
wst04-VHDL20_DWMP_070800_COR-2510070800-omedes-..> 07-Oct-2025 12:42:31 547075
wst04-VHDL20_DWMP_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:17 545355
wst04-VHDL20_DWMP_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:28 545338
wst04-VHDL20_DWMP_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:16 545784
wst04-VHDL20_DWPG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:11 397623
wst04-VHDL20_DWPG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:12 355321
wst04-VHDL20_DWPG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 356422
wst04-VHDL20_DWPG_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:12 356649
wst04-VHDL20_DWPG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:22 400553
wst04-VHDL20_DWPG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:13 343461
wst04-VHDL20_DWPG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 343232
wst04-VHDL20_DWPG_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:12 343784
wst04-VHDL20_DWPH_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:11 308162
wst04-VHDL20_DWPH_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:12 303742
wst04-VHDL20_DWPH_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 259400
wst04-VHDL20_DWPH_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:00:12 259407
wst04-VHDL20_DWPH_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:22 303489
wst04-VHDL20_DWPH_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:13 300637
wst04-VHDL20_DWPH_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 256448
wst04-VHDL20_DWPH_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:00:12 256531
wst04-VHDL20_DWSG_060800-2510060800-omedes--0.pdf 06-Oct-2025 08:45:17 369129
wst04-VHDL20_DWSG_061300-2510061300-omedes--0.pdf 06-Oct-2025 13:45:11 361897
wst04-VHDL20_DWSG_061800-2510061800-omedes--0.pdf 06-Oct-2025 18:45:16 361937
wst04-VHDL20_DWSG_070200-2510070200-omedes--0.pdf 07-Oct-2025 02:45:26 362534
wst04-VHDL20_DWSG_070400-2510070400-omedes--0.pdf 07-Oct-2025 05:15:11 362647
wst04-VHDL20_DWSG_070800-2510070800-omedes--0.pdf 07-Oct-2025 08:45:11 362696
wst04-VHDL20_DWSG_071300-2510071300-omedes--0.pdf 07-Oct-2025 13:45:12 359262
wst04-VHDL20_DWSG_071800-2510071800-omedes--0.pdf 07-Oct-2025 18:45:17 358730
wst04-VHDL20_DWSG_080200-2510080200-omedes--0.pdf 08-Oct-2025 02:45:19 359714
wst04-VHDL20_DWSG_080400-2510080400-omedes--0.pdf 08-Oct-2025 05:15:12 358028