Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_170600                                 17-Mar-2026 14:19:35                4832
FPDL13_DWMZ_180600                                 18-Mar-2026 13:45:55                4611
SXDL31_DWAV_161800                                 16-Mar-2026 18:09:13                4144
SXDL31_DWAV_170800                                 17-Mar-2026 07:56:09                9565
SXDL31_DWAV_171800                                 17-Mar-2026 16:30:15                5596
SXDL31_DWAV_180800                                 18-Mar-2026 08:55:35                9830
SXDL31_DWAV_181800                                 18-Mar-2026 17:35:18                4054
SXDL31_DWAV_LATEST                                 18-Mar-2026 17:35:18                4054
SXDL33_DWAV_170000                                 17-Mar-2026 11:23:49                9509
SXDL33_DWAV_180000                                 18-Mar-2026 09:58:54               14200
SXDL33_DWAV_LATEST                                 18-Mar-2026 09:58:54               14200
ber01-FWDL39_DWMS_171230-2603171230-dsw--0-ia5     17-Mar-2026 12:36:53                1038
ber01-FWDL39_DWMS_181230-2603181230-dsw--0-ia5     18-Mar-2026 11:07:56                1271
ber01-VHDL13_DWEH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:28:16                2296
ber01-VHDL13_DWEH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:28:11                2617
ber01-VHDL13_DWEH_170400-2603170400-dsw--0-ia5     17-Mar-2026 05:58:17                2642
ber01-VHDL13_DWEH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:28:17                2712
ber01-VHDL13_DWEH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:28:17                2431
ber01-VHDL13_DWEH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:28:12                2487
ber01-VHDL13_DWEH_180400-2603180400-dsw--0-ia5     18-Mar-2026 05:58:17                2340
ber01-VHDL13_DWEH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:28:17                2346
ber01-VHDL13_DWHG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                3334
ber01-VHDL13_DWHG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:09                3376
ber01-VHDL13_DWHG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                3408
ber01-VHDL13_DWHG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2962
ber01-VHDL13_DWHG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:08                2840
ber01-VHDL13_DWHG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2764
ber01-VHDL13_DWHG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:06                2772
ber01-VHDL13_DWHG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2710
ber01-VHDL13_DWHH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                3087
ber01-VHDL13_DWHH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:09                3069
ber01-VHDL13_DWHH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                3062
ber01-VHDL13_DWHH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2637
ber01-VHDL13_DWHH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:08                2699
ber01-VHDL13_DWHH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2758
ber01-VHDL13_DWHH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:06                2746
ber01-VHDL13_DWHH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2707
ber01-VHDL13_DWLG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2067
ber01-VHDL13_DWLG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2153
ber01-VHDL13_DWLG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:01                2252
ber01-VHDL13_DWLG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2066
ber01-VHDL13_DWLG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2028
ber01-VHDL13_DWLG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2045
ber01-VHDL13_DWLG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2178
ber01-VHDL13_DWLG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2028
ber01-VHDL13_DWLH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2183
ber01-VHDL13_DWLH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2303
ber01-VHDL13_DWLH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:01                2458
ber01-VHDL13_DWLH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2398
ber01-VHDL13_DWLH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2097
ber01-VHDL13_DWLH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2108
ber01-VHDL13_DWLH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2179
ber01-VHDL13_DWLH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:51                2103
ber01-VHDL13_DWLI_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2261
ber01-VHDL13_DWLI_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2425
ber01-VHDL13_DWLI_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:01                2453
ber01-VHDL13_DWLI_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2331
ber01-VHDL13_DWLI_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2149
ber01-VHDL13_DWLI_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                1974
ber01-VHDL13_DWLI_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2128
ber01-VHDL13_DWLI_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2092
ber01-VHDL13_DWMG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2477
ber01-VHDL13_DWMG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2854
ber01-VHDL13_DWMG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                2862
ber01-VHDL13_DWMG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:01                2623
ber01-VHDL13_DWMG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2098
ber01-VHDL13_DWMG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2659
ber01-VHDL13_DWMG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2658
ber01-VHDL13_DWMG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2418
ber01-VHDL13_DWMO_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2197
ber01-VHDL13_DWMO_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2491
ber01-VHDL13_DWMO_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                2530
ber01-VHDL13_DWMO_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:01                2198
ber01-VHDL13_DWMO_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                1730
ber01-VHDL13_DWMO_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2033
ber01-VHDL13_DWMO_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2030
ber01-VHDL13_DWMO_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:51                1984
ber01-VHDL13_DWMP_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2357
ber01-VHDL13_DWMP_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2981
ber01-VHDL13_DWMP_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                2977
ber01-VHDL13_DWMP_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:01                2781
ber01-VHDL13_DWMP_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2308
ber01-VHDL13_DWMP_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2859
ber01-VHDL13_DWMP_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2878
ber01-VHDL13_DWMP_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:51                2653
ber01-VHDL13_DWOG_161700-2603161700-dsw--0-ia5     16-Mar-2026 19:00:01                3700
ber01-VHDL13_DWOG_161700_COR-2603161700-dsw--0-ia5 16-Mar-2026 19:59:51                4688
ber01-VHDL13_DWOG_170300-2603170300-dsw--0-ia5     17-Mar-2026 04:00:01                5214
ber01-VHDL13_DWOG_170300_COR-2603170300-dsw--0-ia5 17-Mar-2026 04:53:21                4743
ber01-VHDL13_DWOG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:01                4802
ber01-VHDL13_DWOG_171700-2603171700-dsw--0-ia5     17-Mar-2026 19:00:01                4309
ber01-VHDL13_DWOG_180300-2603180300-dsw--0-ia5     18-Mar-2026 04:00:02                4891
ber01-VHDL13_DWOG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:51                4115
ber01-VHDL13_DWOH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:28:16                2426
ber01-VHDL13_DWOH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:28:11                2552
ber01-VHDL13_DWOH_170400-2603170400-dsw--0-ia5     17-Mar-2026 05:58:17                2593
ber01-VHDL13_DWOH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:28:17                2569
ber01-VHDL13_DWOH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:28:17                2233
ber01-VHDL13_DWOH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:28:17                2655
ber01-VHDL13_DWOH_180400-2603180400-dsw--0-ia5     18-Mar-2026 05:58:11                2673
ber01-VHDL13_DWOH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:28:13                2540
ber01-VHDL13_DWOI_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:28:10                2186
ber01-VHDL13_DWOI_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:28:17                2509
ber01-VHDL13_DWOI_170400-2603170400-dsw--0-ia5     17-Mar-2026 05:58:17                2599
ber01-VHDL13_DWOI_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:28:11                3059
ber01-VHDL13_DWOI_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:28:11                2789
ber01-VHDL13_DWOI_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:28:12                2639
ber01-VHDL13_DWOI_180400-2603180400-dsw--0-ia5     18-Mar-2026 05:58:11                2568
ber01-VHDL13_DWOI_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:28:13                2504
ber01-VHDL13_DWON_161806-2603161806-dsw--0-ia5     16-Mar-2026 18:06:17                3414
ber01-VHDL13_DWON_161959-2603161959-dsw--0-ia5     16-Mar-2026 19:59:21                3743
ber01-VHDL13_DWON_170453-2603170453-dsw--0-ia5     17-Mar-2026 04:53:11                4136
ber01-VHDL13_DWON_170623-2603170623-dsw--0-ia5     17-Mar-2026 06:23:17                4332
ber01-VHDL13_DWON_170708-2603170708-dsw--0-ia5     17-Mar-2026 07:08:37                4034
ber01-VHDL13_DWON_170927-2603170927-dsw--0-ia5     17-Mar-2026 09:27:41                4034
ber01-VHDL13_DWON_171539-2603171539-dsw--0-ia5     17-Mar-2026 15:39:41                3373
ber01-VHDL13_DWON_171737-2603171737-dsw--0-ia5     17-Mar-2026 17:37:47                3497
ber01-VHDL13_DWON_172258-2603172258-dsw--0-ia5     17-Mar-2026 22:59:01                3223
ber01-VHDL13_DWON_180629-2603180629-dsw--0-ia5     18-Mar-2026 06:29:13                3263
ber01-VHDL13_DWON_180656-2603180656-dsw--0-ia5     18-Mar-2026 06:57:01                3246
ber01-VHDL13_DWON_180816-2603180816-dsw--0-ia5     18-Mar-2026 08:16:56                3321
ber01-VHDL13_DWON_181053-2603181053-dsw--0-ia5     18-Mar-2026 10:53:56                3843
ber01-VHDL13_DWON_181549-2603181549-dsw--0-ia5     18-Mar-2026 15:49:21                3069
ber01-VHDL13_DWON_181552-2603181552-dsw--0-ia5     18-Mar-2026 15:53:03                3069
ber01-VHDL13_DWON_181744-2603181744-dsw--0-ia5     18-Mar-2026 17:44:02                3069
ber01-VHDL13_DWPG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2111
ber01-VHDL13_DWPG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2402
ber01-VHDL13_DWPG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:01                2238
ber01-VHDL13_DWPG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2205
ber01-VHDL13_DWPG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2050
ber01-VHDL13_DWPG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2206
ber01-VHDL13_DWPG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2150
ber01-VHDL13_DWPG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:51                2040
ber01-VHDL13_DWPH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                2100
ber01-VHDL13_DWPH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                2249
ber01-VHDL13_DWPH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:01                2388
ber01-VHDL13_DWPH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:06                2297
ber01-VHDL13_DWPH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                2149
ber01-VHDL13_DWPH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                2176
ber01-VHDL13_DWPH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:01                2175
ber01-VHDL13_DWPH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                2164
ber01-VHDL13_DWSG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:30:06                3031
ber01-VHDL13_DWSG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:30:03                3105
ber01-VHDL13_DWSG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:06                3025
ber01-VHDL13_DWSG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:30:01                3026
ber01-VHDL13_DWSG_170800_COR-2603170800-dsw--0-ia5 17-Mar-2026 10:30:12                3341
ber01-VHDL13_DWSG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:30:03                3050
ber01-VHDL13_DWSG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:30:06                3115
ber01-VHDL13_DWSG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:08                3061
ber01-VHDL13_DWSG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:30:50                3279
ber01-VHDL17_DWOG_171200-2603171200-dsw--0-ia5     17-Mar-2026 12:50:28                2796
ber01-VHDL17_DWOG_181200-2603181200-dsw--0-ia5     18-Mar-2026 10:48:07                3685
swis2-VHDL20_DWEG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:06                2976
swis2-VHDL20_DWEG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:07                3026
swis2-VHDL20_DWEG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                2937
swis2-VHDL20_DWEG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3074
swis2-VHDL20_DWEG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2583
swis2-VHDL20_DWEG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                2955
swis2-VHDL20_DWEG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                3060
swis2-VHDL20_DWEG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:06                3147
swis2-VHDL20_DWEH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:06                2826
swis2-VHDL20_DWEH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:07                3056
swis2-VHDL20_DWEH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                2981
swis2-VHDL20_DWEH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3222
swis2-VHDL20_DWEH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2790
swis2-VHDL20_DWEH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                2812
swis2-VHDL20_DWEH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                2681
swis2-VHDL20_DWEH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:06                2852
swis2-VHDL20_DWEI_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:06                2538
swis2-VHDL20_DWEI_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:07                2801
swis2-VHDL20_DWEI_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                2954
swis2-VHDL20_DWEI_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3591
swis2-VHDL20_DWEI_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                3144
swis2-VHDL20_DWEI_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                2934
swis2-VHDL20_DWEI_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                2925
swis2-VHDL20_DWEI_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:06                3032
swis2-VHDL20_DWHG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:02                3517
swis2-VHDL20_DWHG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:01                3562
swis2-VHDL20_DWHG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:12                3591
swis2-VHDL20_DWHG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:06                3627
swis2-VHDL20_DWHG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                3023
swis2-VHDL20_DWHG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:06                2950
swis2-VHDL20_DWHG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:06                2955
swis2-VHDL20_DWHG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                3302
swis2-VHDL20_DWHH_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:02                3272
swis2-VHDL20_DWHH_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:01                3255
swis2-VHDL20_DWHH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:12                3248
swis2-VHDL20_DWHH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:06                3241
swis2-VHDL20_DWHH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2885
swis2-VHDL20_DWHH_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:06                2944
swis2-VHDL20_DWHH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:06                2932
swis2-VHDL20_DWHH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                3311
swis2-VHDL20_DWLG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:02                2585
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swis2-VHDL20_DWLG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2558
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swis2-VHDL20_DWLH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2901
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swis2-VHDL20_DWLI_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2824
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swis2-VHDL20_DWLI_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:06                2319
swis2-VHDL20_DWLI_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:12                2475
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swis2-VHDL20_DWMG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                3295
swis2-VHDL20_DWMG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3271
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swis2-VHDL20_DWMG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                3076
swis2-VHDL20_DWMG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                3099
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swis2-VHDL20_DWMO_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                2906
swis2-VHDL20_DWMO_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2740
swis2-VHDL20_DWMO_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2168
swis2-VHDL20_DWMO_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                2463
swis2-VHDL20_DWMO_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                2465
swis2-VHDL20_DWMO_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                2579
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swis2-VHDL20_DWMP_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:07                3508
swis2-VHDL20_DWMP_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                3403
swis2-VHDL20_DWMP_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3431
swis2-VHDL20_DWMP_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2743
swis2-VHDL20_DWMP_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:02                3287
swis2-VHDL20_DWMP_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                3322
swis2-VHDL20_DWMP_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                3259
swis2-VHDL20_DWPG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:02                2703
swis2-VHDL20_DWPG_170200-2603170200-dsw--0-ia5     17-Mar-2026 03:45:01                2787
swis2-VHDL20_DWPG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:12                2585
swis2-VHDL20_DWPG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2668
swis2-VHDL20_DWPG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2513
swis2-VHDL20_DWPG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:06                2536
swis2-VHDL20_DWPG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:12                2479
swis2-VHDL20_DWPG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                2502
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swis2-VHDL20_DWPH_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:00:12                2737
swis2-VHDL20_DWPH_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                2760
swis2-VHDL20_DWPH_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                2612
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swis2-VHDL20_DWPH_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:00:12                2506
swis2-VHDL20_DWPH_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:02                2626
swis2-VHDL20_DWSG_161800-2603161800-dsw--0-ia5     16-Mar-2026 19:45:02                3563
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swis2-VHDL20_DWSG_170400-2603170400-dsw--0-ia5     17-Mar-2026 06:15:05                3379
swis2-VHDL20_DWSG_170800-2603170800-dsw--0-ia5     17-Mar-2026 09:45:02                3549
swis2-VHDL20_DWSG_170800_COR-2603170800-dsw--0-ia5 17-Mar-2026 10:30:12                3870
swis2-VHDL20_DWSG_171300-2603171300-dsw--0-ia5     17-Mar-2026 14:45:02                3723
swis2-VHDL20_DWSG_171800-2603171800-dsw--0-ia5     17-Mar-2026 19:45:01                3405
swis2-VHDL20_DWSG_180200-2603180200-dsw--0-ia5     18-Mar-2026 03:45:06                3489
swis2-VHDL20_DWSG_180400-2603180400-dsw--0-ia5     18-Mar-2026 06:15:01                3416
swis2-VHDL20_DWSG_180800-2603180800-dsw--0-ia5     18-Mar-2026 09:45:06                3832
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wst04-VHDL20_DWEG_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:12              241975
wst04-VHDL20_DWEG_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:21              243065
wst04-VHDL20_DWEG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:16              242327
wst04-VHDL20_DWEG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:13              242345
wst04-VHDL20_DWEG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:11              240370
wst04-VHDL20_DWEG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:12              241893
wst04-VHDL20_DWEG_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:23              241310
wst04-VHDL20_DWEG_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:12              246027
wst04-VHDL20_DWEH_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:12              242432
wst04-VHDL20_DWEH_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:17              243859
wst04-VHDL20_DWEH_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:16              243372
wst04-VHDL20_DWEH_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:13              242404
wst04-VHDL20_DWEH_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:11              240787
wst04-VHDL20_DWEH_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:12              243079
wst04-VHDL20_DWEH_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:23              241221
wst04-VHDL20_DWEH_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:16              244341
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wst04-VHDL20_DWEI_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:21              345369
wst04-VHDL20_DWEI_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:22              345552
wst04-VHDL20_DWEI_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:17              343550
wst04-VHDL20_DWEI_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:11              342002
wst04-VHDL20_DWEI_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:12              343072
wst04-VHDL20_DWEI_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:27              342546
wst04-VHDL20_DWEI_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:16              348645
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wst04-VHDL20_DWHG_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:17              358872
wst04-VHDL20_DWHG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:12              358273
wst04-VHDL20_DWHG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:27              354044
wst04-VHDL20_DWHG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:21              353737
wst04-VHDL20_DWHG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:23              354040
wst04-VHDL20_DWHG_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:12              353250
wst04-VHDL20_DWHG_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:26              353837
wst04-VHDL20_DWHH_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:22              332086
wst04-VHDL20_DWHH_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:17              331768
wst04-VHDL20_DWHH_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:12              331741
wst04-VHDL20_DWHH_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:27              334427
wst04-VHDL20_DWHH_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:21              335108
wst04-VHDL20_DWHH_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:16              335390
wst04-VHDL20_DWHH_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:12              334737
wst04-VHDL20_DWHH_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:22              334847
wst04-VHDL20_DWLG_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:22              333044
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wst04-VHDL20_DWLG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:42              332695
wst04-VHDL20_DWLG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:25              336300
wst04-VHDL20_DWLG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:21              335604
wst04-VHDL20_DWLG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:27              336064
wst04-VHDL20_DWLG_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:42              336458
wst04-VHDL20_DWLG_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:32              334343
wst04-VHDL20_DWLH_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:26              340436
wst04-VHDL20_DWLH_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:27              341396
wst04-VHDL20_DWLH_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:42              340571
wst04-VHDL20_DWLH_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:31              340194
wst04-VHDL20_DWLH_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:21              339221
wst04-VHDL20_DWLH_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:27              339626
wst04-VHDL20_DWLH_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:42              339259
wst04-VHDL20_DWLH_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:32              339407
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wst04-VHDL20_DWLI_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:27              345656
wst04-VHDL20_DWLI_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:42              344712
wst04-VHDL20_DWLI_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:31              340563
wst04-VHDL20_DWLI_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:26              339942
wst04-VHDL20_DWLI_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:20              339700
wst04-VHDL20_DWLI_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:42              340068
wst04-VHDL20_DWLI_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:32              340609
wst04-VHDL20_DWMG_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:16              561191
wst04-VHDL20_DWMG_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:17              561865
wst04-VHDL20_DWMG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:16              561661
wst04-VHDL20_DWMG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:23              539561
wst04-VHDL20_DWMG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:17              538480
wst04-VHDL20_DWMG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:18              539431
wst04-VHDL20_DWMG_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:21              539338
wst04-VHDL20_DWMG_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:22              532415
wst04-VHDL20_DWMO_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:16              457147
wst04-VHDL20_DWMO_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:11              458080
wst04-VHDL20_DWMO_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:16              458520
wst04-VHDL20_DWMO_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:23              449601
wst04-VHDL20_DWMO_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:17              447512
wst04-VHDL20_DWMO_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:18              448406
wst04-VHDL20_DWMO_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:17              448844
wst04-VHDL20_DWMO_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:22              444746
wst04-VHDL20_DWMP_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:16              565585
wst04-VHDL20_DWMP_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:11              565686
wst04-VHDL20_DWMP_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:22              566736
wst04-VHDL20_DWMP_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:23              533742
wst04-VHDL20_DWMP_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:17              532835
wst04-VHDL20_DWMP_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:18              532404
wst04-VHDL20_DWMP_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:15:17              533410
wst04-VHDL20_DWMP_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:22              526642
wst04-VHDL20_DWPG_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:26              349855
wst04-VHDL20_DWPG_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:27              349930
wst04-VHDL20_DWPG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:30              349045
wst04-VHDL20_DWPG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:31              398419
wst04-VHDL20_DWPG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:26              353326
wst04-VHDL20_DWPG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:20              353978
wst04-VHDL20_DWPG_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:32              353728
wst04-VHDL20_DWPG_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:32              390771
wst04-VHDL20_DWPH_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:22              290238
wst04-VHDL20_DWPH_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:21              245201
wst04-VHDL20_DWPH_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:00:30              244590
wst04-VHDL20_DWPH_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:25              292848
wst04-VHDL20_DWPH_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:21              292660
wst04-VHDL20_DWPH_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:20              248186
wst04-VHDL20_DWPH_180400-2603180400-omedes--0.pdf  18-Mar-2026 06:00:32              248573
wst04-VHDL20_DWPH_180800-2603180800-omedes--0.pdf  18-Mar-2026 09:45:26              288557
wst04-VHDL20_DWSG_161800-2603161800-omedes--0.pdf  16-Mar-2026 19:45:12              353514
wst04-VHDL20_DWSG_170200-2603170200-omedes--0.pdf  17-Mar-2026 03:45:17              354664
wst04-VHDL20_DWSG_170400-2603170400-omedes--0.pdf  17-Mar-2026 06:15:12              355096
wst04-VHDL20_DWSG_170800-2603170800-omedes--0.pdf  17-Mar-2026 09:45:13              347530
wst04-VHDL20_DWSG_170800_COR-2603170800-omedes-..> 17-Mar-2026 10:30:23              347758
wst04-VHDL20_DWSG_171300-2603171300-omedes--0.pdf  17-Mar-2026 14:45:11              347278
wst04-VHDL20_DWSG_171800-2603171800-omedes--0.pdf  17-Mar-2026 19:45:11              347418
wst04-VHDL20_DWSG_180200-2603180200-omedes--0.pdf  18-Mar-2026 03:45:12              346780
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