Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Aug-2026 12:55:45 4530
FPDL13_DWMZ_180600 18-Aug-2026 12:38:44 4233
SXDL31_DWAV_170800 17-Aug-2026 07:28:45 6832
SXDL31_DWAV_171800 17-Aug-2026 16:33:14 9469
SXDL31_DWAV_180800 18-Aug-2026 07:32:08 8065
SXDL31_DWAV_181800 18-Aug-2026 15:59:40 13449
SXDL31_DWAV_LATEST 18-Aug-2026 15:59:40 13449
SXDL33_DWAV_170000 17-Aug-2026 10:10:33 17646
SXDL33_DWAV_180000 18-Aug-2026 10:08:04 9321
SXDL33_DWAV_LATEST 18-Aug-2026 10:08:04 9321
ber01-FWDL39_DWMS_171200-2608171200-dsw--0-ia5 17-Aug-2026 11:05:58 1580
ber01-FWDL39_DWMS_181200-2608181200-dsw--0-ia5 18-Aug-2026 11:23:23 2153
ber01-VHDL13_DWEG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2374
ber01-VHDL13_DWEG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:28:18 2633
ber01-VHDL13_DWEH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2415
ber01-VHDL13_DWEH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:28:18 2546
ber01-VHDL13_DWEI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:28:18 2368
ber01-VHDL13_DWEI_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:28:18 2872
ber01-VHDL13_DWHG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3009
ber01-VHDL13_DWHG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 3007
ber01-VHDL13_DWHH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3154
ber01-VHDL13_DWHH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 3015
ber01-VHDL13_DWLG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2859
ber01-VHDL13_DWLG_170800_COR-2608170800-dsw--0-ia5 17-Aug-2026 08:48:11 2791
ber01-VHDL13_DWLG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2708
ber01-VHDL13_DWLH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2764
ber01-VHDL13_DWLH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2637
ber01-VHDL13_DWLI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2201
ber01-VHDL13_DWLI_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2837
ber01-VHDL13_DWMO_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3314
ber01-VHDL13_DWMO_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 3709
ber01-VHDL13_DWMP_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3681
ber01-VHDL13_DWMP_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 3277
ber01-VHDL13_DWMP_180800_COR-2608180800-dsw--0-ia5 18-Aug-2026 08:52:08 3780
ber01-VHDL13_DWOG_170300-2608170300-dsw--0-ia5 17-Aug-2026 03:00:24 4013
ber01-VHDL13_DWOG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 3673
ber01-VHDL13_DWOG_171700-2608171700-dsw--0-ia5 17-Aug-2026 18:00:04 3373
ber01-VHDL13_DWOG_180300-2608180300-dsw--0-ia5 18-Aug-2026 03:00:05 4451
ber01-VHDL13_DWOG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 4515
ber01-VHDL13_DWOG_181700-2608181700-dsw--0-ia5 18-Aug-2026 18:00:03 4929
ber01-VHDL13_DWON_170131-2608170131-dsw--0-ia5 17-Aug-2026 01:31:35 3455
ber01-VHDL13_DWON_170512-2608170512-dsw--0-ia5 17-Aug-2026 05:12:29 3505
ber01-VHDL13_DWON_170915-2608170915-dsw--0-ia5 17-Aug-2026 09:15:33 3505
ber01-VHDL13_DWON_171340-2608171340-dsw--0-ia5 17-Aug-2026 13:40:19 3725
ber01-VHDL13_DWON_171432-2608171432-dsw--0-ia5 17-Aug-2026 14:32:39 3714
ber01-VHDL13_DWON_171722-2608171722-dsw--0-ia5 17-Aug-2026 17:22:54 3164
ber01-VHDL13_DWON_180002-2608180002-dsw--0-ia5 18-Aug-2026 00:02:09 4104
ber01-VHDL13_DWON_180054-2608180054-dsw--0-ia5 18-Aug-2026 00:55:05 4104
ber01-VHDL13_DWON_180235-2608180235-dsw--0-ia5 18-Aug-2026 02:35:49 4104
ber01-VHDL13_DWON_180516-2608180516-dsw--0-ia5 18-Aug-2026 05:16:44 4106
ber01-VHDL13_DWON_180606-2608180606-dsw--0-ia5 18-Aug-2026 06:06:54 3981
ber01-VHDL13_DWON_180759-2608180759-dsw--0-ia5 18-Aug-2026 07:59:43 3986
ber01-VHDL13_DWON_180811-2608180811-dsw--0-ia5 18-Aug-2026 08:11:38 4047
ber01-VHDL13_DWON_181454-2608181454-dsw--0-ia5 18-Aug-2026 14:55:20 4031
ber01-VHDL13_DWON_181638-2608181638-dsw--0-ia5 18-Aug-2026 16:38:30 3799
ber01-VHDL13_DWON_181653-2608181653-dsw--0-ia5 18-Aug-2026 16:53:58 3799
ber01-VHDL13_DWPG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2843
ber01-VHDL13_DWPG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2306
ber01-VHDL13_DWPH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 2468
ber01-VHDL13_DWPH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2972
ber01-VHDL13_DWSG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 3144
ber01-VHDL13_DWSG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 3307
ber01-VHDL17_DWOG_171200-2608171200-dsw--0-ia5 17-Aug-2026 11:34:31 4098
ber01-VHDL17_DWOG_181200-2608181200-dsw--0-ia5 18-Aug-2026 11:57:10 3410
swis2-VHDL20_DWEG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 884
swis2-VHDL20_DWEG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 895
swis2-VHDL20_DWEG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1013
swis2-VHDL20_DWEG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1095
swis2-VHDL20_DWEG_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:02 1051
swis2-VHDL20_DWEG_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:01:19 1052
swis2-VHDL20_DWEG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 1217
swis2-VHDL20_DWEG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1841
swis2-VHDL20_DWEH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:17 898
swis2-VHDL20_DWEH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 909
swis2-VHDL20_DWEH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1021
swis2-VHDL20_DWEH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1121
swis2-VHDL20_DWEH_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:02 832
swis2-VHDL20_DWEH_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:01:19 833
swis2-VHDL20_DWEH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 1244
swis2-VHDL20_DWEH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1575
swis2-VHDL20_DWEI_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:17 905
swis2-VHDL20_DWEI_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:01:19 916
swis2-VHDL20_DWEI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1070
swis2-VHDL20_DWEI_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1109
swis2-VHDL20_DWEI_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:02 1069
swis2-VHDL20_DWEI_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:01:19 1070
swis2-VHDL20_DWEI_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 1498
swis2-VHDL20_DWEI_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1904
swis2-VHDL20_DWHG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:45:51 1133
swis2-VHDL20_DWHG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1130
swis2-VHDL20_DWHG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:45:46 1277
swis2-VHDL20_DWHG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:45:21 1230
swis2-VHDL20_DWHG_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:45:14 1277
swis2-VHDL20_DWHG_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:17 1342
swis2-VHDL20_DWHG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:46:00 1214
swis2-VHDL20_DWHG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:45:11 1339
swis2-VHDL20_DWHH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:45:51 1490
swis2-VHDL20_DWHH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1477
swis2-VHDL20_DWHH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:45:47 1612
swis2-VHDL20_DWHH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:45:21 1342
swis2-VHDL20_DWHH_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:45:14 1379
swis2-VHDL20_DWHH_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:17 1436
swis2-VHDL20_DWHH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:46:00 1271
swis2-VHDL20_DWHH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:45:19 1393
swis2-VHDL20_DWLG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1089
swis2-VHDL20_DWLG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 1079
swis2-VHDL20_DWLG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1197
swis2-VHDL20_DWLG_170800_COR-2608170800-dsw--0-ia5 17-Aug-2026 08:48:49 1201
swis2-VHDL20_DWLG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1097
swis2-VHDL20_DWLG_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:30 1205
swis2-VHDL20_DWLG_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:13 1241
swis2-VHDL20_DWLG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:25 1327
swis2-VHDL20_DWLG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1281
swis2-VHDL20_DWLH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1153
swis2-VHDL20_DWLH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 951
swis2-VHDL20_DWLH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1111
swis2-VHDL20_DWLH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1412
swis2-VHDL20_DWLH_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:30 1053
swis2-VHDL20_DWLH_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:13 983
swis2-VHDL20_DWLH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:25 1094
swis2-VHDL20_DWLH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1036
swis2-VHDL20_DWLI_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 993
swis2-VHDL20_DWLI_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 982
swis2-VHDL20_DWLI_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 843
swis2-VHDL20_DWLI_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1020
swis2-VHDL20_DWLI_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:30 1220
swis2-VHDL20_DWLI_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:13 1271
swis2-VHDL20_DWLI_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:25 1404
swis2-VHDL20_DWLI_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1346
swis2-VHDL20_DWMO_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1152
swis2-VHDL20_DWMO_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:04 1153
swis2-VHDL20_DWMO_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 1469
swis2-VHDL20_DWMO_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1276
swis2-VHDL20_DWMO_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:15 1383
swis2-VHDL20_DWMO_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:03 1384
swis2-VHDL20_DWMO_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 2110
swis2-VHDL20_DWMO_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1789
swis2-VHDL20_DWMP_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1356
swis2-VHDL20_DWMP_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:04 1417
swis2-VHDL20_DWMP_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:16 1755
swis2-VHDL20_DWMP_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 1749
swis2-VHDL20_DWMP_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:15 1422
swis2-VHDL20_DWMP_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:03 1422
swis2-VHDL20_DWMP_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 1573
swis2-VHDL20_DWMP_180800_COR-2608180800-dsw--0-ia5 18-Aug-2026 08:52:08 3560
swis2-VHDL20_DWMP_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1753
swis2-VHDL20_DWPG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 1022
swis2-VHDL20_DWPG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 1287
swis2-VHDL20_DWPG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1277
swis2-VHDL20_DWPG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 891
swis2-VHDL20_DWPG_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:30 879
swis2-VHDL20_DWPG_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:13 856
swis2-VHDL20_DWPG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:25 966
swis2-VHDL20_DWPG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 859
swis2-VHDL20_DWPH_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:32 774
swis2-VHDL20_DWPH_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:14 784
swis2-VHDL20_DWPH_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:35 1008
swis2-VHDL20_DWPH_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:31:06 1073
swis2-VHDL20_DWPH_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:30 934
swis2-VHDL20_DWPH_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:13 907
swis2-VHDL20_DWPH_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:25 1012
swis2-VHDL20_DWPH_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:31:05 1051
swis2-VHDL20_DWSG_170200-2608170200-dsw--0-ia5 17-Aug-2026 02:30:15 1139
swis2-VHDL20_DWSG_170400-2608170400-dsw--0-ia5 17-Aug-2026 05:00:18 1121
swis2-VHDL20_DWSG_170800-2608170800-dsw--0-ia5 17-Aug-2026 08:30:03 1234
swis2-VHDL20_DWSG_171800-2608171800-dsw--0-ia5 17-Aug-2026 18:30:14 772
swis2-VHDL20_DWSG_180200-2608180200-dsw--0-ia5 18-Aug-2026 02:30:02 1102
swis2-VHDL20_DWSG_180400-2608180400-dsw--0-ia5 18-Aug-2026 05:00:17 1087
swis2-VHDL20_DWSG_180800-2608180800-dsw--0-ia5 18-Aug-2026 08:30:15 1541
swis2-VHDL20_DWSG_181800-2608181800-dsw--0-ia5 18-Aug-2026 18:30:16 1584
wst04-VHDL20_DWEG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 241580
wst04-VHDL20_DWEG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 241939
wst04-VHDL20_DWEG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 243289
wst04-VHDL20_DWEG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 243216
wst04-VHDL20_DWEG_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:28 243100
wst04-VHDL20_DWEG_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:13 243428
wst04-VHDL20_DWEG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:15 244720
wst04-VHDL20_DWEG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 251406
wst04-VHDL20_DWEH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:17 240870
wst04-VHDL20_DWEH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 241453
wst04-VHDL20_DWEH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 242750
wst04-VHDL20_DWEH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 244807
wst04-VHDL20_DWEH_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:28 244075
wst04-VHDL20_DWEH_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:13 244729
wst04-VHDL20_DWEH_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:15 246874
wst04-VHDL20_DWEH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 245946
wst04-VHDL20_DWEI_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:25 352713
wst04-VHDL20_DWEI_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:14 353032
wst04-VHDL20_DWEI_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 353830
wst04-VHDL20_DWEI_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 351790
wst04-VHDL20_DWEI_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 352262
wst04-VHDL20_DWEI_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:17 352530
wst04-VHDL20_DWEI_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:15 354160
wst04-VHDL20_DWEI_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 359910
wst04-VHDL20_DWHG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:45:51 361570
wst04-VHDL20_DWHG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 361389
wst04-VHDL20_DWHG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:45:46 362263
wst04-VHDL20_DWHG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:45:23 351835
wst04-VHDL20_DWHG_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:46:14 351456
wst04-VHDL20_DWHG_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:17 351432
wst04-VHDL20_DWHG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:46:00 352196
wst04-VHDL20_DWHG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:45:19 349712
wst04-VHDL20_DWHH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:45:51 350624
wst04-VHDL20_DWHH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 240785
wst04-VHDL20_DWHH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:45:47 350704
wst04-VHDL20_DWHH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:45:23 341185
wst04-VHDL20_DWHH_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:46:14 341143
wst04-VHDL20_DWHH_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:17 235156
wst04-VHDL20_DWHH_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:46:00 341218
wst04-VHDL20_DWHH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:45:19 339020
wst04-VHDL20_DWLG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:32 346783
wst04-VHDL20_DWLG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 346569
wst04-VHDL20_DWLG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 346820
wst04-VHDL20_DWLG_170800_COR-2608170800-omedes-..> 17-Aug-2026 08:48:14 346819
wst04-VHDL20_DWLG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 345074
wst04-VHDL20_DWLG_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 345486
wst04-VHDL20_DWLG_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:44 345244
wst04-VHDL20_DWLG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:47 345449
wst04-VHDL20_DWLG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 341255
wst04-VHDL20_DWLH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 344198
wst04-VHDL20_DWLH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 343285
wst04-VHDL20_DWLH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 343668
wst04-VHDL20_DWLH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 355596
wst04-VHDL20_DWLH_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 353580
wst04-VHDL20_DWLH_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:44 352697
wst04-VHDL20_DWLH_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:50 352916
wst04-VHDL20_DWLH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 345815
wst04-VHDL20_DWLI_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 341577
wst04-VHDL20_DWLI_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:42 341102
wst04-VHDL20_DWLI_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 384597
wst04-VHDL20_DWLI_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 338264
wst04-VHDL20_DWLI_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 339508
wst04-VHDL20_DWLI_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:44 339254
wst04-VHDL20_DWLI_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:47 384231
wst04-VHDL20_DWLI_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 349788
wst04-VHDL20_DWMO_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:17 456965
wst04-VHDL20_DWMO_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 456879
wst04-VHDL20_DWMO_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 456894
wst04-VHDL20_DWMO_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 350989
wst04-VHDL20_DWMO_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:28 454863
wst04-VHDL20_DWMO_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:13 455071
wst04-VHDL20_DWMO_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:25 457081
wst04-VHDL20_DWMO_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 360130
wst04-VHDL20_DWMP_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 579475
wst04-VHDL20_DWMP_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:18 579652
wst04-VHDL20_DWMP_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:35 470095
wst04-VHDL20_DWMP_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:26 458676
wst04-VHDL20_DWMP_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 566642
wst04-VHDL20_DWMP_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:17 566957
wst04-VHDL20_DWMP_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:25 458952
wst04-VHDL20_DWMP_180800_COR-2608180800-omedes-..> 18-Aug-2026 08:52:19 570405
wst04-VHDL20_DWMP_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 477040
wst04-VHDL20_DWPG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 248001
wst04-VHDL20_DWPG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:32 353088
wst04-VHDL20_DWPG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 397781
wst04-VHDL20_DWPG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 349840
wst04-VHDL20_DWPG_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 245572
wst04-VHDL20_DWPG_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:34 349773
wst04-VHDL20_DWPG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:47 394549
wst04-VHDL20_DWPG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 342911
wst04-VHDL20_DWPH_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:30 248772
wst04-VHDL20_DWPH_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:32 248177
wst04-VHDL20_DWPH_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:49 248459
wst04-VHDL20_DWPH_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:31:31 245729
wst04-VHDL20_DWPH_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:30 245163
wst04-VHDL20_DWPH_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:34 245116
wst04-VHDL20_DWPH_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:47 245278
wst04-VHDL20_DWPH_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:31:27 246403
wst04-VHDL20_DWSG_170200-2608170200-omedes--0.pdf 17-Aug-2026 02:30:15 357083
wst04-VHDL20_DWSG_170400-2608170400-omedes--0.pdf 17-Aug-2026 05:00:12 356650
wst04-VHDL20_DWSG_170800-2608170800-omedes--0.pdf 17-Aug-2026 08:30:16 357197
wst04-VHDL20_DWSG_171800-2608171800-omedes--0.pdf 17-Aug-2026 18:30:14 347392
wst04-VHDL20_DWSG_180200-2608180200-omedes--0.pdf 18-Aug-2026 02:30:28 347618
wst04-VHDL20_DWSG_180400-2608180400-omedes--0.pdf 18-Aug-2026 05:00:13 347402
wst04-VHDL20_DWSG_180800-2608180800-omedes--0.pdf 18-Aug-2026 08:30:25 348696
wst04-VHDL20_DWSG_181800-2608181800-omedes--0.pdf 18-Aug-2026 18:30:16 356976