Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_140600 14-Jun-2026 11:49:54 4499
FPDL13_DWMZ_150600 15-Jun-2026 13:16:05 4046
SXDL31_DWAV_141800 14-Jun-2026 16:37:37 7280
SXDL31_DWAV_150800 15-Jun-2026 07:37:43 8179
SXDL31_DWAV_151800 15-Jun-2026 16:50:04 7815
SXDL31_DWAV_160800 16-Jun-2026 08:02:48 12552
SXDL31_DWAV_LATEST 16-Jun-2026 08:02:48 12552
SXDL33_DWAV_150000 15-Jun-2026 09:57:19 11847
SXDL33_DWAV_160000 16-Jun-2026 09:19:11 15269
SXDL33_DWAV_LATEST 16-Jun-2026 09:19:11 15269
ber01-FWDL39_DWMS_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:35:09 1268
ber01-FWDL39_DWMS_151200-2606151200-dsw--0-ia5 15-Jun-2026 10:53:20 1126
ber01-VHDL13_DWEG_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:16 2411
ber01-VHDL13_DWEG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:18 2997
ber01-VHDL13_DWEG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:28:13 3411
ber01-VHDL13_DWEH_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:36 2297
ber01-VHDL13_DWEH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:12 2935
ber01-VHDL13_DWEH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:28:21 3002
ber01-VHDL13_DWEI_140800-2606140800-dsw--0-ia5 14-Jun-2026 19:53:52 2333
ber01-VHDL13_DWEI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:28:16 2811
ber01-VHDL13_DWEI_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:28:21 2930
ber01-VHDL13_DWHG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 3469
ber01-VHDL13_DWHG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2982
ber01-VHDL13_DWHH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 2867
ber01-VHDL13_DWHH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2382
ber01-VHDL13_DWLG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3088
ber01-VHDL13_DWLG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2845
ber01-VHDL13_DWLH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3131
ber01-VHDL13_DWLH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2760
ber01-VHDL13_DWLI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2722
ber01-VHDL13_DWLI_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2645
ber01-VHDL13_DWMO_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2890
ber01-VHDL13_DWMO_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 3586
ber01-VHDL13_DWMP_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2536
ber01-VHDL13_DWMP_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 3454
ber01-VHDL13_DWOG_141700-2606141700-dsw--0-ia5 14-Jun-2026 18:00:02 3580
ber01-VHDL13_DWOG_150300-2606150300-dsw--0-ia5 15-Jun-2026 03:00:03 3506
ber01-VHDL13_DWOG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 4136
ber01-VHDL13_DWOG_151700-2606151700-dsw--0-ia5 15-Jun-2026 18:00:02 3868
ber01-VHDL13_DWOG_160300-2606160300-dsw--0-ia5 16-Jun-2026 03:00:05 4042
ber01-VHDL13_DWOG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 3849
ber01-VHDL13_DWON_141325-2606141325-dsw--0-ia5 14-Jun-2026 13:26:03 4154
ber01-VHDL13_DWON_141728-2606141728-dsw--0-ia5 14-Jun-2026 17:28:27 3385
ber01-VHDL13_DWON_141741-2606141741-dsw--0-ia5 14-Jun-2026 17:41:47 3385
ber01-VHDL13_DWON_150035-2606150035-dsw--0-ia5 15-Jun-2026 00:35:08 3832
ber01-VHDL13_DWON_150149-2606150149-dsw--0-ia5 15-Jun-2026 01:49:46 3812
ber01-VHDL13_DWON_150517-2606150517-dsw--0-ia5 15-Jun-2026 05:17:11 3876
ber01-VHDL13_DWON_150611-2606150611-dsw--0-ia5 15-Jun-2026 06:11:57 3952
ber01-VHDL13_DWON_150811-2606150811-dsw--0-ia5 15-Jun-2026 08:11:31 4056
ber01-VHDL13_DWON_150910-2606150910-dsw--0-ia5 15-Jun-2026 09:10:52 4056
ber01-VHDL13_DWON_151017-2606151017-dsw--0-ia5 15-Jun-2026 10:17:51 4064
ber01-VHDL13_DWON_151440-2606151440-dsw--0-ia5 15-Jun-2026 14:40:32 3790
ber01-VHDL13_DWON_151703-2606151703-dsw--0-ia5 15-Jun-2026 17:03:11 3399
ber01-VHDL13_DWON_160113-2606160113-dsw--0-ia5 16-Jun-2026 01:13:41 4045
ber01-VHDL13_DWON_160204-2606160204-dsw--0-ia5 16-Jun-2026 02:04:46 4045
ber01-VHDL13_DWON_160521-2606160521-dsw--0-ia5 16-Jun-2026 05:21:57 4057
ber01-VHDL13_DWON_160559-2606160559-dsw--0-ia5 16-Jun-2026 05:59:31 3846
ber01-VHDL13_DWON_160749-2606160749-dsw--0-ia5 16-Jun-2026 07:49:16 3869
ber01-VHDL13_DWON_160830-2606160830-dsw--0-ia5 16-Jun-2026 08:30:37 3890
ber01-VHDL13_DWPG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 3104
ber01-VHDL13_DWPG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2811
ber01-VHDL13_DWPH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2872
ber01-VHDL13_DWPH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 2298
ber01-VHDL13_DWSG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 2363
ber01-VHDL13_DWSG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 3286
ber01-VHDL17_DWOG_141200-2606141200-dsw--0-ia5 14-Jun-2026 11:36:53 3479
ber01-VHDL17_DWOG_151200-2606151200-dsw--0-ia5 15-Jun-2026 10:54:11 3600
swis2-VHDL20_DWEG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1113
swis2-VHDL20_DWEG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 985
swis2-VHDL20_DWEG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1067
swis2-VHDL20_DWEG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:14 1296
swis2-VHDL20_DWEG_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 2243
swis2-VHDL20_DWEG_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1348
swis2-VHDL20_DWEG_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:01:21 1316
swis2-VHDL20_DWEG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1804
swis2-VHDL20_DWEH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1185
swis2-VHDL20_DWEH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 1000
swis2-VHDL20_DWEH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1102
swis2-VHDL20_DWEH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:14 1313
swis2-VHDL20_DWEH_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 1897
swis2-VHDL20_DWEH_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1048
swis2-VHDL20_DWEH_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:01:21 1139
swis2-VHDL20_DWEH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1500
swis2-VHDL20_DWEI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1181
swis2-VHDL20_DWEI_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 942
swis2-VHDL20_DWEI_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:01:12 1118
swis2-VHDL20_DWEI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:15 1335
swis2-VHDL20_DWEI_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 1883
swis2-VHDL20_DWEI_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1038
swis2-VHDL20_DWEI_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:01:21 1113
swis2-VHDL20_DWEI_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1474
swis2-VHDL20_DWHG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1538
swis2-VHDL20_DWHG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:45:08 1575
swis2-VHDL20_DWHG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1552
swis2-VHDL20_DWHG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:45:02 1818
swis2-VHDL20_DWHG_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:45:04 1518
swis2-VHDL20_DWHG_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:45:11 1460
swis2-VHDL20_DWHG_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:16 1458
swis2-VHDL20_DWHG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:45:13 1732
swis2-VHDL20_DWHH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:45:02 1721
swis2-VHDL20_DWHH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:45:08 1516
swis2-VHDL20_DWHH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1248
swis2-VHDL20_DWHH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:45:02 1358
swis2-VHDL20_DWHH_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:45:04 1317
swis2-VHDL20_DWHH_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:45:11 1041
swis2-VHDL20_DWHH_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:16 1042
swis2-VHDL20_DWHH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:45:04 1257
swis2-VHDL20_DWLG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1234
swis2-VHDL20_DWLG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1451
swis2-VHDL20_DWLG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1409
swis2-VHDL20_DWLG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1475
swis2-VHDL20_DWLG_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:31:04 1320
swis2-VHDL20_DWLG_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:25 1226
swis2-VHDL20_DWLG_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:12 1078
swis2-VHDL20_DWLG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:29 1117
swis2-VHDL20_DWLH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1261
swis2-VHDL20_DWLH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1408
swis2-VHDL20_DWLH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1391
swis2-VHDL20_DWLH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1484
swis2-VHDL20_DWLH_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:31:04 1374
swis2-VHDL20_DWLH_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:25 1288
swis2-VHDL20_DWLH_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:12 1115
swis2-VHDL20_DWLH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:29 1156
swis2-VHDL20_DWLI_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1015
swis2-VHDL20_DWLI_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1183
swis2-VHDL20_DWLI_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1099
swis2-VHDL20_DWLI_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1165
swis2-VHDL20_DWLI_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:31:04 1303
swis2-VHDL20_DWLI_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:25 1217
swis2-VHDL20_DWLI_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:12 1057
swis2-VHDL20_DWLI_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:29 1100
swis2-VHDL20_DWMO_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1113
swis2-VHDL20_DWMO_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 989
swis2-VHDL20_DWMO_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:03 1002
swis2-VHDL20_DWMO_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1236
swis2-VHDL20_DWMO_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 1457
swis2-VHDL20_DWMO_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1123
swis2-VHDL20_DWMO_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:01 1124
swis2-VHDL20_DWMO_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1801
swis2-VHDL20_DWMP_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:03 1244
swis2-VHDL20_DWMP_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:07 933
swis2-VHDL20_DWMP_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:03 941
swis2-VHDL20_DWMP_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1110
swis2-VHDL20_DWMP_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 1572
swis2-VHDL20_DWMP_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1446
swis2-VHDL20_DWMP_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:01 1446
swis2-VHDL20_DWMP_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1840
swis2-VHDL20_DWPG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1177
swis2-VHDL20_DWPG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1171
swis2-VHDL20_DWPG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1288
swis2-VHDL20_DWPG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1427
swis2-VHDL20_DWPG_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:31:04 1212
swis2-VHDL20_DWPG_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:25 1141
swis2-VHDL20_DWPG_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:12 1136
swis2-VHDL20_DWPG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:29 1177
swis2-VHDL20_DWPH_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:31:02 1690
swis2-VHDL20_DWPH_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:24 1392
swis2-VHDL20_DWPH_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:11 1308
swis2-VHDL20_DWPH_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:22 1308
swis2-VHDL20_DWPH_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:31:04 1055
swis2-VHDL20_DWPH_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:25 912
swis2-VHDL20_DWPH_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:12 887
swis2-VHDL20_DWPH_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:29 928
swis2-VHDL20_DWSG_141800-2606141800-dsw--0-ia5 14-Jun-2026 18:30:01 1102
swis2-VHDL20_DWSG_150200-2606150200-dsw--0-ia5 15-Jun-2026 02:30:01 844
swis2-VHDL20_DWSG_150400-2606150400-dsw--0-ia5 15-Jun-2026 05:00:17 909
swis2-VHDL20_DWSG_150800-2606150800-dsw--0-ia5 15-Jun-2026 08:30:01 1109
swis2-VHDL20_DWSG_151800-2606151800-dsw--0-ia5 15-Jun-2026 18:30:02 1249
swis2-VHDL20_DWSG_160200-2606160200-dsw--0-ia5 16-Jun-2026 02:30:02 1047
swis2-VHDL20_DWSG_160400-2606160400-dsw--0-ia5 16-Jun-2026 05:00:18 1082
swis2-VHDL20_DWSG_160800-2606160800-dsw--0-ia5 16-Jun-2026 08:30:19 1638
wst04-VHDL20_DWEG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 241683
wst04-VHDL20_DWEG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 240407
wst04-VHDL20_DWEG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 240318
wst04-VHDL20_DWEG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:15 241264
wst04-VHDL20_DWEG_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:13 246982
wst04-VHDL20_DWEG_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:13 244767
wst04-VHDL20_DWEG_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:12 244639
wst04-VHDL20_DWEG_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:19 246080
wst04-VHDL20_DWEH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:15 239515
wst04-VHDL20_DWEH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 238461
wst04-VHDL20_DWEH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 238704
wst04-VHDL20_DWEH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:14 239615
wst04-VHDL20_DWEH_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:13 245192
wst04-VHDL20_DWEH_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:13 243421
wst04-VHDL20_DWEH_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:12 243775
wst04-VHDL20_DWEH_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:19 245364
wst04-VHDL20_DWEI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343740
wst04-VHDL20_DWEI_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 343131
wst04-VHDL20_DWEI_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:13 343016
wst04-VHDL20_DWEI_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 343400
wst04-VHDL20_DWEI_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:20 351942
wst04-VHDL20_DWEI_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 350097
wst04-VHDL20_DWEI_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:18 349661
wst04-VHDL20_DWEI_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:19 351430
wst04-VHDL20_DWHG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 336568
wst04-VHDL20_DWHG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:45:20 336513
wst04-VHDL20_DWHG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 336126
wst04-VHDL20_DWHG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:45:12 337709
wst04-VHDL20_DWHG_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:45:12 343652
wst04-VHDL20_DWHG_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:45:11 343999
wst04-VHDL20_DWHG_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:16 343801
wst04-VHDL20_DWHG_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:45:13 345189
wst04-VHDL20_DWHH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:45:13 326497
wst04-VHDL20_DWHH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:45:20 326290
wst04-VHDL20_DWHH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 225991
wst04-VHDL20_DWHH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:45:12 324728
wst04-VHDL20_DWHH_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:45:12 322826
wst04-VHDL20_DWHH_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:45:11 322172
wst04-VHDL20_DWHH_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:16 222991
wst04-VHDL20_DWHH_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:45:13 322637
wst04-VHDL20_DWLG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337538
wst04-VHDL20_DWLG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 337712
wst04-VHDL20_DWLG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 337947
wst04-VHDL20_DWLG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:47 338131
wst04-VHDL20_DWLG_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:31:26 332394
wst04-VHDL20_DWLG_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 332142
wst04-VHDL20_DWLG_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:40 332800
wst04-VHDL20_DWLG_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:41 332982
wst04-VHDL20_DWLH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 333101
wst04-VHDL20_DWLH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 333270
wst04-VHDL20_DWLH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 333510
wst04-VHDL20_DWLH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 333714
wst04-VHDL20_DWLH_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:31:26 336384
wst04-VHDL20_DWLH_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 336112
wst04-VHDL20_DWLH_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:40 336691
wst04-VHDL20_DWLH_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:41 336888
wst04-VHDL20_DWLI_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 341239
wst04-VHDL20_DWLI_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:32 341936
wst04-VHDL20_DWLI_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:41 342013
wst04-VHDL20_DWLI_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 386811
wst04-VHDL20_DWLI_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:31:26 345282
wst04-VHDL20_DWLI_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 345033
wst04-VHDL20_DWLI_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:40 345620
wst04-VHDL20_DWLI_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:41 390395
wst04-VHDL20_DWMO_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 353665
wst04-VHDL20_DWMO_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:17 460301
wst04-VHDL20_DWMO_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 460207
wst04-VHDL20_DWMO_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 460759
wst04-VHDL20_DWMO_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:20 352844
wst04-VHDL20_DWMO_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:13 459610
wst04-VHDL20_DWMO_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:12 459802
wst04-VHDL20_DWMO_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:19 459344
wst04-VHDL20_DWMP_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 459630
wst04-VHDL20_DWMP_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:17 570178
wst04-VHDL20_DWMP_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:17 570095
wst04-VHDL20_DWMP_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 459641
wst04-VHDL20_DWMP_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:20 464530
wst04-VHDL20_DWMP_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 569603
wst04-VHDL20_DWMP_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:16 569435
wst04-VHDL20_DWMP_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:29 464857
wst04-VHDL20_DWPG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 337780
wst04-VHDL20_DWPG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 238368
wst04-VHDL20_DWPG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:31 338075
wst04-VHDL20_DWPG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 384516
wst04-VHDL20_DWPG_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:31:26 339628
wst04-VHDL20_DWPG_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:25 240256
wst04-VHDL20_DWPG_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:32 339975
wst04-VHDL20_DWPG_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:47 383990
wst04-VHDL20_DWPH_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:31:22 243201
wst04-VHDL20_DWPH_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:24 241998
wst04-VHDL20_DWPH_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:31 242065
wst04-VHDL20_DWPH_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:42 242537
wst04-VHDL20_DWPH_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:31:26 237539
wst04-VHDL20_DWPH_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:20 237005
wst04-VHDL20_DWPH_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:32 237510
wst04-VHDL20_DWPH_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:41 236559
wst04-VHDL20_DWSG_141800-2606141800-omedes--0.pdf 14-Jun-2026 18:30:26 343341
wst04-VHDL20_DWSG_150200-2606150200-omedes--0.pdf 15-Jun-2026 02:30:13 341628
wst04-VHDL20_DWSG_150400-2606150400-omedes--0.pdf 15-Jun-2026 05:00:11 342218
wst04-VHDL20_DWSG_150800-2606150800-omedes--0.pdf 15-Jun-2026 08:30:22 342815
wst04-VHDL20_DWSG_151800-2606151800-omedes--0.pdf 15-Jun-2026 18:30:13 351972
wst04-VHDL20_DWSG_160200-2606160200-omedes--0.pdf 16-Jun-2026 02:30:13 351623
wst04-VHDL20_DWSG_160400-2606160400-omedes--0.pdf 16-Jun-2026 05:00:12 351354
wst04-VHDL20_DWSG_160800-2606160800-omedes--0.pdf 16-Jun-2026 08:30:19 353458