Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_240600 24-Oct-2026 14:21:39 6516
FPDL13_DWMZ_250600 25-Oct-2026 12:39:22 21670
SXDL31_DWAV_231800 23-Oct-2026 15:56:40 14671
SXDL31_DWAV_240800 24-Oct-2026 08:01:39 8235
SXDL31_DWAV_241800 24-Oct-2026 16:55:30 10650
SXDL31_DWAV_250800 25-Oct-2026 08:36:41 9995
SXDL31_DWAV_LATEST 25-Oct-2026 08:36:41 9995
SXDL33_DWAV_240000 24-Oct-2026 10:31:51 5521
SXDL33_DWAV_250000 25-Oct-2026 11:39:50 5806
SXDL33_DWAV_LATEST 25-Oct-2026 11:39:50 5806
ber01-FWDL39_DWMS_241200-2610241200-dsw--0-ia5 24-Oct-2026 10:40:11 1402
ber01-FWDL39_DWMS_251200-2610251200-dsw--0-ia5 25-Oct-2026 12:35:20 1180
ber01-VHDL13_DWEG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:14 3587
ber01-VHDL13_DWEG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:19 3255
ber01-VHDL13_DWEG_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:58:21 3047
ber01-VHDL13_DWEH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:14 3776
ber01-VHDL13_DWEH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:13 3048
ber01-VHDL13_DWEH_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:58:19 3037
ber01-VHDL13_DWEI_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:14 3440
ber01-VHDL13_DWEI_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:13 3192
ber01-VHDL13_DWEI_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:58:21 3061
ber01-VHDL13_DWHG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 4947
ber01-VHDL13_DWHG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 4045
ber01-VHDL13_DWHH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 4696
ber01-VHDL13_DWHH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 4125
ber01-VHDL13_DWLG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:04 3971
ber01-VHDL13_DWLG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2796
ber01-VHDL13_DWLH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:04 3282
ber01-VHDL13_DWLH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 3011
ber01-VHDL13_DWLI_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:04 3567
ber01-VHDL13_DWLI_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2837
ber01-VHDL13_DWMO_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 3399
ber01-VHDL13_DWMO_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:07 3140
ber01-VHDL13_DWMP_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 4223
ber01-VHDL13_DWMP_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:07 3752
ber01-VHDL13_DWOG_231700-2610231700-dsw--0-ia5 23-Oct-2026 18:00:17 5381
ber01-VHDL13_DWOG_240300-2610240300-dsw--0-ia5 24-Oct-2026 03:01:16 5413
ber01-VHDL13_DWOG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 4853
ber01-VHDL13_DWOG_241700-2610241700-dsw--0-ia5 24-Oct-2026 18:00:04 4616
ber01-VHDL13_DWOG_250300-2610250300-dsw--0-ia5 25-Oct-2026 04:00:42 5167
ber01-VHDL13_DWOG_250300_COR-2610250300-dsw--0-ia5 25-Oct-2026 04:04:19 4952
ber01-VHDL13_DWOG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:07 4717
ber01-VHDL13_DWON_231607-2610231607-dsw--0-ia5 23-Oct-2026 16:07:23 3674
ber01-VHDL13_DWON_231728-2610231728-dsw--0-ia5 23-Oct-2026 17:28:23 3674
ber01-VHDL13_DWON_231812-2610231812-dsw--0-ia5 23-Oct-2026 18:13:03 3674
ber01-VHDL13_DWON_240151-2610240151-dsw--0-ia5 24-Oct-2026 01:51:45 3493
ber01-VHDL13_DWON_240257-2610240257-dsw--0-ia5 24-Oct-2026 02:59:11 3493
ber01-VHDL13_DWON_240527-2610240527-dsw--0-ia5 24-Oct-2026 05:27:34 3706
ber01-VHDL13_DWON_240557-2610240557-dsw--0-ia5 24-Oct-2026 05:57:18 4142
ber01-VHDL13_DWON_240824-2610240824-dsw--0-ia5 24-Oct-2026 08:24:44 4142
ber01-VHDL13_DWON_241439-2610241439-dsw--0-ia5 24-Oct-2026 14:40:07 3551
ber01-VHDL13_DWON_241734-2610241734-dsw--0-ia5 24-Oct-2026 17:34:40 3804
ber01-VHDL13_DWON_250403-2610250403-dsw--0-ia5 25-Oct-2026 04:04:06 4289
ber01-VHDL13_DWON_250629-2610250629-dsw--0-ia5 25-Oct-2026 06:29:38 4393
ber01-VHDL13_DWON_250631-2610250631-dsw--0-ia5 25-Oct-2026 06:32:21 4414
ber01-VHDL13_DWON_250632_COR-2610250632-dsw--0-ia5 25-Oct-2026 06:32:43 4418
ber01-VHDL13_DWON_250717-2610250717-dsw--0-ia5 25-Oct-2026 07:18:07 3978
ber01-VHDL13_DWON_250923-2610250923-dsw--0-ia5 25-Oct-2026 09:23:38 3914
ber01-VHDL13_DWPG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:04 2716
ber01-VHDL13_DWPG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2523
ber01-VHDL13_DWPH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:04 3172
ber01-VHDL13_DWPH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2730
ber01-VHDL13_DWSG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 3869
ber01-VHDL13_DWSG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 3495
ber01-VHDL17_DWOG_241200-2610241200-dsw--0-ia5 24-Oct-2026 11:14:00 3241
ber01-VHDL17_DWOG_251200-2610251200-dsw--0-ia5 25-Oct-2026 12:13:54 2695
swis2-VHDL20_DWEG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 1838
swis2-VHDL20_DWEG_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:08 1693
swis2-VHDL20_DWEG_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:01:23 1695
swis2-VHDL20_DWEG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 2162
swis2-VHDL20_DWEG_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 1846
swis2-VHDL20_DWEG_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:17 1749
swis2-VHDL20_DWEG_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:01:16 1743
swis2-VHDL20_DWEG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2031
swis2-VHDL20_DWEG_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:57:55 1538
swis2-VHDL20_DWEH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2404
swis2-VHDL20_DWEH_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:08 1073
swis2-VHDL20_DWEH_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:01:23 2152
swis2-VHDL20_DWEH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 2453
swis2-VHDL20_DWEH_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 2110
swis2-VHDL20_DWEH_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:17 1139
swis2-VHDL20_DWEH_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:01:16 1936
swis2-VHDL20_DWEH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 1818
swis2-VHDL20_DWEH_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:57:55 1484
swis2-VHDL20_DWEI_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2055
swis2-VHDL20_DWEI_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:08 1810
swis2-VHDL20_DWEI_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:01:23 1865
swis2-VHDL20_DWEI_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 2099
swis2-VHDL20_DWEI_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 1838
swis2-VHDL20_DWEI_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:17 1776
swis2-VHDL20_DWEI_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:01:16 1780
swis2-VHDL20_DWEI_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2060
swis2-VHDL20_DWEI_250800_COR-2610250800-dsw--0-ia5 25-Oct-2026 13:58:19 1588
swis2-VHDL20_DWHG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:45:25 4304
swis2-VHDL20_DWHG_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:18 2735
swis2-VHDL20_DWHG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 3576
swis2-VHDL20_DWHG_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:45:12 2528
swis2-VHDL20_DWHG_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 2194
swis2-VHDL20_DWHG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2424
swis2-VHDL20_DWHH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:45:25 3826
swis2-VHDL20_DWHH_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:46:12 2690
swis2-VHDL20_DWHH_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:18 2721
swis2-VHDL20_DWHH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 3634
swis2-VHDL20_DWHH_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:45:12 2600
swis2-VHDL20_DWHH_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:45:19 2451
swis2-VHDL20_DWHH_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 2391
swis2-VHDL20_DWHH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 2699
swis2-VHDL20_DWLG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:05 1884
swis2-VHDL20_DWLG_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:31 1622
swis2-VHDL20_DWLG_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:14 1715
swis2-VHDL20_DWLG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:29 2039
swis2-VHDL20_DWLG_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:31:24 1674
swis2-VHDL20_DWLG_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:59 1479
swis2-VHDL20_DWLG_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1305
swis2-VHDL20_DWLG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:26 1492
swis2-VHDL20_DWLH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:05 2023
swis2-VHDL20_DWLH_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:31 1473
swis2-VHDL20_DWLH_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:14 1598
swis2-VHDL20_DWLH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:29 2056
swis2-VHDL20_DWLH_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:31:24 1929
swis2-VHDL20_DWLH_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:59 1793
swis2-VHDL20_DWLH_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1698
swis2-VHDL20_DWLH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:26 1904
swis2-VHDL20_DWLI_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1869
swis2-VHDL20_DWLI_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:31 1481
swis2-VHDL20_DWLI_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:14 1795
swis2-VHDL20_DWLI_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:29 2039
swis2-VHDL20_DWLI_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:31:24 1886
swis2-VHDL20_DWLI_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:59 1549
swis2-VHDL20_DWLI_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1571
swis2-VHDL20_DWLI_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:26 1709
swis2-VHDL20_DWMO_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:09 1395
swis2-VHDL20_DWMO_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:04 1905
swis2-VHDL20_DWMO_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:04 1877
swis2-VHDL20_DWMO_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 2071
swis2-VHDL20_DWMO_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 1858
swis2-VHDL20_DWMO_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:07 1872
swis2-VHDL20_DWMO_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:10 1867
swis2-VHDL20_DWMO_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:07 2059
swis2-VHDL20_DWMP_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:09 2365
swis2-VHDL20_DWMP_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:04 2334
swis2-VHDL20_DWMP_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:04 2321
swis2-VHDL20_DWMP_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 2616
swis2-VHDL20_DWMP_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 2379
swis2-VHDL20_DWMP_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:07 2246
swis2-VHDL20_DWMP_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:10 2252
swis2-VHDL20_DWMP_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:07 2563
swis2-VHDL20_DWPG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1411
swis2-VHDL20_DWPG_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:31 1284
swis2-VHDL20_DWPG_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:14 1278
swis2-VHDL20_DWPG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:29 1571
swis2-VHDL20_DWPG_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:31:24 1566
swis2-VHDL20_DWPG_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:59 1595
swis2-VHDL20_DWPG_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1487
swis2-VHDL20_DWPG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:26 1693
swis2-VHDL20_DWPH_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:31:12 1705
swis2-VHDL20_DWPH_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:31 1522
swis2-VHDL20_DWPH_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:14 1553
swis2-VHDL20_DWPH_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:29 1928
swis2-VHDL20_DWPH_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:31:24 1857
swis2-VHDL20_DWPH_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:59 1573
swis2-VHDL20_DWPH_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1486
swis2-VHDL20_DWPH_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:26 1728
swis2-VHDL20_DWSG_231800-2610231800-dsw--0-ia5 23-Oct-2026 18:30:03 2642
swis2-VHDL20_DWSG_240200-2610240200-dsw--0-ia5 24-Oct-2026 02:30:04 2159
swis2-VHDL20_DWSG_240400-2610240400-dsw--0-ia5 24-Oct-2026 05:00:18 2113
swis2-VHDL20_DWSG_240400_COR-2610240400-dsw--0-ia5 24-Oct-2026 05:01:19 1818
swis2-VHDL20_DWSG_240800-2610240800-dsw--0-ia5 24-Oct-2026 08:30:10 1975
swis2-VHDL20_DWSG_241800-2610241800-dsw--0-ia5 24-Oct-2026 18:30:03 1825
swis2-VHDL20_DWSG_250200-2610250200-dsw--0-ia5 25-Oct-2026 03:30:07 1610
swis2-VHDL20_DWSG_250400-2610250400-dsw--0-ia5 25-Oct-2026 06:00:14 1718
swis2-VHDL20_DWSG_250800-2610250800-dsw--0-ia5 25-Oct-2026 09:30:09 1980
wst04-VHDL20_DWEG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:19 246996
wst04-VHDL20_DWEG_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:18 247363
wst04-VHDL20_DWEG_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:14 247417
wst04-VHDL20_DWEG_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:24 248587
wst04-VHDL20_DWEG_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:19 242392
wst04-VHDL20_DWEG_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 242805
wst04-VHDL20_DWEG_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:14 242294
wst04-VHDL20_DWEG_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:19 242942
wst04-VHDL20_DWEG_250800_COR-2610250800-omedes-..> 25-Oct-2026 13:58:21 239583
wst04-VHDL20_DWEH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:15 240799
wst04-VHDL20_DWEH_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:18 243150
wst04-VHDL20_DWEH_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:14 243076
wst04-VHDL20_DWEH_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:24 243803
wst04-VHDL20_DWEH_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:13 241727
wst04-VHDL20_DWEH_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 244416
wst04-VHDL20_DWEH_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:14 243883
wst04-VHDL20_DWEH_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:19 243380
wst04-VHDL20_DWEH_250800_COR-2610250800-omedes-..> 25-Oct-2026 13:58:21 234711
wst04-VHDL20_DWEI_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:19 356470
wst04-VHDL20_DWEI_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:18 356328
wst04-VHDL20_DWEI_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:14 356825
wst04-VHDL20_DWEI_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:24 357432
wst04-VHDL20_DWEI_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:19 348627
wst04-VHDL20_DWEI_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 348573
wst04-VHDL20_DWEI_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:19 348555
wst04-VHDL20_DWEI_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:26 348797
wst04-VHDL20_DWEI_250800_COR-2610250800-omedes-..> 25-Oct-2026 13:58:21 342034
wst04-VHDL20_DWHG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:45:25 344223
wst04-VHDL20_DWHG_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:46:12 342828
wst04-VHDL20_DWHG_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:18 342813
wst04-VHDL20_DWHG_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:44 345048
wst04-VHDL20_DWHG_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:45:18 341666
wst04-VHDL20_DWHG_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:45:19 340930
wst04-VHDL20_DWHG_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:19 341457
wst04-VHDL20_DWHG_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 342226
wst04-VHDL20_DWHH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:45:25 339474
wst04-VHDL20_DWHH_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:46:12 338793
wst04-VHDL20_DWHH_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:18 235719
wst04-VHDL20_DWHH_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:44 340242
wst04-VHDL20_DWHH_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:45:18 332698
wst04-VHDL20_DWHH_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:45:19 332451
wst04-VHDL20_DWHH_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:46 230128
wst04-VHDL20_DWHH_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 332764
wst04-VHDL20_DWLG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 335188
wst04-VHDL20_DWLG_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:31 334965
wst04-VHDL20_DWLG_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:42 334788
wst04-VHDL20_DWLG_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:48 335413
wst04-VHDL20_DWLG_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:31:27 324048
wst04-VHDL20_DWLG_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:59 322893
wst04-VHDL20_DWLG_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:48 322627
wst04-VHDL20_DWLG_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 323935
wst04-VHDL20_DWLH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:35 338908
wst04-VHDL20_DWLH_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:31 337389
wst04-VHDL20_DWLH_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:42 338041
wst04-VHDL20_DWLH_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:46 339008
wst04-VHDL20_DWLH_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:31:29 332541
wst04-VHDL20_DWLH_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:59 331444
wst04-VHDL20_DWLH_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:48 331126
wst04-VHDL20_DWLH_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 331748
wst04-VHDL20_DWLI_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 340018
wst04-VHDL20_DWLI_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:31 339818
wst04-VHDL20_DWLI_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:42 340123
wst04-VHDL20_DWLI_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:46 385335
wst04-VHDL20_DWLI_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:31:29 331802
wst04-VHDL20_DWLI_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:59 331731
wst04-VHDL20_DWLI_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:48 331553
wst04-VHDL20_DWLI_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 376673
wst04-VHDL20_DWMO_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:19 452670
wst04-VHDL20_DWMO_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:14 453821
wst04-VHDL20_DWMO_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:18 454947
wst04-VHDL20_DWMO_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:29 454380
wst04-VHDL20_DWMO_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:19 449630
wst04-VHDL20_DWMO_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 449651
wst04-VHDL20_DWMO_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:19 450912
wst04-VHDL20_DWMO_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:19 450702
wst04-VHDL20_DWMP_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:28 574775
wst04-VHDL20_DWMP_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:14 573899
wst04-VHDL20_DWMP_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:22 575130
wst04-VHDL20_DWMP_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:29 575294
wst04-VHDL20_DWMP_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:19 563168
wst04-VHDL20_DWMP_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 562697
wst04-VHDL20_DWMP_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:19 563420
wst04-VHDL20_DWMP_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:28 564075
wst04-VHDL20_DWPG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 339663
wst04-VHDL20_DWPG_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:31 239039
wst04-VHDL20_DWPG_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:32 338643
wst04-VHDL20_DWPG_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:46 384574
wst04-VHDL20_DWPG_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:31:27 336669
wst04-VHDL20_DWPG_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:59 238439
wst04-VHDL20_DWPG_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:46 336428
wst04-VHDL20_DWPG_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 381525
wst04-VHDL20_DWPH_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:31:23 241066
wst04-VHDL20_DWPH_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:31 241510
wst04-VHDL20_DWPH_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:32 241392
wst04-VHDL20_DWPH_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:46 242077
wst04-VHDL20_DWPH_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:31:27 238128
wst04-VHDL20_DWPH_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:59 237094
wst04-VHDL20_DWPH_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:46 236846
wst04-VHDL20_DWPH_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:49 237352
wst04-VHDL20_DWSG_231800-2610231800-omedes--0.pdf 23-Oct-2026 18:30:13 352571
wst04-VHDL20_DWSG_240200-2610240200-omedes--0.pdf 24-Oct-2026 02:30:14 352654
wst04-VHDL20_DWSG_240400-2610240400-omedes--0.pdf 24-Oct-2026 05:00:14 352580
wst04-VHDL20_DWSG_240400_COR-2610240400-omedes-..> 24-Oct-2026 05:01:23 351661
wst04-VHDL20_DWSG_240800-2610240800-omedes--0.pdf 24-Oct-2026 08:30:24 351608
wst04-VHDL20_DWSG_241800-2610241800-omedes--0.pdf 24-Oct-2026 18:30:13 346415
wst04-VHDL20_DWSG_250200-2610250200-omedes--0.pdf 25-Oct-2026 03:30:33 345893
wst04-VHDL20_DWSG_250400-2610250400-omedes--0.pdf 25-Oct-2026 06:00:14 346193
wst04-VHDL20_DWSG_250800-2610250800-omedes--0.pdf 25-Oct-2026 09:30:13 346559