Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_160600                                 16-Jan-2026 14:03:34                8327
FPDL13_DWMZ_170600                                 17-Jan-2026 11:03:48                3675
SXDL31_DWAV_160800                                 16-Jan-2026 08:40:53               12076
SXDL31_DWAV_161800                                 16-Jan-2026 15:01:26                7333
SXDL31_DWAV_170800                                 17-Jan-2026 09:52:55               11986
SXDL31_DWAV_171800                                 17-Jan-2026 17:13:13                6369
SXDL31_DWAV_LATEST                                 17-Jan-2026 17:13:13                6369
SXDL33_DWAV_160000                                 16-Jan-2026 09:46:19                5877
SXDL33_DWAV_170000                                 17-Jan-2026 11:07:21                8527
SXDL33_DWAV_LATEST                                 17-Jan-2026 11:07:21                8527
ber01-FWDL39_DWMS_161230-2601161230-dsw--0-ia5     16-Jan-2026 13:02:07                 944
ber01-FWDL39_DWMS_171230-2601171230-dsw--0-ia5     17-Jan-2026 12:38:05                1728
ber01-VHDL13_DWEH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:28:12                3068
ber01-VHDL13_DWEH_160400-2601160400-dsw--0-ia5     16-Jan-2026 05:58:16                3204
ber01-VHDL13_DWEH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:28:16                3614
ber01-VHDL13_DWEH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:28:16                3252
ber01-VHDL13_DWEH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:28:12                3093
ber01-VHDL13_DWEH_170400-2601170400-dsw--0-ia5     17-Jan-2026 05:58:16                3290
ber01-VHDL13_DWEH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:28:17                2776
ber01-VHDL13_DWEH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:28:17                2814
ber01-VHDL13_DWHG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:07                3695
ber01-VHDL13_DWHG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:08                3906
ber01-VHDL13_DWHG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                3915
ber01-VHDL13_DWHG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:07                3037
ber01-VHDL13_DWHG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:10                3113
ber01-VHDL13_DWHG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:07                3113
ber01-VHDL13_DWHG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                3113
ber01-VHDL13_DWHG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2877
ber01-VHDL13_DWHH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:07                3067
ber01-VHDL13_DWHH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:08                3414
ber01-VHDL13_DWHH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                3371
ber01-VHDL13_DWHH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:07                2649
ber01-VHDL13_DWHH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:10                2738
ber01-VHDL13_DWHH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:07                2741
ber01-VHDL13_DWHH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                2346
ber01-VHDL13_DWHH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2229
ber01-VHDL13_DWLG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2902
ber01-VHDL13_DWLG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                3050
ber01-VHDL13_DWLG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                3224
ber01-VHDL13_DWLG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                2599
ber01-VHDL13_DWLG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                2771
ber01-VHDL13_DWLG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                2742
ber01-VHDL13_DWLG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                2994
ber01-VHDL13_DWLG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                3129
ber01-VHDL13_DWLH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2441
ber01-VHDL13_DWLH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                2330
ber01-VHDL13_DWLH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                2423
ber01-VHDL13_DWLH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                1802
ber01-VHDL13_DWLH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                1800
ber01-VHDL13_DWLH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                1795
ber01-VHDL13_DWLH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                1847
ber01-VHDL13_DWLH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2011
ber01-VHDL13_DWLI_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2127
ber01-VHDL13_DWLI_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                2012
ber01-VHDL13_DWLI_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                2084
ber01-VHDL13_DWLI_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                1699
ber01-VHDL13_DWLI_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                1779
ber01-VHDL13_DWLI_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                1654
ber01-VHDL13_DWLI_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                1743
ber01-VHDL13_DWLI_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                1807
ber01-VHDL13_DWMG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                3378
ber01-VHDL13_DWMG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                3384
ber01-VHDL13_DWMG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:01                2682
ber01-VHDL13_DWMG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                2414
ber01-VHDL13_DWMG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                2955
ber01-VHDL13_DWMG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                3043
ber01-VHDL13_DWMG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                3433
ber01-VHDL13_DWMG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2987
ber01-VHDL13_DWMO_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                3291
ber01-VHDL13_DWMO_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                3306
ber01-VHDL13_DWMO_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:01                2691
ber01-VHDL13_DWMO_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                2276
ber01-VHDL13_DWMO_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                2892
ber01-VHDL13_DWMO_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                2686
ber01-VHDL13_DWMO_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                2949
ber01-VHDL13_DWMO_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2583
ber01-VHDL13_DWMP_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                3619
ber01-VHDL13_DWMP_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                3623
ber01-VHDL13_DWMP_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:01                3049
ber01-VHDL13_DWMP_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                2682
ber01-VHDL13_DWMP_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                3245
ber01-VHDL13_DWMP_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                3238
ber01-VHDL13_DWMP_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                3544
ber01-VHDL13_DWMP_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                3132
ber01-VHDL13_DWOG_160300-2601160300-dsw--0-ia5     16-Jan-2026 04:00:08                4486
ber01-VHDL13_DWOG_160300_COR-2601160300-dsw--0-ia5 16-Jan-2026 04:18:47                4495
ber01-VHDL13_DWOG_160800-2601160800-dsw--0-ia5     16-Jan-2026 15:44:56                4337
ber01-VHDL13_DWOG_161700-2601161700-dsw--0-ia5     16-Jan-2026 19:00:02                4321
ber01-VHDL13_DWOG_170300-2601170300-dsw--0-ia5     17-Jan-2026 04:00:04                4543
ber01-VHDL13_DWOG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                4240
ber01-VHDL13_DWOG_171700-2601171700-dsw--0-ia5     17-Jan-2026 19:00:07                3874
ber01-VHDL13_DWOH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:28:12                3117
ber01-VHDL13_DWOH_160400-2601160400-dsw--0-ia5     16-Jan-2026 05:58:11                3078
ber01-VHDL13_DWOH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:28:12                2955
ber01-VHDL13_DWOH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:28:16                2696
ber01-VHDL13_DWOH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:28:12                2721
ber01-VHDL13_DWOH_170400-2601170400-dsw--0-ia5     17-Jan-2026 05:58:12                2934
ber01-VHDL13_DWOH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:28:17                2827
ber01-VHDL13_DWOH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:28:11                2713
ber01-VHDL13_DWOI_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:28:16                2722
ber01-VHDL13_DWOI_160400-2601160400-dsw--0-ia5     16-Jan-2026 05:58:11                2778
ber01-VHDL13_DWOI_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:28:12                3138
ber01-VHDL13_DWOI_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:28:12                2754
ber01-VHDL13_DWOI_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:28:12                2679
ber01-VHDL13_DWOI_170400-2601170400-dsw--0-ia5     17-Jan-2026 05:58:12                2863
ber01-VHDL13_DWOI_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:28:11                2884
ber01-VHDL13_DWOI_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:28:11                2910
ber01-VHDL13_DWON_160151-2601160151-dsw--0-ia5     16-Jan-2026 01:51:11                4198
ber01-VHDL13_DWON_160337-2601160337-dsw--0-ia5     16-Jan-2026 03:38:02                4198
ber01-VHDL13_DWON_160418-2601160418-dsw--0-ia5     16-Jan-2026 04:18:17                4198
ber01-VHDL13_DWON_160630-2601160630-dsw--0-ia5     16-Jan-2026 06:30:51                3710
ber01-VHDL13_DWON_160728-2601160728-dsw--0-ia5     16-Jan-2026 07:28:15                4177
ber01-VHDL13_DWON_160946-2601160946-dsw--0-ia5     16-Jan-2026 09:46:31                4177
ber01-VHDL13_DWON_161422-2601161422-dsw--0-ia5     16-Jan-2026 14:23:01                4286
ber01-VHDL13_DWON_161544-2601161544-dsw--0-ia5     16-Jan-2026 15:44:26                3414
ber01-VHDL13_DWON_161819-2601161819-dsw--0-ia5     16-Jan-2026 18:19:52                3531
ber01-VHDL13_DWON_170149-2601170149-dsw--0-ia5     17-Jan-2026 01:49:17                4351
ber01-VHDL13_DWON_170342-2601170342-dsw--0-ia5     17-Jan-2026 03:42:47                3888
ber01-VHDL13_DWON_170611-2601170611-dsw--0-ia5     17-Jan-2026 06:11:01                3465
ber01-VHDL13_DWON_170656-2601170656-dsw--0-ia5     17-Jan-2026 06:56:36                3722
ber01-VHDL13_DWON_170920-2601170920-dsw--0-ia5     17-Jan-2026 09:20:58                3644
ber01-VHDL13_DWON_171000-2601171000-dsw--0-ia5     17-Jan-2026 10:00:47                3644
ber01-VHDL13_DWON_171555-2601171555-dsw--0-ia5     17-Jan-2026 15:55:28                3105
ber01-VHDL13_DWON_171729-2601171729-dsw--0-ia5     17-Jan-2026 17:29:42                3093
ber01-VHDL13_DWPG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2005
ber01-VHDL13_DWPG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                2136
ber01-VHDL13_DWPG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                2172
ber01-VHDL13_DWPG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                1806
ber01-VHDL13_DWPG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                1915
ber01-VHDL13_DWPG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                2018
ber01-VHDL13_DWPG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                1874
ber01-VHDL13_DWPG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2159
ber01-VHDL13_DWPH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2017
ber01-VHDL13_DWPH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:01                2098
ber01-VHDL13_DWPH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                2196
ber01-VHDL13_DWPH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                1833
ber01-VHDL13_DWPH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                2024
ber01-VHDL13_DWPH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:01                1825
ber01-VHDL13_DWPH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                1834
ber01-VHDL13_DWPH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2068
ber01-VHDL13_DWSG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:30:01                2576
ber01-VHDL13_DWSG_160200_COR-2601160200-dsw--0-ia5 16-Jan-2026 03:35:27                2577
ber01-VHDL13_DWSG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:07                2586
ber01-VHDL13_DWSG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:30:12                2785
ber01-VHDL13_DWSG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:30:02                2404
ber01-VHDL13_DWSG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:30:03                2747
ber01-VHDL13_DWSG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:07                2735
ber01-VHDL13_DWSG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:30:13                2497
ber01-VHDL13_DWSG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:30:09                2120
ber01-VHDL17_DWOG_161200-2601161200-dsw--0-ia5     16-Jan-2026 12:06:03                2356
ber01-VHDL17_DWOG_171200-2601171200-dsw--0-ia5     17-Jan-2026 12:34:58                3134
swis2-VHDL20_DWEG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3397
swis2-VHDL20_DWEG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:06                3496
swis2-VHDL20_DWEG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                3607
swis2-VHDL20_DWEG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                3120
swis2-VHDL20_DWEG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3094
swis2-VHDL20_DWEG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:07                3345
swis2-VHDL20_DWEG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:02                3419
swis2-VHDL20_DWEG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3121
swis2-VHDL20_DWEH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3393
swis2-VHDL20_DWEH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:06                3678
swis2-VHDL20_DWEH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                4345
swis2-VHDL20_DWEH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                3751
swis2-VHDL20_DWEH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3558
swis2-VHDL20_DWEH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:07                3675
swis2-VHDL20_DWEH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:02                3416
swis2-VHDL20_DWEH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3237
swis2-VHDL20_DWEI_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3018
swis2-VHDL20_DWEI_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:06                3237
swis2-VHDL20_DWEI_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                3857
swis2-VHDL20_DWEI_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                3213
swis2-VHDL20_DWEI_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3078
swis2-VHDL20_DWEI_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:07                3250
swis2-VHDL20_DWEI_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:02                3477
swis2-VHDL20_DWEI_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3297
swis2-VHDL20_DWHG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3881
swis2-VHDL20_DWHG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:07                4089
swis2-VHDL20_DWHG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                4624
swis2-VHDL20_DWHG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                3220
swis2-VHDL20_DWHG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3299
swis2-VHDL20_DWHG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:07                3296
swis2-VHDL20_DWHG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                3756
swis2-VHDL20_DWHG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:06                3060
swis2-VHDL20_DWHH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3253
swis2-VHDL20_DWHH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:08                3600
swis2-VHDL20_DWHH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                3996
swis2-VHDL20_DWHH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2835
swis2-VHDL20_DWHH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                2924
swis2-VHDL20_DWHH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:07                2927
swis2-VHDL20_DWHH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                2908
swis2-VHDL20_DWHH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:06                2415
swis2-VHDL20_DWLG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3303
swis2-VHDL20_DWLG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:12                3440
swis2-VHDL20_DWLG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                3786
swis2-VHDL20_DWLG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2989
swis2-VHDL20_DWLG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3164
swis2-VHDL20_DWLG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:11                3135
swis2-VHDL20_DWLG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                3546
swis2-VHDL20_DWLG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3519
swis2-VHDL20_DWLH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                2840
swis2-VHDL20_DWLH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:12                2725
swis2-VHDL20_DWLH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                2994
swis2-VHDL20_DWLH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2197
swis2-VHDL20_DWLH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                2198
swis2-VHDL20_DWLH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:11                2195
swis2-VHDL20_DWLH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                2410
swis2-VHDL20_DWLH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                2408
swis2-VHDL20_DWLI_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                2531
swis2-VHDL20_DWLI_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:12                2402
swis2-VHDL20_DWLI_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                2644
swis2-VHDL20_DWLI_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2089
swis2-VHDL20_DWLI_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                2172
swis2-VHDL20_DWLI_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:11                2048
swis2-VHDL20_DWLI_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                2295
swis2-VHDL20_DWLI_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                2198
swis2-VHDL20_DWMG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3801
swis2-VHDL20_DWMG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:02                3812
swis2-VHDL20_DWMG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                3235
swis2-VHDL20_DWMG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2838
swis2-VHDL20_DWMG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                3395
swis2-VHDL20_DWMG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:01                3432
swis2-VHDL20_DWMG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                4075
swis2-VHDL20_DWMG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3415
swis2-VHDL20_DWMO_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                3720
swis2-VHDL20_DWMO_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:02                3738
swis2-VHDL20_DWMO_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                3212
swis2-VHDL20_DWMO_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2701
swis2-VHDL20_DWMO_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:07                3321
swis2-VHDL20_DWMO_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:01                3079
swis2-VHDL20_DWMO_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                3601
swis2-VHDL20_DWMO_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3015
swis2-VHDL20_DWMP_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                4047
swis2-VHDL20_DWMP_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:02                4051
swis2-VHDL20_DWMP_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:03                3528
swis2-VHDL20_DWMP_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                3103
swis2-VHDL20_DWMP_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:07                3673
swis2-VHDL20_DWMP_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:01                3627
swis2-VHDL20_DWMP_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                4192
swis2-VHDL20_DWMP_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                3556
swis2-VHDL20_DWPG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                2437
swis2-VHDL20_DWPG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:12                2514
swis2-VHDL20_DWPG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                2715
swis2-VHDL20_DWPG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2349
swis2-VHDL20_DWPG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                2296
swis2-VHDL20_DWPG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:11                2401
swis2-VHDL20_DWPG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                2407
swis2-VHDL20_DWPG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                2692
swis2-VHDL20_DWPH_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                2455
swis2-VHDL20_DWPH_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:00:12                2478
swis2-VHDL20_DWPH_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                2739
swis2-VHDL20_DWPH_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:06                2376
swis2-VHDL20_DWPH_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:03                2404
swis2-VHDL20_DWPH_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:00:11                2210
swis2-VHDL20_DWPH_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:06                2366
swis2-VHDL20_DWPH_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                2600
swis2-VHDL20_DWSG_160200-2601160200-dsw--0-ia5     16-Jan-2026 03:45:02                2972
swis2-VHDL20_DWSG_160400-2601160400-dsw--0-ia5     16-Jan-2026 06:15:02                2998
swis2-VHDL20_DWSG_160800-2601160800-dsw--0-ia5     16-Jan-2026 09:45:07                3448
swis2-VHDL20_DWSG_161300-2601161300-dsw--0-ia5     16-Jan-2026 14:45:03                3278
swis2-VHDL20_DWSG_161800-2601161800-dsw--0-ia5     16-Jan-2026 19:45:01                2871
swis2-VHDL20_DWSG_170200-2601170200-dsw--0-ia5     17-Jan-2026 03:45:07                3147
swis2-VHDL20_DWSG_170400-2601170400-dsw--0-ia5     17-Jan-2026 06:15:07                3144
swis2-VHDL20_DWSG_170800-2601170800-dsw--0-ia5     17-Jan-2026 09:45:02                3103
swis2-VHDL20_DWSG_171300-2601171300-dsw--0-ia5     17-Jan-2026 14:45:09                2935
swis2-VHDL20_DWSG_171800-2601171800-dsw--0-ia5     17-Jan-2026 19:45:04                2531
wst04-VHDL20_DWEG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:12              227873
wst04-VHDL20_DWEG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:21              227263
wst04-VHDL20_DWEG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:21              227472
wst04-VHDL20_DWEG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:12              225648
wst04-VHDL20_DWEG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              226581
wst04-VHDL20_DWEG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:21              226677
wst04-VHDL20_DWEG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:22              228734
wst04-VHDL20_DWEG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:12              226789
wst04-VHDL20_DWEH_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:12              228133
wst04-VHDL20_DWEH_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:21              227559
wst04-VHDL20_DWEH_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:21              225868
wst04-VHDL20_DWEH_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:12              225047
wst04-VHDL20_DWEH_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              225393
wst04-VHDL20_DWEH_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:21              225124
wst04-VHDL20_DWEH_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:26              227181
wst04-VHDL20_DWEH_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:12              225895
wst04-VHDL20_DWEI_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:18              318164
wst04-VHDL20_DWEI_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:27              318005
wst04-VHDL20_DWEI_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:25              318045
wst04-VHDL20_DWEI_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:12              317092
wst04-VHDL20_DWEI_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              316579
wst04-VHDL20_DWEI_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:27              316685
wst04-VHDL20_DWEI_170800-2601170800-omedes--0.pdf  17-Jan-2026 10:01:01              318952
wst04-VHDL20_DWEI_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:16              318100
wst04-VHDL20_DWHG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:12              305951
wst04-VHDL20_DWHG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:12              306043
wst04-VHDL20_DWHG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:15              306541
wst04-VHDL20_DWHG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:22              303379
wst04-VHDL20_DWHG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              303661
wst04-VHDL20_DWHG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:11              303788
wst04-VHDL20_DWHG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:22              314549
wst04-VHDL20_DWHG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:16              313204
wst04-VHDL20_DWHH_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:18              291924
wst04-VHDL20_DWHH_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:12              292367
wst04-VHDL20_DWHH_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:15              292975
wst04-VHDL20_DWHH_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:16              291542
wst04-VHDL20_DWHH_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              291746
wst04-VHDL20_DWHH_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:11              291912
wst04-VHDL20_DWHH_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:16              293698
wst04-VHDL20_DWHH_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:22              292938
wst04-VHDL20_DWLG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:26              297700
wst04-VHDL20_DWLG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:41              297406
wst04-VHDL20_DWLG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:31              301847
wst04-VHDL20_DWLG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:22              300713
wst04-VHDL20_DWLG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:22              301412
wst04-VHDL20_DWLG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:41              301319
wst04-VHDL20_DWLG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:26              302296
wst04-VHDL20_DWLG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:46:02              301794
wst04-VHDL20_DWLH_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:20              302046
wst04-VHDL20_DWLH_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:41              301583
wst04-VHDL20_DWLH_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:25              302231
wst04-VHDL20_DWLH_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:22              300152
wst04-VHDL20_DWLH_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:26              301045
wst04-VHDL20_DWLH_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:41              300559
wst04-VHDL20_DWLH_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:26              309983
wst04-VHDL20_DWLH_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:22              309466
wst04-VHDL20_DWLI_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:20              307078
wst04-VHDL20_DWLI_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:41              306915
wst04-VHDL20_DWLI_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:31              308985
wst04-VHDL20_DWLI_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:26              307027
wst04-VHDL20_DWLI_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:22              308009
wst04-VHDL20_DWLI_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:41              307326
wst04-VHDL20_DWLI_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:32              309465
wst04-VHDL20_DWLI_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:22              308978
wst04-VHDL20_DWMG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:18              525230
wst04-VHDL20_DWMG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:17              524882
wst04-VHDL20_DWMG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:17              524608
wst04-VHDL20_DWMG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:16              523657
wst04-VHDL20_DWMG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              524951
wst04-VHDL20_DWMG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:21              524485
wst04-VHDL20_DWMG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:16              525492
wst04-VHDL20_DWMG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:16              523530
wst04-VHDL20_DWMO_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:18              419163
wst04-VHDL20_DWMO_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:17              419394
wst04-VHDL20_DWMO_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:11              417532
wst04-VHDL20_DWMO_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:16              416817
wst04-VHDL20_DWMO_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              417562
wst04-VHDL20_DWMO_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:17              417311
wst04-VHDL20_DWMO_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:12              424742
wst04-VHDL20_DWMO_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:16              422767
wst04-VHDL20_DWMP_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:22              552962
wst04-VHDL20_DWMP_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:17              553926
wst04-VHDL20_DWMP_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:17              546758
wst04-VHDL20_DWMP_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:16              545997
wst04-VHDL20_DWMP_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:22              545741
wst04-VHDL20_DWMP_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:21              546542
wst04-VHDL20_DWMP_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:16              555153
wst04-VHDL20_DWMP_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:16              552893
wst04-VHDL20_DWPG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:26              297024
wst04-VHDL20_DWPG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:32              297371
wst04-VHDL20_DWPG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:31              346133
wst04-VHDL20_DWPG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:26              300607
wst04-VHDL20_DWPG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:26              301195
wst04-VHDL20_DWPG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:31              300844
wst04-VHDL20_DWPG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:26              349573
wst04-VHDL20_DWPG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:46:02              305189
wst04-VHDL20_DWPH_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:20              224279
wst04-VHDL20_DWPH_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:00:32              224511
wst04-VHDL20_DWPH_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:25              267298
wst04-VHDL20_DWPH_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:22              265935
wst04-VHDL20_DWPH_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:22              221451
wst04-VHDL20_DWPH_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:00:31              221292
wst04-VHDL20_DWPH_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:26              266867
wst04-VHDL20_DWPH_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:22              266579
wst04-VHDL20_DWSG_160200-2601160200-omedes--0.pdf  16-Jan-2026 03:45:12              332672
wst04-VHDL20_DWSG_160400-2601160400-omedes--0.pdf  16-Jan-2026 06:15:11              332798
wst04-VHDL20_DWSG_160800-2601160800-omedes--0.pdf  16-Jan-2026 09:45:11              335806
wst04-VHDL20_DWSG_161300-2601161300-omedes--0.pdf  16-Jan-2026 14:45:11              335757
wst04-VHDL20_DWSG_161800-2601161800-omedes--0.pdf  16-Jan-2026 19:45:12              334553
wst04-VHDL20_DWSG_170200-2601170200-omedes--0.pdf  17-Jan-2026 03:45:20              334885
wst04-VHDL20_DWSG_170400-2601170400-omedes--0.pdf  17-Jan-2026 06:15:17              335472
wst04-VHDL20_DWSG_170800-2601170800-omedes--0.pdf  17-Jan-2026 09:45:12              340843
wst04-VHDL20_DWSG_171300-2601171300-omedes--0.pdf  17-Jan-2026 14:45:12              340651
wst04-VHDL20_DWSG_171800-2601171800-omedes--0.pdf  17-Jan-2026 19:45:12              339884