Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Mar-2026 14:06:14 4163
FPDL13_DWMZ_240600 24-Mar-2026 13:40:44 4382
SXDL31_DWAV_221800 22-Mar-2026 17:23:09 6497
SXDL31_DWAV_230800 23-Mar-2026 08:59:30 11247
SXDL31_DWAV_231800 23-Mar-2026 16:38:29 8102
SXDL31_DWAV_240800 24-Mar-2026 09:12:03 14005
SXDL31_DWAV_LATEST 24-Mar-2026 09:12:03 14005
SXDL33_DWAV_230000 23-Mar-2026 11:19:19 8609
SXDL33_DWAV_240000 24-Mar-2026 11:44:30 11706
SXDL33_DWAV_LATEST 24-Mar-2026 11:44:30 11706
ber01-FWDL39_DWMS_231230-2603231230-dsw--0-ia5 23-Mar-2026 12:48:21 1162
ber01-FWDL39_DWMS_241230-2603241230-dsw--0-ia5 24-Mar-2026 12:48:16 1513
ber01-VHDL13_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2449
ber01-VHDL13_DWEH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:17 2777
ber01-VHDL13_DWEH_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:17 2684
ber01-VHDL13_DWEH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:16 3113
ber01-VHDL13_DWEH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:12 3324
ber01-VHDL13_DWEH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:12 3570
ber01-VHDL13_DWEH_240400-2603240400-dsw--0-ia5 24-Mar-2026 05:58:17 3953
ber01-VHDL13_DWEH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:28:17 4046
ber01-VHDL13_DWEH_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:31 3980
ber01-VHDL13_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 3231
ber01-VHDL13_DWHG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3595
ber01-VHDL13_DWHG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3595
ber01-VHDL13_DWHG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 3587
ber01-VHDL13_DWHG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:10 3494
ber01-VHDL13_DWHG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 3761
ber01-VHDL13_DWHG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3628
ber01-VHDL13_DWHG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3957
ber01-VHDL13_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 2620
ber01-VHDL13_DWHH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3138
ber01-VHDL13_DWHH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3138
ber01-VHDL13_DWHH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 3100
ber01-VHDL13_DWHH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:10 2849
ber01-VHDL13_DWHH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 3363
ber01-VHDL13_DWHH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3409
ber01-VHDL13_DWHH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3751
ber01-VHDL13_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1821
ber01-VHDL13_DWLG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2062
ber01-VHDL13_DWLG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2226
ber01-VHDL13_DWLG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2543
ber01-VHDL13_DWLG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2313
ber01-VHDL13_DWLG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3028
ber01-VHDL13_DWLG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:02 3213
ber01-VHDL13_DWLG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3394
ber01-VHDL13_DWLH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1961
ber01-VHDL13_DWLH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2196
ber01-VHDL13_DWLH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2359
ber01-VHDL13_DWLH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2713
ber01-VHDL13_DWLH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2558
ber01-VHDL13_DWLH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3180
ber01-VHDL13_DWLH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:02 3370
ber01-VHDL13_DWLH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3590
ber01-VHDL13_DWLI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1835
ber01-VHDL13_DWLI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2076
ber01-VHDL13_DWLI_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2306
ber01-VHDL13_DWLI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2722
ber01-VHDL13_DWLI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2541
ber01-VHDL13_DWLI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3032
ber01-VHDL13_DWLI_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:02 3151
ber01-VHDL13_DWLI_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3393
ber01-VHDL13_DWMG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2383
ber01-VHDL13_DWMG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2907
ber01-VHDL13_DWMG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 2798
ber01-VHDL13_DWMG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2649
ber01-VHDL13_DWMG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2214
ber01-VHDL13_DWMG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2888
ber01-VHDL13_DWMG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:06 2963
ber01-VHDL13_DWMG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3632
ber01-VHDL13_DWMO_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL13_DWMO_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2755
ber01-VHDL13_DWMO_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 2683
ber01-VHDL13_DWMO_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2458
ber01-VHDL13_DWMO_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2458
ber01-VHDL13_DWMO_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2663
ber01-VHDL13_DWMO_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:06 2709
ber01-VHDL13_DWMO_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3284
ber01-VHDL13_DWMP_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2516
ber01-VHDL13_DWMP_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 3109
ber01-VHDL13_DWMP_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:01 3001
ber01-VHDL13_DWMP_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2611
ber01-VHDL13_DWMP_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2191
ber01-VHDL13_DWMP_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:07 2857
ber01-VHDL13_DWMP_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:06 2989
ber01-VHDL13_DWMP_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 3687
ber01-VHDL13_DWOG_221700-2603221700-dsw--0-ia5 22-Mar-2026 19:00:01 3180
ber01-VHDL13_DWOG_230300-2603230300-dsw--0-ia5 23-Mar-2026 04:00:02 3882
ber01-VHDL13_DWOG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 3827
ber01-VHDL13_DWOG_231700-2603231700-dsw--0-ia5 23-Mar-2026 19:00:06 4444
ber01-VHDL13_DWOG_240300-2603240300-dsw--0-ia5 24-Mar-2026 04:00:06 5192
ber01-VHDL13_DWOG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 4913
ber01-VHDL13_DWOH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2598
ber01-VHDL13_DWOH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:11 2998
ber01-VHDL13_DWOH_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:11 2689
ber01-VHDL13_DWOH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:16 2882
ber01-VHDL13_DWOH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:16 3100
ber01-VHDL13_DWOH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:12 3308
ber01-VHDL13_DWOH_240400-2603240400-dsw--0-ia5 24-Mar-2026 05:58:13 3446
ber01-VHDL13_DWOH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:28:11 3502
ber01-VHDL13_DWOH_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:21 3465
ber01-VHDL13_DWOI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:12 2297
ber01-VHDL13_DWOI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:28:11 2785
ber01-VHDL13_DWOI_230400-2603230400-dsw--0-ia5 23-Mar-2026 05:58:17 2707
ber01-VHDL13_DWOI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:28:12 2877
ber01-VHDL13_DWOI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:28:12 3091
ber01-VHDL13_DWOI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:28:16 3312
ber01-VHDL13_DWOI_240400-2603240400-dsw--0-ia5 24-Mar-2026 05:58:13 3445
ber01-VHDL13_DWOI_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:28:17 3504
ber01-VHDL13_DWOI_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:21 3464
ber01-VHDL13_DWON_221731-2603221731-dsw--0-ia5 22-Mar-2026 17:32:03 2745
ber01-VHDL13_DWON_221752-2603221752-dsw--0-ia5 22-Mar-2026 17:52:23 3119
ber01-VHDL13_DWON_221937-2603221937-dsw--0-ia5 22-Mar-2026 19:37:28 3120
ber01-VHDL13_DWON_222228-2603222228-dsw--0-ia5 22-Mar-2026 22:28:57 3118
ber01-VHDL13_DWON_230000-2603230000-dsw--0-ia5 23-Mar-2026 00:00:22 3800
ber01-VHDL13_DWON_230137-2603230137-dsw--0-ia5 23-Mar-2026 01:37:26 3771
ber01-VHDL13_DWON_230340-2603230340-dsw--0-ia5 23-Mar-2026 03:41:03 3790
ber01-VHDL13_DWON_230628-2603230628-dsw--0-ia5 23-Mar-2026 06:28:47 3388
ber01-VHDL13_DWON_230658-2603230658-dsw--0-ia5 23-Mar-2026 06:58:27 3572
ber01-VHDL13_DWON_230733-2603230733-dsw--0-ia5 23-Mar-2026 07:33:27 3584
ber01-VHDL13_DWON_230842-2603230842-dsw--0-ia5 23-Mar-2026 08:42:47 3584
ber01-VHDL13_DWON_231045-2603231045-dsw--0-ia5 23-Mar-2026 10:45:57 3762
ber01-VHDL13_DWON_231516-2603231516-dsw--0-ia5 23-Mar-2026 15:16:51 3870
ber01-VHDL13_DWON_231522-2603231522-dsw--0-ia5 23-Mar-2026 15:23:01 3870
ber01-VHDL13_DWON_231525-2603231525-dsw--0-ia5 23-Mar-2026 15:25:42 3870
ber01-VHDL13_DWON_231753-2603231753-dsw--0-ia5 23-Mar-2026 17:53:21 3465
ber01-VHDL13_DWON_231846-2603231846-dsw--0-ia5 23-Mar-2026 18:46:08 3465
ber01-VHDL13_DWON_231942-2603231942-dsw--0-ia5 23-Mar-2026 19:42:46 3791
ber01-VHDL13_DWON_232230-2603232230-dsw--0-ia5 23-Mar-2026 22:30:21 3785
ber01-VHDL13_DWON_240003-2603240003-dsw--0-ia5 24-Mar-2026 00:03:07 4493
ber01-VHDL13_DWON_240124-2603240124-dsw--0-ia5 24-Mar-2026 01:24:17 4459
ber01-VHDL13_DWON_240347-2603240347-dsw--0-ia5 24-Mar-2026 03:47:47 4459
ber01-VHDL13_DWON_240627-2603240627-dsw--0-ia5 24-Mar-2026 06:28:02 4923
ber01-VHDL13_DWON_240728-2603240728-dsw--0-ia5 24-Mar-2026 07:28:06 4645
ber01-VHDL13_DWON_240911-2603240911-dsw--0-ia5 24-Mar-2026 09:11:57 4718
ber01-VHDL13_DWON_241100-2603241100-dsw--0-ia5 24-Mar-2026 11:00:47 4718
ber01-VHDL13_DWPG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1745
ber01-VHDL13_DWPG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 1947
ber01-VHDL13_DWPG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 1911
ber01-VHDL13_DWPG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 1914
ber01-VHDL13_DWPG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 1933
ber01-VHDL13_DWPG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 2259
ber01-VHDL13_DWPG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:02 2289
ber01-VHDL13_DWPG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 2514
ber01-VHDL13_DWPH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1868
ber01-VHDL13_DWPH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:03 2142
ber01-VHDL13_DWPH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:07 2002
ber01-VHDL13_DWPH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:02 2009
ber01-VHDL13_DWPH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2171
ber01-VHDL13_DWPH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 2869
ber01-VHDL13_DWPH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:02 2986
ber01-VHDL13_DWPH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 2950
ber01-VHDL13_DWSG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL13_DWSG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:30:09 2865
ber01-VHDL13_DWSG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2871
ber01-VHDL13_DWSG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:30:11 2920
ber01-VHDL13_DWSG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:30:05 2589
ber01-VHDL13_DWSG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:30:02 3061
ber01-VHDL13_DWSG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3054
ber01-VHDL13_DWSG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:30:06 4051
ber01-VHDL17_DWOG_231200-2603231200-dsw--0-ia5 23-Mar-2026 12:43:57 3399
ber01-VHDL17_DWOG_241200-2603241200-dsw--0-ia5 24-Mar-2026 12:21:41 4007
swis2-VHDL20_DWEG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3022
swis2-VHDL20_DWEG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3375
swis2-VHDL20_DWEG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3008
swis2-VHDL20_DWEG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3458
swis2-VHDL20_DWEG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3526
swis2-VHDL20_DWEG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3687
swis2-VHDL20_DWEG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:06 3764
swis2-VHDL20_DWEG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4066
swis2-VHDL20_DWEG_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:21 4029
swis2-VHDL20_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2900
swis2-VHDL20_DWEH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3199
swis2-VHDL20_DWEH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3015
swis2-VHDL20_DWEH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3714
swis2-VHDL20_DWEH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3779
swis2-VHDL20_DWEH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3994
swis2-VHDL20_DWEH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:06 4283
swis2-VHDL20_DWEH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4637
swis2-VHDL20_DWEH_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:21 4571
swis2-VHDL20_DWEI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2746
swis2-VHDL20_DWEI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3179
swis2-VHDL20_DWEI_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3057
swis2-VHDL20_DWEI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3503
swis2-VHDL20_DWEI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3542
swis2-VHDL20_DWEI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3706
swis2-VHDL20_DWEI_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:06 3797
swis2-VHDL20_DWEI_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4118
swis2-VHDL20_DWEI_240800_COR-2603240800-dsw--0-ia5 24-Mar-2026 13:36:21 4078
swis2-VHDL20_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3414
swis2-VHDL20_DWHG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3781
swis2-VHDL20_DWHG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3778
swis2-VHDL20_DWHG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 4123
swis2-VHDL20_DWHG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 3677
swis2-VHDL20_DWHG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3947
swis2-VHDL20_DWHG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3811
swis2-VHDL20_DWHG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4619
swis2-VHDL20_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2806
swis2-VHDL20_DWHH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 3324
swis2-VHDL20_DWHH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 3324
swis2-VHDL20_DWHH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3643
swis2-VHDL20_DWHH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 3035
swis2-VHDL20_DWHH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3549
swis2-VHDL20_DWHH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3595
swis2-VHDL20_DWHH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4358
swis2-VHDL20_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2162
swis2-VHDL20_DWLG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2403
swis2-VHDL20_DWLG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2569
swis2-VHDL20_DWLG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 3033
swis2-VHDL20_DWLG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 2656
swis2-VHDL20_DWLG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3371
swis2-VHDL20_DWLG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3556
swis2-VHDL20_DWLG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 3981
swis2-VHDL20_DWLH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2309
swis2-VHDL20_DWLH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2544
swis2-VHDL20_DWLH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2709
swis2-VHDL20_DWLH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 3214
swis2-VHDL20_DWLH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 2908
swis2-VHDL20_DWLH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3530
swis2-VHDL20_DWLH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3720
swis2-VHDL20_DWLH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 4180
swis2-VHDL20_DWLI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2178
swis2-VHDL20_DWLI_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2419
swis2-VHDL20_DWLI_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2651
swis2-VHDL20_DWLI_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 3213
swis2-VHDL20_DWLI_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 2886
swis2-VHDL20_DWLI_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3377
swis2-VHDL20_DWLI_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3496
swis2-VHDL20_DWLI_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 3982
swis2-VHDL20_DWMG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2773
swis2-VHDL20_DWMG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:04 3297
swis2-VHDL20_DWMG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3190
swis2-VHDL20_DWMG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:06 3233
swis2-VHDL20_DWMG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 2606
swis2-VHDL20_DWMG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3269
swis2-VHDL20_DWMG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:01 3385
swis2-VHDL20_DWMG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 4290
swis2-VHDL20_DWMO_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2702
swis2-VHDL20_DWMO_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:04 3151
swis2-VHDL20_DWMO_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3079
swis2-VHDL20_DWMO_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:06 3015
swis2-VHDL20_DWMO_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 2531
swis2-VHDL20_DWMO_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3061
swis2-VHDL20_DWMO_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:01 3085
swis2-VHDL20_DWMO_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 3912
swis2-VHDL20_DWMP_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2895
swis2-VHDL20_DWMP_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:04 3502
swis2-VHDL20_DWMP_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3393
swis2-VHDL20_DWMP_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:06 3201
swis2-VHDL20_DWMP_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:06 2607
swis2-VHDL20_DWMP_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:06 3252
swis2-VHDL20_DWMP_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:01 3411
swis2-VHDL20_DWMP_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 4396
swis2-VHDL20_DWPG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2204
swis2-VHDL20_DWPG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2275
swis2-VHDL20_DWPG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2238
swis2-VHDL20_DWPG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 2379
swis2-VHDL20_DWPG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 2398
swis2-VHDL20_DWPG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 2589
swis2-VHDL20_DWPG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 2620
swis2-VHDL20_DWPG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 3078
swis2-VHDL20_DWPH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2327
swis2-VHDL20_DWPH_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:06 2469
swis2-VHDL20_DWPH_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:00:11 2331
swis2-VHDL20_DWPH_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:00 2472
swis2-VHDL20_DWPH_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 2634
swis2-VHDL20_DWPH_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:01 3198
swis2-VHDL20_DWPH_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:00:12 3317
swis2-VHDL20_DWPH_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:02 3533
swis2-VHDL20_DWSG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2662
swis2-VHDL20_DWSG_230200-2603230200-dsw--0-ia5 23-Mar-2026 03:45:04 3211
swis2-VHDL20_DWSG_230400-2603230400-dsw--0-ia5 23-Mar-2026 06:15:06 3225
swis2-VHDL20_DWSG_230800-2603230800-dsw--0-ia5 23-Mar-2026 09:45:04 3420
swis2-VHDL20_DWSG_231300-2603231300-dsw--0-ia5 23-Mar-2026 14:45:01 3303
swis2-VHDL20_DWSG_231800-2603231800-dsw--0-ia5 23-Mar-2026 19:45:02 3000
swis2-VHDL20_DWSG_240200-2603240200-dsw--0-ia5 24-Mar-2026 03:45:03 3462
swis2-VHDL20_DWSG_240400-2603240400-dsw--0-ia5 24-Mar-2026 06:15:01 3409
swis2-VHDL20_DWSG_240800-2603240800-dsw--0-ia5 24-Mar-2026 09:45:06 4704
swis2-VHDL20_DWSG_241300-2603241300-dsw--0-ia5 24-Mar-2026 14:45:06 4658
wst04-VHDL20_DWEG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 237684
wst04-VHDL20_DWEG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:16 238978
wst04-VHDL20_DWEG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:12 237156
wst04-VHDL20_DWEG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:12 243318
wst04-VHDL20_DWEG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:12 242939
wst04-VHDL20_DWEG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:16 243665
wst04-VHDL20_DWEG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:16 243339
wst04-VHDL20_DWEG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:16 246719
wst04-VHDL20_DWEG_240800_COR-2603240800-omedes-..> 24-Mar-2026 13:36:26 246715
wst04-VHDL20_DWEH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 235794
wst04-VHDL20_DWEH_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:16 237189
wst04-VHDL20_DWEH_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:16 236479
wst04-VHDL20_DWEH_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:12 238725
wst04-VHDL20_DWEH_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:12 239014
wst04-VHDL20_DWEH_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:12 239631
wst04-VHDL20_DWEH_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:16 239481
wst04-VHDL20_DWEH_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:12 245100
wst04-VHDL20_DWEH_240800_COR-2603240800-omedes-..> 24-Mar-2026 13:36:26 245047
wst04-VHDL20_DWEI_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 337886
wst04-VHDL20_DWEI_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:22 337824
wst04-VHDL20_DWEI_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:22 337966
wst04-VHDL20_DWEI_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:18 345164
wst04-VHDL20_DWEI_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:12 345215
wst04-VHDL20_DWEI_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:16 345415
wst04-VHDL20_DWEI_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:16 345591
wst04-VHDL20_DWEI_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:22 346745
wst04-VHDL20_DWEI_240800_COR-2603240800-omedes-..> 24-Mar-2026 13:36:26 346721
wst04-VHDL20_DWHG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 345011
wst04-VHDL20_DWHG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:12 345449
wst04-VHDL20_DWHG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:11 345405
wst04-VHDL20_DWHG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:22 345431
wst04-VHDL20_DWHG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:22 344213
wst04-VHDL20_DWHG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:22 344739
wst04-VHDL20_DWHG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:12 344564
wst04-VHDL20_DWHG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:26 352237
wst04-VHDL20_DWHH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 332748
wst04-VHDL20_DWHH_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:16 332869
wst04-VHDL20_DWHH_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:11 332909
wst04-VHDL20_DWHH_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:22 331429
wst04-VHDL20_DWHH_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:22 330050
wst04-VHDL20_DWHH_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:16 330276
wst04-VHDL20_DWHH_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:12 330286
wst04-VHDL20_DWHH_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:26 336050
wst04-VHDL20_DWLG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 324079
wst04-VHDL20_DWLG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:22 324156
wst04-VHDL20_DWLG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:41 324497
wst04-VHDL20_DWLG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:32 328216
wst04-VHDL20_DWLG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:20 326654
wst04-VHDL20_DWLG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:22 328971
wst04-VHDL20_DWLG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:40 329380
wst04-VHDL20_DWLG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:32 328871
wst04-VHDL20_DWLH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:26 332706
wst04-VHDL20_DWLH_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:26 332727
wst04-VHDL20_DWLH_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:41 332951
wst04-VHDL20_DWLH_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:32 334987
wst04-VHDL20_DWLH_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:26 333761
wst04-VHDL20_DWLH_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:22 335080
wst04-VHDL20_DWLH_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:40 335316
wst04-VHDL20_DWLH_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:30 337167
wst04-VHDL20_DWLI_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 332925
wst04-VHDL20_DWLI_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:22 333321
wst04-VHDL20_DWLI_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:41 334021
wst04-VHDL20_DWLI_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:26 328665
wst04-VHDL20_DWLI_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:20 327990
wst04-VHDL20_DWLI_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:26 329207
wst04-VHDL20_DWLI_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:40 329502
wst04-VHDL20_DWLI_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:30 333917
wst04-VHDL20_DWMG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 538839
wst04-VHDL20_DWMG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:16 539339
wst04-VHDL20_DWMG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:22 539193
wst04-VHDL20_DWMG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:26 529528
wst04-VHDL20_DWMG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:16 527929
wst04-VHDL20_DWMG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:16 528582
wst04-VHDL20_DWMG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:26 529669
wst04-VHDL20_DWMG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:16 532946
wst04-VHDL20_DWMO_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 448400
wst04-VHDL20_DWMO_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:12 449081
wst04-VHDL20_DWMO_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:22 449458
wst04-VHDL20_DWMO_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:22 431579
wst04-VHDL20_DWMO_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:16 428670
wst04-VHDL20_DWMO_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:12 430068
wst04-VHDL20_DWMO_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:22 431443
wst04-VHDL20_DWMO_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:12 434889
wst04-VHDL20_DWMP_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 534219
wst04-VHDL20_DWMP_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:16 533626
wst04-VHDL20_DWMP_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:26 534716
wst04-VHDL20_DWMP_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:26 537147
wst04-VHDL20_DWMP_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:16 536323
wst04-VHDL20_DWMP_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:16 536204
wst04-VHDL20_DWMP_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:26 537615
wst04-VHDL20_DWMP_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:16 536654
wst04-VHDL20_DWPG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:26 340846
wst04-VHDL20_DWPG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:26 340498
wst04-VHDL20_DWPG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:31 340435
wst04-VHDL20_DWPG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:32 386235
wst04-VHDL20_DWPG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:26 341604
wst04-VHDL20_DWPG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:26 342118
wst04-VHDL20_DWPG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:32 342020
wst04-VHDL20_DWPG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:30 397159
wst04-VHDL20_DWPH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 282951
wst04-VHDL20_DWPH_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:22 238519
wst04-VHDL20_DWPH_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:00:31 238336
wst04-VHDL20_DWPH_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:26 286253
wst04-VHDL20_DWPH_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:20 286459
wst04-VHDL20_DWPH_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:22 242842
wst04-VHDL20_DWPH_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:00:32 242367
wst04-VHDL20_DWPH_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:30 292619
wst04-VHDL20_DWSG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 340444
wst04-VHDL20_DWSG_230200-2603230200-omedes--0.pdf 23-Mar-2026 03:45:12 341086
wst04-VHDL20_DWSG_230400-2603230400-omedes--0.pdf 23-Mar-2026 06:15:16 341781
wst04-VHDL20_DWSG_230800-2603230800-omedes--0.pdf 23-Mar-2026 09:45:12 332430
wst04-VHDL20_DWSG_231300-2603231300-omedes--0.pdf 23-Mar-2026 14:45:12 332955
wst04-VHDL20_DWSG_231800-2603231800-omedes--0.pdf 23-Mar-2026 19:45:12 333016
wst04-VHDL20_DWSG_240200-2603240200-omedes--0.pdf 24-Mar-2026 03:45:12 333251
wst04-VHDL20_DWSG_240400-2603240400-omedes--0.pdf 24-Mar-2026 06:15:12 333341
wst04-VHDL20_DWSG_240800-2603240800-omedes--0.pdf 24-Mar-2026 09:45:12 342008
wst04-VHDL20_DWSG_241300-2603241300-omedes--0.pdf 24-Mar-2026 14:45:13 342240