Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_100600 10-Sep-2026 13:19:35 4659
FPDL13_DWMZ_110600 11-Sep-2026 12:58:09 5474
SXDL31_DWAV_100800 10-Sep-2026 07:09:15 5398
SXDL31_DWAV_101800 10-Sep-2026 15:35:04 6717
SXDL31_DWAV_110800 11-Sep-2026 07:25:35 6841
SXDL31_DWAV_111800 11-Sep-2026 14:56:45 4829
SXDL31_DWAV_LATEST 11-Sep-2026 14:56:45 4829
SXDL33_DWAV_100000 10-Sep-2026 09:57:36 6669
SXDL33_DWAV_110000 11-Sep-2026 09:40:25 10359
SXDL33_DWAV_LATEST 11-Sep-2026 09:40:25 10359
ber01-FWDL39_DWMS_101200-2609101200-dsw--0-ia5 10-Sep-2026 10:59:54 1999
ber01-FWDL39_DWMS_111200-2609111200-dsw--0-ia5 11-Sep-2026 10:14:18 2409
ber01-VHDL13_DWEG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2725
ber01-VHDL13_DWEG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2889
ber01-VHDL13_DWEH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2527
ber01-VHDL13_DWEH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2984
ber01-VHDL13_DWEI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:28:19 2719
ber01-VHDL13_DWEI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2818
ber01-VHDL13_DWHG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 2838
ber01-VHDL13_DWHG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2861
ber01-VHDL13_DWHH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 2806
ber01-VHDL13_DWHH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2943
ber01-VHDL13_DWLG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2151
ber01-VHDL13_DWLG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2108
ber01-VHDL13_DWLH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2238
ber01-VHDL13_DWLH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2187
ber01-VHDL13_DWLI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2293
ber01-VHDL13_DWLI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2026
ber01-VHDL13_DWMO_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2459
ber01-VHDL13_DWMO_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2595
ber01-VHDL13_DWMP_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2778
ber01-VHDL13_DWMP_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2715
ber01-VHDL13_DWOG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:16 3403
ber01-VHDL13_DWOG_100800_COR-2609100800-dsw--0-ia5 10-Sep-2026 08:55:47 3303
ber01-VHDL13_DWOG_101700-2609101700-dsw--0-ia5 10-Sep-2026 18:00:04 3067
ber01-VHDL13_DWOG_110300-2609110300-dsw--0-ia5 11-Sep-2026 03:00:11 3142
ber01-VHDL13_DWOG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 3293
ber01-VHDL13_DWOG_111700-2609111700-dsw--0-ia5 11-Sep-2026 18:00:06 2955
ber01-VHDL13_DWOG_111700_COR-2609111700-dsw--0-ia5 11-Sep-2026 18:48:23 2851
ber01-VHDL13_DWOG_120300-2609120300-dsw--0-ia5 12-Sep-2026 03:00:54 3101
ber01-VHDL13_DWON_100854-2609100854-dsw--0-ia5 10-Sep-2026 08:55:12 3671
ber01-VHDL13_DWON_101433-2609101433-dsw--0-ia5 10-Sep-2026 14:33:43 3472
ber01-VHDL13_DWON_101632-2609101632-dsw--0-ia5 10-Sep-2026 16:32:51 3169
ber01-VHDL13_DWON_101633-2609101633-dsw--0-ia5 10-Sep-2026 16:33:20 3169
ber01-VHDL13_DWON_102151-2609102151-dsw--0-ia5 10-Sep-2026 21:51:11 3169
ber01-VHDL13_DWON_102309-2609102309-dsw--0-ia5 10-Sep-2026 23:09:34 3206
ber01-VHDL13_DWON_110055-2609110055-dsw--0-ia5 11-Sep-2026 00:55:43 3206
ber01-VHDL13_DWON_110121-2609110121-dsw--0-ia5 11-Sep-2026 01:21:49 3206
ber01-VHDL13_DWON_110529-2609110529-dsw--0-ia5 11-Sep-2026 05:29:44 3662
ber01-VHDL13_DWON_110605-2609110605-dsw--0-ia5 11-Sep-2026 06:05:09 3699
ber01-VHDL13_DWON_110813-2609110813-dsw--0-ia5 11-Sep-2026 08:13:08 3601
ber01-VHDL13_DWON_111443-2609111443-dsw--0-ia5 11-Sep-2026 14:43:40 3524
ber01-VHDL13_DWON_111607-2609111607-dsw--0-ia5 11-Sep-2026 16:08:05 2959
ber01-VHDL13_DWON_111801-2609111801-dsw--0-ia5 11-Sep-2026 18:02:05 2959
ber01-VHDL13_DWON_111848-2609111848-dsw--0-ia5 11-Sep-2026 18:48:19 3017
ber01-VHDL13_DWON_120008-2609120008-dsw--0-ia5 12-Sep-2026 00:08:38 3037
ber01-VHDL13_DWON_120254-2609120254-dsw--0-ia5 12-Sep-2026 02:55:23 3037
ber01-VHDL13_DWON_120528-2609120528-dsw--0-ia5 12-Sep-2026 05:28:14 3533
ber01-VHDL13_DWON_120558-2609120558-dsw--0-ia5 12-Sep-2026 05:58:44 3555
ber01-VHDL13_DWPG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2214
ber01-VHDL13_DWPG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2159
ber01-VHDL13_DWPH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2380
ber01-VHDL13_DWPH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2152
ber01-VHDL13_DWSG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 2454
ber01-VHDL13_DWSG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2489
ber01-VHDL17_DWOG_101200-2609101200-dsw--0-ia5 10-Sep-2026 11:07:30 2977
ber01-VHDL17_DWOG_111200-2609111200-dsw--0-ia5 11-Sep-2026 10:48:59 3107
swis2-VHDL20_DWEG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1117
swis2-VHDL20_DWEG_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 1343
swis2-VHDL20_DWEG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 1041
swis2-VHDL20_DWEG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:19 1031
swis2-VHDL20_DWEG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1115
swis2-VHDL20_DWEG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1587
swis2-VHDL20_DWEG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1266
swis2-VHDL20_DWEG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1269
swis2-VHDL20_DWEH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 939
swis2-VHDL20_DWEH_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 1299
swis2-VHDL20_DWEH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 908
swis2-VHDL20_DWEH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:23 905
swis2-VHDL20_DWEH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1205
swis2-VHDL20_DWEH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1686
swis2-VHDL20_DWEH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1297
swis2-VHDL20_DWEH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1278
swis2-VHDL20_DWEI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1126
swis2-VHDL20_DWEI_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 1197
swis2-VHDL20_DWEI_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 895
swis2-VHDL20_DWEI_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:23 892
swis2-VHDL20_DWEI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1121
swis2-VHDL20_DWEI_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1616
swis2-VHDL20_DWEI_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1316
swis2-VHDL20_DWEI_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1305
swis2-VHDL20_DWHG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:45:25 1145
swis2-VHDL20_DWHG_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:45:22 1139
swis2-VHDL20_DWHG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:46:34 984
swis2-VHDL20_DWHG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 981
swis2-VHDL20_DWHG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:45:11 1142
swis2-VHDL20_DWHG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:45:15 1717
swis2-VHDL20_DWHG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:45:24 1456
swis2-VHDL20_DWHG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 1488
swis2-VHDL20_DWHH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:45:25 1098
swis2-VHDL20_DWHH_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:45:22 1089
swis2-VHDL20_DWHH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:46:34 1037
swis2-VHDL20_DWHH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 1037
swis2-VHDL20_DWHH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:45:11 1267
swis2-VHDL20_DWHH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:45:15 1745
swis2-VHDL20_DWHH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:45:24 1387
swis2-VHDL20_DWHH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 1312
swis2-VHDL20_DWLG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1000
swis2-VHDL20_DWLG_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:31:19 979
swis2-VHDL20_DWLG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 837
swis2-VHDL20_DWLG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 836
swis2-VHDL20_DWLG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 944
swis2-VHDL20_DWLG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 892
swis2-VHDL20_DWLG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 842
swis2-VHDL20_DWLG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 854
swis2-VHDL20_DWLH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1135
swis2-VHDL20_DWLH_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:31:19 984
swis2-VHDL20_DWLH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 843
swis2-VHDL20_DWLH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 842
swis2-VHDL20_DWLH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 1102
swis2-VHDL20_DWLH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1140
swis2-VHDL20_DWLH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 872
swis2-VHDL20_DWLH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 941
swis2-VHDL20_DWLI_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1065
swis2-VHDL20_DWLI_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:31:19 979
swis2-VHDL20_DWLI_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 839
swis2-VHDL20_DWLI_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 838
swis2-VHDL20_DWLI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 945
swis2-VHDL20_DWLI_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 975
swis2-VHDL20_DWLI_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 888
swis2-VHDL20_DWLI_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 856
swis2-VHDL20_DWMO_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 968
swis2-VHDL20_DWMO_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 999
swis2-VHDL20_DWMO_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 852
swis2-VHDL20_DWMO_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:09 857
swis2-VHDL20_DWMO_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1139
swis2-VHDL20_DWMO_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 1129
swis2-VHDL20_DWMO_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 929
swis2-VHDL20_DWMO_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:03 1052
swis2-VHDL20_DWMP_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 1057
swis2-VHDL20_DWMP_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 1173
swis2-VHDL20_DWMP_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 978
swis2-VHDL20_DWMP_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:09 925
swis2-VHDL20_DWMP_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1246
swis2-VHDL20_DWMP_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 1103
swis2-VHDL20_DWMP_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 880
swis2-VHDL20_DWMP_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:03 1089
swis2-VHDL20_DWPG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1152
swis2-VHDL20_DWPG_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:31:19 997
swis2-VHDL20_DWPG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 854
swis2-VHDL20_DWPG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 853
swis2-VHDL20_DWPG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 1014
swis2-VHDL20_DWPG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1036
swis2-VHDL20_DWPG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 860
swis2-VHDL20_DWPG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 872
swis2-VHDL20_DWPH_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:25 1128
swis2-VHDL20_DWPH_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:31:19 999
swis2-VHDL20_DWPH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 856
swis2-VHDL20_DWPH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 855
swis2-VHDL20_DWPH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 999
swis2-VHDL20_DWPH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1040
swis2-VHDL20_DWPH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 864
swis2-VHDL20_DWPH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 874
swis2-VHDL20_DWSG_100800-2609100800-dsw--0-ia5 10-Sep-2026 08:30:03 942
swis2-VHDL20_DWSG_101800-2609101800-dsw--0-ia5 10-Sep-2026 18:30:12 1085
swis2-VHDL20_DWSG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:05 927
swis2-VHDL20_DWSG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 910
swis2-VHDL20_DWSG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 998
swis2-VHDL20_DWSG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 972
swis2-VHDL20_DWSG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 867
swis2-VHDL20_DWSG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 889
wst04-VHDL20_DWEG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:16 241509
wst04-VHDL20_DWEG_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:14 245640
wst04-VHDL20_DWEG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 244507
wst04-VHDL20_DWEG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 244105
wst04-VHDL20_DWEG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:15 245049
wst04-VHDL20_DWEG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:13 248257
wst04-VHDL20_DWEG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 247377
wst04-VHDL20_DWEG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 247256
wst04-VHDL20_DWEH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 240937
wst04-VHDL20_DWEH_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:14 241583
wst04-VHDL20_DWEH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 240698
wst04-VHDL20_DWEH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 240526
wst04-VHDL20_DWEH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:15 241668
wst04-VHDL20_DWEH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:13 239407
wst04-VHDL20_DWEH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 238707
wst04-VHDL20_DWEH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 238776
wst04-VHDL20_DWEI_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:16 345182
wst04-VHDL20_DWEI_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:26 349588
wst04-VHDL20_DWEI_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:26 349052
wst04-VHDL20_DWEI_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 348564
wst04-VHDL20_DWEI_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 349156
wst04-VHDL20_DWEI_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 354516
wst04-VHDL20_DWEI_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:19 353511
wst04-VHDL20_DWEI_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 353338
wst04-VHDL20_DWHG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:45:25 342905
wst04-VHDL20_DWHG_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:45:22 345199
wst04-VHDL20_DWHG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:46:34 344492
wst04-VHDL20_DWHG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 344287
wst04-VHDL20_DWHG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:45:31 345047
wst04-VHDL20_DWHG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:45:23 343604
wst04-VHDL20_DWHG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:46:39 342193
wst04-VHDL20_DWHG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:24 342041
wst04-VHDL20_DWHH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:45:25 332056
wst04-VHDL20_DWHH_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:45:22 332445
wst04-VHDL20_DWHH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:46:34 332509
wst04-VHDL20_DWHH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 231777
wst04-VHDL20_DWHH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:45:31 333075
wst04-VHDL20_DWHH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:45:23 334808
wst04-VHDL20_DWHH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:46:39 333714
wst04-VHDL20_DWHH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 231742
wst04-VHDL20_DWLG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 335486
wst04-VHDL20_DWLG_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:31:34 334503
wst04-VHDL20_DWLG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 333832
wst04-VHDL20_DWLG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 333448
wst04-VHDL20_DWLG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 333504
wst04-VHDL20_DWLG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:45 337622
wst04-VHDL20_DWLG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:37 337543
wst04-VHDL20_DWLG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 337151
wst04-VHDL20_DWLH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:52 339108
wst04-VHDL20_DWLH_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:31:34 341642
wst04-VHDL20_DWLH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 340952
wst04-VHDL20_DWLH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 340589
wst04-VHDL20_DWLH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 341621
wst04-VHDL20_DWLH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 334072
wst04-VHDL20_DWLH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 333275
wst04-VHDL20_DWLH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 332951
wst04-VHDL20_DWLI_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 380749
wst04-VHDL20_DWLI_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:31:34 343394
wst04-VHDL20_DWLI_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 342739
wst04-VHDL20_DWLI_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 342339
wst04-VHDL20_DWLI_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:54 387007
wst04-VHDL20_DWLI_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 339212
wst04-VHDL20_DWLI_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 339132
wst04-VHDL20_DWLI_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 338514
wst04-VHDL20_DWMO_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 457982
wst04-VHDL20_DWMO_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:26 354219
wst04-VHDL20_DWMO_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 458627
wst04-VHDL20_DWMO_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 459242
wst04-VHDL20_DWMO_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 459254
wst04-VHDL20_DWMO_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 353956
wst04-VHDL20_DWMO_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 460586
wst04-VHDL20_DWMO_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 460558
wst04-VHDL20_DWMP_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 469176
wst04-VHDL20_DWMP_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:26 461337
wst04-VHDL20_DWMP_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:26 561490
wst04-VHDL20_DWMP_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 562098
wst04-VHDL20_DWMP_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 461511
wst04-VHDL20_DWMP_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 470291
wst04-VHDL20_DWMP_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:19 575498
wst04-VHDL20_DWMP_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 577321
wst04-VHDL20_DWPG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 384744
wst04-VHDL20_DWPG_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:31:34 348294
wst04-VHDL20_DWPG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 242635
wst04-VHDL20_DWPG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:33 347291
wst04-VHDL20_DWPG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 392694
wst04-VHDL20_DWPG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 342295
wst04-VHDL20_DWPG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 239209
wst04-VHDL20_DWPG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:34 341027
wst04-VHDL20_DWPH_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:45 241534
wst04-VHDL20_DWPH_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:31:34 240063
wst04-VHDL20_DWPH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 239361
wst04-VHDL20_DWPH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:33 239022
wst04-VHDL20_DWPH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 239825
wst04-VHDL20_DWPH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 238723
wst04-VHDL20_DWPH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 237822
wst04-VHDL20_DWPH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:34 237450
wst04-VHDL20_DWSG_100800-2609100800-omedes--0.pdf 10-Sep-2026 08:30:17 348119
wst04-VHDL20_DWSG_101800-2609101800-omedes--0.pdf 10-Sep-2026 18:30:26 351415
wst04-VHDL20_DWSG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 351528
wst04-VHDL20_DWSG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 350827
wst04-VHDL20_DWSG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 350852
wst04-VHDL20_DWSG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 351901
wst04-VHDL20_DWSG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 351027
wst04-VHDL20_DWSG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 351006