Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Mar-2026 12:48:40 3509
FPDL13_DWMZ_220600 22-Mar-2026 14:39:20 3825
SXDL31_DWAV_210800 21-Mar-2026 09:43:19 5972
SXDL31_DWAV_211800 21-Mar-2026 17:44:03 6254
SXDL31_DWAV_220800 22-Mar-2026 08:33:47 10590
SXDL31_DWAV_221800 22-Mar-2026 17:23:09 6497
SXDL31_DWAV_LATEST 22-Mar-2026 17:23:09 6497
SXDL33_DWAV_210000 21-Mar-2026 10:30:46 11157
SXDL33_DWAV_220000 22-Mar-2026 11:28:43 13778
SXDL33_DWAV_LATEST 22-Mar-2026 11:28:43 13778
ber01-FWDL39_DWMS_211230-2603211230-dsw--0-ia5 21-Mar-2026 12:10:22 1565
ber01-FWDL39_DWMS_221230-2603221230-dsw--0-ia5 22-Mar-2026 11:48:01 1093
ber01-VHDL13_DWEH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:11 2686
ber01-VHDL13_DWEH_210400-2603210400-dsw--0-ia5 21-Mar-2026 05:58:16 2636
ber01-VHDL13_DWEH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:28:17 2337
ber01-VHDL13_DWEH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:28:12 2204
ber01-VHDL13_DWEH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:28:13 2489
ber01-VHDL13_DWEH_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:13 2438
ber01-VHDL13_DWEH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:16 2360
ber01-VHDL13_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2449
ber01-VHDL13_DWHG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2550
ber01-VHDL13_DWHG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2558
ber01-VHDL13_DWHG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 2848
ber01-VHDL13_DWHG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:06 2616
ber01-VHDL13_DWHG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:11 3037
ber01-VHDL13_DWHG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 3057
ber01-VHDL13_DWHG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 3440
ber01-VHDL13_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 3231
ber01-VHDL13_DWHH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2301
ber01-VHDL13_DWHH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2308
ber01-VHDL13_DWHH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 2704
ber01-VHDL13_DWHH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:06 2327
ber01-VHDL13_DWHH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:11 2767
ber01-VHDL13_DWHH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2770
ber01-VHDL13_DWHH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2735
ber01-VHDL13_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:10 2620
ber01-VHDL13_DWLG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2163
ber01-VHDL13_DWLG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:07 2209
ber01-VHDL13_DWLG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 2147
ber01-VHDL13_DWLG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 1663
ber01-VHDL13_DWLG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 2142
ber01-VHDL13_DWLG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1948
ber01-VHDL13_DWLG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1842
ber01-VHDL13_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1821
ber01-VHDL13_DWLH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 1928
ber01-VHDL13_DWLH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:07 2033
ber01-VHDL13_DWLH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 1912
ber01-VHDL13_DWLH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 1902
ber01-VHDL13_DWLH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 1969
ber01-VHDL13_DWLH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 2000
ber01-VHDL13_DWLH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1984
ber01-VHDL13_DWLH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1961
ber01-VHDL13_DWLI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2248
ber01-VHDL13_DWLI_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:07 2215
ber01-VHDL13_DWLI_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 2286
ber01-VHDL13_DWLI_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 2103
ber01-VHDL13_DWLI_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 2151
ber01-VHDL13_DWLI_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1909
ber01-VHDL13_DWLI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1851
ber01-VHDL13_DWLI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1835
ber01-VHDL13_DWMG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2970
ber01-VHDL13_DWMG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:01 2906
ber01-VHDL13_DWMG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 3432
ber01-VHDL13_DWMG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 2917
ber01-VHDL13_DWMG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 3110
ber01-VHDL13_DWMG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 2899
ber01-VHDL13_DWMG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2680
ber01-VHDL13_DWMG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2383
ber01-VHDL13_DWMO_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2390
ber01-VHDL13_DWMO_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:37 2942
ber01-VHDL13_DWMO_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:01 2938
ber01-VHDL13_DWMO_210400_COR-2603210400-dsw--0-ia5 21-Mar-2026 03:50:37 2942
ber01-VHDL13_DWMO_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 3301
ber01-VHDL13_DWMO_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 2786
ber01-VHDL13_DWMO_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 2812
ber01-VHDL13_DWMO_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 2669
ber01-VHDL13_DWMO_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2508
ber01-VHDL13_DWMO_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL13_DWMP_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2720
ber01-VHDL13_DWMP_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:27 3376
ber01-VHDL13_DWMP_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:01 3372
ber01-VHDL13_DWMP_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 3814
ber01-VHDL13_DWMP_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 3287
ber01-VHDL13_DWMP_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 3259
ber01-VHDL13_DWMP_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:03 3086
ber01-VHDL13_DWMP_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 2897
ber01-VHDL13_DWMP_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2516
ber01-VHDL13_DWOG_210300-2603210300-dsw--0-ia5 21-Mar-2026 04:00:06 3309
ber01-VHDL13_DWOG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 3482
ber01-VHDL13_DWOG_211700-2603211700-dsw--0-ia5 21-Mar-2026 19:00:01 3329
ber01-VHDL13_DWOG_220300-2603220300-dsw--0-ia5 22-Mar-2026 04:00:01 3379
ber01-VHDL13_DWOG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:11 3340
ber01-VHDL13_DWOG_221700-2603221700-dsw--0-ia5 22-Mar-2026 19:00:01 3180
ber01-VHDL13_DWOH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:11 2595
ber01-VHDL13_DWOH_210400-2603210400-dsw--0-ia5 21-Mar-2026 05:58:12 2532
ber01-VHDL13_DWOH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:28:17 2516
ber01-VHDL13_DWOH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:28:12 2578
ber01-VHDL13_DWOH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:28:13 2700
ber01-VHDL13_DWOH_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:13 2658
ber01-VHDL13_DWOH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:16 2528
ber01-VHDL13_DWOH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:16 2598
ber01-VHDL13_DWOI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:17 2534
ber01-VHDL13_DWOI_210400-2603210400-dsw--0-ia5 21-Mar-2026 05:58:16 2450
ber01-VHDL13_DWOI_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:28:11 2172
ber01-VHDL13_DWOI_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:28:16 2103
ber01-VHDL13_DWOI_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:28:13 2483
ber01-VHDL13_DWOI_220400-2603220400-dsw--0-ia5 22-Mar-2026 05:58:17 2429
ber01-VHDL13_DWOI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:28:12 2397
ber01-VHDL13_DWOI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:28:12 2297
ber01-VHDL13_DWON_210342-2603210342-dsw--0-ia5 21-Mar-2026 03:42:52 3198
ber01-VHDL13_DWON_210347-2603210347-dsw--0-ia5 21-Mar-2026 03:47:46 3198
ber01-VHDL13_DWON_210605-2603210605-dsw--0-ia5 21-Mar-2026 06:05:47 3198
ber01-VHDL13_DWON_210629-2603210629-dsw--0-ia5 21-Mar-2026 06:29:53 2989
ber01-VHDL13_DWON_210700-2603210700-dsw--0-ia5 21-Mar-2026 07:00:22 3121
ber01-VHDL13_DWON_210735-2603210735-dsw--0-ia5 21-Mar-2026 07:35:08 3105
ber01-VHDL13_DWON_211231-2603211231-dsw--0-ia5 21-Mar-2026 12:31:42 3082
ber01-VHDL13_DWON_211545-2603211545-dsw--0-ia5 21-Mar-2026 15:45:56 3122
ber01-VHDL13_DWON_211546-2603211546-dsw--0-ia5 21-Mar-2026 15:46:46 3124
ber01-VHDL13_DWON_211809-2603211809-dsw--0-ia5 21-Mar-2026 18:09:02 2899
ber01-VHDL13_DWON_220148-2603220148-dsw--0-ia5 22-Mar-2026 01:48:31 3129
ber01-VHDL13_DWON_220341-2603220341-dsw--0-ia5 22-Mar-2026 03:41:31 3129
ber01-VHDL13_DWON_220627-2603220627-dsw--0-ia5 22-Mar-2026 06:27:27 3302
ber01-VHDL13_DWON_220704-2603220704-dsw--0-ia5 22-Mar-2026 07:04:37 3278
ber01-VHDL13_DWON_220921-2603220921-dsw--0-ia5 22-Mar-2026 09:21:29 3284
ber01-VHDL13_DWON_221533-2603221533-dsw--0-ia5 22-Mar-2026 15:33:24 2745
ber01-VHDL13_DWON_221731-2603221731-dsw--0-ia5 22-Mar-2026 17:32:03 2745
ber01-VHDL13_DWON_221752-2603221752-dsw--0-ia5 22-Mar-2026 17:52:23 3119
ber01-VHDL13_DWON_221937-2603221937-dsw--0-ia5 22-Mar-2026 19:37:28 3120
ber01-VHDL13_DWON_222228-2603222228-dsw--0-ia5 22-Mar-2026 22:28:57 3118
ber01-VHDL13_DWON_230000-2603230000-dsw--0-ia5 23-Mar-2026 00:00:22 3800
ber01-VHDL13_DWON_230137-2603230137-dsw--0-ia5 23-Mar-2026 01:37:26 3771
ber01-VHDL13_DWPG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2014
ber01-VHDL13_DWPG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:07 1974
ber01-VHDL13_DWPG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 1855
ber01-VHDL13_DWPG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 1517
ber01-VHDL13_DWPG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 1810
ber01-VHDL13_DWPG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1771
ber01-VHDL13_DWPG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1751
ber01-VHDL13_DWPG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1745
ber01-VHDL13_DWPH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 1927
ber01-VHDL13_DWPH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:07 1941
ber01-VHDL13_DWPH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 1826
ber01-VHDL13_DWPH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:01 1992
ber01-VHDL13_DWPH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 2223
ber01-VHDL13_DWPH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:01 1984
ber01-VHDL13_DWPH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 1903
ber01-VHDL13_DWPH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 1868
ber01-VHDL13_DWSG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2596
ber01-VHDL13_DWSG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:13 2797
ber01-VHDL13_DWSG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:30:09 2800
ber01-VHDL13_DWSG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:30:06 2416
ber01-VHDL13_DWSG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:30:04 2862
ber01-VHDL13_DWSG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2665
ber01-VHDL13_DWSG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:30:04 2658
ber01-VHDL13_DWSG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:30:02 2308
ber01-VHDL17_DWOG_211200-2603211200-dsw--0-ia5 21-Mar-2026 11:55:31 2638
ber01-VHDL17_DWOG_221200-2603221200-dsw--0-ia5 22-Mar-2026 12:50:40 4087
swis2-VHDL20_DWEG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2873
swis2-VHDL20_DWEG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 3004
swis2-VHDL20_DWEG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 3143
swis2-VHDL20_DWEG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:06 3056
swis2-VHDL20_DWEG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 3111
swis2-VHDL20_DWEG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2975
swis2-VHDL20_DWEG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 3002
swis2-VHDL20_DWEG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3022
swis2-VHDL20_DWEH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 3008
swis2-VHDL20_DWEH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 3105
swis2-VHDL20_DWEH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 2974
swis2-VHDL20_DWEH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:06 2556
swis2-VHDL20_DWEH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 2811
swis2-VHDL20_DWEH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2767
swis2-VHDL20_DWEH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 2859
swis2-VHDL20_DWEH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2900
swis2-VHDL20_DWEI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2827
swis2-VHDL20_DWEI_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 2799
swis2-VHDL20_DWEI_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 2692
swis2-VHDL20_DWEI_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:06 2452
swis2-VHDL20_DWEI_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 2776
swis2-VHDL20_DWEI_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 2777
swis2-VHDL20_DWEI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 2918
swis2-VHDL20_DWEI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2746
swis2-VHDL20_DWHG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2736
swis2-VHDL20_DWHG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2741
swis2-VHDL20_DWHG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 3384
swis2-VHDL20_DWHG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2799
swis2-VHDL20_DWHG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 3223
swis2-VHDL20_DWHG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 3240
swis2-VHDL20_DWHG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 4124
swis2-VHDL20_DWHG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 3414
swis2-VHDL20_DWHH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2487
swis2-VHDL20_DWHH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2494
swis2-VHDL20_DWHH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 3246
swis2-VHDL20_DWHH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2513
swis2-VHDL20_DWHH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2953
swis2-VHDL20_DWHH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:07 2956
swis2-VHDL20_DWHH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 3428
swis2-VHDL20_DWHH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2806
swis2-VHDL20_DWLG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2505
swis2-VHDL20_DWLG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2551
swis2-VHDL20_DWLG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 2634
swis2-VHDL20_DWLG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2005
swis2-VHDL20_DWLG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2484
swis2-VHDL20_DWLG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2289
swis2-VHDL20_DWLG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2330
swis2-VHDL20_DWLG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2162
swis2-VHDL20_DWLH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2277
swis2-VHDL20_DWLH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2382
swis2-VHDL20_DWLH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 2410
swis2-VHDL20_DWLH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2251
swis2-VHDL20_DWLH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2318
swis2-VHDL20_DWLH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2348
swis2-VHDL20_DWLH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2483
swis2-VHDL20_DWLH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2309
swis2-VHDL20_DWLI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2592
swis2-VHDL20_DWLI_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2559
swis2-VHDL20_DWLI_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 2774
swis2-VHDL20_DWLI_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2447
swis2-VHDL20_DWLI_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2495
swis2-VHDL20_DWLI_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2252
swis2-VHDL20_DWLI_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2340
swis2-VHDL20_DWLI_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2178
swis2-VHDL20_DWMG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 3659
swis2-VHDL20_DWMG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 3362
swis2-VHDL20_DWMG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 4113
swis2-VHDL20_DWMG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 3401
swis2-VHDL20_DWMG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:04 3592
swis2-VHDL20_DWMG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 3289
swis2-VHDL20_DWMG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 3247
swis2-VHDL20_DWMG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2773
swis2-VHDL20_DWMO_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2787
swis2-VHDL20_DWMO_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:37 3339
swis2-VHDL20_DWMO_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 3088
swis2-VHDL20_DWMO_210400_COR-2603210400-dsw--0-ia5 21-Mar-2026 03:50:37 3364
swis2-VHDL20_DWMO_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 3966
swis2-VHDL20_DWMO_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 3250
swis2-VHDL20_DWMO_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:04 3276
swis2-VHDL20_DWMO_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 3063
swis2-VHDL20_DWMO_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 3084
swis2-VHDL20_DWMO_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2702
swis2-VHDL20_DWMP_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 3114
swis2-VHDL20_DWMP_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:27 3770
swis2-VHDL20_DWMP_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:06 3499
swis2-VHDL20_DWMP_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:03 4499
swis2-VHDL20_DWMP_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 3682
swis2-VHDL20_DWMP_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:04 3716
swis2-VHDL20_DWMP_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 3476
swis2-VHDL20_DWMP_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:07 3471
swis2-VHDL20_DWMP_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2895
swis2-VHDL20_DWPG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2343
swis2-VHDL20_DWPG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2300
swis2-VHDL20_DWPG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 2313
swis2-VHDL20_DWPG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 1975
swis2-VHDL20_DWPG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2139
swis2-VHDL20_DWPG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2096
swis2-VHDL20_DWPG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2210
swis2-VHDL20_DWPG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2204
swis2-VHDL20_DWPH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2255
swis2-VHDL20_DWPH_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:00:11 2269
swis2-VHDL20_DWPH_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 2284
swis2-VHDL20_DWPH_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:02 2450
swis2-VHDL20_DWPH_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:01 2551
swis2-VHDL20_DWPH_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:00:11 2311
swis2-VHDL20_DWPH_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 2362
swis2-VHDL20_DWPH_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2327
swis2-VHDL20_DWSG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2946
swis2-VHDL20_DWSG_210400-2603210400-dsw--0-ia5 21-Mar-2026 06:15:03 3243
swis2-VHDL20_DWSG_210800-2603210800-dsw--0-ia5 21-Mar-2026 09:45:07 3391
swis2-VHDL20_DWSG_211300-2603211300-dsw--0-ia5 21-Mar-2026 14:45:04 3313
swis2-VHDL20_DWSG_211800-2603211800-dsw--0-ia5 21-Mar-2026 19:45:06 2899
swis2-VHDL20_DWSG_220200-2603220200-dsw--0-ia5 22-Mar-2026 03:45:07 3313
swis2-VHDL20_DWSG_220400-2603220400-dsw--0-ia5 22-Mar-2026 06:15:01 3018
swis2-VHDL20_DWSG_220800-2603220800-dsw--0-ia5 22-Mar-2026 09:45:01 3157
swis2-VHDL20_DWSG_221300-2603221300-dsw--0-ia5 22-Mar-2026 14:45:11 2951
swis2-VHDL20_DWSG_221800-2603221800-dsw--0-ia5 22-Mar-2026 19:45:02 2662
wst04-VHDL20_DWEG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 245133
wst04-VHDL20_DWEG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:12 244970
wst04-VHDL20_DWEG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:17 244003
wst04-VHDL20_DWEG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:12 241549
wst04-VHDL20_DWEG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:17 242373
wst04-VHDL20_DWEG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:16 241915
wst04-VHDL20_DWEG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:11 238789
wst04-VHDL20_DWEG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 237684
wst04-VHDL20_DWEH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 240510
wst04-VHDL20_DWEH_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:16 240205
wst04-VHDL20_DWEH_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:17 239605
wst04-VHDL20_DWEH_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:12 239241
wst04-VHDL20_DWEH_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:11 239684
wst04-VHDL20_DWEH_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:16 239374
wst04-VHDL20_DWEH_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:11 236241
wst04-VHDL20_DWEH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 235794
wst04-VHDL20_DWEI_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 351782
wst04-VHDL20_DWEI_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:22 351872
wst04-VHDL20_DWEI_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:27 349319
wst04-VHDL20_DWEI_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:16 348373
wst04-VHDL20_DWEI_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:21 348412
wst04-VHDL20_DWEI_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:22 348501
wst04-VHDL20_DWEI_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:17 338466
wst04-VHDL20_DWEI_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 337886
wst04-VHDL20_DWHG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 355607
wst04-VHDL20_DWHG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:11 355800
wst04-VHDL20_DWHG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:21 349336
wst04-VHDL20_DWHG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:22 346934
wst04-VHDL20_DWHG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:21 347541
wst04-VHDL20_DWHG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:11 347664
wst04-VHDL20_DWHG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:21 346396
wst04-VHDL20_DWHG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 345011
wst04-VHDL20_DWHH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 329725
wst04-VHDL20_DWHH_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:11 329785
wst04-VHDL20_DWHH_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:21 332511
wst04-VHDL20_DWHH_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:16 331460
wst04-VHDL20_DWHH_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:17 333101
wst04-VHDL20_DWHH_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:11 333204
wst04-VHDL20_DWHH_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:17 333642
wst04-VHDL20_DWHH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 332748
wst04-VHDL20_DWLG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 336211
wst04-VHDL20_DWLG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:41 336495
wst04-VHDL20_DWLG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:27 331580
wst04-VHDL20_DWLG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:26 329703
wst04-VHDL20_DWLG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:21 330293
wst04-VHDL20_DWLG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:42 330225
wst04-VHDL20_DWLG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:31 324740
wst04-VHDL20_DWLG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 324079
wst04-VHDL20_DWLH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 338304
wst04-VHDL20_DWLH_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:41 338550
wst04-VHDL20_DWLH_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:27 344094
wst04-VHDL20_DWLH_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:22 343229
wst04-VHDL20_DWLH_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:21 343358
wst04-VHDL20_DWLH_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:42 343484
wst04-VHDL20_DWLH_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:27 333423
wst04-VHDL20_DWLH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:26 332706
wst04-VHDL20_DWLI_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:26 335067
wst04-VHDL20_DWLI_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:41 335122
wst04-VHDL20_DWLI_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:31 337411
wst04-VHDL20_DWLI_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:22 336731
wst04-VHDL20_DWLI_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:28 336807
wst04-VHDL20_DWLI_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:42 336676
wst04-VHDL20_DWLI_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:31 334072
wst04-VHDL20_DWLI_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 332925
wst04-VHDL20_DWMG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 543284
wst04-VHDL20_DWMG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:22 542053
wst04-VHDL20_DWMG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:17 541346
wst04-VHDL20_DWMG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:16 540145
wst04-VHDL20_DWMG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:15 539884
wst04-VHDL20_DWMG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:26 539908
wst04-VHDL20_DWMG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:27 539454
wst04-VHDL20_DWMG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 538839
wst04-VHDL20_DWMO_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 442874
wst04-VHDL20_DWMO_210200_COR-2603210200-omedes-..> 21-Mar-2026 03:59:41 443862
wst04-VHDL20_DWMO_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:22 443657
wst04-VHDL20_DWMO_210400_COR-2603210400-omedes-..> 21-Mar-2026 03:50:45 444342
wst04-VHDL20_DWMO_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:13 446549
wst04-VHDL20_DWMO_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:16 445383
wst04-VHDL20_DWMO_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:13 445441
wst04-VHDL20_DWMO_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:22 445580
wst04-VHDL20_DWMO_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:21 449273
wst04-VHDL20_DWMO_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 448400
wst04-VHDL20_DWMP_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 541792
wst04-VHDL20_DWMP_210200_COR-2603210200-omedes-..> 21-Mar-2026 03:59:31 542416
wst04-VHDL20_DWMP_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:22 542663
wst04-VHDL20_DWMP_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:27 541930
wst04-VHDL20_DWMP_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:16 540108
wst04-VHDL20_DWMP_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:15 538101
wst04-VHDL20_DWMP_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:26 539348
wst04-VHDL20_DWMP_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:27 534799
wst04-VHDL20_DWMP_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:16 534219
wst04-VHDL20_DWPG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:26 343500
wst04-VHDL20_DWPG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:31 343459
wst04-VHDL20_DWPG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:31 392977
wst04-VHDL20_DWPG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:26 347804
wst04-VHDL20_DWPG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:28 347950
wst04-VHDL20_DWPG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:31 347923
wst04-VHDL20_DWPG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:31 385838
wst04-VHDL20_DWPG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:26 340846
wst04-VHDL20_DWPH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 242085
wst04-VHDL20_DWPH_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:00:31 242181
wst04-VHDL20_DWPH_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:27 290912
wst04-VHDL20_DWPH_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:22 290860
wst04-VHDL20_DWPH_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:21 246374
wst04-VHDL20_DWPH_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:00:31 246239
wst04-VHDL20_DWPH_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:27 283769
wst04-VHDL20_DWPH_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:22 282951
wst04-VHDL20_DWSG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 348811
wst04-VHDL20_DWSG_210400-2603210400-omedes--0.pdf 21-Mar-2026 06:15:18 348550
wst04-VHDL20_DWSG_210800-2603210800-omedes--0.pdf 21-Mar-2026 09:45:11 348770
wst04-VHDL20_DWSG_211300-2603211300-omedes--0.pdf 21-Mar-2026 14:45:11 349208
wst04-VHDL20_DWSG_211800-2603211800-omedes--0.pdf 21-Mar-2026 19:45:12 348605
wst04-VHDL20_DWSG_220200-2603220200-omedes--0.pdf 22-Mar-2026 03:45:11 348099
wst04-VHDL20_DWSG_220400-2603220400-omedes--0.pdf 22-Mar-2026 06:15:12 348553
wst04-VHDL20_DWSG_220800-2603220800-omedes--0.pdf 22-Mar-2026 09:45:11 342119
wst04-VHDL20_DWSG_221300-2603221300-omedes--0.pdf 22-Mar-2026 14:45:11 341523
wst04-VHDL20_DWSG_221800-2603221800-omedes--0.pdf 22-Mar-2026 19:45:12 340444