Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Mar-2026 13:15:09 4400
FPDL13_DWMZ_200600 20-Mar-2026 14:56:30 4304
SXDL31_DWAV_190800 19-Mar-2026 07:44:54 11687
SXDL31_DWAV_191800 19-Mar-2026 17:37:10 4627
SXDL31_DWAV_200800 20-Mar-2026 08:57:25 13144
SXDL31_DWAV_201800 20-Mar-2026 17:21:39 2595
SXDL31_DWAV_LATEST 20-Mar-2026 17:21:39 2595
SXDL33_DWAV_190000 19-Mar-2026 10:58:45 9367
SXDL33_DWAV_200000 20-Mar-2026 11:12:14 9887
SXDL33_DWAV_LATEST 20-Mar-2026 11:12:14 9887
ber01-FWDL39_DWMS_191230-2603191230-dsw--0-ia5 19-Mar-2026 12:20:35 1779
ber01-FWDL39_DWMS_201230-2603201230-dsw--0-ia5 20-Mar-2026 12:31:57 1113
ber01-VHDL13_DWEH_190400-2603190400-dsw--0-ia5 19-Mar-2026 05:58:12 2693
ber01-VHDL13_DWEH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:28:16 2511
ber01-VHDL13_DWEH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:28:16 2480
ber01-VHDL13_DWEH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:28:11 2596
ber01-VHDL13_DWEH_200400-2603200400-dsw--0-ia5 20-Mar-2026 05:58:11 2528
ber01-VHDL13_DWEH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:28:16 2595
ber01-VHDL13_DWEH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:28:17 2503
ber01-VHDL13_DWEH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:11 2686
ber01-VHDL13_DWHG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2635
ber01-VHDL13_DWHG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:13 2815
ber01-VHDL13_DWHG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:06 2884
ber01-VHDL13_DWHG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2719
ber01-VHDL13_DWHG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:06 2719
ber01-VHDL13_DWHG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 2695
ber01-VHDL13_DWHG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:09 2332
ber01-VHDL13_DWHG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2550
ber01-VHDL13_DWHH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2934
ber01-VHDL13_DWHH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:13 2678
ber01-VHDL13_DWHH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:06 2546
ber01-VHDL13_DWHH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2364
ber01-VHDL13_DWHH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:06 2364
ber01-VHDL13_DWHH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 2503
ber01-VHDL13_DWHH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:09 2077
ber01-VHDL13_DWHH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2301
ber01-VHDL13_DWLG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:01 1823
ber01-VHDL13_DWLG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 1792
ber01-VHDL13_DWLG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 1603
ber01-VHDL13_DWLG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 1730
ber01-VHDL13_DWLG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:00 1971
ber01-VHDL13_DWLG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 1988
ber01-VHDL13_DWLG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 2056
ber01-VHDL13_DWLG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2163
ber01-VHDL13_DWLH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:01 2115
ber01-VHDL13_DWLH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2203
ber01-VHDL13_DWLH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 1893
ber01-VHDL13_DWLH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 1937
ber01-VHDL13_DWLH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:00 1934
ber01-VHDL13_DWLH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 1820
ber01-VHDL13_DWLH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 1806
ber01-VHDL13_DWLH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 1928
ber01-VHDL13_DWLI_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:01 1883
ber01-VHDL13_DWLI_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 1962
ber01-VHDL13_DWLI_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 1766
ber01-VHDL13_DWLI_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 1909
ber01-VHDL13_DWLI_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:00 1929
ber01-VHDL13_DWLI_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 1927
ber01-VHDL13_DWLI_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 2097
ber01-VHDL13_DWLI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2248
ber01-VHDL13_DWMG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:07 2676
ber01-VHDL13_DWMG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2372
ber01-VHDL13_DWMG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 2535
ber01-VHDL13_DWMG_191800_COR-2603191800-dsw--0-ia5 19-Mar-2026 20:07:27 2639
ber01-VHDL13_DWMG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2728
ber01-VHDL13_DWMG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:02 2720
ber01-VHDL13_DWMG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 3089
ber01-VHDL13_DWMG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:09 2786
ber01-VHDL13_DWMG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2970
ber01-VHDL13_DWMO_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:07 2401
ber01-VHDL13_DWMO_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2073
ber01-VHDL13_DWMO_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 2252
ber01-VHDL13_DWMO_191800_COR-2603191800-dsw--0-ia5 19-Mar-2026 20:08:01 2510
ber01-VHDL13_DWMO_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2553
ber01-VHDL13_DWMO_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:02 2546
ber01-VHDL13_DWMO_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 2523
ber01-VHDL13_DWMO_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:09 2422
ber01-VHDL13_DWMO_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2390
ber01-VHDL13_DWMO_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:37 2942
ber01-VHDL13_DWMO_210400_COR-2603210400-dsw--0-ia5 21-Mar-2026 03:50:37 2942
ber01-VHDL13_DWMP_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:07 2621
ber01-VHDL13_DWMP_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2161
ber01-VHDL13_DWMP_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 2464
ber01-VHDL13_DWMP_191800_COR-2603191800-dsw--0-ia5 19-Mar-2026 20:07:51 2682
ber01-VHDL13_DWMP_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2793
ber01-VHDL13_DWMP_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:02 2765
ber01-VHDL13_DWMP_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 3117
ber01-VHDL13_DWMP_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:09 2788
ber01-VHDL13_DWMP_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2720
ber01-VHDL13_DWMP_210200_COR-2603210200-dsw--0-ia5 21-Mar-2026 03:59:27 3376
ber01-VHDL13_DWOG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:13 3381
ber01-VHDL13_DWOG_191700-2603191700-dsw--0-ia5 19-Mar-2026 19:00:01 3281
ber01-VHDL13_DWOG_200300-2603200300-dsw--0-ia5 20-Mar-2026 04:00:01 3225
ber01-VHDL13_DWOG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:07 3046
ber01-VHDL13_DWOG_201700-2603201700-dsw--0-ia5 20-Mar-2026 19:00:01 2866
ber01-VHDL13_DWOG_210300-2603210300-dsw--0-ia5 21-Mar-2026 04:00:06 3309
ber01-VHDL13_DWOH_190400-2603190400-dsw--0-ia5 19-Mar-2026 05:58:12 2433
ber01-VHDL13_DWOH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:28:12 2357
ber01-VHDL13_DWOH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:28:16 2465
ber01-VHDL13_DWOH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:28:11 2480
ber01-VHDL13_DWOH_200400-2603200400-dsw--0-ia5 20-Mar-2026 05:58:11 2523
ber01-VHDL13_DWOH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:28:12 2667
ber01-VHDL13_DWOH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:28:17 2457
ber01-VHDL13_DWOH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:11 2595
ber01-VHDL13_DWOI_190400-2603190400-dsw--0-ia5 19-Mar-2026 05:58:17 2435
ber01-VHDL13_DWOI_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:28:16 2378
ber01-VHDL13_DWOI_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:28:12 2370
ber01-VHDL13_DWOI_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:28:18 2190
ber01-VHDL13_DWOI_200400-2603200400-dsw--0-ia5 20-Mar-2026 05:58:17 2297
ber01-VHDL13_DWOI_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:28:12 2357
ber01-VHDL13_DWOI_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:28:11 2191
ber01-VHDL13_DWOI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:28:17 2534
ber01-VHDL13_DWON_190417-2603190417-dsw--0-ia5 19-Mar-2026 04:17:47 3597
ber01-VHDL13_DWON_190625-2603190625-dsw--0-ia5 19-Mar-2026 06:25:41 3462
ber01-VHDL13_DWON_190645-2603190645-dsw--0-ia5 19-Mar-2026 06:45:06 3460
ber01-VHDL13_DWON_190907-2603190907-dsw--0-ia5 19-Mar-2026 09:07:26 3460
ber01-VHDL13_DWON_191513-2603191513-dsw--0-ia5 19-Mar-2026 15:13:41 3506
ber01-VHDL13_DWON_191739-2603191739-dsw--0-ia5 19-Mar-2026 17:40:06 3022
ber01-VHDL13_DWON_191933-2603191933-dsw--0-ia5 19-Mar-2026 19:33:48 3022
ber01-VHDL13_DWON_200130-2603200130-dsw--0-ia5 20-Mar-2026 01:30:35 3379
ber01-VHDL13_DWON_200629-2603200629-dsw--0-ia5 20-Mar-2026 06:30:02 3271
ber01-VHDL13_DWON_200716-2603200716-dsw--0-ia5 20-Mar-2026 07:17:02 3206
ber01-VHDL13_DWON_200951-2603200951-dsw--0-ia5 20-Mar-2026 09:51:16 3206
ber01-VHDL13_DWON_201421-2603201421-dsw--0-ia5 20-Mar-2026 14:21:52 3128
ber01-VHDL13_DWON_201633-2603201633-dsw--0-ia5 20-Mar-2026 16:33:16 2866
ber01-VHDL13_DWON_201739-2603201739-dsw--0-ia5 20-Mar-2026 17:39:06 2918
ber01-VHDL13_DWON_201808-2603201808-dsw--0-ia5 20-Mar-2026 18:08:58 2918
ber01-VHDL13_DWON_210143-2603210143-dsw--0-ia5 21-Mar-2026 01:43:31 3198
ber01-VHDL13_DWON_210342-2603210342-dsw--0-ia5 21-Mar-2026 03:42:52 3198
ber01-VHDL13_DWON_210347-2603210347-dsw--0-ia5 21-Mar-2026 03:47:46 3198
ber01-VHDL13_DWPG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:01 2264
ber01-VHDL13_DWPG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2336
ber01-VHDL13_DWPG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 2029
ber01-VHDL13_DWPG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 1976
ber01-VHDL13_DWPG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:00 1956
ber01-VHDL13_DWPG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 1775
ber01-VHDL13_DWPG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 1840
ber01-VHDL13_DWPG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 2014
ber01-VHDL13_DWPH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:01 2224
ber01-VHDL13_DWPH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:04 2239
ber01-VHDL13_DWPH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 1903
ber01-VHDL13_DWPH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 1949
ber01-VHDL13_DWPH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:00 1965
ber01-VHDL13_DWPH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 1873
ber01-VHDL13_DWPH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 1825
ber01-VHDL13_DWPH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:11 1927
ber01-VHDL13_DWSG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2543
ber01-VHDL13_DWSG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:30:13 2656
ber01-VHDL13_DWSG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:30:01 2103
ber01-VHDL13_DWSG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:30:11 2619
ber01-VHDL13_DWSG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:06 2445
ber01-VHDL13_DWSG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:30:04 2714
ber01-VHDL13_DWSG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:30:05 2205
ber01-VHDL13_DWSG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:30:12 2596
ber01-VHDL17_DWOG_191200-2603191200-dsw--0-ia5 19-Mar-2026 12:52:21 2910
ber01-VHDL17_DWOG_201200-2603201200-dsw--0-ia5 20-Mar-2026 12:42:33 2646
swis2-VHDL20_DWEG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:15:01 2756
swis2-VHDL20_DWEG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 2835
swis2-VHDL20_DWEG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:02 2791
swis2-VHDL20_DWEG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2759
swis2-VHDL20_DWEG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:15:02 2841
swis2-VHDL20_DWEG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:06 3295
swis2-VHDL20_DWEG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2781
swis2-VHDL20_DWEG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2873
swis2-VHDL20_DWEH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:15:01 3028
swis2-VHDL20_DWEH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:06 3011
swis2-VHDL20_DWEH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:02 2831
swis2-VHDL20_DWEH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2917
swis2-VHDL20_DWEH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:15:02 2858
swis2-VHDL20_DWEH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:06 3233
swis2-VHDL20_DWEH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2855
swis2-VHDL20_DWEH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 3008
swis2-VHDL20_DWEI_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:15:01 2786
swis2-VHDL20_DWEI_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 2900
swis2-VHDL20_DWEI_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:02 2718
swis2-VHDL20_DWEI_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2482
swis2-VHDL20_DWEI_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:15:02 2646
swis2-VHDL20_DWEI_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:06 2878
swis2-VHDL20_DWEI_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2540
swis2-VHDL20_DWEI_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2827
swis2-VHDL20_DWHG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2818
swis2-VHDL20_DWHG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 3400
swis2-VHDL20_DWHG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 3067
swis2-VHDL20_DWHG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2905
swis2-VHDL20_DWHG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:06 2902
swis2-VHDL20_DWHG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 3325
swis2-VHDL20_DWHG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:06 2515
swis2-VHDL20_DWHG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2736
swis2-VHDL20_DWHH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 3120
swis2-VHDL20_DWHH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 3272
swis2-VHDL20_DWHH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 2732
swis2-VHDL20_DWHH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2550
swis2-VHDL20_DWHH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:06 2550
swis2-VHDL20_DWHH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 3148
swis2-VHDL20_DWHH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:06 2263
swis2-VHDL20_DWHH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2487
swis2-VHDL20_DWLG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2164
swis2-VHDL20_DWLG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 2279
swis2-VHDL20_DWLG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 1944
swis2-VHDL20_DWLG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2071
swis2-VHDL20_DWLG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:12 2313
swis2-VHDL20_DWLG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 2476
swis2-VHDL20_DWLG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2398
swis2-VHDL20_DWLG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2505
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swis2-VHDL20_DWMO_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2787
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swis2-VHDL20_DWMP_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:15:07 3012
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swis2-VHDL20_DWMP_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:02 3187
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swis2-VHDL20_DWMP_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 3114
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swis2-VHDL20_DWPG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2590
swis2-VHDL20_DWPG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 2795
swis2-VHDL20_DWPG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 2488
swis2-VHDL20_DWPG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2305
swis2-VHDL20_DWPG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:12 2282
swis2-VHDL20_DWPG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 2234
swis2-VHDL20_DWPG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2299
swis2-VHDL20_DWPG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2343
swis2-VHDL20_DWPH_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:00:11 2552
swis2-VHDL20_DWPH_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 2698
swis2-VHDL20_DWPH_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 2362
swis2-VHDL20_DWPH_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2277
swis2-VHDL20_DWPH_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:00:12 2293
swis2-VHDL20_DWPH_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 2332
swis2-VHDL20_DWPH_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2284
swis2-VHDL20_DWPH_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2255
swis2-VHDL20_DWSG_190400-2603190400-dsw--0-ia5 19-Mar-2026 06:15:01 2922
swis2-VHDL20_DWSG_190800-2603190800-dsw--0-ia5 19-Mar-2026 09:45:01 3181
swis2-VHDL20_DWSG_191300-2603191300-dsw--0-ia5 19-Mar-2026 14:45:07 2851
swis2-VHDL20_DWSG_191800-2603191800-dsw--0-ia5 19-Mar-2026 19:45:06 2484
swis2-VHDL20_DWSG_200200-2603200200-dsw--0-ia5 20-Mar-2026 03:45:06 2994
swis2-VHDL20_DWSG_200400-2603200400-dsw--0-ia5 20-Mar-2026 06:15:06 2824
swis2-VHDL20_DWSG_200800-2603200800-dsw--0-ia5 20-Mar-2026 09:45:01 3270
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swis2-VHDL20_DWSG_201800-2603201800-dsw--0-ia5 20-Mar-2026 19:45:04 2586
swis2-VHDL20_DWSG_210200-2603210200-dsw--0-ia5 21-Mar-2026 03:45:06 2946
wst04-VHDL20_DWEG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:17 244371
wst04-VHDL20_DWEG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:16 241081
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wst04-VHDL20_DWEG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:16 240734
wst04-VHDL20_DWEG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:22 240997
wst04-VHDL20_DWEG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:16 246322
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wst04-VHDL20_DWEG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 245133
wst04-VHDL20_DWEH_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:17 244960
wst04-VHDL20_DWEH_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:12 240008
wst04-VHDL20_DWEH_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:12 239013
wst04-VHDL20_DWEH_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:16 240560
wst04-VHDL20_DWEH_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:18 240248
wst04-VHDL20_DWEH_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:12 240824
wst04-VHDL20_DWEH_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:12 238971
wst04-VHDL20_DWEH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 240510
wst04-VHDL20_DWEI_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:21 347039
wst04-VHDL20_DWEI_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:16 343750
wst04-VHDL20_DWEI_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:12 343358
wst04-VHDL20_DWEI_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:16 342997
wst04-VHDL20_DWEI_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:18 343826
wst04-VHDL20_DWEI_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:16 351962
wst04-VHDL20_DWEI_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:12 350945
wst04-VHDL20_DWEI_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 351782
wst04-VHDL20_DWHG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:11 352909
wst04-VHDL20_DWHG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:22 355708
wst04-VHDL20_DWHG_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:16 354790
wst04-VHDL20_DWHG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:22 354987
wst04-VHDL20_DWHG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:12 354994
wst04-VHDL20_DWHG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:28 356325
wst04-VHDL20_DWHG_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:22 354831
wst04-VHDL20_DWHG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 355607
wst04-VHDL20_DWHH_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:11 335027
wst04-VHDL20_DWHH_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:22 329638
wst04-VHDL20_DWHH_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:16 329144
wst04-VHDL20_DWHH_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:22 329159
wst04-VHDL20_DWHH_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:12 329235
wst04-VHDL20_DWHH_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:28 329684
wst04-VHDL20_DWHH_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:16 328797
wst04-VHDL20_DWHH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 329725
wst04-VHDL20_DWLG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:42 333522
wst04-VHDL20_DWLG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:32 335434
wst04-VHDL20_DWLG_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:22 334525
wst04-VHDL20_DWLG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:26 336067
wst04-VHDL20_DWLG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:42 336593
wst04-VHDL20_DWLG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:36 337146
wst04-VHDL20_DWLG_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:26 335743
wst04-VHDL20_DWLG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 336211
wst04-VHDL20_DWLH_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:42 339588
wst04-VHDL20_DWLH_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:30 346007
wst04-VHDL20_DWLH_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:22 345318
wst04-VHDL20_DWLH_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:22 346656
wst04-VHDL20_DWLH_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:42 346860
wst04-VHDL20_DWLH_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:30 338881
wst04-VHDL20_DWLH_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:20 337607
wst04-VHDL20_DWLH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 338304
wst04-VHDL20_DWLI_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:42 339795
wst04-VHDL20_DWLI_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:32 332900
wst04-VHDL20_DWLI_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:26 331971
wst04-VHDL20_DWLI_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:22 333736
wst04-VHDL20_DWLI_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:42 333937
wst04-VHDL20_DWLI_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:30 335293
wst04-VHDL20_DWLI_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:20 334806
wst04-VHDL20_DWLI_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:26 335067
wst04-VHDL20_DWMG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:21 532378
wst04-VHDL20_DWMG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:26 541962
wst04-VHDL20_DWMG_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:22 541390
wst04-VHDL20_DWMG_191800_COR-2603191800-omedes-..> 19-Mar-2026 20:07:37 541390
wst04-VHDL20_DWMG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:16 541707
wst04-VHDL20_DWMG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:22 541624
wst04-VHDL20_DWMG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:16 542800
wst04-VHDL20_DWMG_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:16 541591
wst04-VHDL20_DWMG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 543284
wst04-VHDL20_DWMO_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:17 444010
wst04-VHDL20_DWMO_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:22 452905
wst04-VHDL20_DWMO_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:18 452601
wst04-VHDL20_DWMO_191800_COR-2603191800-omedes-..> 19-Mar-2026 20:08:07 452872
wst04-VHDL20_DWMO_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:12 453076
wst04-VHDL20_DWMO_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:22 453536
wst04-VHDL20_DWMO_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:16 442959
wst04-VHDL20_DWMO_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:16 442775
wst04-VHDL20_DWMO_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 442874
wst04-VHDL20_DWMO_210200_COR-2603210200-omedes-..> 21-Mar-2026 03:59:41 443862
wst04-VHDL20_DWMO_210400_COR-2603210400-omedes-..> 21-Mar-2026 03:50:45 444342
wst04-VHDL20_DWMP_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:17 526125
wst04-VHDL20_DWMP_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:26 532369
wst04-VHDL20_DWMP_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:18 532670
wst04-VHDL20_DWMP_191800_COR-2603191800-omedes-..> 19-Mar-2026 20:07:57 532671
wst04-VHDL20_DWMP_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:12 531781
wst04-VHDL20_DWMP_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:26 532789
wst04-VHDL20_DWMP_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:26 543515
wst04-VHDL20_DWMP_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:16 541833
wst04-VHDL20_DWMP_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:17 541792
wst04-VHDL20_DWMP_210200_COR-2603210200-omedes-..> 21-Mar-2026 03:59:31 542416
wst04-VHDL20_DWPG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:32 346828
wst04-VHDL20_DWPG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:32 392570
wst04-VHDL20_DWPG_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:26 347689
wst04-VHDL20_DWPG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:26 348627
wst04-VHDL20_DWPG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:32 348706
wst04-VHDL20_DWPG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:30 388894
wst04-VHDL20_DWPG_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:26 343367
wst04-VHDL20_DWPG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:26 343500
wst04-VHDL20_DWPH_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:00:32 244236
wst04-VHDL20_DWPH_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:26 291803
wst04-VHDL20_DWPH_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:22 291602
wst04-VHDL20_DWPH_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:22 247362
wst04-VHDL20_DWPH_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:00:32 247412
wst04-VHDL20_DWPH_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:26 286836
wst04-VHDL20_DWPH_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:20 286677
wst04-VHDL20_DWPH_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:22 242085
wst04-VHDL20_DWSG_190400-2603190400-omedes--0.pdf 19-Mar-2026 06:15:11 346898
wst04-VHDL20_DWSG_190800-2603190800-omedes--0.pdf 19-Mar-2026 09:45:10 341193
wst04-VHDL20_DWSG_191300-2603191300-omedes--0.pdf 19-Mar-2026 14:45:25 339913
wst04-VHDL20_DWSG_191800-2603191800-omedes--0.pdf 19-Mar-2026 19:45:12 339688
wst04-VHDL20_DWSG_200200-2603200200-omedes--0.pdf 20-Mar-2026 03:45:12 341294
wst04-VHDL20_DWSG_200400-2603200400-omedes--0.pdf 20-Mar-2026 06:15:12 340538
wst04-VHDL20_DWSG_200800-2603200800-omedes--0.pdf 20-Mar-2026 09:45:12 348287
wst04-VHDL20_DWSG_201300-2603201300-omedes--0.pdf 20-Mar-2026 14:45:16 347853
wst04-VHDL20_DWSG_201800-2603201800-omedes--0.pdf 20-Mar-2026 19:45:12 346982
wst04-VHDL20_DWSG_210200-2603210200-omedes--0.pdf 21-Mar-2026 03:45:11 348811