Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Jul-2026 12:41:08 4353
SXDL31_DWAV_021800 02-Jul-2026 16:06:24 11237
SXDL31_DWAV_030800 03-Jul-2026 06:42:06 7487
SXDL31_DWAV_031800 03-Jul-2026 16:15:04 7128
SXDL31_DWAV_040800 04-Jul-2026 06:47:43 8669
SXDL31_DWAV_LATEST 04-Jul-2026 06:47:43 8669
SXDL33_DWAV_030000 03-Jul-2026 10:46:19 7996
SXDL33_DWAV_040000 04-Jul-2026 09:59:05 7167
SXDL33_DWAV_LATEST 04-Jul-2026 09:59:05 7167
ber01-FWDL39_DWMS_021200-2607021200-dsw--0-ia5 02-Jul-2026 12:16:07 1553
ber01-FWDL39_DWMS_031200-2607031200-dsw--0-ia5 03-Jul-2026 11:23:07 1736
ber01-VHDL13_DWEG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2395
ber01-VHDL13_DWEG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2997
ber01-VHDL13_DWEH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2360
ber01-VHDL13_DWEH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2541
ber01-VHDL13_DWEI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:28:17 2057
ber01-VHDL13_DWEI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:28:18 2533
ber01-VHDL13_DWHG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:07 3701
ber01-VHDL13_DWHG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3859
ber01-VHDL13_DWHH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:07 3365
ber01-VHDL13_DWHH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3281
ber01-VHDL13_DWLG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2145
ber01-VHDL13_DWLG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3047
ber01-VHDL13_DWLH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2258
ber01-VHDL13_DWLH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2590
ber01-VHDL13_DWLI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2072
ber01-VHDL13_DWLI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2610
ber01-VHDL13_DWMO_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 2884
ber01-VHDL13_DWMO_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3143
ber01-VHDL13_DWMP_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 2851
ber01-VHDL13_DWMP_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3034
ber01-VHDL13_DWMP_040800_COR-2607040800-dsw--0-ia5 04-Jul-2026 08:44:45 3159
ber01-VHDL13_DWOG_021700-2607021700-dsw--0-ia5 02-Jul-2026 18:00:02 4071
ber01-VHDL13_DWOG_030300-2607030300-dsw--0-ia5 03-Jul-2026 03:00:20 3915
ber01-VHDL13_DWOG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 3867
ber01-VHDL13_DWOG_031700-2607031700-dsw--0-ia5 03-Jul-2026 18:00:01 3385
ber01-VHDL13_DWOG_040300-2607040300-dsw--0-ia5 04-Jul-2026 03:00:07 4052
ber01-VHDL13_DWOG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 3609
ber01-VHDL13_DWON_021455-2607021455-dsw--0-ia5 02-Jul-2026 14:55:50 4084
ber01-VHDL13_DWON_021630-2607021630-dsw--0-ia5 02-Jul-2026 16:30:57 3853
ber01-VHDL13_DWON_021658-2607021658-dsw--0-ia5 02-Jul-2026 16:58:42 3853
ber01-VHDL13_DWON_030122-2607030122-dsw--0-ia5 03-Jul-2026 01:22:47 4157
ber01-VHDL13_DWON_030234-2607030234-dsw--0-ia5 03-Jul-2026 02:34:16 4157
ber01-VHDL13_DWON_030519-2607030519-dsw--0-ia5 03-Jul-2026 05:20:01 4059
ber01-VHDL13_DWON_030652-2607030652-dsw--0-ia5 03-Jul-2026 06:53:02 4059
ber01-VHDL13_DWON_031124-2607031124-dsw--0-ia5 03-Jul-2026 11:24:22 3977
ber01-VHDL13_DWON_031422-2607031422-dsw--0-ia5 03-Jul-2026 14:22:27 3437
ber01-VHDL13_DWON_031718-2607031718-dsw--0-ia5 03-Jul-2026 17:18:26 3185
ber01-VHDL13_DWON_031719-2607031719-dsw--0-ia5 03-Jul-2026 17:19:12 3185
ber01-VHDL13_DWON_031857-2607031857-dsw--0-ia5 03-Jul-2026 18:57:18 3206
ber01-VHDL13_DWON_032014-2607032014-dsw--0-ia5 03-Jul-2026 20:14:43 3261
ber01-VHDL13_DWON_040119-2607040119-dsw--0-ia5 04-Jul-2026 01:19:06 3579
ber01-VHDL13_DWON_040237-2607040237-dsw--0-ia5 04-Jul-2026 02:37:16 3579
ber01-VHDL13_DWON_040240-2607040240-dsw--0-ia5 04-Jul-2026 02:40:28 3607
ber01-VHDL13_DWON_040522-2607040522-dsw--0-ia5 04-Jul-2026 05:22:51 3927
ber01-VHDL13_DWON_040621-2607040621-dsw--0-ia5 04-Jul-2026 06:21:55 3927
ber01-VHDL13_DWON_040812-2607040812-dsw--0-ia5 04-Jul-2026 08:12:32 3927
ber01-VHDL13_DWON_040855-2607040855-dsw--0-ia5 04-Jul-2026 08:55:53 3927
ber01-VHDL13_DWPG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2223
ber01-VHDL13_DWPG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2480
ber01-VHDL13_DWPH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2464
ber01-VHDL13_DWPH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 2752
ber01-VHDL13_DWSG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 2416
ber01-VHDL13_DWSG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 3112
ber01-VHDL17_DWOG_021200-2607021200-dsw--0-ia5 02-Jul-2026 11:49:06 3114
ber01-VHDL17_DWOG_031200-2607031200-dsw--0-ia5 03-Jul-2026 11:40:11 3173
swis2-VHDL20_DWEG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 859
swis2-VHDL20_DWEG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 739
swis2-VHDL20_DWEG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 740
swis2-VHDL20_DWEG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 839
swis2-VHDL20_DWEG_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:03 1098
swis2-VHDL20_DWEG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 910
swis2-VHDL20_DWEG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 1102
swis2-VHDL20_DWEG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1272
swis2-VHDL20_DWEH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 976
swis2-VHDL20_DWEH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 838
swis2-VHDL20_DWEH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 841
swis2-VHDL20_DWEH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 936
swis2-VHDL20_DWEH_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:03 1026
swis2-VHDL20_DWEH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 853
swis2-VHDL20_DWEH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 963
swis2-VHDL20_DWEH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1127
swis2-VHDL20_DWEI_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 894
swis2-VHDL20_DWEI_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 758
swis2-VHDL20_DWEI_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:01:21 759
swis2-VHDL20_DWEI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 914
swis2-VHDL20_DWEI_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:03 1120
swis2-VHDL20_DWEI_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 929
swis2-VHDL20_DWEI_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:01:22 1151
swis2-VHDL20_DWEI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1213
swis2-VHDL20_DWHG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:45:06 1353
swis2-VHDL20_DWHG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:45:14 1377
swis2-VHDL20_DWHG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 1376
swis2-VHDL20_DWHG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:45:09 1844
swis2-VHDL20_DWHG_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:45:02 2523
swis2-VHDL20_DWHG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:45:10 1547
swis2-VHDL20_DWHG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1539
swis2-VHDL20_DWHG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:45:30 1883
swis2-VHDL20_DWHH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:45:06 1578
swis2-VHDL20_DWHH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:45:14 1447
swis2-VHDL20_DWHH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 1449
swis2-VHDL20_DWHH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:45:09 1733
swis2-VHDL20_DWHH_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:45:02 2701
swis2-VHDL20_DWHH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:45:10 1330
swis2-VHDL20_DWHH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1330
swis2-VHDL20_DWHH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:45:30 1594
swis2-VHDL20_DWLG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1394
swis2-VHDL20_DWLG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 984
swis2-VHDL20_DWLG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 917
swis2-VHDL20_DWLG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1117
swis2-VHDL20_DWLG_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:31:00 1224
swis2-VHDL20_DWLG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 946
swis2-VHDL20_DWLG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1251
swis2-VHDL20_DWLG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1607
swis2-VHDL20_DWLH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1550
swis2-VHDL20_DWLH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1083
swis2-VHDL20_DWLH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 990
swis2-VHDL20_DWLH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1256
swis2-VHDL20_DWLH_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:31:00 1218
swis2-VHDL20_DWLH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 950
swis2-VHDL20_DWLH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1011
swis2-VHDL20_DWLH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1267
swis2-VHDL20_DWLI_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1173
swis2-VHDL20_DWLI_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 865
swis2-VHDL20_DWLI_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 826
swis2-VHDL20_DWLI_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1019
swis2-VHDL20_DWLI_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:31:00 1074
swis2-VHDL20_DWLI_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 846
swis2-VHDL20_DWLI_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1128
swis2-VHDL20_DWLI_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1380
swis2-VHDL20_DWMO_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:05 859
swis2-VHDL20_DWMO_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:06 1000
swis2-VHDL20_DWMO_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:03 897
swis2-VHDL20_DWMO_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 1133
swis2-VHDL20_DWMO_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:09 1257
swis2-VHDL20_DWMO_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 1005
swis2-VHDL20_DWMO_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:06 1021
swis2-VHDL20_DWMO_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 1320
swis2-VHDL20_DWMP_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:05 1143
swis2-VHDL20_DWMP_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:06 1061
swis2-VHDL20_DWMP_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:03 953
swis2-VHDL20_DWMP_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:05 1082
swis2-VHDL20_DWMP_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:09 1256
swis2-VHDL20_DWMP_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:02 1003
swis2-VHDL20_DWMP_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:06 1018
swis2-VHDL20_DWMP_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:02 1227
swis2-VHDL20_DWMP_040800_COR-2607040800-dsw--0-ia5 04-Jul-2026 08:46:04 1282
swis2-VHDL20_DWPG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1415
swis2-VHDL20_DWPG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1044
swis2-VHDL20_DWPG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 979
swis2-VHDL20_DWPG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1126
swis2-VHDL20_DWPG_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:31:00 1093
swis2-VHDL20_DWPG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 863
swis2-VHDL20_DWPG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1063
swis2-VHDL20_DWPG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1200
swis2-VHDL20_DWPH_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:31:03 1878
swis2-VHDL20_DWPH_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:25 1881
swis2-VHDL20_DWPH_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:11 1022
swis2-VHDL20_DWPH_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:21 1193
swis2-VHDL20_DWPH_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:31:00 1381
swis2-VHDL20_DWPH_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:21 1003
swis2-VHDL20_DWPH_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1298
swis2-VHDL20_DWPH_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:22 1536
swis2-VHDL20_DWSG_021800-2607021800-dsw--0-ia5 02-Jul-2026 18:30:01 986
swis2-VHDL20_DWSG_030200-2607030200-dsw--0-ia5 03-Jul-2026 02:30:02 895
swis2-VHDL20_DWSG_030400-2607030400-dsw--0-ia5 03-Jul-2026 05:00:17 830
swis2-VHDL20_DWSG_030800-2607030800-dsw--0-ia5 03-Jul-2026 08:30:01 1050
swis2-VHDL20_DWSG_031800-2607031800-dsw--0-ia5 03-Jul-2026 18:30:03 1261
swis2-VHDL20_DWSG_040200-2607040200-dsw--0-ia5 04-Jul-2026 02:30:10 1053
swis2-VHDL20_DWSG_040400-2607040400-dsw--0-ia5 04-Jul-2026 05:00:16 1038
swis2-VHDL20_DWSG_040800-2607040800-dsw--0-ia5 04-Jul-2026 08:30:10 1405
wst04-VHDL20_DWEG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 234423
wst04-VHDL20_DWEG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 232895
wst04-VHDL20_DWEG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 232750
wst04-VHDL20_DWEG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 233529
wst04-VHDL20_DWEG_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:12 231946
wst04-VHDL20_DWEG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 230766
wst04-VHDL20_DWEG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 231545
wst04-VHDL20_DWEG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 232433
wst04-VHDL20_DWEH_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 231063
wst04-VHDL20_DWEH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 230051
wst04-VHDL20_DWEH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 229897
wst04-VHDL20_DWEH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 230678
wst04-VHDL20_DWEH_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:12 232609
wst04-VHDL20_DWEH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 231879
wst04-VHDL20_DWEH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 232357
wst04-VHDL20_DWEH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:10 233367
wst04-VHDL20_DWEI_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:27 330492
wst04-VHDL20_DWEI_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 329419
wst04-VHDL20_DWEI_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 329274
wst04-VHDL20_DWEI_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:11 329581
wst04-VHDL20_DWEI_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:24 324898
wst04-VHDL20_DWEI_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:13 324349
wst04-VHDL20_DWEI_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 325350
wst04-VHDL20_DWEI_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 326044
wst04-VHDL20_DWHG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:45:12 336999
wst04-VHDL20_DWHG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:45:14 337025
wst04-VHDL20_DWHG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 336832
wst04-VHDL20_DWHG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:45:14 339089
wst04-VHDL20_DWHG_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:45:12 338479
wst04-VHDL20_DWHG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:45:40 334579
wst04-VHDL20_DWHG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 334579
wst04-VHDL20_DWHG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:45:30 336186
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wst04-VHDL20_DWHH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:45:14 323726
wst04-VHDL20_DWHH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 227512
wst04-VHDL20_DWHH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:45:14 323985
wst04-VHDL20_DWHH_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:45:12 326191
wst04-VHDL20_DWHH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:45:40 323285
wst04-VHDL20_DWHH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 226005
wst04-VHDL20_DWHH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:45:30 323358
wst04-VHDL20_DWLG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:20 326311
wst04-VHDL20_DWLG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 325790
wst04-VHDL20_DWLG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:41 325505
wst04-VHDL20_DWLG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 326230
wst04-VHDL20_DWLG_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:31:29 333694
wst04-VHDL20_DWLG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 333500
wst04-VHDL20_DWLG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 334136
wst04-VHDL20_DWLG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 335337
wst04-VHDL20_DWLH_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:20 327078
wst04-VHDL20_DWLH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:27 326408
wst04-VHDL20_DWLH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:41 326120
wst04-VHDL20_DWLH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:48 326458
wst04-VHDL20_DWLH_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:31:22 331827
wst04-VHDL20_DWLH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 331620
wst04-VHDL20_DWLH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 331342
wst04-VHDL20_DWLH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 332515
wst04-VHDL20_DWLI_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:26 328799
wst04-VHDL20_DWLI_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 328363
wst04-VHDL20_DWLI_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:41 328309
wst04-VHDL20_DWLI_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 373656
wst04-VHDL20_DWLI_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:31:22 332108
wst04-VHDL20_DWLI_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:28 331926
wst04-VHDL20_DWLI_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:42 332677
wst04-VHDL20_DWLI_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 377661
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wst04-VHDL20_DWMO_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:16 439037
wst04-VHDL20_DWMO_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 438474
wst04-VHDL20_DWMO_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:17 438668
wst04-VHDL20_DWMO_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:24 342054
wst04-VHDL20_DWMO_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:16 444062
wst04-VHDL20_DWMO_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 443945
wst04-VHDL20_DWMO_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:16 444449
wst04-VHDL20_DWMP_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:27 458306
wst04-VHDL20_DWMP_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:16 561283
wst04-VHDL20_DWMP_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:17 560297
wst04-VHDL20_DWMP_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:21 457460
wst04-VHDL20_DWMP_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:24 465969
wst04-VHDL20_DWMP_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:16 572779
wst04-VHDL20_DWMP_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:16 572584
wst04-VHDL20_DWMP_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:22 465188
wst04-VHDL20_DWPG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:20 331889
wst04-VHDL20_DWPG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 234813
wst04-VHDL20_DWPG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:31 330922
wst04-VHDL20_DWPG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 375696
wst04-VHDL20_DWPG_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:31:22 339545
wst04-VHDL20_DWPG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 237774
wst04-VHDL20_DWPG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:30 339201
wst04-VHDL20_DWPG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 384331
wst04-VHDL20_DWPH_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:31:20 237780
wst04-VHDL20_DWPH_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:25 237695
wst04-VHDL20_DWPH_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:31 235410
wst04-VHDL20_DWPH_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:41 235663
wst04-VHDL20_DWPH_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:31:22 237877
wst04-VHDL20_DWPH_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:21 236982
wst04-VHDL20_DWPH_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:30 237327
wst04-VHDL20_DWPH_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:49 237938
wst04-VHDL20_DWSG_021800-2607021800-omedes--0.pdf 02-Jul-2026 18:30:21 337171
wst04-VHDL20_DWSG_030200-2607030200-omedes--0.pdf 03-Jul-2026 02:30:12 336924
wst04-VHDL20_DWSG_030400-2607030400-omedes--0.pdf 03-Jul-2026 05:00:11 336006
wst04-VHDL20_DWSG_030800-2607030800-omedes--0.pdf 03-Jul-2026 08:30:17 336814
wst04-VHDL20_DWSG_031800-2607031800-omedes--0.pdf 03-Jul-2026 18:30:24 333735
wst04-VHDL20_DWSG_040200-2607040200-omedes--0.pdf 04-Jul-2026 02:30:10 332685
wst04-VHDL20_DWSG_040400-2607040400-omedes--0.pdf 04-Jul-2026 05:00:12 333193
wst04-VHDL20_DWSG_040800-2607040800-omedes--0.pdf 04-Jul-2026 08:30:22 334090