Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Oct-2026 13:07:39 4839
FPDL13_DWMZ_300600 30-Sep-2026 13:46:52 4474
SXDL31_DWAV_010800 01-Oct-2026 07:54:05 8700
SXDL31_DWAV_011800 01-Oct-2026 16:34:40 6216
SXDL31_DWAV_300800 30-Sep-2026 08:12:14 8838
SXDL31_DWAV_301800 30-Sep-2026 16:53:18 10303
SXDL31_DWAV_LATEST 01-Oct-2026 16:34:40 6216
SXDL33_DWAV_010000 01-Oct-2026 10:21:14 13866
SXDL33_DWAV_300000 30-Sep-2026 10:11:54 10644
SXDL33_DWAV_LATEST 01-Oct-2026 10:21:14 13866
ber01-FWDL39_DWMS_011200-2610011200-dsw--0-ia5 01-Oct-2026 11:34:50 1893
ber01-FWDL39_DWMS_301200-2609301200-dsw--0-ia5 30-Sep-2026 10:53:48 1445
ber01-VHDL13_DWEG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:28:24 3389
ber01-VHDL13_DWEG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:28:18 3405
ber01-VHDL13_DWEG_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 3424
ber01-VHDL13_DWEH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:28:18 3236
ber01-VHDL13_DWEH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:28:24 3682
ber01-VHDL13_DWEH_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 3689
ber01-VHDL13_DWEI_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:28:14 3024
ber01-VHDL13_DWEI_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:28:18 3529
ber01-VHDL13_DWEI_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 3515
ber01-VHDL13_DWHG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 3201
ber01-VHDL13_DWHG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 2905
ber01-VHDL13_DWHH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 3290
ber01-VHDL13_DWHH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 3082
ber01-VHDL13_DWLG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 2818
ber01-VHDL13_DWLG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 2129
ber01-VHDL13_DWLH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 2776
ber01-VHDL13_DWLH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 2037
ber01-VHDL13_DWLI_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 2978
ber01-VHDL13_DWLI_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 2056
ber01-VHDL13_DWMO_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 3184
ber01-VHDL13_DWMO_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 3169
ber01-VHDL13_DWMP_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 3458
ber01-VHDL13_DWMP_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 3097
ber01-VHDL13_DWOG_010300-2610010300-dsw--0-ia5 01-Oct-2026 03:02:25 4467
ber01-VHDL13_DWOG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 4289
ber01-VHDL13_DWOG_291700-2609291700-dsw--0-ia5 29-Sep-2026 18:00:04 3153
ber01-VHDL13_DWOG_300300-2609300300-dsw--0-ia5 30-Sep-2026 03:00:21 3544
ber01-VHDL13_DWOG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 3753
ber01-VHDL13_DWOG_301700-2609301700-dsw--0-ia5 30-Sep-2026 18:00:03 3825
ber01-VHDL13_DWON_010239-2610010239-dsw--0-ia5 01-Oct-2026 02:39:33 3742
ber01-VHDL13_DWON_010525-2610010525-dsw--0-ia5 01-Oct-2026 05:25:34 3556
ber01-VHDL13_DWON_010600-2610010600-dsw--0-ia5 01-Oct-2026 06:00:09 3953
ber01-VHDL13_DWON_010640-2610010640-dsw--0-ia5 01-Oct-2026 06:41:15 3797
ber01-VHDL13_DWON_010904-2610010904-dsw--0-ia5 01-Oct-2026 09:04:18 3797
ber01-VHDL13_DWON_011534-2610011534-dsw--0-ia5 01-Oct-2026 15:34:53 3306
ber01-VHDL13_DWON_011657-2610011657-dsw--0-ia5 01-Oct-2026 16:57:48 3302
ber01-VHDL13_DWON_300115-2609300115-dsw--0-ia5 30-Sep-2026 01:15:23 3849
ber01-VHDL13_DWON_300244-2609300244-dsw--0-ia5 30-Sep-2026 02:46:12 3849
ber01-VHDL13_DWON_300245-2609300245-dsw--0-ia5 30-Sep-2026 02:46:12 3849
ber01-VHDL13_DWON_300529-2609300529-dsw--0-ia5 30-Sep-2026 05:29:54 3788
ber01-VHDL13_DWON_300603-2609300603-dsw--0-ia5 30-Sep-2026 06:03:05 4153
ber01-VHDL13_DWON_301447-2609301447-dsw--0-ia5 30-Sep-2026 14:48:00 4180
ber01-VHDL13_DWON_301658-2609301658-dsw--0-ia5 30-Sep-2026 16:58:29 3652
ber01-VHDL13_DWON_302014-2609302014-dsw--0-ia5 30-Sep-2026 20:14:54 3648
ber01-VHDL13_DWPG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 2670
ber01-VHDL13_DWPG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1893
ber01-VHDL13_DWPH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 2709
ber01-VHDL13_DWPH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 2137
ber01-VHDL13_DWSG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:02 3391
ber01-VHDL13_DWSG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 3040
ber01-VHDL17_DWOG_011200-2610011200-dsw--0-ia5 01-Oct-2026 11:57:49 3223
ber01-VHDL17_DWOG_301200-2609301200-dsw--0-ia5 30-Sep-2026 11:44:31 4081
swis2-VHDL20_DWEG_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:03 1400
swis2-VHDL20_DWEG_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:01:18 1407
swis2-VHDL20_DWEG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 1714
swis2-VHDL20_DWEG_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:05 1217
swis2-VHDL20_DWEG_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1077
swis2-VHDL20_DWEG_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:01:19 1181
swis2-VHDL20_DWEG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1642
swis2-VHDL20_DWEG_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 1685
swis2-VHDL20_DWEG_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1535
swis2-VHDL20_DWEH_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:03 1423
swis2-VHDL20_DWEH_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:01:18 1424
swis2-VHDL20_DWEH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 1596
swis2-VHDL20_DWEH_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:05 1482
swis2-VHDL20_DWEH_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1316
swis2-VHDL20_DWEH_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:01:19 1420
swis2-VHDL20_DWEH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1794
swis2-VHDL20_DWEH_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 1826
swis2-VHDL20_DWEH_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1775
swis2-VHDL20_DWEI_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:03 1364
swis2-VHDL20_DWEI_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:01:18 1347
swis2-VHDL20_DWEI_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:08 1639
swis2-VHDL20_DWEI_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:05 1477
swis2-VHDL20_DWEI_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1320
swis2-VHDL20_DWEI_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:01:19 1424
swis2-VHDL20_DWEI_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1814
swis2-VHDL20_DWEI_300800_COR-2609300800-dsw--0-ia5 30-Sep-2026 08:46:44 1845
swis2-VHDL20_DWEI_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1659
swis2-VHDL20_DWHG_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:45:17 1545
swis2-VHDL20_DWHG_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1542
swis2-VHDL20_DWHG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:45:16 1625
swis2-VHDL20_DWHG_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:45:17 1636
swis2-VHDL20_DWHG_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:46:20 1411
swis2-VHDL20_DWHG_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:18 1408
swis2-VHDL20_DWHG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:45:27 1702
swis2-VHDL20_DWHG_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:45:20 1609
swis2-VHDL20_DWHH_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:45:17 1524
swis2-VHDL20_DWHH_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1524
swis2-VHDL20_DWHH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:45:16 1613
swis2-VHDL20_DWHH_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:45:17 1630
swis2-VHDL20_DWHH_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:46:20 1402
swis2-VHDL20_DWHH_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:18 1402
swis2-VHDL20_DWHH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:45:27 1652
swis2-VHDL20_DWHH_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:45:20 1610
swis2-VHDL20_DWLG_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:24 893
swis2-VHDL20_DWLG_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1072
swis2-VHDL20_DWLG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:38 1309
swis2-VHDL20_DWLG_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:31:10 1015
swis2-VHDL20_DWLG_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:34 930
swis2-VHDL20_DWLG_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:14 825
swis2-VHDL20_DWLG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:28 954
swis2-VHDL20_DWLG_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:31:02 914
swis2-VHDL20_DWLH_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:24 897
swis2-VHDL20_DWLH_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1055
swis2-VHDL20_DWLH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:38 1242
swis2-VHDL20_DWLH_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:31:10 900
swis2-VHDL20_DWLH_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:34 812
swis2-VHDL20_DWLH_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:14 790
swis2-VHDL20_DWLH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:28 917
swis2-VHDL20_DWLH_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:31:02 915
swis2-VHDL20_DWLI_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:24 1100
swis2-VHDL20_DWLI_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1270
swis2-VHDL20_DWLI_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:38 1402
swis2-VHDL20_DWLI_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:31:10 894
swis2-VHDL20_DWLI_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:34 807
swis2-VHDL20_DWLI_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:14 785
swis2-VHDL20_DWLI_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:28 914
swis2-VHDL20_DWLI_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:31:02 912
swis2-VHDL20_DWMO_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:05 1565
swis2-VHDL20_DWMO_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:08 1344
swis2-VHDL20_DWMO_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 1407
swis2-VHDL20_DWMO_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:07 1230
swis2-VHDL20_DWMO_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1334
swis2-VHDL20_DWMO_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:04 1340
swis2-VHDL20_DWMO_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1402
swis2-VHDL20_DWMO_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1477
swis2-VHDL20_DWMP_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:05 1615
swis2-VHDL20_DWMP_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:08 1527
swis2-VHDL20_DWMP_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:10 1777
swis2-VHDL20_DWMP_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:07 1363
swis2-VHDL20_DWMP_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1380
swis2-VHDL20_DWMP_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:04 1385
swis2-VHDL20_DWMP_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1549
swis2-VHDL20_DWMP_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1516
swis2-VHDL20_DWPG_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:24 908
swis2-VHDL20_DWPG_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1093
swis2-VHDL20_DWPG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:38 1278
swis2-VHDL20_DWPG_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:31:10 910
swis2-VHDL20_DWPG_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:34 823
swis2-VHDL20_DWPG_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:14 801
swis2-VHDL20_DWPG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:28 926
swis2-VHDL20_DWPG_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:31:02 932
swis2-VHDL20_DWPH_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:24 917
swis2-VHDL20_DWPH_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:14 1076
swis2-VHDL20_DWPH_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:38 1261
swis2-VHDL20_DWPH_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:31:10 912
swis2-VHDL20_DWPH_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:34 824
swis2-VHDL20_DWPH_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:14 802
swis2-VHDL20_DWPH_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:28 928
swis2-VHDL20_DWPH_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:31:02 938
swis2-VHDL20_DWSG_010200-2610010200-dsw--0-ia5 01-Oct-2026 02:30:03 1575
swis2-VHDL20_DWSG_010400-2610010400-dsw--0-ia5 01-Oct-2026 05:00:18 1718
swis2-VHDL20_DWSG_010800-2610010800-dsw--0-ia5 01-Oct-2026 08:30:02 1848
swis2-VHDL20_DWSG_291800-2609291800-dsw--0-ia5 29-Sep-2026 18:30:05 1227
swis2-VHDL20_DWSG_300200-2609300200-dsw--0-ia5 30-Sep-2026 02:30:04 1179
swis2-VHDL20_DWSG_300400-2609300400-dsw--0-ia5 30-Sep-2026 05:00:18 1306
swis2-VHDL20_DWSG_300800-2609300800-dsw--0-ia5 30-Sep-2026 08:30:06 1372
swis2-VHDL20_DWSG_301800-2609301800-dsw--0-ia5 30-Sep-2026 18:30:13 1351
wst04-VHDL20_DWEG_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:21 242089
wst04-VHDL20_DWEG_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:14 241953
wst04-VHDL20_DWEG_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:14 242917
wst04-VHDL20_DWEG_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:13 242239
wst04-VHDL20_DWEG_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:17 241879
wst04-VHDL20_DWEG_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:14 242118
wst04-VHDL20_DWEG_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 242587
wst04-VHDL20_DWEG_300800_COR-2609300800-omedes-..> 30-Sep-2026 08:46:44 242558
wst04-VHDL20_DWEG_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:19 242858
wst04-VHDL20_DWEH_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:21 235618
wst04-VHDL20_DWEH_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:14 235434
wst04-VHDL20_DWEH_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:14 236076
wst04-VHDL20_DWEH_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:13 235656
wst04-VHDL20_DWEH_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:17 235579
wst04-VHDL20_DWEH_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:14 235735
wst04-VHDL20_DWEH_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 236135
wst04-VHDL20_DWEH_300800_COR-2609300800-omedes-..> 30-Sep-2026 08:46:44 236038
wst04-VHDL20_DWEH_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:21 235912
wst04-VHDL20_DWEI_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 348476
wst04-VHDL20_DWEI_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:18 348169
wst04-VHDL20_DWEI_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:14 349330
wst04-VHDL20_DWEI_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:34 348476
wst04-VHDL20_DWEI_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:17 348298
wst04-VHDL20_DWEI_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:14 348482
wst04-VHDL20_DWEI_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 349153
wst04-VHDL20_DWEI_300800_COR-2609300800-omedes-..> 30-Sep-2026 08:46:44 349084
wst04-VHDL20_DWEI_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:21 349462
wst04-VHDL20_DWHG_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:45:17 349218
wst04-VHDL20_DWHG_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:24 349011
wst04-VHDL20_DWHG_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:45:16 349823
wst04-VHDL20_DWHG_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:45:25 350299
wst04-VHDL20_DWHG_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:46:20 348712
wst04-VHDL20_DWHG_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:18 348527
wst04-VHDL20_DWHG_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:45:27 350706
wst04-VHDL20_DWHG_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:45:31 349604
wst04-VHDL20_DWHH_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:45:17 334973
wst04-VHDL20_DWHH_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:18 230898
wst04-VHDL20_DWHH_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:45:16 334980
wst04-VHDL20_DWHH_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:45:25 335701
wst04-VHDL20_DWHH_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:46:20 334447
wst04-VHDL20_DWHH_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:18 230373
wst04-VHDL20_DWHH_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:45:27 335777
wst04-VHDL20_DWHH_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:45:31 335065
wst04-VHDL20_DWLG_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 333020
wst04-VHDL20_DWLG_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:44 332947
wst04-VHDL20_DWLG_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:49 333554
wst04-VHDL20_DWLG_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:31:23 333464
wst04-VHDL20_DWLG_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:34 333220
wst04-VHDL20_DWLG_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:44 333181
wst04-VHDL20_DWLG_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:48 333513
wst04-VHDL20_DWLG_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:31:39 333250
wst04-VHDL20_DWLH_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 336985
wst04-VHDL20_DWLH_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:44 336933
wst04-VHDL20_DWLH_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:49 337538
wst04-VHDL20_DWLH_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:31:23 336869
wst04-VHDL20_DWLH_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:36 336765
wst04-VHDL20_DWLH_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:44 337058
wst04-VHDL20_DWLH_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:48 337215
wst04-VHDL20_DWLH_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:31:39 337179
wst04-VHDL20_DWLI_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:38 338953
wst04-VHDL20_DWLI_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:44 338877
wst04-VHDL20_DWLI_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:31:00 383687
wst04-VHDL20_DWLI_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:31:27 337925
wst04-VHDL20_DWLI_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:34 337838
wst04-VHDL20_DWLI_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:44 338102
wst04-VHDL20_DWLI_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:48 382901
wst04-VHDL20_DWLI_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:31:39 338292
wst04-VHDL20_DWMO_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 456314
wst04-VHDL20_DWMO_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:14 456242
wst04-VHDL20_DWMO_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:38 456331
wst04-VHDL20_DWMO_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:34 355561
wst04-VHDL20_DWMO_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:19 456012
wst04-VHDL20_DWMO_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:18 456166
wst04-VHDL20_DWMO_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 456011
wst04-VHDL20_DWMO_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:21 354378
wst04-VHDL20_DWMP_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 563081
wst04-VHDL20_DWMP_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:18 563956
wst04-VHDL20_DWMP_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:38 461792
wst04-VHDL20_DWMP_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:34 462528
wst04-VHDL20_DWMP_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:19 562532
wst04-VHDL20_DWMP_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:18 562669
wst04-VHDL20_DWMP_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 461331
wst04-VHDL20_DWMP_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:29 461279
wst04-VHDL20_DWPG_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 243857
wst04-VHDL20_DWPG_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:34 347451
wst04-VHDL20_DWPG_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:31:00 392567
wst04-VHDL20_DWPG_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:31:23 347289
wst04-VHDL20_DWPG_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:34 243631
wst04-VHDL20_DWPG_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:34 347565
wst04-VHDL20_DWPG_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:48 392223
wst04-VHDL20_DWPG_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:31:39 347619
wst04-VHDL20_DWPH_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:24 242331
wst04-VHDL20_DWPH_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:34 242327
wst04-VHDL20_DWPH_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:49 242836
wst04-VHDL20_DWPH_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:31:23 242167
wst04-VHDL20_DWPH_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:34 242096
wst04-VHDL20_DWPH_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:34 242443
wst04-VHDL20_DWPH_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:48 242519
wst04-VHDL20_DWPH_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:31:39 242520
wst04-VHDL20_DWSG_010200-2610010200-omedes--0.pdf 01-Oct-2026 02:30:21 348153
wst04-VHDL20_DWSG_010400-2610010400-omedes--0.pdf 01-Oct-2026 05:00:18 348947
wst04-VHDL20_DWSG_010800-2610010800-omedes--0.pdf 01-Oct-2026 08:30:18 349143
wst04-VHDL20_DWSG_291800-2609291800-omedes--0.pdf 29-Sep-2026 18:30:13 348179
wst04-VHDL20_DWSG_300200-2609300200-omedes--0.pdf 30-Sep-2026 02:30:17 348029
wst04-VHDL20_DWSG_300400-2609300400-omedes--0.pdf 30-Sep-2026 05:00:14 348754
wst04-VHDL20_DWSG_300800-2609300800-omedes--0.pdf 30-Sep-2026 08:30:28 348863
wst04-VHDL20_DWSG_301800-2609301800-omedes--0.pdf 30-Sep-2026 18:30:19 348775