Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Oct-2026 13:40:30 4504
FPDL13_DWMZ_050600 05-Oct-2026 11:26:03 2894
SXDL31_DWAV_041800 04-Oct-2026 15:23:04 6630
SXDL31_DWAV_050800 05-Oct-2026 07:26:09 7200
SXDL31_DWAV_051800 05-Oct-2026 16:28:07 8164
SXDL31_DWAV_060800 06-Oct-2026 07:40:00 12622
SXDL31_DWAV_LATEST 06-Oct-2026 07:40:00 12622
SXDL33_DWAV_040000 04-Oct-2026 09:49:37 5929
SXDL33_DWAV_050000 05-Oct-2026 10:21:54 8314
SXDL33_DWAV_LATEST 05-Oct-2026 10:21:54 8314
ber01-FWDL39_DWMS_041200-2610041200-dsw--0-ia5 04-Oct-2026 11:23:13 1332
ber01-FWDL39_DWMS_051200-2610051200-dsw--0-ia5 05-Oct-2026 10:15:05 1503
ber01-VHDL13_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:14 2420
ber01-VHDL13_DWEG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:24 2657
ber01-VHDL13_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:18 2507
ber01-VHDL13_DWEH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:24 2910
ber01-VHDL13_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:28:24 2519
ber01-VHDL13_DWEI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:28:18 2783
ber01-VHDL13_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2940
ber01-VHDL13_DWHG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 2993
ber01-VHDL13_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 2848
ber01-VHDL13_DWHH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 2945
ber01-VHDL13_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1894
ber01-VHDL13_DWLG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2258
ber01-VHDL13_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2072
ber01-VHDL13_DWLH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2369
ber01-VHDL13_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1945
ber01-VHDL13_DWLI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2246
ber01-VHDL13_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 2717
ber01-VHDL13_DWMO_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2425
ber01-VHDL13_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 3018
ber01-VHDL13_DWMP_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 3002
ber01-VHDL13_DWOG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:12 3554
ber01-VHDL13_DWOG_041700-2610041700-dsw--0-ia5 04-Oct-2026 18:00:05 3101
ber01-VHDL13_DWOG_050300-2610050300-dsw--0-ia5 05-Oct-2026 03:00:07 4019
ber01-VHDL13_DWOG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:09 3687
ber01-VHDL13_DWOG_051700-2610051700-dsw--0-ia5 05-Oct-2026 18:00:05 3302
ber01-VHDL13_DWOG_060300-2610060300-dsw--0-ia5 06-Oct-2026 03:01:08 3440
ber01-VHDL13_DWON_040802-2610040802-dsw--0-ia5 04-Oct-2026 08:03:13 4016
ber01-VHDL13_DWON_041455-2610041455-dsw--0-ia5 04-Oct-2026 14:55:45 3823
ber01-VHDL13_DWON_041625-2610041625-dsw--0-ia5 04-Oct-2026 16:25:34 3227
ber01-VHDL13_DWON_041814-2610041814-dsw--0-ia5 04-Oct-2026 18:14:49 3460
ber01-VHDL13_DWON_042155-2610042155-dsw--0-ia5 04-Oct-2026 21:56:14 3479
ber01-VHDL13_DWON_050000-2610050000-dsw--0-ia5 05-Oct-2026 00:00:30 4148
ber01-VHDL13_DWON_050137-2610050137-dsw--0-ia5 05-Oct-2026 01:38:06 4094
ber01-VHDL13_DWON_050245-2610050245-dsw--0-ia5 05-Oct-2026 02:46:58 4094
ber01-VHDL13_DWON_050526-2610050526-dsw--0-ia5 05-Oct-2026 05:26:13 3433
ber01-VHDL13_DWON_050555-2610050555-dsw--0-ia5 05-Oct-2026 05:56:05 3592
ber01-VHDL13_DWON_050753-2610050753-dsw--0-ia5 05-Oct-2026 07:53:25 3756
ber01-VHDL13_DWON_051408-2610051408-dsw--0-ia5 05-Oct-2026 14:08:34 3695
ber01-VHDL13_DWON_051648-2610051648-dsw--0-ia5 05-Oct-2026 16:48:28 3600
ber01-VHDL13_DWON_052142-2610052142-dsw--0-ia5 05-Oct-2026 21:43:16 3343
ber01-VHDL13_DWON_060141-2610060141-dsw--0-ia5 06-Oct-2026 01:41:38 3409
ber01-VHDL13_DWON_060241-2610060241-dsw--0-ia5 06-Oct-2026 02:43:41 3409
ber01-VHDL13_DWON_060507-2610060507-dsw--0-ia5 06-Oct-2026 05:07:18 3934
ber01-VHDL13_DWON_060550-2610060550-dsw--0-ia5 06-Oct-2026 05:50:11 3934
ber01-VHDL13_DWON_060755-2610060755-dsw--0-ia5 06-Oct-2026 07:55:58 3894
ber01-VHDL13_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1940
ber01-VHDL13_DWPG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2305
ber01-VHDL13_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1995
ber01-VHDL13_DWPH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2268
ber01-VHDL13_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 3036
ber01-VHDL13_DWSG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 2685
ber01-VHDL17_DWOG_041200-2610041200-dsw--0-ia5 04-Oct-2026 11:22:03 2932
ber01-VHDL17_DWOG_051200-2610051200-dsw--0-ia5 05-Oct-2026 12:00:18 2449
swis2-VHDL20_DWEG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1052
swis2-VHDL20_DWEG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1326
swis2-VHDL20_DWEG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 838
swis2-VHDL20_DWEG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 824
swis2-VHDL20_DWEG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1349
swis2-VHDL20_DWEG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2373
swis2-VHDL20_DWEG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1659
swis2-VHDL20_DWEG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1621
swis2-VHDL20_DWEH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1063
swis2-VHDL20_DWEH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1403
swis2-VHDL20_DWEH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 845
swis2-VHDL20_DWEH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 838
swis2-VHDL20_DWEH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1471
swis2-VHDL20_DWEH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2552
swis2-VHDL20_DWEH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1689
swis2-VHDL20_DWEH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1682
swis2-VHDL20_DWEI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1080
swis2-VHDL20_DWEI_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1320
swis2-VHDL20_DWEI_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 860
swis2-VHDL20_DWEI_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:01:19 846
swis2-VHDL20_DWEI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1372
swis2-VHDL20_DWEI_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 2459
swis2-VHDL20_DWEI_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1758
swis2-VHDL20_DWEI_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:01:24 1752
swis2-VHDL20_DWHG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1370
swis2-VHDL20_DWHG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:45:18 1495
swis2-VHDL20_DWHG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:45:44 1204
swis2-VHDL20_DWHG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1189
swis2-VHDL20_DWHG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:45:17 1441
swis2-VHDL20_DWHG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:45:13 1617
swis2-VHDL20_DWHG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:45:35 1026
swis2-VHDL20_DWHG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1023
swis2-VHDL20_DWHH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:45:45 1371
swis2-VHDL20_DWHH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:45:18 1741
swis2-VHDL20_DWHH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:45:44 1396
swis2-VHDL20_DWHH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1366
swis2-VHDL20_DWHH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:45:17 1547
swis2-VHDL20_DWHH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:45:13 1557
swis2-VHDL20_DWHH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:45:35 1080
swis2-VHDL20_DWHH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1080
swis2-VHDL20_DWLG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 810
swis2-VHDL20_DWLG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1104
swis2-VHDL20_DWLG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 797
swis2-VHDL20_DWLG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 877
swis2-VHDL20_DWLG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 972
swis2-VHDL20_DWLG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1047
swis2-VHDL20_DWLG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 760
swis2-VHDL20_DWLG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 757
swis2-VHDL20_DWLH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 817
swis2-VHDL20_DWLH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1124
swis2-VHDL20_DWLH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 790
swis2-VHDL20_DWLH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 884
swis2-VHDL20_DWLH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 1016
swis2-VHDL20_DWLH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1084
swis2-VHDL20_DWLH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 767
swis2-VHDL20_DWLH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 895
swis2-VHDL20_DWLI_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 812
swis2-VHDL20_DWLI_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1079
swis2-VHDL20_DWLI_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 785
swis2-VHDL20_DWLI_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 879
swis2-VHDL20_DWLI_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 977
swis2-VHDL20_DWLI_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1066
swis2-VHDL20_DWLI_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 762
swis2-VHDL20_DWLI_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 759
swis2-VHDL20_DWMO_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1234
swis2-VHDL20_DWMO_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1202
swis2-VHDL20_DWMO_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 969
swis2-VHDL20_DWMO_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:03 976
swis2-VHDL20_DWMO_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1145
swis2-VHDL20_DWMO_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1119
swis2-VHDL20_DWMO_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:03 820
swis2-VHDL20_DWMO_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:03 974
swis2-VHDL20_DWMP_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:05 1417
swis2-VHDL20_DWMP_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1546
swis2-VHDL20_DWMP_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 1278
swis2-VHDL20_DWMP_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:03 1272
swis2-VHDL20_DWMP_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1422
swis2-VHDL20_DWMP_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1398
swis2-VHDL20_DWMP_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:03 1066
swis2-VHDL20_DWMP_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:03 1220
swis2-VHDL20_DWPG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 828
swis2-VHDL20_DWPG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1050
swis2-VHDL20_DWPG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 815
swis2-VHDL20_DWPG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 888
swis2-VHDL20_DWPG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 961
swis2-VHDL20_DWPG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 1034
swis2-VHDL20_DWPG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 765
swis2-VHDL20_DWPG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 762
swis2-VHDL20_DWPH_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:23 803
swis2-VHDL20_DWPH_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:31:11 1138
swis2-VHDL20_DWPH_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:28 788
swis2-VHDL20_DWPH_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:13 878
swis2-VHDL20_DWPH_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:31 962
swis2-VHDL20_DWPH_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:31:14 987
swis2-VHDL20_DWPH_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:26 764
swis2-VHDL20_DWPH_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 743
swis2-VHDL20_DWSG_040800-2610040800-dsw--0-ia5 04-Oct-2026 08:30:15 1308
swis2-VHDL20_DWSG_041800-2610041800-dsw--0-ia5 04-Oct-2026 18:30:04 1399
swis2-VHDL20_DWSG_050200-2610050200-dsw--0-ia5 05-Oct-2026 02:30:03 1234
swis2-VHDL20_DWSG_050400-2610050400-dsw--0-ia5 05-Oct-2026 05:00:19 1196
swis2-VHDL20_DWSG_050800-2610050800-dsw--0-ia5 05-Oct-2026 08:30:03 1050
swis2-VHDL20_DWSG_051800-2610051800-dsw--0-ia5 05-Oct-2026 18:30:03 1484
swis2-VHDL20_DWSG_060200-2610060200-dsw--0-ia5 06-Oct-2026 02:30:05 1355
swis2-VHDL20_DWSG_060400-2610060400-dsw--0-ia5 06-Oct-2026 05:00:19 1494
wst04-VHDL20_DWEG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 242050
wst04-VHDL20_DWEG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:17 243049
wst04-VHDL20_DWEG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 240241
wst04-VHDL20_DWEG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 240056
wst04-VHDL20_DWEG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:13 242652
wst04-VHDL20_DWEG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 244579
wst04-VHDL20_DWEG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 242573
wst04-VHDL20_DWEG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 242180
wst04-VHDL20_DWEH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:15 235539
wst04-VHDL20_DWEH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:17 236088
wst04-VHDL20_DWEH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 233400
wst04-VHDL20_DWEH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 233517
wst04-VHDL20_DWEH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:13 236283
wst04-VHDL20_DWEH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 237770
wst04-VHDL20_DWEH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 236147
wst04-VHDL20_DWEH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 235660
wst04-VHDL20_DWEI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 347746
wst04-VHDL20_DWEI_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 349478
wst04-VHDL20_DWEI_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 346552
wst04-VHDL20_DWEI_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 346301
wst04-VHDL20_DWEI_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:18 349042
wst04-VHDL20_DWEI_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 351104
wst04-VHDL20_DWEI_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 349603
wst04-VHDL20_DWEI_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 349141
wst04-VHDL20_DWHG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 348375
wst04-VHDL20_DWHG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:45:18 348002
wst04-VHDL20_DWHG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:45:45 347391
wst04-VHDL20_DWHG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:23 347136
wst04-VHDL20_DWHG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:45:20 348384
wst04-VHDL20_DWHG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:45:15 349417
wst04-VHDL20_DWHG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:45:35 347298
wst04-VHDL20_DWHG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:23 347080
wst04-VHDL20_DWHH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:46:08 333809
wst04-VHDL20_DWHH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:45:18 335402
wst04-VHDL20_DWHH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:45:45 334213
wst04-VHDL20_DWHH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 230135
wst04-VHDL20_DWHH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:45:20 334593
wst04-VHDL20_DWHH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:45:15 334584
wst04-VHDL20_DWHH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:45:35 332742
wst04-VHDL20_DWHH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 228589
wst04-VHDL20_DWLG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 332978
wst04-VHDL20_DWLG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 333949
wst04-VHDL20_DWLG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 333449
wst04-VHDL20_DWLG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 332608
wst04-VHDL20_DWLG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 333553
wst04-VHDL20_DWLG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:29 333565
wst04-VHDL20_DWLG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 333371
wst04-VHDL20_DWLG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 332176
wst04-VHDL20_DWLH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 337007
wst04-VHDL20_DWLH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 337743
wst04-VHDL20_DWLH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 337432
wst04-VHDL20_DWLH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 336623
wst04-VHDL20_DWLH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:53 337601
wst04-VHDL20_DWLH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:29 337966
wst04-VHDL20_DWLH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 337376
wst04-VHDL20_DWLH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 337136
wst04-VHDL20_DWLI_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 382640
wst04-VHDL20_DWLI_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 338809
wst04-VHDL20_DWLI_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 338508
wst04-VHDL20_DWLI_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:43 337672
wst04-VHDL20_DWLI_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 383256
wst04-VHDL20_DWLI_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 338693
wst04-VHDL20_DWLI_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:28 338456
wst04-VHDL20_DWLI_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:44 337253
wst04-VHDL20_DWMO_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:19 454807
wst04-VHDL20_DWMO_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 353087
wst04-VHDL20_DWMO_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:20 455069
wst04-VHDL20_DWMO_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 454928
wst04-VHDL20_DWMO_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:31 455136
wst04-VHDL20_DWMO_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 352416
wst04-VHDL20_DWMO_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 454923
wst04-VHDL20_DWMO_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 455174
wst04-VHDL20_DWMP_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 460720
wst04-VHDL20_DWMP_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:36 460898
wst04-VHDL20_DWMP_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:20 562348
wst04-VHDL20_DWMP_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:19 562592
wst04-VHDL20_DWMP_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:31 461081
wst04-VHDL20_DWMP_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:34 459971
wst04-VHDL20_DWMP_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 562162
wst04-VHDL20_DWMP_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:19 562241
wst04-VHDL20_DWPG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 391996
wst04-VHDL20_DWPG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 347868
wst04-VHDL20_DWPG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 244341
wst04-VHDL20_DWPG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:33 346840
wst04-VHDL20_DWPG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 391815
wst04-VHDL20_DWPG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 348044
wst04-VHDL20_DWPG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:28 244259
wst04-VHDL20_DWPG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:33 346713
wst04-VHDL20_DWPH_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:56 242279
wst04-VHDL20_DWPH_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:31:28 243716
wst04-VHDL20_DWPH_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:28 242998
wst04-VHDL20_DWPH_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:33 241724
wst04-VHDL20_DWPH_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:43 243097
wst04-VHDL20_DWPH_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:31:24 243301
wst04-VHDL20_DWPH_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:26 242733
wst04-VHDL20_DWPH_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:33 241541
wst04-VHDL20_DWSG_040800-2610040800-omedes--0.pdf 04-Oct-2026 08:30:23 347632
wst04-VHDL20_DWSG_041800-2610041800-omedes--0.pdf 04-Oct-2026 18:30:20 347520
wst04-VHDL20_DWSG_050200-2610050200-omedes--0.pdf 05-Oct-2026 02:30:14 347747
wst04-VHDL20_DWSG_050400-2610050400-omedes--0.pdf 05-Oct-2026 05:00:13 347519
wst04-VHDL20_DWSG_050800-2610050800-omedes--0.pdf 05-Oct-2026 08:30:18 347070
wst04-VHDL20_DWSG_051800-2610051800-omedes--0.pdf 05-Oct-2026 18:30:32 350428
wst04-VHDL20_DWSG_060200-2610060200-omedes--0.pdf 06-Oct-2026 02:30:13 348391
wst04-VHDL20_DWSG_060400-2610060400-omedes--0.pdf 06-Oct-2026 05:00:13 349016