Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_280600 28-Jan-2026 13:52:19 3702
FPDL13_DWMZ_290600 29-Jan-2026 13:29:24 9455
SXDL31_DWAV_271800 27-Jan-2026 18:10:25 8766
SXDL31_DWAV_280800 28-Jan-2026 08:15:58 9482
SXDL31_DWAV_281800 28-Jan-2026 17:44:01 6513
SXDL31_DWAV_290800 29-Jan-2026 08:41:34 8096
SXDL31_DWAV_LATEST 29-Jan-2026 08:41:34 8096
SXDL33_DWAV_280000 28-Jan-2026 10:56:59 11613
SXDL33_DWAV_290000 29-Jan-2026 11:00:09 8763
SXDL33_DWAV_LATEST 29-Jan-2026 11:00:09 8763
ber01-FWDL39_DWMS_281230-2601281230-dsw--0-ia5 28-Jan-2026 12:38:37 2120
ber01-FWDL39_DWMS_291230-2601291230-dsw--0-ia5 29-Jan-2026 12:26:52 1787
ber01-VHDL13_DWEH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:17 3949
ber01-VHDL13_DWEH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 3961
ber01-VHDL13_DWEH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:11 3771
ber01-VHDL13_DWEH_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:12 3912
ber01-VHDL13_DWEH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:16 4068
ber01-VHDL13_DWEH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:17 3640
ber01-VHDL13_DWEH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:28:11 3739
ber01-VHDL13_DWEH_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:17 3736
ber01-VHDL13_DWEH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:17 3785
ber01-VHDL13_DWHG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3966
ber01-VHDL13_DWHG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3500
ber01-VHDL13_DWHG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3500
ber01-VHDL13_DWHG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:10 3850
ber01-VHDL13_DWHG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:08 3183
ber01-VHDL13_DWHG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:07 4453
ber01-VHDL13_DWHG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4454
ber01-VHDL13_DWHG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 4565
ber01-VHDL13_DWHH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3136
ber01-VHDL13_DWHH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 2969
ber01-VHDL13_DWHH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 2969
ber01-VHDL13_DWHH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:10 3128
ber01-VHDL13_DWHH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:08 2922
ber01-VHDL13_DWHH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:07 3905
ber01-VHDL13_DWHH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 3910
ber01-VHDL13_DWHH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 4145
ber01-VHDL13_DWLG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2539
ber01-VHDL13_DWLG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2434
ber01-VHDL13_DWLG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2434
ber01-VHDL13_DWLG_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:34:51 2985
ber01-VHDL13_DWLG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2920
ber01-VHDL13_DWLG_280800_COR-2601280800-dsw--0-ia5 28-Jan-2026 11:00:26 3062
ber01-VHDL13_DWLG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2635
ber01-VHDL13_DWLG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 2483
ber01-VHDL13_DWLG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2418
ber01-VHDL13_DWLG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2441
ber01-VHDL13_DWLH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2412
ber01-VHDL13_DWLH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2355
ber01-VHDL13_DWLH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2355
ber01-VHDL13_DWLH_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:34:41 2808
ber01-VHDL13_DWLH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2815
ber01-VHDL13_DWLH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2433
ber01-VHDL13_DWLH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 2333
ber01-VHDL13_DWLH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2244
ber01-VHDL13_DWLH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2271
ber01-VHDL13_DWLI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2062
ber01-VHDL13_DWLI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 1962
ber01-VHDL13_DWLI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 1962
ber01-VHDL13_DWLI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:35:04 2411
ber01-VHDL13_DWLI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2750
ber01-VHDL13_DWLI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2226
ber01-VHDL13_DWLI_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 2239
ber01-VHDL13_DWLI_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2292
ber01-VHDL13_DWLI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2234
ber01-VHDL13_DWMG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3381
ber01-VHDL13_DWMG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3528
ber01-VHDL13_DWMG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 3248
ber01-VHDL13_DWMG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3722
ber01-VHDL13_DWMG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3072
ber01-VHDL13_DWMG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:05 3373
ber01-VHDL13_DWMG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3383
ber01-VHDL13_DWMG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3564
ber01-VHDL13_DWMO_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2969
ber01-VHDL13_DWMO_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3299
ber01-VHDL13_DWMO_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 3229
ber01-VHDL13_DWMO_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3604
ber01-VHDL13_DWMO_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3615
ber01-VHDL13_DWMO_281800_COR-2601281800-dsw--0-ia5 28-Jan-2026 19:34:59 2963
ber01-VHDL13_DWMO_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:05 3267
ber01-VHDL13_DWMO_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3277
ber01-VHDL13_DWMO_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3438
ber01-VHDL13_DWMP_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 3074
ber01-VHDL13_DWMP_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:08 3240
ber01-VHDL13_DWMP_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:03 2908
ber01-VHDL13_DWMP_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3189
ber01-VHDL13_DWMP_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2845
ber01-VHDL13_DWMP_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:05 3223
ber01-VHDL13_DWMP_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:02 3160
ber01-VHDL13_DWMP_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 3519
ber01-VHDL13_DWOG_271700-2601271700-dsw--0-ia5 27-Jan-2026 19:00:02 6162
ber01-VHDL13_DWOG_280300-2601280300-dsw--0-ia5 28-Jan-2026 04:00:02 5464
ber01-VHDL13_DWOG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 5688
ber01-VHDL13_DWOG_281700-2601281700-dsw--0-ia5 28-Jan-2026 19:00:06 4933
ber01-VHDL13_DWOG_290300-2601290300-dsw--0-ia5 29-Jan-2026 04:00:01 5067
ber01-VHDL13_DWOG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:01 5261
ber01-VHDL13_DWOH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:11 3720
ber01-VHDL13_DWOH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 3481
ber01-VHDL13_DWOH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:11 3503
ber01-VHDL13_DWOH_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:16 3510
ber01-VHDL13_DWOH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:16 3455
ber01-VHDL13_DWOH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:11 3308
ber01-VHDL13_DWOH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:28:11 3277
ber01-VHDL13_DWOH_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:11 3319
ber01-VHDL13_DWOH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:11 3456
ber01-VHDL13_DWOI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:28:11 2952
ber01-VHDL13_DWOI_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:47 2899
ber01-VHDL13_DWOI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:28:17 2634
ber01-VHDL13_DWOI_280400-2601280400-dsw--0-ia5 28-Jan-2026 05:58:16 2584
ber01-VHDL13_DWOI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:07:31 2592
ber01-VHDL13_DWOI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:28:12 2669
ber01-VHDL13_DWOI_280800_COR-2601280800-dsw--0-ia5 28-Jan-2026 06:06:17 2598
ber01-VHDL13_DWOI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:28:11 3132
ber01-VHDL13_DWOI_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:28:11 3092
ber01-VHDL13_DWOI_290400-2601290400-dsw--0-ia5 29-Jan-2026 05:58:17 3090
ber01-VHDL13_DWOI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:28:11 3169
ber01-VHDL13_DWON_271531-2601271531-dsw--0-ia5 27-Jan-2026 15:31:52 4260
ber01-VHDL13_DWON_271836-2601271836-dsw--0-ia5 27-Jan-2026 18:36:51 4851
ber01-VHDL13_DWON_272001-2601272001-dsw--0-ia5 27-Jan-2026 20:01:46 4290
ber01-VHDL13_DWON_280016-2601280016-dsw--0-ia5 28-Jan-2026 00:16:27 3869
ber01-VHDL13_DWON_280354-2601280354-dsw--0-ia5 28-Jan-2026 03:54:17 3869
ber01-VHDL13_DWON_280629-2601280629-dsw--0-ia5 28-Jan-2026 06:29:16 4252
ber01-VHDL13_DWON_280725-2601280725-dsw--0-ia5 28-Jan-2026 07:25:23 4440
ber01-VHDL13_DWON_280726-2601280726-dsw--0-ia5 28-Jan-2026 07:26:47 4440
ber01-VHDL13_DWON_280919-2601280919-dsw--0-ia5 28-Jan-2026 09:19:57 4493
ber01-VHDL13_DWON_281559-2601281559-dsw--0-ia5 28-Jan-2026 16:00:02 3735
ber01-VHDL13_DWON_281800-2601281800-dsw--0-ia5 28-Jan-2026 18:00:36 3735
ber01-VHDL13_DWON_281818-2601281818-dsw--0-ia5 28-Jan-2026 18:18:47 3729
ber01-VHDL13_DWON_282122-2601282122-dsw--0-ia5 28-Jan-2026 21:22:17 3732
ber01-VHDL13_DWON_290147-2601290147-dsw--0-ia5 29-Jan-2026 01:48:01 4387
ber01-VHDL13_DWON_290343-2601290343-dsw--0-ia5 29-Jan-2026 03:43:26 4056
ber01-VHDL13_DWON_290625-2601290625-dsw--0-ia5 29-Jan-2026 06:25:47 4430
ber01-VHDL13_DWON_290718-2601290718-dsw--0-ia5 29-Jan-2026 07:18:10 4430
ber01-VHDL13_DWON_290916-2601290916-dsw--0-ia5 29-Jan-2026 09:16:58 4430
ber01-VHDL13_DWON_290921-2601290921-dsw--0-ia5 29-Jan-2026 09:21:06 4430
ber01-VHDL13_DWPG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2037
ber01-VHDL13_DWPG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 1785
ber01-VHDL13_DWPG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2006
ber01-VHDL13_DWPG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2104
ber01-VHDL13_DWPG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2037
ber01-VHDL13_DWPG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 2129
ber01-VHDL13_DWPG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2363
ber01-VHDL13_DWPG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2506
ber01-VHDL13_DWPH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:06 2367
ber01-VHDL13_DWPH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 2085
ber01-VHDL13_DWPH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:00 2325
ber01-VHDL13_DWPH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 2451
ber01-VHDL13_DWPH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 2283
ber01-VHDL13_DWPH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 2258
ber01-VHDL13_DWPH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 2491
ber01-VHDL13_DWPH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:06 2727
ber01-VHDL13_DWSG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:30:01 4099
ber01-VHDL13_DWSG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:30:01 3441
ber01-VHDL13_DWSG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3441
ber01-VHDL13_DWSG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:30:05 3169
ber01-VHDL13_DWSG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:30:03 3954
ber01-VHDL13_DWSG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:30:02 3816
ber01-VHDL13_DWSG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 3449
ber01-VHDL13_DWSG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:30:01 3818
ber01-VHDL17_DWOG_281200-2601281200-dsw--0-ia5 28-Jan-2026 12:13:27 3401
ber01-VHDL17_DWOG_291200-2601291200-dsw--0-ia5 29-Jan-2026 13:04:22 3279
swis2-VHDL20_DWEG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 4063
swis2-VHDL20_DWEG_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 4067
swis2-VHDL20_DWEG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 3989
swis2-VHDL20_DWEG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3918
swis2-VHDL20_DWEG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 4081
swis2-VHDL20_DWEG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3812
swis2-VHDL20_DWEG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 3618
swis2-VHDL20_DWEG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3717
swis2-VHDL20_DWEG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4058
swis2-VHDL20_DWEH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 4435
swis2-VHDL20_DWEH_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 4439
swis2-VHDL20_DWEH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 4215
swis2-VHDL20_DWEH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 4307
swis2-VHDL20_DWEH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4694
swis2-VHDL20_DWEH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 4075
swis2-VHDL20_DWEH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 4138
swis2-VHDL20_DWEH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 4131
swis2-VHDL20_DWEH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4402
swis2-VHDL20_DWEI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 3435
swis2-VHDL20_DWEI_271800_COR-2601271800-dsw--0-ia5 27-Jan-2026 19:40:37 3439
swis2-VHDL20_DWEI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:06 2995
swis2-VHDL20_DWEI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3004
swis2-VHDL20_DWEI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3306
swis2-VHDL20_DWEI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3550
swis2-VHDL20_DWEI_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 3448
swis2-VHDL20_DWEI_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3491
swis2-VHDL20_DWEI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 3804
swis2-VHDL20_DWHG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 4149
swis2-VHDL20_DWHG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3686
swis2-VHDL20_DWHG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3683
swis2-VHDL20_DWHG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4713
swis2-VHDL20_DWHG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3366
swis2-VHDL20_DWHG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 4639
swis2-VHDL20_DWHG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4637
swis2-VHDL20_DWHG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 5432
swis2-VHDL20_DWHH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:02 3322
swis2-VHDL20_DWHH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3155
swis2-VHDL20_DWHH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:07 3155
swis2-VHDL20_DWHH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3802
swis2-VHDL20_DWHH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3108
swis2-VHDL20_DWHH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 4091
swis2-VHDL20_DWHH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:06 4096
swis2-VHDL20_DWHH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 5050
swis2-VHDL20_DWLG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3033
swis2-VHDL20_DWLG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2928
swis2-VHDL20_DWLG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2844
swis2-VHDL20_DWLG_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:49:02 3415
swis2-VHDL20_DWLG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3575
swis2-VHDL20_DWLG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3064
swis2-VHDL20_DWLG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 2912
swis2-VHDL20_DWLG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2820
swis2-VHDL20_DWLG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 3034
swis2-VHDL20_DWLH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2929
swis2-VHDL20_DWLH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2888
swis2-VHDL20_DWLH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2781
swis2-VHDL20_DWLH_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:48:32 3249
swis2-VHDL20_DWLH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3455
swis2-VHDL20_DWLH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2874
swis2-VHDL20_DWLH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 2774
swis2-VHDL20_DWLH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2654
swis2-VHDL20_DWLH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 2876
swis2-VHDL20_DWLI_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2615
swis2-VHDL20_DWLI_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2515
swis2-VHDL20_DWLI_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2345
swis2-VHDL20_DWLI_280400_COR-2601280400-dsw--0-ia5 28-Jan-2026 06:49:26 2819
swis2-VHDL20_DWLI_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3351
swis2-VHDL20_DWLI_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2632
swis2-VHDL20_DWLI_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 2645
swis2-VHDL20_DWLI_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2695
swis2-VHDL20_DWLI_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 2827
swis2-VHDL20_DWMG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3990
swis2-VHDL20_DWMG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 4041
swis2-VHDL20_DWMG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3641
swis2-VHDL20_DWMG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4387
swis2-VHDL20_DWMG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3528
swis2-VHDL20_DWMG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 3763
swis2-VHDL20_DWMG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3800
swis2-VHDL20_DWMG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 4214
swis2-VHDL20_DWMO_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3582
swis2-VHDL20_DWMO_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3846
swis2-VHDL20_DWMO_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3629
swis2-VHDL20_DWMO_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 4280
swis2-VHDL20_DWMO_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3422
swis2-VHDL20_DWMO_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 3669
swis2-VHDL20_DWMO_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3698
swis2-VHDL20_DWMO_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 4096
swis2-VHDL20_DWMP_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3638
swis2-VHDL20_DWMP_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3733
swis2-VHDL20_DWMP_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:02 3304
swis2-VHDL20_DWMP_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:06 3911
swis2-VHDL20_DWMP_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:07 3233
swis2-VHDL20_DWMP_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 3622
swis2-VHDL20_DWMP_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:03 3559
swis2-VHDL20_DWMP_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:07 4159
swis2-VHDL20_DWPG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 2681
swis2-VHDL20_DWPG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2176
swis2-VHDL20_DWPG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2518
swis2-VHDL20_DWPG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 2922
swis2-VHDL20_DWPG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 2855
swis2-VHDL20_DWPG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 2644
swis2-VHDL20_DWPG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2891
swis2-VHDL20_DWPG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 3255
swis2-VHDL20_DWPH_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 3183
swis2-VHDL20_DWPH_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 2647
swis2-VHDL20_DWPH_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:00:11 2837
swis2-VHDL20_DWPH_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3267
swis2-VHDL20_DWPH_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 3099
swis2-VHDL20_DWPH_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:06 2770
swis2-VHDL20_DWPH_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:00:16 2977
swis2-VHDL20_DWPH_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:09 3463
swis2-VHDL20_DWSG_271800-2601271800-dsw--0-ia5 27-Jan-2026 19:45:06 4631
swis2-VHDL20_DWSG_280200-2601280200-dsw--0-ia5 28-Jan-2026 03:45:02 3925
swis2-VHDL20_DWSG_280400-2601280400-dsw--0-ia5 28-Jan-2026 06:15:06 3855
swis2-VHDL20_DWSG_280800-2601280800-dsw--0-ia5 28-Jan-2026 09:45:01 3744
swis2-VHDL20_DWSG_281300-2601281300-dsw--0-ia5 28-Jan-2026 14:45:01 4269
swis2-VHDL20_DWSG_281800-2601281800-dsw--0-ia5 28-Jan-2026 19:45:03 4519
swis2-VHDL20_DWSG_290200-2601290200-dsw--0-ia5 29-Jan-2026 03:45:02 4186
swis2-VHDL20_DWSG_290400-2601290400-dsw--0-ia5 29-Jan-2026 06:15:06 3858
swis2-VHDL20_DWSG_290800-2601290800-dsw--0-ia5 29-Jan-2026 09:45:02 4538
swis2-VHDL20_DWSG_291300-2601291300-dsw--0-ia5 29-Jan-2026 14:45:12 4266
wst04-VHDL20_DWEG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 226416
wst04-VHDL20_DWEG_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 226416
wst04-VHDL20_DWEG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 226015
wst04-VHDL20_DWEG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 225438
wst04-VHDL20_DWEG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 225828
wst04-VHDL20_DWEG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 224830
wst04-VHDL20_DWEG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:12 226152
wst04-VHDL20_DWEG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:23 225222
wst04-VHDL20_DWEG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 230889
wst04-VHDL20_DWEH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 229785
wst04-VHDL20_DWEH_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 229785
wst04-VHDL20_DWEH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 229540
wst04-VHDL20_DWEH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:22 228993
wst04-VHDL20_DWEH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:22 229600
wst04-VHDL20_DWEH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 229123
wst04-VHDL20_DWEH_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:12 229661
wst04-VHDL20_DWEH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 229209
wst04-VHDL20_DWEH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 233039
wst04-VHDL20_DWEI_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 313481
wst04-VHDL20_DWEI_271800_COR-2601271800-omedes-..> 27-Jan-2026 19:40:51 313481
wst04-VHDL20_DWEI_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 312949
wst04-VHDL20_DWEI_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 312789
wst04-VHDL20_DWEI_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 313615
wst04-VHDL20_DWEI_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 312909
wst04-VHDL20_DWEI_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:16 313873
wst04-VHDL20_DWEI_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:23 313308
wst04-VHDL20_DWEI_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 326233
wst04-VHDL20_DWHG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 300903
wst04-VHDL20_DWHG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 300593
wst04-VHDL20_DWHG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:13 300501
wst04-VHDL20_DWHG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 301308
wst04-VHDL20_DWHG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 299016
wst04-VHDL20_DWHG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:12 300963
wst04-VHDL20_DWHG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:12 301018
wst04-VHDL20_DWHG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 297911
wst04-VHDL20_DWHH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:12 293185
wst04-VHDL20_DWHH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 292472
wst04-VHDL20_DWHH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:13 292415
wst04-VHDL20_DWHH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 297165
wst04-VHDL20_DWHH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 296412
wst04-VHDL20_DWHH_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:12 297551
wst04-VHDL20_DWHH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:16 297566
wst04-VHDL20_DWHH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 298303
wst04-VHDL20_DWLG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 293972
wst04-VHDL20_DWLG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:26 293902
wst04-VHDL20_DWLG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 293797
wst04-VHDL20_DWLG_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:46:51 294898
wst04-VHDL20_DWLG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 293053
wst04-VHDL20_DWLG_280800_COR-2601280800-omedes-..> 28-Jan-2026 11:02:21 293049
wst04-VHDL20_DWLG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 292294
wst04-VHDL20_DWLG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:22 292058
wst04-VHDL20_DWLG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 292471
wst04-VHDL20_DWLG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 297582
wst04-VHDL20_DWLH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 290210
wst04-VHDL20_DWLH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 289881
wst04-VHDL20_DWLH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 289772
wst04-VHDL20_DWLH_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:46:11 290716
wst04-VHDL20_DWLH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 295848
wst04-VHDL20_DWLH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 295125
wst04-VHDL20_DWLH_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:22 295026
wst04-VHDL20_DWLH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 294969
wst04-VHDL20_DWLH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 290755
wst04-VHDL20_DWLI_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 289932
wst04-VHDL20_DWLI_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 289569
wst04-VHDL20_DWLI_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:42 289379
wst04-VHDL20_DWLI_280400_COR-2601280400-omedes-..> 28-Jan-2026 06:48:12 290435
wst04-VHDL20_DWLI_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 301937
wst04-VHDL20_DWLI_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 300565
wst04-VHDL20_DWLI_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:22 300932
wst04-VHDL20_DWLI_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:42 301459
wst04-VHDL20_DWLI_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 296396
wst04-VHDL20_DWMG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 508206
wst04-VHDL20_DWMG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 507679
wst04-VHDL20_DWMG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 507542
wst04-VHDL20_DWMG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 513334
wst04-VHDL20_DWMG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 512415
wst04-VHDL20_DWMG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:16 512343
wst04-VHDL20_DWMG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 512542
wst04-VHDL20_DWMG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:22 523663
wst04-VHDL20_DWMO_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:06 400163
wst04-VHDL20_DWMO_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 400475
wst04-VHDL20_DWMO_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:12 401113
wst04-VHDL20_DWMO_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 409774
wst04-VHDL20_DWMO_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 408815
wst04-VHDL20_DWMO_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:16 409362
wst04-VHDL20_DWMO_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 409751
wst04-VHDL20_DWMO_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:16 415140
wst04-VHDL20_DWMP_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:16 543014
wst04-VHDL20_DWMP_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:16 541533
wst04-VHDL20_DWMP_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:16 542578
wst04-VHDL20_DWMP_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:16 550148
wst04-VHDL20_DWMP_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:16 549288
wst04-VHDL20_DWMP_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:16 548790
wst04-VHDL20_DWMP_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:17 549679
wst04-VHDL20_DWMP_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:22 559982
wst04-VHDL20_DWPG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 294805
wst04-VHDL20_DWPG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 294920
wst04-VHDL20_DWPG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:31 295120
wst04-VHDL20_DWPG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:26 348567
wst04-VHDL20_DWPG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:26 304442
wst04-VHDL20_DWPG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:26 304316
wst04-VHDL20_DWPG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:32 304404
wst04-VHDL20_DWPG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:32 346850
wst04-VHDL20_DWPH_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:22 264863
wst04-VHDL20_DWPH_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:22 220166
wst04-VHDL20_DWPH_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:00:31 220286
wst04-VHDL20_DWPH_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:20 267437
wst04-VHDL20_DWPH_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:22 267292
wst04-VHDL20_DWPH_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:22 222661
wst04-VHDL20_DWPH_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:00:32 222817
wst04-VHDL20_DWPH_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:26 265305
wst04-VHDL20_DWSG_271800-2601271800-omedes--0.pdf 27-Jan-2026 19:45:10 322030
wst04-VHDL20_DWSG_280200-2601280200-omedes--0.pdf 28-Jan-2026 03:45:12 322544
wst04-VHDL20_DWSG_280400-2601280400-omedes--0.pdf 28-Jan-2026 06:15:12 322403
wst04-VHDL20_DWSG_280800-2601280800-omedes--0.pdf 28-Jan-2026 09:45:12 328875
wst04-VHDL20_DWSG_281300-2601281300-omedes--0.pdf 28-Jan-2026 14:45:13 329982
wst04-VHDL20_DWSG_281800-2601281800-omedes--0.pdf 28-Jan-2026 19:45:12 329980
wst04-VHDL20_DWSG_290200-2601290200-omedes--0.pdf 29-Jan-2026 03:45:12 329720
wst04-VHDL20_DWSG_290400-2601290400-omedes--0.pdf 29-Jan-2026 06:15:12 329277
wst04-VHDL20_DWSG_290800-2601290800-omedes--0.pdf 29-Jan-2026 09:45:12 343401
wst04-VHDL20_DWSG_291300-2601291300-omedes--0.pdf 29-Jan-2026 14:45:12 343298