Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_290600 29-Jun-2026 14:05:33 6917
FPDL13_DWMZ_300600 30-Jun-2026 12:49:50 2484
SXDL31_DWAV_290800 29-Jun-2026 07:38:48 12485
SXDL31_DWAV_291800 29-Jun-2026 16:42:55 5469
SXDL31_DWAV_300800 30-Jun-2026 07:54:10 16057
SXDL31_DWAV_301800 30-Jun-2026 15:15:10 8020
SXDL31_DWAV_LATEST 30-Jun-2026 15:15:10 8020
SXDL33_DWAV_290000 29-Jun-2026 09:19:00 12039
SXDL33_DWAV_300000 30-Jun-2026 10:09:35 9882
SXDL33_DWAV_LATEST 30-Jun-2026 10:09:35 9882
ber01-FWDL39_DWMS_291200-2606291200-dsw--0-ia5 29-Jun-2026 11:41:03 2341
ber01-FWDL39_DWMS_301200-2606301200-dsw--0-ia5 30-Jun-2026 11:51:27 2106
ber01-VHDL13_DWEG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 3680
ber01-VHDL13_DWEG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:28:17 3080
ber01-VHDL13_DWEH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 2905
ber01-VHDL13_DWEH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:28:11 2867
ber01-VHDL13_DWEI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:28:16 3558
ber01-VHDL13_DWEI_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:28:17 2620
ber01-VHDL13_DWHG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3859
ber01-VHDL13_DWHG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:13 3830
ber01-VHDL13_DWHH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3286
ber01-VHDL13_DWHH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:13 3552
ber01-VHDL13_DWLG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 2965
ber01-VHDL13_DWLG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 2858
ber01-VHDL13_DWLH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 2951
ber01-VHDL13_DWLH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 2849
ber01-VHDL13_DWLI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 3017
ber01-VHDL13_DWLI_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 2923
ber01-VHDL13_DWMO_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3636
ber01-VHDL13_DWMO_290800_COR-2606290800-dsw--0-ia5 29-Jun-2026 13:01:41 3614
ber01-VHDL13_DWMO_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 3712
ber01-VHDL13_DWMP_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3525
ber01-VHDL13_DWMP_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 3815
ber01-VHDL13_DWOG_010300-2607010300-dsw--0-ia5 01-Jul-2026 03:00:02 4215
ber01-VHDL13_DWOG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 5269
ber01-VHDL13_DWOG_291700-2606291700-dsw--0-ia5 29-Jun-2026 18:00:06 4349
ber01-VHDL13_DWOG_300300-2606300300-dsw--0-ia5 30-Jun-2026 03:00:01 3961
ber01-VHDL13_DWOG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 5150
ber01-VHDL13_DWOG_301700-2606301700-dsw--0-ia5 30-Jun-2026 18:00:02 4351
ber01-VHDL13_DWON_010217-2607010217-dsw--0-ia5 01-Jul-2026 02:17:07 3598
ber01-VHDL13_DWON_010528-2607010528-dsw--0-ia5 01-Jul-2026 05:29:01 3997
ber01-VHDL13_DWON_290629-2606290629-dsw--0-ia5 29-Jun-2026 06:29:56 3843
ber01-VHDL13_DWON_290826-2606290826-dsw--0-ia5 29-Jun-2026 08:27:02 3820
ber01-VHDL13_DWON_290955-2606290955-dsw--0-ia5 29-Jun-2026 09:55:06 3822
ber01-VHDL13_DWON_291500-2606291500-dsw--0-ia5 29-Jun-2026 15:00:42 3902
ber01-VHDL13_DWON_291759-2606291759-dsw--0-ia5 29-Jun-2026 17:59:21 3269
ber01-VHDL13_DWON_300151-2606300151-dsw--0-ia5 30-Jun-2026 01:51:21 3224
ber01-VHDL13_DWON_300529-2606300529-dsw--0-ia5 30-Jun-2026 05:29:16 3289
ber01-VHDL13_DWON_300603-2606300603-dsw--0-ia5 30-Jun-2026 06:03:57 4305
ber01-VHDL13_DWON_300725-2606300725-dsw--0-ia5 30-Jun-2026 07:25:52 4305
ber01-VHDL13_DWON_301412-2606301412-dsw--0-ia5 30-Jun-2026 14:12:55 4271
ber01-VHDL13_DWON_301728-2606301728-dsw--0-ia5 30-Jun-2026 17:28:47 3548
ber01-VHDL13_DWON_302343-2606302343-dsw--0-ia5 30-Jun-2026 23:44:01 3587
ber01-VHDL13_DWPG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:00 3520
ber01-VHDL13_DWPG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 3036
ber01-VHDL13_DWPG_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 15:47:31 2995
ber01-VHDL13_DWPH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:07 3141
ber01-VHDL13_DWPH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 2661
ber01-VHDL13_DWPH_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 15:47:46 3519
ber01-VHDL13_DWSG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 3730
ber01-VHDL13_DWSG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 3697
ber01-VHDL13_DWSG_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 12:38:20 3893
ber01-VHDL17_DWOG_291200-2606291200-dsw--0-ia5 29-Jun-2026 11:32:16 3021
ber01-VHDL17_DWOG_301200-2606301200-dsw--0-ia5 30-Jun-2026 11:34:09 3314
swis2-VHDL20_DWEG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1529
swis2-VHDL20_DWEG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 1126
swis2-VHDL20_DWEG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1984
swis2-VHDL20_DWEG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1755
swis2-VHDL20_DWEG_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1522
swis2-VHDL20_DWEG_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:01:18 1375
swis2-VHDL20_DWEG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 1509
swis2-VHDL20_DWEG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1692
swis2-VHDL20_DWEH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1118
swis2-VHDL20_DWEH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 1102
swis2-VHDL20_DWEH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1558
swis2-VHDL20_DWEH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1715
swis2-VHDL20_DWEH_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1438
swis2-VHDL20_DWEH_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:01:18 1273
swis2-VHDL20_DWEH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 1406
swis2-VHDL20_DWEH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1700
swis2-VHDL20_DWEI_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 922
swis2-VHDL20_DWEI_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:01:21 963
swis2-VHDL20_DWEI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1963
swis2-VHDL20_DWEI_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1551
swis2-VHDL20_DWEI_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1360
swis2-VHDL20_DWEI_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:01:18 1114
swis2-VHDL20_DWEI_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 1248
swis2-VHDL20_DWEI_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1450
swis2-VHDL20_DWHG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:45:45 1483
swis2-VHDL20_DWHG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1495
swis2-VHDL20_DWHG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:45:01 2032
swis2-VHDL20_DWHG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:45:15 2012
swis2-VHDL20_DWHG_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:45:01 1597
swis2-VHDL20_DWHG_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:16 1594
swis2-VHDL20_DWHG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:45:07 1956
swis2-VHDL20_DWHG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:45:07 1831
swis2-VHDL20_DWHH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:45:45 1760
swis2-VHDL20_DWHH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1773
swis2-VHDL20_DWHH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:45:01 1663
swis2-VHDL20_DWHH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:45:15 2064
swis2-VHDL20_DWHH_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:45:01 1398
swis2-VHDL20_DWHH_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:16 1438
swis2-VHDL20_DWHH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:45:07 2116
swis2-VHDL20_DWHH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:45:07 2157
swis2-VHDL20_DWLG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1787
swis2-VHDL20_DWLG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1639
swis2-VHDL20_DWLG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1519
swis2-VHDL20_DWLG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1110
swis2-VHDL20_DWLG_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:22 1426
swis2-VHDL20_DWLG_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:12 1539
swis2-VHDL20_DWLG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:21 1580
swis2-VHDL20_DWLG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1928
swis2-VHDL20_DWLH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1003
swis2-VHDL20_DWLH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1235
swis2-VHDL20_DWLH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1503
swis2-VHDL20_DWLH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1056
swis2-VHDL20_DWLH_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:22 1432
swis2-VHDL20_DWLH_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:12 1501
swis2-VHDL20_DWLH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:21 1644
swis2-VHDL20_DWLH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1601
swis2-VHDL20_DWLI_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1458
swis2-VHDL20_DWLI_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1485
swis2-VHDL20_DWLI_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1559
swis2-VHDL20_DWLI_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1048
swis2-VHDL20_DWLI_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:22 1460
swis2-VHDL20_DWLI_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:12 1492
swis2-VHDL20_DWLI_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:21 1664
swis2-VHDL20_DWLI_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1640
swis2-VHDL20_DWMO_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1431
swis2-VHDL20_DWMO_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:01 1417
swis2-VHDL20_DWMO_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 2018
swis2-VHDL20_DWMO_290800_COR-2606290800-dsw--0-ia5 29-Jun-2026 13:01:41 3334
swis2-VHDL20_DWMO_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:07 1955
swis2-VHDL20_DWMO_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1594
swis2-VHDL20_DWMO_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:02 1599
swis2-VHDL20_DWMO_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 1947
swis2-VHDL20_DWMO_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1964
swis2-VHDL20_DWMP_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1461
swis2-VHDL20_DWMP_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:01 1445
swis2-VHDL20_DWMP_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 2067
swis2-VHDL20_DWMP_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:07 2448
swis2-VHDL20_DWMP_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1551
swis2-VHDL20_DWMP_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:02 1784
swis2-VHDL20_DWMP_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 2091
swis2-VHDL20_DWMP_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1970
swis2-VHDL20_DWPG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1229
swis2-VHDL20_DWPG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1225
swis2-VHDL20_DWPG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 2274
swis2-VHDL20_DWPG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1125
swis2-VHDL20_DWPG_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:22 1604
swis2-VHDL20_DWPG_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:12 1692
swis2-VHDL20_DWPG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:21 1788
swis2-VHDL20_DWPG_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 15:50:01 1515
swis2-VHDL20_DWPG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 1501
swis2-VHDL20_DWPH_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:22 1526
swis2-VHDL20_DWPH_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:11 1347
swis2-VHDL20_DWPH_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:22 1829
swis2-VHDL20_DWPH_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:31:09 1059
swis2-VHDL20_DWPH_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:22 1254
swis2-VHDL20_DWPH_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:12 1308
swis2-VHDL20_DWPH_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:21 1453
swis2-VHDL20_DWPH_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 15:50:16 2028
swis2-VHDL20_DWPH_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:31:02 2013
swis2-VHDL20_DWSG_010200-2607010200-dsw--0-ia5 01-Jul-2026 02:30:06 1418
swis2-VHDL20_DWSG_010400-2607010400-dsw--0-ia5 01-Jul-2026 05:00:17 1445
swis2-VHDL20_DWSG_290800-2606290800-dsw--0-ia5 29-Jun-2026 08:30:02 1819
swis2-VHDL20_DWSG_291800-2606291800-dsw--0-ia5 29-Jun-2026 18:30:04 1939
swis2-VHDL20_DWSG_291800_COR-2606291800-dsw--0-ia5 29-Jun-2026 22:02:12 2103
swis2-VHDL20_DWSG_300200-2606300200-dsw--0-ia5 30-Jun-2026 02:30:09 1585
swis2-VHDL20_DWSG_300400-2606300400-dsw--0-ia5 30-Jun-2026 05:00:16 1683
swis2-VHDL20_DWSG_300800-2606300800-dsw--0-ia5 30-Jun-2026 08:30:01 1975
swis2-VHDL20_DWSG_300800_COR-2606300800-dsw--0-ia5 30-Jun-2026 12:38:20 1905
swis2-VHDL20_DWSG_301800-2606301800-dsw--0-ia5 30-Jun-2026 18:30:06 1854
wst04-VHDL20_DWEG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 240004
wst04-VHDL20_DWEG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 240088
wst04-VHDL20_DWEG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:12 242210
wst04-VHDL20_DWEG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:11 243440
wst04-VHDL20_DWEG_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:12 242107
wst04-VHDL20_DWEG_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:10 242129
wst04-VHDL20_DWEG_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:13 242923
wst04-VHDL20_DWEG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 240881
wst04-VHDL20_DWEH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 237448
wst04-VHDL20_DWEH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 238108
wst04-VHDL20_DWEH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:12 241322
wst04-VHDL20_DWEH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:11 236256
wst04-VHDL20_DWEH_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:12 235365
wst04-VHDL20_DWEH_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:10 235111
wst04-VHDL20_DWEH_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:13 236209
wst04-VHDL20_DWEH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 239027
wst04-VHDL20_DWEI_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 341425
wst04-VHDL20_DWEI_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 341703
wst04-VHDL20_DWEI_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:16 348759
wst04-VHDL20_DWEI_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 348527
wst04-VHDL20_DWEI_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:12 347183
wst04-VHDL20_DWEI_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:10 346755
wst04-VHDL20_DWEI_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:17 347095
wst04-VHDL20_DWEI_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:14 343297
wst04-VHDL20_DWHG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:45:45 350379
wst04-VHDL20_DWHG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 350381
wst04-VHDL20_DWHG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:45:12 357215
wst04-VHDL20_DWHG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:45:15 351060
wst04-VHDL20_DWHG_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:45:12 348421
wst04-VHDL20_DWHG_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:16 348233
wst04-VHDL20_DWHG_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:45:19 350466
wst04-VHDL20_DWHG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:45:16 351959
wst04-VHDL20_DWHH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:45:45 334998
wst04-VHDL20_DWHH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 229800
wst04-VHDL20_DWHH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:45:12 337518
wst04-VHDL20_DWHH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:45:15 337688
wst04-VHDL20_DWHH_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:45:12 334646
wst04-VHDL20_DWHH_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:12 231382
wst04-VHDL20_DWHH_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:45:19 336877
wst04-VHDL20_DWHH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:45:16 336004
wst04-VHDL20_DWLG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 343468
wst04-VHDL20_DWLG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 343077
wst04-VHDL20_DWLG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 332290
wst04-VHDL20_DWLG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 337195
wst04-VHDL20_DWLG_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:22 337410
wst04-VHDL20_DWLG_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:42 338029
wst04-VHDL20_DWLG_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:49 338045
wst04-VHDL20_DWLG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 344272
wst04-VHDL20_DWLH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:31 350084
wst04-VHDL20_DWLH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 350244
wst04-VHDL20_DWLH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 340093
wst04-VHDL20_DWLH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:32 347567
wst04-VHDL20_DWLH_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:22 347628
wst04-VHDL20_DWLH_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:42 347955
wst04-VHDL20_DWLH_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:42 348971
wst04-VHDL20_DWLH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 350938
wst04-VHDL20_DWLI_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 344825
wst04-VHDL20_DWLI_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:41 344460
wst04-VHDL20_DWLI_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 378145
wst04-VHDL20_DWLI_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 341984
wst04-VHDL20_DWLI_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:22 342065
wst04-VHDL20_DWLI_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:42 342571
wst04-VHDL20_DWLI_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:42 388203
wst04-VHDL20_DWLI_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 345161
wst04-VHDL20_DWMO_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:18 464037
wst04-VHDL20_DWMO_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 463872
wst04-VHDL20_DWMO_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:18 454477
wst04-VHDL20_DWMO_290800_COR-2606290800-omedes-..> 29-Jun-2026 13:01:53 470101
wst04-VHDL20_DWMO_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 360446
wst04-VHDL20_DWMO_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:18 468375
wst04-VHDL20_DWMO_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:16 469831
wst04-VHDL20_DWMO_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:17 470166
wst04-VHDL20_DWMO_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 357395
wst04-VHDL20_DWMP_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:18 590181
wst04-VHDL20_DWMP_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:17 589994
wst04-VHDL20_DWMP_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:22 478253
wst04-VHDL20_DWMP_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:30:17 488397
wst04-VHDL20_DWMP_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:18 594342
wst04-VHDL20_DWMP_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:16 596584
wst04-VHDL20_DWMP_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:23 487864
wst04-VHDL20_DWMP_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 480820
wst04-VHDL20_DWPG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 247049
wst04-VHDL20_DWPG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:31 353451
wst04-VHDL20_DWPG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:47 388124
wst04-VHDL20_DWPG_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 341892
wst04-VHDL20_DWPG_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:27 240616
wst04-VHDL20_DWPG_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:32 343428
wst04-VHDL20_DWPG_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:42 388133
wst04-VHDL20_DWPG_300800_COR-2606300800-omedes-..> 30-Jun-2026 15:48:46 398541
wst04-VHDL20_DWPG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 353946
wst04-VHDL20_DWPH_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:22 244198
wst04-VHDL20_DWPH_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:31 243585
wst04-VHDL20_DWPH_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:41 242353
wst04-VHDL20_DWPH_291800-2606291800-omedes--0.pdf 29-Jun-2026 18:31:25 247159
wst04-VHDL20_DWPH_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:22 247482
wst04-VHDL20_DWPH_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:32 247368
wst04-VHDL20_DWPH_300800-2606300800-omedes--0.pdf 30-Jun-2026 08:30:42 247550
wst04-VHDL20_DWPH_300800_COR-2606300800-omedes-..> 30-Jun-2026 15:49:26 245066
wst04-VHDL20_DWPH_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:31:27 245086
wst04-VHDL20_DWSG_010200-2607010200-omedes--0.pdf 01-Jul-2026 02:30:12 343099
wst04-VHDL20_DWSG_010400-2607010400-omedes--0.pdf 01-Jul-2026 05:00:11 343921
wst04-VHDL20_DWSG_290800-2606290800-omedes--0.pdf 29-Jun-2026 08:30:16 353177
wst04-VHDL20_DWSG_291800-2606291800-omedes--0.pdf 29-Jun-2026 22:02:22 357847
wst04-VHDL20_DWSG_300200-2606300200-omedes--0.pdf 30-Jun-2026 02:30:12 355663
wst04-VHDL20_DWSG_300400-2606300400-omedes--0.pdf 30-Jun-2026 05:00:12 356183
wst04-VHDL20_DWSG_300800-2606300800-omedes--0.pdf 30-Jun-2026 12:38:20 345466
wst04-VHDL20_DWSG_301800-2606301800-omedes--0.pdf 30-Jun-2026 18:30:16 345513