Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Oct-2026 13:07:39 4839
FPDL13_DWMZ_020600 02-Oct-2026 08:11:59 2585
FPDL13_DWMZ_030600 03-Oct-2026 10:22:43 5833
SXDL31_DWAV_011800 01-Oct-2026 16:34:40 6216
SXDL31_DWAV_020800 02-Oct-2026 07:28:04 9492
SXDL31_DWAV_021800 02-Oct-2026 15:36:49 7201
SXDL31_DWAV_030800 03-Oct-2026 07:54:44 8464
SXDL31_DWAV_LATEST 03-Oct-2026 07:54:44 8464
SXDL33_DWAV_020000 02-Oct-2026 10:41:34 8670
SXDL33_DWAV_030000 03-Oct-2026 10:04:13 916
SXDL33_DWAV_LATEST 03-Oct-2026 10:04:13 916
ber01-FWDL39_DWMS_011200-2610011200-dsw--0-ia5 01-Oct-2026 11:34:50 1893
ber01-FWDL39_DWMS_021200-2610021200-dsw--0-ia5 02-Oct-2026 10:36:09 1743
ber01-VHDL13_DWEG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:28:23 2248
ber01-VHDL13_DWEG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:20 2215
ber01-VHDL13_DWEH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:28:19 2397
ber01-VHDL13_DWEH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:13 2212
ber01-VHDL13_DWEI_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:28:23 2420
ber01-VHDL13_DWEI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:28:24 2511
ber01-VHDL13_DWHG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 2739
ber01-VHDL13_DWHG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2722
ber01-VHDL13_DWHH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 2661
ber01-VHDL13_DWHH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2617
ber01-VHDL13_DWLG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 2426
ber01-VHDL13_DWLG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2237
ber01-VHDL13_DWLH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 2432
ber01-VHDL13_DWLH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2218
ber01-VHDL13_DWLI_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 2437
ber01-VHDL13_DWLI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2277
ber01-VHDL13_DWMO_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 2656
ber01-VHDL13_DWMO_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 2918
ber01-VHDL13_DWMP_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 3014
ber01-VHDL13_DWMP_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 3401
ber01-VHDL13_DWOG_011700-2610011700-dsw--0-ia5 01-Oct-2026 18:00:08 3536
ber01-VHDL13_DWOG_020300-2610020300-dsw--0-ia5 02-Oct-2026 03:01:09 3931
ber01-VHDL13_DWOG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 3257
ber01-VHDL13_DWOG_021700-2610021700-dsw--0-ia5 02-Oct-2026 18:00:11 2643
ber01-VHDL13_DWOG_030300-2610030300-dsw--0-ia5 03-Oct-2026 03:01:05 2922
ber01-VHDL13_DWOG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2729
ber01-VHDL13_DWON_011534-2610011534-dsw--0-ia5 01-Oct-2026 15:34:53 3306
ber01-VHDL13_DWON_011657-2610011657-dsw--0-ia5 01-Oct-2026 16:57:48 3302
ber01-VHDL13_DWON_011936-2610011936-dsw--0-ia5 01-Oct-2026 19:37:11 3302
ber01-VHDL13_DWON_011954-2610011954-dsw--0-ia5 01-Oct-2026 19:55:10 3407
ber01-VHDL13_DWON_020119-2610020119-dsw--0-ia5 02-Oct-2026 01:19:29 3389
ber01-VHDL13_DWON_020246-2610020246-dsw--0-ia5 02-Oct-2026 02:46:39 3390
ber01-VHDL13_DWON_020528-2610020528-dsw--0-ia5 02-Oct-2026 05:28:43 3245
ber01-VHDL13_DWON_020537-2610020537-dsw--0-ia5 02-Oct-2026 05:38:01 3243
ber01-VHDL13_DWON_020719-2610020719-dsw--0-ia5 02-Oct-2026 07:19:58 3826
ber01-VHDL13_DWON_021110-2610021110-dsw--0-ia5 02-Oct-2026 11:10:33 3703
ber01-VHDL13_DWON_021425-2610021425-dsw--0-ia5 02-Oct-2026 14:25:19 3149
ber01-VHDL13_DWON_021540-2610021540-dsw--0-ia5 02-Oct-2026 15:41:04 3016
ber01-VHDL13_DWON_021543-2610021543-dsw--0-ia5 02-Oct-2026 15:43:14 2906
ber01-VHDL13_DWON_021725-2610021725-dsw--0-ia5 02-Oct-2026 17:25:33 2930
ber01-VHDL13_DWON_022103-2610022103-dsw--0-ia5 02-Oct-2026 21:03:39 2709
ber01-VHDL13_DWON_030110-2610030110-dsw--0-ia5 03-Oct-2026 01:10:10 2850
ber01-VHDL13_DWON_030244-2610030244-dsw--0-ia5 03-Oct-2026 02:45:38 2845
ber01-VHDL13_DWON_030518-2610030518-dsw--0-ia5 03-Oct-2026 05:18:23 3187
ber01-VHDL13_DWON_030927-2610030927-dsw--0-ia5 03-Oct-2026 09:27:44 3234
ber01-VHDL13_DWPG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 2281
ber01-VHDL13_DWPG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2170
ber01-VHDL13_DWPH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 2384
ber01-VHDL13_DWPH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2452
ber01-VHDL13_DWSG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 2439
ber01-VHDL13_DWSG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 2979
ber01-VHDL17_DWOG_011200-2610011200-dsw--0-ia5 01-Oct-2026 11:57:49 3223
ber01-VHDL17_DWOG_021200-2610021200-dsw--0-ia5 02-Oct-2026 11:49:04 2978
swis2-VHDL20_DWEG_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1507
swis2-VHDL20_DWEG_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 730
swis2-VHDL20_DWEG_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:01:23 698
swis2-VHDL20_DWEG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 894
swis2-VHDL20_DWEG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 938
swis2-VHDL20_DWEG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 757
swis2-VHDL20_DWEG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 820
swis2-VHDL20_DWEG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1007
swis2-VHDL20_DWEH_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1527
swis2-VHDL20_DWEH_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 835
swis2-VHDL20_DWEH_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:01:23 803
swis2-VHDL20_DWEH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 998
swis2-VHDL20_DWEH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 964
swis2-VHDL20_DWEH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 771
swis2-VHDL20_DWEH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 834
swis2-VHDL20_DWEH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1015
swis2-VHDL20_DWEI_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1404
swis2-VHDL20_DWEI_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 844
swis2-VHDL20_DWEI_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:01:23 812
swis2-VHDL20_DWEI_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:07 1005
swis2-VHDL20_DWEI_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 1211
swis2-VHDL20_DWEI_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1030
swis2-VHDL20_DWEI_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:01:22 1087
swis2-VHDL20_DWEI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1194
swis2-VHDL20_DWHG_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:45:16 1587
swis2-VHDL20_DWHG_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:45:26 1028
swis2-VHDL20_DWHG_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 1025
swis2-VHDL20_DWHG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:45:11 1087
swis2-VHDL20_DWHG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:45:19 1109
swis2-VHDL20_DWHG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:45:43 995
swis2-VHDL20_DWHG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 992
swis2-VHDL20_DWHG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:45:51 1076
swis2-VHDL20_DWHH_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:45:16 1550
swis2-VHDL20_DWHH_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:45:26 975
swis2-VHDL20_DWHH_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 975
swis2-VHDL20_DWHH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:45:11 1102
swis2-VHDL20_DWHH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:45:19 1143
swis2-VHDL20_DWHH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:45:43 1017
swis2-VHDL20_DWHH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 1017
swis2-VHDL20_DWHH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:45:51 1083
swis2-VHDL20_DWLG_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:31:09 1068
swis2-VHDL20_DWLG_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:32 900
swis2-VHDL20_DWLG_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 856
swis2-VHDL20_DWLG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:30 961
swis2-VHDL20_DWLG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 911
swis2-VHDL20_DWLG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 778
swis2-VHDL20_DWLG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 908
swis2-VHDL20_DWLG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 854
swis2-VHDL20_DWLH_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:31:09 1046
swis2-VHDL20_DWLH_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:32 912
swis2-VHDL20_DWLH_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 873
swis2-VHDL20_DWLH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:30 978
swis2-VHDL20_DWLH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 918
swis2-VHDL20_DWLH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 785
swis2-VHDL20_DWLH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 865
swis2-VHDL20_DWLH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 908
swis2-VHDL20_DWLI_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:31:09 1194
swis2-VHDL20_DWLI_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:32 901
swis2-VHDL20_DWLI_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 868
swis2-VHDL20_DWLI_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:30 973
swis2-VHDL20_DWLI_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 913
swis2-VHDL20_DWLI_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 780
swis2-VHDL20_DWLI_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 860
swis2-VHDL20_DWLI_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 903
swis2-VHDL20_DWMO_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1374
swis2-VHDL20_DWMO_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 1060
swis2-VHDL20_DWMO_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:05 1021
swis2-VHDL20_DWMO_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 1104
swis2-VHDL20_DWMO_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:02 1117
swis2-VHDL20_DWMO_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1500
swis2-VHDL20_DWMO_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:18 1506
swis2-VHDL20_DWMO_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1398
swis2-VHDL20_DWMP_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1855
swis2-VHDL20_DWMP_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 1655
swis2-VHDL20_DWMP_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:05 1331
swis2-VHDL20_DWMP_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 1400
swis2-VHDL20_DWMP_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:02 1356
swis2-VHDL20_DWMP_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1686
swis2-VHDL20_DWMP_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:18 1691
swis2-VHDL20_DWMP_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:18 1763
swis2-VHDL20_DWPG_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:31:09 1053
swis2-VHDL20_DWPG_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:32 916
swis2-VHDL20_DWPG_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 878
swis2-VHDL20_DWPG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:30 983
swis2-VHDL20_DWPG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 923
swis2-VHDL20_DWPG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 787
swis2-VHDL20_DWPG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 912
swis2-VHDL20_DWPG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 872
swis2-VHDL20_DWPH_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:31:09 1072
swis2-VHDL20_DWPH_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:32 923
swis2-VHDL20_DWPH_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 884
swis2-VHDL20_DWPH_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:30 992
swis2-VHDL20_DWPH_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:31:03 917
swis2-VHDL20_DWPH_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:23 796
swis2-VHDL20_DWPH_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 902
swis2-VHDL20_DWPH_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 904
swis2-VHDL20_DWSG_011800-2610011800-dsw--0-ia5 01-Oct-2026 18:30:04 1793
swis2-VHDL20_DWSG_020200-2610020200-dsw--0-ia5 02-Oct-2026 02:30:05 1235
swis2-VHDL20_DWSG_020400-2610020400-dsw--0-ia5 02-Oct-2026 05:00:16 1188
swis2-VHDL20_DWSG_020800-2610020800-dsw--0-ia5 02-Oct-2026 08:30:17 1069
swis2-VHDL20_DWSG_021800-2610021800-dsw--0-ia5 02-Oct-2026 18:30:09 1167
swis2-VHDL20_DWSG_030200-2610030200-dsw--0-ia5 03-Oct-2026 02:30:03 1498
swis2-VHDL20_DWSG_030400-2610030400-dsw--0-ia5 03-Oct-2026 05:00:27 1496
swis2-VHDL20_DWSG_030800-2610030800-dsw--0-ia5 03-Oct-2026 08:30:29 1458
wst04-VHDL20_DWEG_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:13 242616
wst04-VHDL20_DWEG_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:13 240238
wst04-VHDL20_DWEG_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 239717
wst04-VHDL20_DWEG_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:17 240535
wst04-VHDL20_DWEG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 240497
wst04-VHDL20_DWEG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 239523
wst04-VHDL20_DWEG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 239563
wst04-VHDL20_DWEG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 240318
wst04-VHDL20_DWEH_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:13 235519
wst04-VHDL20_DWEH_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:13 233496
wst04-VHDL20_DWEH_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 233277
wst04-VHDL20_DWEH_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:17 234559
wst04-VHDL20_DWEH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 233381
wst04-VHDL20_DWEH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 233002
wst04-VHDL20_DWEH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 233018
wst04-VHDL20_DWEH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 233806
wst04-VHDL20_DWEI_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:19 348974
wst04-VHDL20_DWEI_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:28 346655
wst04-VHDL20_DWEI_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 346096
wst04-VHDL20_DWEI_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:17 346846
wst04-VHDL20_DWEI_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:28 348248
wst04-VHDL20_DWEI_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 347261
wst04-VHDL20_DWEI_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 347258
wst04-VHDL20_DWEI_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 347106
wst04-VHDL20_DWHG_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:45:18 349233
wst04-VHDL20_DWHG_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:45:26 347682
wst04-VHDL20_DWHG_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 347474
wst04-VHDL20_DWHG_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:45:15 347933
wst04-VHDL20_DWHG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:45:22 347343
wst04-VHDL20_DWHG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:45:43 346917
wst04-VHDL20_DWHG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 346679
wst04-VHDL20_DWHG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:45:51 347427
wst04-VHDL20_DWHH_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:45:18 334670
wst04-VHDL20_DWHH_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:45:26 333353
wst04-VHDL20_DWHH_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 229215
wst04-VHDL20_DWHH_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:45:15 333091
wst04-VHDL20_DWHH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:45:22 332825
wst04-VHDL20_DWHH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:45:43 332591
wst04-VHDL20_DWHH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 228444
wst04-VHDL20_DWHH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:45:51 333115
wst04-VHDL20_DWLG_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:31:26 333880
wst04-VHDL20_DWLG_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:32 333243
wst04-VHDL20_DWLG_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:57 333315
wst04-VHDL20_DWLG_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:52 377970
wst04-VHDL20_DWLG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 333078
wst04-VHDL20_DWLG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 332412
wst04-VHDL20_DWLG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 332783
wst04-VHDL20_DWLG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 332811
wst04-VHDL20_DWLH_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:31:26 337888
wst04-VHDL20_DWLH_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:32 337280
wst04-VHDL20_DWLH_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:57 337348
wst04-VHDL20_DWLH_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:52 381983
wst04-VHDL20_DWLH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 337094
wst04-VHDL20_DWLH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 336430
wst04-VHDL20_DWLH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 336429
wst04-VHDL20_DWLH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 336376
wst04-VHDL20_DWLI_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:31:34 339180
wst04-VHDL20_DWLI_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:32 338334
wst04-VHDL20_DWLI_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:57 338393
wst04-VHDL20_DWLI_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:52 383053
wst04-VHDL20_DWLI_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 338160
wst04-VHDL20_DWLI_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 337515
wst04-VHDL20_DWLI_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:52 337481
wst04-VHDL20_DWLI_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 382008
wst04-VHDL20_DWMO_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:19 354631
wst04-VHDL20_DWMO_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:15 455602
wst04-VHDL20_DWMO_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 455124
wst04-VHDL20_DWMO_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:30 455396
wst04-VHDL20_DWMO_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 353320
wst04-VHDL20_DWMO_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 455830
wst04-VHDL20_DWMO_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 455983
wst04-VHDL20_DWMO_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 455614
wst04-VHDL20_DWMP_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:19 462119
wst04-VHDL20_DWMP_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:28 563968
wst04-VHDL20_DWMP_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 562878
wst04-VHDL20_DWMP_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:30 460980
wst04-VHDL20_DWMP_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 460848
wst04-VHDL20_DWMP_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:17 562283
wst04-VHDL20_DWMP_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 562557
wst04-VHDL20_DWMP_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 461068
wst04-VHDL20_DWPG_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:31:34 348301
wst04-VHDL20_DWPG_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:32 244165
wst04-VHDL20_DWPG_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:47 347820
wst04-VHDL20_DWPG_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:54 392413
wst04-VHDL20_DWPG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 347521
wst04-VHDL20_DWPG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:37 243295
wst04-VHDL20_DWPG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:45 346931
wst04-VHDL20_DWPG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 391829
wst04-VHDL20_DWPH_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:31:26 243208
wst04-VHDL20_DWPH_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:32 242622
wst04-VHDL20_DWPH_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:47 242706
wst04-VHDL20_DWPH_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:52 287300
wst04-VHDL20_DWPH_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:31:40 242475
wst04-VHDL20_DWPH_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:23 241781
wst04-VHDL20_DWPH_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:45 241829
wst04-VHDL20_DWPH_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:56 242150
wst04-VHDL20_DWSG_011800-2610011800-omedes--0.pdf 01-Oct-2026 18:30:13 349324
wst04-VHDL20_DWSG_020200-2610020200-omedes--0.pdf 02-Oct-2026 02:30:13 347766
wst04-VHDL20_DWSG_020400-2610020400-omedes--0.pdf 02-Oct-2026 05:00:16 347794
wst04-VHDL20_DWSG_020800-2610020800-omedes--0.pdf 02-Oct-2026 08:30:17 347314
wst04-VHDL20_DWSG_021800-2610021800-omedes--0.pdf 02-Oct-2026 18:30:24 347958
wst04-VHDL20_DWSG_030200-2610030200-omedes--0.pdf 03-Oct-2026 02:30:13 347599
wst04-VHDL20_DWSG_030400-2610030400-omedes--0.pdf 03-Oct-2026 05:00:27 347390
wst04-VHDL20_DWSG_030800-2610030800-omedes--0.pdf 03-Oct-2026 08:30:29 347519