Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_270600                                 27-Sep-2026 10:25:40                3344
FPDL13_DWMZ_280600                                 28-Sep-2026 12:51:39                2857
SXDL31_DWAV_271800                                 27-Sep-2026 15:27:00                2617
SXDL31_DWAV_280800                                 28-Sep-2026 07:21:30               12182
SXDL31_DWAV_281800                                 28-Sep-2026 17:40:50                5358
SXDL31_DWAV_290800                                 29-Sep-2026 07:36:26               13584
SXDL31_DWAV_LATEST                                 29-Sep-2026 07:36:26               13584
SXDL33_DWAV_270000                                 27-Sep-2026 10:10:30               12261
SXDL33_DWAV_280000                                 28-Sep-2026 09:39:59                6236
SXDL33_DWAV_290000                                 29-Sep-2026 09:44:31                7858
SXDL33_DWAV_LATEST                                 29-Sep-2026 09:44:31                7858
ber01-FWDL39_DWMS_271200-2609271200-dsw--0-ia5     27-Sep-2026 11:12:18                1457
ber01-FWDL39_DWMS_271200_COR-2609271200-dsw--0-ia5 27-Sep-2026 12:32:24                1447
ber01-FWDL39_DWMS_281200-2609281200-dsw--0-ia5     28-Sep-2026 12:29:14                1258
ber01-VHDL13_DWEG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:28:19                2366
ber01-VHDL13_DWEG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:28:18                2553
ber01-VHDL13_DWEH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:28:19                2696
ber01-VHDL13_DWEH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:28:18                2910
ber01-VHDL13_DWEI_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:28:19                2384
ber01-VHDL13_DWEI_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:28:18                2818
ber01-VHDL13_DWHG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2887
ber01-VHDL13_DWHG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                2586
ber01-VHDL13_DWHH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2672
ber01-VHDL13_DWHH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                2734
ber01-VHDL13_DWLG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2418
ber01-VHDL13_DWLG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                2200
ber01-VHDL13_DWLH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2081
ber01-VHDL13_DWLH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1961
ber01-VHDL13_DWLI_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2007
ber01-VHDL13_DWLI_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1878
ber01-VHDL13_DWMO_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2598
ber01-VHDL13_DWMO_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                2847
ber01-VHDL13_DWMP_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2523
ber01-VHDL13_DWMP_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                2421
ber01-VHDL13_DWOG_271700-2609271700-dsw--0-ia5     27-Sep-2026 18:00:04                2973
ber01-VHDL13_DWOG_280300-2609280300-dsw--0-ia5     28-Sep-2026 03:00:12                3162
ber01-VHDL13_DWOG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                3367
ber01-VHDL13_DWOG_281700-2609281700-dsw--0-ia5     28-Sep-2026 18:00:04                3319
ber01-VHDL13_DWOG_290300-2609290300-dsw--0-ia5     29-Sep-2026 03:00:07                3003
ber01-VHDL13_DWOG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                3063
ber01-VHDL13_DWON_271438-2609271438-dsw--0-ia5     27-Sep-2026 14:39:01                3166
ber01-VHDL13_DWON_271623-2609271623-dsw--0-ia5     27-Sep-2026 16:23:17                3166
ber01-VHDL13_DWON_271747-2609271747-dsw--0-ia5     27-Sep-2026 17:47:47                3166
ber01-VHDL13_DWON_280033-2609280033-dsw--0-ia5     28-Sep-2026 00:34:13                3729
ber01-VHDL13_DWON_280524-2609280524-dsw--0-ia5     28-Sep-2026 05:24:28                3729
ber01-VHDL13_DWON_280605-2609280605-dsw--0-ia5     28-Sep-2026 06:05:23                3911
ber01-VHDL13_DWON_280731-2609280731-dsw--0-ia5     28-Sep-2026 07:32:06                3911
ber01-VHDL13_DWON_281442-2609281442-dsw--0-ia5     28-Sep-2026 14:43:25                3385
ber01-VHDL13_DWON_282350-2609282350-dsw--0-ia5     28-Sep-2026 23:50:48                3430
ber01-VHDL13_DWON_290255-2609290255-dsw--0-ia5     29-Sep-2026 02:57:33                3430
ber01-VHDL13_DWON_290329-2609290329-dsw--0-ia5     29-Sep-2026 03:29:33                3430
ber01-VHDL13_DWON_290525-2609290525-dsw--0-ia5     29-Sep-2026 05:25:14                3358
ber01-VHDL13_DWON_290535-2609290535-dsw--0-ia5     29-Sep-2026 05:35:53                3346
ber01-VHDL13_DWON_290810-2609290810-dsw--0-ia5     29-Sep-2026 08:10:29                3343
ber01-VHDL13_DWPG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                1788
ber01-VHDL13_DWPG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1693
ber01-VHDL13_DWPH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2144
ber01-VHDL13_DWPH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1997
ber01-VHDL13_DWSG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                2521
ber01-VHDL13_DWSG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                2518
ber01-VHDL17_DWOG_271200-2609271200-dsw--0-ia5     27-Sep-2026 12:00:33                2838
ber01-VHDL17_DWOG_281200-2609281200-dsw--0-ia5     28-Sep-2026 10:55:59                2893
swis2-VHDL20_DWEG_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:04                 908
swis2-VHDL20_DWEG_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 793
swis2-VHDL20_DWEG_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:01:18                 793
swis2-VHDL20_DWEG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                 950
swis2-VHDL20_DWEG_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                1227
swis2-VHDL20_DWEG_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                 803
swis2-VHDL20_DWEG_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:01:20                 809
swis2-VHDL20_DWEG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1126
swis2-VHDL20_DWEH_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:04                1210
swis2-VHDL20_DWEH_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 807
swis2-VHDL20_DWEH_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:01:18                 807
swis2-VHDL20_DWEH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                1066
swis2-VHDL20_DWEH_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                1530
swis2-VHDL20_DWEH_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                1094
swis2-VHDL20_DWEH_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:01:20                1086
swis2-VHDL20_DWEH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1397
swis2-VHDL20_DWEI_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:04                1205
swis2-VHDL20_DWEI_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 815
swis2-VHDL20_DWEI_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:01:18                 815
swis2-VHDL20_DWEI_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                1080
swis2-VHDL20_DWEI_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                1527
swis2-VHDL20_DWEI_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                1100
swis2-VHDL20_DWEI_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:01:20                1092
swis2-VHDL20_DWEI_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                1409
swis2-VHDL20_DWHG_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:45:11                1303
swis2-VHDL20_DWHG_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:45:28                1206
swis2-VHDL20_DWHG_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:18                1195
swis2-VHDL20_DWHG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:45:49                1408
swis2-VHDL20_DWHG_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:45:22                1365
swis2-VHDL20_DWHG_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:47:13                1134
swis2-VHDL20_DWHG_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:18                 971
swis2-VHDL20_DWHG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:45:54                1597
swis2-VHDL20_DWHH_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:45:11                1287
swis2-VHDL20_DWHH_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:45:28                1133
swis2-VHDL20_DWHH_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:18                1125
swis2-VHDL20_DWHH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:45:49                1264
swis2-VHDL20_DWHH_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:45:22                1309
swis2-VHDL20_DWHH_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:47:13                1211
swis2-VHDL20_DWHH_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:18                1101
swis2-VHDL20_DWHH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:45:54                1574
swis2-VHDL20_DWLG_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:31:14                 988
swis2-VHDL20_DWLG_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:25                 791
swis2-VHDL20_DWLG_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:14                 844
swis2-VHDL20_DWLG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:32                1013
swis2-VHDL20_DWLG_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:31:11                 991
swis2-VHDL20_DWLG_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:38                 898
swis2-VHDL20_DWLG_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:14                 790
swis2-VHDL20_DWLG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:36                 884
swis2-VHDL20_DWLH_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:31:14                 928
swis2-VHDL20_DWLH_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:25                 707
swis2-VHDL20_DWLH_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:14                 744
swis2-VHDL20_DWLH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:32                 816
swis2-VHDL20_DWLH_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:31:11                 792
swis2-VHDL20_DWLH_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:38                 722
swis2-VHDL20_DWLH_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:14                 729
swis2-VHDL20_DWLH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:36                 801
swis2-VHDL20_DWLI_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:31:14                 898
swis2-VHDL20_DWLI_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:25                 702
swis2-VHDL20_DWLI_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:14                 740
swis2-VHDL20_DWLI_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:32                 811
swis2-VHDL20_DWLI_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:31:11                 834
swis2-VHDL20_DWLI_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:38                 717
swis2-VHDL20_DWLI_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:14                 724
swis2-VHDL20_DWLI_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:36                 843
swis2-VHDL20_DWMO_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:04                1262
swis2-VHDL20_DWMO_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 838
swis2-VHDL20_DWMO_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:04                 781
swis2-VHDL20_DWMO_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                 923
swis2-VHDL20_DWMO_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                 942
swis2-VHDL20_DWMO_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                 912
swis2-VHDL20_DWMO_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:04                 925
swis2-VHDL20_DWMO_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                1058
swis2-VHDL20_DWMP_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:04                1446
swis2-VHDL20_DWMP_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 837
swis2-VHDL20_DWMP_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:04                 779
swis2-VHDL20_DWMP_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                1025
swis2-VHDL20_DWMP_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                1023
swis2-VHDL20_DWMP_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                 912
swis2-VHDL20_DWMP_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:04                 926
swis2-VHDL20_DWMP_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:16                1085
swis2-VHDL20_DWPG_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:31:14                 804
swis2-VHDL20_DWPG_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:25                 717
swis2-VHDL20_DWPG_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:14                 755
swis2-VHDL20_DWPG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:32                 826
swis2-VHDL20_DWPG_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:31:11                 802
swis2-VHDL20_DWPG_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:38                 733
swis2-VHDL20_DWPG_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:14                 740
swis2-VHDL20_DWPG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:36                 811
swis2-VHDL20_DWPH_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:31:14                 807
swis2-VHDL20_DWPH_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:25                 692
swis2-VHDL20_DWPH_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:14                 757
swis2-VHDL20_DWPH_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:32                 829
swis2-VHDL20_DWPH_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:31:11                 804
swis2-VHDL20_DWPH_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:38                 733
swis2-VHDL20_DWPH_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:14                 740
swis2-VHDL20_DWPH_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:36                 812
swis2-VHDL20_DWSG_271800-2609271800-dsw--0-ia5     27-Sep-2026 18:30:13                1065
swis2-VHDL20_DWSG_280200-2609280200-dsw--0-ia5     28-Sep-2026 02:30:03                 771
swis2-VHDL20_DWSG_280400-2609280400-dsw--0-ia5     28-Sep-2026 05:00:18                 801
swis2-VHDL20_DWSG_280800-2609280800-dsw--0-ia5     28-Sep-2026 08:30:12                 884
swis2-VHDL20_DWSG_281800-2609281800-dsw--0-ia5     28-Sep-2026 18:30:04                 929
swis2-VHDL20_DWSG_290200-2609290200-dsw--0-ia5     29-Sep-2026 02:30:08                 901
swis2-VHDL20_DWSG_290400-2609290400-dsw--0-ia5     29-Sep-2026 05:00:18                 842
swis2-VHDL20_DWSG_290800-2609290800-dsw--0-ia5     29-Sep-2026 08:30:03                 913
wst04-VHDL20_DWEG_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:15              241234
wst04-VHDL20_DWEG_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:15              239801
wst04-VHDL20_DWEG_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:14              239615
wst04-VHDL20_DWEG_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:32              240426
wst04-VHDL20_DWEG_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:30              242539
wst04-VHDL20_DWEG_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              240348
wst04-VHDL20_DWEG_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:14              240138
wst04-VHDL20_DWEG_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:16              241384
wst04-VHDL20_DWEH_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:15              235526
wst04-VHDL20_DWEH_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:15              233014
wst04-VHDL20_DWEH_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:14              233086
wst04-VHDL20_DWEH_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:12              234817
wst04-VHDL20_DWEH_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:22              235848
wst04-VHDL20_DWEH_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              235241
wst04-VHDL20_DWEH_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:14              235274
wst04-VHDL20_DWEH_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:16              236132
wst04-VHDL20_DWEI_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:34              348259
wst04-VHDL20_DWEI_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:19              346128
wst04-VHDL20_DWEI_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:14              345887
wst04-VHDL20_DWEI_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:32              347067
wst04-VHDL20_DWEI_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:30              349404
wst04-VHDL20_DWEI_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              348267
wst04-VHDL20_DWEI_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:14              348051
wst04-VHDL20_DWEI_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:16              348351
wst04-VHDL20_DWHG_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:45:13              347908
wst04-VHDL20_DWHG_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:45:28              347807
wst04-VHDL20_DWHG_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:18              347612
wst04-VHDL20_DWHG_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:45:49              349863
wst04-VHDL20_DWHG_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:45:22              348784
wst04-VHDL20_DWHG_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:47:13              348468
wst04-VHDL20_DWHG_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:18              347130
wst04-VHDL20_DWHG_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:46:17              349552
wst04-VHDL20_DWHH_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:45:13              333827
wst04-VHDL20_DWHH_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:45:28              333434
wst04-VHDL20_DWHH_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:18              229310
wst04-VHDL20_DWHH_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:45:49              334102
wst04-VHDL20_DWHH_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:45:22              334312
wst04-VHDL20_DWHH_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:47:13              333518
wst04-VHDL20_DWHH_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:18              229269
wst04-VHDL20_DWHH_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:46:17              334594
wst04-VHDL20_DWLG_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:31:24              334387
wst04-VHDL20_DWLG_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:25              333491
wst04-VHDL20_DWLG_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:44              333411
wst04-VHDL20_DWLG_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:52              334203
wst04-VHDL20_DWLG_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:31:34              333728
wst04-VHDL20_DWLG_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:38              333132
wst04-VHDL20_DWLG_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:42              332896
wst04-VHDL20_DWLG_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:50              333479
wst04-VHDL20_DWLH_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:31:28              337794
wst04-VHDL20_DWLH_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:25              337150
wst04-VHDL20_DWLH_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:44              337019
wst04-VHDL20_DWLH_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:52              337063
wst04-VHDL20_DWLH_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:31:31              337260
wst04-VHDL20_DWLH_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:30              337164
wst04-VHDL20_DWLH_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:42              337008
wst04-VHDL20_DWLH_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:50              337046
wst04-VHDL20_DWLI_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:31:24              338850
wst04-VHDL20_DWLI_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:25              338245
wst04-VHDL20_DWLI_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:44              338071
wst04-VHDL20_DWLI_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:52              382708
wst04-VHDL20_DWLI_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:31:31              338749
wst04-VHDL20_DWLI_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:30              338253
wst04-VHDL20_DWLI_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:42              338079
wst04-VHDL20_DWLI_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:50              383109
wst04-VHDL20_DWMO_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:34              353957
wst04-VHDL20_DWMO_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:15              455214
wst04-VHDL20_DWMO_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:14              455440
wst04-VHDL20_DWMO_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:32              455480
wst04-VHDL20_DWMO_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:30              353147
wst04-VHDL20_DWMO_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              455540
wst04-VHDL20_DWMO_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:18              455395
wst04-VHDL20_DWMO_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:16              455380
wst04-VHDL20_DWMP_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:34              460907
wst04-VHDL20_DWMP_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:19              561579
wst04-VHDL20_DWMP_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:18              561910
wst04-VHDL20_DWMP_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:32              461228
wst04-VHDL20_DWMP_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:30              460508
wst04-VHDL20_DWMP_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              561924
wst04-VHDL20_DWMP_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:18              561859
wst04-VHDL20_DWMP_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:36              460653
wst04-VHDL20_DWPG_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:31:24              347829
wst04-VHDL20_DWPG_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:27              244023
wst04-VHDL20_DWPG_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:32              347512
wst04-VHDL20_DWPG_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:31:01              392066
wst04-VHDL20_DWPG_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:31:31              347706
wst04-VHDL20_DWPG_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:30              244052
wst04-VHDL20_DWPG_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:34              347515
wst04-VHDL20_DWPG_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:50              392077
wst04-VHDL20_DWPH_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:31:24              242700
wst04-VHDL20_DWPH_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:25              242450
wst04-VHDL20_DWPH_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:32              242404
wst04-VHDL20_DWPH_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:52              242355
wst04-VHDL20_DWPH_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:31:31              242593
wst04-VHDL20_DWPH_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:30              242481
wst04-VHDL20_DWPH_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:34              242346
wst04-VHDL20_DWPH_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:50              242358
wst04-VHDL20_DWSG_271800-2609271800-omedes--0.pdf  27-Sep-2026 18:30:34              347888
wst04-VHDL20_DWSG_280200-2609280200-omedes--0.pdf  28-Sep-2026 02:30:15              347093
wst04-VHDL20_DWSG_280400-2609280400-omedes--0.pdf  28-Sep-2026 05:00:18              346651
wst04-VHDL20_DWSG_280800-2609280800-omedes--0.pdf  28-Sep-2026 08:30:32              347488
wst04-VHDL20_DWSG_281800-2609281800-omedes--0.pdf  28-Sep-2026 18:30:22              347458
wst04-VHDL20_DWSG_290200-2609290200-omedes--0.pdf  29-Sep-2026 02:30:17              347146
wst04-VHDL20_DWSG_290400-2609290400-omedes--0.pdf  29-Sep-2026 05:00:14              346947
wst04-VHDL20_DWSG_290800-2609290800-omedes--0.pdf  29-Sep-2026 08:30:16              347743