Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Apr-2026 12:24:25 3300
FPDL13_DWMZ_050600 05-Apr-2026 13:26:39 14738
SXDL31_DWAV_040800 04-Apr-2026 07:26:19 8163
SXDL31_DWAV_041800 04-Apr-2026 17:14:41 10217
SXDL31_DWAV_050800 05-Apr-2026 07:06:59 7598
SXDL31_DWAV_051800 05-Apr-2026 16:56:03 8977
SXDL31_DWAV_LATEST 05-Apr-2026 16:56:03 8977
SXDL33_DWAV_040000 04-Apr-2026 09:23:40 8864
SXDL33_DWAV_050000 05-Apr-2026 09:44:10 9979
SXDL33_DWAV_LATEST 05-Apr-2026 09:44:10 9979
ber01-FWDL39_DWMS_041230-2604041230-dsw--0-ia5 04-Apr-2026 11:07:27 1186
ber01-FWDL39_DWMS_051230-2604051230-dsw--0-ia5 05-Apr-2026 10:52:31 2156
ber01-VHDL13_DWEH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:16 2567
ber01-VHDL13_DWEH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:11 2826
ber01-VHDL13_DWEH_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:11 2702
ber01-VHDL13_DWEH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:18 3288
ber01-VHDL13_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2752
ber01-VHDL13_DWEH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2673
ber01-VHDL13_DWEH_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:16 2454
ber01-VHDL13_DWEH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:17 3028
ber01-VHDL13_DWEH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:13 1899
ber01-VHDL13_DWHG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:07 3177
ber01-VHDL13_DWHG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 3330
ber01-VHDL13_DWHG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3330
ber01-VHDL13_DWHG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:08 3448
ber01-VHDL13_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 3209
ber01-VHDL13_DWHG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:10 3169
ber01-VHDL13_DWHG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 3163
ber01-VHDL13_DWHG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:07 3068
ber01-VHDL13_DWHH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:07 2741
ber01-VHDL13_DWHH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2980
ber01-VHDL13_DWHH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 2980
ber01-VHDL13_DWHH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:08 3178
ber01-VHDL13_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2666
ber01-VHDL13_DWHH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:10 2722
ber01-VHDL13_DWHH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2722
ber01-VHDL13_DWHH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:07 2915
ber01-VHDL13_DWLG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 3001
ber01-VHDL13_DWLG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2699
ber01-VHDL13_DWLG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2820
ber01-VHDL13_DWLG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2837
ber01-VHDL13_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2715
ber01-VHDL13_DWLG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2638
ber01-VHDL13_DWLG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2602
ber01-VHDL13_DWLG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2941
ber01-VHDL13_DWLH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2933
ber01-VHDL13_DWLH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2897
ber01-VHDL13_DWLH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2783
ber01-VHDL13_DWLH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2768
ber01-VHDL13_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2772
ber01-VHDL13_DWLH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2716
ber01-VHDL13_DWLH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2670
ber01-VHDL13_DWLH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3107
ber01-VHDL13_DWLI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2627
ber01-VHDL13_DWLI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2494
ber01-VHDL13_DWLI_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2222
ber01-VHDL13_DWLI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2222
ber01-VHDL13_DWLI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2328
ber01-VHDL13_DWLI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2295
ber01-VHDL13_DWLI_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2215
ber01-VHDL13_DWLI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2382
ber01-VHDL13_DWMG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2438
ber01-VHDL13_DWMG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2612
ber01-VHDL13_DWMG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2636
ber01-VHDL13_DWMG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2966
ber01-VHDL13_DWMG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2878
ber01-VHDL13_DWMG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 3277
ber01-VHDL13_DWMG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 3074
ber01-VHDL13_DWMG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3299
ber01-VHDL13_DWMO_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2445
ber01-VHDL13_DWMO_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2680
ber01-VHDL13_DWMO_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2608
ber01-VHDL13_DWMO_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2735
ber01-VHDL13_DWMO_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2753
ber01-VHDL13_DWMO_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2693
ber01-VHDL13_DWMO_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 2603
ber01-VHDL13_DWMO_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2777
ber01-VHDL13_DWMP_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2459
ber01-VHDL13_DWMP_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2541
ber01-VHDL13_DWMP_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2530
ber01-VHDL13_DWMP_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2874
ber01-VHDL13_DWMP_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:07 2715
ber01-VHDL13_DWMP_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 3400
ber01-VHDL13_DWMP_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:06 3428
ber01-VHDL13_DWMP_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2978
ber01-VHDL13_DWOG_040300-2604040300-dsw--0-ia5 04-Apr-2026 03:00:01 4673
ber01-VHDL13_DWOG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 4117
ber01-VHDL13_DWOG_041700-2604041700-dsw--0-ia5 04-Apr-2026 18:00:02 4843
ber01-VHDL13_DWOG_050300-2604050300-dsw--0-ia5 05-Apr-2026 03:00:01 4669
ber01-VHDL13_DWOG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 5026
ber01-VHDL13_DWOG_051700-2604051700-dsw--0-ia5 05-Apr-2026 18:00:02 3876
ber01-VHDL13_DWOH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:12 2436
ber01-VHDL13_DWOH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:11 2798
ber01-VHDL13_DWOH_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:17 2856
ber01-VHDL13_DWOH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:12 2890
ber01-VHDL13_DWOH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:16 2537
ber01-VHDL13_DWOH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2689
ber01-VHDL13_DWOH_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:12 2404
ber01-VHDL13_DWOH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:17 2699
ber01-VHDL13_DWOH_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1823
ber01-VHDL13_DWOI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:28:12 2383
ber01-VHDL13_DWOI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:28:17 2558
ber01-VHDL13_DWOI_040400-2604040400-dsw--0-ia5 04-Apr-2026 04:58:17 2501
ber01-VHDL13_DWOI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:28:18 2814
ber01-VHDL13_DWOI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:28:10 2471
ber01-VHDL13_DWOI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:28:11 2583
ber01-VHDL13_DWOI_050400-2604050400-dsw--0-ia5 05-Apr-2026 04:58:16 2356
ber01-VHDL13_DWOI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:28:11 2584
ber01-VHDL13_DWOI_051800-2604051800-dsw--0-ia5 05-Apr-2026 18:28:17 1685
ber01-VHDL13_DWON_031945-2604031945-dsw--0-ia5 03-Apr-2026 19:45:42 3938
ber01-VHDL13_DWON_040119-2604040119-dsw--0-ia5 04-Apr-2026 01:19:51 3946
ber01-VHDL13_DWON_040243-2604040243-dsw--0-ia5 04-Apr-2026 02:44:01 4362
ber01-VHDL13_DWON_040529-2604040529-dsw--0-ia5 04-Apr-2026 05:29:32 4200
ber01-VHDL13_DWON_040618-2604040618-dsw--0-ia5 04-Apr-2026 06:18:57 4561
ber01-VHDL13_DWON_040739-2604040739-dsw--0-ia5 04-Apr-2026 07:39:01 4461
ber01-VHDL13_DWON_041059-2604041059-dsw--0-ia5 04-Apr-2026 11:00:01 4461
ber01-VHDL13_DWON_041458-2604041458-dsw--0-ia5 04-Apr-2026 14:59:04 3826
ber01-VHDL13_DWON_041749-2604041749-dsw--0-ia5 04-Apr-2026 17:49:43 4156
ber01-VHDL13_DWON_050243-2604050243-dsw--0-ia5 05-Apr-2026 02:43:31 4039
ber01-VHDL13_DWON_050528-2604050528-dsw--0-ia5 05-Apr-2026 05:28:21 5071
ber01-VHDL13_DWON_050621-2604050621-dsw--0-ia5 05-Apr-2026 06:21:37 5046
ber01-VHDL13_DWON_050823-2604050823-dsw--0-ia5 05-Apr-2026 08:23:07 4862
ber01-VHDL13_DWON_050855-2604050855-dsw--0-ia5 05-Apr-2026 08:55:36 4862
ber01-VHDL13_DWON_051500-2604051500-dsw--0-ia5 05-Apr-2026 15:00:46 3326
ber01-VHDL13_DWON_051736-2604051736-dsw--0-ia5 05-Apr-2026 17:36:31 3219
ber01-VHDL13_DWPG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2332
ber01-VHDL13_DWPG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2446
ber01-VHDL13_DWPG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2531
ber01-VHDL13_DWPG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2532
ber01-VHDL13_DWPG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2390
ber01-VHDL13_DWPG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2404
ber01-VHDL13_DWPG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2375
ber01-VHDL13_DWPG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2681
ber01-VHDL13_DWPH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2710
ber01-VHDL13_DWPH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2694
ber01-VHDL13_DWPH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:01 2632
ber01-VHDL13_DWPH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 2632
ber01-VHDL13_DWPH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2711
ber01-VHDL13_DWPH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2788
ber01-VHDL13_DWPH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:00 2750
ber01-VHDL13_DWPH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 3286
ber01-VHDL13_DWSG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:30:02 2572
ber01-VHDL13_DWSG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:30:05 2862
ber01-VHDL13_DWSG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:17 2861
ber01-VHDL13_DWSG_040400_COR-2604040400-dsw--0-ia5 04-Apr-2026 05:02:07 2822
ber01-VHDL13_DWSG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:30:02 3499
ber01-VHDL13_DWSG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:30:03 2622
ber01-VHDL13_DWSG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:30:05 2726
ber01-VHDL13_DWSG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:16 2814
ber01-VHDL13_DWSG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:30:02 2796
ber01-VHDL17_DWOG_041200-2604041200-dsw--0-ia5 04-Apr-2026 10:47:17 2957
ber01-VHDL17_DWOG_051200-2604051200-dsw--0-ia5 05-Apr-2026 10:49:37 3098
swis2-VHDL20_DWEG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2762
swis2-VHDL20_DWEG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3077
swis2-VHDL20_DWEG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:03 3173
swis2-VHDL20_DWEG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:10 3569
swis2-VHDL20_DWEG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2860
swis2-VHDL20_DWEG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2965
swis2-VHDL20_DWEG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:02 2928
swis2-VHDL20_DWEG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3382
swis2-VHDL20_DWEH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2921
swis2-VHDL20_DWEH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3150
swis2-VHDL20_DWEH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:07 3031
swis2-VHDL20_DWEH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3992
swis2-VHDL20_DWEH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 3103
swis2-VHDL20_DWEH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2994
swis2-VHDL20_DWEH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:06 2990
swis2-VHDL20_DWEH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3736
swis2-VHDL20_DWEI_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 2734
swis2-VHDL20_DWEI_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 2853
swis2-VHDL20_DWEI_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:15:07 2849
swis2-VHDL20_DWEI_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3540
swis2-VHDL20_DWEI_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:06 2819
swis2-VHDL20_DWEI_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2875
swis2-VHDL20_DWEI_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:15:02 2911
swis2-VHDL20_DWEI_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:04 3314
swis2-VHDL20_DWHG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:06 3360
swis2-VHDL20_DWHG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3516
swis2-VHDL20_DWHG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3513
swis2-VHDL20_DWHG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3981
swis2-VHDL20_DWHG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 3392
swis2-VHDL20_DWHG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 3355
swis2-VHDL20_DWHG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 3346
swis2-VHDL20_DWHG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:06 3619
swis2-VHDL20_DWHH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:06 2927
swis2-VHDL20_DWHH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3166
swis2-VHDL20_DWHH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3166
swis2-VHDL20_DWHH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3720
swis2-VHDL20_DWHH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:02 2852
swis2-VHDL20_DWHH_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2908
swis2-VHDL20_DWHH_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2908
swis2-VHDL20_DWHH_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:06 3485
swis2-VHDL20_DWLG_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 3342
swis2-VHDL20_DWLG_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3040
swis2-VHDL20_DWLG_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3162
swis2-VHDL20_DWLG_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3328
swis2-VHDL20_DWLG_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3057
swis2-VHDL20_DWLG_050200-2604050200-dsw--0-ia5 05-Apr-2026 02:45:04 2980
swis2-VHDL20_DWLG_050400-2604050400-dsw--0-ia5 05-Apr-2026 05:00:12 2947
swis2-VHDL20_DWLG_050800-2604050800-dsw--0-ia5 05-Apr-2026 08:45:01 3433
swis2-VHDL20_DWLH_031800-2604031800-dsw--0-ia5 03-Apr-2026 18:45:02 3281
swis2-VHDL20_DWLH_040200-2604040200-dsw--0-ia5 04-Apr-2026 02:45:10 3245
swis2-VHDL20_DWLH_040400-2604040400-dsw--0-ia5 04-Apr-2026 05:00:11 3132
swis2-VHDL20_DWLH_040800-2604040800-dsw--0-ia5 04-Apr-2026 08:45:09 3270
swis2-VHDL20_DWLH_041800-2604041800-dsw--0-ia5 04-Apr-2026 18:45:00 3121
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wst04-VHDL20_DWEG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 240830
wst04-VHDL20_DWEG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 240323
wst04-VHDL20_DWEG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 242157
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wst04-VHDL20_DWEG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 241963
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wst04-VHDL20_DWEH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 238707
wst04-VHDL20_DWEH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 240177
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wst04-VHDL20_DWEH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 242341
wst04-VHDL20_DWEH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 241346
wst04-VHDL20_DWEH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 242856
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wst04-VHDL20_DWEI_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 344086
wst04-VHDL20_DWEI_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 344003
wst04-VHDL20_DWEI_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:20 345516
wst04-VHDL20_DWEI_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:12 346183
wst04-VHDL20_DWEI_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 346001
wst04-VHDL20_DWEI_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 345937
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wst04-VHDL20_DWHG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:11 334736
wst04-VHDL20_DWHG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 336005
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wst04-VHDL20_DWHG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:12 341737
wst04-VHDL20_DWHG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:18 342266
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wst04-VHDL20_DWHH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 321907
wst04-VHDL20_DWHH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:11 321942
wst04-VHDL20_DWHH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 322819
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wst04-VHDL20_DWHH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 321548
wst04-VHDL20_DWHH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:12 321534
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wst04-VHDL20_DWLG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 324308
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wst04-VHDL20_DWLG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 325382
wst04-VHDL20_DWLG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 334708
wst04-VHDL20_DWLG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 335253
wst04-VHDL20_DWLG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 335234
wst04-VHDL20_DWLG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:25 335736
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wst04-VHDL20_DWLH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 321772
wst04-VHDL20_DWLH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:41 322143
wst04-VHDL20_DWLH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 322731
wst04-VHDL20_DWLH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 331780
wst04-VHDL20_DWLH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 332064
wst04-VHDL20_DWLH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 332060
wst04-VHDL20_DWLH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:25 332775
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wst04-VHDL20_DWLI_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 330804
wst04-VHDL20_DWLI_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:41 330634
wst04-VHDL20_DWLI_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 331022
wst04-VHDL20_DWLI_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 333437
wst04-VHDL20_DWLI_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 333428
wst04-VHDL20_DWLI_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:42 333417
wst04-VHDL20_DWLI_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:32 333406
wst04-VHDL20_DWMG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:16 549085
wst04-VHDL20_DWMG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 549677
wst04-VHDL20_DWMG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 549620
wst04-VHDL20_DWMG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 550261
wst04-VHDL20_DWMG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 552152
wst04-VHDL20_DWMG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 552384
wst04-VHDL20_DWMG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 552738
wst04-VHDL20_DWMG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 553725
wst04-VHDL20_DWMO_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:16 449573
wst04-VHDL20_DWMO_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 450229
wst04-VHDL20_DWMO_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 450659
wst04-VHDL20_DWMO_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 450635
wst04-VHDL20_DWMO_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 450179
wst04-VHDL20_DWMO_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 449972
wst04-VHDL20_DWMO_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 450516
wst04-VHDL20_DWMO_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 450701
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wst04-VHDL20_DWMP_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 551600
wst04-VHDL20_DWMP_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:17 552579
wst04-VHDL20_DWMP_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:17 552874
wst04-VHDL20_DWMP_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:16 549804
wst04-VHDL20_DWMP_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 549239
wst04-VHDL20_DWMP_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:16 550624
wst04-VHDL20_DWMP_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:23 550915
wst04-VHDL20_DWPG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:26 337909
wst04-VHDL20_DWPG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 337910
wst04-VHDL20_DWPG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:31 338377
wst04-VHDL20_DWPG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:32 383382
wst04-VHDL20_DWPG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:26 336141
wst04-VHDL20_DWPG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 335424
wst04-VHDL20_DWPG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:32 335346
wst04-VHDL20_DWPG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:28 380268
wst04-VHDL20_DWPH_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:22 282292
wst04-VHDL20_DWPH_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:40 237247
wst04-VHDL20_DWPH_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:00:31 236822
wst04-VHDL20_DWPH_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:26 281816
wst04-VHDL20_DWPH_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:22 280042
wst04-VHDL20_DWPH_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 235073
wst04-VHDL20_DWPH_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:00:32 235040
wst04-VHDL20_DWPH_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:28 281072
wst04-VHDL20_DWSG_031800-2604031800-omedes--0.pdf 03-Apr-2026 18:45:12 347774
wst04-VHDL20_DWSG_040200-2604040200-omedes--0.pdf 04-Apr-2026 02:45:15 349985
wst04-VHDL20_DWSG_040400-2604040400-omedes--0.pdf 04-Apr-2026 05:15:11 350379
wst04-VHDL20_DWSG_040400_COR-2604040400-omedes-..> 04-Apr-2026 05:02:11 350379
wst04-VHDL20_DWSG_040800-2604040800-omedes--0.pdf 04-Apr-2026 08:45:22 350971
wst04-VHDL20_DWSG_041300-2604041300-omedes--0.pdf 04-Apr-2026 13:45:12 348402
wst04-VHDL20_DWSG_041800-2604041800-omedes--0.pdf 04-Apr-2026 18:45:12 347019
wst04-VHDL20_DWSG_050200-2604050200-omedes--0.pdf 05-Apr-2026 02:45:31 346845
wst04-VHDL20_DWSG_050400-2604050400-omedes--0.pdf 05-Apr-2026 05:15:12 346969
wst04-VHDL20_DWSG_050800-2604050800-omedes--0.pdf 05-Apr-2026 08:45:11 347266
wst04-VHDL20_DWSG_051300-2604051300-omedes--0.pdf 05-Apr-2026 13:45:12 354478