Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_220600                                 22-May-2026 13:46:08                5067
FPDL13_DWMZ_230600                                 23-May-2026 13:49:54                4788
SXDL31_DWAV_211800                                 21-May-2026 16:34:04                4850
SXDL31_DWAV_220800                                 22-May-2026 07:22:04                6334
SXDL31_DWAV_221800                                 22-May-2026 16:35:20                4859
SXDL31_DWAV_230800                                 23-May-2026 06:43:44                5761
SXDL31_DWAV_231800                                 23-May-2026 15:03:25                5866
SXDL31_DWAV_LATEST                                 23-May-2026 15:03:25                5866
SXDL33_DWAV_220000                                 22-May-2026 09:17:29               10379
SXDL33_DWAV_230000                                 23-May-2026 09:54:31               10130
SXDL33_DWAV_LATEST                                 23-May-2026 09:54:31               10130
ber01-FWDL39_DWMS_221230-2605221230-dsw--0-ia5     22-May-2026 11:01:17                1427
ber01-FWDL39_DWMS_231230-2605231230-dsw--0-ia5     23-May-2026 11:29:17                 964
ber01-VHDL13_DWEG_220800-2605220800-dsw--0-ia5     22-May-2026 08:28:12                1935
ber01-VHDL13_DWEG_230800-2605230800-dsw--0-ia5     23-May-2026 08:28:16                2003
ber01-VHDL13_DWEH_220800-2605220800-dsw--0-ia5     22-May-2026 08:28:16                2009
ber01-VHDL13_DWEH_230800-2605230800-dsw--0-ia5     23-May-2026 08:28:16                1987
ber01-VHDL13_DWEI_220800-2605220800-dsw--0-ia5     22-May-2026 08:28:16                1943
ber01-VHDL13_DWEI_230800-2605230800-dsw--0-ia5     23-May-2026 08:28:16                1929
ber01-VHDL13_DWHG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:16                2311
ber01-VHDL13_DWHG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:08                2099
ber01-VHDL13_DWHG_230800_COR-2605230800-dsw--0-ia5 23-May-2026 10:19:06                2291
ber01-VHDL13_DWHH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:16                2284
ber01-VHDL13_DWHH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:08                2296
ber01-VHDL13_DWHH_230800_COR-2605230800-dsw--0-ia5 23-May-2026 10:19:32                2370
ber01-VHDL13_DWLG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2041
ber01-VHDL13_DWLG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                1979
ber01-VHDL13_DWLH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2278
ber01-VHDL13_DWLH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2125
ber01-VHDL13_DWLI_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2074
ber01-VHDL13_DWLI_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2014
ber01-VHDL13_DWMO_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2445
ber01-VHDL13_DWMO_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2130
ber01-VHDL13_DWMP_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2157
ber01-VHDL13_DWMP_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2005
ber01-VHDL13_DWOG_211700-2605211700-dsw--0-ia5     21-May-2026 18:00:00                2194
ber01-VHDL13_DWOG_220300-2605220300-dsw--0-ia5     22-May-2026 03:00:07                2405
ber01-VHDL13_DWOG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2606
ber01-VHDL13_DWOG_221700-2605221700-dsw--0-ia5     22-May-2026 18:00:02                2241
ber01-VHDL13_DWOG_230300-2605230300-dsw--0-ia5     23-May-2026 03:00:01                2665
ber01-VHDL13_DWOG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2609
ber01-VHDL13_DWOG_230800_COR-2605230800-dsw--0-ia5 23-May-2026 08:34:23                2613
ber01-VHDL13_DWON_211711-2605211711-dsw--0-ia5     21-May-2026 17:11:31                2309
ber01-VHDL13_DWON_212104-2605212104-dsw--0-ia5     21-May-2026 21:04:57                2299
ber01-VHDL13_DWON_220132-2605220132-dsw--0-ia5     22-May-2026 01:32:28                2439
ber01-VHDL13_DWON_220244-2605220244-dsw--0-ia5     22-May-2026 02:44:17                2439
ber01-VHDL13_DWON_220443-2605220443-dsw--0-ia5     22-May-2026 04:43:51                2443
ber01-VHDL13_DWON_220504-2605220504-dsw--0-ia5     22-May-2026 05:04:21                3045
ber01-VHDL13_DWON_220637-2605220637-dsw--0-ia5     22-May-2026 06:37:57                3045
ber01-VHDL13_DWON_220725-2605220725-dsw--0-ia5     22-May-2026 07:25:16                3045
ber01-VHDL13_DWON_221152-2605221152-dsw--0-ia5     22-May-2026 11:52:31                3029
ber01-VHDL13_DWON_221409-2605221409-dsw--0-ia5     22-May-2026 14:09:47                2781
ber01-VHDL13_DWON_221639-2605221639-dsw--0-ia5     22-May-2026 16:40:06                2471
ber01-VHDL13_DWON_222244-2605222244-dsw--0-ia5     22-May-2026 22:44:07                2706
ber01-VHDL13_DWON_230248-2605230248-dsw--0-ia5     23-May-2026 02:48:40                2715
ber01-VHDL13_DWON_230517-2605230517-dsw--0-ia5     23-May-2026 05:17:41                3074
ber01-VHDL13_DWON_230603-2605230603-dsw--0-ia5     23-May-2026 06:03:41                3074
ber01-VHDL13_DWON_230613-2605230613-dsw--0-ia5     23-May-2026 06:13:37                3186
ber01-VHDL13_DWON_230644-2605230644-dsw--0-ia5     23-May-2026 06:44:07                3186
ber01-VHDL13_DWON_230726-2605230726-dsw--0-ia5     23-May-2026 07:26:32                3186
ber01-VHDL13_DWON_230833-2605230833-dsw--0-ia5     23-May-2026 08:33:42                3186
ber01-VHDL13_DWON_231442-2605231442-dsw--0-ia5     23-May-2026 14:43:01                2995
ber01-VHDL13_DWON_231557-2605231557-dsw--0-ia5     23-May-2026 15:57:37                2602
ber01-VHDL13_DWPG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2055
ber01-VHDL13_DWPG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                1951
ber01-VHDL13_DWPH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                2154
ber01-VHDL13_DWPH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2021
ber01-VHDL13_DWSG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:16                2280
ber01-VHDL13_DWSG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                2299
ber01-VHDL17_DWOG_221200-2605221200-dsw--0-ia5     22-May-2026 11:48:27                2402
ber01-VHDL17_DWOG_231200-2605231200-dsw--0-ia5     23-May-2026 09:44:22                1884
swis2-VHDL20_DWEG_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 969
swis2-VHDL20_DWEG_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:02                 846
swis2-VHDL20_DWEG_220400-2605220400-dsw--0-ia5     22-May-2026 05:01:25                 723
swis2-VHDL20_DWEG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 869
swis2-VHDL20_DWEG_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                1038
swis2-VHDL20_DWEG_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 905
swis2-VHDL20_DWEG_230400-2605230400-dsw--0-ia5     23-May-2026 05:01:27                 766
swis2-VHDL20_DWEG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                 878
swis2-VHDL20_DWEH_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 832
swis2-VHDL20_DWEH_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:07                 831
swis2-VHDL20_DWEH_220400-2605220400-dsw--0-ia5     22-May-2026 05:01:25                 737
swis2-VHDL20_DWEH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 877
swis2-VHDL20_DWEH_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                1064
swis2-VHDL20_DWEH_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 919
swis2-VHDL20_DWEH_230400-2605230400-dsw--0-ia5     23-May-2026 05:01:27                 775
swis2-VHDL20_DWEH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                 822
swis2-VHDL20_DWEI_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 991
swis2-VHDL20_DWEI_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:07                 869
swis2-VHDL20_DWEI_220400-2605220400-dsw--0-ia5     22-May-2026 05:01:25                 745
swis2-VHDL20_DWEI_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 891
swis2-VHDL20_DWEI_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                1060
swis2-VHDL20_DWEI_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 927
swis2-VHDL20_DWEI_230400-2605230400-dsw--0-ia5     23-May-2026 05:01:27                 788
swis2-VHDL20_DWEI_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                 911
swis2-VHDL20_DWHG_211800-2605211800-dsw--0-ia5     21-May-2026 18:45:04                1134
swis2-VHDL20_DWHG_220200-2605220200-dsw--0-ia5     22-May-2026 02:45:07                1122
swis2-VHDL20_DWHG_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:16                1119
swis2-VHDL20_DWHG_220800-2605220800-dsw--0-ia5     22-May-2026 08:45:07                1251
swis2-VHDL20_DWHG_221800-2605221800-dsw--0-ia5     22-May-2026 18:45:02                1124
swis2-VHDL20_DWHG_230200-2605230200-dsw--0-ia5     23-May-2026 02:45:06                1044
swis2-VHDL20_DWHG_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                1025
swis2-VHDL20_DWHG_230800-2605230800-dsw--0-ia5     23-May-2026 08:45:02                1091
swis2-VHDL20_DWHH_211800-2605211800-dsw--0-ia5     21-May-2026 18:45:04                1140
swis2-VHDL20_DWHH_220200-2605220200-dsw--0-ia5     22-May-2026 02:45:07                1117
swis2-VHDL20_DWHH_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:16                1117
swis2-VHDL20_DWHH_220800-2605220800-dsw--0-ia5     22-May-2026 08:45:07                1252
swis2-VHDL20_DWHH_221800-2605221800-dsw--0-ia5     22-May-2026 18:45:02                1317
swis2-VHDL20_DWHH_230200-2605230200-dsw--0-ia5     23-May-2026 02:45:01                1208
swis2-VHDL20_DWHH_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                1192
swis2-VHDL20_DWHH_230800-2605230800-dsw--0-ia5     23-May-2026 08:45:02                1261
swis2-VHDL20_DWLG_211800-2605211800-dsw--0-ia5     21-May-2026 18:31:02                 938
swis2-VHDL20_DWLG_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:22                 797
swis2-VHDL20_DWLG_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:10                 805
swis2-VHDL20_DWLG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:20                 885
swis2-VHDL20_DWLG_221800-2605221800-dsw--0-ia5     22-May-2026 18:31:03                 801
swis2-VHDL20_DWLG_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:21                 916
swis2-VHDL20_DWLG_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 757
swis2-VHDL20_DWLG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:24                 851
swis2-VHDL20_DWLH_211800-2605211800-dsw--0-ia5     21-May-2026 18:31:02                 945
swis2-VHDL20_DWLH_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:22                 804
swis2-VHDL20_DWLH_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:10                 802
swis2-VHDL20_DWLH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:20                 882
swis2-VHDL20_DWLH_221800-2605221800-dsw--0-ia5     22-May-2026 18:31:03                 807
swis2-VHDL20_DWLH_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:21                 771
swis2-VHDL20_DWLH_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 736
swis2-VHDL20_DWLH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:24                 830
swis2-VHDL20_DWLI_211800-2605211800-dsw--0-ia5     21-May-2026 18:31:02                 940
swis2-VHDL20_DWLI_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:22                 799
swis2-VHDL20_DWLI_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:10                 797
swis2-VHDL20_DWLI_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:20                 877
swis2-VHDL20_DWLI_221800-2605221800-dsw--0-ia5     22-May-2026 18:31:03                 802
swis2-VHDL20_DWLI_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:21                 766
swis2-VHDL20_DWLI_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 731
swis2-VHDL20_DWLI_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:24                 839
swis2-VHDL20_DWMO_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 856
swis2-VHDL20_DWMO_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:02                 756
swis2-VHDL20_DWMO_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:06                 777
swis2-VHDL20_DWMO_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 947
swis2-VHDL20_DWMO_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                 900
swis2-VHDL20_DWMO_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 781
swis2-VHDL20_DWMO_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:01                 798
swis2-VHDL20_DWMO_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                 936
swis2-VHDL20_DWMP_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 878
swis2-VHDL20_DWMP_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:02                 755
swis2-VHDL20_DWMP_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:06                 793
swis2-VHDL20_DWMP_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 927
swis2-VHDL20_DWMP_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                 881
swis2-VHDL20_DWMP_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 771
swis2-VHDL20_DWMP_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:01                 787
swis2-VHDL20_DWMP_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                 910
swis2-VHDL20_DWPG_211800-2605211800-dsw--0-ia5     21-May-2026 18:31:02                 956
swis2-VHDL20_DWPG_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:22                 815
swis2-VHDL20_DWPG_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:10                 823
swis2-VHDL20_DWPG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:20                 903
swis2-VHDL20_DWPG_221800-2605221800-dsw--0-ia5     22-May-2026 18:31:03                 818
swis2-VHDL20_DWPG_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:21                 860
swis2-VHDL20_DWPG_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 747
swis2-VHDL20_DWPG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:24                 841
swis2-VHDL20_DWPH_211800-2605211800-dsw--0-ia5     21-May-2026 18:31:02                 956
swis2-VHDL20_DWPH_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:22                 887
swis2-VHDL20_DWPH_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:10                 823
swis2-VHDL20_DWPH_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:20                 903
swis2-VHDL20_DWPH_221800-2605221800-dsw--0-ia5     22-May-2026 18:31:03                 829
swis2-VHDL20_DWPH_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:21                 854
swis2-VHDL20_DWPH_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 741
swis2-VHDL20_DWPH_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:24                 845
swis2-VHDL20_DWSG_211800-2605211800-dsw--0-ia5     21-May-2026 18:30:02                 817
swis2-VHDL20_DWSG_220200-2605220200-dsw--0-ia5     22-May-2026 02:30:02                 759
swis2-VHDL20_DWSG_220400-2605220400-dsw--0-ia5     22-May-2026 05:00:18                 794
swis2-VHDL20_DWSG_220800-2605220800-dsw--0-ia5     22-May-2026 08:30:01                 859
swis2-VHDL20_DWSG_221800-2605221800-dsw--0-ia5     22-May-2026 18:30:06                 831
swis2-VHDL20_DWSG_230200-2605230200-dsw--0-ia5     23-May-2026 02:30:07                 748
swis2-VHDL20_DWSG_230400-2605230400-dsw--0-ia5     23-May-2026 05:00:17                 847
swis2-VHDL20_DWSG_230800-2605230800-dsw--0-ia5     23-May-2026 08:30:01                1031
wst04-VHDL20_DWEG_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:14              236503
wst04-VHDL20_DWEG_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:12              235722
wst04-VHDL20_DWEG_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:12              235368
wst04-VHDL20_DWEG_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:16              236347
wst04-VHDL20_DWEG_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:11              237135
wst04-VHDL20_DWEG_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:13              236269
wst04-VHDL20_DWEG_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:11              236161
wst04-VHDL20_DWEG_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:11              236944
wst04-VHDL20_DWEH_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:14              228112
wst04-VHDL20_DWEH_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:12              227808
wst04-VHDL20_DWEH_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:12              227905
wst04-VHDL20_DWEH_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:16              228905
wst04-VHDL20_DWEH_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:11              232678
wst04-VHDL20_DWEH_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:13              232481
wst04-VHDL20_DWEH_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:11              232306
wst04-VHDL20_DWEH_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:11              232147
wst04-VHDL20_DWEI_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:16              335160
wst04-VHDL20_DWEI_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:12              334965
wst04-VHDL20_DWEI_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:12              334537
wst04-VHDL20_DWEI_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:16              335033
wst04-VHDL20_DWEI_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:16              335233
wst04-VHDL20_DWEI_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:13              334960
wst04-VHDL20_DWEI_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:11              334772
wst04-VHDL20_DWEI_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:16              335064
wst04-VHDL20_DWHG_211800-2605211800-omedes--0.pdf  21-May-2026 18:45:12              337752
wst04-VHDL20_DWHG_220200-2605220200-omedes--0.pdf  22-May-2026 02:45:36              338287
wst04-VHDL20_DWHG_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:16              338100
wst04-VHDL20_DWHG_220800-2605220800-omedes--0.pdf  22-May-2026 08:45:12              339461
wst04-VHDL20_DWHG_221800-2605221800-omedes--0.pdf  22-May-2026 18:45:12              337916
wst04-VHDL20_DWHG_230200-2605230200-omedes--0.pdf  23-May-2026 02:45:12              337687
wst04-VHDL20_DWHG_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:17              337434
wst04-VHDL20_DWHG_230800-2605230800-omedes--0.pdf  23-May-2026 08:45:12              338208
wst04-VHDL20_DWHG_230800_COR-2605230800-omedes-..> 23-May-2026 10:17:42              334237
wst04-VHDL20_DWHH_211800-2605211800-omedes--0.pdf  21-May-2026 18:45:12              326206
wst04-VHDL20_DWHH_220200-2605220200-omedes--0.pdf  22-May-2026 02:45:36              327026
wst04-VHDL20_DWHH_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:16              225594
wst04-VHDL20_DWHH_220800-2605220800-omedes--0.pdf  22-May-2026 08:45:12              327516
wst04-VHDL20_DWHH_221800-2605221800-omedes--0.pdf  22-May-2026 18:45:12              323580
wst04-VHDL20_DWHH_230200-2605230200-omedes--0.pdf  23-May-2026 02:45:12              323396
wst04-VHDL20_DWHH_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:17              223985
wst04-VHDL20_DWHH_230800-2605230800-omedes--0.pdf  23-May-2026 08:45:12              323546
wst04-VHDL20_DWHH_230800_COR-2605230800-omedes-..> 23-May-2026 10:18:26              327884
wst04-VHDL20_DWLG_211800-2605211800-omedes--0.pdf  21-May-2026 18:31:21              326317
wst04-VHDL20_DWLG_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:22              325440
wst04-VHDL20_DWLG_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:42              324712
wst04-VHDL20_DWLG_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:47              324770
wst04-VHDL20_DWLG_221800-2605221800-omedes--0.pdf  22-May-2026 18:31:22              324033
wst04-VHDL20_DWLG_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:33              324824
wst04-VHDL20_DWLG_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:41              324178
wst04-VHDL20_DWLG_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:41              324251
wst04-VHDL20_DWLH_211800-2605211800-omedes--0.pdf  21-May-2026 18:31:29              328431
wst04-VHDL20_DWLH_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:22              327541
wst04-VHDL20_DWLH_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:42              326832
wst04-VHDL20_DWLH_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:43              326880
wst04-VHDL20_DWLH_221800-2605221800-omedes--0.pdf  22-May-2026 18:31:22              324942
wst04-VHDL20_DWLH_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:21              325164
wst04-VHDL20_DWLH_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:41              324703
wst04-VHDL20_DWLH_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:41              324727
wst04-VHDL20_DWLI_211800-2605211800-omedes--0.pdf  21-May-2026 18:31:21              327751
wst04-VHDL20_DWLI_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:27              326867
wst04-VHDL20_DWLI_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:42              326119
wst04-VHDL20_DWLI_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:43              370768
wst04-VHDL20_DWLI_221800-2605221800-omedes--0.pdf  22-May-2026 18:31:31              330857
wst04-VHDL20_DWLI_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:21              331074
wst04-VHDL20_DWLI_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:41              330594
wst04-VHDL20_DWLI_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:41              375642
wst04-VHDL20_DWMO_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:16              341918
wst04-VHDL20_DWMO_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:15              446998
wst04-VHDL20_DWMO_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:16              446901
wst04-VHDL20_DWMO_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:16              447196
wst04-VHDL20_DWMO_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:16              339182
wst04-VHDL20_DWMO_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:18              442115
wst04-VHDL20_DWMO_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:17              442334
wst04-VHDL20_DWMO_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:18              441721
wst04-VHDL20_DWMP_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:16              450972
wst04-VHDL20_DWMP_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:15              553389
wst04-VHDL20_DWMP_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:16              553343
wst04-VHDL20_DWMP_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:23              451192
wst04-VHDL20_DWMP_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:16              447761
wst04-VHDL20_DWMP_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:18              545398
wst04-VHDL20_DWMP_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:17              545657
wst04-VHDL20_DWMP_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:24              447809
wst04-VHDL20_DWPG_211800-2605211800-omedes--0.pdf  21-May-2026 18:31:21              330453
wst04-VHDL20_DWPG_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:22              234138
wst04-VHDL20_DWPG_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:32              328920
wst04-VHDL20_DWPG_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:43              373478
wst04-VHDL20_DWPG_221800-2605221800-omedes--0.pdf  22-May-2026 18:31:22              331817
wst04-VHDL20_DWPG_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:21              235755
wst04-VHDL20_DWPG_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:31              331620
wst04-VHDL20_DWPG_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:46              376154
wst04-VHDL20_DWPH_211800-2605211800-omedes--0.pdf  21-May-2026 18:31:21              238861
wst04-VHDL20_DWPH_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:22              238136
wst04-VHDL20_DWPH_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:32              237321
wst04-VHDL20_DWPH_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:43              237288
wst04-VHDL20_DWPH_221800-2605221800-omedes--0.pdf  22-May-2026 18:31:22              237535
wst04-VHDL20_DWPH_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:21              237489
wst04-VHDL20_DWPH_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:31              236803
wst04-VHDL20_DWPH_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:41              237324
wst04-VHDL20_DWSG_211800-2605211800-omedes--0.pdf  21-May-2026 18:30:16              337744
wst04-VHDL20_DWSG_220200-2605220200-omedes--0.pdf  22-May-2026 02:30:12              337484
wst04-VHDL20_DWSG_220400-2605220400-omedes--0.pdf  22-May-2026 05:00:12              337351
wst04-VHDL20_DWSG_220800-2605220800-omedes--0.pdf  22-May-2026 08:30:16              337347
wst04-VHDL20_DWSG_221800-2605221800-omedes--0.pdf  22-May-2026 18:30:19              334987
wst04-VHDL20_DWSG_230200-2605230200-omedes--0.pdf  23-May-2026 02:30:13              335495
wst04-VHDL20_DWSG_230400-2605230400-omedes--0.pdf  23-May-2026 05:00:11              335700
wst04-VHDL20_DWSG_230800-2605230800-omedes--0.pdf  23-May-2026 08:30:11              335845