Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_280600                                 28-May-2026 10:45:34                4030
FPDL13_DWMZ_290600                                 29-May-2026 14:09:23                6155
SXDL31_DWAV_280800                                 28-May-2026 07:58:23                9676
SXDL31_DWAV_281800                                 28-May-2026 17:11:09                8512
SXDL31_DWAV_290800                                 29-May-2026 06:47:44                9964
SXDL31_DWAV_291800                                 29-May-2026 15:37:06                3983
SXDL31_DWAV_LATEST                                 29-May-2026 15:37:06                3983
SXDL33_DWAV_280000                                 28-May-2026 09:38:03                7683
SXDL33_DWAV_290000                                 29-May-2026 10:30:12                8498
SXDL33_DWAV_LATEST                                 29-May-2026 10:30:12                8498
ber01-FWDL39_DWMS_281230-2605281230-dsw--0-ia5     28-May-2026 11:53:41                1109
ber01-FWDL39_DWMS_291230-2605291230-dsw--0-ia5     29-May-2026 12:02:31                1102
ber01-VHDL13_DWEG_280800-2605280800-dsw--0-ia5     28-May-2026 08:28:17                2901
ber01-VHDL13_DWEG_280800_COR-2605280800-dsw--0-ia5 28-May-2026 17:45:16                3570
ber01-VHDL13_DWEG_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:17                3727
ber01-VHDL13_DWEH_280800-2605280800-dsw--0-ia5     28-May-2026 08:28:21                3104
ber01-VHDL13_DWEH_280800_COR-2605280800-dsw--0-ia5 28-May-2026 17:44:41                3438
ber01-VHDL13_DWEH_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:17                3586
ber01-VHDL13_DWEI_280800-2605280800-dsw--0-ia5     28-May-2026 08:28:17                3131
ber01-VHDL13_DWEI_280800_COR-2605280800-dsw--0-ia5 28-May-2026 08:39:16                3168
ber01-VHDL13_DWEI_290800-2605290800-dsw--0-ia5     29-May-2026 08:28:21                3618
ber01-VHDL13_DWHG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                3240
ber01-VHDL13_DWHG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3451
ber01-VHDL13_DWHH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                3174
ber01-VHDL13_DWHH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3003
ber01-VHDL13_DWLG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2265
ber01-VHDL13_DWLG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3414
ber01-VHDL13_DWLH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2166
ber01-VHDL13_DWLH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                2959
ber01-VHDL13_DWLI_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2197
ber01-VHDL13_DWLI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3322
ber01-VHDL13_DWMO_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2906
ber01-VHDL13_DWMO_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3485
ber01-VHDL13_DWMP_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2811
ber01-VHDL13_DWMP_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                3170
ber01-VHDL13_DWOG_280300-2605280300-dsw--0-ia5     28-May-2026 03:00:03                4227
ber01-VHDL13_DWOG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                4138
ber01-VHDL13_DWOG_281700-2605281700-dsw--0-ia5     28-May-2026 18:00:07                3796
ber01-VHDL13_DWOG_290300-2605290300-dsw--0-ia5     29-May-2026 03:00:02                4240
ber01-VHDL13_DWOG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                4126
ber01-VHDL13_DWOG_291700-2605291700-dsw--0-ia5     29-May-2026 18:00:02                4014
ber01-VHDL13_DWON_280252-2605280252-dsw--0-ia5     28-May-2026 02:52:57                3884
ber01-VHDL13_DWON_280526-2605280526-dsw--0-ia5     28-May-2026 05:26:31                4383
ber01-VHDL13_DWON_281321-2605281321-dsw--0-ia5     28-May-2026 13:21:17                4137
ber01-VHDL13_DWON_281729-2605281729-dsw--0-ia5     28-May-2026 17:29:28                3670
ber01-VHDL13_DWON_281737-2605281737-dsw--0-ia5     28-May-2026 17:37:42                3556
ber01-VHDL13_DWON_282121-2605282121-dsw--0-ia5     28-May-2026 21:21:37                3553
ber01-VHDL13_DWON_290153-2605290153-dsw--0-ia5     29-May-2026 01:53:53                3531
ber01-VHDL13_DWON_290244-2605290244-dsw--0-ia5     29-May-2026 02:44:57                3846
ber01-VHDL13_DWON_290526-2605290526-dsw--0-ia5     29-May-2026 05:26:51                3846
ber01-VHDL13_DWON_290627-2605290627-dsw--0-ia5     29-May-2026 06:27:51                4408
ber01-VHDL13_DWON_291444-2605291444-dsw--0-ia5     29-May-2026 14:44:24                3557
ber01-VHDL13_DWON_291724-2605291724-dsw--0-ia5     29-May-2026 17:24:23                3536
ber01-VHDL13_DWPG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2372
ber01-VHDL13_DWPG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3158
ber01-VHDL13_DWPH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2408
ber01-VHDL13_DWPH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3356
ber01-VHDL13_DWSG_271800_COR-2605271800-dsw--0-ia5 28-May-2026 05:31:32                2838
ber01-VHDL13_DWSG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                2828
ber01-VHDL13_DWSG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                3499
ber01-VHDL13_DWSG_290800_COR-2605290800-dsw--0-ia5 29-May-2026 08:35:49                3617
ber01-VHDL17_DWOG_281200-2605281200-dsw--0-ia5     28-May-2026 11:44:31                2735
ber01-VHDL17_DWOG_291200-2605291200-dsw--0-ia5     29-May-2026 11:51:31                3023
swis2-VHDL20_DWEG_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:06                1134
swis2-VHDL20_DWEG_280400-2605280400-dsw--0-ia5     28-May-2026 05:01:27                1133
swis2-VHDL20_DWEG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1546
swis2-VHDL20_DWEG_280800_COR-2605280800-dsw--0-ia5 28-May-2026 08:38:56                1980
swis2-VHDL20_DWEG_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2035
swis2-VHDL20_DWEG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1665
swis2-VHDL20_DWEG_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1665
swis2-VHDL20_DWEG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                2017
swis2-VHDL20_DWEG_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1943
swis2-VHDL20_DWEH_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:06                1468
swis2-VHDL20_DWEH_280400-2605280400-dsw--0-ia5     28-May-2026 05:01:27                1474
swis2-VHDL20_DWEH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1881
swis2-VHDL20_DWEH_280800_COR-2605280800-dsw--0-ia5 28-May-2026 08:38:56                1892
swis2-VHDL20_DWEH_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2056
swis2-VHDL20_DWEH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1628
swis2-VHDL20_DWEH_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1629
swis2-VHDL20_DWEH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1977
swis2-VHDL20_DWEH_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1857
swis2-VHDL20_DWEI_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:06                1417
swis2-VHDL20_DWEI_280400-2605280400-dsw--0-ia5     28-May-2026 05:01:27                1424
swis2-VHDL20_DWEI_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1837
swis2-VHDL20_DWEI_280800_COR-2605280800-dsw--0-ia5 28-May-2026 08:38:56                1860
swis2-VHDL20_DWEI_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:06                2025
swis2-VHDL20_DWEI_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:06                1611
swis2-VHDL20_DWEI_290400-2605290400-dsw--0-ia5     29-May-2026 05:01:23                1607
swis2-VHDL20_DWEI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1992
swis2-VHDL20_DWEI_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1870
swis2-VHDL20_DWHG_280200-2605280200-dsw--0-ia5     28-May-2026 02:45:06                1660
swis2-VHDL20_DWHG_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:17                1657
swis2-VHDL20_DWHG_280800-2605280800-dsw--0-ia5     28-May-2026 08:45:11                1726
swis2-VHDL20_DWHG_281800-2605281800-dsw--0-ia5     28-May-2026 18:45:02                1669
swis2-VHDL20_DWHG_290200-2605290200-dsw--0-ia5     29-May-2026 02:45:26                1501
swis2-VHDL20_DWHG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1498
swis2-VHDL20_DWHG_290800-2605290800-dsw--0-ia5     29-May-2026 08:45:06                1834
swis2-VHDL20_DWHG_291800-2605291800-dsw--0-ia5     29-May-2026 18:45:03                1992
swis2-VHDL20_DWHH_280200-2605280200-dsw--0-ia5     28-May-2026 02:45:06                1518
swis2-VHDL20_DWHH_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:17                1518
swis2-VHDL20_DWHH_280800-2605280800-dsw--0-ia5     28-May-2026 08:45:11                1596
swis2-VHDL20_DWHH_281800-2605281800-dsw--0-ia5     28-May-2026 18:45:02                1581
swis2-VHDL20_DWHH_290200-2605290200-dsw--0-ia5     29-May-2026 02:45:26                1402
swis2-VHDL20_DWHH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1402
swis2-VHDL20_DWHH_290800-2605290800-dsw--0-ia5     29-May-2026 08:45:06                1568
swis2-VHDL20_DWHH_291800-2605291800-dsw--0-ia5     29-May-2026 18:45:03                1625
swis2-VHDL20_DWLG_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:22                 729
swis2-VHDL20_DWLG_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:11                 767
swis2-VHDL20_DWLG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:22                 947
swis2-VHDL20_DWLG_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1524
swis2-VHDL20_DWLG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1121
swis2-VHDL20_DWLG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1399
swis2-VHDL20_DWLG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1769
swis2-VHDL20_DWLG_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1865
swis2-VHDL20_DWLH_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:22                 740
swis2-VHDL20_DWLH_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:11                 774
swis2-VHDL20_DWLH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:22                 999
swis2-VHDL20_DWLH_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1375
swis2-VHDL20_DWLH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1117
swis2-VHDL20_DWLH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1171
swis2-VHDL20_DWLH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1392
swis2-VHDL20_DWLH_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1392
swis2-VHDL20_DWLI_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:22                 733
swis2-VHDL20_DWLI_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:11                 769
swis2-VHDL20_DWLI_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:22                 965
swis2-VHDL20_DWLI_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1499
swis2-VHDL20_DWLI_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1124
swis2-VHDL20_DWLI_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1375
swis2-VHDL20_DWLI_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1693
swis2-VHDL20_DWLI_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1786
swis2-VHDL20_DWMO_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:04                 762
swis2-VHDL20_DWMO_280200_COR-2605280200-dsw--0-ia5 28-May-2026 02:34:58                3141
swis2-VHDL20_DWMO_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:01                 990
swis2-VHDL20_DWMO_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1542
swis2-VHDL20_DWMO_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1735
swis2-VHDL20_DWMO_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:04                1417
swis2-VHDL20_DWMO_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:02                1426
swis2-VHDL20_DWMO_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                2038
swis2-VHDL20_DWMO_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                2274
swis2-VHDL20_DWMO_291800_COR-2605291800-dsw--0-ia5 29-May-2026 21:11:22                3275
swis2-VHDL20_DWMP_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:04                 814
swis2-VHDL20_DWMP_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:01                1041
swis2-VHDL20_DWMP_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1511
swis2-VHDL20_DWMP_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1654
swis2-VHDL20_DWMP_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:04                1252
swis2-VHDL20_DWMP_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:02                1272
swis2-VHDL20_DWMP_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:16                1839
swis2-VHDL20_DWMP_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                2004
swis2-VHDL20_DWPG_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:22                 996
swis2-VHDL20_DWPG_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:11                1025
swis2-VHDL20_DWPG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:22                1213
swis2-VHDL20_DWPG_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1506
swis2-VHDL20_DWPG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1374
swis2-VHDL20_DWPG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1435
swis2-VHDL20_DWPG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1545
swis2-VHDL20_DWPG_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1545
swis2-VHDL20_DWPH_280200-2605280200-dsw--0-ia5     28-May-2026 02:30:22                 996
swis2-VHDL20_DWPH_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:11                1025
swis2-VHDL20_DWPH_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:22                1210
swis2-VHDL20_DWPH_281800-2605281800-dsw--0-ia5     28-May-2026 18:31:06                1475
swis2-VHDL20_DWPH_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:21                1604
swis2-VHDL20_DWPH_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:12                1682
swis2-VHDL20_DWPH_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:21                1775
swis2-VHDL20_DWPH_291800-2605291800-dsw--0-ia5     29-May-2026 18:31:05                1805
swis2-VHDL20_DWSG_280200-2605280200-dsw--0-ia5     28-May-2026 22:27:17                1111
swis2-VHDL20_DWSG_280200_COR-2605280200-dsw--0-ia5 28-May-2026 02:36:03                1016
swis2-VHDL20_DWSG_280400-2605280400-dsw--0-ia5     28-May-2026 05:00:21                 924
swis2-VHDL20_DWSG_280400_COR-2605280400-dsw--0-ia5 28-May-2026 05:32:58                 928
swis2-VHDL20_DWSG_280800-2605280800-dsw--0-ia5     28-May-2026 08:30:08                1469
swis2-VHDL20_DWSG_281800-2605281800-dsw--0-ia5     28-May-2026 18:30:01                1267
swis2-VHDL20_DWSG_290200-2605290200-dsw--0-ia5     29-May-2026 02:30:00                1034
swis2-VHDL20_DWSG_290400-2605290400-dsw--0-ia5     29-May-2026 05:00:16                1494
swis2-VHDL20_DWSG_290800-2605290800-dsw--0-ia5     29-May-2026 08:30:02                1760
swis2-VHDL20_DWSG_290800_COR-2605290800-dsw--0-ia5 29-May-2026 08:35:49                1792
swis2-VHDL20_DWSG_291800-2605291800-dsw--0-ia5     29-May-2026 18:30:01                1873
wst04-VHDL20_DWEG_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:12              242327
wst04-VHDL20_DWEG_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:11              242141
wst04-VHDL20_DWEG_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:12              243236
wst04-VHDL20_DWEG_280800_COR-2605280800-omedes-..> 28-May-2026 08:39:16              244095
wst04-VHDL20_DWEG_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:12              242994
wst04-VHDL20_DWEG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              242139
wst04-VHDL20_DWEG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              241716
wst04-VHDL20_DWEG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              242689
wst04-VHDL20_DWEG_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:12              242572
wst04-VHDL20_DWEH_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:12              241624
wst04-VHDL20_DWEH_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:11              241784
wst04-VHDL20_DWEH_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:12              242896
wst04-VHDL20_DWEH_280800_COR-2605280800-omedes-..> 28-May-2026 08:39:16              242686
wst04-VHDL20_DWEH_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:12              238891
wst04-VHDL20_DWEH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              238639
wst04-VHDL20_DWEH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              238705
wst04-VHDL20_DWEH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              239686
wst04-VHDL20_DWEH_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:12              242740
wst04-VHDL20_DWEI_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:16              345217
wst04-VHDL20_DWEI_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:17              345017
wst04-VHDL20_DWEI_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:16              346289
wst04-VHDL20_DWEI_280800_COR-2605280800-omedes-..> 28-May-2026 08:39:19              346817
wst04-VHDL20_DWEI_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              345404
wst04-VHDL20_DWEI_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              344053
wst04-VHDL20_DWEI_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:16              343595
wst04-VHDL20_DWEI_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:16              345194
wst04-VHDL20_DWEI_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              345953
wst04-VHDL20_DWHG_280200-2605280200-omedes--0.pdf  28-May-2026 02:45:30              349234
wst04-VHDL20_DWHG_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:17              349044
wst04-VHDL20_DWHG_280800-2605280800-omedes--0.pdf  28-May-2026 08:45:11              350609
wst04-VHDL20_DWHG_281800-2605281800-omedes--0.pdf  28-May-2026 18:45:12              357934
wst04-VHDL20_DWHG_290200-2605290200-omedes--0.pdf  29-May-2026 02:45:26              356897
wst04-VHDL20_DWHG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:16              356909
wst04-VHDL20_DWHG_290800-2605290800-omedes--0.pdf  29-May-2026 08:45:11              358653
wst04-VHDL20_DWHG_291800-2605291800-omedes--0.pdf  29-May-2026 18:45:11              357618
wst04-VHDL20_DWHH_280200-2605280200-omedes--0.pdf  28-May-2026 02:45:30              329238
wst04-VHDL20_DWHH_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:11              227978
wst04-VHDL20_DWHH_280800-2605280800-omedes--0.pdf  28-May-2026 08:45:11              329280
wst04-VHDL20_DWHH_281800-2605281800-omedes--0.pdf  28-May-2026 18:45:12              343270
wst04-VHDL20_DWHH_290200-2605290200-omedes--0.pdf  29-May-2026 02:45:26              343087
wst04-VHDL20_DWHH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:22              231593
wst04-VHDL20_DWHH_290800-2605290800-omedes--0.pdf  29-May-2026 08:45:11              343726
wst04-VHDL20_DWHH_291800-2605291800-omedes--0.pdf  29-May-2026 18:45:11              347687
wst04-VHDL20_DWLG_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:26              335475
wst04-VHDL20_DWLG_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:41              335599
wst04-VHDL20_DWLG_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:42              336091
wst04-VHDL20_DWLG_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:26              350532
wst04-VHDL20_DWLG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:26              349543
wst04-VHDL20_DWLG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              349730
wst04-VHDL20_DWLG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              350870
wst04-VHDL20_DWLG_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              343582
wst04-VHDL20_DWLH_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:22              343113
wst04-VHDL20_DWLH_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:41              343142
wst04-VHDL20_DWLH_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:47              343701
wst04-VHDL20_DWLH_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              349721
wst04-VHDL20_DWLH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              348863
wst04-VHDL20_DWLH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              348689
wst04-VHDL20_DWLH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              349032
wst04-VHDL20_DWLH_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              340094
wst04-VHDL20_DWLI_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:22              343375
wst04-VHDL20_DWLI_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:41              343419
wst04-VHDL20_DWLI_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:42              388508
wst04-VHDL20_DWLI_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              352560
wst04-VHDL20_DWLI_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              351617
wst04-VHDL20_DWLI_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:42              351726
wst04-VHDL20_DWLI_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:46              397428
wst04-VHDL20_DWLI_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:26              347832
wst04-VHDL20_DWMO_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:12              466321
wst04-VHDL20_DWMO_280200_COR-2605280200-omedes-..> 28-May-2026 02:35:10              471254
wst04-VHDL20_DWMO_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:17              466004
wst04-VHDL20_DWMO_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:22              466503
wst04-VHDL20_DWMO_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              360542
wst04-VHDL20_DWMO_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              468762
wst04-VHDL20_DWMO_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              468976
wst04-VHDL20_DWMO_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:21              468808
wst04-VHDL20_DWMO_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              360495
wst04-VHDL20_DWMO_291800_COR-2605291800-omedes-..> 29-May-2026 21:11:28              466701
wst04-VHDL20_DWMP_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:16              578627
wst04-VHDL20_DWMP_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:17              578356
wst04-VHDL20_DWMP_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:22              471951
wst04-VHDL20_DWMP_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:16              474633
wst04-VHDL20_DWMP_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:16              576973
wst04-VHDL20_DWMP_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:18              577189
wst04-VHDL20_DWMP_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:21              474164
wst04-VHDL20_DWMP_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              472844
wst04-VHDL20_DWPG_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:22              239871
wst04-VHDL20_DWPG_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:31              338209
wst04-VHDL20_DWPG_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:47              383219
wst04-VHDL20_DWPG_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              349839
wst04-VHDL20_DWPG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              245751
wst04-VHDL20_DWPG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:32              349430
wst04-VHDL20_DWPG_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              394962
wst04-VHDL20_DWPG_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:26              343044
wst04-VHDL20_DWPH_280200-2605280200-omedes--0.pdf  28-May-2026 02:30:22              238659
wst04-VHDL20_DWPH_280400-2605280400-omedes--0.pdf  28-May-2026 05:00:31              238787
wst04-VHDL20_DWPH_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:42              239273
wst04-VHDL20_DWPH_281800-2605281800-omedes--0.pdf  28-May-2026 18:31:22              246292
wst04-VHDL20_DWPH_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:21              246302
wst04-VHDL20_DWPH_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:32              246178
wst04-VHDL20_DWPH_290800-2605290800-omedes--0.pdf  29-May-2026 08:30:42              246321
wst04-VHDL20_DWPH_291800-2605291800-omedes--0.pdf  29-May-2026 18:31:20              248386
wst04-VHDL20_DWSG_280200-2605280200-omedes--0.pdf  28-May-2026 02:36:07              348496
wst04-VHDL20_DWSG_280400-2605280400-omedes--0.pdf  28-May-2026 05:33:01              349115
wst04-VHDL20_DWSG_280800-2605280800-omedes--0.pdf  28-May-2026 08:30:16              350606
wst04-VHDL20_DWSG_281800-2605281800-omedes--0.pdf  28-May-2026 18:30:18              351833
wst04-VHDL20_DWSG_290200-2605290200-omedes--0.pdf  29-May-2026 02:30:11              351342
wst04-VHDL20_DWSG_290400-2605290400-omedes--0.pdf  29-May-2026 05:00:12              352545
wst04-VHDL20_DWSG_290800-2605290800-omedes--0.pdf  29-May-2026 08:35:59              353642
wst04-VHDL20_DWSG_291800-2605291800-omedes--0.pdf  29-May-2026 18:30:16              355475