Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Jun-2026 13:46:39 4085
SXDL31_DWAV_031800 03-Jun-2026 17:01:46 13100
SXDL31_DWAV_040800 04-Jun-2026 07:42:14 8344
SXDL31_DWAV_041800 04-Jun-2026 17:27:55 5338
SXDL31_DWAV_050800 05-Jun-2026 07:14:45 11487
SXDL31_DWAV_LATEST 05-Jun-2026 07:14:45 11487
SXDL33_DWAV_040000 04-Jun-2026 10:14:04 7985
SXDL33_DWAV_050000 05-Jun-2026 10:42:44 9013
SXDL33_DWAV_LATEST 05-Jun-2026 10:42:44 9013
ber01-FWDL39_DWMS_031230-2606031230-dsw--0-ia5 03-Jun-2026 12:01:02 2223
ber01-FWDL39_DWMS_041200-2606041200-dsw--0-ia5 04-Jun-2026 10:27:06 2081
ber01-FWDL39_DWMS_051200-2606051200-dsw--0-ia5 05-Jun-2026 11:28:26 1767
ber01-VHDL13_DWEG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:12 4178
ber01-VHDL13_DWEG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:28:22 3588
ber01-VHDL13_DWEH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:12 4284
ber01-VHDL13_DWEH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:28:16 3677
ber01-VHDL13_DWEI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:28:18 4155
ber01-VHDL13_DWEI_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:28:16 3664
ber01-VHDL13_DWHG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3536
ber01-VHDL13_DWHG_040800_COR-2606040800-dsw--0-ia5 04-Jun-2026 10:49:56 3543
ber01-VHDL13_DWHG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 2633
ber01-VHDL13_DWHH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3435
ber01-VHDL13_DWHH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 2744
ber01-VHDL13_DWLG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2892
ber01-VHDL13_DWLG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:04 2279
ber01-VHDL13_DWLH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3202
ber01-VHDL13_DWLH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:04 2701
ber01-VHDL13_DWLI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3171
ber01-VHDL13_DWLI_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:04 2522
ber01-VHDL13_DWMO_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3637
ber01-VHDL13_DWMO_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 3028
ber01-VHDL13_DWMP_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3600
ber01-VHDL13_DWMP_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 3357
ber01-VHDL13_DWOG_031700-2606031700-dsw--0-ia5 03-Jun-2026 18:00:02 4472
ber01-VHDL13_DWOG_040300-2606040300-dsw--0-ia5 04-Jun-2026 03:00:02 4201
ber01-VHDL13_DWOG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 4644
ber01-VHDL13_DWOG_041700-2606041700-dsw--0-ia5 04-Jun-2026 18:00:03 3823
ber01-VHDL13_DWOG_050300-2606050300-dsw--0-ia5 05-Jun-2026 03:00:01 3142
ber01-VHDL13_DWOG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:00 3337
ber01-VHDL13_DWON_031457-2606031457-dsw--0-ia5 03-Jun-2026 14:57:17 3867
ber01-VHDL13_DWON_031705-2606031705-dsw--0-ia5 03-Jun-2026 17:05:51 3373
ber01-VHDL13_DWON_032017-2606032017-dsw--0-ia5 03-Jun-2026 20:17:32 2994
ber01-VHDL13_DWON_040008-2606040008-dsw--0-ia5 04-Jun-2026 00:08:48 2747
ber01-VHDL13_DWON_040239-2606040239-dsw--0-ia5 04-Jun-2026 02:39:41 2747
ber01-VHDL13_DWON_040527-2606040527-dsw--0-ia5 04-Jun-2026 05:27:21 3154
ber01-VHDL13_DWON_040558-2606040558-dsw--0-ia5 04-Jun-2026 05:58:47 3322
ber01-VHDL13_DWON_040806-2606040806-dsw--0-ia5 04-Jun-2026 08:06:47 3415
ber01-VHDL13_DWON_040935-2606040935-dsw--0-ia5 04-Jun-2026 09:35:26 3415
ber01-VHDL13_DWON_041457-2606041457-dsw--0-ia5 04-Jun-2026 14:57:42 3469
ber01-VHDL13_DWON_041738-2606041738-dsw--0-ia5 04-Jun-2026 17:39:03 2802
ber01-VHDL13_DWON_050143-2606050143-dsw--0-ia5 05-Jun-2026 01:43:16 2719
ber01-VHDL13_DWON_050147-2606050147-dsw--0-ia5 05-Jun-2026 01:47:55 2654
ber01-VHDL13_DWON_050526-2606050526-dsw--0-ia5 05-Jun-2026 05:26:36 2894
ber01-VHDL13_DWON_050608-2606050608-dsw--0-ia5 05-Jun-2026 06:08:22 3131
ber01-VHDL13_DWON_050938-2606050938-dsw--0-ia5 05-Jun-2026 09:38:41 3169
ber01-VHDL13_DWPG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3023
ber01-VHDL13_DWPG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:04 2858
ber01-VHDL13_DWPH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3074
ber01-VHDL13_DWPH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:04 2887
ber01-VHDL13_DWSG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 3861
ber01-VHDL13_DWSG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 2777
ber01-VHDL17_DWOG_041200-2606041200-dsw--0-ia5 04-Jun-2026 11:55:21 3105
swis2-VHDL20_DWEG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1903
swis2-VHDL20_DWEG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1803
swis2-VHDL20_DWEG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1927
swis2-VHDL20_DWEG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2192
swis2-VHDL20_DWEG_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1732
swis2-VHDL20_DWEG_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:01 1255
swis2-VHDL20_DWEG_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:01:17 1365
swis2-VHDL20_DWEG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:00 1720
swis2-VHDL20_DWEH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2108
swis2-VHDL20_DWEH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1827
swis2-VHDL20_DWEH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1931
swis2-VHDL20_DWEH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2180
swis2-VHDL20_DWEH_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1727
swis2-VHDL20_DWEH_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:01 1251
swis2-VHDL20_DWEH_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:01:17 1377
swis2-VHDL20_DWEH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:00 1786
swis2-VHDL20_DWEI_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2180
swis2-VHDL20_DWEI_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:07 1846
swis2-VHDL20_DWEI_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:01:17 1924
swis2-VHDL20_DWEI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2189
swis2-VHDL20_DWEI_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1776
swis2-VHDL20_DWEI_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:01 1291
swis2-VHDL20_DWEI_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:01:17 1416
swis2-VHDL20_DWEI_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:00 1818
swis2-VHDL20_DWHG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:45:02 2383
swis2-VHDL20_DWHG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:46:28 2063
swis2-VHDL20_DWHG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 2057
swis2-VHDL20_DWHG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:45:08 2115
swis2-VHDL20_DWHG_040800_COR-2606040800-dsw--0-ia5 04-Jun-2026 10:50:57 2122
swis2-VHDL20_DWHG_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:45:07 2139
swis2-VHDL20_DWHG_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:45:10 1544
swis2-VHDL20_DWHG_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:16 1605
swis2-VHDL20_DWHG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:45:01 1557
swis2-VHDL20_DWHH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:45:02 2350
swis2-VHDL20_DWHH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:46:28 2063
swis2-VHDL20_DWHH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 2083
swis2-VHDL20_DWHH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:45:08 2120
swis2-VHDL20_DWHH_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:45:07 2242
swis2-VHDL20_DWHH_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:45:10 1625
swis2-VHDL20_DWHH_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:16 1703
swis2-VHDL20_DWHH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:45:01 1696
swis2-VHDL20_DWLG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1194
swis2-VHDL20_DWLG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 997
swis2-VHDL20_DWLG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1212
swis2-VHDL20_DWLG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1626
swis2-VHDL20_DWLG_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:31:09 1188
swis2-VHDL20_DWLG_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:28 1178
swis2-VHDL20_DWLG_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:12 1103
swis2-VHDL20_DWLG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:21 1191
swis2-VHDL20_DWLH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1578
swis2-VHDL20_DWLH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1494
swis2-VHDL20_DWLH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1608
swis2-VHDL20_DWLH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1912
swis2-VHDL20_DWLH_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:31:09 1146
swis2-VHDL20_DWLH_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:28 1187
swis2-VHDL20_DWLH_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:12 1329
swis2-VHDL20_DWLH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:21 1417
swis2-VHDL20_DWLI_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1512
swis2-VHDL20_DWLI_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1458
swis2-VHDL20_DWLI_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1571
swis2-VHDL20_DWLI_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1871
swis2-VHDL20_DWLI_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:31:09 1192
swis2-VHDL20_DWLI_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:28 1181
swis2-VHDL20_DWLI_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:12 1302
swis2-VHDL20_DWLI_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:21 1390
swis2-VHDL20_DWMO_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1638
swis2-VHDL20_DWMO_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1562
swis2-VHDL20_DWMO_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:06 1500
swis2-VHDL20_DWMO_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2052
swis2-VHDL20_DWMO_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1478
swis2-VHDL20_DWMO_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:07 1323
swis2-VHDL20_DWMO_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:02 1499
swis2-VHDL20_DWMO_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 1555
swis2-VHDL20_DWMP_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 1922
swis2-VHDL20_DWMP_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1705
swis2-VHDL20_DWMP_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:06 1660
swis2-VHDL20_DWMP_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2039
swis2-VHDL20_DWMP_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1832
swis2-VHDL20_DWMP_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:07 1415
swis2-VHDL20_DWMP_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:02 1485
swis2-VHDL20_DWMP_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:07 1759
swis2-VHDL20_DWPG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1507
swis2-VHDL20_DWPG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1323
swis2-VHDL20_DWPG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1483
swis2-VHDL20_DWPG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1829
swis2-VHDL20_DWPG_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:31:09 1155
swis2-VHDL20_DWPG_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:28 1197
swis2-VHDL20_DWPG_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:12 1319
swis2-VHDL20_DWPG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:21 1436
swis2-VHDL20_DWPH_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:31:06 1492
swis2-VHDL20_DWPH_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:22 1335
swis2-VHDL20_DWPH_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:12 1487
swis2-VHDL20_DWPH_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:21 1833
swis2-VHDL20_DWPH_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:31:09 1155
swis2-VHDL20_DWPH_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:28 1206
swis2-VHDL20_DWPH_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:12 1280
swis2-VHDL20_DWPH_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:21 1444
swis2-VHDL20_DWSG_031800-2606031800-dsw--0-ia5 03-Jun-2026 18:30:06 2178
swis2-VHDL20_DWSG_040200-2606040200-dsw--0-ia5 04-Jun-2026 02:30:02 1988
swis2-VHDL20_DWSG_040400-2606040400-dsw--0-ia5 04-Jun-2026 05:00:16 1754
swis2-VHDL20_DWSG_040800-2606040800-dsw--0-ia5 04-Jun-2026 08:30:15 2182
swis2-VHDL20_DWSG_041800-2606041800-dsw--0-ia5 04-Jun-2026 18:30:01 1433
swis2-VHDL20_DWSG_050200-2606050200-dsw--0-ia5 05-Jun-2026 02:30:01 1137
swis2-VHDL20_DWSG_050400-2606050400-dsw--0-ia5 05-Jun-2026 05:00:16 1201
swis2-VHDL20_DWSG_050800-2606050800-dsw--0-ia5 05-Jun-2026 08:30:00 1340
wst04-VHDL20_DWEG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 240189
wst04-VHDL20_DWEG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 239446
wst04-VHDL20_DWEG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 239557
wst04-VHDL20_DWEG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 240603
wst04-VHDL20_DWEG_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:12 241238
wst04-VHDL20_DWEG_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:11 239921
wst04-VHDL20_DWEG_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:12 239785
wst04-VHDL20_DWEG_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:11 240830
wst04-VHDL20_DWEH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:12 242937
wst04-VHDL20_DWEH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 242396
wst04-VHDL20_DWEH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 242811
wst04-VHDL20_DWEH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 243862
wst04-VHDL20_DWEH_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:12 239718
wst04-VHDL20_DWEH_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:11 238662
wst04-VHDL20_DWEH_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:12 238846
wst04-VHDL20_DWEH_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:11 239953
wst04-VHDL20_DWEI_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 342566
wst04-VHDL20_DWEI_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 342205
wst04-VHDL20_DWEI_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:12 342293
wst04-VHDL20_DWEI_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:15 342802
wst04-VHDL20_DWEI_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:16 344807
wst04-VHDL20_DWEI_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:11 343322
wst04-VHDL20_DWEI_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:12 343626
wst04-VHDL20_DWEI_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:11 344963
wst04-VHDL20_DWHG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:45:12 356650
wst04-VHDL20_DWHG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:46:28 355030
wst04-VHDL20_DWHG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:22 355033
wst04-VHDL20_DWHG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:45:28 356430
wst04-VHDL20_DWHG_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:45:11 356049
wst04-VHDL20_DWHG_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:45:10 353946
wst04-VHDL20_DWHG_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:22 354587
wst04-VHDL20_DWHG_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:45:11 355579
wst04-VHDL20_DWHH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:45:12 343636
wst04-VHDL20_DWHH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:46:28 343453
wst04-VHDL20_DWHH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 236522
wst04-VHDL20_DWHH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:45:28 343844
wst04-VHDL20_DWHH_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:45:11 348655
wst04-VHDL20_DWHH_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:45:10 347624
wst04-VHDL20_DWHH_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:16 237425
wst04-VHDL20_DWHH_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:45:11 347882
wst04-VHDL20_DWLG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:28 349621
wst04-VHDL20_DWLG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 348724
wst04-VHDL20_DWLG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 349680
wst04-VHDL20_DWLG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 350147
wst04-VHDL20_DWLG_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:31:32 345302
wst04-VHDL20_DWLG_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:28 344806
wst04-VHDL20_DWLG_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:41 345148
wst04-VHDL20_DWLG_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:41 345330
wst04-VHDL20_DWLH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 343394
wst04-VHDL20_DWLH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 342503
wst04-VHDL20_DWLH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 343280
wst04-VHDL20_DWLH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 344543
wst04-VHDL20_DWLH_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:31:22 340366
wst04-VHDL20_DWLH_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:28 339932
wst04-VHDL20_DWLH_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:41 340453
wst04-VHDL20_DWLH_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:41 340696
wst04-VHDL20_DWLI_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 336805
wst04-VHDL20_DWLI_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 335885
wst04-VHDL20_DWLI_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:41 336660
wst04-VHDL20_DWLI_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 382520
wst04-VHDL20_DWLI_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:31:22 336383
wst04-VHDL20_DWLI_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:23 335904
wst04-VHDL20_DWLI_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:41 336432
wst04-VHDL20_DWLI_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:47 381219
wst04-VHDL20_DWMO_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 356934
wst04-VHDL20_DWMO_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:17 469181
wst04-VHDL20_DWMO_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 468988
wst04-VHDL20_DWMO_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:23 469700
wst04-VHDL20_DWMO_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:18 352221
wst04-VHDL20_DWMO_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:17 463127
wst04-VHDL20_DWMO_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:16 463361
wst04-VHDL20_DWMO_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:21 463318
wst04-VHDL20_DWMP_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:21 482147
wst04-VHDL20_DWMP_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:17 598726
wst04-VHDL20_DWMP_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 599002
wst04-VHDL20_DWMP_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:23 482528
wst04-VHDL20_DWMP_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:18 467763
wst04-VHDL20_DWMP_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:17 580832
wst04-VHDL20_DWMP_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:16 580314
wst04-VHDL20_DWMP_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:21 466944
wst04-VHDL20_DWPG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:28 348957
wst04-VHDL20_DWPG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:28 243413
wst04-VHDL20_DWPG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:32 348851
wst04-VHDL20_DWPG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 394673
wst04-VHDL20_DWPG_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:31:22 346347
wst04-VHDL20_DWPG_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:23 242879
wst04-VHDL20_DWPG_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:32 346474
wst04-VHDL20_DWPG_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:47 391245
wst04-VHDL20_DWPH_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:31:24 251736
wst04-VHDL20_DWPH_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:22 250723
wst04-VHDL20_DWPH_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:32 251601
wst04-VHDL20_DWPH_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:46 252096
wst04-VHDL20_DWPH_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:31:22 251137
wst04-VHDL20_DWPH_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:23 250738
wst04-VHDL20_DWPH_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:32 251214
wst04-VHDL20_DWPH_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:41 251398
wst04-VHDL20_DWSG_031800-2606031800-omedes--0.pdf 03-Jun-2026 18:30:17 349986
wst04-VHDL20_DWSG_040200-2606040200-omedes--0.pdf 04-Jun-2026 02:30:11 349643
wst04-VHDL20_DWSG_040400-2606040400-omedes--0.pdf 04-Jun-2026 05:00:16 349606
wst04-VHDL20_DWSG_040800-2606040800-omedes--0.pdf 04-Jun-2026 08:30:17 350514
wst04-VHDL20_DWSG_041800-2606041800-omedes--0.pdf 04-Jun-2026 18:30:16 349834
wst04-VHDL20_DWSG_050200-2606050200-omedes--0.pdf 05-Jun-2026 02:30:11 349683
wst04-VHDL20_DWSG_050400-2606050400-omedes--0.pdf 05-Jun-2026 05:00:12 350083
wst04-VHDL20_DWSG_050800-2606050800-omedes--0.pdf 05-Jun-2026 08:30:17 350998