Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_120600 12-Aug-2026 12:35:27 5392
FPDL13_DWMZ_130600 13-Aug-2026 14:13:04 5380
SXDL31_DWAV_120800 12-Aug-2026 07:45:16 10904
SXDL31_DWAV_121800 12-Aug-2026 16:37:20 4401
SXDL31_DWAV_130800 13-Aug-2026 07:13:24 6136
SXDL31_DWAV_131800 13-Aug-2026 16:31:58 4765
SXDL31_DWAV_LATEST 13-Aug-2026 16:31:58 4765
SXDL33_DWAV_120000 12-Aug-2026 10:38:24 7106
SXDL33_DWAV_130000 13-Aug-2026 10:03:29 8167
SXDL33_DWAV_LATEST 13-Aug-2026 10:03:29 8167
ber01-FWDL39_DWMS_121200-2608121200-dsw--0-ia5 12-Aug-2026 10:51:39 1318
ber01-FWDL39_DWMS_131200-2608131200-dsw--0-ia5 13-Aug-2026 11:49:29 1560
ber01-VHDL13_DWEG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2632
ber01-VHDL13_DWEG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2824
ber01-VHDL13_DWEH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2599
ber01-VHDL13_DWEH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2675
ber01-VHDL13_DWEI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:28:18 2335
ber01-VHDL13_DWEI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:28:18 2722
ber01-VHDL13_DWHG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 2798
ber01-VHDL13_DWHG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 3573
ber01-VHDL13_DWHH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 2758
ber01-VHDL13_DWHH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 3033
ber01-VHDL13_DWLG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2108
ber01-VHDL13_DWLG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2647
ber01-VHDL13_DWLH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2164
ber01-VHDL13_DWLH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2597
ber01-VHDL13_DWLI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2147
ber01-VHDL13_DWLI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2474
ber01-VHDL13_DWMO_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2307
ber01-VHDL13_DWMO_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2573
ber01-VHDL13_DWMP_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2040
ber01-VHDL13_DWMP_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2348
ber01-VHDL13_DWOG_120300-2608120300-dsw--0-ia5 12-Aug-2026 03:00:04 2862
ber01-VHDL13_DWOG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2753
ber01-VHDL13_DWOG_121700-2608121700-dsw--0-ia5 12-Aug-2026 18:00:03 2429
ber01-VHDL13_DWOG_130300-2608130300-dsw--0-ia5 13-Aug-2026 03:00:07 2921
ber01-VHDL13_DWOG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2826
ber01-VHDL13_DWOG_131700-2608131700-dsw--0-ia5 13-Aug-2026 18:00:10 2692
ber01-VHDL13_DWON_120003-2608120003-dsw--0-ia5 12-Aug-2026 00:03:07 3023
ber01-VHDL13_DWON_120135-2608120135-dsw--0-ia5 12-Aug-2026 01:35:53 2999
ber01-VHDL13_DWON_120249-2608120249-dsw--0-ia5 12-Aug-2026 02:50:46 2999
ber01-VHDL13_DWON_120309-2608120309-dsw--0-ia5 12-Aug-2026 03:10:12 2999
ber01-VHDL13_DWON_120527-2608120527-dsw--0-ia5 12-Aug-2026 05:28:04 3119
ber01-VHDL13_DWON_120622-2608120622-dsw--0-ia5 12-Aug-2026 06:22:18 3116
ber01-VHDL13_DWON_121445-2608121445-dsw--0-ia5 12-Aug-2026 14:45:46 2755
ber01-VHDL13_DWON_121715-2608121715-dsw--0-ia5 12-Aug-2026 17:15:43 2664
ber01-VHDL13_DWON_121836-2608121836-dsw--0-ia5 12-Aug-2026 18:36:54 2683
ber01-VHDL13_DWON_122103-2608122103-dsw--0-ia5 12-Aug-2026 21:03:23 2673
ber01-VHDL13_DWON_130001-2608130001-dsw--0-ia5 13-Aug-2026 00:01:47 3108
ber01-VHDL13_DWON_130134-2608130134-dsw--0-ia5 13-Aug-2026 01:35:12 3084
ber01-VHDL13_DWON_130248-2608130248-dsw--0-ia5 13-Aug-2026 02:48:45 3088
ber01-VHDL13_DWON_130525-2608130525-dsw--0-ia5 13-Aug-2026 05:25:33 3118
ber01-VHDL13_DWON_130609-2608130609-dsw--0-ia5 13-Aug-2026 06:09:19 3241
ber01-VHDL13_DWON_130817-2608130817-dsw--0-ia5 13-Aug-2026 08:17:59 3241
ber01-VHDL13_DWON_131439-2608131439-dsw--0-ia5 13-Aug-2026 14:40:50 3228
ber01-VHDL13_DWON_131440-2608131440-dsw--0-ia5 13-Aug-2026 14:40:54 3228
ber01-VHDL13_DWON_131722-2608131722-dsw--0-ia5 13-Aug-2026 17:22:38 3017
ber01-VHDL13_DWPG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2031
ber01-VHDL13_DWPG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2485
ber01-VHDL13_DWPH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 2001
ber01-VHDL13_DWPH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 2528
ber01-VHDL13_DWSG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 1687
ber01-VHDL13_DWSG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 2263
ber01-VHDL17_DWOG_121200-2608121200-dsw--0-ia5 12-Aug-2026 11:02:48 2460
ber01-VHDL17_DWOG_131200-2608131200-dsw--0-ia5 13-Aug-2026 11:40:37 2518
swis2-VHDL20_DWEG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 787
swis2-VHDL20_DWEG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 787
swis2-VHDL20_DWEG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1073
swis2-VHDL20_DWEG_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:09 1227
swis2-VHDL20_DWEG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 793
swis2-VHDL20_DWEG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:15 786
swis2-VHDL20_DWEG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1251
swis2-VHDL20_DWEG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1506
swis2-VHDL20_DWEH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 741
swis2-VHDL20_DWEH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 741
swis2-VHDL20_DWEH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1157
swis2-VHDL20_DWEH_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:09 1129
swis2-VHDL20_DWEH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 807
swis2-VHDL20_DWEH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:19 798
swis2-VHDL20_DWEH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1144
swis2-VHDL20_DWEH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1548
swis2-VHDL20_DWEI_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 810
swis2-VHDL20_DWEI_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:01:18 810
swis2-VHDL20_DWEI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1096
swis2-VHDL20_DWEI_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:09 1250
swis2-VHDL20_DWEI_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 813
swis2-VHDL20_DWEI_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:01:19 806
swis2-VHDL20_DWEI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1274
swis2-VHDL20_DWEI_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1536
swis2-VHDL20_DWHG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:45:06 962
swis2-VHDL20_DWHG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 959
swis2-VHDL20_DWHG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:45:23 1115
swis2-VHDL20_DWHG_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:45:08 1046
swis2-VHDL20_DWHG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:46:57 974
swis2-VHDL20_DWHG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 971
swis2-VHDL20_DWHG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:45:09 1166
swis2-VHDL20_DWHG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:45:05 1247
swis2-VHDL20_DWHH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:45:06 962
swis2-VHDL20_DWHH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 962
swis2-VHDL20_DWHH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:45:23 1113
swis2-VHDL20_DWHH_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:45:08 1061
swis2-VHDL20_DWHH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:46:57 976
swis2-VHDL20_DWHH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 976
swis2-VHDL20_DWHH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:45:09 1045
swis2-VHDL20_DWHH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:45:05 1129
swis2-VHDL20_DWLG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 929
swis2-VHDL20_DWLG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 952
swis2-VHDL20_DWLG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1040
swis2-VHDL20_DWLG_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:31:08 1112
swis2-VHDL20_DWLG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1028
swis2-VHDL20_DWLG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1098
swis2-VHDL20_DWLG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1209
swis2-VHDL20_DWLG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1182
swis2-VHDL20_DWLH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 932
swis2-VHDL20_DWLH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 956
swis2-VHDL20_DWLH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1044
swis2-VHDL20_DWLH_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:31:08 1252
swis2-VHDL20_DWLH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1032
swis2-VHDL20_DWLH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1102
swis2-VHDL20_DWLH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1349
swis2-VHDL20_DWLH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1186
swis2-VHDL20_DWLI_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 931
swis2-VHDL20_DWLI_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 954
swis2-VHDL20_DWLI_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1042
swis2-VHDL20_DWLI_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:31:08 1131
swis2-VHDL20_DWLI_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1009
swis2-VHDL20_DWLI_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1103
swis2-VHDL20_DWLI_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1255
swis2-VHDL20_DWLI_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1184
swis2-VHDL20_DWMO_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 874
swis2-VHDL20_DWMO_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:03 822
swis2-VHDL20_DWMO_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 1070
swis2-VHDL20_DWMO_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:09 1320
swis2-VHDL20_DWMO_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 848
swis2-VHDL20_DWMO_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:07 856
swis2-VHDL20_DWMO_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1195
swis2-VHDL20_DWMO_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1152
swis2-VHDL20_DWMP_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 872
swis2-VHDL20_DWMP_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:03 819
swis2-VHDL20_DWMP_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:04 982
swis2-VHDL20_DWMP_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:09 1323
swis2-VHDL20_DWMP_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 840
swis2-VHDL20_DWMP_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:07 847
swis2-VHDL20_DWMP_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:04 1359
swis2-VHDL20_DWMP_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1442
swis2-VHDL20_DWPG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 946
swis2-VHDL20_DWPG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 970
swis2-VHDL20_DWPG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 1058
swis2-VHDL20_DWPG_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:31:08 1232
swis2-VHDL20_DWPG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 1033
swis2-VHDL20_DWPG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 1110
swis2-VHDL20_DWPG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1338
swis2-VHDL20_DWPG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 1200
swis2-VHDL20_DWPH_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:29 697
swis2-VHDL20_DWPH_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:14 720
swis2-VHDL20_DWPH_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:26 811
swis2-VHDL20_DWPH_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:31:08 985
swis2-VHDL20_DWPH_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:28 787
swis2-VHDL20_DWPH_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:13 858
swis2-VHDL20_DWPH_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:37 1085
swis2-VHDL20_DWPH_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:31:07 950
swis2-VHDL20_DWSG_120200-2608120200-dsw--0-ia5 12-Aug-2026 02:30:13 793
swis2-VHDL20_DWSG_120400-2608120400-dsw--0-ia5 12-Aug-2026 05:00:20 719
swis2-VHDL20_DWSG_120800-2608120800-dsw--0-ia5 12-Aug-2026 08:30:08 725
swis2-VHDL20_DWSG_121800-2608121800-dsw--0-ia5 12-Aug-2026 18:30:07 1095
swis2-VHDL20_DWSG_130200-2608130200-dsw--0-ia5 13-Aug-2026 02:30:03 744
swis2-VHDL20_DWSG_130400-2608130400-dsw--0-ia5 13-Aug-2026 05:00:19 750
swis2-VHDL20_DWSG_130800-2608130800-dsw--0-ia5 13-Aug-2026 08:30:08 1214
swis2-VHDL20_DWSG_131800-2608131800-dsw--0-ia5 13-Aug-2026 18:30:13 1405
wst04-VHDL20_DWEG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 235239
wst04-VHDL20_DWEG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 234750
wst04-VHDL20_DWEG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:14 236054
wst04-VHDL20_DWEG_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:30:19 234675
wst04-VHDL20_DWEG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 232751
wst04-VHDL20_DWEG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 232784
wst04-VHDL20_DWEG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 234668
wst04-VHDL20_DWEG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 243995
wst04-VHDL20_DWEH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 233404
wst04-VHDL20_DWEH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 233228
wst04-VHDL20_DWEH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:14 234987
wst04-VHDL20_DWEH_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:30:13 234379
wst04-VHDL20_DWEH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 233153
wst04-VHDL20_DWEH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 233143
wst04-VHDL20_DWEH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 234893
wst04-VHDL20_DWEH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 237584
wst04-VHDL20_DWEI_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:27 338719
wst04-VHDL20_DWEI_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:18 338148
wst04-VHDL20_DWEI_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 339683
wst04-VHDL20_DWEI_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:30:19 334229
wst04-VHDL20_DWEI_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 332135
wst04-VHDL20_DWEI_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 332169
wst04-VHDL20_DWEI_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 333533
wst04-VHDL20_DWEI_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:25 348283
wst04-VHDL20_DWHG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:45:14 338693
wst04-VHDL20_DWHG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:20 338474
wst04-VHDL20_DWHG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:45:24 339500
wst04-VHDL20_DWHG_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:45:14 335408
wst04-VHDL20_DWHG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:46:57 334424
wst04-VHDL20_DWHG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 334210
wst04-VHDL20_DWHG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:45:22 335372
wst04-VHDL20_DWHG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:45:15 348667
wst04-VHDL20_DWHH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:45:14 326674
wst04-VHDL20_DWHH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:20 225315
wst04-VHDL20_DWHH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:45:24 326525
wst04-VHDL20_DWHH_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:45:14 329746
wst04-VHDL20_DWHH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:46:57 329008
wst04-VHDL20_DWHH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 227528
wst04-VHDL20_DWHH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:45:22 329280
wst04-VHDL20_DWHH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:45:15 331779
wst04-VHDL20_DWLG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 332507
wst04-VHDL20_DWLG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 332361
wst04-VHDL20_DWLG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 332775
wst04-VHDL20_DWLG_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:31:24 328604
wst04-VHDL20_DWLG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 328387
wst04-VHDL20_DWLG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:43 327778
wst04-VHDL20_DWLG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 328204
wst04-VHDL20_DWLG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 333684
wst04-VHDL20_DWLH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 330807
wst04-VHDL20_DWLH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 330660
wst04-VHDL20_DWLH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 331072
wst04-VHDL20_DWLH_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:31:28 333415
wst04-VHDL20_DWLH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 333053
wst04-VHDL20_DWLH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:43 332448
wst04-VHDL20_DWLH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:31:06 333025
wst04-VHDL20_DWLH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:31 340662
wst04-VHDL20_DWLI_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 326254
wst04-VHDL20_DWLI_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:44 326107
wst04-VHDL20_DWLI_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 371107
wst04-VHDL20_DWLI_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:31:24 329155
wst04-VHDL20_DWLI_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 328916
wst04-VHDL20_DWLI_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:43 328329
wst04-VHDL20_DWLI_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 373366
wst04-VHDL20_DWLI_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 337800
wst04-VHDL20_DWMO_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 443052
wst04-VHDL20_DWMO_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 442831
wst04-VHDL20_DWMO_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 443250
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wst04-VHDL20_DWMO_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 440803
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wst04-VHDL20_DWMO_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 351553
wst04-VHDL20_DWMP_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:27 573767
wst04-VHDL20_DWMP_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:18 573606
wst04-VHDL20_DWMP_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:26 470739
wst04-VHDL20_DWMP_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:30:19 453173
wst04-VHDL20_DWMP_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 554632
wst04-VHDL20_DWMP_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:19 554909
wst04-VHDL20_DWMP_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 453443
wst04-VHDL20_DWMP_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 468688
wst04-VHDL20_DWPG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 237565
wst04-VHDL20_DWPG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:34 336890
wst04-VHDL20_DWPG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:49 381868
wst04-VHDL20_DWPG_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:31:24 336530
wst04-VHDL20_DWPG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 236997
wst04-VHDL20_DWPG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:33 335430
wst04-VHDL20_DWPG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 380728
wst04-VHDL20_DWPG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 342177
wst04-VHDL20_DWPH_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:29 237910
wst04-VHDL20_DWPH_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:34 237679
wst04-VHDL20_DWPH_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:43 238142
wst04-VHDL20_DWPH_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:31:24 235928
wst04-VHDL20_DWPH_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:28 235579
wst04-VHDL20_DWPH_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:33 235042
wst04-VHDL20_DWPH_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:58 235495
wst04-VHDL20_DWPH_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:31:29 239603
wst04-VHDL20_DWSG_120200-2608120200-omedes--0.pdf 12-Aug-2026 02:30:15 344757
wst04-VHDL20_DWSG_120400-2608120400-omedes--0.pdf 12-Aug-2026 05:00:14 344476
wst04-VHDL20_DWSG_120800-2608120800-omedes--0.pdf 12-Aug-2026 08:30:18 344369
wst04-VHDL20_DWSG_121800-2608121800-omedes--0.pdf 12-Aug-2026 18:30:13 343538
wst04-VHDL20_DWSG_130200-2608130200-omedes--0.pdf 13-Aug-2026 02:30:23 343015
wst04-VHDL20_DWSG_130400-2608130400-omedes--0.pdf 13-Aug-2026 05:00:13 343119
wst04-VHDL20_DWSG_130800-2608130800-omedes--0.pdf 13-Aug-2026 08:30:23 343691
wst04-VHDL20_DWSG_131800-2608131800-omedes--0.pdf 13-Aug-2026 18:30:13 354185