Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Jul-2026 11:15:00 3908
FPDL13_DWMZ_140600 14-Jul-2026 12:21:29 3860
SXDL31_DWAV_130800 13-Jul-2026 08:46:02 12682
SXDL31_DWAV_131800 13-Jul-2026 17:11:43 7983
SXDL31_DWAV_140800 14-Jul-2026 08:04:05 13043
SXDL31_DWAV_141800 14-Jul-2026 17:55:04 9654
SXDL31_DWAV_LATEST 14-Jul-2026 17:55:04 9654
SXDL33_DWAV_130000 13-Jul-2026 10:33:15 8260
SXDL33_DWAV_140000 14-Jul-2026 10:16:40 11362
SXDL33_DWAV_LATEST 14-Jul-2026 10:16:40 11362
ber01-FWDL39_DWMS_131200-2607131200-dsw--0-ia5 13-Jul-2026 10:48:27 1343
ber01-FWDL39_DWMS_141200-2607141200-dsw--0-ia5 14-Jul-2026 10:32:45 1859
ber01-VHDL13_DWEG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:16 3456
ber01-VHDL13_DWEG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3722
ber01-VHDL13_DWEG_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:15 3902
ber01-VHDL13_DWEH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:16 3399
ber01-VHDL13_DWEH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3377
ber01-VHDL13_DWEH_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:31 3348
ber01-VHDL13_DWEI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:28:11 3238
ber01-VHDL13_DWEI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:28:16 3591
ber01-VHDL13_DWEI_140800_COR-2607140800-dsw--0-ia5 14-Jul-2026 18:40:51 3828
ber01-VHDL13_DWHG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3346
ber01-VHDL13_DWHG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:07 3334
ber01-VHDL13_DWHH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3223
ber01-VHDL13_DWHH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:07 3122
ber01-VHDL13_DWLG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3178
ber01-VHDL13_DWLG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:51:03 3448
ber01-VHDL13_DWLG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3120
ber01-VHDL13_DWLH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3252
ber01-VHDL13_DWLH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3329
ber01-VHDL13_DWLI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 2890
ber01-VHDL13_DWLI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2934
ber01-VHDL13_DWMO_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3226
ber01-VHDL13_DWMO_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 3434
ber01-VHDL13_DWMP_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3215
ber01-VHDL13_DWMP_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 3542
ber01-VHDL13_DWOG_130300-2607130300-dsw--0-ia5 13-Jul-2026 03:00:02 4000
ber01-VHDL13_DWOG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 3872
ber01-VHDL13_DWOG_131700-2607131700-dsw--0-ia5 13-Jul-2026 18:00:02 4468
ber01-VHDL13_DWOG_140300-2607140300-dsw--0-ia5 14-Jul-2026 03:00:02 4072
ber01-VHDL13_DWOG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 4211
ber01-VHDL13_DWOG_141700-2607141700-dsw--0-ia5 14-Jul-2026 18:00:02 4792
ber01-VHDL13_DWON_122257-2607122257-dsw--0-ia5 12-Jul-2026 22:57:31 3430
ber01-VHDL13_DWON_130220-2607130220-dsw--0-ia5 13-Jul-2026 02:20:27 3450
ber01-VHDL13_DWON_130516-2607130516-dsw--0-ia5 13-Jul-2026 05:16:31 3460
ber01-VHDL13_DWON_130735-2607130735-dsw--0-ia5 13-Jul-2026 07:35:21 3377
ber01-VHDL13_DWON_131054-2607131054-dsw--0-ia5 13-Jul-2026 10:54:27 3442
ber01-VHDL13_DWON_131403-2607131403-dsw--0-ia5 13-Jul-2026 14:03:17 3984
ber01-VHDL13_DWON_131742-2607131742-dsw--0-ia5 13-Jul-2026 17:43:04 3845
ber01-VHDL13_DWON_132022-2607132022-dsw--0-ia5 13-Jul-2026 20:22:46 3687
ber01-VHDL13_DWON_140015-2607140015-dsw--0-ia5 14-Jul-2026 00:15:36 3484
ber01-VHDL13_DWON_140253-2607140253-dsw--0-ia5 14-Jul-2026 02:53:29 3484
ber01-VHDL13_DWON_140513-2607140513-dsw--0-ia5 14-Jul-2026 05:13:16 3835
ber01-VHDL13_DWON_140604-2607140604-dsw--0-ia5 14-Jul-2026 06:04:52 3784
ber01-VHDL13_DWON_140816-2607140816-dsw--0-ia5 14-Jul-2026 08:16:22 3811
ber01-VHDL13_DWON_140910-2607140910-dsw--0-ia5 14-Jul-2026 09:10:42 3811
ber01-VHDL13_DWON_141502-2607141502-dsw--0-ia5 14-Jul-2026 15:02:22 3653
ber01-VHDL13_DWPG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 3614
ber01-VHDL13_DWPG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3603
ber01-VHDL13_DWPH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:09 2828
ber01-VHDL13_DWPH_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:07:36 3224
ber01-VHDL13_DWPH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2656
ber01-VHDL13_DWSG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 4152
ber01-VHDL13_DWSG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 09:16:06 4156
ber01-VHDL13_DWSG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 3713
ber01-VHDL17_DWOG_131200-2607131200-dsw--0-ia5 13-Jul-2026 12:12:11 2688
ber01-VHDL17_DWOG_141200-2607141200-dsw--0-ia5 14-Jul-2026 11:30:42 2704
swis2-VHDL20_DWEG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1208
swis2-VHDL20_DWEG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1622
swis2-VHDL20_DWEG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1902
swis2-VHDL20_DWEG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2340
swis2-VHDL20_DWEG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1982
swis2-VHDL20_DWEG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1725
swis2-VHDL20_DWEG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2189
swis2-VHDL20_DWEG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2669
swis2-VHDL20_DWEH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1096
swis2-VHDL20_DWEH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1583
swis2-VHDL20_DWEH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1969
swis2-VHDL20_DWEH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2374
swis2-VHDL20_DWEH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1976
swis2-VHDL20_DWEH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1924
swis2-VHDL20_DWEH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 1943
swis2-VHDL20_DWEH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2318
swis2-VHDL20_DWEI_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1177
swis2-VHDL20_DWEI_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:01:23 1587
swis2-VHDL20_DWEI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1869
swis2-VHDL20_DWEI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2366
swis2-VHDL20_DWEI_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1784
swis2-VHDL20_DWEI_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:01:15 1991
swis2-VHDL20_DWEI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2209
swis2-VHDL20_DWEI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2633
swis2-VHDL20_DWHG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:45:12 1621
swis2-VHDL20_DWHG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1448
swis2-VHDL20_DWHG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:45:19 1565
swis2-VHDL20_DWHG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1680
swis2-VHDL20_DWHG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:45:34 1558
swis2-VHDL20_DWHG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1559
swis2-VHDL20_DWHG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:45:14 1610
swis2-VHDL20_DWHG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1616
swis2-VHDL20_DWHH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:45:12 1532
swis2-VHDL20_DWHH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1379
swis2-VHDL20_DWHH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:45:19 1496
swis2-VHDL20_DWHH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:45:11 1612
swis2-VHDL20_DWHH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:45:34 1336
swis2-VHDL20_DWHH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1343
swis2-VHDL20_DWHH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:45:14 1474
swis2-VHDL20_DWHH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:45:09 1301
swis2-VHDL20_DWLG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1159
swis2-VHDL20_DWLG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1527
swis2-VHDL20_DWLG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1647
swis2-VHDL20_DWLG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:52:07 1780
swis2-VHDL20_DWLG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1508
swis2-VHDL20_DWLG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1519
swis2-VHDL20_DWLG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1365
swis2-VHDL20_DWLG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1484
swis2-VHDL20_DWLG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1667
swis2-VHDL20_DWLH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1427
swis2-VHDL20_DWLH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1658
swis2-VHDL20_DWLH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1954
swis2-VHDL20_DWLH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2032
swis2-VHDL20_DWLH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1973
swis2-VHDL20_DWLH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1533
swis2-VHDL20_DWLH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1697
swis2-VHDL20_DWLH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1469
swis2-VHDL20_DWLI_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1224
swis2-VHDL20_DWLI_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1527
swis2-VHDL20_DWLI_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1801
swis2-VHDL20_DWLI_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1680
swis2-VHDL20_DWLI_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1536
swis2-VHDL20_DWLI_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1373
swis2-VHDL20_DWLI_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1484
swis2-VHDL20_DWLI_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1388
swis2-VHDL20_DWMO_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1433
swis2-VHDL20_DWMO_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:06 1396
swis2-VHDL20_DWMO_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1620
swis2-VHDL20_DWMO_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1836
swis2-VHDL20_DWMO_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 2018
swis2-VHDL20_DWMO_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:01 1547
swis2-VHDL20_DWMO_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 1875
swis2-VHDL20_DWMO_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1857
swis2-VHDL20_DWMP_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:11 1607
swis2-VHDL20_DWMP_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:06 1596
swis2-VHDL20_DWMP_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1627
swis2-VHDL20_DWMP_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:05 1966
swis2-VHDL20_DWMP_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1727
swis2-VHDL20_DWMP_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:01 1606
swis2-VHDL20_DWMP_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:03 1933
swis2-VHDL20_DWMP_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 1697
swis2-VHDL20_DWPG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1420
swis2-VHDL20_DWPG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1610
swis2-VHDL20_DWPG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1908
swis2-VHDL20_DWPG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 2012
swis2-VHDL20_DWPG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1591
swis2-VHDL20_DWPG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1668
swis2-VHDL20_DWPG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1818
swis2-VHDL20_DWPG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1569
swis2-VHDL20_DWPH_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:23 1099
swis2-VHDL20_DWPH_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1393
swis2-VHDL20_DWPH_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:22 1714
swis2-VHDL20_DWPH_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 15:08:21 1886
swis2-VHDL20_DWPH_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:31:01 1501
swis2-VHDL20_DWPH_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:25 1209
swis2-VHDL20_DWPH_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:11 1184
swis2-VHDL20_DWPH_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:28 1440
swis2-VHDL20_DWPH_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:31:01 1642
swis2-VHDL20_DWSG_130200-2607130200-dsw--0-ia5 13-Jul-2026 02:30:04 1548
swis2-VHDL20_DWSG_130400-2607130400-dsw--0-ia5 13-Jul-2026 05:00:16 1638
swis2-VHDL20_DWSG_130800-2607130800-dsw--0-ia5 13-Jul-2026 08:30:03 1884
swis2-VHDL20_DWSG_130800_COR-2607130800-dsw--0-ia5 13-Jul-2026 09:16:06 1888
swis2-VHDL20_DWSG_131800-2607131800-dsw--0-ia5 13-Jul-2026 18:30:11 2014
swis2-VHDL20_DWSG_140200-2607140200-dsw--0-ia5 14-Jul-2026 02:30:04 1932
swis2-VHDL20_DWSG_140400-2607140400-dsw--0-ia5 14-Jul-2026 05:00:17 1680
swis2-VHDL20_DWSG_140800-2607140800-dsw--0-ia5 14-Jul-2026 08:30:01 2123
swis2-VHDL20_DWSG_141800-2607141800-dsw--0-ia5 14-Jul-2026 18:30:05 2273
wst04-VHDL20_DWEG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 236700
wst04-VHDL20_DWEG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 237388
wst04-VHDL20_DWEG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:12 238203
wst04-VHDL20_DWEG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 250466
wst04-VHDL20_DWEG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 249549
wst04-VHDL20_DWEG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 249413
wst04-VHDL20_DWEG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 250338
wst04-VHDL20_DWEG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 243699
wst04-VHDL20_DWEH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 239829
wst04-VHDL20_DWEH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 240857
wst04-VHDL20_DWEH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:12 241961
wst04-VHDL20_DWEH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:11 245588
wst04-VHDL20_DWEH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 245626
wst04-VHDL20_DWEH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 245594
wst04-VHDL20_DWEH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 246272
wst04-VHDL20_DWEH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:16 238368
wst04-VHDL20_DWEI_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 342281
wst04-VHDL20_DWEI_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 343629
wst04-VHDL20_DWEI_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:16 343974
wst04-VHDL20_DWEI_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 359237
wst04-VHDL20_DWEI_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 358667
wst04-VHDL20_DWEI_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 358853
wst04-VHDL20_DWEI_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:11 359106
wst04-VHDL20_DWEI_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 351459
wst04-VHDL20_DWHG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:45:12 345367
wst04-VHDL20_DWHG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 344999
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wst04-VHDL20_DWHG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:45:14 351236
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wst04-VHDL20_DWHH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 226162
wst04-VHDL20_DWHH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:45:19 335360
wst04-VHDL20_DWHH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:45:11 332372
wst04-VHDL20_DWHH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:45:34 332054
wst04-VHDL20_DWHH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:17 225783
wst04-VHDL20_DWHH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:45:14 332497
wst04-VHDL20_DWHH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:45:11 332131
wst04-VHDL20_DWLG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 346598
wst04-VHDL20_DWLG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:42 347336
wst04-VHDL20_DWLG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:40 348512
wst04-VHDL20_DWLG_130800_COR-2607130800-omedes-..> 13-Jul-2026 15:51:45 348285
wst04-VHDL20_DWLG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 347717
wst04-VHDL20_DWLG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:27 347564
wst04-VHDL20_DWLG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:41 347111
wst04-VHDL20_DWLG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:48 347326
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wst04-VHDL20_DWLH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:48 345852
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wst04-VHDL20_DWLH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 351134
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wst04-VHDL20_DWLH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:41 350184
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wst04-VHDL20_DWLI_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:42 384938
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wst04-VHDL20_DWLI_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 347904
wst04-VHDL20_DWLI_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:41 347864
wst04-VHDL20_DWLI_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:41 392628
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wst04-VHDL20_DWMO_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:16 465828
wst04-VHDL20_DWMO_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:16 464139
wst04-VHDL20_DWMO_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 355746
wst04-VHDL20_DWMO_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 464205
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wst04-VHDL20_DWMP_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:22 472481
wst04-VHDL20_DWMP_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 461312
wst04-VHDL20_DWMP_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 562238
wst04-VHDL20_DWMP_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:17 561925
wst04-VHDL20_DWMP_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:22 460161
wst04-VHDL20_DWMP_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 481870
wst04-VHDL20_DWPG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 243535
wst04-VHDL20_DWPG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:30 349729
wst04-VHDL20_DWPG_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:40 395564
wst04-VHDL20_DWPG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 354333
wst04-VHDL20_DWPG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 246600
wst04-VHDL20_DWPG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:31 352597
wst04-VHDL20_DWPG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:41 397536
wst04-VHDL20_DWPG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 347925
wst04-VHDL20_DWPH_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:23 245623
wst04-VHDL20_DWPH_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:30 246349
wst04-VHDL20_DWPH_130800-2607130800-omedes--0.pdf 13-Jul-2026 08:30:42 246743
wst04-VHDL20_DWPH_130800_COR-2607130800-omedes-..> 13-Jul-2026 15:08:07 251260
wst04-VHDL20_DWPH_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:31:27 250131
wst04-VHDL20_DWPH_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:25 249188
wst04-VHDL20_DWPH_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:31 249250
wst04-VHDL20_DWPH_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:41 249533
wst04-VHDL20_DWPH_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:31:24 247426
wst04-VHDL20_DWSG_130200-2607130200-omedes--0.pdf 13-Jul-2026 02:30:11 352578
wst04-VHDL20_DWSG_130400-2607130400-omedes--0.pdf 13-Jul-2026 05:00:12 352130
wst04-VHDL20_DWSG_130800-2607130800-omedes--0.pdf 13-Jul-2026 09:16:17 352360
wst04-VHDL20_DWSG_131800-2607131800-omedes--0.pdf 13-Jul-2026 18:30:17 355294
wst04-VHDL20_DWSG_140200-2607140200-omedes--0.pdf 14-Jul-2026 02:30:16 356357
wst04-VHDL20_DWSG_140400-2607140400-omedes--0.pdf 14-Jul-2026 05:00:11 355099
wst04-VHDL20_DWSG_140800-2607140800-omedes--0.pdf 14-Jul-2026 08:30:22 355486
wst04-VHDL20_DWSG_141800-2607141800-omedes--0.pdf 14-Jul-2026 18:30:18 361799