Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_060600 06-Mar-2026 14:14:59 3268
FPDL13_DWMZ_070600 07-Mar-2026 12:26:09 11913
SXDL31_DWAV_060800 06-Mar-2026 09:05:08 12624
SXDL31_DWAV_061800 06-Mar-2026 17:12:33 3429
SXDL31_DWAV_070800 07-Mar-2026 08:01:15 5839
SXDL31_DWAV_071800 07-Mar-2026 17:33:37 6449
SXDL31_DWAV_LATEST 07-Mar-2026 17:33:37 6449
SXDL33_DWAV_060000 06-Mar-2026 10:27:55 5630
SXDL33_DWAV_070000 07-Mar-2026 11:29:13 11483
SXDL33_DWAV_LATEST 07-Mar-2026 11:29:13 11483
ber01-FWDL39_DWMS_061230-2603061230-dsw--0-ia5 06-Mar-2026 13:07:21 1332
ber01-FWDL39_DWMS_071230-2603071230-dsw--0-ia5 07-Mar-2026 12:39:17 1150
ber01-VHDL13_DWEH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:11 2259
ber01-VHDL13_DWEH_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:17 2474
ber01-VHDL13_DWEH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:16 2477
ber01-VHDL13_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2559
ber01-VHDL13_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2590
ber01-VHDL13_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2442
ber01-VHDL13_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2445
ber01-VHDL13_DWEH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2439
ber01-VHDL13_DWHG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2754
ber01-VHDL13_DWHG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2679
ber01-VHDL13_DWHG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2727
ber01-VHDL13_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2424
ber01-VHDL13_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2735
ber01-VHDL13_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2897
ber01-VHDL13_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2897
ber01-VHDL13_DWHG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2415
ber01-VHDL13_DWHH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2368
ber01-VHDL13_DWHH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2368
ber01-VHDL13_DWHH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2536
ber01-VHDL13_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2305
ber01-VHDL13_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 2474
ber01-VHDL13_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2476
ber01-VHDL13_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2520
ber01-VHDL13_DWHH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2140
ber01-VHDL13_DWLG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1686
ber01-VHDL13_DWLG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1555
ber01-VHDL13_DWLG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1616
ber01-VHDL13_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1541
ber01-VHDL13_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1718
ber01-VHDL13_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1927
ber01-VHDL13_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:07 2088
ber01-VHDL13_DWLG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1983
ber01-VHDL13_DWLH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1669
ber01-VHDL13_DWLH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1598
ber01-VHDL13_DWLH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1747
ber01-VHDL13_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2015
ber01-VHDL13_DWLH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1937
ber01-VHDL13_DWLH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2129
ber01-VHDL13_DWLH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2155
ber01-VHDL13_DWLH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1874
ber01-VHDL13_DWLI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1760
ber01-VHDL13_DWLI_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1458
ber01-VHDL13_DWLI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1518
ber01-VHDL13_DWLI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1512
ber01-VHDL13_DWLI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1711
ber01-VHDL13_DWLI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 1801
ber01-VHDL13_DWLI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 1944
ber01-VHDL13_DWLI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1905
ber01-VHDL13_DWMG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2136
ber01-VHDL13_DWMG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2147
ber01-VHDL13_DWMG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 1928
ber01-VHDL13_DWMG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2370
ber01-VHDL13_DWMG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2370
ber01-VHDL13_DWMG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2320
ber01-VHDL13_DWMG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2202
ber01-VHDL13_DWMG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2330
ber01-VHDL13_DWMO_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2308
ber01-VHDL13_DWMO_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2308
ber01-VHDL13_DWMO_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2177
ber01-VHDL13_DWMO_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2302
ber01-VHDL13_DWMO_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2435
ber01-VHDL13_DWMO_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2435
ber01-VHDL13_DWMO_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2322
ber01-VHDL13_DWMO_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2296
ber01-VHDL13_DWMP_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2329
ber01-VHDL13_DWMP_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 2329
ber01-VHDL13_DWMP_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2183
ber01-VHDL13_DWMP_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2283
ber01-VHDL13_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2412
ber01-VHDL13_DWMP_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2412
ber01-VHDL13_DWMP_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2279
ber01-VHDL13_DWMP_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2144
ber01-VHDL13_DWOG_060300-2603060300-dsw--0-ia5 06-Mar-2026 04:00:01 3645
ber01-VHDL13_DWOG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 3261
ber01-VHDL13_DWOG_061700-2603061700-dsw--0-ia5 06-Mar-2026 19:00:06 3023
ber01-VHDL13_DWOG_070300-2603070300-dsw--0-ia5 07-Mar-2026 04:00:01 3613
ber01-VHDL13_DWOG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 3484
ber01-VHDL13_DWOG_071700-2603071700-dsw--0-ia5 07-Mar-2026 19:00:05 2785
ber01-VHDL13_DWOH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:11 2496
ber01-VHDL13_DWOH_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:11 2498
ber01-VHDL13_DWOH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:16 2478
ber01-VHDL13_DWOH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2410
ber01-VHDL13_DWOH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:11 2650
ber01-VHDL13_DWOH_070400-2603070400-dsw--0-ia5 07-Mar-2026 05:58:17 2599
ber01-VHDL13_DWOH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2521
ber01-VHDL13_DWOH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2497
ber01-VHDL13_DWOI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:28:18 2352
ber01-VHDL13_DWOI_060400-2603060400-dsw--0-ia5 06-Mar-2026 05:58:17 2270
ber01-VHDL13_DWOI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:28:12 2276
ber01-VHDL13_DWOI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:28:17 2167
ber01-VHDL13_DWOI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:28:17 2367
ber01-VHDL13_DWOI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:08:07 2274
ber01-VHDL13_DWOI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:28:16 2280
ber01-VHDL13_DWOI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:28:17 2350
ber01-VHDL13_DWON_060228-2603060228-dsw--0-ia5 06-Mar-2026 02:28:41 3293
ber01-VHDL13_DWON_060314-2603060314-dsw--0-ia5 06-Mar-2026 03:14:06 3293
ber01-VHDL13_DWON_060624-2603060624-dsw--0-ia5 06-Mar-2026 06:24:37 3687
ber01-VHDL13_DWON_060629-2603060629-dsw--0-ia5 06-Mar-2026 06:29:21 3514
ber01-VHDL13_DWON_060714-2603060714-dsw--0-ia5 06-Mar-2026 07:14:31 3365
ber01-VHDL13_DWON_061157-2603061157-dsw--0-ia5 06-Mar-2026 11:57:38 3365
ber01-VHDL13_DWON_061537-2603061537-dsw--0-ia5 06-Mar-2026 15:37:43 2935
ber01-VHDL13_DWON_061712-2603061712-dsw--0-ia5 06-Mar-2026 17:12:58 2935
ber01-VHDL13_DWON_061726-2603061726-dsw--0-ia5 06-Mar-2026 17:26:17 3145
ber01-VHDL13_DWON_062246-2603062246-dsw--0-ia5 06-Mar-2026 22:46:25 3207
ber01-VHDL13_DWON_070131-2603070131-dsw--0-ia5 07-Mar-2026 01:31:30 3260
ber01-VHDL13_DWON_070426-2603070426-dsw--0-ia5 07-Mar-2026 04:26:47 3260
ber01-VHDL13_DWON_070545-2603070545-dsw--0-ia5 07-Mar-2026 05:45:12 3440
ber01-VHDL13_DWON_071002-2603071002-dsw--0-ia5 07-Mar-2026 10:02:17 3440
ber01-VHDL13_DWON_071401-2603071401-dsw--0-ia5 07-Mar-2026 14:01:21 3590
ber01-VHDL13_DWON_071522-2603071522-dsw--0-ia5 07-Mar-2026 15:22:48 3590
ber01-VHDL13_DWON_071833-2603071833-dsw--0-ia5 07-Mar-2026 18:33:44 3013
ber01-VHDL13_DWON_080119-2603080119-dsw--0-ia5 08-Mar-2026 01:19:52 3342
ber01-VHDL13_DWPG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 1738
ber01-VHDL13_DWPG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1685
ber01-VHDL13_DWPG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 1831
ber01-VHDL13_DWPG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 1848
ber01-VHDL13_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1829
ber01-VHDL13_DWPG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2243
ber01-VHDL13_DWPG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2115
ber01-VHDL13_DWPG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 1901
ber01-VHDL13_DWPH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2085
ber01-VHDL13_DWPH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:01 1982
ber01-VHDL13_DWPH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:06 2143
ber01-VHDL13_DWPH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2034
ber01-VHDL13_DWPH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:08 1780
ber01-VHDL13_DWPH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:01 2278
ber01-VHDL13_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2191
ber01-VHDL13_DWPH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:02 2001
ber01-VHDL13_DWSG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:30:06 2449
ber01-VHDL13_DWSG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:06 2494
ber01-VHDL13_DWSG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:30:02 2389
ber01-VHDL13_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:30:05 2101
ber01-VHDL13_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:30:01 2400
ber01-VHDL13_DWSG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2484
ber01-VHDL13_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:30:06 2393
ber01-VHDL13_DWSG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:30:06 2321
ber01-VHDL17_DWOG_061200-2603061200-dsw--0-ia5 06-Mar-2026 12:02:46 1871
ber01-VHDL17_DWOG_071200-2603071200-dsw--0-ia5 07-Mar-2026 10:53:51 3549
swis2-VHDL20_DWEG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2772
swis2-VHDL20_DWEG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2818
swis2-VHDL20_DWEG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2953
swis2-VHDL20_DWEG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2736
swis2-VHDL20_DWEG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2926
swis2-VHDL20_DWEG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2919
swis2-VHDL20_DWEG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2995
swis2-VHDL20_DWEG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2823
swis2-VHDL20_DWEH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2580
swis2-VHDL20_DWEH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2809
swis2-VHDL20_DWEH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2977
swis2-VHDL20_DWEH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2913
swis2-VHDL20_DWEH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2911
swis2-VHDL20_DWEH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2777
swis2-VHDL20_DWEH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2944
swis2-VHDL20_DWEH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2793
swis2-VHDL20_DWEI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:03 2644
swis2-VHDL20_DWEI_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2621
swis2-VHDL20_DWEI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 2798
swis2-VHDL20_DWEI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2518
swis2-VHDL20_DWEI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2659
swis2-VHDL20_DWEI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:06 2625
swis2-VHDL20_DWEI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2801
swis2-VHDL20_DWEI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2701
swis2-VHDL20_DWHG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2940
swis2-VHDL20_DWHG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2862
swis2-VHDL20_DWHG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 3263
swis2-VHDL20_DWHG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2607
swis2-VHDL20_DWHG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2921
swis2-VHDL20_DWHG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 3080
swis2-VHDL20_DWHG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3428
swis2-VHDL20_DWHG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:06 2598
swis2-VHDL20_DWHH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2554
swis2-VHDL20_DWHH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:08 2554
swis2-VHDL20_DWHH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:06 3083
swis2-VHDL20_DWHH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2491
swis2-VHDL20_DWHH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2660
swis2-VHDL20_DWHH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:07 2662
swis2-VHDL20_DWHH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 3063
swis2-VHDL20_DWHH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:06 2326
swis2-VHDL20_DWLG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2031
swis2-VHDL20_DWLG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 1897
swis2-VHDL20_DWLG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2104
swis2-VHDL20_DWLG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 1883
swis2-VHDL20_DWLG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2060
swis2-VHDL20_DWLG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2269
swis2-VHDL20_DWLG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2574
swis2-VHDL20_DWLG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2325
swis2-VHDL20_DWLH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2021
swis2-VHDL20_DWLH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 1946
swis2-VHDL20_DWLH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2245
swis2-VHDL20_DWLH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2363
swis2-VHDL20_DWLH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2285
swis2-VHDL20_DWLH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2478
swis2-VHDL20_DWLH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2652
swis2-VHDL20_DWLH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2223
swis2-VHDL20_DWLI_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2107
swis2-VHDL20_DWLI_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 1802
swis2-VHDL20_DWLI_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2007
swis2-VHDL20_DWLI_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 1856
swis2-VHDL20_DWLI_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2055
swis2-VHDL20_DWLI_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:15 2145
swis2-VHDL20_DWLI_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2431
swis2-VHDL20_DWLI_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2249
swis2-VHDL20_DWMG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2505
swis2-VHDL20_DWMG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2537
swis2-VHDL20_DWMG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2494
swis2-VHDL20_DWMG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:07 2653
swis2-VHDL20_DWMG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2759
swis2-VHDL20_DWMG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2710
swis2-VHDL20_DWMG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2767
swis2-VHDL20_DWMG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2720
swis2-VHDL20_DWMO_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2682
swis2-VHDL20_DWMO_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2702
swis2-VHDL20_DWMO_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2691
swis2-VHDL20_DWMO_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:07 2696
swis2-VHDL20_DWMO_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2829
swis2-VHDL20_DWMO_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2829
swis2-VHDL20_DWMO_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2895
swis2-VHDL20_DWMO_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2690
swis2-VHDL20_DWMP_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2702
swis2-VHDL20_DWMP_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2719
swis2-VHDL20_DWMP_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2737
swis2-VHDL20_DWMP_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:07 2653
swis2-VHDL20_DWMP_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2805
swis2-VHDL20_DWMP_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2802
swis2-VHDL20_DWMP_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2850
swis2-VHDL20_DWMP_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2526
swis2-VHDL20_DWPG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2066
swis2-VHDL20_DWPG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 2011
swis2-VHDL20_DWPG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2290
swis2-VHDL20_DWPG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2307
swis2-VHDL20_DWPG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2158
swis2-VHDL20_DWPG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2569
swis2-VHDL20_DWPG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2573
swis2-VHDL20_DWPG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2359
swis2-VHDL20_DWPH_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:01 2412
swis2-VHDL20_DWPH_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:00:12 2310
swis2-VHDL20_DWPH_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2602
swis2-VHDL20_DWPH_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:05 2493
swis2-VHDL20_DWPH_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:06 2108
swis2-VHDL20_DWPH_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:00:17 2606
swis2-VHDL20_DWPH_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:07 2649
swis2-VHDL20_DWPH_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2459
swis2-VHDL20_DWSG_060200-2603060200-dsw--0-ia5 06-Mar-2026 03:45:07 2796
swis2-VHDL20_DWSG_060400-2603060400-dsw--0-ia5 06-Mar-2026 06:15:01 2847
swis2-VHDL20_DWSG_060800-2603060800-dsw--0-ia5 06-Mar-2026 09:45:01 2906
swis2-VHDL20_DWSG_061300-2603061300-dsw--0-ia5 06-Mar-2026 14:45:06 2570
swis2-VHDL20_DWSG_061800-2603061800-dsw--0-ia5 06-Mar-2026 19:45:02 2455
swis2-VHDL20_DWSG_070200-2603070200-dsw--0-ia5 07-Mar-2026 03:45:01 2745
swis2-VHDL20_DWSG_070400-2603070400-dsw--0-ia5 07-Mar-2026 06:15:02 2836
swis2-VHDL20_DWSG_070800-2603070800-dsw--0-ia5 07-Mar-2026 09:45:01 2888
swis2-VHDL20_DWSG_071300-2603071300-dsw--0-ia5 07-Mar-2026 14:45:15 2820
swis2-VHDL20_DWSG_071800-2603071800-dsw--0-ia5 07-Mar-2026 19:45:02 2695
wst04-VHDL20_DWEG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:22 249019
wst04-VHDL20_DWEG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:28 248599
wst04-VHDL20_DWEG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 246873
wst04-VHDL20_DWEG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:11 245922
wst04-VHDL20_DWEG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 247010
wst04-VHDL20_DWEG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 246038
wst04-VHDL20_DWEG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 247207
wst04-VHDL20_DWEG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:12 246239
wst04-VHDL20_DWEH_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:22 247223
wst04-VHDL20_DWEH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:22 247093
wst04-VHDL20_DWEH_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 244992
wst04-VHDL20_DWEH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:11 244584
wst04-VHDL20_DWEH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 246239
wst04-VHDL20_DWEH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:17 244582
wst04-VHDL20_DWEH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 245375
wst04-VHDL20_DWEH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:12 244515
wst04-VHDL20_DWEI_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:22 361660
wst04-VHDL20_DWEI_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:28 361605
wst04-VHDL20_DWEI_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:22 355199
wst04-VHDL20_DWEI_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 354616
wst04-VHDL20_DWEI_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 355254
wst04-VHDL20_DWEI_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:21 354741
wst04-VHDL20_DWEI_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:11 356387
wst04-VHDL20_DWEI_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:16 355816
wst04-VHDL20_DWHG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:18 362957
wst04-VHDL20_DWHG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:12 362906
wst04-VHDL20_DWHG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:26 355603
wst04-VHDL20_DWHG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 354181
wst04-VHDL20_DWHG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 354516
wst04-VHDL20_DWHG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:13 354659
wst04-VHDL20_DWHG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:17 356997
wst04-VHDL20_DWHG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 354547
wst04-VHDL20_DWHH_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:18 332908
wst04-VHDL20_DWHH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:12 332978
wst04-VHDL20_DWHH_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:26 337045
wst04-VHDL20_DWHH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 335844
wst04-VHDL20_DWHH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 336304
wst04-VHDL20_DWHH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:13 336323
wst04-VHDL20_DWHH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 336047
wst04-VHDL20_DWHH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 333802
wst04-VHDL20_DWLG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 349858
wst04-VHDL20_DWLG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:42 349638
wst04-VHDL20_DWLG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 345575
wst04-VHDL20_DWLG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 345004
wst04-VHDL20_DWLG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 345514
wst04-VHDL20_DWLG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 345321
wst04-VHDL20_DWLG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 353524
wst04-VHDL20_DWLG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 353732
wst04-VHDL20_DWLH_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 353863
wst04-VHDL20_DWLH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:42 353765
wst04-VHDL20_DWLH_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 354553
wst04-VHDL20_DWLH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 354103
wst04-VHDL20_DWLH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 354351
wst04-VHDL20_DWLH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 354460
wst04-VHDL20_DWLH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 347549
wst04-VHDL20_DWLH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 347424
wst04-VHDL20_DWLI_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 354824
wst04-VHDL20_DWLI_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:42 354630
wst04-VHDL20_DWLI_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 346059
wst04-VHDL20_DWLI_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 345613
wst04-VHDL20_DWLI_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 345315
wst04-VHDL20_DWLI_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:41 345308
wst04-VHDL20_DWLI_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 343395
wst04-VHDL20_DWLI_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 342983
wst04-VHDL20_DWMG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:16 584735
wst04-VHDL20_DWMG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:22 584986
wst04-VHDL20_DWMG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 581717
wst04-VHDL20_DWMG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 581388
wst04-VHDL20_DWMG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 581559
wst04-VHDL20_DWMG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 581767
wst04-VHDL20_DWMG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 588174
wst04-VHDL20_DWMG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 587223
wst04-VHDL20_DWMO_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:11 484158
wst04-VHDL20_DWMO_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:16 485329
wst04-VHDL20_DWMO_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:12 482693
wst04-VHDL20_DWMO_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 481633
wst04-VHDL20_DWMO_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 482319
wst04-VHDL20_DWMO_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:21 482745
wst04-VHDL20_DWMO_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 476714
wst04-VHDL20_DWMO_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 475174
wst04-VHDL20_DWMP_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:11 577812
wst04-VHDL20_DWMP_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:22 578699
wst04-VHDL20_DWMP_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:16 569755
wst04-VHDL20_DWMP_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:17 569532
wst04-VHDL20_DWMP_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:16 568482
wst04-VHDL20_DWMP_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:27 569323
wst04-VHDL20_DWMP_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:27 573450
wst04-VHDL20_DWMP_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:18 572358
wst04-VHDL20_DWPG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:26 354517
wst04-VHDL20_DWPG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:30 354431
wst04-VHDL20_DWPG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:36 400648
wst04-VHDL20_DWPG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:26 355913
wst04-VHDL20_DWPG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:26 356233
wst04-VHDL20_DWPG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:31 356676
wst04-VHDL20_DWPG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:37 403974
wst04-VHDL20_DWPG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:26 359188
wst04-VHDL20_DWPH_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:22 250515
wst04-VHDL20_DWPH_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:00:30 250436
wst04-VHDL20_DWPH_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:30 296519
wst04-VHDL20_DWPH_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:22 296230
wst04-VHDL20_DWPH_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:22 251473
wst04-VHDL20_DWPH_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:00:31 252332
wst04-VHDL20_DWPH_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:31 295720
wst04-VHDL20_DWPH_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:22 295732
wst04-VHDL20_DWSG_060200-2603060200-omedes--0.pdf 06-Mar-2026 03:45:16 364422
wst04-VHDL20_DWSG_060400-2603060400-omedes--0.pdf 06-Mar-2026 06:15:12 364782
wst04-VHDL20_DWSG_060800-2603060800-omedes--0.pdf 06-Mar-2026 09:45:12 367425
wst04-VHDL20_DWSG_061300-2603061300-omedes--0.pdf 06-Mar-2026 14:45:12 367113
wst04-VHDL20_DWSG_061800-2603061800-omedes--0.pdf 06-Mar-2026 19:45:11 366955
wst04-VHDL20_DWSG_070200-2603070200-omedes--0.pdf 07-Mar-2026 03:45:12 367140
wst04-VHDL20_DWSG_070400-2603070400-omedes--0.pdf 07-Mar-2026 06:15:17 367503
wst04-VHDL20_DWSG_070800-2603070800-omedes--0.pdf 07-Mar-2026 09:45:11 360470
wst04-VHDL20_DWSG_071300-2603071300-omedes--0.pdf 07-Mar-2026 14:45:15 360437
wst04-VHDL20_DWSG_071800-2603071800-omedes--0.pdf 07-Mar-2026 19:45:12 360452