Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_050600 05-Sep-2026 12:11:49 4033
FPDL13_DWMZ_060600 06-Sep-2026 11:05:41 7211
SXDL31_DWAV_050800 05-Sep-2026 07:20:44 7213
SXDL31_DWAV_051800 05-Sep-2026 16:24:53 7403
SXDL31_DWAV_060800 06-Sep-2026 07:11:09 8041
SXDL31_DWAV_061800 06-Sep-2026 16:39:48 7202
SXDL31_DWAV_LATEST 06-Sep-2026 16:39:48 7202
SXDL33_DWAV_050000 05-Sep-2026 09:27:23 8257
SXDL33_DWAV_060000 06-Sep-2026 09:54:10 7475
SXDL33_DWAV_LATEST 06-Sep-2026 09:54:10 7475
ber01-FWDL39_DWMS_051200-2609051200-dsw--0-ia5 05-Sep-2026 12:02:04 1317
ber01-FWDL39_DWMS_061200-2609061200-dsw--0-ia5 06-Sep-2026 11:04:14 1186
ber01-VHDL13_DWEG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3202
ber01-VHDL13_DWEG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:28:26 2748
ber01-VHDL13_DWEH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3141
ber01-VHDL13_DWEH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:28:26 2460
ber01-VHDL13_DWEI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:28:19 3008
ber01-VHDL13_DWEI_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:28:26 2735
ber01-VHDL13_DWHG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 3532
ber01-VHDL13_DWHG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2940
ber01-VHDL13_DWHH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 3607
ber01-VHDL13_DWHH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2883
ber01-VHDL13_DWLG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2777
ber01-VHDL13_DWLG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2163
ber01-VHDL13_DWLH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3258
ber01-VHDL13_DWLH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2245
ber01-VHDL13_DWLI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2539
ber01-VHDL13_DWLI_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2112
ber01-VHDL13_DWMO_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2765
ber01-VHDL13_DWMO_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2826
ber01-VHDL13_DWMP_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2969
ber01-VHDL13_DWMP_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2949
ber01-VHDL13_DWOG_050300-2609050300-dsw--0-ia5 05-Sep-2026 03:01:13 4591
ber01-VHDL13_DWOG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:12 4230
ber01-VHDL13_DWOG_051700-2609051700-dsw--0-ia5 05-Sep-2026 18:00:04 2987
ber01-VHDL13_DWOG_060300-2609060300-dsw--0-ia5 06-Sep-2026 03:00:44 3418
ber01-VHDL13_DWOG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2975
ber01-VHDL13_DWOG_061700-2609061700-dsw--0-ia5 06-Sep-2026 18:34:56 3847
ber01-VHDL13_DWOG_061700_COR-2609061700-dsw--0-ia5 06-Sep-2026 17:11:58 3851
ber01-VHDL13_DWON_050116-2609050116-dsw--0-ia5 05-Sep-2026 01:16:37 4023
ber01-VHDL13_DWON_050244-2609050244-dsw--0-ia5 05-Sep-2026 02:46:58 4023
ber01-VHDL13_DWON_050529-2609050529-dsw--0-ia5 05-Sep-2026 05:29:23 4295
ber01-VHDL13_DWON_050552-2609050552-dsw--0-ia5 05-Sep-2026 05:52:33 4038
ber01-VHDL13_DWON_050807-2609050807-dsw--0-ia5 05-Sep-2026 08:07:33 4024
ber01-VHDL13_DWON_051455-2609051455-dsw--0-ia5 05-Sep-2026 14:57:29 3869
ber01-VHDL13_DWON_051741-2609051741-dsw--0-ia5 05-Sep-2026 17:41:33 3011
ber01-VHDL13_DWON_060106-2609060106-dsw--0-ia5 06-Sep-2026 01:06:57 3454
ber01-VHDL13_DWON_060243-2609060243-dsw--0-ia5 06-Sep-2026 02:43:18 3526
ber01-VHDL13_DWON_060244-2609060244-dsw--0-ia5 06-Sep-2026 02:44:09 3526
ber01-VHDL13_DWON_060516-2609060516-dsw--0-ia5 06-Sep-2026 05:16:13 3117
ber01-VHDL13_DWON_060933-2609060933-dsw--0-ia5 06-Sep-2026 09:33:52 3117
ber01-VHDL13_DWON_061248-2609061248-dsw--0-ia5 06-Sep-2026 12:48:48 3596
ber01-VHDL13_DWON_061249-2609061249-dsw--0-ia5 06-Sep-2026 12:50:11 3596
ber01-VHDL13_DWON_061711-2609061711-dsw--0-ia5 06-Sep-2026 17:11:24 4002
ber01-VHDL13_DWON_061834-2609061834-dsw--0-ia5 06-Sep-2026 18:34:48 4002
ber01-VHDL13_DWPG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 2971
ber01-VHDL13_DWPG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2160
ber01-VHDL13_DWPH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3475
ber01-VHDL13_DWPH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 2357
ber01-VHDL13_DWSG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 3147
ber01-VHDL13_DWSG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 3168
ber01-VHDL17_DWOG_051200-2609051200-dsw--0-ia5 05-Sep-2026 10:48:08 3038
ber01-VHDL17_DWOG_061200-2609061200-dsw--0-ia5 06-Sep-2026 11:47:58 2762
swis2-VHDL20_DWEG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 951
swis2-VHDL20_DWEG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 957
swis2-VHDL20_DWEG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1240
swis2-VHDL20_DWEG_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1350
swis2-VHDL20_DWEG_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 1143
swis2-VHDL20_DWEG_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:01:24 1140
swis2-VHDL20_DWEG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1158
swis2-VHDL20_DWEG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:03 1546
swis2-VHDL20_DWEH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1019
swis2-VHDL20_DWEH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 1028
swis2-VHDL20_DWEH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1311
swis2-VHDL20_DWEH_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1363
swis2-VHDL20_DWEH_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 1143
swis2-VHDL20_DWEH_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:01:24 1140
swis2-VHDL20_DWEH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1016
swis2-VHDL20_DWEH_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:03 1309
swis2-VHDL20_DWEI_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 965
swis2-VHDL20_DWEI_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:01:17 971
swis2-VHDL20_DWEI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1257
swis2-VHDL20_DWEI_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1372
swis2-VHDL20_DWEI_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 1164
swis2-VHDL20_DWEI_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:01:24 1161
swis2-VHDL20_DWEI_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1179
swis2-VHDL20_DWEI_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:03 1620
swis2-VHDL20_DWHG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:46:58 1674
swis2-VHDL20_DWHG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1709
swis2-VHDL20_DWHG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:45:33 1846
swis2-VHDL20_DWHG_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:45:13 1564
swis2-VHDL20_DWHG_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:45:08 1209
swis2-VHDL20_DWHG_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 1258
swis2-VHDL20_DWHG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:45:16 1411
swis2-VHDL20_DWHG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:45:17 1385
swis2-VHDL20_DWHH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:46:58 1690
swis2-VHDL20_DWHH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1711
swis2-VHDL20_DWHH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:45:33 1984
swis2-VHDL20_DWHH_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:45:13 1664
swis2-VHDL20_DWHH_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:45:08 1533
swis2-VHDL20_DWHH_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 1446
swis2-VHDL20_DWHH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:45:16 1410
swis2-VHDL20_DWHH_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:45:17 1362
swis2-VHDL20_DWLG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 892
swis2-VHDL20_DWLG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1096
swis2-VHDL20_DWLG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1329
swis2-VHDL20_DWLG_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:31:08 840
swis2-VHDL20_DWLG_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:28 691
swis2-VHDL20_DWLG_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 777
swis2-VHDL20_DWLG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:40 905
swis2-VHDL20_DWLG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:31:04 992
swis2-VHDL20_DWLH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1124
swis2-VHDL20_DWLH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1319
swis2-VHDL20_DWLH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1660
swis2-VHDL20_DWLH_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:31:08 1074
swis2-VHDL20_DWLH_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:28 698
swis2-VHDL20_DWLH_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 784
swis2-VHDL20_DWLH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:40 1038
swis2-VHDL20_DWLH_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:31:04 1125
swis2-VHDL20_DWLI_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 911
swis2-VHDL20_DWLI_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 964
swis2-VHDL20_DWLI_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1204
swis2-VHDL20_DWLI_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:31:08 843
swis2-VHDL20_DWLI_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:28 693
swis2-VHDL20_DWLI_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 779
swis2-VHDL20_DWLI_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:40 925
swis2-VHDL20_DWLI_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:31:04 1015
swis2-VHDL20_DWMO_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1356
swis2-VHDL20_DWMO_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:03 1204
swis2-VHDL20_DWMO_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1379
swis2-VHDL20_DWMO_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1246
swis2-VHDL20_DWMO_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 909
swis2-VHDL20_DWMO_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:08 912
swis2-VHDL20_DWMO_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1180
swis2-VHDL20_DWMO_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:09 1654
swis2-VHDL20_DWMP_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1453
swis2-VHDL20_DWMP_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:03 1401
swis2-VHDL20_DWMP_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1274
swis2-VHDL20_DWMP_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1701
swis2-VHDL20_DWMP_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 1171
swis2-VHDL20_DWMP_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:08 1142
swis2-VHDL20_DWMP_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1510
swis2-VHDL20_DWMP_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:09 1865
swis2-VHDL20_DWPG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1180
swis2-VHDL20_DWPG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1294
swis2-VHDL20_DWPG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 1591
swis2-VHDL20_DWPG_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:31:08 858
swis2-VHDL20_DWPG_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:28 709
swis2-VHDL20_DWPG_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 795
swis2-VHDL20_DWPG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:40 940
swis2-VHDL20_DWPG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:31:04 1027
swis2-VHDL20_DWPH_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:23 1531
swis2-VHDL20_DWPH_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:13 1681
swis2-VHDL20_DWPH_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:32 2001
swis2-VHDL20_DWPH_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:31:08 978
swis2-VHDL20_DWPH_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:28 827
swis2-VHDL20_DWPH_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 913
swis2-VHDL20_DWPH_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:40 1075
swis2-VHDL20_DWPH_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:31:04 944
swis2-VHDL20_DWSG_050200-2609050200-dsw--0-ia5 05-Sep-2026 02:30:04 1156
swis2-VHDL20_DWSG_050400-2609050400-dsw--0-ia5 05-Sep-2026 05:00:19 1129
swis2-VHDL20_DWSG_050800-2609050800-dsw--0-ia5 05-Sep-2026 08:30:03 1376
swis2-VHDL20_DWSG_051800-2609051800-dsw--0-ia5 05-Sep-2026 18:30:11 1342
swis2-VHDL20_DWSG_060200-2609060200-dsw--0-ia5 06-Sep-2026 02:30:04 1110
swis2-VHDL20_DWSG_060400-2609060400-dsw--0-ia5 06-Sep-2026 05:00:17 1241
swis2-VHDL20_DWSG_060800-2609060800-dsw--0-ia5 06-Sep-2026 08:30:23 1366
swis2-VHDL20_DWSG_061800-2609061800-dsw--0-ia5 06-Sep-2026 18:30:03 1395
wst04-VHDL20_DWEG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 241043
wst04-VHDL20_DWEG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 240599
wst04-VHDL20_DWEG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:14 241896
wst04-VHDL20_DWEG_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:11 239760
wst04-VHDL20_DWEG_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:14 239087
wst04-VHDL20_DWEG_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 237956
wst04-VHDL20_DWEG_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 238689
wst04-VHDL20_DWEG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:13 244323
wst04-VHDL20_DWEH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 243178
wst04-VHDL20_DWEH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 242961
wst04-VHDL20_DWEH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:14 244295
wst04-VHDL20_DWEH_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:11 241457
wst04-VHDL20_DWEH_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:14 241059
wst04-VHDL20_DWEH_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 240219
wst04-VHDL20_DWEH_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 239761
wst04-VHDL20_DWEH_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:13 243029
wst04-VHDL20_DWEI_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 346146
wst04-VHDL20_DWEI_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 345627
wst04-VHDL20_DWEI_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 346412
wst04-VHDL20_DWEI_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:30 339964
wst04-VHDL20_DWEI_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:14 339159
wst04-VHDL20_DWEI_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 337946
wst04-VHDL20_DWEI_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 338102
wst04-VHDL20_DWEI_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:19 352921
wst04-VHDL20_DWHG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:46:58 345471
wst04-VHDL20_DWHG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 345263
wst04-VHDL20_DWHG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:45:33 346306
wst04-VHDL20_DWHG_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:45:16 339725
wst04-VHDL20_DWHG_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:45:14 337792
wst04-VHDL20_DWHG_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 337589
wst04-VHDL20_DWHG_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:45:22 339522
wst04-VHDL20_DWHG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:45:25 341204
wst04-VHDL20_DWHH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:46:58 339358
wst04-VHDL20_DWHH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 232468
wst04-VHDL20_DWHH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:45:33 339565
wst04-VHDL20_DWHH_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:45:16 338073
wst04-VHDL20_DWHH_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:45:14 336800
wst04-VHDL20_DWHH_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 234453
wst04-VHDL20_DWHH_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:45:22 336387
wst04-VHDL20_DWHH_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:45:25 334003
wst04-VHDL20_DWLG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 338812
wst04-VHDL20_DWLG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 338815
wst04-VHDL20_DWLG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 339600
wst04-VHDL20_DWLG_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:31:37 333027
wst04-VHDL20_DWLG_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:24 332244
wst04-VHDL20_DWLG_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:01:24 332408
wst04-VHDL20_DWLG_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:42 333134
wst04-VHDL20_DWLG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:31:23 332774
wst04-VHDL20_DWLH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:40 346929
wst04-VHDL20_DWLH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 346889
wst04-VHDL20_DWLH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 348026
wst04-VHDL20_DWLH_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:31:37 332180
wst04-VHDL20_DWLH_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:24 331055
wst04-VHDL20_DWLH_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:01:24 331233
wst04-VHDL20_DWLH_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:42 332176
wst04-VHDL20_DWLH_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:31:23 336489
wst04-VHDL20_DWLI_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 343224
wst04-VHDL20_DWLI_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:43 343062
wst04-VHDL20_DWLI_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 388489
wst04-VHDL20_DWLI_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:31:49 333391
wst04-VHDL20_DWLI_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:28 332611
wst04-VHDL20_DWLI_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:01:24 332751
wst04-VHDL20_DWLI_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:57 378076
wst04-VHDL20_DWLI_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:31:23 333081
wst04-VHDL20_DWMO_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 460477
wst04-VHDL20_DWMO_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 459772
wst04-VHDL20_DWMO_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 459316
wst04-VHDL20_DWMO_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:30 350629
wst04-VHDL20_DWMO_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:18 454224
wst04-VHDL20_DWMO_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 453182
wst04-VHDL20_DWMO_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 452781
wst04-VHDL20_DWMO_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:19 346144
wst04-VHDL20_DWMP_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:18 564528
wst04-VHDL20_DWMP_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:19 564927
wst04-VHDL20_DWMP_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 460275
wst04-VHDL20_DWMP_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:30 452825
wst04-VHDL20_DWMP_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:18 553408
wst04-VHDL20_DWMP_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 552522
wst04-VHDL20_DWMP_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 452044
wst04-VHDL20_DWMP_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:19 456324
wst04-VHDL20_DWPG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 247443
wst04-VHDL20_DWPG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:33 349466
wst04-VHDL20_DWPG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:58 395118
wst04-VHDL20_DWPG_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:31:37 341204
wst04-VHDL20_DWPG_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:24 239654
wst04-VHDL20_DWPG_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:01:18 340648
wst04-VHDL20_DWPG_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:42 385913
wst04-VHDL20_DWPG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:31:23 336559
wst04-VHDL20_DWPH_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:23 249024
wst04-VHDL20_DWPH_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:33 248991
wst04-VHDL20_DWPH_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:44 249316
wst04-VHDL20_DWPH_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:31:37 241028
wst04-VHDL20_DWPH_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:24 240121
wst04-VHDL20_DWPH_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:01:18 240316
wst04-VHDL20_DWPH_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:42 241137
wst04-VHDL20_DWPH_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:31:23 240498
wst04-VHDL20_DWSG_050200-2609050200-omedes--0.pdf 05-Sep-2026 02:30:16 349091
wst04-VHDL20_DWSG_050400-2609050400-omedes--0.pdf 05-Sep-2026 05:00:13 349446
wst04-VHDL20_DWSG_050800-2609050800-omedes--0.pdf 05-Sep-2026 08:30:32 349617
wst04-VHDL20_DWSG_051800-2609051800-omedes--0.pdf 05-Sep-2026 18:30:30 344140
wst04-VHDL20_DWSG_060200-2609060200-omedes--0.pdf 06-Sep-2026 02:30:14 344474
wst04-VHDL20_DWSG_060400-2609060400-omedes--0.pdf 06-Sep-2026 05:00:17 343416
wst04-VHDL20_DWSG_060800-2609060800-omedes--0.pdf 06-Sep-2026 08:30:23 343864
wst04-VHDL20_DWSG_061800-2609061800-omedes--0.pdf 06-Sep-2026 18:30:19 349214