Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_160600 16-Mar-2026 13:54:05 4822
FPDL13_DWMZ_170600 17-Mar-2026 14:19:35 4832
SXDL31_DWAV_160800 16-Mar-2026 07:53:10 12828
SXDL31_DWAV_161800 16-Mar-2026 18:09:13 4144
SXDL31_DWAV_170800 17-Mar-2026 07:56:09 9565
SXDL31_DWAV_171800 17-Mar-2026 16:30:15 5596
SXDL31_DWAV_LATEST 17-Mar-2026 16:30:15 5596
SXDL33_DWAV_160000 16-Mar-2026 11:18:13 7347
SXDL33_DWAV_170000 17-Mar-2026 11:23:49 9509
SXDL33_DWAV_LATEST 17-Mar-2026 11:23:49 9509
ber01-FWDL39_DWMS_161230-2603161230-dsw--0-ia5 16-Mar-2026 12:06:31 2031
ber01-FWDL39_DWMS_171230-2603171230-dsw--0-ia5 17-Mar-2026 12:36:53 1038
ber01-VHDL13_DWEH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2623
ber01-VHDL13_DWEH_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:11 2734
ber01-VHDL13_DWEH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:17 2744
ber01-VHDL13_DWEH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:16 2296
ber01-VHDL13_DWEH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:11 2617
ber01-VHDL13_DWEH_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2642
ber01-VHDL13_DWEH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:28:17 2712
ber01-VHDL13_DWEH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:28:17 2431
ber01-VHDL13_DWHG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3706
ber01-VHDL13_DWHG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3767
ber01-VHDL13_DWHG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 4022
ber01-VHDL13_DWHG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3334
ber01-VHDL13_DWHG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:09 3376
ber01-VHDL13_DWHG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3408
ber01-VHDL13_DWHG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2962
ber01-VHDL13_DWHG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:08 2840
ber01-VHDL13_DWHH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 2965
ber01-VHDL13_DWHH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 2976
ber01-VHDL13_DWHH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 3312
ber01-VHDL13_DWHH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3087
ber01-VHDL13_DWHH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:09 3069
ber01-VHDL13_DWHH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3062
ber01-VHDL13_DWHH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2637
ber01-VHDL13_DWHH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:08 2699
ber01-VHDL13_DWLG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2975
ber01-VHDL13_DWLG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3002
ber01-VHDL13_DWLG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3127
ber01-VHDL13_DWLG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2067
ber01-VHDL13_DWLG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2153
ber01-VHDL13_DWLG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2252
ber01-VHDL13_DWLG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2066
ber01-VHDL13_DWLG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2028
ber01-VHDL13_DWLH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 3190
ber01-VHDL13_DWLH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3315
ber01-VHDL13_DWLH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3495
ber01-VHDL13_DWLH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2183
ber01-VHDL13_DWLH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2303
ber01-VHDL13_DWLH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2458
ber01-VHDL13_DWLH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2398
ber01-VHDL13_DWLH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2097
ber01-VHDL13_DWLI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2792
ber01-VHDL13_DWLI_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3125
ber01-VHDL13_DWLI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3381
ber01-VHDL13_DWLI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2261
ber01-VHDL13_DWLI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2425
ber01-VHDL13_DWLI_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2453
ber01-VHDL13_DWLI_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2331
ber01-VHDL13_DWLI_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2149
ber01-VHDL13_DWMG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3072
ber01-VHDL13_DWMG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 3086
ber01-VHDL13_DWMG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3696
ber01-VHDL13_DWMG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2477
ber01-VHDL13_DWMG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2854
ber01-VHDL13_DWMG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2862
ber01-VHDL13_DWMG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:01 2623
ber01-VHDL13_DWMG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2098
ber01-VHDL13_DWMO_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 2924
ber01-VHDL13_DWMO_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 2944
ber01-VHDL13_DWMO_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3195
ber01-VHDL13_DWMO_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2197
ber01-VHDL13_DWMO_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2491
ber01-VHDL13_DWMO_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2530
ber01-VHDL13_DWMO_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:01 2198
ber01-VHDL13_DWMO_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 1730
ber01-VHDL13_DWMP_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3027
ber01-VHDL13_DWMP_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 2938
ber01-VHDL13_DWMP_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3520
ber01-VHDL13_DWMP_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2357
ber01-VHDL13_DWMP_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2981
ber01-VHDL13_DWMP_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2977
ber01-VHDL13_DWMP_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:01 2781
ber01-VHDL13_DWMP_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2308
ber01-VHDL13_DWOG_160300-2603160300-dsw--0-ia5 16-Mar-2026 04:00:02 4723
ber01-VHDL13_DWOG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 4063
ber01-VHDL13_DWOG_161700-2603161700-dsw--0-ia5 16-Mar-2026 19:00:01 3700
ber01-VHDL13_DWOG_161700_COR-2603161700-dsw--0-ia5 16-Mar-2026 19:59:51 4688
ber01-VHDL13_DWOG_170300-2603170300-dsw--0-ia5 17-Mar-2026 04:00:01 5214
ber01-VHDL13_DWOG_170300_COR-2603170300-dsw--0-ia5 17-Mar-2026 04:53:21 4743
ber01-VHDL13_DWOG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:01 4802
ber01-VHDL13_DWOG_171700-2603171700-dsw--0-ia5 17-Mar-2026 19:00:01 4309
ber01-VHDL13_DWOH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2713
ber01-VHDL13_DWOH_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:17 2668
ber01-VHDL13_DWOH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:17 2709
ber01-VHDL13_DWOH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:16 2426
ber01-VHDL13_DWOH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:11 2552
ber01-VHDL13_DWOH_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2593
ber01-VHDL13_DWOH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:28:17 2569
ber01-VHDL13_DWOH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:28:17 2233
ber01-VHDL13_DWOI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2693
ber01-VHDL13_DWOI_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:17 2644
ber01-VHDL13_DWOI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:11 2546
ber01-VHDL13_DWOI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:10 2186
ber01-VHDL13_DWOI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:17 2509
ber01-VHDL13_DWOI_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2599
ber01-VHDL13_DWOI_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:28:11 3059
ber01-VHDL13_DWOI_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:28:11 2789
ber01-VHDL13_DWON_160303-2603160303-dsw--0-ia5 16-Mar-2026 03:03:16 4465
ber01-VHDL13_DWON_160627-2603160627-dsw--0-ia5 16-Mar-2026 06:27:37 3623
ber01-VHDL13_DWON_160730-2603160730-dsw--0-ia5 16-Mar-2026 07:30:11 4008
ber01-VHDL13_DWON_161526-2603161526-dsw--0-ia5 16-Mar-2026 15:26:21 3390
ber01-VHDL13_DWON_161806-2603161806-dsw--0-ia5 16-Mar-2026 18:06:17 3414
ber01-VHDL13_DWON_161959-2603161959-dsw--0-ia5 16-Mar-2026 19:59:21 3743
ber01-VHDL13_DWON_170453-2603170453-dsw--0-ia5 17-Mar-2026 04:53:11 4136
ber01-VHDL13_DWON_170623-2603170623-dsw--0-ia5 17-Mar-2026 06:23:17 4332
ber01-VHDL13_DWON_170708-2603170708-dsw--0-ia5 17-Mar-2026 07:08:37 4034
ber01-VHDL13_DWON_170927-2603170927-dsw--0-ia5 17-Mar-2026 09:27:41 4034
ber01-VHDL13_DWON_171539-2603171539-dsw--0-ia5 17-Mar-2026 15:39:41 3373
ber01-VHDL13_DWON_171737-2603171737-dsw--0-ia5 17-Mar-2026 17:37:47 3497
ber01-VHDL13_DWON_172258-2603172258-dsw--0-ia5 17-Mar-2026 22:59:01 3223
ber01-VHDL13_DWPG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2618
ber01-VHDL13_DWPG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 2646
ber01-VHDL13_DWPG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 2919
ber01-VHDL13_DWPG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2111
ber01-VHDL13_DWPG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2402
ber01-VHDL13_DWPG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2238
ber01-VHDL13_DWPG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2205
ber01-VHDL13_DWPG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2050
ber01-VHDL13_DWPH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2712
ber01-VHDL13_DWPH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 2674
ber01-VHDL13_DWPH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3082
ber01-VHDL13_DWPH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2100
ber01-VHDL13_DWPH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2249
ber01-VHDL13_DWPH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2388
ber01-VHDL13_DWPH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:06 2297
ber01-VHDL13_DWPH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 2149
ber01-VHDL13_DWSG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3502
ber01-VHDL13_DWSG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3530
ber01-VHDL13_DWSG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 3687
ber01-VHDL13_DWSG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3031
ber01-VHDL13_DWSG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 3105
ber01-VHDL13_DWSG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3025
ber01-VHDL13_DWSG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:30:01 3026
ber01-VHDL13_DWSG_170800_COR-2603170800-dsw--0-ia5 17-Mar-2026 10:30:12 3341
ber01-VHDL13_DWSG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:30:03 3050
ber01-VHDL17_DWOG_161200-2603161200-dsw--0-ia5 16-Mar-2026 12:59:11 2568
ber01-VHDL17_DWOG_171200-2603171200-dsw--0-ia5 17-Mar-2026 12:50:28 2796
swis2-VHDL20_DWEG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3103
swis2-VHDL20_DWEG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3044
swis2-VHDL20_DWEG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3365
swis2-VHDL20_DWEG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2976
swis2-VHDL20_DWEG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3026
swis2-VHDL20_DWEG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2937
swis2-VHDL20_DWEG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3074
swis2-VHDL20_DWEG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2583
swis2-VHDL20_DWEH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3066
swis2-VHDL20_DWEH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3071
swis2-VHDL20_DWEH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3326
swis2-VHDL20_DWEH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2826
swis2-VHDL20_DWEH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3056
swis2-VHDL20_DWEH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2981
swis2-VHDL20_DWEH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3222
swis2-VHDL20_DWEH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2790
swis2-VHDL20_DWEI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3090
swis2-VHDL20_DWEI_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 2996
swis2-VHDL20_DWEI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3073
swis2-VHDL20_DWEI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2538
swis2-VHDL20_DWEI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 2801
swis2-VHDL20_DWEI_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2954
swis2-VHDL20_DWEI_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3591
swis2-VHDL20_DWEI_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 3144
swis2-VHDL20_DWHG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3892
swis2-VHDL20_DWHG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3950
swis2-VHDL20_DWHG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 4827
swis2-VHDL20_DWHG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3517
swis2-VHDL20_DWHG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 3562
swis2-VHDL20_DWHG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 3591
swis2-VHDL20_DWHG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:06 3627
swis2-VHDL20_DWHG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 3023
swis2-VHDL20_DWHH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3151
swis2-VHDL20_DWHH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3162
swis2-VHDL20_DWHH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3855
swis2-VHDL20_DWHH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3272
swis2-VHDL20_DWHH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 3255
swis2-VHDL20_DWHH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 3248
swis2-VHDL20_DWHH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:06 3241
swis2-VHDL20_DWHH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2885
swis2-VHDL20_DWLG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 3360
swis2-VHDL20_DWLG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3520
swis2-VHDL20_DWLG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 3812
swis2-VHDL20_DWLG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2585
swis2-VHDL20_DWLG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2671
swis2-VHDL20_DWLG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 2595
swis2-VHDL20_DWLG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2558
swis2-VHDL20_DWLG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2371
swis2-VHDL20_DWLH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 3582
swis2-VHDL20_DWLH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3817
swis2-VHDL20_DWLH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 4168
swis2-VHDL20_DWLH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2596
swis2-VHDL20_DWLH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2716
swis2-VHDL20_DWLH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 2808
swis2-VHDL20_DWLH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2901
swis2-VHDL20_DWLH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2447
swis2-VHDL20_DWLI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 3182
swis2-VHDL20_DWLI_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3625
swis2-VHDL20_DWLI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 4047
swis2-VHDL20_DWLI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2672
swis2-VHDL20_DWLI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2836
swis2-VHDL20_DWLI_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 2798
swis2-VHDL20_DWLI_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2824
swis2-VHDL20_DWLI_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2494
swis2-VHDL20_DWMG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3506
swis2-VHDL20_DWMG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3615
swis2-VHDL20_DWMG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 4501
swis2-VHDL20_DWMG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3030
swis2-VHDL20_DWMG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3395
swis2-VHDL20_DWMG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 3295
swis2-VHDL20_DWMG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3271
swis2-VHDL20_DWMG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2558
swis2-VHDL20_DWMO_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3403
swis2-VHDL20_DWMO_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3429
swis2-VHDL20_DWMO_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 3845
swis2-VHDL20_DWMO_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2686
swis2-VHDL20_DWMO_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 2941
swis2-VHDL20_DWMO_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2906
swis2-VHDL20_DWMO_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2740
swis2-VHDL20_DWMO_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2168
swis2-VHDL20_DWMP_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3402
swis2-VHDL20_DWMP_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3457
swis2-VHDL20_DWMP_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 4321
swis2-VHDL20_DWMP_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2973
swis2-VHDL20_DWMP_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3508
swis2-VHDL20_DWMP_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 3403
swis2-VHDL20_DWMP_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3431
swis2-VHDL20_DWMP_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2743
swis2-VHDL20_DWPG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 2946
swis2-VHDL20_DWPG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3087
swis2-VHDL20_DWPG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 3511
swis2-VHDL20_DWPG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2703
swis2-VHDL20_DWPG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2787
swis2-VHDL20_DWPG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 2585
swis2-VHDL20_DWPG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2668
swis2-VHDL20_DWPG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2513
swis2-VHDL20_DWPH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 3039
swis2-VHDL20_DWPH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3117
swis2-VHDL20_DWPH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 3674
swis2-VHDL20_DWPH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2699
swis2-VHDL20_DWPH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2637
swis2-VHDL20_DWPH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 2737
swis2-VHDL20_DWPH_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 2760
swis2-VHDL20_DWPH_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 2612
swis2-VHDL20_DWSG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3887
swis2-VHDL20_DWSG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3923
swis2-VHDL20_DWSG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 4253
swis2-VHDL20_DWSG_161300-2603161300-dsw--0-ia5 16-Mar-2026 14:45:06 4208
swis2-VHDL20_DWSG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3563
swis2-VHDL20_DWSG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3453
swis2-VHDL20_DWSG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 3379
swis2-VHDL20_DWSG_170800-2603170800-dsw--0-ia5 17-Mar-2026 09:45:02 3549
swis2-VHDL20_DWSG_170800_COR-2603170800-dsw--0-ia5 17-Mar-2026 10:30:12 3870
swis2-VHDL20_DWSG_171300-2603171300-dsw--0-ia5 17-Mar-2026 14:45:02 3723
swis2-VHDL20_DWSG_171800-2603171800-dsw--0-ia5 17-Mar-2026 19:45:01 3405
wst04-VHDL20_DWEG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:17 246983
wst04-VHDL20_DWEG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:17 246432
wst04-VHDL20_DWEG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:16 244714
wst04-VHDL20_DWEG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:12 241975
wst04-VHDL20_DWEG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:21 243065
wst04-VHDL20_DWEG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:16 242327
wst04-VHDL20_DWEG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:13 242345
wst04-VHDL20_DWEG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:11 240370
wst04-VHDL20_DWEH_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:21 248241
wst04-VHDL20_DWEH_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:17 247673
wst04-VHDL20_DWEH_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:12 244732
wst04-VHDL20_DWEH_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:12 242432
wst04-VHDL20_DWEH_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:17 243859
wst04-VHDL20_DWEH_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:16 243372
wst04-VHDL20_DWEH_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:13 242404
wst04-VHDL20_DWEH_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:11 240787
wst04-VHDL20_DWEI_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:21 350817
wst04-VHDL20_DWEI_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:21 350725
wst04-VHDL20_DWEI_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:16 346358
wst04-VHDL20_DWEI_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:16 344720
wst04-VHDL20_DWEI_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:21 345369
wst04-VHDL20_DWEI_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:22 345552
wst04-VHDL20_DWEI_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:17 343550
wst04-VHDL20_DWEI_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:11 342002
wst04-VHDL20_DWHG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:17 355096
wst04-VHDL20_DWHG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:12 355222
wst04-VHDL20_DWHG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:26 361743
wst04-VHDL20_DWHG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:22 358986
wst04-VHDL20_DWHG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:17 358872
wst04-VHDL20_DWHG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:12 358273
wst04-VHDL20_DWHG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:27 354044
wst04-VHDL20_DWHG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:21 353737
wst04-VHDL20_DWHH_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:17 335833
wst04-VHDL20_DWHH_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:12 335950
wst04-VHDL20_DWHH_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:26 333331
wst04-VHDL20_DWHH_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:22 332086
wst04-VHDL20_DWHH_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:17 331768
wst04-VHDL20_DWHH_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:12 331741
wst04-VHDL20_DWHH_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:27 334427
wst04-VHDL20_DWHH_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:21 335108
wst04-VHDL20_DWLG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:27 338356
wst04-VHDL20_DWLG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:42 337097
wst04-VHDL20_DWLG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:32 334746
wst04-VHDL20_DWLG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:22 333044
wst04-VHDL20_DWLG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:27 333423
wst04-VHDL20_DWLG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:42 332695
wst04-VHDL20_DWLG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:25 336300
wst04-VHDL20_DWLG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:21 335604
wst04-VHDL20_DWLH_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:21 344025
wst04-VHDL20_DWLH_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:42 343473
wst04-VHDL20_DWLH_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:32 342775
wst04-VHDL20_DWLH_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:26 340436
wst04-VHDL20_DWLH_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:27 341396
wst04-VHDL20_DWLH_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:42 340571
wst04-VHDL20_DWLH_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:31 340194
wst04-VHDL20_DWLH_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:21 339221
wst04-VHDL20_DWLI_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:27 343208
wst04-VHDL20_DWLI_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:42 343426
wst04-VHDL20_DWLI_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:36 347414
wst04-VHDL20_DWLI_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:22 344955
wst04-VHDL20_DWLI_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:27 345656
wst04-VHDL20_DWLI_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:42 344712
wst04-VHDL20_DWLI_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:31 340563
wst04-VHDL20_DWLI_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:26 339942
wst04-VHDL20_DWMG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:11 557748
wst04-VHDL20_DWMG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:21 557454
wst04-VHDL20_DWMG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:26 564349
wst04-VHDL20_DWMG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:16 561191
wst04-VHDL20_DWMG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:17 561865
wst04-VHDL20_DWMG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:16 561661
wst04-VHDL20_DWMG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:23 539561
wst04-VHDL20_DWMG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:17 538480
wst04-VHDL20_DWMO_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:11 454689
wst04-VHDL20_DWMO_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:17 455303
wst04-VHDL20_DWMO_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:22 460113
wst04-VHDL20_DWMO_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:16 457147
wst04-VHDL20_DWMO_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:11 458080
wst04-VHDL20_DWMO_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:16 458520
wst04-VHDL20_DWMO_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:23 449601
wst04-VHDL20_DWMO_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:17 447512
wst04-VHDL20_DWMP_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:11 561617
wst04-VHDL20_DWMP_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:27 562514
wst04-VHDL20_DWMP_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:22 569309
wst04-VHDL20_DWMP_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:16 565585
wst04-VHDL20_DWMP_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:11 565686
wst04-VHDL20_DWMP_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:22 566736
wst04-VHDL20_DWMP_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:23 533742
wst04-VHDL20_DWMP_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:17 532835
wst04-VHDL20_DWPG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:27 356609
wst04-VHDL20_DWPG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:32 357108
wst04-VHDL20_DWPG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:32 395857
wst04-VHDL20_DWPG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:26 349855
wst04-VHDL20_DWPG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:27 349930
wst04-VHDL20_DWPG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:30 349045
wst04-VHDL20_DWPG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:31 398419
wst04-VHDL20_DWPG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:26 353326
wst04-VHDL20_DWPH_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:21 247553
wst04-VHDL20_DWPH_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:00:32 248007
wst04-VHDL20_DWPH_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:32 291977
wst04-VHDL20_DWPH_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:22 290238
wst04-VHDL20_DWPH_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:21 245201
wst04-VHDL20_DWPH_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:00:30 244590
wst04-VHDL20_DWPH_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:25 292848
wst04-VHDL20_DWPH_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:21 292660
wst04-VHDL20_DWSG_160200-2603160200-omedes--0.pdf 16-Mar-2026 03:45:17 352600
wst04-VHDL20_DWSG_160400-2603160400-omedes--0.pdf 16-Mar-2026 06:15:11 352047
wst04-VHDL20_DWSG_160800-2603160800-omedes--0.pdf 16-Mar-2026 09:45:12 353498
wst04-VHDL20_DWSG_161300-2603161300-omedes--0.pdf 16-Mar-2026 14:45:12 354042
wst04-VHDL20_DWSG_161800-2603161800-omedes--0.pdf 16-Mar-2026 19:45:12 353514
wst04-VHDL20_DWSG_170200-2603170200-omedes--0.pdf 17-Mar-2026 03:45:17 354664
wst04-VHDL20_DWSG_170400-2603170400-omedes--0.pdf 17-Mar-2026 06:15:12 355096
wst04-VHDL20_DWSG_170800-2603170800-omedes--0.pdf 17-Mar-2026 09:45:13 347530
wst04-VHDL20_DWSG_170800_COR-2603170800-omedes-..> 17-Mar-2026 10:30:23 347758
wst04-VHDL20_DWSG_171300-2603171300-omedes--0.pdf 17-Mar-2026 14:45:11 347278
wst04-VHDL20_DWSG_171800-2603171800-omedes--0.pdf 17-Mar-2026 19:45:11 347418