Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_110600 11-Sep-2026 12:58:09 5474
FPDL13_DWMZ_120600 12-Sep-2026 13:32:15 5159
SXDL31_DWAV_110800 11-Sep-2026 07:25:35 6841
SXDL31_DWAV_111800 11-Sep-2026 14:56:45 4829
SXDL31_DWAV_120800 12-Sep-2026 07:52:02 8217
SXDL31_DWAV_121800 12-Sep-2026 16:08:02 4579
SXDL31_DWAV_LATEST 12-Sep-2026 16:08:02 4579
SXDL33_DWAV_110000 11-Sep-2026 09:40:25 10359
SXDL33_DWAV_120000 12-Sep-2026 09:59:54 8485
SXDL33_DWAV_LATEST 12-Sep-2026 09:59:54 8485
ber01-FWDL39_DWMS_111200-2609111200-dsw--0-ia5 11-Sep-2026 10:14:18 2409
ber01-FWDL39_DWMS_121230-2609121230-dsw--0-ia5 12-Sep-2026 10:18:07 1140
ber01-VHDL13_DWEG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2889
ber01-VHDL13_DWEG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:28:18 3180
ber01-VHDL13_DWEH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2984
ber01-VHDL13_DWEH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:28:18 3346
ber01-VHDL13_DWEI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:28:18 2818
ber01-VHDL13_DWEI_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:28:18 3059
ber01-VHDL13_DWHG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2861
ber01-VHDL13_DWHG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 3412
ber01-VHDL13_DWHH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2943
ber01-VHDL13_DWHH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 3118
ber01-VHDL13_DWLG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2108
ber01-VHDL13_DWLG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2229
ber01-VHDL13_DWLH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2187
ber01-VHDL13_DWLH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2388
ber01-VHDL13_DWLI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2026
ber01-VHDL13_DWLI_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2146
ber01-VHDL13_DWMO_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2595
ber01-VHDL13_DWMO_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2724
ber01-VHDL13_DWMP_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2715
ber01-VHDL13_DWMP_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2962
ber01-VHDL13_DWOG_110300-2609110300-dsw--0-ia5 11-Sep-2026 03:00:11 3142
ber01-VHDL13_DWOG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 3293
ber01-VHDL13_DWOG_111700-2609111700-dsw--0-ia5 11-Sep-2026 18:00:06 2955
ber01-VHDL13_DWOG_111700_COR-2609111700-dsw--0-ia5 11-Sep-2026 18:48:23 2851
ber01-VHDL13_DWOG_120300-2609120300-dsw--0-ia5 12-Sep-2026 03:00:54 3101
ber01-VHDL13_DWOG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 3308
ber01-VHDL13_DWOG_121700-2609121700-dsw--0-ia5 12-Sep-2026 18:00:04 3011
ber01-VHDL13_DWON_110121-2609110121-dsw--0-ia5 11-Sep-2026 01:21:49 3206
ber01-VHDL13_DWON_110529-2609110529-dsw--0-ia5 11-Sep-2026 05:29:44 3662
ber01-VHDL13_DWON_110605-2609110605-dsw--0-ia5 11-Sep-2026 06:05:09 3699
ber01-VHDL13_DWON_110813-2609110813-dsw--0-ia5 11-Sep-2026 08:13:08 3601
ber01-VHDL13_DWON_111443-2609111443-dsw--0-ia5 11-Sep-2026 14:43:40 3524
ber01-VHDL13_DWON_111607-2609111607-dsw--0-ia5 11-Sep-2026 16:08:05 2959
ber01-VHDL13_DWON_111801-2609111801-dsw--0-ia5 11-Sep-2026 18:02:05 2959
ber01-VHDL13_DWON_111848-2609111848-dsw--0-ia5 11-Sep-2026 18:48:19 3017
ber01-VHDL13_DWON_120008-2609120008-dsw--0-ia5 12-Sep-2026 00:08:38 3037
ber01-VHDL13_DWON_120254-2609120254-dsw--0-ia5 12-Sep-2026 02:55:23 3037
ber01-VHDL13_DWON_120528-2609120528-dsw--0-ia5 12-Sep-2026 05:28:14 3533
ber01-VHDL13_DWON_120558-2609120558-dsw--0-ia5 12-Sep-2026 05:58:44 3555
ber01-VHDL13_DWON_120854-2609120854-dsw--0-ia5 12-Sep-2026 08:54:48 3603
ber01-VHDL13_DWON_121435-2609121435-dsw--0-ia5 12-Sep-2026 14:35:45 3726
ber01-VHDL13_DWON_121716-2609121716-dsw--0-ia5 12-Sep-2026 17:17:04 3109
ber01-VHDL13_DWON_121932-2609121932-dsw--0-ia5 12-Sep-2026 19:33:09 3704
ber01-VHDL13_DWON_122139-2609122139-dsw--0-ia5 12-Sep-2026 21:39:34 3700
ber01-VHDL13_DWON_130006-2609130006-dsw--0-ia5 13-Sep-2026 00:06:58 4473
ber01-VHDL13_DWPG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2159
ber01-VHDL13_DWPG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2180
ber01-VHDL13_DWPH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 2152
ber01-VHDL13_DWPH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2271
ber01-VHDL13_DWSG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 2489
ber01-VHDL13_DWSG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 2468
ber01-VHDL17_DWOG_111200-2609111200-dsw--0-ia5 11-Sep-2026 10:48:59 3107
ber01-VHDL17_DWOG_121200-2609121200-dsw--0-ia5 12-Sep-2026 11:28:29 3418
swis2-VHDL20_DWEG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 1041
swis2-VHDL20_DWEG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:19 1031
swis2-VHDL20_DWEG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1115
swis2-VHDL20_DWEG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1587
swis2-VHDL20_DWEG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1266
swis2-VHDL20_DWEG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1269
swis2-VHDL20_DWEG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 1538
swis2-VHDL20_DWEG_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:03 1512
swis2-VHDL20_DWEH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 908
swis2-VHDL20_DWEH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:23 905
swis2-VHDL20_DWEH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1205
swis2-VHDL20_DWEH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1686
swis2-VHDL20_DWEH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1297
swis2-VHDL20_DWEH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1278
swis2-VHDL20_DWEH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 1567
swis2-VHDL20_DWEH_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:03 1564
swis2-VHDL20_DWEI_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 895
swis2-VHDL20_DWEI_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:01:23 892
swis2-VHDL20_DWEI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1121
swis2-VHDL20_DWEI_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:03 1616
swis2-VHDL20_DWEI_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 1316
swis2-VHDL20_DWEI_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:01:28 1305
swis2-VHDL20_DWEI_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 1553
swis2-VHDL20_DWEI_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:03 1522
swis2-VHDL20_DWHG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:46:34 984
swis2-VHDL20_DWHG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 981
swis2-VHDL20_DWHG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:45:11 1142
swis2-VHDL20_DWHG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:45:15 1717
swis2-VHDL20_DWHG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:45:24 1456
swis2-VHDL20_DWHG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 1488
swis2-VHDL20_DWHG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:45:42 1454
swis2-VHDL20_DWHG_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:45:14 1451
swis2-VHDL20_DWHH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:46:34 1037
swis2-VHDL20_DWHH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 1037
swis2-VHDL20_DWHH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:45:11 1267
swis2-VHDL20_DWHH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:45:15 1745
swis2-VHDL20_DWHH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:45:24 1387
swis2-VHDL20_DWHH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 1312
swis2-VHDL20_DWHH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:45:42 1440
swis2-VHDL20_DWHH_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:45:14 1434
swis2-VHDL20_DWLG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 837
swis2-VHDL20_DWLG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 836
swis2-VHDL20_DWLG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 944
swis2-VHDL20_DWLG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 892
swis2-VHDL20_DWLG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 842
swis2-VHDL20_DWLG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 854
swis2-VHDL20_DWLG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 975
swis2-VHDL20_DWLG_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:31:05 970
swis2-VHDL20_DWLH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 843
swis2-VHDL20_DWLH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 842
swis2-VHDL20_DWLH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 1102
swis2-VHDL20_DWLH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1140
swis2-VHDL20_DWLH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 872
swis2-VHDL20_DWLH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 941
swis2-VHDL20_DWLH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 1062
swis2-VHDL20_DWLH_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:31:05 1099
swis2-VHDL20_DWLI_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 839
swis2-VHDL20_DWLI_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 838
swis2-VHDL20_DWLI_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 945
swis2-VHDL20_DWLI_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 975
swis2-VHDL20_DWLI_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 888
swis2-VHDL20_DWLI_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 856
swis2-VHDL20_DWLI_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 977
swis2-VHDL20_DWLI_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:31:05 985
swis2-VHDL20_DWMO_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 852
swis2-VHDL20_DWMO_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:09 857
swis2-VHDL20_DWMO_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1139
swis2-VHDL20_DWMO_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 1129
swis2-VHDL20_DWMO_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 929
swis2-VHDL20_DWMO_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:03 1052
swis2-VHDL20_DWMO_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 1248
swis2-VHDL20_DWMO_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:09 1335
swis2-VHDL20_DWMP_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:03 978
swis2-VHDL20_DWMP_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:09 925
swis2-VHDL20_DWMP_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:14 1246
swis2-VHDL20_DWMP_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 1103
swis2-VHDL20_DWMP_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 880
swis2-VHDL20_DWMP_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:03 1089
swis2-VHDL20_DWMP_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 1309
swis2-VHDL20_DWMP_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:09 1540
swis2-VHDL20_DWPG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 854
swis2-VHDL20_DWPG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 853
swis2-VHDL20_DWPG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 1014
swis2-VHDL20_DWPG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1036
swis2-VHDL20_DWPG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 860
swis2-VHDL20_DWPG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 872
swis2-VHDL20_DWPG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 995
swis2-VHDL20_DWPG_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:31:05 1032
swis2-VHDL20_DWPH_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:38 856
swis2-VHDL20_DWPH_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:13 855
swis2-VHDL20_DWPH_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:25 999
swis2-VHDL20_DWPH_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:31:08 1040
swis2-VHDL20_DWPH_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:23 864
swis2-VHDL20_DWPH_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:12 874
swis2-VHDL20_DWPH_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:27 997
swis2-VHDL20_DWPH_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:31:05 1018
swis2-VHDL20_DWSG_110200-2609110200-dsw--0-ia5 11-Sep-2026 02:30:05 927
swis2-VHDL20_DWSG_110400-2609110400-dsw--0-ia5 11-Sep-2026 05:00:19 910
swis2-VHDL20_DWSG_110800-2609110800-dsw--0-ia5 11-Sep-2026 08:30:15 998
swis2-VHDL20_DWSG_111800-2609111800-dsw--0-ia5 11-Sep-2026 18:30:09 972
swis2-VHDL20_DWSG_120200-2609120200-dsw--0-ia5 12-Sep-2026 02:30:03 867
swis2-VHDL20_DWSG_120400-2609120400-dsw--0-ia5 12-Sep-2026 05:00:18 889
swis2-VHDL20_DWSG_120800-2609120800-dsw--0-ia5 12-Sep-2026 08:30:03 998
swis2-VHDL20_DWSG_121800-2609121800-dsw--0-ia5 12-Sep-2026 18:30:03 1181
wst04-VHDL20_DWEG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 244507
wst04-VHDL20_DWEG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 244105
wst04-VHDL20_DWEG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:15 245049
wst04-VHDL20_DWEG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:13 248257
wst04-VHDL20_DWEG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 247377
wst04-VHDL20_DWEG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 247256
wst04-VHDL20_DWEG_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 248042
wst04-VHDL20_DWEG_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 247406
wst04-VHDL20_DWEH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 240698
wst04-VHDL20_DWEH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 240526
wst04-VHDL20_DWEH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:15 241668
wst04-VHDL20_DWEH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:13 239407
wst04-VHDL20_DWEH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 238707
wst04-VHDL20_DWEH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 238776
wst04-VHDL20_DWEH_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 239641
wst04-VHDL20_DWEH_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 242667
wst04-VHDL20_DWEI_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:26 349052
wst04-VHDL20_DWEI_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 348564
wst04-VHDL20_DWEI_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 349156
wst04-VHDL20_DWEI_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 354516
wst04-VHDL20_DWEI_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:19 353511
wst04-VHDL20_DWEI_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 353338
wst04-VHDL20_DWEI_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 354340
wst04-VHDL20_DWEI_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 356937
wst04-VHDL20_DWHG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:46:34 344492
wst04-VHDL20_DWHG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 344287
wst04-VHDL20_DWHG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:45:31 345047
wst04-VHDL20_DWHG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:45:23 343604
wst04-VHDL20_DWHG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:46:39 342193
wst04-VHDL20_DWHG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:24 342041
wst04-VHDL20_DWHG_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:45:42 343025
wst04-VHDL20_DWHG_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:45:14 356315
wst04-VHDL20_DWHH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:46:34 332509
wst04-VHDL20_DWHH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 231777
wst04-VHDL20_DWHH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:45:31 333075
wst04-VHDL20_DWHH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:45:23 334808
wst04-VHDL20_DWHH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:46:39 333714
wst04-VHDL20_DWHH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 231742
wst04-VHDL20_DWHH_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:45:42 333420
wst04-VHDL20_DWHH_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:45:14 342676
wst04-VHDL20_DWLG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 333832
wst04-VHDL20_DWLG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 333448
wst04-VHDL20_DWLG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 333504
wst04-VHDL20_DWLG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:45 337622
wst04-VHDL20_DWLG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:37 337543
wst04-VHDL20_DWLG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 337151
wst04-VHDL20_DWLG_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:42 337218
wst04-VHDL20_DWLG_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:31:23 339925
wst04-VHDL20_DWLH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 340952
wst04-VHDL20_DWLH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 340589
wst04-VHDL20_DWLH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 341621
wst04-VHDL20_DWLH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 334072
wst04-VHDL20_DWLH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 333275
wst04-VHDL20_DWLH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 332951
wst04-VHDL20_DWLH_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:42 333178
wst04-VHDL20_DWLH_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:31:23 345650
wst04-VHDL20_DWLI_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 342739
wst04-VHDL20_DWLI_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:43 342339
wst04-VHDL20_DWLI_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:54 387007
wst04-VHDL20_DWLI_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 339212
wst04-VHDL20_DWLI_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 339132
wst04-VHDL20_DWLI_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:44 338514
wst04-VHDL20_DWLI_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:53 383183
wst04-VHDL20_DWLI_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:31:29 337515
wst04-VHDL20_DWMO_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 458627
wst04-VHDL20_DWMO_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 459242
wst04-VHDL20_DWMO_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 459254
wst04-VHDL20_DWMO_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 353956
wst04-VHDL20_DWMO_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 460586
wst04-VHDL20_DWMO_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 460558
wst04-VHDL20_DWMO_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 460619
wst04-VHDL20_DWMO_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 356806
wst04-VHDL20_DWMP_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:26 561490
wst04-VHDL20_DWMP_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:19 562098
wst04-VHDL20_DWMP_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 461511
wst04-VHDL20_DWMP_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 470291
wst04-VHDL20_DWMP_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:19 575498
wst04-VHDL20_DWMP_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:18 577321
wst04-VHDL20_DWMP_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 471549
wst04-VHDL20_DWMP_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 470347
wst04-VHDL20_DWPG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 242635
wst04-VHDL20_DWPG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:33 347291
wst04-VHDL20_DWPG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 392694
wst04-VHDL20_DWPG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 342295
wst04-VHDL20_DWPG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 239209
wst04-VHDL20_DWPG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:34 341027
wst04-VHDL20_DWPG_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:42 385669
wst04-VHDL20_DWPG_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:31:23 349961
wst04-VHDL20_DWPH_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:38 239361
wst04-VHDL20_DWPH_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:33 239022
wst04-VHDL20_DWPH_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:52 239825
wst04-VHDL20_DWPH_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:31:33 238723
wst04-VHDL20_DWPH_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:23 237822
wst04-VHDL20_DWPH_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:34 237450
wst04-VHDL20_DWPH_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:42 237492
wst04-VHDL20_DWPH_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:31:23 247959
wst04-VHDL20_DWSG_110200-2609110200-omedes--0.pdf 11-Sep-2026 02:30:13 351528
wst04-VHDL20_DWSG_110400-2609110400-omedes--0.pdf 11-Sep-2026 05:00:13 350827
wst04-VHDL20_DWSG_110800-2609110800-omedes--0.pdf 11-Sep-2026 08:30:25 350852
wst04-VHDL20_DWSG_111800-2609111800-omedes--0.pdf 11-Sep-2026 18:30:19 351901
wst04-VHDL20_DWSG_120200-2609120200-omedes--0.pdf 12-Sep-2026 02:30:15 351027
wst04-VHDL20_DWSG_120400-2609120400-omedes--0.pdf 12-Sep-2026 05:00:12 351006
wst04-VHDL20_DWSG_120800-2609120800-omedes--0.pdf 12-Sep-2026 08:30:27 351423
wst04-VHDL20_DWSG_121800-2609121800-omedes--0.pdf 12-Sep-2026 18:30:30 357239