Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Aug-2026 13:29:28 4249
FPDL13_DWMZ_260600 26-Aug-2026 11:21:33 4091
SXDL31_DWAV_250800 25-Aug-2026 07:25:54 7217
SXDL31_DWAV_251800 25-Aug-2026 15:39:06 6092
SXDL31_DWAV_260800 26-Aug-2026 07:46:40 8201
SXDL31_DWAV_261800 26-Aug-2026 17:27:34 6021
SXDL31_DWAV_LATEST 26-Aug-2026 17:27:34 6021
SXDL33_DWAV_250000 25-Aug-2026 10:45:39 11145
SXDL33_DWAV_260000 26-Aug-2026 10:09:29 5950
SXDL33_DWAV_LATEST 26-Aug-2026 10:09:29 5950
ber01-FWDL39_DWMS_251200-2608251200-dsw--0-ia5 25-Aug-2026 11:31:24 1866
ber01-FWDL39_DWMS_261200-2608261200-dsw--0-ia5 26-Aug-2026 08:53:56 1544
ber01-VHDL13_DWEG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:14 2771
ber01-VHDL13_DWEG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 2818
ber01-VHDL13_DWEG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:28:19 3084
ber01-VHDL13_DWEH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:14 2943
ber01-VHDL13_DWEH_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 3215
ber01-VHDL13_DWEH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:28:14 3709
ber01-VHDL13_DWEH_260800_COR-2608260800-dsw--0-ia5 26-Aug-2026 15:09:11 4271
ber01-VHDL13_DWEI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:28:18 3314
ber01-VHDL13_DWEI_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:39:19 3448
ber01-VHDL13_DWEI_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:28:19 3471
ber01-VHDL13_DWEI_260800_COR-2608260800-dsw--0-ia5 26-Aug-2026 15:10:38 4003
ber01-VHDL13_DWHG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:10 3237
ber01-VHDL13_DWHG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:20 3300
ber01-VHDL13_DWHH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:10 3078
ber01-VHDL13_DWHH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:20 3282
ber01-VHDL13_DWLG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2521
ber01-VHDL13_DWLG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2510
ber01-VHDL13_DWLH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2930
ber01-VHDL13_DWLH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 3020
ber01-VHDL13_DWLI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2804
ber01-VHDL13_DWLI_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2851
ber01-VHDL13_DWMO_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3566
ber01-VHDL13_DWMO_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:05 2974
ber01-VHDL13_DWMP_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3619
ber01-VHDL13_DWMP_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:05 3401
ber01-VHDL13_DWOG_250300-2608250300-dsw--0-ia5 25-Aug-2026 03:00:11 4151
ber01-VHDL13_DWOG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 3783
ber01-VHDL13_DWOG_251700-2608251700-dsw--0-ia5 25-Aug-2026 18:00:03 3535
ber01-VHDL13_DWOG_260300-2608260300-dsw--0-ia5 26-Aug-2026 03:00:19 4282
ber01-VHDL13_DWOG_260800-2608260800-dsw--0-ia5 26-Aug-2026 14:58:20 3048
ber01-VHDL13_DWOG_260800_COR-2608260800-dsw--0-ia5 26-Aug-2026 15:02:12 3023
ber01-VHDL13_DWOG_261700-2608261700-dsw--0-ia5 26-Aug-2026 18:00:09 3685
ber01-VHDL13_DWON_242154-2608242154-dsw--0-ia5 24-Aug-2026 21:54:33 3551
ber01-VHDL13_DWON_250004-2608250004-dsw--0-ia5 25-Aug-2026 00:04:09 3959
ber01-VHDL13_DWON_250149-2608250149-dsw--0-ia5 25-Aug-2026 01:49:48 4011
ber01-VHDL13_DWON_250253-2608250253-dsw--0-ia5 25-Aug-2026 02:53:50 4010
ber01-VHDL13_DWON_250307-2608250307-dsw--0-ia5 25-Aug-2026 03:08:08 4010
ber01-VHDL13_DWON_250528-2608250528-dsw--0-ia5 25-Aug-2026 05:28:20 3831
ber01-VHDL13_DWON_250624-2608250624-dsw--0-ia5 25-Aug-2026 06:24:58 3721
ber01-VHDL13_DWON_250811-2608250811-dsw--0-ia5 25-Aug-2026 08:11:09 3753
ber01-VHDL13_DWON_251454-2608251454-dsw--0-ia5 25-Aug-2026 14:54:25 3752
ber01-VHDL13_DWON_251546-2608251546-dsw--0-ia5 25-Aug-2026 15:46:53 3438
ber01-VHDL13_DWON_251723-2608251723-dsw--0-ia5 25-Aug-2026 17:23:39 3438
ber01-VHDL13_DWON_251902-2608251902-dsw--0-ia5 25-Aug-2026 19:02:49 3969
ber01-VHDL13_DWON_251937-2608251937-dsw--0-ia5 25-Aug-2026 19:38:06 3969
ber01-VHDL13_DWON_252124-2608252124-dsw--0-ia5 25-Aug-2026 21:24:13 4015
ber01-VHDL13_DWON_260009-2608260009-dsw--0-ia5 26-Aug-2026 00:10:10 4527
ber01-VHDL13_DWON_260142-2608260142-dsw--0-ia5 26-Aug-2026 01:42:36 4471
ber01-VHDL13_DWON_260251-2608260251-dsw--0-ia5 26-Aug-2026 02:52:20 4525
ber01-VHDL13_DWON_260515-2608260515-dsw--0-ia5 26-Aug-2026 05:15:28 4610
ber01-VHDL13_DWON_260551-2608260551-dsw--0-ia5 26-Aug-2026 05:51:49 4610
ber01-VHDL13_DWON_260807-2608260807-dsw--0-ia5 26-Aug-2026 08:07:23 4610
ber01-VHDL13_DWON_261457-2608261457-dsw--0-ia5 26-Aug-2026 14:58:08 3410
ber01-VHDL13_DWON_261501-2608261501-dsw--0-ia5 26-Aug-2026 15:01:39 3335
ber01-VHDL13_DWON_261558-2608261558-dsw--0-ia5 26-Aug-2026 15:58:54 3335
ber01-VHDL13_DWON_261649-2608261649-dsw--0-ia5 26-Aug-2026 16:49:14 3281
ber01-VHDL13_DWON_261729-2608261729-dsw--0-ia5 26-Aug-2026 17:29:33 3281
ber01-VHDL13_DWPG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2509
ber01-VHDL13_DWPG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2547
ber01-VHDL13_DWPH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:02 2622
ber01-VHDL13_DWPH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2934
ber01-VHDL13_DWSG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 3757
ber01-VHDL13_DWSG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 10:51:49 3628
ber01-VHDL13_DWSG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 3870
ber01-VHDL17_DWOG_251200-2608251200-dsw--0-ia5 25-Aug-2026 11:57:09 3227
ber01-VHDL17_DWOG_261200-2608261200-dsw--0-ia5 26-Aug-2026 11:38:00 2717
swis2-VHDL20_DWEG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 783
swis2-VHDL20_DWEG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 805
swis2-VHDL20_DWEG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1212
swis2-VHDL20_DWEG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1252
swis2-VHDL20_DWEG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1373
swis2-VHDL20_DWEG_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1156
swis2-VHDL20_DWEG_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:01:25 1237
swis2-VHDL20_DWEG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 1694
swis2-VHDL20_DWEG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 1796
swis2-VHDL20_DWEH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1000
swis2-VHDL20_DWEH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 1004
swis2-VHDL20_DWEH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1405
swis2-VHDL20_DWEH_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1794
swis2-VHDL20_DWEH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1889
swis2-VHDL20_DWEH_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1457
swis2-VHDL20_DWEH_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:01:25 1595
swis2-VHDL20_DWEH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2123
swis2-VHDL20_DWEH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2731
swis2-VHDL20_DWEI_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1413
swis2-VHDL20_DWEI_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:01:12 1284
swis2-VHDL20_DWEI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:04 1691
swis2-VHDL20_DWEI_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 08:38:58 1982
swis2-VHDL20_DWEI_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1689
swis2-VHDL20_DWEI_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1405
swis2-VHDL20_DWEI_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:01:25 1536
swis2-VHDL20_DWEI_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 2160
swis2-VHDL20_DWEI_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2409
swis2-VHDL20_DWHG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:46:28 1201
swis2-VHDL20_DWHG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 1197
swis2-VHDL20_DWHG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:48:26 1482
swis2-VHDL20_DWHG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:45:08 1695
swis2-VHDL20_DWHG_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:46:05 1447
swis2-VHDL20_DWHG_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:19 1444
swis2-VHDL20_DWHG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:46:10 1702
swis2-VHDL20_DWHG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:45:04 1929
swis2-VHDL20_DWHH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:46:28 1368
swis2-VHDL20_DWHH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 1378
swis2-VHDL20_DWHH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:48:26 1637
swis2-VHDL20_DWHH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:45:08 1838
swis2-VHDL20_DWHH_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:46:05 1586
swis2-VHDL20_DWHH_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:19 1586
swis2-VHDL20_DWHH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:46:10 1851
swis2-VHDL20_DWHH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:45:04 2312
swis2-VHDL20_DWLG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 738
swis2-VHDL20_DWLG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 751
swis2-VHDL20_DWLG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1138
swis2-VHDL20_DWLG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1207
swis2-VHDL20_DWLG_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:23 836
swis2-VHDL20_DWLG_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:13 846
swis2-VHDL20_DWLG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:34 994
swis2-VHDL20_DWLG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1738
swis2-VHDL20_DWLH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 745
swis2-VHDL20_DWLH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 943
swis2-VHDL20_DWLH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1367
swis2-VHDL20_DWLH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1422
swis2-VHDL20_DWLH_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:23 1328
swis2-VHDL20_DWLH_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:13 960
swis2-VHDL20_DWLH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:34 1160
swis2-VHDL20_DWLH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1842
swis2-VHDL20_DWLI_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 837
swis2-VHDL20_DWLI_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 880
swis2-VHDL20_DWLI_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 1159
swis2-VHDL20_DWLI_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1423
swis2-VHDL20_DWLI_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:23 1129
swis2-VHDL20_DWLI_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:13 937
swis2-VHDL20_DWLI_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:34 1087
swis2-VHDL20_DWLI_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1625
swis2-VHDL20_DWMO_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1145
swis2-VHDL20_DWMO_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:05 1274
swis2-VHDL20_DWMO_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1590
swis2-VHDL20_DWMO_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1754
swis2-VHDL20_DWMO_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1228
swis2-VHDL20_DWMO_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:05 1232
swis2-VHDL20_DWMO_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:05 1431
swis2-VHDL20_DWMO_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2223
swis2-VHDL20_DWMP_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1150
swis2-VHDL20_DWMP_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:05 1278
swis2-VHDL20_DWMP_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1919
swis2-VHDL20_DWMP_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 2098
swis2-VHDL20_DWMP_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1484
swis2-VHDL20_DWMP_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:05 1484
swis2-VHDL20_DWMP_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:05 1659
swis2-VHDL20_DWMP_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2358
swis2-VHDL20_DWPG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 845
swis2-VHDL20_DWPG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 855
swis2-VHDL20_DWPG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 835
swis2-VHDL20_DWPG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 935
swis2-VHDL20_DWPG_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:23 875
swis2-VHDL20_DWPG_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:13 885
swis2-VHDL20_DWPG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:34 1021
swis2-VHDL20_DWPG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1528
swis2-VHDL20_DWPH_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:31 864
swis2-VHDL20_DWPH_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:13 847
swis2-VHDL20_DWPH_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:24 996
swis2-VHDL20_DWPH_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:31:05 1030
swis2-VHDL20_DWPH_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:23 1036
swis2-VHDL20_DWPH_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:13 1080
swis2-VHDL20_DWPH_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:34 1227
swis2-VHDL20_DWPH_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:31:09 1701
swis2-VHDL20_DWSG_250200-2608250200-dsw--0-ia5 25-Aug-2026 02:30:06 1184
swis2-VHDL20_DWSG_250400-2608250400-dsw--0-ia5 25-Aug-2026 05:00:19 1351
swis2-VHDL20_DWSG_250800-2608250800-dsw--0-ia5 25-Aug-2026 08:30:08 1864
swis2-VHDL20_DWSG_250800_COR-2608250800-dsw--0-ia5 25-Aug-2026 10:51:49 1735
swis2-VHDL20_DWSG_251800-2608251800-dsw--0-ia5 25-Aug-2026 18:30:11 1977
swis2-VHDL20_DWSG_260200-2608260200-dsw--0-ia5 26-Aug-2026 02:30:05 1398
swis2-VHDL20_DWSG_260400-2608260400-dsw--0-ia5 26-Aug-2026 05:00:19 1385
swis2-VHDL20_DWSG_260800-2608260800-dsw--0-ia5 26-Aug-2026 08:30:03 1713
swis2-VHDL20_DWSG_261800-2608261800-dsw--0-ia5 26-Aug-2026 18:30:10 2049
wst04-VHDL20_DWEG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 246737
wst04-VHDL20_DWEG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 246325
wst04-VHDL20_DWEG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:14 247711
wst04-VHDL20_DWEG_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 247719
wst04-VHDL20_DWEG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 243620
wst04-VHDL20_DWEG_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:21 242957
wst04-VHDL20_DWEG_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:13 242585
wst04-VHDL20_DWEG_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:34 243220
wst04-VHDL20_DWEG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 247490
wst04-VHDL20_DWEH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 243643
wst04-VHDL20_DWEH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 243489
wst04-VHDL20_DWEH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:14 244697
wst04-VHDL20_DWEH_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 245235
wst04-VHDL20_DWEH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 243461
wst04-VHDL20_DWEH_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:21 242589
wst04-VHDL20_DWEH_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:13 243145
wst04-VHDL20_DWEH_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:34 243893
wst04-VHDL20_DWEH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 246642
wst04-VHDL20_DWEI_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 359701
wst04-VHDL20_DWEI_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 359098
wst04-VHDL20_DWEI_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:18 360469
wst04-VHDL20_DWEI_250800_COR-2608250800-omedes-..> 25-Aug-2026 08:39:19 360588
wst04-VHDL20_DWEI_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 354148
wst04-VHDL20_DWEI_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 353437
wst04-VHDL20_DWEI_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:19 353632
wst04-VHDL20_DWEI_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:34 354572
wst04-VHDL20_DWEI_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 357481
wst04-VHDL20_DWHG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:46:28 346184
wst04-VHDL20_DWHG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 345961
wst04-VHDL20_DWHG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:48:26 347334
wst04-VHDL20_DWHG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:45:29 351933
wst04-VHDL20_DWHG_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:46:05 350734
wst04-VHDL20_DWHG_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:19 350519
wst04-VHDL20_DWHG_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:46:10 351923
wst04-VHDL20_DWHG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:45:30 351892
wst04-VHDL20_DWHH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:46:28 336863
wst04-VHDL20_DWHH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 231355
wst04-VHDL20_DWHH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:48:26 338213
wst04-VHDL20_DWHH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:45:29 344069
wst04-VHDL20_DWHH_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:46:05 343205
wst04-VHDL20_DWHH_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:19 234243
wst04-VHDL20_DWHH_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:46:10 343802
wst04-VHDL20_DWHH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:45:30 342308
wst04-VHDL20_DWLG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 336474
wst04-VHDL20_DWLG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 336534
wst04-VHDL20_DWLG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:48 337709
wst04-VHDL20_DWLG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 343014
wst04-VHDL20_DWLG_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 386249
wst04-VHDL20_DWLG_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:43 341676
wst04-VHDL20_DWLG_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:56 342404
wst04-VHDL20_DWLG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 342959
wst04-VHDL20_DWLH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 331557
wst04-VHDL20_DWLH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 332086
wst04-VHDL20_DWLH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 333766
wst04-VHDL20_DWLH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 344652
wst04-VHDL20_DWLH_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 388229
wst04-VHDL20_DWLH_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:43 342771
wst04-VHDL20_DWLH_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:56 343212
wst04-VHDL20_DWLH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 345567
wst04-VHDL20_DWLI_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 340969
wst04-VHDL20_DWLI_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:44 340838
wst04-VHDL20_DWLI_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 385956
wst04-VHDL20_DWLI_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:30 345856
wst04-VHDL20_DWLI_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 390000
wst04-VHDL20_DWLI_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:43 345323
wst04-VHDL20_DWLI_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:56 390201
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wst04-VHDL20_DWMO_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 461175
wst04-VHDL20_DWMO_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 461130
wst04-VHDL20_DWMO_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:18 461041
wst04-VHDL20_DWMO_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 360128
wst04-VHDL20_DWMO_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:21 470921
wst04-VHDL20_DWMO_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:13 470804
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wst04-VHDL20_DWMO_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 354035
wst04-VHDL20_DWMP_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 578204
wst04-VHDL20_DWMP_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:19 578098
wst04-VHDL20_DWMP_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:24 471507
wst04-VHDL20_DWMP_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:24 480845
wst04-VHDL20_DWMP_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 589466
wst04-VHDL20_DWMP_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:19 589489
wst04-VHDL20_DWMP_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:34 479594
wst04-VHDL20_DWMP_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 470874
wst04-VHDL20_DWPG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:39 239515
wst04-VHDL20_DWPG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:34 339608
wst04-VHDL20_DWPG_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 384565
wst04-VHDL20_DWPG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 350913
wst04-VHDL20_DWPG_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 245162
wst04-VHDL20_DWPG_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:33 350306
wst04-VHDL20_DWPG_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:56 395308
wst04-VHDL20_DWPG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 348676
wst04-VHDL20_DWPH_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:31 238321
wst04-VHDL20_DWPH_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:34 238131
wst04-VHDL20_DWPH_250800-2608250800-omedes--0.pdf 25-Aug-2026 08:30:44 239162
wst04-VHDL20_DWPH_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:31:28 244886
wst04-VHDL20_DWPH_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:23 289200
wst04-VHDL20_DWPH_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:33 245210
wst04-VHDL20_DWPH_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:56 245461
wst04-VHDL20_DWPH_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:31:33 245414
wst04-VHDL20_DWSG_250200-2608250200-omedes--0.pdf 25-Aug-2026 02:30:24 358074
wst04-VHDL20_DWSG_250400-2608250400-omedes--0.pdf 25-Aug-2026 05:00:13 359628
wst04-VHDL20_DWSG_250800-2608250800-omedes--0.pdf 25-Aug-2026 10:51:59 360268
wst04-VHDL20_DWSG_251800-2608251800-omedes--0.pdf 25-Aug-2026 18:30:19 359967
wst04-VHDL20_DWSG_260200-2608260200-omedes--0.pdf 26-Aug-2026 02:30:21 358387
wst04-VHDL20_DWSG_260400-2608260400-omedes--0.pdf 26-Aug-2026 05:00:13 358169
wst04-VHDL20_DWSG_260800-2608260800-omedes--0.pdf 26-Aug-2026 08:30:34 359892
wst04-VHDL20_DWSG_261800-2608261800-omedes--0.pdf 26-Aug-2026 18:30:25 354857