Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_280600 28-Mar-2026 15:06:35 4565
FPDL13_DWMZ_290600 29-Mar-2026 13:50:44 4837
SXDL31_DWAV_271800 27-Mar-2026 17:40:44 6466
SXDL31_DWAV_280800 28-Mar-2026 07:46:05 14739
SXDL31_DWAV_281800 28-Mar-2026 16:05:10 7088
SXDL31_DWAV_290800 29-Mar-2026 08:48:58 14380
SXDL31_DWAV_LATEST 29-Mar-2026 08:48:58 14380
SXDL33_DWAV_280000 28-Mar-2026 10:45:05 8845
SXDL33_DWAV_LATEST 28-Mar-2026 10:45:05 8845
ber01-FWDL39_DWMS_281230-2603281230-dsw--0-ia5 28-Mar-2026 11:59:07 1514
ber01-FWDL39_DWMS_291230-2603291230-dsw--0-ia5 29-Mar-2026 11:36:17 1426
ber01-VHDL13_DWEH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:28:16 3052
ber01-VHDL13_DWEH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:28:13 3425
ber01-VHDL13_DWEH_280400-2603280400-dsw--0-ia5 28-Mar-2026 05:58:16 3582
ber01-VHDL13_DWEH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:28:17 3619
ber01-VHDL13_DWEH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:17 3172
ber01-VHDL13_DWEH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3280
ber01-VHDL13_DWEH_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:11 3149
ber01-VHDL13_DWEH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:11 3224
ber01-VHDL13_DWHG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 3237
ber01-VHDL13_DWHG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 3462
ber01-VHDL13_DWHG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:12 3351
ber01-VHDL13_DWHG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 3595
ber01-VHDL13_DWHG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3888
ber01-VHDL13_DWHG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:07 3680
ber01-VHDL13_DWHG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3707
ber01-VHDL13_DWHG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3838
ber01-VHDL13_DWHH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2487
ber01-VHDL13_DWHH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 2864
ber01-VHDL13_DWHH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:12 2728
ber01-VHDL13_DWHH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 3215
ber01-VHDL13_DWHH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3573
ber01-VHDL13_DWHH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:07 3328
ber01-VHDL13_DWHH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3353
ber01-VHDL13_DWHH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3512
ber01-VHDL13_DWLG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2949
ber01-VHDL13_DWLG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 3112
ber01-VHDL13_DWLG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:06 3214
ber01-VHDL13_DWLG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 3455
ber01-VHDL13_DWLG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3588
ber01-VHDL13_DWLG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3491
ber01-VHDL13_DWLG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3423
ber01-VHDL13_DWLG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3274
ber01-VHDL13_DWLH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2794
ber01-VHDL13_DWLH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 3043
ber01-VHDL13_DWLH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:06 3116
ber01-VHDL13_DWLH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 3311
ber01-VHDL13_DWLH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3048
ber01-VHDL13_DWLH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3104
ber01-VHDL13_DWLH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3248
ber01-VHDL13_DWLH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3068
ber01-VHDL13_DWLI_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2609
ber01-VHDL13_DWLI_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 2753
ber01-VHDL13_DWLI_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:06 2826
ber01-VHDL13_DWLI_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 3229
ber01-VHDL13_DWLI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3125
ber01-VHDL13_DWLI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3175
ber01-VHDL13_DWLI_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3137
ber01-VHDL13_DWLI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2955
ber01-VHDL13_DWMG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 3047
ber01-VHDL13_DWMG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:03 3538
ber01-VHDL13_DWMG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:02 3440
ber01-VHDL13_DWMG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 3324
ber01-VHDL13_DWMG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3243
ber01-VHDL13_DWMG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3483
ber01-VHDL13_DWMG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3273
ber01-VHDL13_DWMG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3767
ber01-VHDL13_DWMO_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2923
ber01-VHDL13_DWMO_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:03 3374
ber01-VHDL13_DWMO_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:02 3373
ber01-VHDL13_DWMO_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 3318
ber01-VHDL13_DWMO_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2965
ber01-VHDL13_DWMO_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3279
ber01-VHDL13_DWMO_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3240
ber01-VHDL13_DWMO_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3548
ber01-VHDL13_DWMP_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2941
ber01-VHDL13_DWMP_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:03 3698
ber01-VHDL13_DWMP_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:02 3377
ber01-VHDL13_DWMP_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 3344
ber01-VHDL13_DWMP_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3257
ber01-VHDL13_DWMP_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3392
ber01-VHDL13_DWMP_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3143
ber01-VHDL13_DWMP_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3728
ber01-VHDL13_DWOG_271700-2603271700-dsw--0-ia5 27-Mar-2026 19:00:02 4011
ber01-VHDL13_DWOG_280300-2603280300-dsw--0-ia5 28-Mar-2026 04:00:02 4211
ber01-VHDL13_DWOG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:07 4454
ber01-VHDL13_DWOG_281700-2603281700-dsw--0-ia5 28-Mar-2026 19:00:02 4150
ber01-VHDL13_DWOG_290300-2603290300-dsw--0-ia5 29-Mar-2026 03:00:06 4936
ber01-VHDL13_DWOG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 5155
ber01-VHDL13_DWOH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:28:16 2876
ber01-VHDL13_DWOH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:28:13 3158
ber01-VHDL13_DWOH_280400-2603280400-dsw--0-ia5 28-Mar-2026 05:58:12 3434
ber01-VHDL13_DWOH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:28:11 3411
ber01-VHDL13_DWOH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:11 3278
ber01-VHDL13_DWOH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3220
ber01-VHDL13_DWOH_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:11 3087
ber01-VHDL13_DWOH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:17 3222
ber01-VHDL13_DWOI_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:28:11 3000
ber01-VHDL13_DWOI_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:28:17 3322
ber01-VHDL13_DWOI_280400-2603280400-dsw--0-ia5 28-Mar-2026 05:58:16 3527
ber01-VHDL13_DWOI_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:28:17 3562
ber01-VHDL13_DWOI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:17 3256
ber01-VHDL13_DWOI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3186
ber01-VHDL13_DWOI_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:17 3065
ber01-VHDL13_DWOI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:17 3230
ber01-VHDL13_DWON_271745-2603271745-dsw--0-ia5 27-Mar-2026 17:45:16 3414
ber01-VHDL13_DWON_280201-2603280201-dsw--0-ia5 28-Mar-2026 02:01:26 3227
ber01-VHDL13_DWON_280341-2603280341-dsw--0-ia5 28-Mar-2026 03:41:26 3227
ber01-VHDL13_DWON_280349-2603280349-dsw--0-ia5 28-Mar-2026 03:49:47 3227
ber01-VHDL13_DWON_280631-2603280631-dsw--0-ia5 28-Mar-2026 06:31:55 3139
ber01-VHDL13_DWON_281225-2603281225-dsw--0-ia5 28-Mar-2026 12:26:00 3139
ber01-VHDL13_DWON_281616-2603281616-dsw--0-ia5 28-Mar-2026 16:17:01 3064
ber01-VHDL13_DWON_281748-2603281748-dsw--0-ia5 28-Mar-2026 17:48:36 3114
ber01-VHDL13_DWON_282228-2603282228-dsw--0-ia5 28-Mar-2026 22:28:31 3111
ber01-VHDL13_DWON_290139-2603290139-dsw--0-ia5 29-Mar-2026 01:39:51 3310
ber01-VHDL13_DWON_290144-2603290144-dsw--0-ia5 29-Mar-2026 01:44:57 3306
ber01-VHDL13_DWON_290353-2603290353-dsw--0-ia5 29-Mar-2026 03:53:11 3306
ber01-VHDL13_DWON_290519-2603290519-dsw--0-ia5 29-Mar-2026 05:19:30 3748
ber01-VHDL13_DWON_290620-2603290620-dsw--0-ia5 29-Mar-2026 06:20:57 3748
ber01-VHDL13_DWON_290827-2603290827-dsw--0-ia5 29-Mar-2026 08:27:57 3748
ber01-VHDL13_DWON_290840-2603290840-dsw--0-ia5 29-Mar-2026 08:40:37 3748
ber01-VHDL13_DWON_291439-2603291439-dsw--0-ia5 29-Mar-2026 14:39:36 3179
ber01-VHDL13_DWPG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2654
ber01-VHDL13_DWPG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 2965
ber01-VHDL13_DWPG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:06 2946
ber01-VHDL13_DWPG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 2981
ber01-VHDL13_DWPG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2608
ber01-VHDL13_DWPG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 2726
ber01-VHDL13_DWPG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 2912
ber01-VHDL13_DWPG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2670
ber01-VHDL13_DWPH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 2669
ber01-VHDL13_DWPH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:07 2960
ber01-VHDL13_DWPH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:06 2916
ber01-VHDL13_DWPH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 2979
ber01-VHDL13_DWPH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2814
ber01-VHDL13_DWPH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 2670
ber01-VHDL13_DWPH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 2696
ber01-VHDL13_DWPH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2533
ber01-VHDL13_DWSG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:30:09 3005
ber01-VHDL13_DWSG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:30:03 3159
ber01-VHDL13_DWSG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:12 3213
ber01-VHDL13_DWSG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:30:01 3114
ber01-VHDL13_DWSG_280800_COR-2603280800-dsw--0-ia5 28-Mar-2026 10:25:07 3144
ber01-VHDL13_DWSG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3279
ber01-VHDL13_DWSG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3155
ber01-VHDL13_DWSG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3306
ber01-VHDL13_DWSG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3600
ber01-VHDL17_DWOG_281200-2603281200-dsw--0-ia5 28-Mar-2026 12:51:42 3255
ber01-VHDL17_DWOG_291200-2603291200-dsw--0-ia5 29-Mar-2026 11:54:27 2900
swis2-VHDL20_DWEG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:06 3319
swis2-VHDL20_DWEG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:06 3540
swis2-VHDL20_DWEG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:15:06 3914
swis2-VHDL20_DWEG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:01 4124
swis2-VHDL20_DWEG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3764
swis2-VHDL20_DWEG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3659
swis2-VHDL20_DWEG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3521
swis2-VHDL20_DWEG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3932
swis2-VHDL20_DWEH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:06 3478
swis2-VHDL20_DWEH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:06 3811
swis2-VHDL20_DWEH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:15:06 4075
swis2-VHDL20_DWEH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:06 4358
swis2-VHDL20_DWEH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3711
swis2-VHDL20_DWEH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3817
swis2-VHDL20_DWEH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3595
swis2-VHDL20_DWEH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3956
swis2-VHDL20_DWEI_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:06 3470
swis2-VHDL20_DWEI_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:06 3729
swis2-VHDL20_DWEI_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:15:06 4038
swis2-VHDL20_DWEI_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:01 4322
swis2-VHDL20_DWEI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3767
swis2-VHDL20_DWEI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3641
swis2-VHDL20_DWEI_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3530
swis2-VHDL20_DWEI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3987
swis2-VHDL20_DWHG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:06 3420
swis2-VHDL20_DWHG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:01 3648
swis2-VHDL20_DWHG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:12 3534
swis2-VHDL20_DWHG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:06 4389
swis2-VHDL20_DWHG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 4071
swis2-VHDL20_DWHG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:06 3866
swis2-VHDL20_DWHG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3890
swis2-VHDL20_DWHG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4506
swis2-VHDL20_DWHH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:06 2673
swis2-VHDL20_DWHH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:01 3050
swis2-VHDL20_DWHH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:12 2914
swis2-VHDL20_DWHH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:06 3822
swis2-VHDL20_DWHH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3759
swis2-VHDL20_DWHH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:06 3514
swis2-VHDL20_DWHH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3539
swis2-VHDL20_DWHH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4054
swis2-VHDL20_DWLG_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:02 3290
swis2-VHDL20_DWLG_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:06 3453
swis2-VHDL20_DWLG_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:16 3645
swis2-VHDL20_DWLG_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:06 4072
swis2-VHDL20_DWLG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 4019
swis2-VHDL20_DWLG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3922
swis2-VHDL20_DWLG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3821
swis2-VHDL20_DWLG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3938
swis2-VHDL20_DWLH_271800-2603271800-dsw--0-ia5 27-Mar-2026 19:45:02 3142
swis2-VHDL20_DWLH_280200-2603280200-dsw--0-ia5 28-Mar-2026 03:45:06 3391
swis2-VHDL20_DWLH_280400-2603280400-dsw--0-ia5 28-Mar-2026 06:00:16 3550
swis2-VHDL20_DWLH_280800-2603280800-dsw--0-ia5 28-Mar-2026 09:45:01 3930
swis2-VHDL20_DWLH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3482
swis2-VHDL20_DWLH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3492
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