Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Aug-2026 13:59:58 4236
FPDL13_DWMZ_040600 04-Aug-2026 14:30:14 3857
SXDL31_DWAV_030800 03-Aug-2026 07:43:48 15668
SXDL31_DWAV_031800 03-Aug-2026 16:36:51 3343
SXDL31_DWAV_040800 04-Aug-2026 08:14:04 9592
SXDL31_DWAV_041800 04-Aug-2026 16:15:49 7881
SXDL31_DWAV_LATEST 04-Aug-2026 16:15:49 7881
SXDL33_DWAV_030000 03-Aug-2026 10:38:20 9514
SXDL33_DWAV_040000 04-Aug-2026 10:18:04 14152
SXDL33_DWAV_LATEST 04-Aug-2026 10:18:04 14152
ber01-FWDL39_DWMS_031200-2608031200-dsw--0-ia5 03-Aug-2026 12:07:17 1947
ber01-FWDL39_DWMS_041200-2608041200-dsw--0-ia5 04-Aug-2026 11:21:17 1368
ber01-VHDL13_DWEG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:23 3553
ber01-VHDL13_DWEG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:12 3172
ber01-VHDL13_DWEH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:23 3568
ber01-VHDL13_DWEH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:16 3227
ber01-VHDL13_DWEI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:28:27 3649
ber01-VHDL13_DWEI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:28:22 2919
ber01-VHDL13_DWHG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3996
ber01-VHDL13_DWHG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3584
ber01-VHDL13_DWHH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3669
ber01-VHDL13_DWHH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 4020
ber01-VHDL13_DWLG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3096
ber01-VHDL13_DWLG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3103
ber01-VHDL13_DWLH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3330
ber01-VHDL13_DWLH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3132
ber01-VHDL13_DWLI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3389
ber01-VHDL13_DWLI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3091
ber01-VHDL13_DWMO_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3758
ber01-VHDL13_DWMO_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3447
ber01-VHDL13_DWMP_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3837
ber01-VHDL13_DWMP_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3768
ber01-VHDL13_DWOG_030300-2608030300-dsw--0-ia5 03-Aug-2026 03:00:21 3796
ber01-VHDL13_DWOG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3963
ber01-VHDL13_DWOG_031700-2608031700-dsw--0-ia5 03-Aug-2026 18:00:02 4302
ber01-VHDL13_DWOG_040300-2608040300-dsw--0-ia5 04-Aug-2026 03:00:06 3644
ber01-VHDL13_DWOG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3675
ber01-VHDL13_DWOG_041700-2608041700-dsw--0-ia5 04-Aug-2026 18:00:01 5156
ber01-VHDL13_DWOG_041700_COR-2608041700-dsw--0-ia5 04-Aug-2026 17:23:57 5160
ber01-VHDL13_DWON_030115-2608030115-dsw--0-ia5 03-Aug-2026 01:15:42 3118
ber01-VHDL13_DWON_030247-2608030247-dsw--0-ia5 03-Aug-2026 02:48:35 3470
ber01-VHDL13_DWON_030524-2608030524-dsw--0-ia5 03-Aug-2026 05:24:42 3578
ber01-VHDL13_DWON_030553-2608030553-dsw--0-ia5 03-Aug-2026 05:53:51 3578
ber01-VHDL13_DWON_030824-2608030824-dsw--0-ia5 03-Aug-2026 08:24:37 3647
ber01-VHDL13_DWON_031019-2608031019-dsw--0-ia5 03-Aug-2026 10:19:27 3647
ber01-VHDL13_DWON_031445-2608031445-dsw--0-ia5 03-Aug-2026 14:47:20 3417
ber01-VHDL13_DWON_031650-2608031650-dsw--0-ia5 03-Aug-2026 16:50:38 2991
ber01-VHDL13_DWON_031651-2608031651-dsw--0-ia5 03-Aug-2026 16:51:37 2991
ber01-VHDL13_DWON_031841-2608031841-dsw--0-ia5 03-Aug-2026 18:41:06 3004
ber01-VHDL13_DWON_040012-2608040012-dsw--0-ia5 04-Aug-2026 00:12:07 3157
ber01-VHDL13_DWON_040252-2608040252-dsw--0-ia5 04-Aug-2026 02:52:31 3157
ber01-VHDL13_DWON_040529-2608040529-dsw--0-ia5 04-Aug-2026 05:29:36 3473
ber01-VHDL13_DWON_040629-2608040629-dsw--0-ia5 04-Aug-2026 06:29:27 3490
ber01-VHDL13_DWON_040722-2608040722-dsw--0-ia5 04-Aug-2026 07:22:06 3490
ber01-VHDL13_DWON_041520-2608041520-dsw--0-ia5 04-Aug-2026 15:20:41 3648
ber01-VHDL13_DWON_041723-2608041723-dsw--0-ia5 04-Aug-2026 17:23:31 4010
ber01-VHDL13_DWPG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3346
ber01-VHDL13_DWPG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3252
ber01-VHDL13_DWPH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 3368
ber01-VHDL13_DWPH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3272
ber01-VHDL13_DWSG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 4143
ber01-VHDL13_DWSG_030800_COR-2608030800-dsw--0-ia5 03-Aug-2026 12:19:32 4097
ber01-VHDL13_DWSG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 3496
ber01-VHDL17_DWOG_031200-2608031200-dsw--0-ia5 03-Aug-2026 12:00:01 2637
ber01-VHDL17_DWOG_041200-2608041200-dsw--0-ia5 04-Aug-2026 10:49:42 3444
swis2-VHDL20_DWEG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1638
swis2-VHDL20_DWEG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1788
swis2-VHDL20_DWEG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2064
swis2-VHDL20_DWEG_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:06 1807
swis2-VHDL20_DWEG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1550
swis2-VHDL20_DWEG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1641
swis2-VHDL20_DWEG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1695
swis2-VHDL20_DWEG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2140
swis2-VHDL20_DWEH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1676
swis2-VHDL20_DWEH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1801
swis2-VHDL20_DWEH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2024
swis2-VHDL20_DWEH_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:06 1804
swis2-VHDL20_DWEH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1542
swis2-VHDL20_DWEH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1650
swis2-VHDL20_DWEH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1842
swis2-VHDL20_DWEH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2172
swis2-VHDL20_DWEI_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1801
swis2-VHDL20_DWEI_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:02:27 1932
swis2-VHDL20_DWEI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2127
swis2-VHDL20_DWEI_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:06 1840
swis2-VHDL20_DWEI_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1459
swis2-VHDL20_DWEI_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:02:26 1402
swis2-VHDL20_DWEI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1525
swis2-VHDL20_DWEI_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 2084
swis2-VHDL20_DWHG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:45:31 2101
swis2-VHDL20_DWHG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 2098
swis2-VHDL20_DWHG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:45:27 2575
swis2-VHDL20_DWHG_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:45:03 2662
swis2-VHDL20_DWHG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:45:23 2297
swis2-VHDL20_DWHG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:23 2141
swis2-VHDL20_DWHG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:45:19 2105
swis2-VHDL20_DWHG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:45:06 2190
swis2-VHDL20_DWHH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:45:31 1608
swis2-VHDL20_DWHH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 1608
swis2-VHDL20_DWHH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:45:27 2234
swis2-VHDL20_DWHH_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:45:03 2389
swis2-VHDL20_DWHH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:45:23 2204
swis2-VHDL20_DWHH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:23 2204
swis2-VHDL20_DWHH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:45:19 2318
swis2-VHDL20_DWHH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:45:07 2238
swis2-VHDL20_DWLG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1344
swis2-VHDL20_DWLG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1203
swis2-VHDL20_DWLG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1423
swis2-VHDL20_DWLG_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:31:07 1416
swis2-VHDL20_DWLG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1227
swis2-VHDL20_DWLG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1410
swis2-VHDL20_DWLG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1506
swis2-VHDL20_DWLG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1442
swis2-VHDL20_DWLH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1321
swis2-VHDL20_DWLH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1423
swis2-VHDL20_DWLH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1645
swis2-VHDL20_DWLH_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:31:07 1422
swis2-VHDL20_DWLH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1238
swis2-VHDL20_DWLH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1401
swis2-VHDL20_DWLH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1570
swis2-VHDL20_DWLH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1373
swis2-VHDL20_DWLI_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1334
swis2-VHDL20_DWLI_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1448
swis2-VHDL20_DWLI_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1668
swis2-VHDL20_DWLI_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:31:07 1416
swis2-VHDL20_DWLI_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1227
swis2-VHDL20_DWLI_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:13 1396
swis2-VHDL20_DWLI_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1567
swis2-VHDL20_DWLI_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1353
swis2-VHDL20_DWMO_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1416
swis2-VHDL20_DWMO_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:06 1752
swis2-VHDL20_DWMO_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2062
swis2-VHDL20_DWMO_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:06 1980
swis2-VHDL20_DWMO_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:12 1673
swis2-VHDL20_DWMO_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:01 1685
swis2-VHDL20_DWMO_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 2029
swis2-VHDL20_DWMO_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1624
swis2-VHDL20_DWMP_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1464
swis2-VHDL20_DWMP_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:06 1726
swis2-VHDL20_DWMP_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 2138
swis2-VHDL20_DWMP_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:06 2356
swis2-VHDL20_DWMP_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:12 1705
swis2-VHDL20_DWMP_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:01 1716
swis2-VHDL20_DWMP_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 2093
swis2-VHDL20_DWMP_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1899
swis2-VHDL20_DWPG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1126
swis2-VHDL20_DWPG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1355
swis2-VHDL20_DWPG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1588
swis2-VHDL20_DWPG_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:31:07 1536
swis2-VHDL20_DWPG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1318
swis2-VHDL20_DWPG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1506
swis2-VHDL20_DWPG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1632
swis2-VHDL20_DWPG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1407
swis2-VHDL20_DWPH_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:22 1108
swis2-VHDL20_DWPH_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:12 1313
swis2-VHDL20_DWPH_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:21 1570
swis2-VHDL20_DWPH_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:31:07 1719
swis2-VHDL20_DWPH_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:28 1428
swis2-VHDL20_DWPH_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:11 1444
swis2-VHDL20_DWPH_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:27 1618
swis2-VHDL20_DWPH_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:31:02 1481
swis2-VHDL20_DWSG_030200-2608030200-dsw--0-ia5 03-Aug-2026 02:30:06 1450
swis2-VHDL20_DWSG_030400-2608030400-dsw--0-ia5 03-Aug-2026 05:00:22 1398
swis2-VHDL20_DWSG_030400_COR-2608030400-dsw--0-ia5 03-Aug-2026 05:13:41 1767
swis2-VHDL20_DWSG_030800-2608030800-dsw--0-ia5 03-Aug-2026 08:30:07 1955
swis2-VHDL20_DWSG_030800_COR-2608030800-dsw--0-ia5 03-Aug-2026 12:19:32 1996
swis2-VHDL20_DWSG_031800-2608031800-dsw--0-ia5 03-Aug-2026 18:30:02 1914
swis2-VHDL20_DWSG_040200-2608040200-dsw--0-ia5 04-Aug-2026 02:30:04 1503
swis2-VHDL20_DWSG_040400-2608040400-dsw--0-ia5 04-Aug-2026 05:00:21 1410
swis2-VHDL20_DWSG_040800-2608040800-dsw--0-ia5 04-Aug-2026 08:30:14 1714
swis2-VHDL20_DWSG_041800-2608041800-dsw--0-ia5 04-Aug-2026 18:30:04 1426
wst04-VHDL20_DWEG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:10 239999
wst04-VHDL20_DWEG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 240138
wst04-VHDL20_DWEG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:14 241527
wst04-VHDL20_DWEG_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:18 243416
wst04-VHDL20_DWEG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 242756
wst04-VHDL20_DWEG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 243167
wst04-VHDL20_DWEG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:14 243394
wst04-VHDL20_DWEG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 247698
wst04-VHDL20_DWEH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 238736
wst04-VHDL20_DWEH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 238792
wst04-VHDL20_DWEH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:14 240232
wst04-VHDL20_DWEH_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:18 241397
wst04-VHDL20_DWEH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 240487
wst04-VHDL20_DWEH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 240570
wst04-VHDL20_DWEH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:14 241424
wst04-VHDL20_DWEH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 240676
wst04-VHDL20_DWEI_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 346971
wst04-VHDL20_DWEI_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:22 347020
wst04-VHDL20_DWEI_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:16 347426
wst04-VHDL20_DWEI_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:18 351637
wst04-VHDL20_DWEI_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 350734
wst04-VHDL20_DWEI_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:23 350408
wst04-VHDL20_DWEI_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:18 351207
wst04-VHDL20_DWEI_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 352318
wst04-VHDL20_DWHG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:45:31 339047
wst04-VHDL20_DWHG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:12 338842
wst04-VHDL20_DWHG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:45:27 341093
wst04-VHDL20_DWHG_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:45:18 354291
wst04-VHDL20_DWHG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:45:22 353238
wst04-VHDL20_DWHG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:17 352784
wst04-VHDL20_DWHG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:45:19 353994
wst04-VHDL20_DWHG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:45:14 348453
wst04-VHDL20_DWHH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:45:31 331766
wst04-VHDL20_DWHH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:16 228783
wst04-VHDL20_DWHH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:45:27 334191
wst04-VHDL20_DWHH_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:45:18 343724
wst04-VHDL20_DWHH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:45:22 342228
wst04-VHDL20_DWHH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:23 235344
wst04-VHDL20_DWHH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:45:19 343118
wst04-VHDL20_DWHH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:45:14 342735
wst04-VHDL20_DWLG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 341232
wst04-VHDL20_DWLG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:42 341176
wst04-VHDL20_DWLG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:52 342203
wst04-VHDL20_DWLG_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:31:24 343036
wst04-VHDL20_DWLG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:32 341963
wst04-VHDL20_DWLG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:41 342126
wst04-VHDL20_DWLG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:47 342339
wst04-VHDL20_DWLG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 345752
wst04-VHDL20_DWLH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 343746
wst04-VHDL20_DWLH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:48 343835
wst04-VHDL20_DWLH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 344848
wst04-VHDL20_DWLH_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:31:31 345461
wst04-VHDL20_DWLH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 344347
wst04-VHDL20_DWLH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:47 344519
wst04-VHDL20_DWLH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:51 344806
wst04-VHDL20_DWLH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 344326
wst04-VHDL20_DWLI_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:37 337809
wst04-VHDL20_DWLI_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:42 337918
wst04-VHDL20_DWLI_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 383476
wst04-VHDL20_DWLI_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:31:31 345200
wst04-VHDL20_DWLI_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 344113
wst04-VHDL20_DWLI_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:41 344257
wst04-VHDL20_DWLI_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:47 389130
wst04-VHDL20_DWLI_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 341343
wst04-VHDL20_DWMO_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:10 460536
wst04-VHDL20_DWMO_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:12 459734
wst04-VHDL20_DWMO_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:31 460002
wst04-VHDL20_DWMO_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:24 361303
wst04-VHDL20_DWMO_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:12 472025
wst04-VHDL20_DWMO_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:11 472216
wst04-VHDL20_DWMO_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 472025
wst04-VHDL20_DWMO_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 363603
wst04-VHDL20_DWMP_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 588703
wst04-VHDL20_DWMP_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:16 588675
wst04-VHDL20_DWMP_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:31 480505
wst04-VHDL20_DWMP_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:26 487424
wst04-VHDL20_DWMP_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:19 601503
wst04-VHDL20_DWMP_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:27 601691
wst04-VHDL20_DWMP_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 487246
wst04-VHDL20_DWMP_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 496110
wst04-VHDL20_DWPG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 243397
wst04-VHDL20_DWPG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:32 347198
wst04-VHDL20_DWPG_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 392953
wst04-VHDL20_DWPG_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:31:31 352538
wst04-VHDL20_DWPG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 245464
wst04-VHDL20_DWPG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:31 351498
wst04-VHDL20_DWPG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:42 397037
wst04-VHDL20_DWPG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 345767
wst04-VHDL20_DWPH_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:29 244406
wst04-VHDL20_DWPH_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:00:32 244596
wst04-VHDL20_DWPH_030800-2608030800-omedes--0.pdf 03-Aug-2026 08:30:48 244949
wst04-VHDL20_DWPH_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:31:24 246464
wst04-VHDL20_DWPH_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:28 246055
wst04-VHDL20_DWPH_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:31 246158
wst04-VHDL20_DWPH_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:42 246310
wst04-VHDL20_DWPH_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:31:30 246422
wst04-VHDL20_DWSG_030200-2608030200-omedes--0.pdf 03-Aug-2026 02:30:22 358622
wst04-VHDL20_DWSG_030400-2608030400-omedes--0.pdf 03-Aug-2026 05:13:47 358454
wst04-VHDL20_DWSG_030800-2608030800-omedes--0.pdf 03-Aug-2026 12:19:40 367518
wst04-VHDL20_DWSG_031800-2608031800-omedes--0.pdf 03-Aug-2026 18:30:24 367826
wst04-VHDL20_DWSG_040200-2608040200-omedes--0.pdf 04-Aug-2026 02:30:12 365748
wst04-VHDL20_DWSG_040400-2608040400-omedes--0.pdf 04-Aug-2026 05:00:13 365897
wst04-VHDL20_DWSG_040800-2608040800-omedes--0.pdf 04-Aug-2026 08:30:27 367889
wst04-VHDL20_DWSG_041800-2608041800-omedes--0.pdf 04-Aug-2026 18:30:19 361535