Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_150600 15-Mar-2026 14:54:19 9442
FPDL13_DWMZ_160600 16-Mar-2026 13:54:05 4822
SXDL31_DWAV_150800 15-Mar-2026 08:06:49 6881
SXDL31_DWAV_151800 15-Mar-2026 17:55:10 7760
SXDL31_DWAV_160800 16-Mar-2026 07:53:10 12828
SXDL31_DWAV_161800 16-Mar-2026 18:09:13 4144
SXDL31_DWAV_170800 17-Mar-2026 07:56:09 9565
SXDL31_DWAV_LATEST 17-Mar-2026 07:56:09 9565
SXDL33_DWAV_150000 15-Mar-2026 11:03:29 16330
SXDL33_DWAV_160000 16-Mar-2026 11:18:13 7347
SXDL33_DWAV_LATEST 16-Mar-2026 11:18:13 7347
ber01-FWDL39_DWMS_151230-2603151230-dsw--0-ia5 15-Mar-2026 12:30:49 1360
ber01-FWDL39_DWMS_161230-2603161230-dsw--0-ia5 16-Mar-2026 12:06:31 2031
ber01-VHDL13_DWEH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:17 3075
ber01-VHDL13_DWEH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:16 2782
ber01-VHDL13_DWEH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2623
ber01-VHDL13_DWEH_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:11 2734
ber01-VHDL13_DWEH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:17 2744
ber01-VHDL13_DWEH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:16 2296
ber01-VHDL13_DWEH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:11 2617
ber01-VHDL13_DWEH_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2642
ber01-VHDL13_DWHG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:10 4629
ber01-VHDL13_DWHG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:01:17 3882
ber01-VHDL13_DWHG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 3363
ber01-VHDL13_DWHG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3706
ber01-VHDL13_DWHG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3767
ber01-VHDL13_DWHG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 4022
ber01-VHDL13_DWHG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3334
ber01-VHDL13_DWHG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:09 3376
ber01-VHDL13_DWHG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3408
ber01-VHDL13_DWHH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:10 3716
ber01-VHDL13_DWHH_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:01:41 3269
ber01-VHDL13_DWHH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2696
ber01-VHDL13_DWHH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 2965
ber01-VHDL13_DWHH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 2976
ber01-VHDL13_DWHH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 3312
ber01-VHDL13_DWHH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3087
ber01-VHDL13_DWHH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:09 3069
ber01-VHDL13_DWHH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3062
ber01-VHDL13_DWLG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3131
ber01-VHDL13_DWLG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2828
ber01-VHDL13_DWLG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2975
ber01-VHDL13_DWLG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3002
ber01-VHDL13_DWLG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3127
ber01-VHDL13_DWLG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2067
ber01-VHDL13_DWLG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2153
ber01-VHDL13_DWLG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2252
ber01-VHDL13_DWLH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3221
ber01-VHDL13_DWLH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2947
ber01-VHDL13_DWLH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 3190
ber01-VHDL13_DWLH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3315
ber01-VHDL13_DWLH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3495
ber01-VHDL13_DWLH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2183
ber01-VHDL13_DWLH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2303
ber01-VHDL13_DWLH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2458
ber01-VHDL13_DWLI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2921
ber01-VHDL13_DWLI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2587
ber01-VHDL13_DWLI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2792
ber01-VHDL13_DWLI_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3125
ber01-VHDL13_DWLI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3381
ber01-VHDL13_DWLI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2261
ber01-VHDL13_DWLI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2425
ber01-VHDL13_DWLI_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2453
ber01-VHDL13_DWMG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2827
ber01-VHDL13_DWMG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2955
ber01-VHDL13_DWMG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3072
ber01-VHDL13_DWMG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 3086
ber01-VHDL13_DWMG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3696
ber01-VHDL13_DWMG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2477
ber01-VHDL13_DWMG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2854
ber01-VHDL13_DWMG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2862
ber01-VHDL13_DWMO_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2890
ber01-VHDL13_DWMO_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2912
ber01-VHDL13_DWMO_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 2924
ber01-VHDL13_DWMO_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 2944
ber01-VHDL13_DWMO_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3195
ber01-VHDL13_DWMO_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2197
ber01-VHDL13_DWMO_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2491
ber01-VHDL13_DWMO_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2530
ber01-VHDL13_DWMP_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2717
ber01-VHDL13_DWMP_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:08 2668
ber01-VHDL13_DWMP_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3027
ber01-VHDL13_DWMP_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:02 2938
ber01-VHDL13_DWMP_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3520
ber01-VHDL13_DWMP_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2357
ber01-VHDL13_DWMP_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2981
ber01-VHDL13_DWMP_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 2977
ber01-VHDL13_DWOG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3945
ber01-VHDL13_DWOG_151700-2603151700-dsw--0-ia5 15-Mar-2026 19:00:01 3605
ber01-VHDL13_DWOG_151700_COR-2603151700-dsw--0-ia5 15-Mar-2026 22:02:28 4216
ber01-VHDL13_DWOG_160300-2603160300-dsw--0-ia5 16-Mar-2026 04:00:02 4723
ber01-VHDL13_DWOG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 4063
ber01-VHDL13_DWOG_161700-2603161700-dsw--0-ia5 16-Mar-2026 19:00:01 3700
ber01-VHDL13_DWOG_161700_COR-2603161700-dsw--0-ia5 16-Mar-2026 19:59:51 4688
ber01-VHDL13_DWOG_170300-2603170300-dsw--0-ia5 17-Mar-2026 04:00:01 5214
ber01-VHDL13_DWOG_170300_COR-2603170300-dsw--0-ia5 17-Mar-2026 04:53:21 4743
ber01-VHDL13_DWOH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:17 3025
ber01-VHDL13_DWOH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:16 2807
ber01-VHDL13_DWOH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2713
ber01-VHDL13_DWOH_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:17 2668
ber01-VHDL13_DWOH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:17 2709
ber01-VHDL13_DWOH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:16 2426
ber01-VHDL13_DWOH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:11 2552
ber01-VHDL13_DWOH_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2593
ber01-VHDL13_DWOI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:28:11 3073
ber01-VHDL13_DWOI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:28:12 2861
ber01-VHDL13_DWOI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:28:12 2693
ber01-VHDL13_DWOI_160400-2603160400-dsw--0-ia5 16-Mar-2026 05:58:17 2644
ber01-VHDL13_DWOI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:28:11 2546
ber01-VHDL13_DWOI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:28:10 2186
ber01-VHDL13_DWOI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:28:17 2509
ber01-VHDL13_DWOI_170400-2603170400-dsw--0-ia5 17-Mar-2026 05:58:17 2599
ber01-VHDL13_DWON_150927-2603150927-dsw--0-ia5 15-Mar-2026 09:28:01 3741
ber01-VHDL13_DWON_150958-2603150958-dsw--0-ia5 15-Mar-2026 09:58:57 3741
ber01-VHDL13_DWON_151557-2603151557-dsw--0-ia5 15-Mar-2026 15:57:08 3818
ber01-VHDL13_DWON_151828-2603151828-dsw--0-ia5 15-Mar-2026 18:28:38 3164
ber01-VHDL13_DWON_152202-2603152202-dsw--0-ia5 15-Mar-2026 22:02:07 4027
ber01-VHDL13_DWON_160303-2603160303-dsw--0-ia5 16-Mar-2026 03:03:16 4465
ber01-VHDL13_DWON_160627-2603160627-dsw--0-ia5 16-Mar-2026 06:27:37 3623
ber01-VHDL13_DWON_160730-2603160730-dsw--0-ia5 16-Mar-2026 07:30:11 4008
ber01-VHDL13_DWON_161526-2603161526-dsw--0-ia5 16-Mar-2026 15:26:21 3390
ber01-VHDL13_DWON_161806-2603161806-dsw--0-ia5 16-Mar-2026 18:06:17 3414
ber01-VHDL13_DWON_161959-2603161959-dsw--0-ia5 16-Mar-2026 19:59:21 3743
ber01-VHDL13_DWON_170453-2603170453-dsw--0-ia5 17-Mar-2026 04:53:11 4136
ber01-VHDL13_DWON_170623-2603170623-dsw--0-ia5 17-Mar-2026 06:23:17 4332
ber01-VHDL13_DWON_170708-2603170708-dsw--0-ia5 17-Mar-2026 07:08:37 4034
ber01-VHDL13_DWPG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2398
ber01-VHDL13_DWPG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2117
ber01-VHDL13_DWPG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2618
ber01-VHDL13_DWPG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 2646
ber01-VHDL13_DWPG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 2919
ber01-VHDL13_DWPG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2111
ber01-VHDL13_DWPG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2402
ber01-VHDL13_DWPG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2238
ber01-VHDL13_DWPH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 2407
ber01-VHDL13_DWPH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 2149
ber01-VHDL13_DWPH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:00 2712
ber01-VHDL13_DWPH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 2674
ber01-VHDL13_DWPH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:01 3082
ber01-VHDL13_DWPH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 2100
ber01-VHDL13_DWPH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 2249
ber01-VHDL13_DWPH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:01 2388
ber01-VHDL13_DWSG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:30:04 3237
ber01-VHDL13_DWSG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 13:56:35 3641
ber01-VHDL13_DWSG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:30:03 3371
ber01-VHDL13_DWSG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:30:06 3502
ber01-VHDL13_DWSG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:06 3530
ber01-VHDL13_DWSG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:30:07 3687
ber01-VHDL13_DWSG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:30:06 3031
ber01-VHDL13_DWSG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:30:03 3105
ber01-VHDL13_DWSG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:06 3025
ber01-VHDL17_DWOG_151200-2603151200-dsw--0-ia5 15-Mar-2026 13:11:17 3039
ber01-VHDL17_DWOG_161200-2603161200-dsw--0-ia5 16-Mar-2026 12:59:11 2568
swis2-VHDL20_DWEG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3670
swis2-VHDL20_DWEG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3247
swis2-VHDL20_DWEG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3103
swis2-VHDL20_DWEG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3044
swis2-VHDL20_DWEG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3365
swis2-VHDL20_DWEG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2976
swis2-VHDL20_DWEG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3026
swis2-VHDL20_DWEG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2937
swis2-VHDL20_DWEH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3699
swis2-VHDL20_DWEH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3257
swis2-VHDL20_DWEH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3066
swis2-VHDL20_DWEH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 3071
swis2-VHDL20_DWEH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3326
swis2-VHDL20_DWEH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2826
swis2-VHDL20_DWEH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 3056
swis2-VHDL20_DWEH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2981
swis2-VHDL20_DWEI_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3700
swis2-VHDL20_DWEI_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3316
swis2-VHDL20_DWEI_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3090
swis2-VHDL20_DWEI_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:15:02 2996
swis2-VHDL20_DWEI_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3073
swis2-VHDL20_DWEI_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:06 2538
swis2-VHDL20_DWEI_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:07 2801
swis2-VHDL20_DWEI_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:15:05 2954
swis2-VHDL20_DWHG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:06 5560
swis2-VHDL20_DWHG_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:02:07 4813
swis2-VHDL20_DWHG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3546
swis2-VHDL20_DWHG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3892
swis2-VHDL20_DWHG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3950
swis2-VHDL20_DWHG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 4827
swis2-VHDL20_DWHG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3517
swis2-VHDL20_DWHG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 3562
swis2-VHDL20_DWHG_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 3591
swis2-VHDL20_DWHH_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:06 4258
swis2-VHDL20_DWHH_150800_COR-2603150800-dsw--0-ia5 15-Mar-2026 12:02:37 3811
swis2-VHDL20_DWHH_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 2882
swis2-VHDL20_DWHH_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:01 3151
swis2-VHDL20_DWHH_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3162
swis2-VHDL20_DWHH_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:06 3855
swis2-VHDL20_DWHH_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 3272
swis2-VHDL20_DWHH_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 3255
swis2-VHDL20_DWHH_170400-2603170400-dsw--0-ia5 17-Mar-2026 06:00:12 3248
swis2-VHDL20_DWLG_150800-2603150800-dsw--0-ia5 15-Mar-2026 09:45:04 3741
swis2-VHDL20_DWLG_151800-2603151800-dsw--0-ia5 15-Mar-2026 19:45:02 3213
swis2-VHDL20_DWLG_160200-2603160200-dsw--0-ia5 16-Mar-2026 03:45:07 3360
swis2-VHDL20_DWLG_160400-2603160400-dsw--0-ia5 16-Mar-2026 06:00:12 3520
swis2-VHDL20_DWLG_160800-2603160800-dsw--0-ia5 16-Mar-2026 09:45:02 3812
swis2-VHDL20_DWLG_161800-2603161800-dsw--0-ia5 16-Mar-2026 19:45:02 2585
swis2-VHDL20_DWLG_170200-2603170200-dsw--0-ia5 17-Mar-2026 03:45:01 2671
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wst04-VHDL20_DWSG_150800_COR-2603150800-omedes-..> 15-Mar-2026 13:56:41 352957
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