Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_280600 28-Mar-2026 15:06:35 4565
FPDL13_DWMZ_290600 29-Mar-2026 13:50:44 4837
FPDL13_DWMZ_300600 30-Mar-2026 12:49:45 3548
SXDL31_DWAV_281800 28-Mar-2026 16:05:10 7088
SXDL31_DWAV_290800 29-Mar-2026 08:48:58 14380
SXDL31_DWAV_291800 29-Mar-2026 17:13:29 8971
SXDL31_DWAV_300800 30-Mar-2026 07:07:23 9686
SXDL31_DWAV_LATEST 30-Mar-2026 07:07:23 9686
SXDL33_DWAV_300000 30-Mar-2026 11:00:34 11693
SXDL33_DWAV_LATEST 30-Mar-2026 11:00:34 11693
ber01-FWDL39_DWMS_291230-2603291230-dsw--0-ia5 29-Mar-2026 11:36:17 1426
ber01-FWDL39_DWMS_301230-2603301230-dsw--0-ia5 30-Mar-2026 11:04:27 1180
ber01-VHDL13_DWEH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:17 3172
ber01-VHDL13_DWEH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3280
ber01-VHDL13_DWEH_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:11 3149
ber01-VHDL13_DWEH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:11 3224
ber01-VHDL13_DWEH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:28:16 3424
ber01-VHDL13_DWEH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:28:11 3175
ber01-VHDL13_DWEH_300400-2603300400-dsw--0-ia5 30-Mar-2026 04:58:12 3370
ber01-VHDL13_DWEH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:28:17 3619
ber01-VHDL13_DWHG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3888
ber01-VHDL13_DWHG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:07 3680
ber01-VHDL13_DWHG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3707
ber01-VHDL13_DWHG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3838
ber01-VHDL13_DWHG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:07 3598
ber01-VHDL13_DWHG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 3357
ber01-VHDL13_DWHG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3357
ber01-VHDL13_DWHG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:09 3354
ber01-VHDL13_DWHH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3573
ber01-VHDL13_DWHH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:07 3328
ber01-VHDL13_DWHH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3353
ber01-VHDL13_DWHH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3512
ber01-VHDL13_DWHH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:07 2997
ber01-VHDL13_DWHH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 2792
ber01-VHDL13_DWHH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 2792
ber01-VHDL13_DWHH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:09 2744
ber01-VHDL13_DWLG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3588
ber01-VHDL13_DWLG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3491
ber01-VHDL13_DWLG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3423
ber01-VHDL13_DWLG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3274
ber01-VHDL13_DWLG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:01 2948
ber01-VHDL13_DWLG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 3055
ber01-VHDL13_DWLG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:06 3138
ber01-VHDL13_DWLG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 3480
ber01-VHDL13_DWLH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3048
ber01-VHDL13_DWLH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3104
ber01-VHDL13_DWLH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3248
ber01-VHDL13_DWLH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3068
ber01-VHDL13_DWLH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:01 2933
ber01-VHDL13_DWLH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 2903
ber01-VHDL13_DWLH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:06 2921
ber01-VHDL13_DWLH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 3136
ber01-VHDL13_DWLI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3125
ber01-VHDL13_DWLI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3175
ber01-VHDL13_DWLI_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3137
ber01-VHDL13_DWLI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2955
ber01-VHDL13_DWLI_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:01 2850
ber01-VHDL13_DWLI_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 2879
ber01-VHDL13_DWLI_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:06 2874
ber01-VHDL13_DWLI_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 3142
ber01-VHDL13_DWMG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3243
ber01-VHDL13_DWMG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3483
ber01-VHDL13_DWMG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3273
ber01-VHDL13_DWMG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3767
ber01-VHDL13_DWMG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:05 3915
ber01-VHDL13_DWMG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:05 3911
ber01-VHDL13_DWMG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:02 3741
ber01-VHDL13_DWMG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:09 3937
ber01-VHDL13_DWMO_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2965
ber01-VHDL13_DWMO_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3279
ber01-VHDL13_DWMO_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3240
ber01-VHDL13_DWMO_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3548
ber01-VHDL13_DWMO_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:05 3507
ber01-VHDL13_DWMO_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:05 3637
ber01-VHDL13_DWMO_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:02 3457
ber01-VHDL13_DWMO_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:09 3463
ber01-VHDL13_DWMP_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3257
ber01-VHDL13_DWMP_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3392
ber01-VHDL13_DWMP_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 3143
ber01-VHDL13_DWMP_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3728
ber01-VHDL13_DWMP_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:05 3832
ber01-VHDL13_DWMP_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:05 4065
ber01-VHDL13_DWMP_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:02 3925
ber01-VHDL13_DWMP_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:09 4099
ber01-VHDL13_DWOG_281700-2603281700-dsw--0-ia5 28-Mar-2026 19:00:02 4150
ber01-VHDL13_DWOG_290300-2603290300-dsw--0-ia5 29-Mar-2026 03:00:06 4936
ber01-VHDL13_DWOG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 5155
ber01-VHDL13_DWOG_291700-2603291700-dsw--0-ia5 29-Mar-2026 18:00:02 4789
ber01-VHDL13_DWOG_300300-2603300300-dsw--0-ia5 30-Mar-2026 03:00:06 5506
ber01-VHDL13_DWOG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 5207
ber01-VHDL13_DWOH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:11 3278
ber01-VHDL13_DWOH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3220
ber01-VHDL13_DWOH_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:11 3087
ber01-VHDL13_DWOH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:17 3222
ber01-VHDL13_DWOH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:28:16 3403
ber01-VHDL13_DWOH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:28:11 3169
ber01-VHDL13_DWOH_300400-2603300400-dsw--0-ia5 30-Mar-2026 04:58:16 3376
ber01-VHDL13_DWOH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:28:17 3472
ber01-VHDL13_DWOI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:28:17 3256
ber01-VHDL13_DWOI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:28:11 3186
ber01-VHDL13_DWOI_290400-2603290400-dsw--0-ia5 29-Mar-2026 04:58:17 3065
ber01-VHDL13_DWOI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:28:17 3230
ber01-VHDL13_DWOI_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:28:12 3409
ber01-VHDL13_DWOI_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:28:17 3182
ber01-VHDL13_DWOI_300400-2603300400-dsw--0-ia5 30-Mar-2026 04:58:16 3351
ber01-VHDL13_DWOI_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:28:17 3492
ber01-VHDL13_DWON_281616-2603281616-dsw--0-ia5 28-Mar-2026 16:17:01 3064
ber01-VHDL13_DWON_281748-2603281748-dsw--0-ia5 28-Mar-2026 17:48:36 3114
ber01-VHDL13_DWON_282228-2603282228-dsw--0-ia5 28-Mar-2026 22:28:31 3111
ber01-VHDL13_DWON_290139-2603290139-dsw--0-ia5 29-Mar-2026 01:39:51 3310
ber01-VHDL13_DWON_290144-2603290144-dsw--0-ia5 29-Mar-2026 01:44:57 3306
ber01-VHDL13_DWON_290353-2603290353-dsw--0-ia5 29-Mar-2026 03:53:11 3306
ber01-VHDL13_DWON_290519-2603290519-dsw--0-ia5 29-Mar-2026 05:19:30 3748
ber01-VHDL13_DWON_290620-2603290620-dsw--0-ia5 29-Mar-2026 06:20:57 3748
ber01-VHDL13_DWON_290827-2603290827-dsw--0-ia5 29-Mar-2026 08:27:57 3748
ber01-VHDL13_DWON_290840-2603290840-dsw--0-ia5 29-Mar-2026 08:40:37 3748
ber01-VHDL13_DWON_291439-2603291439-dsw--0-ia5 29-Mar-2026 14:39:36 3179
ber01-VHDL13_DWON_291717-2603291717-dsw--0-ia5 29-Mar-2026 17:17:46 3157
ber01-VHDL13_DWON_291725-2603291725-dsw--0-ia5 29-Mar-2026 17:25:57 3157
ber01-VHDL13_DWON_291736-2603291736-dsw--0-ia5 29-Mar-2026 17:36:57 3157
ber01-VHDL13_DWON_291915-2603291915-dsw--0-ia5 29-Mar-2026 19:15:07 3805
ber01-VHDL13_DWON_292131-2603292131-dsw--0-ia5 29-Mar-2026 21:31:33 3803
ber01-VHDL13_DWON_300006-2603300006-dsw--0-ia5 30-Mar-2026 00:06:17 4191
ber01-VHDL13_DWON_300141-2603300141-dsw--0-ia5 30-Mar-2026 01:41:37 4000
ber01-VHDL13_DWON_300142-2603300142-dsw--0-ia5 30-Mar-2026 01:42:36 4000
ber01-VHDL13_DWON_300245-2603300245-dsw--0-ia5 30-Mar-2026 02:45:41 4000
ber01-VHDL13_DWON_300527-2603300527-dsw--0-ia5 30-Mar-2026 05:27:11 3749
ber01-VHDL13_DWON_300608-2603300608-dsw--0-ia5 30-Mar-2026 06:08:11 3794
ber01-VHDL13_DWON_300901-2603300901-dsw--0-ia5 30-Mar-2026 09:01:37 3794
ber01-VHDL13_DWPG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2608
ber01-VHDL13_DWPG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 2726
ber01-VHDL13_DWPG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 2912
ber01-VHDL13_DWPG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2670
ber01-VHDL13_DWPG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:01 2466
ber01-VHDL13_DWPG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 2198
ber01-VHDL13_DWPG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:06 2166
ber01-VHDL13_DWPG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 2350
ber01-VHDL13_DWPH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 2814
ber01-VHDL13_DWPH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 2670
ber01-VHDL13_DWPH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:01 2696
ber01-VHDL13_DWPH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 2533
ber01-VHDL13_DWPH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:01 2458
ber01-VHDL13_DWPH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 2411
ber01-VHDL13_DWPH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:06 2478
ber01-VHDL13_DWPH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 2550
ber01-VHDL13_DWSG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:30:06 3279
ber01-VHDL13_DWSG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:30:02 3155
ber01-VHDL13_DWSG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3306
ber01-VHDL13_DWSG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:30:10 3600
ber01-VHDL13_DWSG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:30:05 3216
ber01-VHDL13_DWSG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:30:09 3331
ber01-VHDL13_DWSG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3748
ber01-VHDL13_DWSG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:30:02 3709
ber01-VHDL17_DWOG_291200-2603291200-dsw--0-ia5 29-Mar-2026 11:54:27 2900
ber01-VHDL17_DWOG_301200-2603301200-dsw--0-ia5 30-Mar-2026 11:53:27 3220
swis2-VHDL20_DWEG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3764
swis2-VHDL20_DWEG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3659
swis2-VHDL20_DWEG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3521
swis2-VHDL20_DWEG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3932
swis2-VHDL20_DWEG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3843
swis2-VHDL20_DWEG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3569
swis2-VHDL20_DWEG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 3756
swis2-VHDL20_DWEG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4080
swis2-VHDL20_DWEH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3711
swis2-VHDL20_DWEH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3817
swis2-VHDL20_DWEH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3595
swis2-VHDL20_DWEH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3956
swis2-VHDL20_DWEH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3898
swis2-VHDL20_DWEH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3620
swis2-VHDL20_DWEH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 3762
swis2-VHDL20_DWEH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4252
swis2-VHDL20_DWEI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3767
swis2-VHDL20_DWEI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3641
swis2-VHDL20_DWEI_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:08 3530
swis2-VHDL20_DWEI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:07 3987
swis2-VHDL20_DWEI_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3881
swis2-VHDL20_DWEI_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3599
swis2-VHDL20_DWEI_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 3762
swis2-VHDL20_DWEI_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4147
swis2-VHDL20_DWHG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 4071
swis2-VHDL20_DWHG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:06 3866
swis2-VHDL20_DWHG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3890
swis2-VHDL20_DWHG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4506
swis2-VHDL20_DWHG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3781
swis2-VHDL20_DWHG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3543
swis2-VHDL20_DWHG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3540
swis2-VHDL20_DWHG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4006
swis2-VHDL20_DWHH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3759
swis2-VHDL20_DWHH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:06 3514
swis2-VHDL20_DWHH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:17 3539
swis2-VHDL20_DWHH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4054
swis2-VHDL20_DWHH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3183
swis2-VHDL20_DWHH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 2978
swis2-VHDL20_DWHH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 2978
swis2-VHDL20_DWHH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 3317
swis2-VHDL20_DWLG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 4019
swis2-VHDL20_DWLG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3922
swis2-VHDL20_DWLG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3821
swis2-VHDL20_DWLG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3938
swis2-VHDL20_DWLG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 3361
swis2-VHDL20_DWLG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3468
swis2-VHDL20_DWLG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3562
swis2-VHDL20_DWLG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4131
swis2-VHDL20_DWLH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3482
swis2-VHDL20_DWLH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3492
swis2-VHDL20_DWLH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3648
swis2-VHDL20_DWLH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3723
swis2-VHDL20_DWLH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 3333
swis2-VHDL20_DWLH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3303
swis2-VHDL20_DWLH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3352
swis2-VHDL20_DWLH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 3791
swis2-VHDL20_DWLI_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3558
swis2-VHDL20_DWLI_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3608
swis2-VHDL20_DWLI_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3559
swis2-VHDL20_DWLI_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3626
swis2-VHDL20_DWLI_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 3272
swis2-VHDL20_DWLI_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 3301
swis2-VHDL20_DWLI_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 3298
swis2-VHDL20_DWLI_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 3802
swis2-VHDL20_DWMG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3696
swis2-VHDL20_DWMG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3943
swis2-VHDL20_DWMG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:05 3784
swis2-VHDL20_DWMG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4564
swis2-VHDL20_DWMG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 4419
swis2-VHDL20_DWMG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 4450
swis2-VHDL20_DWMG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 4230
swis2-VHDL20_DWMG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4693
swis2-VHDL20_DWMO_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3419
swis2-VHDL20_DWMO_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3736
swis2-VHDL20_DWMO_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:05 3757
swis2-VHDL20_DWMO_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4348
swis2-VHDL20_DWMO_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 3972
swis2-VHDL20_DWMO_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 4104
swis2-VHDL20_DWMO_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 3946
swis2-VHDL20_DWMO_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4240
swis2-VHDL20_DWMP_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3646
swis2-VHDL20_DWMP_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3808
swis2-VHDL20_DWMP_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:05 3570
swis2-VHDL20_DWMP_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4439
swis2-VHDL20_DWMP_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:06 4254
swis2-VHDL20_DWMP_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 4513
swis2-VHDL20_DWMP_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 4417
swis2-VHDL20_DWMP_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4864
swis2-VHDL20_DWPG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3168
swis2-VHDL20_DWPG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3129
swis2-VHDL20_DWPG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3237
swis2-VHDL20_DWPG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3184
swis2-VHDL20_DWPG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 2980
swis2-VHDL20_DWPG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 2529
swis2-VHDL20_DWPG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 2548
swis2-VHDL20_DWPG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 2946
swis2-VHDL20_DWPH_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:04 3329
swis2-VHDL20_DWPH_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3055
swis2-VHDL20_DWPH_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:00:11 3023
swis2-VHDL20_DWPH_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 3047
swis2-VHDL20_DWPH_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 2972
swis2-VHDL20_DWPH_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 2741
swis2-VHDL20_DWPH_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:00:16 2862
swis2-VHDL20_DWPH_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 3167
swis2-VHDL20_DWSG_281300-2603281300-dsw--0-ia5 28-Mar-2026 14:45:02 3719
swis2-VHDL20_DWSG_281800-2603281800-dsw--0-ia5 28-Mar-2026 19:45:00 3872
swis2-VHDL20_DWSG_290200-2603290200-dsw--0-ia5 29-Mar-2026 02:45:03 3764
swis2-VHDL20_DWSG_290400-2603290400-dsw--0-ia5 29-Mar-2026 05:15:05 3814
swis2-VHDL20_DWSG_290800-2603290800-dsw--0-ia5 29-Mar-2026 08:45:03 4335
swis2-VHDL20_DWSG_291300-2603291300-dsw--0-ia5 29-Mar-2026 13:45:02 4144
swis2-VHDL20_DWSG_291800-2603291800-dsw--0-ia5 29-Mar-2026 18:45:01 3731
swis2-VHDL20_DWSG_300200-2603300200-dsw--0-ia5 30-Mar-2026 02:45:08 4108
swis2-VHDL20_DWSG_300400-2603300400-dsw--0-ia5 30-Mar-2026 05:15:05 4268
swis2-VHDL20_DWSG_300800-2603300800-dsw--0-ia5 30-Mar-2026 08:45:06 4448
swis2-VHDL20_DWSG_301300-2603301300-dsw--0-ia5 30-Mar-2026 13:45:03 4238
wst04-VHDL20_DWEG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:12 242647
wst04-VHDL20_DWEG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:10 243578
wst04-VHDL20_DWEG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:17 243087
wst04-VHDL20_DWEG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:16 244359
wst04-VHDL20_DWEG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:12 243331
wst04-VHDL20_DWEG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:12 242948
wst04-VHDL20_DWEG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:11 243012
wst04-VHDL20_DWEG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:13 244164
wst04-VHDL20_DWEH_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:12 244262
wst04-VHDL20_DWEH_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:10 244851
wst04-VHDL20_DWEH_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:17 244421
wst04-VHDL20_DWEH_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:16 245185
wst04-VHDL20_DWEH_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:16 240304
wst04-VHDL20_DWEH_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:12 239886
wst04-VHDL20_DWEH_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:11 239862
wst04-VHDL20_DWEH_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:13 240746
wst04-VHDL20_DWEI_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:12 345624
wst04-VHDL20_DWEI_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:16 346104
wst04-VHDL20_DWEI_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:23 346067
wst04-VHDL20_DWEI_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 346888
wst04-VHDL20_DWEI_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:16 340154
wst04-VHDL20_DWEI_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:16 339596
wst04-VHDL20_DWEI_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:17 339941
wst04-VHDL20_DWEI_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:13 340879
wst04-VHDL20_DWHG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:22 343983
wst04-VHDL20_DWHG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:22 343700
wst04-VHDL20_DWHG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:11 343724
wst04-VHDL20_DWHG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 345625
wst04-VHDL20_DWHG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:16 334991
wst04-VHDL20_DWHG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:21 334645
wst04-VHDL20_DWHG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:12 334708
wst04-VHDL20_DWHG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:27 336640
wst04-VHDL20_DWHH_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:22 328800
wst04-VHDL20_DWHH_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:22 328261
wst04-VHDL20_DWHH_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:11 328252
wst04-VHDL20_DWHH_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 329398
wst04-VHDL20_DWHH_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:22 328555
wst04-VHDL20_DWHH_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:21 328288
wst04-VHDL20_DWHH_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:12 328395
wst04-VHDL20_DWHH_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:27 329398
wst04-VHDL20_DWLG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:22 329930
wst04-VHDL20_DWLG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:29 330159
wst04-VHDL20_DWLG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:41 329183
wst04-VHDL20_DWLG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:32 329583
wst04-VHDL20_DWLG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:22 328901
wst04-VHDL20_DWLG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:32 329235
wst04-VHDL20_DWLG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:40 329106
wst04-VHDL20_DWLG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:31 329553
wst04-VHDL20_DWLH_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:22 335700
wst04-VHDL20_DWLH_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:29 336835
wst04-VHDL20_DWLH_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:41 336128
wst04-VHDL20_DWLH_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:32 336441
wst04-VHDL20_DWLH_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:22 333069
wst04-VHDL20_DWLH_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:32 333255
wst04-VHDL20_DWLH_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:40 332916
wst04-VHDL20_DWLH_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:31 333549
wst04-VHDL20_DWLI_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:26 332466
wst04-VHDL20_DWLI_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:29 333112
wst04-VHDL20_DWLI_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:41 332735
wst04-VHDL20_DWLI_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 332916
wst04-VHDL20_DWLI_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:22 323919
wst04-VHDL20_DWLI_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:21 323666
wst04-VHDL20_DWLI_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:40 323341
wst04-VHDL20_DWLI_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:31 324014
wst04-VHDL20_DWMG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:16 537440
wst04-VHDL20_DWMG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:16 537989
wst04-VHDL20_DWMG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:17 537477
wst04-VHDL20_DWMG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 539438
wst04-VHDL20_DWMG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:12 536208
wst04-VHDL20_DWMG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:16 537653
wst04-VHDL20_DWMG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:17 536765
wst04-VHDL20_DWMG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:21 538191
wst04-VHDL20_DWMO_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:16 436602
wst04-VHDL20_DWMO_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:16 437073
wst04-VHDL20_DWMO_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:12 437322
wst04-VHDL20_DWMO_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 437875
wst04-VHDL20_DWMO_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:12 437319
wst04-VHDL20_DWMO_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:12 437680
wst04-VHDL20_DWMO_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:17 438087
wst04-VHDL20_DWMO_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:21 438084
wst04-VHDL20_DWMP_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:16 542022
wst04-VHDL20_DWMP_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:16 541079
wst04-VHDL20_DWMP_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:17 541985
wst04-VHDL20_DWMP_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 543544
wst04-VHDL20_DWMP_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:16 543000
wst04-VHDL20_DWMP_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:16 542306
wst04-VHDL20_DWMP_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:17 544357
wst04-VHDL20_DWMP_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:17 545134
wst04-VHDL20_DWPG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:26 348132
wst04-VHDL20_DWPG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:22 347553
wst04-VHDL20_DWPG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:31 348080
wst04-VHDL20_DWPG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:32 392793
wst04-VHDL20_DWPG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:26 337083
wst04-VHDL20_DWPG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:32 335954
wst04-VHDL20_DWPG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:30 335786
wst04-VHDL20_DWPG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:37 380928
wst04-VHDL20_DWPH_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:22 288516
wst04-VHDL20_DWPH_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:22 242830
wst04-VHDL20_DWPH_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:00:31 243033
wst04-VHDL20_DWPH_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:26 287981
wst04-VHDL20_DWPH_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:22 283419
wst04-VHDL20_DWPH_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:21 238247
wst04-VHDL20_DWPH_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:00:30 238029
wst04-VHDL20_DWPH_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:27 282957
wst04-VHDL20_DWSG_281300-2603281300-omedes--0.pdf 28-Mar-2026 14:45:12 342889
wst04-VHDL20_DWSG_281800-2603281800-omedes--0.pdf 28-Mar-2026 19:45:12 343233
wst04-VHDL20_DWSG_290200-2603290200-omedes--0.pdf 29-Mar-2026 02:45:12 343751
wst04-VHDL20_DWSG_290400-2603290400-omedes--0.pdf 29-Mar-2026 05:15:12 343745
wst04-VHDL20_DWSG_290800-2603290800-omedes--0.pdf 29-Mar-2026 08:45:11 343873
wst04-VHDL20_DWSG_291300-2603291300-omedes--0.pdf 29-Mar-2026 13:45:12 344407
wst04-VHDL20_DWSG_291800-2603291800-omedes--0.pdf 29-Mar-2026 18:45:12 342654
wst04-VHDL20_DWSG_300200-2603300200-omedes--0.pdf 30-Mar-2026 02:45:16 343946
wst04-VHDL20_DWSG_300400-2603300400-omedes--0.pdf 30-Mar-2026 05:15:13 343958
wst04-VHDL20_DWSG_300800-2603300800-omedes--0.pdf 30-Mar-2026 08:45:17 343833
wst04-VHDL20_DWSG_301300-2603301300-omedes--0.pdf 30-Mar-2026 13:45:11 346109