Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_250600                                 25-Dec-2025 12:14:03                3078
FPDL13_DWMZ_260600                                 26-Dec-2025 13:22:59                1807
SXDL31_DWAV_250800                                 25-Dec-2025 09:24:50                7494
SXDL31_DWAV_251800                                 25-Dec-2025 17:38:58                5434
SXDL31_DWAV_260800                                 26-Dec-2025 08:33:04                9993
SXDL31_DWAV_261800                                 26-Dec-2025 17:26:23                5318
SXDL31_DWAV_LATEST                                 26-Dec-2025 17:26:23                5318
SXDL33_DWAV_250000                                 25-Dec-2025 11:19:19               16571
SXDL33_DWAV_260000                                 26-Dec-2025 10:55:44                5445
SXDL33_DWAV_LATEST                                 26-Dec-2025 10:55:44                5445
ber01-FWDL39_DWMS_251230-2512251230-dsw--0-ia5     25-Dec-2025 12:30:36                1218
ber01-FWDL39_DWMS_261230-2512261230-dsw--0-ia5     26-Dec-2025 12:05:46                1069
ber01-VHDL13_DWEH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:28:17                2955
ber01-VHDL13_DWEH_250800_COR-2512250800-dsw--0-ia5 25-Dec-2025 14:19:27                3071
ber01-VHDL13_DWEH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:28:16                2583
ber01-VHDL13_DWEH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:28:16                3351
ber01-VHDL13_DWEH_260400-2512260400-dsw--0-ia5     26-Dec-2025 05:58:11                3309
ber01-VHDL13_DWEH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:28:16                3180
ber01-VHDL13_DWEH_261800-2512261800-dsw--0-ia5     26-Dec-2025 22:05:36                3129
ber01-VHDL13_DWEH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:28:17                3857
ber01-VHDL13_DWEH_270400-2512270400-dsw--0-ia5     27-Dec-2025 05:58:13                3590
ber01-VHDL13_DWHG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                3968
ber01-VHDL13_DWHG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                3408
ber01-VHDL13_DWHG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:09                3394
ber01-VHDL13_DWHG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                3402
ber01-VHDL13_DWHG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                3385
ber01-VHDL13_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:58:23                3269
ber01-VHDL13_DWHG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:12                3184
ber01-VHDL13_DWHG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:01:11                3156
ber01-VHDL13_DWHG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                3482
ber01-VHDL13_DWHG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                3825
ber01-VHDL13_DWHH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                3335
ber01-VHDL13_DWHH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                3125
ber01-VHDL13_DWHH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:09                3041
ber01-VHDL13_DWHH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                3009
ber01-VHDL13_DWHH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                2836
ber01-VHDL13_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:58:57                2732
ber01-VHDL13_DWHH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:12                2778
ber01-VHDL13_DWHH_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:02:01                2834
ber01-VHDL13_DWHH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                3461
ber01-VHDL13_DWHH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                3631
ber01-VHDL13_DWLG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                1914
ber01-VHDL13_DWLG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                1839
ber01-VHDL13_DWLG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                2063
ber01-VHDL13_DWLG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2130
ber01-VHDL13_DWLG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                2303
ber01-VHDL13_DWLG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1938
ber01-VHDL13_DWLG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2523
ber01-VHDL13_DWLG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                2531
ber01-VHDL13_DWLH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                1904
ber01-VHDL13_DWLH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                1663
ber01-VHDL13_DWLH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                1972
ber01-VHDL13_DWLH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2105
ber01-VHDL13_DWLH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                2629
ber01-VHDL13_DWLH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1830
ber01-VHDL13_DWLH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2374
ber01-VHDL13_DWLH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                2402
ber01-VHDL13_DWLI_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                1899
ber01-VHDL13_DWLI_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                1470
ber01-VHDL13_DWLI_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                1763
ber01-VHDL13_DWLI_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2061
ber01-VHDL13_DWLI_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                2529
ber01-VHDL13_DWLI_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1551
ber01-VHDL13_DWLI_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2129
ber01-VHDL13_DWLI_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                2373
ber01-VHDL13_DWMG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                3146
ber01-VHDL13_DWMG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                3135
ber01-VHDL13_DWMG_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:31                3139
ber01-VHDL13_DWMG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                3184
ber01-VHDL13_DWMG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                3202
ber01-VHDL13_DWMG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                2885
ber01-VHDL13_DWMG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                2934
ber01-VHDL13_DWMG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:18                2938
ber01-VHDL13_DWMG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                3475
ber01-VHDL13_DWMG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:02                3243
ber01-VHDL13_DWMO_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                2577
ber01-VHDL13_DWMO_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                1925
ber01-VHDL13_DWMO_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:47                2405
ber01-VHDL13_DWMO_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                2530
ber01-VHDL13_DWMO_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2548
ber01-VHDL13_DWMO_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                2311
ber01-VHDL13_DWMO_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1726
ber01-VHDL13_DWMO_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:36                2175
ber01-VHDL13_DWMO_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2946
ber01-VHDL13_DWMO_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:02                2759
ber01-VHDL13_DWMP_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                2937
ber01-VHDL13_DWMP_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                2653
ber01-VHDL13_DWMP_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:37                3150
ber01-VHDL13_DWMP_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                3338
ber01-VHDL13_DWMP_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                3356
ber01-VHDL13_DWMP_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                3151
ber01-VHDL13_DWMP_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                3265
ber01-VHDL13_DWMP_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:26                3269
ber01-VHDL13_DWMP_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                3777
ber01-VHDL13_DWMP_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:02                3570
ber01-VHDL13_DWOG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                4942
ber01-VHDL13_DWOG_251700-2512251700-dsw--0-ia5     25-Dec-2025 19:00:03                3525
ber01-VHDL13_DWOG_260300-2512260300-dsw--0-ia5     26-Dec-2025 04:00:02                4631
ber01-VHDL13_DWOG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:06                4507
ber01-VHDL13_DWOG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 12:23:57                5146
ber01-VHDL13_DWOG_261700-2512261700-dsw--0-ia5     26-Dec-2025 19:00:02                4530
ber01-VHDL13_DWOG_270300-2512270300-dsw--0-ia5     27-Dec-2025 04:00:01                4879
ber01-VHDL13_DWOH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:28:17                2953
ber01-VHDL13_DWOH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:28:16                2182
ber01-VHDL13_DWOH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:28:12                2664
ber01-VHDL13_DWOH_260400-2512260400-dsw--0-ia5     26-Dec-2025 05:58:17                2622
ber01-VHDL13_DWOH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:28:16                2632
ber01-VHDL13_DWOH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:28:12                2483
ber01-VHDL13_DWOH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:28:11                3502
ber01-VHDL13_DWOH_270400-2512270400-dsw--0-ia5     27-Dec-2025 05:58:13                3338
ber01-VHDL13_DWOI_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:28:11                2617
ber01-VHDL13_DWOI_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:28:12                1994
ber01-VHDL13_DWOI_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:28:12                2303
ber01-VHDL13_DWOI_260400-2512260400-dsw--0-ia5     26-Dec-2025 05:58:17                2256
ber01-VHDL13_DWOI_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:28:13                2290
ber01-VHDL13_DWOI_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:28:12                2105
ber01-VHDL13_DWOI_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:28:17                2687
ber01-VHDL13_DWOI_270400-2512270400-dsw--0-ia5     27-Dec-2025 05:58:17                2503
ber01-VHDL13_DWON_250717-2512250717-dsw--0-ia5     25-Dec-2025 07:17:11                4271
ber01-VHDL13_DWON_250950-2512250950-dsw--0-ia5     25-Dec-2025 09:50:31                4271
ber01-VHDL13_DWON_251404-2512251404-dsw--0-ia5     25-Dec-2025 14:05:01                3904
ber01-VHDL13_DWON_251829-2512251829-dsw--0-ia5     25-Dec-2025 18:29:59                3695
ber01-VHDL13_DWON_252259-2512252259-dsw--0-ia5     25-Dec-2025 22:59:17                3561
ber01-VHDL13_DWON_252312-2512252312-dsw--0-ia5     25-Dec-2025 23:12:13                4315
ber01-VHDL13_DWON_260254-2512260254-dsw--0-ia5     26-Dec-2025 02:55:03                3792
ber01-VHDL13_DWON_260629-2512260629-dsw--0-ia5     26-Dec-2025 06:29:53                4238
ber01-VHDL13_DWON_260702-2512260702-dsw--0-ia5     26-Dec-2025 07:02:16                4274
ber01-VHDL13_DWON_261222-2512261222-dsw--0-ia5     26-Dec-2025 12:22:42                4352
ber01-VHDL13_DWON_261533-2512261533-dsw--0-ia5     26-Dec-2025 15:34:04                4127
ber01-VHDL13_DWON_261741-2512261741-dsw--0-ia5     26-Dec-2025 17:41:42                4084
ber01-VHDL13_DWON_262221-2512262221-dsw--0-ia5     26-Dec-2025 22:21:07                4029
ber01-VHDL13_DWON_270350-2512270350-dsw--0-ia5     27-Dec-2025 03:50:35                4459
ber01-VHDL13_DWON_270351-2512270351-dsw--0-ia5     27-Dec-2025 03:51:39                4459
ber01-VHDL13_DWON_270610-2512270610-dsw--0-ia5     27-Dec-2025 06:10:37                4804
ber01-VHDL13_DWPG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                1680
ber01-VHDL13_DWPG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                2061
ber01-VHDL13_DWPG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                2326
ber01-VHDL13_DWPG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2197
ber01-VHDL13_DWPG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                2149
ber01-VHDL13_DWPG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1695
ber01-VHDL13_DWPG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2157
ber01-VHDL13_DWPG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                2114
ber01-VHDL13_DWPH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                1831
ber01-VHDL13_DWPH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                2004
ber01-VHDL13_DWPH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:02                2136
ber01-VHDL13_DWPH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:01                2177
ber01-VHDL13_DWPH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                2486
ber01-VHDL13_DWPH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                1921
ber01-VHDL13_DWPH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:07                2723
ber01-VHDL13_DWPH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                2436
ber01-VHDL13_DWSG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:30:08                3387
ber01-VHDL13_DWSG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:30:10                2514
ber01-VHDL13_DWSG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:30:00                2980
ber01-VHDL13_DWSG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:07                2992
ber01-VHDL13_DWSG_260400_COR-2512260400-dsw--0-ia5 26-Dec-2025 06:17:51                3248
ber01-VHDL13_DWSG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:30:01                3245
ber01-VHDL13_DWSG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:30:02                2913
ber01-VHDL13_DWSG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:30:01                2919
ber01-VHDL13_DWSG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                3076
ber01-VHDL17_DWOG_251200-2512251200-dsw--0-ia5     25-Dec-2025 12:18:31                4468
ber01-VHDL17_DWOG_261200-2512261200-dsw--0-ia5     26-Dec-2025 12:33:10                3947
swis2-VHDL20_DWEG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:02                3620
swis2-VHDL20_DWEG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                2603
swis2-VHDL20_DWEG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:06                3035
swis2-VHDL20_DWEG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:06                3043
swis2-VHDL20_DWEG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3382
swis2-VHDL20_DWEG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2910
swis2-VHDL20_DWEG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                3880
swis2-VHDL20_DWEG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                4015
swis2-VHDL20_DWEH_250800-2512250800-dsw--0-ia5     25-Dec-2025 13:22:23                3817
swis2-VHDL20_DWEH_250800_COR-2512250800-dsw--0-ia5 25-Dec-2025 14:21:28                3946
swis2-VHDL20_DWEH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                3085
swis2-VHDL20_DWEH_260200-2512260200-dsw--0-ia5     26-Dec-2025 21:33:42                3335
swis2-VHDL20_DWEH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:06                3935
swis2-VHDL20_DWEH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                4165
swis2-VHDL20_DWEH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                3755
swis2-VHDL20_DWEH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                4424
swis2-VHDL20_DWEH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                4279
swis2-VHDL20_DWEI_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:02                3331
swis2-VHDL20_DWEI_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                2440
swis2-VHDL20_DWEI_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:06                2690
swis2-VHDL20_DWEI_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:06                2708
swis2-VHDL20_DWEI_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                2934
swis2-VHDL20_DWEI_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2557
swis2-VHDL20_DWEI_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                3081
swis2-VHDL20_DWEI_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                3144
swis2-VHDL20_DWHG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                4613
swis2-VHDL20_DWHG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                3591
swis2-VHDL20_DWHG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:06                3580
swis2-VHDL20_DWHG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                3585
swis2-VHDL20_DWHG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                4164
swis2-VHDL20_DWHG_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:59:31                4062
swis2-VHDL20_DWHG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                3367
swis2-VHDL20_DWHG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:02:37                3339
swis2-VHDL20_DWHG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                3668
swis2-VHDL20_DWHG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                4008
swis2-VHDL20_DWHH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                3992
swis2-VHDL20_DWHH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                3311
swis2-VHDL20_DWHH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:06                3227
swis2-VHDL20_DWHH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                3195
swis2-VHDL20_DWHH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3532
swis2-VHDL20_DWHH_260800_COR-2512260800-dsw--0-ia5 26-Dec-2025 15:59:53                3413
swis2-VHDL20_DWHH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2964
swis2-VHDL20_DWHH_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 20:03:16                3020
swis2-VHDL20_DWHH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                3647
swis2-VHDL20_DWHH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:06                3817
swis2-VHDL20_DWLG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                2406
swis2-VHDL20_DWLG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                2178
swis2-VHDL20_DWLG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2405
swis2-VHDL20_DWLG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                2479
swis2-VHDL20_DWLG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                2854
swis2-VHDL20_DWLG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2287
swis2-VHDL20_DWLG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                2921
swis2-VHDL20_DWLG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:17                2923
swis2-VHDL20_DWLH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                2407
swis2-VHDL20_DWLH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                2009
swis2-VHDL20_DWLH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2321
swis2-VHDL20_DWLH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                2461
swis2-VHDL20_DWLH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3253
swis2-VHDL20_DWLH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2227
swis2-VHDL20_DWLH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                2818
swis2-VHDL20_DWLH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:17                2821
swis2-VHDL20_DWLI_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                2392
swis2-VHDL20_DWLI_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                1811
swis2-VHDL20_DWLI_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2107
swis2-VHDL20_DWLI_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                2412
swis2-VHDL20_DWLI_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3101
swis2-VHDL20_DWLI_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                1902
swis2-VHDL20_DWLI_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                2483
swis2-VHDL20_DWLI_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:17                2826
swis2-VHDL20_DWMG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                3742
swis2-VHDL20_DWMG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                3568
swis2-VHDL20_DWMG_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:31                3572
swis2-VHDL20_DWMG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                3573
swis2-VHDL20_DWMG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:02                3628
swis2-VHDL20_DWMG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:06                3524
swis2-VHDL20_DWMG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                3350
swis2-VHDL20_DWMG_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:18                3354
swis2-VHDL20_DWMG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                3966
swis2-VHDL20_DWMG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                3729
swis2-VHDL20_DWMO_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                3181
swis2-VHDL20_DWMO_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                2824
swis2-VHDL20_DWMO_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:47                2828
swis2-VHDL20_DWMO_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2954
swis2-VHDL20_DWMO_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:02                2978
swis2-VHDL20_DWMO_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:06                2958
swis2-VHDL20_DWMO_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2591
swis2-VHDL20_DWMO_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:36                2595
swis2-VHDL20_DWMO_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                3367
swis2-VHDL20_DWMO_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                3249
swis2-VHDL20_DWMP_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                3541
swis2-VHDL20_DWMP_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                3598
swis2-VHDL20_DWMP_251800_COR-2512251800-dsw--0-ia5 25-Dec-2025 19:43:37                3602
swis2-VHDL20_DWMP_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                3758
swis2-VHDL20_DWMP_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:02                3785
swis2-VHDL20_DWMP_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:06                3799
swis2-VHDL20_DWMP_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                3665
swis2-VHDL20_DWMP_261800_COR-2512261800-dsw--0-ia5 26-Dec-2025 19:44:26                3669
swis2-VHDL20_DWMP_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                4233
swis2-VHDL20_DWMP_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                3989
swis2-VHDL20_DWPG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                2149
swis2-VHDL20_DWPG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                2530
swis2-VHDL20_DWPG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2655
swis2-VHDL20_DWPG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                2559
swis2-VHDL20_DWPG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                2712
swis2-VHDL20_DWPG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2258
swis2-VHDL20_DWPG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:40                2594
swis2-VHDL20_DWPG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:17                2548
swis2-VHDL20_DWPH_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                2290
swis2-VHDL20_DWPH_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:04                2463
swis2-VHDL20_DWPH_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:01                2464
swis2-VHDL20_DWPH_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:00:11                2505
swis2-VHDL20_DWPH_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3058
swis2-VHDL20_DWPH_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:02                2493
swis2-VHDL20_DWPH_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                3168
swis2-VHDL20_DWPH_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:00:17                2794
swis2-VHDL20_DWSG_250800-2512250800-dsw--0-ia5     25-Dec-2025 09:45:06                4112
swis2-VHDL20_DWSG_251300-2512251300-dsw--0-ia5     25-Dec-2025 14:45:12                3882
swis2-VHDL20_DWSG_251800-2512251800-dsw--0-ia5     25-Dec-2025 19:45:06                2982
swis2-VHDL20_DWSG_260200-2512260200-dsw--0-ia5     26-Dec-2025 03:45:06                3439
swis2-VHDL20_DWSG_260400-2512260400-dsw--0-ia5     26-Dec-2025 06:15:02                3401
swis2-VHDL20_DWSG_260400_COR-2512260400-dsw--0-ia5 26-Dec-2025 06:17:51                3614
swis2-VHDL20_DWSG_260800-2512260800-dsw--0-ia5     26-Dec-2025 09:45:02                3769
swis2-VHDL20_DWSG_261300-2512261300-dsw--0-ia5     26-Dec-2025 14:45:10                3639
swis2-VHDL20_DWSG_261800-2512261800-dsw--0-ia5     26-Dec-2025 19:45:06                3281
swis2-VHDL20_DWSG_270200-2512270200-dsw--0-ia5     27-Dec-2025 03:45:38                3321
swis2-VHDL20_DWSG_270400-2512270400-dsw--0-ia5     27-Dec-2025 06:15:02                3485
wst04-VHDL20_DWEG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:22              220060
wst04-VHDL20_DWEG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:16              216232
wst04-VHDL20_DWEG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:16              217593
wst04-VHDL20_DWEG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:22              217041
wst04-VHDL20_DWEG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:22              227182
wst04-VHDL20_DWEG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:16              224835
wst04-VHDL20_DWEG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              227691
wst04-VHDL20_DWEG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:27              227202
wst04-VHDL20_DWEH_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:22              217610
wst04-VHDL20_DWEH_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:16              215639
wst04-VHDL20_DWEH_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:16              217582
wst04-VHDL20_DWEH_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:26              217406
wst04-VHDL20_DWEH_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:22              225450
wst04-VHDL20_DWEH_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:16              224483
wst04-VHDL20_DWEH_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              224886
wst04-VHDL20_DWEH_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:21              224848
wst04-VHDL20_DWEI_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:26              291254
wst04-VHDL20_DWEI_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:16              288816
wst04-VHDL20_DWEI_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:16              289607
wst04-VHDL20_DWEI_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:26              289502
wst04-VHDL20_DWEI_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:26              309233
wst04-VHDL20_DWEI_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:16              308532
wst04-VHDL20_DWEI_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              309233
wst04-VHDL20_DWEI_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:27              309390
wst04-VHDL20_DWHG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:16              309545
wst04-VHDL20_DWHG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:16              306827
wst04-VHDL20_DWHG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:12              306726
wst04-VHDL20_DWHG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:11              306804
wst04-VHDL20_DWHG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:17              311638
wst04-VHDL20_DWHG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:16              309115
wst04-VHDL20_DWHG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              309937
wst04-VHDL20_DWHG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:11              310232
wst04-VHDL20_DWHH_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:22              303621
wst04-VHDL20_DWHH_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:22              302120
wst04-VHDL20_DWHH_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:12              302081
wst04-VHDL20_DWHH_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:11              302162
wst04-VHDL20_DWHH_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:22              305922
wst04-VHDL20_DWHH_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:22              305856
wst04-VHDL20_DWHH_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              307323
wst04-VHDL20_DWHH_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:11              307014
wst04-VHDL20_DWLG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:30              294118
wst04-VHDL20_DWLG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:22              293368
wst04-VHDL20_DWLG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:22              294178
wst04-VHDL20_DWLG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:41              293819
wst04-VHDL20_DWLG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:30              295621
wst04-VHDL20_DWLG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:26              294801
wst04-VHDL20_DWLG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              295694
wst04-VHDL20_DWLG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:41              295564
wst04-VHDL20_DWLH_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:30              297898
wst04-VHDL20_DWLH_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:26              297214
wst04-VHDL20_DWLH_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:26              297730
wst04-VHDL20_DWLH_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:41              297884
wst04-VHDL20_DWLH_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:30              300213
wst04-VHDL20_DWLH_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:20              298721
wst04-VHDL20_DWLH_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              299282
wst04-VHDL20_DWLH_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:41              299496
wst04-VHDL20_DWLI_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:30              290782
wst04-VHDL20_DWLI_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:26              289701
wst04-VHDL20_DWLI_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:22              290051
wst04-VHDL20_DWLI_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:41              290292
wst04-VHDL20_DWLI_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:30              300816
wst04-VHDL20_DWLI_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:26              299906
wst04-VHDL20_DWLI_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              300735
wst04-VHDL20_DWLI_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:41              301249
wst04-VHDL20_DWMG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:16              477026
wst04-VHDL20_DWMG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:16              476283
wst04-VHDL20_DWMG_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:37              476283
wst04-VHDL20_DWMG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:22              476302
wst04-VHDL20_DWMG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:22              476195
wst04-VHDL20_DWMG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:17              486489
wst04-VHDL20_DWMG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:16              486024
wst04-VHDL20_DWMG_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:26              486024
wst04-VHDL20_DWMG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              486759
wst04-VHDL20_DWMG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:21              486443
wst04-VHDL20_DWMO_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:12              392087
wst04-VHDL20_DWMO_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:12              390201
wst04-VHDL20_DWMO_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:51              390201
wst04-VHDL20_DWMO_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:18              390898
wst04-VHDL20_DWMO_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:22              391384
wst04-VHDL20_DWMO_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:12              397869
wst04-VHDL20_DWMO_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:12              396067
wst04-VHDL20_DWMO_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:42              396067
wst04-VHDL20_DWMO_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              397720
wst04-VHDL20_DWMO_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:21              398114
wst04-VHDL20_DWMP_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:16              492111
wst04-VHDL20_DWMP_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:12              491459
wst04-VHDL20_DWMP_251800_COR-2512251800-omedes-..> 25-Dec-2025 19:43:47              491459
wst04-VHDL20_DWMP_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:18              490318
wst04-VHDL20_DWMP_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:22              491523
wst04-VHDL20_DWMP_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:17              492902
wst04-VHDL20_DWMP_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:12              492496
wst04-VHDL20_DWMP_261800_COR-2512261800-omedes-..> 26-Dec-2025 19:44:32              492496
wst04-VHDL20_DWMP_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:38              491836
wst04-VHDL20_DWMP_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:17              492884
wst04-VHDL20_DWPG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:30              347094
wst04-VHDL20_DWPG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:22              303135
wst04-VHDL20_DWPG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:26              303324
wst04-VHDL20_DWPG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:31              303183
wst04-VHDL20_DWPG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:30              355557
wst04-VHDL20_DWPG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:26              310197
wst04-VHDL20_DWPG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              310547
wst04-VHDL20_DWPG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:31              310582
wst04-VHDL20_DWPH_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:26              270672
wst04-VHDL20_DWPH_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:22              270707
wst04-VHDL20_DWPH_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:22              226467
wst04-VHDL20_DWPH_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:00:31              225685
wst04-VHDL20_DWPH_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:26              268530
wst04-VHDL20_DWPH_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:20              267673
wst04-VHDL20_DWPH_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              224610
wst04-VHDL20_DWPH_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:00:31              224112
wst04-VHDL20_DWSG_250800-2512250800-omedes--0.pdf  25-Dec-2025 09:45:12              303553
wst04-VHDL20_DWSG_251300-2512251300-omedes--0.pdf  25-Dec-2025 14:45:12              303496
wst04-VHDL20_DWSG_251800-2512251800-omedes--0.pdf  25-Dec-2025 19:45:12              302511
wst04-VHDL20_DWSG_260200-2512260200-omedes--0.pdf  26-Dec-2025 03:45:12              302504
wst04-VHDL20_DWSG_260400-2512260400-omedes--0.pdf  26-Dec-2025 06:15:16              303072
wst04-VHDL20_DWSG_260400_COR-2512260400-omedes-..> 26-Dec-2025 06:18:01              303883
wst04-VHDL20_DWSG_260800-2512260800-omedes--0.pdf  26-Dec-2025 09:45:12              308699
wst04-VHDL20_DWSG_261300-2512261300-omedes--0.pdf  26-Dec-2025 14:45:13              308891
wst04-VHDL20_DWSG_261800-2512261800-omedes--0.pdf  26-Dec-2025 19:45:12              307529
wst04-VHDL20_DWSG_270200-2512270200-omedes--0.pdf  27-Dec-2025 03:45:40              307791
wst04-VHDL20_DWSG_270400-2512270400-omedes--0.pdf  27-Dec-2025 06:15:17              308212