Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_180600 18-Sep-2026 11:46:09 3783
FPDL13_DWMZ_190600 19-Sep-2026 10:36:51 11466
SXDL31_DWAV_180800 18-Sep-2026 07:13:54 14979
SXDL31_DWAV_181800 18-Sep-2026 17:05:45 6129
SXDL31_DWAV_190800 19-Sep-2026 08:05:14 13677
SXDL31_DWAV_191800 19-Sep-2026 16:37:28 11962
SXDL31_DWAV_LATEST 19-Sep-2026 16:37:28 11962
SXDL33_DWAV_180000 18-Sep-2026 10:03:20 5102
SXDL33_DWAV_190000 19-Sep-2026 10:02:08 5840
SXDL33_DWAV_LATEST 19-Sep-2026 10:02:08 5840
ber01-FWDL39_DWMS_181200-2609181200-dsw--0-ia5 18-Sep-2026 11:07:25 1195
ber01-FWDL39_DWMS_191200-2609191200-dsw--0-ia5 19-Sep-2026 11:05:44 1171
ber01-VHDL13_DWEG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:18 2621
ber01-VHDL13_DWEG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:28:14 2822
ber01-VHDL13_DWEH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:14 2596
ber01-VHDL13_DWEH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:28:18 2784
ber01-VHDL13_DWEI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:28:18 2550
ber01-VHDL13_DWEI_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:28:18 2582
ber01-VHDL13_DWHG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 3538
ber01-VHDL13_DWHG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:12 3473
ber01-VHDL13_DWHG_190800_COR-2609190800-dsw--0-ia5 19-Sep-2026 09:05:37 3473
ber01-VHDL13_DWHH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 3604
ber01-VHDL13_DWHH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:12 3476
ber01-VHDL13_DWHH_190800_COR-2609190800-dsw--0-ia5 19-Sep-2026 09:06:05 3484
ber01-VHDL13_DWLG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2424
ber01-VHDL13_DWLG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 2810
ber01-VHDL13_DWLH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2686
ber01-VHDL13_DWLH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 3438
ber01-VHDL13_DWLI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2440
ber01-VHDL13_DWLI_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 2834
ber01-VHDL13_DWMO_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 2844
ber01-VHDL13_DWMO_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 3150
ber01-VHDL13_DWMP_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 2795
ber01-VHDL13_DWMP_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 3101
ber01-VHDL13_DWOG_180300-2609180300-dsw--0-ia5 18-Sep-2026 03:00:03 3615
ber01-VHDL13_DWOG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:11 3950
ber01-VHDL13_DWOG_181700-2609181700-dsw--0-ia5 18-Sep-2026 18:00:06 3889
ber01-VHDL13_DWOG_190300-2609190300-dsw--0-ia5 19-Sep-2026 03:01:01 3897
ber01-VHDL13_DWOG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 3553
ber01-VHDL13_DWOG_191700-2609191700-dsw--0-ia5 19-Sep-2026 18:00:04 3793
ber01-VHDL13_DWON_180130-2609180130-dsw--0-ia5 18-Sep-2026 01:30:29 3301
ber01-VHDL13_DWON_180419-2609180419-dsw--0-ia5 18-Sep-2026 04:20:25 3301
ber01-VHDL13_DWON_180523-2609180523-dsw--0-ia5 18-Sep-2026 05:23:22 3964
ber01-VHDL13_DWON_180839-2609180839-dsw--0-ia5 18-Sep-2026 08:39:23 3911
ber01-VHDL13_DWON_181357-2609181357-dsw--0-ia5 18-Sep-2026 13:57:29 3798
ber01-VHDL13_DWON_181710-2609181710-dsw--0-ia5 18-Sep-2026 17:10:53 3361
ber01-VHDL13_DWON_190144-2609190144-dsw--0-ia5 19-Sep-2026 01:44:59 3161
ber01-VHDL13_DWON_190517-2609190517-dsw--0-ia5 19-Sep-2026 05:17:38 3822
ber01-VHDL13_DWON_190631-2609190631-dsw--0-ia5 19-Sep-2026 06:32:15 3823
ber01-VHDL13_DWON_191037-2609191037-dsw--0-ia5 19-Sep-2026 10:37:52 3823
ber01-VHDL13_DWON_191348-2609191348-dsw--0-ia5 19-Sep-2026 13:48:48 3898
ber01-VHDL13_DWON_191644-2609191644-dsw--0-ia5 19-Sep-2026 16:44:22 3567
ber01-VHDL13_DWON_191720-2609191720-dsw--0-ia5 19-Sep-2026 17:20:38 3567
ber01-VHDL13_DWPG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2254
ber01-VHDL13_DWPG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 2848
ber01-VHDL13_DWPH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2411
ber01-VHDL13_DWPH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 2829
ber01-VHDL13_DWSG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 2585
ber01-VHDL13_DWSG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 2329
ber01-VHDL17_DWOG_181200-2609181200-dsw--0-ia5 18-Sep-2026 12:03:24 2068
ber01-VHDL17_DWOG_191200-2609191200-dsw--0-ia5 19-Sep-2026 11:34:05 2207
swis2-VHDL20_DWEG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1101
swis2-VHDL20_DWEG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1078
swis2-VHDL20_DWEG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1293
swis2-VHDL20_DWEG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1388
swis2-VHDL20_DWEG_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:08 993
swis2-VHDL20_DWEG_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:01:08 989
swis2-VHDL20_DWEG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 1211
swis2-VHDL20_DWEG_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:09 1535
swis2-VHDL20_DWEH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1115
swis2-VHDL20_DWEH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1092
swis2-VHDL20_DWEH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1230
swis2-VHDL20_DWEH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1445
swis2-VHDL20_DWEH_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:08 1019
swis2-VHDL20_DWEH_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:01:08 1015
swis2-VHDL20_DWEH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 1229
swis2-VHDL20_DWEH_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:09 1723
swis2-VHDL20_DWEI_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:07 1123
swis2-VHDL20_DWEI_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:01:18 1100
swis2-VHDL20_DWEI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1284
swis2-VHDL20_DWEI_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1334
swis2-VHDL20_DWEI_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:08 987
swis2-VHDL20_DWEI_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:01:08 983
swis2-VHDL20_DWEI_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 1202
swis2-VHDL20_DWEI_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:09 1435
swis2-VHDL20_DWHG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:46:01 1585
swis2-VHDL20_DWHG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 1582
swis2-VHDL20_DWHG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:45:13 2028
swis2-VHDL20_DWHG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:45:10 2560
swis2-VHDL20_DWHG_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:48:09 1934
swis2-VHDL20_DWHG_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 1920
swis2-VHDL20_DWHG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:45:55 1956
swis2-VHDL20_DWHG_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:45:13 1999
swis2-VHDL20_DWHH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:46:01 2027
swis2-VHDL20_DWHH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 2027
swis2-VHDL20_DWHH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:45:13 2386
swis2-VHDL20_DWHH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:45:10 3192
swis2-VHDL20_DWHH_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:48:09 2443
swis2-VHDL20_DWHH_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 2427
swis2-VHDL20_DWHH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:45:55 2118
swis2-VHDL20_DWHH_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:45:13 2201
swis2-VHDL20_DWLG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 880
swis2-VHDL20_DWLG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 834
swis2-VHDL20_DWLG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 980
swis2-VHDL20_DWLG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 883
swis2-VHDL20_DWLG_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:24 950
swis2-VHDL20_DWLG_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 948
swis2-VHDL20_DWLG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:35 1042
swis2-VHDL20_DWLG_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:31:05 1136
swis2-VHDL20_DWLH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 1067
swis2-VHDL20_DWLH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 982
swis2-VHDL20_DWLH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1287
swis2-VHDL20_DWLH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1117
swis2-VHDL20_DWLH_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:24 1109
swis2-VHDL20_DWLH_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 1131
swis2-VHDL20_DWLH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:35 1225
swis2-VHDL20_DWLH_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:31:03 1511
swis2-VHDL20_DWLI_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 882
swis2-VHDL20_DWLI_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 836
swis2-VHDL20_DWLI_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 914
swis2-VHDL20_DWLI_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 776
swis2-VHDL20_DWLI_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:24 826
swis2-VHDL20_DWLI_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 832
swis2-VHDL20_DWLI_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:35 925
swis2-VHDL20_DWLI_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:31:05 1205
swis2-VHDL20_DWMO_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1060
swis2-VHDL20_DWMO_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:15 1037
swis2-VHDL20_DWMO_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 1330
swis2-VHDL20_DWMO_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1243
swis2-VHDL20_DWMO_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:06 1234
swis2-VHDL20_DWMO_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 1210
swis2-VHDL20_DWMO_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 1298
swis2-VHDL20_DWMO_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:03 1391
swis2-VHDL20_DWMP_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1075
swis2-VHDL20_DWMP_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:15 1043
swis2-VHDL20_DWMP_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:14 1278
swis2-VHDL20_DWMP_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 1177
swis2-VHDL20_DWMP_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:06 1260
swis2-VHDL20_DWMP_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 1240
swis2-VHDL20_DWMP_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 1301
swis2-VHDL20_DWMP_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:03 1549
swis2-VHDL20_DWPG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 901
swis2-VHDL20_DWPG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 853
swis2-VHDL20_DWPG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1119
swis2-VHDL20_DWPG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1023
swis2-VHDL20_DWPG_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:24 984
swis2-VHDL20_DWPG_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 945
swis2-VHDL20_DWPG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:35 1054
swis2-VHDL20_DWPG_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:31:05 1302
swis2-VHDL20_DWPH_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:24 1076
swis2-VHDL20_DWPH_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 895
swis2-VHDL20_DWPH_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:22 1201
swis2-VHDL20_DWPH_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:31:03 1114
swis2-VHDL20_DWPH_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:24 1125
swis2-VHDL20_DWPH_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 1110
swis2-VHDL20_DWPH_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:35 1307
swis2-VHDL20_DWPH_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:31:05 1471
swis2-VHDL20_DWSG_180200-2609180200-dsw--0-ia5 18-Sep-2026 02:30:03 1031
swis2-VHDL20_DWSG_180400-2609180400-dsw--0-ia5 18-Sep-2026 05:00:17 1031
swis2-VHDL20_DWSG_180800-2609180800-dsw--0-ia5 18-Sep-2026 08:30:05 1083
swis2-VHDL20_DWSG_181800-2609181800-dsw--0-ia5 18-Sep-2026 18:30:03 941
swis2-VHDL20_DWSG_190200-2609190200-dsw--0-ia5 19-Sep-2026 02:30:06 935
swis2-VHDL20_DWSG_190400-2609190400-dsw--0-ia5 19-Sep-2026 05:00:23 936
swis2-VHDL20_DWSG_190800-2609190800-dsw--0-ia5 19-Sep-2026 08:30:04 937
swis2-VHDL20_DWSG_191800-2609191800-dsw--0-ia5 19-Sep-2026 18:30:03 1165
wst04-VHDL20_DWEG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 242912
wst04-VHDL20_DWEG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 242823
wst04-VHDL20_DWEG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 243753
wst04-VHDL20_DWEG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 244169
wst04-VHDL20_DWEG_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:22 242894
wst04-VHDL20_DWEG_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 242292
wst04-VHDL20_DWEG_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:24 243313
wst04-VHDL20_DWEG_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:13 240675
wst04-VHDL20_DWEH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 233748
wst04-VHDL20_DWEH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 233879
wst04-VHDL20_DWEH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 234723
wst04-VHDL20_DWEH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 234009
wst04-VHDL20_DWEH_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:22 232349
wst04-VHDL20_DWEH_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 231968
wst04-VHDL20_DWEH_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:24 233020
wst04-VHDL20_DWEH_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:13 236743
wst04-VHDL20_DWEI_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 345429
wst04-VHDL20_DWEI_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 345255
wst04-VHDL20_DWEI_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:14 345658
wst04-VHDL20_DWEI_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 348484
wst04-VHDL20_DWEI_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:22 347783
wst04-VHDL20_DWEI_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 347130
wst04-VHDL20_DWEI_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:35 347619
wst04-VHDL20_DWEI_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:25 344291
wst04-VHDL20_DWHG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:46:18 325071
wst04-VHDL20_DWHG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 324865
wst04-VHDL20_DWHG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:45:41 326622
wst04-VHDL20_DWHG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:45:14 332698
wst04-VHDL20_DWHG_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:48:09 330795
wst04-VHDL20_DWHG_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 330627
wst04-VHDL20_DWHG_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:46:24 333622
wst04-VHDL20_DWHG_190800_COR-2609190800-omedes-..> 19-Sep-2026 08:51:41 333622
wst04-VHDL20_DWHG_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:45:13 337980
wst04-VHDL20_DWHH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:46:18 329328
wst04-VHDL20_DWHH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 230561
wst04-VHDL20_DWHH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:45:41 329501
wst04-VHDL20_DWHH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:45:14 330407
wst04-VHDL20_DWHH_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:48:09 329870
wst04-VHDL20_DWHH_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 232582
wst04-VHDL20_DWHH_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:46:24 329465
wst04-VHDL20_DWHH_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:45:13 324052
wst04-VHDL20_DWLG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 327255
wst04-VHDL20_DWLG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 327307
wst04-VHDL20_DWLG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:51 327843
wst04-VHDL20_DWLG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 329464
wst04-VHDL20_DWLG_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 374075
wst04-VHDL20_DWLG_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:43 329284
wst04-VHDL20_DWLG_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:59 329525
wst04-VHDL20_DWLG_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:31:33 331069
wst04-VHDL20_DWLH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 326425
wst04-VHDL20_DWLH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 326413
wst04-VHDL20_DWLH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 327222
wst04-VHDL20_DWLH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 328306
wst04-VHDL20_DWLH_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 372460
wst04-VHDL20_DWLH_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:43 327711
wst04-VHDL20_DWLH_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:59 327933
wst04-VHDL20_DWLH_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:31:33 333419
wst04-VHDL20_DWLI_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 329540
wst04-VHDL20_DWLI_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:43 329574
wst04-VHDL20_DWLI_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 374651
wst04-VHDL20_DWLI_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 330112
wst04-VHDL20_DWLI_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:37 374851
wst04-VHDL20_DWLI_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:43 330052
wst04-VHDL20_DWLI_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:59 374831
wst04-VHDL20_DWLI_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:31:33 333522
wst04-VHDL20_DWMO_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:22 434347
wst04-VHDL20_DWMO_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 434263
wst04-VHDL20_DWMO_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:18 434268
wst04-VHDL20_DWMO_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 340289
wst04-VHDL20_DWMO_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 437385
wst04-VHDL20_DWMO_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 437274
wst04-VHDL20_DWMO_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:35 437967
wst04-VHDL20_DWMO_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:25 343986
wst04-VHDL20_DWMP_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:22 550282
wst04-VHDL20_DWMP_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 550223
wst04-VHDL20_DWMP_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:24 448023
wst04-VHDL20_DWMP_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 452411
wst04-VHDL20_DWMP_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 553501
wst04-VHDL20_DWMP_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 553346
wst04-VHDL20_DWMP_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:35 452452
wst04-VHDL20_DWMP_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:25 455327
wst04-VHDL20_DWPG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:29 232417
wst04-VHDL20_DWPG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:33 324877
wst04-VHDL20_DWPG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 370562
wst04-VHDL20_DWPG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:28 332530
wst04-VHDL20_DWPG_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 235171
wst04-VHDL20_DWPG_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:33 331849
wst04-VHDL20_DWPG_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:59 376795
wst04-VHDL20_DWPG_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:31:33 341699
wst04-VHDL20_DWPH_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:24 234719
wst04-VHDL20_DWPH_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:33 234184
wst04-VHDL20_DWPH_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:43 234931
wst04-VHDL20_DWPH_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:31:26 239379
wst04-VHDL20_DWPH_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:24 283492
wst04-VHDL20_DWPH_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:33 238788
wst04-VHDL20_DWPH_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:59 239121
wst04-VHDL20_DWPH_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:31:33 236597
wst04-VHDL20_DWSG_180200-2609180200-omedes--0.pdf 18-Sep-2026 02:30:13 334522
wst04-VHDL20_DWSG_180400-2609180400-omedes--0.pdf 18-Sep-2026 05:00:17 334339
wst04-VHDL20_DWSG_180800-2609180800-omedes--0.pdf 18-Sep-2026 08:30:18 334363
wst04-VHDL20_DWSG_181800-2609181800-omedes--0.pdf 18-Sep-2026 18:30:18 341655
wst04-VHDL20_DWSG_190200-2609190200-omedes--0.pdf 19-Sep-2026 02:30:22 341716
wst04-VHDL20_DWSG_190400-2609190400-omedes--0.pdf 19-Sep-2026 05:00:23 341520
wst04-VHDL20_DWSG_190800-2609190800-omedes--0.pdf 19-Sep-2026 08:30:35 341481
wst04-VHDL20_DWSG_191800-2609191800-omedes--0.pdf 19-Sep-2026 18:30:25 344043