Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_210600 21-Jun-2026 13:48:00 4057
FPDL13_DWMZ_220600 22-Jun-2026 12:40:46 3886
SXDL31_DWAV_201800 20-Jun-2026 16:29:04 5903
SXDL31_DWAV_210800 21-Jun-2026 08:13:45 9179
SXDL31_DWAV_211800 21-Jun-2026 17:05:19 9009
SXDL31_DWAV_220800 22-Jun-2026 06:56:00 14323
SXDL31_DWAV_LATEST 22-Jun-2026 06:56:00 14323
SXDL33_DWAV_210000 21-Jun-2026 10:36:37 14192
SXDL33_DWAV_220000 22-Jun-2026 09:40:59 6260
SXDL33_DWAV_LATEST 22-Jun-2026 09:40:59 6260
ber01-FWDL39_DWMS_211200-2606211200-dsw--0-ia5 21-Jun-2026 11:06:53 1169
ber01-FWDL39_DWMS_221200-2606221200-dsw--0-ia5 22-Jun-2026 11:31:17 1227
ber01-VHDL13_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3719
ber01-VHDL13_DWEG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:16 3338
ber01-VHDL13_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3725
ber01-VHDL13_DWEH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:12 3120
ber01-VHDL13_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:28:17 3430
ber01-VHDL13_DWEI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:28:16 3187
ber01-VHDL13_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3615
ber01-VHDL13_DWHG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2801
ber01-VHDL13_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2871
ber01-VHDL13_DWHH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2439
ber01-VHDL13_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2810
ber01-VHDL13_DWLG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2162
ber01-VHDL13_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2707
ber01-VHDL13_DWLH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2084
ber01-VHDL13_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2760
ber01-VHDL13_DWLI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 2125
ber01-VHDL13_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 3483
ber01-VHDL13_DWMO_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 3016
ber01-VHDL13_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL13_DWMP_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 2875
ber01-VHDL13_DWOG_201700-2606201700-dsw--0-ia5 20-Jun-2026 18:00:01 4235
ber01-VHDL13_DWOG_210300-2606210300-dsw--0-ia5 21-Jun-2026 03:00:02 4349
ber01-VHDL13_DWOG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 4689
ber01-VHDL13_DWOG_211700-2606211700-dsw--0-ia5 21-Jun-2026 18:00:01 3993
ber01-VHDL13_DWOG_220300-2606220300-dsw--0-ia5 22-Jun-2026 03:00:02 3355
ber01-VHDL13_DWOG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 3574
ber01-VHDL13_DWON_201720-2606201720-dsw--0-ia5 20-Jun-2026 17:20:26 3308
ber01-VHDL13_DWON_202127-2606202127-dsw--0-ia5 20-Jun-2026 21:27:53 3286
ber01-VHDL13_DWON_202344-2606202344-dsw--0-ia5 20-Jun-2026 23:44:12 3329
ber01-VHDL13_DWON_210128-2606210128-dsw--0-ia5 21-Jun-2026 01:28:56 3578
ber01-VHDL13_DWON_210249-2606210249-dsw--0-ia5 21-Jun-2026 02:50:29 3766
ber01-VHDL13_DWON_210530-2606210530-dsw--0-ia5 21-Jun-2026 05:30:07 3553
ber01-VHDL13_DWON_210629-2606210629-dsw--0-ia5 21-Jun-2026 06:29:27 4007
ber01-VHDL13_DWON_210721-2606210721-dsw--0-ia5 21-Jun-2026 07:21:22 4143
ber01-VHDL13_DWON_210722-2606210722-dsw--0-ia5 21-Jun-2026 07:22:51 4147
ber01-VHDL13_DWON_211000-2606211000-dsw--0-ia5 21-Jun-2026 10:00:52 3894
ber01-VHDL13_DWON_211446-2606211446-dsw--0-ia5 21-Jun-2026 14:46:37 3864
ber01-VHDL13_DWON_211728-2606211728-dsw--0-ia5 21-Jun-2026 17:28:12 3283
ber01-VHDL13_DWON_220058-2606220058-dsw--0-ia5 22-Jun-2026 00:58:31 3823
ber01-VHDL13_DWON_220233-2606220233-dsw--0-ia5 22-Jun-2026 02:33:35 3823
ber01-VHDL13_DWON_220522-2606220522-dsw--0-ia5 22-Jun-2026 05:22:47 3355
ber01-VHDL13_DWON_220746-2606220746-dsw--0-ia5 22-Jun-2026 07:46:51 3355
ber01-VHDL13_DWON_221508-2606221508-dsw--0-ia5 22-Jun-2026 15:08:51 3298
ber01-VHDL13_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2496
ber01-VHDL13_DWPG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1798
ber01-VHDL13_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 2126
ber01-VHDL13_DWPH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1944
ber01-VHDL13_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 3223
ber01-VHDL13_DWSG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 3376
ber01-VHDL17_DWOG_211200-2606211200-dsw--0-ia5 21-Jun-2026 11:45:56 3174
ber01-VHDL17_DWOG_221200-2606221200-dsw--0-ia5 22-Jun-2026 11:10:17 3384
swis2-VHDL20_DWEG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2417
swis2-VHDL20_DWEG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1743
swis2-VHDL20_DWEG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1633
swis2-VHDL20_DWEG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1977
swis2-VHDL20_DWEG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2106
swis2-VHDL20_DWEG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1579
swis2-VHDL20_DWEG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:17 1557
swis2-VHDL20_DWEG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1931
swis2-VHDL20_DWEH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2456
swis2-VHDL20_DWEH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1613
swis2-VHDL20_DWEH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1662
swis2-VHDL20_DWEH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 2022
swis2-VHDL20_DWEH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2153
swis2-VHDL20_DWEH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:06 1402
swis2-VHDL20_DWEH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:17 1438
swis2-VHDL20_DWEH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1778
swis2-VHDL20_DWEI_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2312
swis2-VHDL20_DWEI_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1641
swis2-VHDL20_DWEI_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:01:17 1595
swis2-VHDL20_DWEI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1884
swis2-VHDL20_DWEI_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 2223
swis2-VHDL20_DWEI_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:06 1599
swis2-VHDL20_DWEI_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:01:21 1608
swis2-VHDL20_DWEI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1981
swis2-VHDL20_DWHG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:45:06 2117
swis2-VHDL20_DWHG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:45:08 1979
swis2-VHDL20_DWHG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1880
swis2-VHDL20_DWHG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 2030
swis2-VHDL20_DWHG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:45:01 1754
swis2-VHDL20_DWHG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:45:06 1350
swis2-VHDL20_DWHG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 1344
swis2-VHDL20_DWHG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:45:08 1361
swis2-VHDL20_DWHH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:45:06 1526
swis2-VHDL20_DWHH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:45:08 1470
swis2-VHDL20_DWHH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1245
swis2-VHDL20_DWHH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:45:13 1419
swis2-VHDL20_DWHH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:45:01 1095
swis2-VHDL20_DWHH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:45:06 991
swis2-VHDL20_DWHH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 988
swis2-VHDL20_DWHH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:45:08 1097
swis2-VHDL20_DWLG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1337
swis2-VHDL20_DWLG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1341
swis2-VHDL20_DWLG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1372
swis2-VHDL20_DWLG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1578
swis2-VHDL20_DWLG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:19 1378
swis2-VHDL20_DWLG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1179
swis2-VHDL20_DWLG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 866
swis2-VHDL20_DWLG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1077
swis2-VHDL20_DWLH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1290
swis2-VHDL20_DWLH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1145
swis2-VHDL20_DWLH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1488
swis2-VHDL20_DWLH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1612
swis2-VHDL20_DWLH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1183
swis2-VHDL20_DWLH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1198
swis2-VHDL20_DWLH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 874
swis2-VHDL20_DWLH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1094
swis2-VHDL20_DWLI_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1206
swis2-VHDL20_DWLI_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1395
swis2-VHDL20_DWLI_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1494
swis2-VHDL20_DWLI_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1700
swis2-VHDL20_DWLI_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1377
swis2-VHDL20_DWLI_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 1177
swis2-VHDL20_DWLI_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 867
swis2-VHDL20_DWLI_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 1087
swis2-VHDL20_DWMO_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 2012
swis2-VHDL20_DWMO_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:07 1577
swis2-VHDL20_DWMO_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:03 1626
swis2-VHDL20_DWMO_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1806
swis2-VHDL20_DWMO_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:19 1743
swis2-VHDL20_DWMO_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1725
swis2-VHDL20_DWMO_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:02 1611
swis2-VHDL20_DWMO_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 1565
swis2-VHDL20_DWMP_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 1898
swis2-VHDL20_DWMP_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:07 1506
swis2-VHDL20_DWMP_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:03 1511
swis2-VHDL20_DWMP_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:17 1709
swis2-VHDL20_DWMP_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1710
swis2-VHDL20_DWMP_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1598
swis2-VHDL20_DWMP_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:02 1428
swis2-VHDL20_DWMP_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:07 1537
swis2-VHDL20_DWPG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 1289
swis2-VHDL20_DWPG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 1368
swis2-VHDL20_DWPG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 1571
swis2-VHDL20_DWPG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1445
swis2-VHDL20_DWPG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1053
swis2-VHDL20_DWPG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 836
swis2-VHDL20_DWPG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 773
swis2-VHDL20_DWPG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 978
swis2-VHDL20_DWPH_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:31:01 861
swis2-VHDL20_DWPH_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:22 842
swis2-VHDL20_DWPH_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:11 931
swis2-VHDL20_DWPH_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:21 1049
swis2-VHDL20_DWPH_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 925
swis2-VHDL20_DWPH_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:24 843
swis2-VHDL20_DWPH_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:11 770
swis2-VHDL20_DWPH_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:23 894
swis2-VHDL20_DWSG_201800-2606201800-dsw--0-ia5 20-Jun-2026 18:30:06 1674
swis2-VHDL20_DWSG_210200-2606210200-dsw--0-ia5 21-Jun-2026 02:30:02 1439
swis2-VHDL20_DWSG_210400-2606210400-dsw--0-ia5 21-Jun-2026 05:00:17 1369
swis2-VHDL20_DWSG_210800-2606210800-dsw--0-ia5 21-Jun-2026 08:30:16 1607
swis2-VHDL20_DWSG_211800-2606211800-dsw--0-ia5 21-Jun-2026 18:31:20 1676
swis2-VHDL20_DWSG_220200-2606220200-dsw--0-ia5 22-Jun-2026 02:30:01 1580
swis2-VHDL20_DWSG_220400-2606220400-dsw--0-ia5 22-Jun-2026 05:00:17 1445
swis2-VHDL20_DWSG_220800-2606220800-dsw--0-ia5 22-Jun-2026 08:30:03 1595
wst04-VHDL20_DWEG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 252206
wst04-VHDL20_DWEG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 250231
wst04-VHDL20_DWEG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 249721
wst04-VHDL20_DWEG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 251328
wst04-VHDL20_DWEG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:19 250641
wst04-VHDL20_DWEG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 248937
wst04-VHDL20_DWEG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 248350
wst04-VHDL20_DWEG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 249739
wst04-VHDL20_DWEH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 251789
wst04-VHDL20_DWEH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 250156
wst04-VHDL20_DWEH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 250338
wst04-VHDL20_DWEH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 251448
wst04-VHDL20_DWEH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 248963
wst04-VHDL20_DWEH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 247723
wst04-VHDL20_DWEH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 247064
wst04-VHDL20_DWEH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 248708
wst04-VHDL20_DWEI_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 364279
wst04-VHDL20_DWEI_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:11 362813
wst04-VHDL20_DWEI_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:13 362501
wst04-VHDL20_DWEI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:16 363969
wst04-VHDL20_DWEI_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 368362
wst04-VHDL20_DWEI_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 367176
wst04-VHDL20_DWEI_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 366558
wst04-VHDL20_DWEI_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:12 367392
wst04-VHDL20_DWHG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:45:12 356361
wst04-VHDL20_DWHG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:46:02 356597
wst04-VHDL20_DWHG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 356296
wst04-VHDL20_DWHG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 357125
wst04-VHDL20_DWHG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:45:11 353970
wst04-VHDL20_DWHG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:45:12 351253
wst04-VHDL20_DWHG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 350801
wst04-VHDL20_DWHG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:45:14 352203
wst04-VHDL20_DWHH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:45:12 328647
wst04-VHDL20_DWHH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:46:02 328879
wst04-VHDL20_DWHH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 220325
wst04-VHDL20_DWHH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:45:13 328334
wst04-VHDL20_DWHH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:45:11 322707
wst04-VHDL20_DWHH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:45:12 322955
wst04-VHDL20_DWHH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 219072
wst04-VHDL20_DWHH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:45:14 322212
wst04-VHDL20_DWLG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 352773
wst04-VHDL20_DWLG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 353209
wst04-VHDL20_DWLG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 352497
wst04-VHDL20_DWLG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 353321
wst04-VHDL20_DWLG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 351663
wst04-VHDL20_DWLG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 351932
wst04-VHDL20_DWLG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 351267
wst04-VHDL20_DWLG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 351545
wst04-VHDL20_DWLH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 343548
wst04-VHDL20_DWLH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 343838
wst04-VHDL20_DWLH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 343291
wst04-VHDL20_DWLH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 343371
wst04-VHDL20_DWLH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 343471
wst04-VHDL20_DWLH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 343907
wst04-VHDL20_DWLH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 343024
wst04-VHDL20_DWLH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 343307
wst04-VHDL20_DWLI_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 353474
wst04-VHDL20_DWLI_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:29 354099
wst04-VHDL20_DWLI_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:41 353355
wst04-VHDL20_DWLI_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:50 398790
wst04-VHDL20_DWLI_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 355868
wst04-VHDL20_DWLI_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:27 356126
wst04-VHDL20_DWLI_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:41 355497
wst04-VHDL20_DWLI_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:47 400384
wst04-VHDL20_DWMO_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 378463
wst04-VHDL20_DWMO_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:17 494590
wst04-VHDL20_DWMO_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 494678
wst04-VHDL20_DWMO_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 493573
wst04-VHDL20_DWMO_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 371880
wst04-VHDL20_DWMO_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:16 492903
wst04-VHDL20_DWMO_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 493006
wst04-VHDL20_DWMO_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:16 492102
wst04-VHDL20_DWMP_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:17 504062
wst04-VHDL20_DWMP_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:17 615762
wst04-VHDL20_DWMP_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:17 616132
wst04-VHDL20_DWMP_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:21 503869
wst04-VHDL20_DWMP_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 494450
wst04-VHDL20_DWMP_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:16 612612
wst04-VHDL20_DWMP_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:17 611994
wst04-VHDL20_DWMP_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:23 494097
wst04-VHDL20_DWPG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 350233
wst04-VHDL20_DWPG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 248418
wst04-VHDL20_DWPG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:31 350161
wst04-VHDL20_DWPG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 394534
wst04-VHDL20_DWPG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 356703
wst04-VHDL20_DWPG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 250192
wst04-VHDL20_DWPG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:31 356354
wst04-VHDL20_DWPG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 401580
wst04-VHDL20_DWPH_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:31:24 240533
wst04-VHDL20_DWPH_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:22 241001
wst04-VHDL20_DWPH_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:31 240225
wst04-VHDL20_DWPH_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:40 240225
wst04-VHDL20_DWPH_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:25 235589
wst04-VHDL20_DWPH_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:24 236017
wst04-VHDL20_DWPH_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:31 235633
wst04-VHDL20_DWPH_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:42 235642
wst04-VHDL20_DWSG_201800-2606201800-omedes--0.pdf 20-Jun-2026 18:30:11 362175
wst04-VHDL20_DWSG_210200-2606210200-omedes--0.pdf 21-Jun-2026 02:30:15 361029
wst04-VHDL20_DWSG_210400-2606210400-omedes--0.pdf 21-Jun-2026 05:00:11 360800
wst04-VHDL20_DWSG_210800-2606210800-omedes--0.pdf 21-Jun-2026 08:30:17 361943
wst04-VHDL20_DWSG_211800-2606211800-omedes--0.pdf 21-Jun-2026 18:31:20 364380
wst04-VHDL20_DWSG_220200-2606220200-omedes--0.pdf 22-Jun-2026 02:30:14 363798
wst04-VHDL20_DWSG_220400-2606220400-omedes--0.pdf 22-Jun-2026 05:00:11 363504
wst04-VHDL20_DWSG_220800-2606220800-omedes--0.pdf 22-Jun-2026 08:30:18 364375