Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_010600 01-Jun-2026 13:54:59 5577
FPDL13_DWMZ_310600 31-May-2026 13:35:51 4015
SXDL31_DWAV_010800 01-Jun-2026 08:17:18 12181
SXDL31_DWAV_011800 01-Jun-2026 16:38:29 6139
SXDL31_DWAV_310800 31-May-2026 09:40:29 12965
SXDL31_DWAV_311800 31-May-2026 16:44:19 6805
SXDL31_DWAV_LATEST 01-Jun-2026 16:38:29 6139
SXDL33_DWAV_010000 01-Jun-2026 09:17:23 8222
SXDL33_DWAV_310000 31-May-2026 10:32:22 7891
SXDL33_DWAV_LATEST 01-Jun-2026 09:17:23 8222
ber01-FWDL39_DWMS_011230-2606011230-dsw--0-ia5 01-Jun-2026 11:11:52 2019
ber01-FWDL39_DWMS_311230-2605311230-dsw--0-ia5 31-May-2026 12:14:32 1667
ber01-VHDL13_DWEG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:28:21 3051
ber01-VHDL13_DWEG_310800-2605310800-dsw--0-ia5 31-May-2026 08:28:11 3195
ber01-VHDL13_DWEH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:28:17 3227
ber01-VHDL13_DWEH_310800-2605310800-dsw--0-ia5 31-May-2026 08:28:17 3440
ber01-VHDL13_DWEI_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:28:17 3155
ber01-VHDL13_DWEI_310800-2605310800-dsw--0-ia5 31-May-2026 08:28:21 3241
ber01-VHDL13_DWHG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:08 2951
ber01-VHDL13_DWHG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:16 3530
ber01-VHDL13_DWHH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:06 2836
ber01-VHDL13_DWHH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:16 3131
ber01-VHDL13_DWLG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 2582
ber01-VHDL13_DWLG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3014
ber01-VHDL13_DWLH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 2561
ber01-VHDL13_DWLH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 2803
ber01-VHDL13_DWLI_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 2622
ber01-VHDL13_DWLI_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3018
ber01-VHDL13_DWMO_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 3499
ber01-VHDL13_DWMO_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3735
ber01-VHDL13_DWMP_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 3561
ber01-VHDL13_DWMP_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3700
ber01-VHDL13_DWOG_010300-2606010300-dsw--0-ia5 01-Jun-2026 03:00:10 3833
ber01-VHDL13_DWOG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 3379
ber01-VHDL13_DWOG_011700-2606011700-dsw--0-ia5 01-Jun-2026 18:00:01 3774
ber01-VHDL13_DWOG_310300-2605310300-dsw--0-ia5 31-May-2026 03:00:09 3671
ber01-VHDL13_DWOG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3764
ber01-VHDL13_DWOG_311700-2605311700-dsw--0-ia5 31-May-2026 18:00:07 3436
ber01-VHDL13_DWON_010004-2606010004-dsw--0-ia5 01-Jun-2026 00:04:11 3828
ber01-VHDL13_DWON_010135-2606010135-dsw--0-ia5 01-Jun-2026 01:36:04 3907
ber01-VHDL13_DWON_010137-2606010137-dsw--0-ia5 01-Jun-2026 01:37:28 3907
ber01-VHDL13_DWON_010243-2606010243-dsw--0-ia5 01-Jun-2026 02:43:17 3907
ber01-VHDL13_DWON_010519-2606010519-dsw--0-ia5 01-Jun-2026 05:19:43 3944
ber01-VHDL13_DWON_010524-2606010524-dsw--0-ia5 01-Jun-2026 05:24:27 3944
ber01-VHDL13_DWON_010558-2606010558-dsw--0-ia5 01-Jun-2026 05:58:52 3944
ber01-VHDL13_DWON_010732-2606010732-dsw--0-ia5 01-Jun-2026 07:32:48 3944
ber01-VHDL13_DWON_010823-2606010823-dsw--0-ia5 01-Jun-2026 08:23:51 3886
ber01-VHDL13_DWON_011454-2606011454-dsw--0-ia5 01-Jun-2026 14:54:42 3547
ber01-VHDL13_DWON_011645-2606011645-dsw--0-ia5 01-Jun-2026 16:45:32 3358
ber01-VHDL13_DWON_011831-2606011831-dsw--0-ia5 01-Jun-2026 18:32:04 3622
ber01-VHDL13_DWON_012138-2606012138-dsw--0-ia5 01-Jun-2026 21:38:47 3551
ber01-VHDL13_DWON_020006-2606020006-dsw--0-ia5 02-Jun-2026 00:06:07 3815
ber01-VHDL13_DWON_020127-2606020127-dsw--0-ia5 02-Jun-2026 01:27:41 3857
ber01-VHDL13_DWON_020128-2606020128-dsw--0-ia5 02-Jun-2026 01:28:16 3823
ber01-VHDL13_DWON_310525-2605310525-dsw--0-ia5 31-May-2026 05:25:23 3952
ber01-VHDL13_DWON_310526-2605310526-dsw--0-ia5 31-May-2026 05:26:17 3952
ber01-VHDL13_DWON_311314-2605311314-dsw--0-ia5 31-May-2026 13:14:51 3676
ber01-VHDL13_DWON_311730-2605311730-dsw--0-ia5 31-May-2026 17:30:06 3231
ber01-VHDL13_DWON_311731-2605311731-dsw--0-ia5 31-May-2026 17:31:12 3231
ber01-VHDL13_DWON_311848-2605311848-dsw--0-ia5 31-May-2026 18:48:22 3484
ber01-VHDL13_DWON_312137-2605312137-dsw--0-ia5 31-May-2026 21:37:27 3277
ber01-VHDL13_DWPG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 2812
ber01-VHDL13_DWPG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3294
ber01-VHDL13_DWPH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 2819
ber01-VHDL13_DWPH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 2848
ber01-VHDL13_DWSG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 3242
ber01-VHDL13_DWSG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 3381
ber01-VHDL17_DWOG_011200-2606011200-dsw--0-ia5 01-Jun-2026 10:53:57 2560
ber01-VHDL17_DWOG_311200-2605311200-dsw--0-ia5 31-May-2026 10:58:57 2648
swis2-VHDL20_DWEG_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:01 1229
swis2-VHDL20_DWEG_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:01:21 1223
swis2-VHDL20_DWEG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1444
swis2-VHDL20_DWEG_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 1772
swis2-VHDL20_DWEG_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:00 1556
swis2-VHDL20_DWEG_310400-2605310400-dsw--0-ia5 31-May-2026 05:01:27 1513
swis2-VHDL20_DWEG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 1817
swis2-VHDL20_DWEG_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:02 1906
swis2-VHDL20_DWEH_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:01 1247
swis2-VHDL20_DWEH_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:01:21 1244
swis2-VHDL20_DWEH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1464
swis2-VHDL20_DWEH_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 1767
swis2-VHDL20_DWEH_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:00 1803
swis2-VHDL20_DWEH_310400-2605310400-dsw--0-ia5 31-May-2026 05:01:27 1532
swis2-VHDL20_DWEH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 1837
swis2-VHDL20_DWEH_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:02 2082
swis2-VHDL20_DWEI_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:01 1258
swis2-VHDL20_DWEI_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:01:21 1255
swis2-VHDL20_DWEI_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1473
swis2-VHDL20_DWEI_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 1761
swis2-VHDL20_DWEI_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:00 1841
swis2-VHDL20_DWEI_310400-2605310400-dsw--0-ia5 31-May-2026 05:01:27 1454
swis2-VHDL20_DWEI_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 1756
swis2-VHDL20_DWEI_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:02 1426
swis2-VHDL20_DWHG_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:45:10 1332
swis2-VHDL20_DWHG_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:16 1329
swis2-VHDL20_DWHG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:45:04 1650
swis2-VHDL20_DWHG_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:45:01 1655
swis2-VHDL20_DWHG_310200-2605310200-dsw--0-ia5 31-May-2026 02:45:19 1457
swis2-VHDL20_DWHG_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:16 1597
swis2-VHDL20_DWHG_310800-2605310800-dsw--0-ia5 31-May-2026 08:45:04 1976
swis2-VHDL20_DWHG_311800-2605311800-dsw--0-ia5 31-May-2026 18:45:02 1967
swis2-VHDL20_DWHH_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:45:10 1334
swis2-VHDL20_DWHH_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:16 1334
swis2-VHDL20_DWHH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:45:04 1584
swis2-VHDL20_DWHH_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:45:01 1637
swis2-VHDL20_DWHH_310200-2605310200-dsw--0-ia5 31-May-2026 02:45:19 1228
swis2-VHDL20_DWHH_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:16 1247
swis2-VHDL20_DWHH_310800-2605310800-dsw--0-ia5 31-May-2026 08:45:04 1747
swis2-VHDL20_DWHH_311800-2605311800-dsw--0-ia5 31-May-2026 18:45:02 1732
swis2-VHDL20_DWLG_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:22 1214
swis2-VHDL20_DWLG_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:12 1021
swis2-VHDL20_DWLG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:21 1222
swis2-VHDL20_DWLG_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:31:01 1313
swis2-VHDL20_DWLG_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:23 1003
swis2-VHDL20_DWLG_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:12 1284
swis2-VHDL20_DWLG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:22 1370
swis2-VHDL20_DWLG_311800-2605311800-dsw--0-ia5 31-May-2026 18:31:05 1269
swis2-VHDL20_DWLH_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:22 1081
swis2-VHDL20_DWLH_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:12 1039
swis2-VHDL20_DWLH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:21 1265
swis2-VHDL20_DWLH_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:31:01 1274
swis2-VHDL20_DWLH_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:23 1240
swis2-VHDL20_DWLH_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:12 1276
swis2-VHDL20_DWLH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:22 1362
swis2-VHDL20_DWLH_311800-2605311800-dsw--0-ia5 31-May-2026 18:31:05 1227
swis2-VHDL20_DWLI_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:22 1253
swis2-VHDL20_DWLI_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:12 1044
swis2-VHDL20_DWLI_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:21 1179
swis2-VHDL20_DWLI_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:31:01 1347
swis2-VHDL20_DWLI_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:23 1244
swis2-VHDL20_DWLI_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:12 1361
swis2-VHDL20_DWLI_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:22 1446
swis2-VHDL20_DWLI_311800-2605311800-dsw--0-ia5 31-May-2026 18:31:05 1259
swis2-VHDL20_DWMO_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:06 1276
swis2-VHDL20_DWMO_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:06 1498
swis2-VHDL20_DWMO_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1649
swis2-VHDL20_DWMO_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 1969
swis2-VHDL20_DWMO_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:03 1430
swis2-VHDL20_DWMO_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:02 1570
swis2-VHDL20_DWMO_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 1932
swis2-VHDL20_DWMO_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:06 1624
swis2-VHDL20_DWMP_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:06 1579
swis2-VHDL20_DWMP_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:06 1606
swis2-VHDL20_DWMP_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1841
swis2-VHDL20_DWMP_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 2352
swis2-VHDL20_DWMP_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:03 1580
swis2-VHDL20_DWMP_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:02 1759
swis2-VHDL20_DWMP_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 2043
swis2-VHDL20_DWMP_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:06 1814
swis2-VHDL20_DWPG_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:22 1334
swis2-VHDL20_DWPG_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:12 1327
swis2-VHDL20_DWPG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:21 1471
swis2-VHDL20_DWPG_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:31:01 1517
swis2-VHDL20_DWPG_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:23 1334
swis2-VHDL20_DWPG_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:12 1704
swis2-VHDL20_DWPG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:22 1800
swis2-VHDL20_DWPG_311800-2605311800-dsw--0-ia5 31-May-2026 18:31:05 1232
swis2-VHDL20_DWPH_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:22 1307
swis2-VHDL20_DWPH_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:12 1330
swis2-VHDL20_DWPH_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:21 1454
swis2-VHDL20_DWPH_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:31:01 1540
swis2-VHDL20_DWPH_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:23 1353
swis2-VHDL20_DWPH_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:12 1204
swis2-VHDL20_DWPH_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:22 1304
swis2-VHDL20_DWPH_311800-2605311800-dsw--0-ia5 31-May-2026 18:31:05 1255
swis2-VHDL20_DWSG_010200-2606010200-dsw--0-ia5 01-Jun-2026 02:30:06 1847
swis2-VHDL20_DWSG_010400-2606010400-dsw--0-ia5 01-Jun-2026 05:00:18 1562
swis2-VHDL20_DWSG_010800-2606010800-dsw--0-ia5 01-Jun-2026 08:30:02 1850
swis2-VHDL20_DWSG_011800-2606011800-dsw--0-ia5 01-Jun-2026 18:30:01 1785
swis2-VHDL20_DWSG_020200-2606020200-dsw--0-ia5 02-Jun-2026 02:30:07 1324
swis2-VHDL20_DWSG_310400-2605310400-dsw--0-ia5 31-May-2026 05:00:16 1346
swis2-VHDL20_DWSG_310400_COR-2605310400-dsw--0-ia5 31-May-2026 06:19:41 1350
swis2-VHDL20_DWSG_310800-2605310800-dsw--0-ia5 31-May-2026 08:30:01 1622
swis2-VHDL20_DWSG_311800-2605311800-dsw--0-ia5 31-May-2026 18:30:02 1244
wst04-VHDL20_DWEG_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:14 243541
wst04-VHDL20_DWEG_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:12 242872
wst04-VHDL20_DWEG_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:12 244559
wst04-VHDL20_DWEG_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:12 246427
wst04-VHDL20_DWEG_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:11 245622
wst04-VHDL20_DWEG_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:12 242298
wst04-VHDL20_DWEG_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:16 243130
wst04-VHDL20_DWEG_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:12 244827
wst04-VHDL20_DWEH_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:14 245991
wst04-VHDL20_DWEH_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:16 245575
wst04-VHDL20_DWEH_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:12 247275
wst04-VHDL20_DWEH_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:12 244762
wst04-VHDL20_DWEH_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:11 244900
wst04-VHDL20_DWEH_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:12 248167
wst04-VHDL20_DWEH_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:16 248626
wst04-VHDL20_DWEH_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:12 247517
wst04-VHDL20_DWEI_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:16 352515
wst04-VHDL20_DWEI_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:16 351811
wst04-VHDL20_DWEI_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:17 352945
wst04-VHDL20_DWEI_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:16 351913
wst04-VHDL20_DWEI_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:11 351791
wst04-VHDL20_DWEI_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:12 350216
wst04-VHDL20_DWEI_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:16 351551
wst04-VHDL20_DWEI_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:17 352290
wst04-VHDL20_DWHG_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:45:10 358594
wst04-VHDL20_DWHG_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:16 358398
wst04-VHDL20_DWHG_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:45:13 360055
wst04-VHDL20_DWHG_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:45:11 350248
wst04-VHDL20_DWHG_310200-2605310200-omedes--0.pdf 31-May-2026 02:45:19 352645
wst04-VHDL20_DWHG_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:16 352506
wst04-VHDL20_DWHG_310800-2605310800-omedes--0.pdf 31-May-2026 08:45:12 354093
wst04-VHDL20_DWHG_311800-2605311800-omedes--0.pdf 31-May-2026 18:45:12 360842
wst04-VHDL20_DWHH_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:45:10 336768
wst04-VHDL20_DWHH_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:16 230953
wst04-VHDL20_DWHH_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:45:13 336834
wst04-VHDL20_DWHH_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:45:11 338849
wst04-VHDL20_DWHH_310200-2605310200-omedes--0.pdf 31-May-2026 02:45:19 339195
wst04-VHDL20_DWHH_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:16 234308
wst04-VHDL20_DWHH_310800-2605310800-omedes--0.pdf 31-May-2026 08:45:12 340177
wst04-VHDL20_DWHH_311800-2605311800-omedes--0.pdf 31-May-2026 18:45:12 338314
wst04-VHDL20_DWLG_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:22 350791
wst04-VHDL20_DWLG_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:42 349742
wst04-VHDL20_DWLG_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:47 350031
wst04-VHDL20_DWLG_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:31:24 351106
wst04-VHDL20_DWLG_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:28 350663
wst04-VHDL20_DWLG_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:42 347040
wst04-VHDL20_DWLG_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:46 347105
wst04-VHDL20_DWLG_311800-2605311800-omedes--0.pdf 31-May-2026 18:31:22 351135
wst04-VHDL20_DWLH_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:26 352782
wst04-VHDL20_DWLH_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:42 351947
wst04-VHDL20_DWLH_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:42 352281
wst04-VHDL20_DWLH_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:31:24 339757
wst04-VHDL20_DWLH_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:23 339462
wst04-VHDL20_DWLH_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:42 343703
wst04-VHDL20_DWLH_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:46 343726
wst04-VHDL20_DWLH_311800-2605311800-omedes--0.pdf 31-May-2026 18:31:28 352582
wst04-VHDL20_DWLI_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:22 353613
wst04-VHDL20_DWLI_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:42 352560
wst04-VHDL20_DWLI_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:47 397342
wst04-VHDL20_DWLI_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:31:24 345527
wst04-VHDL20_DWLI_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:23 345338
wst04-VHDL20_DWLI_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:42 354352
wst04-VHDL20_DWLI_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:46 398981
wst04-VHDL20_DWLI_311800-2605311800-omedes--0.pdf 31-May-2026 18:31:28 353860
wst04-VHDL20_DWMO_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:16 476387
wst04-VHDL20_DWMO_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:12 477099
wst04-VHDL20_DWMO_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:17 476808
wst04-VHDL20_DWMO_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:16 363036
wst04-VHDL20_DWMO_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:17 475653
wst04-VHDL20_DWMO_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:16 475262
wst04-VHDL20_DWMO_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:22 474537
wst04-VHDL20_DWMO_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:17 365498
wst04-VHDL20_DWMP_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:16 604698
wst04-VHDL20_DWMP_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:22 603796
wst04-VHDL20_DWMP_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:23 489931
wst04-VHDL20_DWMP_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:16 483047
wst04-VHDL20_DWMP_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:17 597942
wst04-VHDL20_DWMP_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:22 603218
wst04-VHDL20_DWMP_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:22 487736
wst04-VHDL20_DWMP_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:20 490263
wst04-VHDL20_DWPG_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:22 245288
wst04-VHDL20_DWPG_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:32 352019
wst04-VHDL20_DWPG_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:42 397514
wst04-VHDL20_DWPG_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:31:28 347003
wst04-VHDL20_DWPG_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:23 243610
wst04-VHDL20_DWPG_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:32 339378
wst04-VHDL20_DWPG_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:46 383673
wst04-VHDL20_DWPG_311800-2605311800-omedes--0.pdf 31-May-2026 18:31:22 351199
wst04-VHDL20_DWPH_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:22 247009
wst04-VHDL20_DWPH_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:32 246930
wst04-VHDL20_DWPH_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:42 247043
wst04-VHDL20_DWPH_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:31:24 244924
wst04-VHDL20_DWPH_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:23 244708
wst04-VHDL20_DWPH_310400-2605310400-omedes--0.pdf 31-May-2026 05:00:32 241652
wst04-VHDL20_DWPH_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:46 241492
wst04-VHDL20_DWPH_311800-2605311800-omedes--0.pdf 31-May-2026 18:31:22 246377
wst04-VHDL20_DWSG_010200-2606010200-omedes--0.pdf 01-Jun-2026 02:30:14 357447
wst04-VHDL20_DWSG_010400-2606010400-omedes--0.pdf 01-Jun-2026 05:00:12 356541
wst04-VHDL20_DWSG_010800-2606010800-omedes--0.pdf 01-Jun-2026 08:30:17 357968
wst04-VHDL20_DWSG_011800-2606011800-omedes--0.pdf 01-Jun-2026 18:30:16 358971
wst04-VHDL20_DWSG_020200-2606020200-omedes--0.pdf 02-Jun-2026 02:30:11 356939
wst04-VHDL20_DWSG_310400-2605310400-omedes--0.pdf 31-May-2026 06:19:51 359729
wst04-VHDL20_DWSG_310800-2605310800-omedes--0.pdf 31-May-2026 08:30:16 360766
wst04-VHDL20_DWSG_311800-2605311800-omedes--0.pdf 31-May-2026 18:30:12 354672