Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jan-2026 13:48:13 6165
FPDL13_DWMZ_200600 20-Jan-2026 13:04:59 3859
SXDL31_DWAV_190800 19-Jan-2026 07:42:49 12185
SXDL31_DWAV_191800 19-Jan-2026 17:19:20 8217
SXDL31_DWAV_200800 20-Jan-2026 07:47:24 13914
SXDL31_DWAV_201800 20-Jan-2026 17:31:52 10703
SXDL31_DWAV_LATEST 20-Jan-2026 17:31:52 10703
SXDL33_DWAV_190000 19-Jan-2026 10:59:53 5684
SXDL33_DWAV_200000 20-Jan-2026 11:30:26 25457
SXDL33_DWAV_LATEST 20-Jan-2026 11:30:26 25457
ber01-FWDL39_DWMS_191230-2601191230-dsw--0-ia5 19-Jan-2026 12:33:10 1328
ber01-FWDL39_DWMS_201230-2601201230-dsw--0-ia5 20-Jan-2026 11:42:38 830
ber01-VHDL13_DWEH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:11 3271
ber01-VHDL13_DWEH_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:12 3026
ber01-VHDL13_DWEH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:16 2674
ber01-VHDL13_DWEH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:28:17 2487
ber01-VHDL13_DWEH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:28:16 3085
ber01-VHDL13_DWEH_200400-2601200400-dsw--0-ia5 20-Jan-2026 05:58:11 3026
ber01-VHDL13_DWEH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:28:17 2800
ber01-VHDL13_DWEH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:28:17 2711
ber01-VHDL13_DWHG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2558
ber01-VHDL13_DWHG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2564
ber01-VHDL13_DWHG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2634
ber01-VHDL13_DWHG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2624
ber01-VHDL13_DWHG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2697
ber01-VHDL13_DWHG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2697
ber01-VHDL13_DWHG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:16 2986
ber01-VHDL13_DWHG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2832
ber01-VHDL13_DWHH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2559
ber01-VHDL13_DWHH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2559
ber01-VHDL13_DWHH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2483
ber01-VHDL13_DWHH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2343
ber01-VHDL13_DWHH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2573
ber01-VHDL13_DWHH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2573
ber01-VHDL13_DWHH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 3060
ber01-VHDL13_DWHH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2864
ber01-VHDL13_DWLG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 2898
ber01-VHDL13_DWLG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 2792
ber01-VHDL13_DWLG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2594
ber01-VHDL13_DWLG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2476
ber01-VHDL13_DWLG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2622
ber01-VHDL13_DWLG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2734
ber01-VHDL13_DWLG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:16 2558
ber01-VHDL13_DWLG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2313
ber01-VHDL13_DWLH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1801
ber01-VHDL13_DWLH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1825
ber01-VHDL13_DWLH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1696
ber01-VHDL13_DWLH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 1635
ber01-VHDL13_DWLH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 1776
ber01-VHDL13_DWLH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 1721
ber01-VHDL13_DWLH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 1657
ber01-VHDL13_DWLH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 1652
ber01-VHDL13_DWLI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1579
ber01-VHDL13_DWLI_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1566
ber01-VHDL13_DWLI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1437
ber01-VHDL13_DWLI_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 1512
ber01-VHDL13_DWLI_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 1680
ber01-VHDL13_DWLI_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 1671
ber01-VHDL13_DWLI_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 1612
ber01-VHDL13_DWLI_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 1627
ber01-VHDL13_DWMG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 3180
ber01-VHDL13_DWMG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 3251
ber01-VHDL13_DWMG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3527
ber01-VHDL13_DWMG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:19:01 3629
ber01-VHDL13_DWMG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2743
ber01-VHDL13_DWMG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2887
ber01-VHDL13_DWMG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2895
ber01-VHDL13_DWMG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:16 2580
ber01-VHDL13_DWMG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2783
ber01-VHDL13_DWMO_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 2618
ber01-VHDL13_DWMO_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 2618
ber01-VHDL13_DWMO_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 2632
ber01-VHDL13_DWMO_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2454
ber01-VHDL13_DWMO_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2953
ber01-VHDL13_DWMO_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2961
ber01-VHDL13_DWMO_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 2651
ber01-VHDL13_DWMO_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2741
ber01-VHDL13_DWMP_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 3160
ber01-VHDL13_DWMP_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:02 3233
ber01-VHDL13_DWMP_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3415
ber01-VHDL13_DWMP_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:20:41 3516
ber01-VHDL13_DWMP_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2863
ber01-VHDL13_DWMP_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 3013
ber01-VHDL13_DWMP_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 3021
ber01-VHDL13_DWMP_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 2768
ber01-VHDL13_DWMP_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 3055
ber01-VHDL13_DWOG_190300-2601190300-dsw--0-ia5 19-Jan-2026 04:00:03 4833
ber01-VHDL13_DWOG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 4768
ber01-VHDL13_DWOG_191700-2601191700-dsw--0-ia5 19-Jan-2026 19:00:14 4565
ber01-VHDL13_DWOG_200300-2601200300-dsw--0-ia5 20-Jan-2026 04:00:01 4772
ber01-VHDL13_DWOG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:16 4362
ber01-VHDL13_DWOG_201700-2601201700-dsw--0-ia5 20-Jan-2026 19:00:14 5198
ber01-VHDL13_DWOH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:17 2994
ber01-VHDL13_DWOH_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:12 2912
ber01-VHDL13_DWOH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:16 2639
ber01-VHDL13_DWOH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:28:12 2291
ber01-VHDL13_DWOH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:28:12 2634
ber01-VHDL13_DWOH_200400-2601200400-dsw--0-ia5 20-Jan-2026 05:58:17 2633
ber01-VHDL13_DWOH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:28:17 2365
ber01-VHDL13_DWOH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:28:21 2126
ber01-VHDL13_DWOI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:28:11 3416
ber01-VHDL13_DWOI_190400-2601190400-dsw--0-ia5 19-Jan-2026 05:58:15 3109
ber01-VHDL13_DWOI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:28:12 2563
ber01-VHDL13_DWOI_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:28:12 2360
ber01-VHDL13_DWOI_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:28:12 2829
ber01-VHDL13_DWOI_200400-2601200400-dsw--0-ia5 20-Jan-2026 05:58:17 2778
ber01-VHDL13_DWOI_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:28:11 2670
ber01-VHDL13_DWOI_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:28:17 2268
ber01-VHDL13_DWON_190313-2601190313-dsw--0-ia5 19-Jan-2026 03:13:54 3464
ber01-VHDL13_DWON_190629-2601190629-dsw--0-ia5 19-Jan-2026 06:29:52 4068
ber01-VHDL13_DWON_190720-2601190720-dsw--0-ia5 19-Jan-2026 07:20:11 4061
ber01-VHDL13_DWON_190928-2601190928-dsw--0-ia5 19-Jan-2026 09:28:37 4061
ber01-VHDL13_DWON_190954-2601190954-dsw--0-ia5 19-Jan-2026 09:54:46 4061
ber01-VHDL13_DWON_191545-2601191545-dsw--0-ia5 19-Jan-2026 15:45:41 3372
ber01-VHDL13_DWON_191747-2601191747-dsw--0-ia5 19-Jan-2026 17:47:06 3428
ber01-VHDL13_DWON_192253-2601192253-dsw--0-ia5 19-Jan-2026 22:53:32 3501
ber01-VHDL13_DWON_200234-2601200234-dsw--0-ia5 20-Jan-2026 02:35:15 3631
ber01-VHDL13_DWON_200627-2601200627-dsw--0-ia5 20-Jan-2026 06:27:52 3680
ber01-VHDL13_DWON_200926-2601200926-dsw--0-ia5 20-Jan-2026 09:26:58 4413
ber01-VHDL13_DWON_201541-2601201541-dsw--0-ia5 20-Jan-2026 15:42:59 3760
ber01-VHDL13_DWON_201815-2601201815-dsw--0-ia5 20-Jan-2026 18:15:14 3760
ber01-VHDL13_DWON_201826-2601201826-dsw--0-ia5 20-Jan-2026 18:26:32 3755
ber01-VHDL13_DWON_201828-2601201828-dsw--0-ia5 20-Jan-2026 18:28:41 3755
ber01-VHDL13_DWPG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1719
ber01-VHDL13_DWPG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1723
ber01-VHDL13_DWPG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1580
ber01-VHDL13_DWPG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 1515
ber01-VHDL13_DWPG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 1780
ber01-VHDL13_DWPG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 1843
ber01-VHDL13_DWPG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:16 1966
ber01-VHDL13_DWPG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 1908
ber01-VHDL13_DWPH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:07 1942
ber01-VHDL13_DWPH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:07 1911
ber01-VHDL13_DWPH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 1769
ber01-VHDL13_DWPH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 1922
ber01-VHDL13_DWPH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2299
ber01-VHDL13_DWPH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2467
ber01-VHDL13_DWPH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 2583
ber01-VHDL13_DWPH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2703
ber01-VHDL13_DWSG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:30:01 2829
ber01-VHDL13_DWSG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 3111
ber01-VHDL13_DWSG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:30:15 3184
ber01-VHDL13_DWSG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:48:52 3466
ber01-VHDL13_DWSG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:30:15 2912
ber01-VHDL13_DWSG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:30:15 2800
ber01-VHDL13_DWSG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2802
ber01-VHDL13_DWSG_200400_COR-2601200400-dsw--0-ia5 20-Jan-2026 06:21:01 3064
ber01-VHDL13_DWSG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:30:15 3061
ber01-VHDL13_DWSG_200800_COR-2601200800-dsw--0-ia5 20-Jan-2026 11:37:56 3012
ber01-VHDL13_DWSG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:30:15 2928
ber01-VHDL17_DWOG_191200-2601191200-dsw--0-ia5 19-Jan-2026 12:16:57 2707
ber01-VHDL17_DWOG_201200-2601201200-dsw--0-ia5 20-Jan-2026 12:47:02 3199
swis2-VHDL20_DWEG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3372
swis2-VHDL20_DWEG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3325
swis2-VHDL20_DWEG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3256
swis2-VHDL20_DWEG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2716
swis2-VHDL20_DWEG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 3009
swis2-VHDL20_DWEG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 2996
swis2-VHDL20_DWEG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 2928
swis2-VHDL20_DWEG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 2498
swis2-VHDL20_DWEH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3669
swis2-VHDL20_DWEH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3259
swis2-VHDL20_DWEH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3296
swis2-VHDL20_DWEH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2916
swis2-VHDL20_DWEH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 3480
swis2-VHDL20_DWEH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3434
swis2-VHDL20_DWEH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3488
swis2-VHDL20_DWEH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3142
swis2-VHDL20_DWEI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3836
swis2-VHDL20_DWEI_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3422
swis2-VHDL20_DWEI_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3229
swis2-VHDL20_DWEI_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2768
swis2-VHDL20_DWEI_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:15 3177
swis2-VHDL20_DWEI_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3198
swis2-VHDL20_DWEI_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3306
swis2-VHDL20_DWEI_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 2688
swis2-VHDL20_DWHG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 2744
swis2-VHDL20_DWHG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2747
swis2-VHDL20_DWHG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3244
swis2-VHDL20_DWHG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2807
swis2-VHDL20_DWHG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2883
swis2-VHDL20_DWHG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2880
swis2-VHDL20_DWHG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3590
swis2-VHDL20_DWHG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3015
swis2-VHDL20_DWHH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 2745
swis2-VHDL20_DWHH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:11 2745
swis2-VHDL20_DWHH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3104
swis2-VHDL20_DWHH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2529
swis2-VHDL20_DWHH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2759
swis2-VHDL20_DWHH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2759
swis2-VHDL20_DWHH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3682
swis2-VHDL20_DWHH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3050
swis2-VHDL20_DWLG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 3252
swis2-VHDL20_DWLG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 3132
swis2-VHDL20_DWLG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3078
swis2-VHDL20_DWLG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2819
swis2-VHDL20_DWLG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:15 2965
swis2-VHDL20_DWLG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 3077
swis2-VHDL20_DWLG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3109
swis2-VHDL20_DWLG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 2656
swis2-VHDL20_DWLH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 2162
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swis2-VHDL20_DWLH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2191
swis2-VHDL20_DWLH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 1985
swis2-VHDL20_DWLH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2126
swis2-VHDL20_DWLH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2071
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swis2-VHDL20_DWLI_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 1935
swis2-VHDL20_DWLI_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 1908
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swis2-VHDL20_DWLI_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 1857
swis2-VHDL20_DWLI_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2025
swis2-VHDL20_DWLI_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2016
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swis2-VHDL20_DWMG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3694
swis2-VHDL20_DWMG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:02 3676
swis2-VHDL20_DWMG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 4161
swis2-VHDL20_DWMG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 3160
swis2-VHDL20_DWMG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 3286
swis2-VHDL20_DWMG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3292
swis2-VHDL20_DWMG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3134
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swis2-VHDL20_DWMO_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3128
swis2-VHDL20_DWMO_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:02 3057
swis2-VHDL20_DWMO_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3272
swis2-VHDL20_DWMO_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2882
swis2-VHDL20_DWMO_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 3354
swis2-VHDL20_DWMO_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3362
swis2-VHDL20_DWMO_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3216
swis2-VHDL20_DWMO_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3183
swis2-VHDL20_DWMP_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:07 3679
swis2-VHDL20_DWMP_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:07 3657
swis2-VHDL20_DWMP_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 4052
swis2-VHDL20_DWMP_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 3267
swis2-VHDL20_DWMP_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:15 3413
swis2-VHDL20_DWMP_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3418
swis2-VHDL20_DWMP_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3331
swis2-VHDL20_DWMP_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3490
swis2-VHDL20_DWPG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 2068
swis2-VHDL20_DWPG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 2050
swis2-VHDL20_DWPG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2041
swis2-VHDL20_DWPG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 1976
swis2-VHDL20_DWPG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2110
swis2-VHDL20_DWPG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2170
swis2-VHDL20_DWPG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 2445
swis2-VHDL20_DWPG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 2387
swis2-VHDL20_DWPH_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:05 2289
swis2-VHDL20_DWPH_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:00:18 2240
swis2-VHDL20_DWPH_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 2230
swis2-VHDL20_DWPH_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 2383
swis2-VHDL20_DWPH_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 2628
swis2-VHDL20_DWPH_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:00:16 2796
swis2-VHDL20_DWPH_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3064
swis2-VHDL20_DWPH_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3184
swis2-VHDL20_DWSG_190200-2601190200-dsw--0-ia5 19-Jan-2026 03:45:02 3312
swis2-VHDL20_DWSG_190400-2601190400-dsw--0-ia5 19-Jan-2026 06:15:02 3519
swis2-VHDL20_DWSG_190800-2601190800-dsw--0-ia5 19-Jan-2026 09:45:15 3892
swis2-VHDL20_DWSG_190800_COR-2601190800-dsw--0-ia5 19-Jan-2026 10:48:52 3696
swis2-VHDL20_DWSG_191300-2601191300-dsw--0-ia5 19-Jan-2026 14:45:21 3958
swis2-VHDL20_DWSG_191800-2601191800-dsw--0-ia5 19-Jan-2026 19:45:15 3340
swis2-VHDL20_DWSG_200200-2601200200-dsw--0-ia5 20-Jan-2026 03:45:14 3174
swis2-VHDL20_DWSG_200400-2601200400-dsw--0-ia5 20-Jan-2026 06:15:14 3136
swis2-VHDL20_DWSG_200400_COR-2601200400-dsw--0-ia5 20-Jan-2026 06:21:01 3432
swis2-VHDL20_DWSG_200800-2601200800-dsw--0-ia5 20-Jan-2026 09:45:14 3591
swis2-VHDL20_DWSG_200800_COR-2601200800-dsw--0-ia5 20-Jan-2026 11:37:56 3542
swis2-VHDL20_DWSG_201300-2601201300-dsw--0-ia5 20-Jan-2026 14:45:28 3440
swis2-VHDL20_DWSG_201800-2601201800-dsw--0-ia5 20-Jan-2026 19:45:15 3298
wst04-VHDL20_DWEG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 229525
wst04-VHDL20_DWEG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 228992
wst04-VHDL20_DWEG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:21 227519
wst04-VHDL20_DWEG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:15 225530
wst04-VHDL20_DWEG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:14 226293
wst04-VHDL20_DWEG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:22 225834
wst04-VHDL20_DWEG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:27 223383
wst04-VHDL20_DWEG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:15 222285
wst04-VHDL20_DWEH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 229783
wst04-VHDL20_DWEH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:27 228999
wst04-VHDL20_DWEH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:21 226731
wst04-VHDL20_DWEH_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:15 225424
wst04-VHDL20_DWEH_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:17 226808
wst04-VHDL20_DWEH_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:22 226340
wst04-VHDL20_DWEH_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:21 226564
wst04-VHDL20_DWEH_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:17 225393
wst04-VHDL20_DWEI_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 324569
wst04-VHDL20_DWEI_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:27 324293
wst04-VHDL20_DWEI_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:27 321937
wst04-VHDL20_DWEI_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:15 321139
wst04-VHDL20_DWEI_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:23 321307
wst04-VHDL20_DWEI_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:22 321236
wst04-VHDL20_DWEI_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:27 310895
wst04-VHDL20_DWEI_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:17 309774
wst04-VHDL20_DWHG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 310945
wst04-VHDL20_DWHG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:11 310970
wst04-VHDL20_DWHG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 306774
wst04-VHDL20_DWHG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 305492
wst04-VHDL20_DWHG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:15 305611
wst04-VHDL20_DWHG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:16 305657
wst04-VHDL20_DWHG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:17 307216
wst04-VHDL20_DWHG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:15 305948
wst04-VHDL20_DWHH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 295642
wst04-VHDL20_DWHH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:11 295754
wst04-VHDL20_DWHH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 294363
wst04-VHDL20_DWHH_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:17 293549
wst04-VHDL20_DWHH_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:14 293267
wst04-VHDL20_DWHH_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:16 293273
wst04-VHDL20_DWHH_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:14 295039
wst04-VHDL20_DWHH_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:15 294315
wst04-VHDL20_DWLG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 304604
wst04-VHDL20_DWLG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 304757
wst04-VHDL20_DWLG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 311428
wst04-VHDL20_DWLG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 311117
wst04-VHDL20_DWLG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:27 312385
wst04-VHDL20_DWLG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:42 311415
wst04-VHDL20_DWLG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:27 309780
wst04-VHDL20_DWLG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:27 309352
wst04-VHDL20_DWLH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:27 309917
wst04-VHDL20_DWLH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 309868
wst04-VHDL20_DWLH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:25 309700
wst04-VHDL20_DWLH_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 309613
wst04-VHDL20_DWLH_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:27 310449
wst04-VHDL20_DWLH_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:42 309961
wst04-VHDL20_DWLH_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:31 300158
wst04-VHDL20_DWLH_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:27 299957
wst04-VHDL20_DWLI_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 317542
wst04-VHDL20_DWLI_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:41 317501
wst04-VHDL20_DWLI_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 320680
wst04-VHDL20_DWLI_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 320752
wst04-VHDL20_DWLI_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:21 321571
wst04-VHDL20_DWLI_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:42 321117
wst04-VHDL20_DWLI_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:31 307495
wst04-VHDL20_DWLI_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:27 307310
wst04-VHDL20_DWMG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 539642
wst04-VHDL20_DWMG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 539622
wst04-VHDL20_DWMG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 535821
wst04-VHDL20_DWMG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 534404
wst04-VHDL20_DWMG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:17 533936
wst04-VHDL20_DWMG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:22 533812
wst04-VHDL20_DWMG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:17 527644
wst04-VHDL20_DWMG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:21 526844
wst04-VHDL20_DWMO_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:17 433738
wst04-VHDL20_DWMO_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:17 434196
wst04-VHDL20_DWMO_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:15 432968
wst04-VHDL20_DWMO_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:17 432221
wst04-VHDL20_DWMO_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:17 432651
wst04-VHDL20_DWMO_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:16 433166
wst04-VHDL20_DWMO_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:17 418306
wst04-VHDL20_DWMO_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:15 418067
wst04-VHDL20_DWMP_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 559287
wst04-VHDL20_DWMP_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:21 560373
wst04-VHDL20_DWMP_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:17 550681
wst04-VHDL20_DWMP_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:17 549650
wst04-VHDL20_DWMP_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:21 548202
wst04-VHDL20_DWMP_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:16 549253
wst04-VHDL20_DWMP_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:17 551121
wst04-VHDL20_DWMP_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:17 550141
wst04-VHDL20_DWPG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:27 307796
wst04-VHDL20_DWPG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:31 307747
wst04-VHDL20_DWPG_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:31 349755
wst04-VHDL20_DWPG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:27 305235
wst04-VHDL20_DWPG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:21 305945
wst04-VHDL20_DWPG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:32 305629
wst04-VHDL20_DWPG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:31 349051
wst04-VHDL20_DWPG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:31 303697
wst04-VHDL20_DWPH_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:21 222509
wst04-VHDL20_DWPH_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:00:31 222355
wst04-VHDL20_DWPH_190800-2601190800-omedes--0.pdf 19-Jan-2026 09:45:25 266033
wst04-VHDL20_DWPH_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:21 266294
wst04-VHDL20_DWPH_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:21 222421
wst04-VHDL20_DWPH_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:00:32 222524
wst04-VHDL20_DWPH_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:27 267514
wst04-VHDL20_DWPH_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:21 267163
wst04-VHDL20_DWSG_190200-2601190200-omedes--0.pdf 19-Jan-2026 03:45:11 339227
wst04-VHDL20_DWSG_190400-2601190400-omedes--0.pdf 19-Jan-2026 06:15:11 339682
wst04-VHDL20_DWSG_190800-2601190800-omedes--0.pdf 19-Jan-2026 10:49:03 328862
wst04-VHDL20_DWSG_191300-2601191300-omedes--0.pdf 19-Jan-2026 14:45:21 329535
wst04-VHDL20_DWSG_191800-2601191800-omedes--0.pdf 19-Jan-2026 19:45:15 328567
wst04-VHDL20_DWSG_200200-2601200200-omedes--0.pdf 20-Jan-2026 03:45:15 328328
wst04-VHDL20_DWSG_200400-2601200400-omedes--0.pdf 20-Jan-2026 06:15:14 328757
wst04-VHDL20_DWSG_200400_COR-2601200400-omedes-..> 20-Jan-2026 06:21:12 329893
wst04-VHDL20_DWSG_200800-2601200800-omedes--0.pdf 20-Jan-2026 09:45:14 323951
wst04-VHDL20_DWSG_200800_COR-2601200800-omedes-..> 20-Jan-2026 11:38:09 323892
wst04-VHDL20_DWSG_201300-2601201300-omedes--0.pdf 20-Jan-2026 14:45:28 323339
wst04-VHDL20_DWSG_201800-2601201800-omedes--0.pdf 20-Jan-2026 19:45:15 323436