Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_300600 30-Jul-2026 13:13:54 5536
FPDL13_DWMZ_310600 31-Jul-2026 14:14:29 5150
SXDL31_DWAV_300800 30-Jul-2026 08:24:38 8868
SXDL31_DWAV_301800 30-Jul-2026 16:14:21 3931
SXDL31_DWAV_310800 31-Jul-2026 07:35:06 13148
SXDL31_DWAV_LATEST 31-Jul-2026 07:35:06 13148
SXDL33_DWAV_300000 30-Jul-2026 09:43:43 21627
SXDL33_DWAV_310000 31-Jul-2026 09:35:34 7685
SXDL33_DWAV_LATEST 31-Jul-2026 09:35:34 7685
ber01-FWDL39_DWMS_301200-2607301200-dsw--0-ia5 30-Jul-2026 11:02:17 2011
ber01-FWDL39_DWMS_311200-2607311200-dsw--0-ia5 31-Jul-2026 11:41:47 2333
ber01-VHDL13_DWEG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:27 4849
ber01-VHDL13_DWEG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:28:27 3867
ber01-VHDL13_DWEH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:21 4847
ber01-VHDL13_DWEH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:28:21 2749
ber01-VHDL13_DWEI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:28:21 4705
ber01-VHDL13_DWEI_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:28:11 3822
ber01-VHDL13_DWHG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4199
ber01-VHDL13_DWHG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3567
ber01-VHDL13_DWHH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4142
ber01-VHDL13_DWHH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3133
ber01-VHDL13_DWLG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 4155
ber01-VHDL13_DWLG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3259
ber01-VHDL13_DWLH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4045
ber01-VHDL13_DWLH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 2879
ber01-VHDL13_DWLI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4065
ber01-VHDL13_DWLI_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3250
ber01-VHDL13_DWMO_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4078
ber01-VHDL13_DWMO_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 2818
ber01-VHDL13_DWMP_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 3972
ber01-VHDL13_DWMP_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:45:51 3600
ber01-VHDL13_DWMP_310800_COR-2607310800-dsw--0-ia5 31-Jul-2026 08:43:16 3604
ber01-VHDL13_DWOG_291700-2607291700-dsw--0-ia5 29-Jul-2026 18:00:07 3823
ber01-VHDL13_DWOG_300300-2607300300-dsw--0-ia5 30-Jul-2026 03:00:04 4299
ber01-VHDL13_DWOG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4250
ber01-VHDL13_DWOG_301700-2607301700-dsw--0-ia5 30-Jul-2026 18:00:08 3919
ber01-VHDL13_DWOG_310300-2607310300-dsw--0-ia5 31-Jul-2026 03:00:03 5054
ber01-VHDL13_DWOG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 4431
ber01-VHDL13_DWON_291722-2607291722-dsw--0-ia5 29-Jul-2026 17:22:21 3463
ber01-VHDL13_DWON_292214-2607292214-dsw--0-ia5 29-Jul-2026 22:14:23 4012
ber01-VHDL13_DWON_300054-2607300054-dsw--0-ia5 30-Jul-2026 00:54:56 4012
ber01-VHDL13_DWON_300239-2607300239-dsw--0-ia5 30-Jul-2026 02:39:34 4043
ber01-VHDL13_DWON_300530-2607300530-dsw--0-ia5 30-Jul-2026 05:31:01 4043
ber01-VHDL13_DWON_300612-2607300612-dsw--0-ia5 30-Jul-2026 06:12:16 3939
ber01-VHDL13_DWON_300849-2607300849-dsw--0-ia5 30-Jul-2026 08:49:33 3939
ber01-VHDL13_DWON_301103-2607301103-dsw--0-ia5 30-Jul-2026 11:03:11 3939
ber01-VHDL13_DWON_301534-2607301534-dsw--0-ia5 30-Jul-2026 15:34:51 3270
ber01-VHDL13_DWON_301719-2607301719-dsw--0-ia5 30-Jul-2026 17:19:07 3329
ber01-VHDL13_DWON_301804-2607301804-dsw--0-ia5 30-Jul-2026 18:04:57 3329
ber01-VHDL13_DWON_302052-2607302052-dsw--0-ia5 30-Jul-2026 20:52:58 3900
ber01-VHDL13_DWON_302059-2607302059-dsw--0-ia5 30-Jul-2026 20:59:11 3900
ber01-VHDL13_DWON_302145-2607302145-dsw--0-ia5 30-Jul-2026 21:45:30 3896
ber01-VHDL13_DWON_310009-2607310009-dsw--0-ia5 31-Jul-2026 00:09:41 4339
ber01-VHDL13_DWON_310140-2607310140-dsw--0-ia5 31-Jul-2026 01:40:43 4617
ber01-VHDL13_DWON_310249-2607310249-dsw--0-ia5 31-Jul-2026 02:50:15 4589
ber01-VHDL13_DWON_310530-2607310530-dsw--0-ia5 31-Jul-2026 05:30:12 3591
ber01-VHDL13_DWON_310621-2607310621-dsw--0-ia5 31-Jul-2026 06:21:41 3898
ber01-VHDL13_DWON_310719-2607310719-dsw--0-ia5 31-Jul-2026 07:19:22 3898
ber01-VHDL13_DWON_311327-2607311327-dsw--0-ia5 31-Jul-2026 13:28:01 3605
ber01-VHDL13_DWPG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 4129
ber01-VHDL13_DWPG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3253
ber01-VHDL13_DWPH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 4181
ber01-VHDL13_DWPH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 2698
ber01-VHDL13_DWSG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:17 3854
ber01-VHDL13_DWSG_300800_COR-2607300800-dsw--0-ia5 30-Jul-2026 14:29:57 4076
ber01-VHDL13_DWSG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 3205
ber01-VHDL17_DWOG_301200-2607301200-dsw--0-ia5 30-Jul-2026 10:51:21 3321
ber01-VHDL17_DWOG_311200-2607311200-dsw--0-ia5 31-Jul-2026 11:55:10 2860
swis2-VHDL20_DWEG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2669
swis2-VHDL20_DWEG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2201
swis2-VHDL20_DWEG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2202
swis2-VHDL20_DWEG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2524
swis2-VHDL20_DWEG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2034
swis2-VHDL20_DWEG_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1851
swis2-VHDL20_DWEG_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:02:22 1673
swis2-VHDL20_DWEG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 1961
swis2-VHDL20_DWEH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2685
swis2-VHDL20_DWEH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2301
swis2-VHDL20_DWEH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2302
swis2-VHDL20_DWEH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2545
swis2-VHDL20_DWEH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 1485
swis2-VHDL20_DWEH_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1361
swis2-VHDL20_DWEH_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:02:22 1027
swis2-VHDL20_DWEH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 1345
swis2-VHDL20_DWEI_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 2536
swis2-VHDL20_DWEI_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 2098
swis2-VHDL20_DWEI_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:02:21 2099
swis2-VHDL20_DWEI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2405
swis2-VHDL20_DWEI_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2051
swis2-VHDL20_DWEI_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1856
swis2-VHDL20_DWEI_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:02:22 1754
swis2-VHDL20_DWEI_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 2054
swis2-VHDL20_DWHG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:45:13 2307
swis2-VHDL20_DWHG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:45:37 2284
swis2-VHDL20_DWHG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 2364
swis2-VHDL20_DWHG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:45:57 2586
swis2-VHDL20_DWHG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:45:05 2216
swis2-VHDL20_DWHG_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:47:03 1754
swis2-VHDL20_DWHG_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:22 1751
swis2-VHDL20_DWHG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:45:25 1975
swis2-VHDL20_DWHH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:45:13 2410
swis2-VHDL20_DWHH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:45:37 2373
swis2-VHDL20_DWHH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 2394
swis2-VHDL20_DWHH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:45:57 2627
swis2-VHDL20_DWHH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:45:05 1730
swis2-VHDL20_DWHH_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:47:03 1371
swis2-VHDL20_DWHH_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:22 1371
swis2-VHDL20_DWHH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:45:25 1681
swis2-VHDL20_DWLG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2223
swis2-VHDL20_DWLG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2041
swis2-VHDL20_DWLG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:16 2043
swis2-VHDL20_DWLG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2390
swis2-VHDL20_DWLG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2333
swis2-VHDL20_DWLG_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:23 1754
swis2-VHDL20_DWLG_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:12 1494
swis2-VHDL20_DWLG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:24 1647
swis2-VHDL20_DWLH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2173
swis2-VHDL20_DWLH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 1967
swis2-VHDL20_DWLH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 1962
swis2-VHDL20_DWLH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2304
swis2-VHDL20_DWLH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2142
swis2-VHDL20_DWLH_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:23 1514
swis2-VHDL20_DWLH_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:12 1393
swis2-VHDL20_DWLH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:24 1479
swis2-VHDL20_DWLI_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2115
swis2-VHDL20_DWLI_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 1931
swis2-VHDL20_DWLI_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 1932
swis2-VHDL20_DWLI_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2273
swis2-VHDL20_DWLI_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2067
swis2-VHDL20_DWLI_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:23 1449
swis2-VHDL20_DWLI_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:12 1444
swis2-VHDL20_DWLI_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:24 1572
swis2-VHDL20_DWMO_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 1993
swis2-VHDL20_DWMO_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1927
swis2-VHDL20_DWMO_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:08 2153
swis2-VHDL20_DWMO_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2427
swis2-VHDL20_DWMO_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2008
swis2-VHDL20_DWMO_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1483
swis2-VHDL20_DWMO_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:06 1484
swis2-VHDL20_DWMO_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 1457
swis2-VHDL20_DWMP_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:07 1875
swis2-VHDL20_DWMP_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1798
swis2-VHDL20_DWMP_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:08 1798
swis2-VHDL20_DWMP_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 2180
swis2-VHDL20_DWMP_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:12 2188
swis2-VHDL20_DWMP_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1583
swis2-VHDL20_DWMP_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:06 1583
swis2-VHDL20_DWMP_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:47:11 1856
swis2-VHDL20_DWMP_310800_COR-2607310800-dsw--0-ia5 31-Jul-2026 08:43:16 3472
swis2-VHDL20_DWPG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2313
swis2-VHDL20_DWPG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2133
swis2-VHDL20_DWPG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:16 2130
swis2-VHDL20_DWPG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2476
swis2-VHDL20_DWPG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 2223
swis2-VHDL20_DWPG_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:23 1518
swis2-VHDL20_DWPG_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:12 1564
swis2-VHDL20_DWPG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:24 1815
swis2-VHDL20_DWPH_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:31:10 2147
swis2-VHDL20_DWPH_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:24 2083
swis2-VHDL20_DWPH_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:12 2085
swis2-VHDL20_DWPH_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:26 2431
swis2-VHDL20_DWPH_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:31:20 1803
swis2-VHDL20_DWPH_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:23 1143
swis2-VHDL20_DWPH_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:12 1091
swis2-VHDL20_DWPH_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:24 1200
swis2-VHDL20_DWSG_291800-2607291800-dsw--0-ia5 29-Jul-2026 18:30:01 1845
swis2-VHDL20_DWSG_300200-2607300200-dsw--0-ia5 30-Jul-2026 02:30:06 1543
swis2-VHDL20_DWSG_300400-2607300400-dsw--0-ia5 30-Jul-2026 05:00:22 1596
swis2-VHDL20_DWSG_300800-2607300800-dsw--0-ia5 30-Jul-2026 08:30:16 1850
swis2-VHDL20_DWSG_301800-2607301800-dsw--0-ia5 30-Jul-2026 18:30:01 1437
swis2-VHDL20_DWSG_310200-2607310200-dsw--0-ia5 31-Jul-2026 02:30:08 1198
swis2-VHDL20_DWSG_310400-2607310400-dsw--0-ia5 31-Jul-2026 05:00:22 1204
swis2-VHDL20_DWSG_310800-2607310800-dsw--0-ia5 31-Jul-2026 08:30:09 1491
wst04-VHDL20_DWEG_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 245514
wst04-VHDL20_DWEG_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 244413
wst04-VHDL20_DWEG_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:12 244286
wst04-VHDL20_DWEG_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 246152
wst04-VHDL20_DWEG_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 248717
wst04-VHDL20_DWEG_310200-2607310200-omedes--0.pdf 31-Jul-2026 02:30:16 247562
wst04-VHDL20_DWEG_310400-2607310400-omedes--0.pdf 31-Jul-2026 05:00:16 247611
wst04-VHDL20_DWEG_310800-2607310800-omedes--0.pdf 31-Jul-2026 08:30:16 248522
wst04-VHDL20_DWEH_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 242654
wst04-VHDL20_DWEH_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 242248
wst04-VHDL20_DWEH_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:12 242247
wst04-VHDL20_DWEH_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 243818
wst04-VHDL20_DWEH_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 242670
wst04-VHDL20_DWEH_310200-2607310200-omedes--0.pdf 31-Jul-2026 02:30:16 242907
wst04-VHDL20_DWEH_310400-2607310400-omedes--0.pdf 31-Jul-2026 05:00:16 242557
wst04-VHDL20_DWEH_310800-2607310800-omedes--0.pdf 31-Jul-2026 08:30:24 243569
wst04-VHDL20_DWEI_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:30:24 350770
wst04-VHDL20_DWEI_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:30:16 350270
wst04-VHDL20_DWEI_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:18 350070
wst04-VHDL20_DWEI_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:30:16 351313
wst04-VHDL20_DWEI_301800-2607301800-omedes--0.pdf 30-Jul-2026 18:30:21 360153
wst04-VHDL20_DWEI_310200-2607310200-omedes--0.pdf 31-Jul-2026 02:30:16 359527
wst04-VHDL20_DWEI_310400-2607310400-omedes--0.pdf 31-Jul-2026 05:00:22 359604
wst04-VHDL20_DWEI_310800-2607310800-omedes--0.pdf 31-Jul-2026 08:30:24 360004
wst04-VHDL20_DWHG_291800-2607291800-omedes--0.pdf 29-Jul-2026 18:45:13 358084
wst04-VHDL20_DWHG_300200-2607300200-omedes--0.pdf 30-Jul-2026 02:45:37 357237
wst04-VHDL20_DWHG_300400-2607300400-omedes--0.pdf 30-Jul-2026 05:00:22 357302
wst04-VHDL20_DWHG_300800-2607300800-omedes--0.pdf 30-Jul-2026 08:45:57 358940
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wst04-VHDL20_DWMP_310800_COR-2607310800-omedes-..> 31-Jul-2026 08:43:29 582700
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