Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_130600 13-Dec-2018 08:50 3747
FPDL13_DWMZ_140600 14-Dec-2018 09:39 5410
SXDL31_DWAV_121800 12-Dec-2018 17:19 7910
SXDL31_DWAV_130800 13-Dec-2018 08:30 8799
SXDL31_DWAV_131800 13-Dec-2018 16:38 13819
SXDL31_DWAV_140800 14-Dec-2018 08:32 10922
SXDL33_DWAV_130000 13-Dec-2018 11:08 7081
SXDL33_DWAV_140000 14-Dec-2018 13:33 6257
ber01-VHDL13_DWEH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:28 2594
ber01-VHDL13_DWEH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:28 2579
ber01-VHDL13_DWEH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:58 2992
ber01-VHDL13_DWEH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:28 2807
ber01-VHDL13_DWEH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:28 2821
ber01-VHDL13_DWEH_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:28 2973
ber01-VHDL13_DWEH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:28 2829
ber01-VHDL13_DWEH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:28 3123
ber01-VHDL13_DWEH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:58 3132
ber01-VHDL13_DWEH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:28 2995
ber01-VHDL13_DWEH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:28 2885
ber01-VHDL13_DWEH_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:28 2876
ber01-VHDL13_DWHG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2908
ber01-VHDL13_DWHG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 3122
ber01-VHDL13_DWHG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 3128
ber01-VHDL13_DWHG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2875
ber01-VHDL13_DWHG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2917
ber01-VHDL13_DWHG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2564
ber01-VHDL13_DWHG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2949
ber01-VHDL13_DWHG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2954
ber01-VHDL13_DWHG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2688
ber01-VHDL13_DWHG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2808
ber01-VHDL13_DWHH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2687
ber01-VHDL13_DWHH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2884
ber01-VHDL13_DWHH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2834
ber01-VHDL13_DWHH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2836
ber01-VHDL13_DWHH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3066
ber01-VHDL13_DWHH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2820
ber01-VHDL13_DWHH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2561
ber01-VHDL13_DWHH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2559
ber01-VHDL13_DWHH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2232
ber01-VHDL13_DWHH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2416
ber01-VHDL13_DWLG_121733-1812121733-dsw--0-ia5 12-Dec-2018 17:33 2657
ber01-VHDL13_DWLG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2304
ber01-VHDL13_DWLG_121833-1812121833-dsw--0-ia5 12-Dec-2018 18:33 2320
ber01-VHDL13_DWLG_122033-1812122033-dsw--0-ia5 12-Dec-2018 20:33 2332
ber01-VHDL13_DWLG_122133-1812122133-dsw--0-ia5 12-Dec-2018 21:33 2332
ber01-VHDL13_DWLG_130133-1812130133-dsw--0-ia5 13-Dec-2018 01:33 2445
ber01-VHDL13_DWLG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2678
ber01-VHDL13_DWLG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2481
ber01-VHDL13_DWLG_130633-1812130633-dsw--0-ia5 13-Dec-2018 06:33 2509
ber01-VHDL13_DWLG_130733-1812130733-dsw--0-ia5 13-Dec-2018 07:33 2509
ber01-VHDL13_DWLG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2436
ber01-VHDL13_DWLG_130833-1812130833-dsw--0-ia5 13-Dec-2018 08:33 2415
ber01-VHDL13_DWLG_131033-1812131033-dsw--0-ia5 13-Dec-2018 10:33 2440
ber01-VHDL13_DWLG_131133-1812131133-dsw--0-ia5 13-Dec-2018 11:33 2426
ber01-VHDL13_DWLG_131233-1812131233-dsw--0-ia5 13-Dec-2018 12:33 2462
ber01-VHDL13_DWLG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2450
ber01-VHDL13_DWLG_131433-1812131433-dsw--0-ia5 13-Dec-2018 14:33 2285
ber01-VHDL13_DWLG_131533-1812131533-dsw--0-ia5 13-Dec-2018 15:33 2278
ber01-VHDL13_DWLG_131633-1812131633-dsw--0-ia5 13-Dec-2018 16:33 2278
ber01-VHDL13_DWLG_131733-1812131733-dsw--0-ia5 13-Dec-2018 17:33 2278
ber01-VHDL13_DWLG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2156
ber01-VHDL13_DWLG_131833-1812131833-dsw--0-ia5 13-Dec-2018 18:33 2184
ber01-VHDL13_DWLG_132033-1812132033-dsw--0-ia5 13-Dec-2018 20:33 2184
ber01-VHDL13_DWLG_132133-1812132133-dsw--0-ia5 13-Dec-2018 21:33 2184
ber01-VHDL13_DWLG_140133-1812140133-dsw--0-ia5 14-Dec-2018 01:33 2379
ber01-VHDL13_DWLG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2385
ber01-VHDL13_DWLG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2323
ber01-VHDL13_DWLG_140633-1812140633-dsw--0-ia5 14-Dec-2018 06:33 2351
ber01-VHDL13_DWLG_140733-1812140733-dsw--0-ia5 14-Dec-2018 07:33 2351
ber01-VHDL13_DWLG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2443
ber01-VHDL13_DWLG_140833-1812140833-dsw--0-ia5 14-Dec-2018 08:33 2474
ber01-VHDL13_DWLG_141033-1812141033-dsw--0-ia5 14-Dec-2018 10:33 2474
ber01-VHDL13_DWLG_141133-1812141133-dsw--0-ia5 14-Dec-2018 11:33 2474
ber01-VHDL13_DWLG_141233-1812141233-dsw--0-ia5 14-Dec-2018 12:33 2449
ber01-VHDL13_DWLG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2371
ber01-VHDL13_DWLG_141433-1812141433-dsw--0-ia5 14-Dec-2018 14:33 2349
ber01-VHDL13_DWLG_141533-1812141533-dsw--0-ia5 14-Dec-2018 15:33 2349
ber01-VHDL13_DWLG_141633-1812141633-dsw--0-ia5 14-Dec-2018 16:33 2349
ber01-VHDL13_DWLH_121733-1812121733-dsw--0-ia5 12-Dec-2018 17:33 2598
ber01-VHDL13_DWLH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2500
ber01-VHDL13_DWLH_121833-1812121833-dsw--0-ia5 12-Dec-2018 18:33 2266
ber01-VHDL13_DWLH_122033-1812122033-dsw--0-ia5 12-Dec-2018 20:33 2528
ber01-VHDL13_DWLH_122133-1812122133-dsw--0-ia5 12-Dec-2018 21:33 2528
ber01-VHDL13_DWLH_130133-1812130133-dsw--0-ia5 13-Dec-2018 01:33 2544
ber01-VHDL13_DWLH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2544
ber01-VHDL13_DWLH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2583
ber01-VHDL13_DWLH_130633-1812130633-dsw--0-ia5 13-Dec-2018 06:33 2611
ber01-VHDL13_DWLH_130733-1812130733-dsw--0-ia5 13-Dec-2018 07:33 2611
ber01-VHDL13_DWLH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2365
ber01-VHDL13_DWLH_130833-1812130833-dsw--0-ia5 13-Dec-2018 08:33 2393
ber01-VHDL13_DWLH_131033-1812131033-dsw--0-ia5 13-Dec-2018 10:33 2454
ber01-VHDL13_DWLH_131133-1812131133-dsw--0-ia5 13-Dec-2018 11:33 2460
ber01-VHDL13_DWLH_131233-1812131233-dsw--0-ia5 13-Dec-2018 12:33 2487
ber01-VHDL13_DWLH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2421
ber01-VHDL13_DWLH_131433-1812131433-dsw--0-ia5 13-Dec-2018 14:33 2238
ber01-VHDL13_DWLH_131533-1812131533-dsw--0-ia5 13-Dec-2018 15:33 2237
ber01-VHDL13_DWLH_131633-1812131633-dsw--0-ia5 13-Dec-2018 16:33 2237
ber01-VHDL13_DWLH_131733-1812131733-dsw--0-ia5 13-Dec-2018 17:33 2423
ber01-VHDL13_DWLH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2155
ber01-VHDL13_DWLH_131833-1812131833-dsw--0-ia5 13-Dec-2018 18:33 2183
ber01-VHDL13_DWLH_132033-1812132033-dsw--0-ia5 13-Dec-2018 20:33 2183
ber01-VHDL13_DWLH_132133-1812132133-dsw--0-ia5 13-Dec-2018 21:33 2183
ber01-VHDL13_DWLH_140133-1812140133-dsw--0-ia5 14-Dec-2018 01:33 2324
ber01-VHDL13_DWLH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2349
ber01-VHDL13_DWLH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2222
ber01-VHDL13_DWLH_140633-1812140633-dsw--0-ia5 14-Dec-2018 06:33 2250
ber01-VHDL13_DWLH_140733-1812140733-dsw--0-ia5 14-Dec-2018 07:33 2250
ber01-VHDL13_DWLH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2450
ber01-VHDL13_DWLH_140833-1812140833-dsw--0-ia5 14-Dec-2018 08:33 2478
ber01-VHDL13_DWLH_141033-1812141033-dsw--0-ia5 14-Dec-2018 10:33 2478
ber01-VHDL13_DWLH_141133-1812141133-dsw--0-ia5 14-Dec-2018 11:33 2478
ber01-VHDL13_DWLH_141233-1812141233-dsw--0-ia5 14-Dec-2018 12:33 2407
ber01-VHDL13_DWLH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2339
ber01-VHDL13_DWLH_141433-1812141433-dsw--0-ia5 14-Dec-2018 14:33 2305
ber01-VHDL13_DWLH_141533-1812141533-dsw--0-ia5 14-Dec-2018 15:33 2305
ber01-VHDL13_DWLH_141633-1812141633-dsw--0-ia5 14-Dec-2018 16:33 2305
ber01-VHDL13_DWLI_121733-1812121733-dsw--0-ia5 12-Dec-2018 17:33 2647
ber01-VHDL13_DWLI_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2159
ber01-VHDL13_DWLI_121833-1812121833-dsw--0-ia5 12-Dec-2018 18:33 2210
ber01-VHDL13_DWLI_122033-1812122033-dsw--0-ia5 12-Dec-2018 20:33 2187
ber01-VHDL13_DWLI_122133-1812122133-dsw--0-ia5 12-Dec-2018 21:33 2187
ber01-VHDL13_DWLI_130133-1812130133-dsw--0-ia5 13-Dec-2018 01:33 2234
ber01-VHDL13_DWLI_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2498
ber01-VHDL13_DWLI_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2401
ber01-VHDL13_DWLI_130633-1812130633-dsw--0-ia5 13-Dec-2018 06:33 2429
ber01-VHDL13_DWLI_130733-1812130733-dsw--0-ia5 13-Dec-2018 07:33 2429
ber01-VHDL13_DWLI_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2308
ber01-VHDL13_DWLI_130833-1812130833-dsw--0-ia5 13-Dec-2018 08:33 2275
ber01-VHDL13_DWLI_131033-1812131033-dsw--0-ia5 13-Dec-2018 10:33 2355
ber01-VHDL13_DWLI_131133-1812131133-dsw--0-ia5 13-Dec-2018 11:33 2425
ber01-VHDL13_DWLI_131233-1812131233-dsw--0-ia5 13-Dec-2018 12:33 2491
ber01-VHDL13_DWLI_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2481
ber01-VHDL13_DWLI_131433-1812131433-dsw--0-ia5 13-Dec-2018 14:33 2370
ber01-VHDL13_DWLI_131533-1812131533-dsw--0-ia5 13-Dec-2018 15:33 2363
ber01-VHDL13_DWLI_131633-1812131633-dsw--0-ia5 13-Dec-2018 16:33 2363
ber01-VHDL13_DWLI_131733-1812131733-dsw--0-ia5 13-Dec-2018 17:33 2363
ber01-VHDL13_DWLI_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2126
ber01-VHDL13_DWLI_131833-1812131833-dsw--0-ia5 13-Dec-2018 18:33 2424
ber01-VHDL13_DWLI_132033-1812132033-dsw--0-ia5 13-Dec-2018 20:33 2154
ber01-VHDL13_DWLI_132133-1812132133-dsw--0-ia5 13-Dec-2018 21:33 2154
ber01-VHDL13_DWLI_140133-1812140133-dsw--0-ia5 14-Dec-2018 01:33 2329
ber01-VHDL13_DWLI_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2308
ber01-VHDL13_DWLI_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2280
ber01-VHDL13_DWLI_140633-1812140633-dsw--0-ia5 14-Dec-2018 06:33 2308
ber01-VHDL13_DWLI_140733-1812140733-dsw--0-ia5 14-Dec-2018 07:33 2308
ber01-VHDL13_DWLI_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2488
ber01-VHDL13_DWLI_140833-1812140833-dsw--0-ia5 14-Dec-2018 08:33 2516
ber01-VHDL13_DWLI_141033-1812141033-dsw--0-ia5 14-Dec-2018 10:33 2516
ber01-VHDL13_DWLI_141133-1812141133-dsw--0-ia5 14-Dec-2018 11:33 2516
ber01-VHDL13_DWLI_141233-1812141233-dsw--0-ia5 14-Dec-2018 12:33 2373
ber01-VHDL13_DWLI_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2320
ber01-VHDL13_DWLI_141433-1812141433-dsw--0-ia5 14-Dec-2018 14:33 2346
ber01-VHDL13_DWLI_141533-1812141533-dsw--0-ia5 14-Dec-2018 15:33 2346
ber01-VHDL13_DWLI_141633-1812141633-dsw--0-ia5 14-Dec-2018 16:33 2346
ber01-VHDL13_DWMG_121700-1812121700-dsw--0-ia5 12-Dec-2018 17:30 2834
ber01-VHDL13_DWMG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2847
ber01-VHDL13_DWMG_122000-1812122000-dsw--0-ia5 12-Dec-2018 20:30 2883
ber01-VHDL13_DWMG_122100-1812122100-dsw--0-ia5 12-Dec-2018 21:30 2883
ber01-VHDL13_DWMG_122200-1812122200-dsw--0-ia5 12-Dec-2018 22:30 2883
ber01-VHDL13_DWMG_122300-1812122300-dsw--0-ia5 12-Dec-2018 23:30 3444
ber01-VHDL13_DWMG_130000-1812130000-dsw--0-ia5 13-Dec-2018 00:30 3444
ber01-VHDL13_DWMG_130100-1812130100-dsw--0-ia5 13-Dec-2018 01:30 3444
ber01-VHDL13_DWMG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 3444
ber01-VHDL13_DWMG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 3450
ber01-VHDL13_DWMG_130600-1812130600-dsw--0-ia5 13-Dec-2018 06:30 3473
ber01-VHDL13_DWMG_130700-1812130700-dsw--0-ia5 13-Dec-2018 07:30 3449
ber01-VHDL13_DWMG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 3463
ber01-VHDL13_DWMG_131000-1812131000-dsw--0-ia5 13-Dec-2018 10:30 3434
ber01-VHDL13_DWMG_131100-1812131100-dsw--0-ia5 13-Dec-2018 11:30 3598
ber01-VHDL13_DWMG_131200-1812131200-dsw--0-ia5 13-Dec-2018 12:30 3465
ber01-VHDL13_DWMG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3470
ber01-VHDL13_DWMG_131500-1812131500-dsw--0-ia5 13-Dec-2018 15:30 2825
ber01-VHDL13_DWMG_131600-1812131600-dsw--0-ia5 13-Dec-2018 16:30 2825
ber01-VHDL13_DWMG_131700-1812131700-dsw--0-ia5 13-Dec-2018 17:30 2670
ber01-VHDL13_DWMG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2670
ber01-VHDL13_DWMG_132000-1812132000-dsw--0-ia5 13-Dec-2018 20:30 2652
ber01-VHDL13_DWMG_132100-1812132100-dsw--0-ia5 13-Dec-2018 21:30 2652
ber01-VHDL13_DWMG_132200-1812132200-dsw--0-ia5 13-Dec-2018 22:30 2652
ber01-VHDL13_DWMG_132300-1812132300-dsw--0-ia5 13-Dec-2018 23:30 2841
ber01-VHDL13_DWMG_140000-1812140000-dsw--0-ia5 14-Dec-2018 00:30 2841
ber01-VHDL13_DWMG_140100-1812140100-dsw--0-ia5 14-Dec-2018 01:30 2841
ber01-VHDL13_DWMG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2841
ber01-VHDL13_DWMG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 3015
ber01-VHDL13_DWMG_140600-1812140600-dsw--0-ia5 14-Dec-2018 06:30 3079
ber01-VHDL13_DWMG_140700-1812140700-dsw--0-ia5 14-Dec-2018 07:30 3070
ber01-VHDL13_DWMG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2800
ber01-VHDL13_DWMG_141000-1812141000-dsw--0-ia5 14-Dec-2018 10:30 2800
ber01-VHDL13_DWMG_141100-1812141100-dsw--0-ia5 14-Dec-2018 11:30 2748
ber01-VHDL13_DWMG_141200-1812141200-dsw--0-ia5 14-Dec-2018 12:30 2748
ber01-VHDL13_DWMG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2793
ber01-VHDL13_DWMG_141500-1812141500-dsw--0-ia5 14-Dec-2018 15:30 2455
ber01-VHDL13_DWMG_141600-1812141600-dsw--0-ia5 14-Dec-2018 16:30 2455
ber01-VHDL13_DWMO_121700-1812121700-dsw--0-ia5 12-Dec-2018 17:30 2555
ber01-VHDL13_DWMO_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2405
ber01-VHDL13_DWMO_122000-1812122000-dsw--0-ia5 12-Dec-2018 20:30 2410
ber01-VHDL13_DWMO_122100-1812122100-dsw--0-ia5 12-Dec-2018 21:30 2410
ber01-VHDL13_DWMO_122200-1812122200-dsw--0-ia5 12-Dec-2018 22:30 2410
ber01-VHDL13_DWMO_122300-1812122300-dsw--0-ia5 12-Dec-2018 23:30 3111
ber01-VHDL13_DWMO_130000-1812130000-dsw--0-ia5 13-Dec-2018 00:30 3111
ber01-VHDL13_DWMO_130100-1812130100-dsw--0-ia5 13-Dec-2018 01:30 3111
ber01-VHDL13_DWMO_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 3111
ber01-VHDL13_DWMO_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 3123
ber01-VHDL13_DWMO_130600-1812130600-dsw--0-ia5 13-Dec-2018 06:30 3123
ber01-VHDL13_DWMO_130700-1812130700-dsw--0-ia5 13-Dec-2018 07:30 3123
ber01-VHDL13_DWMO_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 3201
ber01-VHDL13_DWMO_131000-1812131000-dsw--0-ia5 13-Dec-2018 10:30 3153
ber01-VHDL13_DWMO_131100-1812131100-dsw--0-ia5 13-Dec-2018 11:30 3306
ber01-VHDL13_DWMO_131200-1812131200-dsw--0-ia5 13-Dec-2018 12:30 3257
ber01-VHDL13_DWMO_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3265
ber01-VHDL13_DWMO_131500-1812131500-dsw--0-ia5 13-Dec-2018 15:30 2593
ber01-VHDL13_DWMO_131600-1812131600-dsw--0-ia5 13-Dec-2018 16:30 2593
ber01-VHDL13_DWMO_131700-1812131700-dsw--0-ia5 13-Dec-2018 17:30 2431
ber01-VHDL13_DWMO_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2431
ber01-VHDL13_DWMO_132000-1812132000-dsw--0-ia5 13-Dec-2018 20:30 2367
ber01-VHDL13_DWMO_132100-1812132100-dsw--0-ia5 13-Dec-2018 21:30 2367
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ber01-VHDL13_DWMP_131100-1812131100-dsw--0-ia5 13-Dec-2018 11:30 3271
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ber01-VHDL13_DWMP_131500-1812131500-dsw--0-ia5 13-Dec-2018 15:30 2716
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ber01-VHDL13_DWMP_132100-1812132100-dsw--0-ia5 13-Dec-2018 21:30 2583
ber01-VHDL13_DWMP_132200-1812132200-dsw--0-ia5 13-Dec-2018 22:30 2583
ber01-VHDL13_DWMP_132300-1812132300-dsw--0-ia5 13-Dec-2018 23:30 2739
ber01-VHDL13_DWMP_140000-1812140000-dsw--0-ia5 14-Dec-2018 00:30 2739
ber01-VHDL13_DWMP_140100-1812140100-dsw--0-ia5 14-Dec-2018 01:30 2739
ber01-VHDL13_DWMP_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2739
ber01-VHDL13_DWMP_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2966
ber01-VHDL13_DWMP_140600-1812140600-dsw--0-ia5 14-Dec-2018 06:30 3075
ber01-VHDL13_DWMP_140700-1812140700-dsw--0-ia5 14-Dec-2018 07:30 3107
ber01-VHDL13_DWMP_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2834
ber01-VHDL13_DWMP_141000-1812141000-dsw--0-ia5 14-Dec-2018 10:30 2834
ber01-VHDL13_DWMP_141100-1812141100-dsw--0-ia5 14-Dec-2018 11:30 2797
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ber01-VHDL13_DWMP_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2839
ber01-VHDL13_DWMP_141500-1812141500-dsw--0-ia5 14-Dec-2018 15:30 2558
ber01-VHDL13_DWMP_141600-1812141600-dsw--0-ia5 14-Dec-2018 16:30 2558
ber01-VHDL13_DWOG_121700-1812121700-dsw--0-ia5 12-Dec-2018 18:30 3951
ber01-VHDL13_DWOG_130100-1812130100-dsw--0-ia5 13-Dec-2018 02:45 4667
ber01-VHDL13_DWOG_130300-1812130300-dsw--0-ia5 13-Dec-2018 04:00 4677
ber01-VHDL13_DWOG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:15 4799
ber01-VHDL13_DWOG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:00 4586
ber01-VHDL13_DWOG_131700-1812131700-dsw--0-ia5 13-Dec-2018 18:30 4447
ber01-VHDL13_DWOG_140100-1812140100-dsw--0-ia5 14-Dec-2018 02:45 4800
ber01-VHDL13_DWOG_140300-1812140300-dsw--0-ia5 14-Dec-2018 04:00 4621
ber01-VHDL13_DWOG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:15 4119
ber01-VHDL13_DWOG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:00 3774
ber01-VHDL13_DWOH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:28 2433
ber01-VHDL13_DWOH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:28 2267
ber01-VHDL13_DWOH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:58 2633
ber01-VHDL13_DWOH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:28 2354
ber01-VHDL13_DWOH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:28 2390
ber01-VHDL13_DWOH_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:28 2557
ber01-VHDL13_DWOH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:28 2383
ber01-VHDL13_DWOH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:28 2750
ber01-VHDL13_DWOH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:58 2665
ber01-VHDL13_DWOH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:28 2497
ber01-VHDL13_DWOH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:28 2385
ber01-VHDL13_DWOH_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:28 2422
ber01-VHDL13_DWOI_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:28 2256
ber01-VHDL13_DWOI_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:28 2577
ber01-VHDL13_DWOI_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:58 2886
ber01-VHDL13_DWOI_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:28 2766
ber01-VHDL13_DWOI_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:28 2761
ber01-VHDL13_DWOI_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:28 2540
ber01-VHDL13_DWOI_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:28 2428
ber01-VHDL13_DWOI_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:28 2761
ber01-VHDL13_DWOI_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:58 2669
ber01-VHDL13_DWOI_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:28 2566
ber01-VHDL13_DWOI_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:28 2549
ber01-VHDL13_DWOI_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:28 2609
ber01-VHDL13_DWON_121756-1812121756-dsw--0-ia5 12-Dec-2018 17:57 3593
ber01-VHDL13_DWON_122008-1812122008-dsw--0-ia5 12-Dec-2018 20:08 4292
ber01-VHDL13_DWON_130012-1812130012-dsw--0-ia5 13-Dec-2018 00:12 4205
ber01-VHDL13_DWON_130200-1812130200-dsw--0-ia5 13-Dec-2018 02:00 4205
ber01-VHDL13_DWON_130355-1812130355-dsw--0-ia5 13-Dec-2018 03:55 4205
ber01-VHDL13_DWON_130629-1812130629-dsw--0-ia5 13-Dec-2018 06:29 4458
ber01-VHDL13_DWON_130722-1812130722-dsw--0-ia5 13-Dec-2018 07:22 4454
ber01-VHDL13_DWON_130754-1812130754-dsw--0-ia5 13-Dec-2018 07:54 4509
ber01-VHDL13_DWON_130803-1812130803-dsw--0-ia5 13-Dec-2018 08:03 4478
ber01-VHDL13_DWON_131241-1812131241-dsw--0-ia5 13-Dec-2018 12:41 4296
ber01-VHDL13_DWON_131609-1812131609-dsw--0-ia5 13-Dec-2018 16:09 4029
ber01-VHDL13_DWON_131648-1812131648-dsw--0-ia5 13-Dec-2018 16:48 4003
ber01-VHDL13_DWON_131722-1812131722-dsw--0-ia5 13-Dec-2018 17:22 4003
ber01-VHDL13_DWON_131746-1812131746-dsw--0-ia5 13-Dec-2018 17:46 4003
ber01-VHDL13_DWON_132110-1812132110-dsw--0-ia5 13-Dec-2018 21:10 4254
ber01-VHDL13_DWON_140235-1812140235-dsw--0-ia5 14-Dec-2018 02:35 4472
ber01-VHDL13_DWON_140342-1812140342-dsw--0-ia5 14-Dec-2018 03:42 4472
ber01-VHDL13_DWON_140628-1812140628-dsw--0-ia5 14-Dec-2018 06:28 4197
ber01-VHDL13_DWON_140634-1812140634-dsw--0-ia5 14-Dec-2018 06:34 4185
ber01-VHDL13_DWON_140704-1812140704-dsw--0-ia5 14-Dec-2018 07:04 4022
ber01-VHDL13_DWON_141226-1812141226-dsw--0-ia5 14-Dec-2018 12:26 4363
ber01-VHDL13_DWPG_121730-1812121730-dsw--0-ia5 12-Dec-2018 17:30 2221
ber01-VHDL13_DWPG_121750-1812121750-dsw--0-ia5 12-Dec-2018 18:30 2221
ber01-VHDL13_DWPG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2000
ber01-VHDL13_DWPG_122030-1812122030-dsw--0-ia5 12-Dec-2018 20:30 2063
ber01-VHDL13_DWPG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2216
ber01-VHDL13_DWPG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2396
ber01-VHDL13_DWPG_130630-1812130630-dsw--0-ia5 13-Dec-2018 06:30 2395
ber01-VHDL13_DWPG_130730-1812130730-dsw--0-ia5 13-Dec-2018 07:30 2395
ber01-VHDL13_DWPG_130750-1812130750-dsw--0-ia5 13-Dec-2018 08:30 2395
ber01-VHDL13_DWPG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2403
ber01-VHDL13_DWPG_131030-1812131030-dsw--0-ia5 13-Dec-2018 10:30 2403
ber01-VHDL13_DWPG_131130-1812131130-dsw--0-ia5 13-Dec-2018 11:30 2403
ber01-VHDL13_DWPG_131230-1812131230-dsw--0-ia5 13-Dec-2018 12:30 2325
ber01-VHDL13_DWPG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2124
ber01-VHDL13_DWPG_131430-1812131430-dsw--0-ia5 13-Dec-2018 14:30 2124
ber01-VHDL13_DWPG_131450-1812131450-dsw--0-ia5 13-Dec-2018 15:30 2113
ber01-VHDL13_DWPG_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:30 2146
ber01-VHDL13_DWPG_131730-1812131730-dsw--0-ia5 13-Dec-2018 17:30 2146
ber01-VHDL13_DWPG_131750-1812131750-dsw--0-ia5 13-Dec-2018 18:30 2035
ber01-VHDL13_DWPG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2035
ber01-VHDL13_DWPG_132030-1812132030-dsw--0-ia5 13-Dec-2018 20:30 2035
ber01-VHDL13_DWPG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 1894
ber01-VHDL13_DWPG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2127
ber01-VHDL13_DWPG_140630-1812140630-dsw--0-ia5 14-Dec-2018 06:30 2126
ber01-VHDL13_DWPG_140730-1812140730-dsw--0-ia5 14-Dec-2018 07:30 2105
ber01-VHDL13_DWPG_140750-1812140750-dsw--0-ia5 14-Dec-2018 08:30 2105
ber01-VHDL13_DWPG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2171
ber01-VHDL13_DWPG_141030-1812141030-dsw--0-ia5 14-Dec-2018 10:30 2171
ber01-VHDL13_DWPG_141130-1812141130-dsw--0-ia5 14-Dec-2018 11:30 2171
ber01-VHDL13_DWPG_141230-1812141230-dsw--0-ia5 14-Dec-2018 12:30 2166
ber01-VHDL13_DWPG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2065
ber01-VHDL13_DWPG_141430-1812141430-dsw--0-ia5 14-Dec-2018 14:30 2065
ber01-VHDL13_DWPG_141450-1812141450-dsw--0-ia5 14-Dec-2018 15:30 2065
ber01-VHDL13_DWPG_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:30 2332
ber01-VHDL13_DWPH_121730-1812121730-dsw--0-ia5 12-Dec-2018 17:30 2346
ber01-VHDL13_DWPH_121750-1812121750-dsw--0-ia5 12-Dec-2018 18:30 2346
ber01-VHDL13_DWPH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 1987
ber01-VHDL13_DWPH_122030-1812122030-dsw--0-ia5 12-Dec-2018 20:30 1949
ber01-VHDL13_DWPH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2235
ber01-VHDL13_DWPH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2449
ber01-VHDL13_DWPH_130630-1812130630-dsw--0-ia5 13-Dec-2018 06:30 2449
ber01-VHDL13_DWPH_130730-1812130730-dsw--0-ia5 13-Dec-2018 07:30 2449
ber01-VHDL13_DWPH_130750-1812130750-dsw--0-ia5 13-Dec-2018 08:30 2449
ber01-VHDL13_DWPH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2557
ber01-VHDL13_DWPH_131030-1812131030-dsw--0-ia5 13-Dec-2018 10:30 2557
ber01-VHDL13_DWPH_131130-1812131130-dsw--0-ia5 13-Dec-2018 11:30 2557
ber01-VHDL13_DWPH_131230-1812131230-dsw--0-ia5 13-Dec-2018 12:30 2597
ber01-VHDL13_DWPH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2546
ber01-VHDL13_DWPH_131430-1812131430-dsw--0-ia5 13-Dec-2018 14:30 2546
ber01-VHDL13_DWPH_131450-1812131450-dsw--0-ia5 13-Dec-2018 15:30 2546
ber01-VHDL13_DWPH_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:30 2595
ber01-VHDL13_DWPH_131730-1812131730-dsw--0-ia5 13-Dec-2018 17:30 2595
ber01-VHDL13_DWPH_131750-1812131750-dsw--0-ia5 13-Dec-2018 18:30 2379
ber01-VHDL13_DWPH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2376
ber01-VHDL13_DWPH_132030-1812132030-dsw--0-ia5 13-Dec-2018 20:30 2376
ber01-VHDL13_DWPH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2356
ber01-VHDL13_DWPH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2770
ber01-VHDL13_DWPH_140630-1812140630-dsw--0-ia5 14-Dec-2018 06:30 2770
ber01-VHDL13_DWPH_140730-1812140730-dsw--0-ia5 14-Dec-2018 07:30 2748
ber01-VHDL13_DWPH_140750-1812140750-dsw--0-ia5 14-Dec-2018 08:30 2748
ber01-VHDL13_DWPH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2469
ber01-VHDL13_DWPH_141030-1812141030-dsw--0-ia5 14-Dec-2018 10:30 2469
ber01-VHDL13_DWPH_141130-1812141130-dsw--0-ia5 14-Dec-2018 11:30 2489
ber01-VHDL13_DWPH_141230-1812141230-dsw--0-ia5 14-Dec-2018 12:30 2551
ber01-VHDL13_DWPH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2350
ber01-VHDL13_DWPH_141430-1812141430-dsw--0-ia5 14-Dec-2018 14:30 2350
ber01-VHDL13_DWPH_141450-1812141450-dsw--0-ia5 14-Dec-2018 15:30 2350
ber01-VHDL13_DWPH_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:30 2439
ber01-VHDL13_DWSG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2946
ber01-VHDL13_DWSG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2974
ber01-VHDL13_DWSG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2784
ber01-VHDL13_DWSG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2517
ber01-VHDL13_DWSG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3021
ber01-VHDL13_DWSG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2938
ber01-VHDL13_DWSG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 3089
ber01-VHDL13_DWSG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 3232
ber01-VHDL13_DWSG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 3381
ber01-VHDL13_DWSG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 3361
ber01-VHDL13_DWSN_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 1869
ber01-VHDL13_DWSN_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2043
ber01-VHDL13_DWSN_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2076
ber01-VHDL13_DWSN_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2098
ber01-VHDL13_DWSN_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:30 2449
ber01-VHDL13_DWSN_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2422
ber01-VHDL13_DWSN_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2652
ber01-VHDL13_DWSN_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2708
ber01-VHDL13_DWSN_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2804
ber01-VHDL13_DWSN_141300-1812141300-dsw--0-ia5 14-Dec-2018 14:30 2783
ber01-VHDL13_DWSO_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2625
ber01-VHDL13_DWSO_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2746
ber01-VHDL13_DWSO_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2509
ber01-VHDL13_DWSO_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2313
ber01-VHDL13_DWSO_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:30 2712
ber01-VHDL13_DWSO_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2730
ber01-VHDL13_DWSO_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2999
ber01-VHDL13_DWSO_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2979
ber01-VHDL13_DWSO_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 3010
ber01-VHDL13_DWSO_141300-1812141300-dsw--0-ia5 14-Dec-2018 14:30 2926
ber01-VHDL13_DWSP_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 1979
ber01-VHDL13_DWSP_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2173
ber01-VHDL13_DWSP_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2255
ber01-VHDL13_DWSP_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2125
ber01-VHDL13_DWSP_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:30 2470
ber01-VHDL13_DWSP_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2506
ber01-VHDL13_DWSP_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2731
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ber01-VHDL13_DWSP_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2790
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ber01-VHDL20_DWHG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 4812
ber01-VHDL20_DWHG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 5086
ber01-VHDL20_DWHG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 5032
ber01-VHDL20_DWHG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 4779
ber01-VHDL20_DWHG_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:45 4821
ber01-VHDL20_DWHG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 4448
ber01-VHDL20_DWHG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 4864
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ber01-VHDL20_DWHG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 4527
ber01-VHDL20_DWHG_141300-1812141300-dsw--0-ia5 14-Dec-2018 14:45 4646
ber01-VHDL20_DWHH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 3848
ber01-VHDL20_DWHH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4058
ber01-VHDL20_DWHH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 3995
ber01-VHDL20_DWHH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 3997
ber01-VHDL20_DWHH_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:45 4227
ber01-VHDL20_DWHH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 3949
ber01-VHDL20_DWHH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 3697
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gts01-VHDL12_DWON_121815-1812121845-afsv--32-ia5 12-Dec-2018 18:45 2965
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gts01-VHDL12_DWON_141330-1812141330-afsv--86-ia5 14-Dec-2018 13:30 3979
pid-VHDL12_DWEH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:28 1968
pid-VHDL12_DWEH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:28 2822
pid-VHDL12_DWHG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2651
pid-VHDL12_DWHG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2655
pid-VHDL12_DWHG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2580
pid-VHDL12_DWHG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2583
pid-VHDL12_DWHH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2425
pid-VHDL12_DWHH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2375
pid-VHDL12_DWHH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2295
pid-VHDL12_DWHH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 2293
pid-VHDL12_DWLG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 1967
pid-VHDL12_DWLG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2270
pid-VHDL12_DWLG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2073
pid-VHDL12_DWLG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2031
pid-VHDL12_DWLG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2042
pid-VHDL12_DWLG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 1762
pid-VHDL12_DWLG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2023
pid-VHDL12_DWLG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 1961
pid-VHDL12_DWLG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2084
pid-VHDL12_DWLG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 2009
pid-VHDL12_DWLH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2166
pid-VHDL12_DWLH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2140
pid-VHDL12_DWLH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2179
pid-VHDL12_DWLH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 1961
pid-VHDL12_DWLH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2017
pid-VHDL12_DWLH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 1755
pid-VHDL12_DWLH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2004
pid-VHDL12_DWLH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 1877
pid-VHDL12_DWLH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2105
pid-VHDL12_DWLH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 1994
pid-VHDL12_DWLI_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 1835
pid-VHDL12_DWLI_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2110
pid-VHDL12_DWLI_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2013
pid-VHDL12_DWLI_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 1920
pid-VHDL12_DWLI_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2022
pid-VHDL12_DWLI_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 1718
pid-VHDL12_DWLI_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 1966
pid-VHDL12_DWLI_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 1938
pid-VHDL12_DWLI_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2146
pid-VHDL12_DWLI_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 1978
pid-VHDL12_DWMG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 2383
pid-VHDL12_DWMG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 2677
pid-VHDL12_DWMG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 2683
pid-VHDL12_DWMG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 2696
pid-VHDL12_DWMG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 2709
pid-VHDL12_DWMG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 2096
pid-VHDL12_DWMG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2398
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pid-VHDL12_DWMG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 2363
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swis2-VHDL20_DWHG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 5086
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swis2-VHDL20_DWHG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 4864
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swis2-VHDL20_DWHH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4058
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swis2-VHDL20_DWLG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 4072
swis2-VHDL20_DWLG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4446
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swis2-VHDL20_DWLH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 4269
swis2-VHDL20_DWLH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4313
swis2-VHDL20_DWLH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 4347
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swis2-VHDL20_DWLI_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4266
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swis2-VHDL20_DWLI_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 4071
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swis2-VHDL20_DWLI_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 3879
swis2-VHDL20_DWLI_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 4061
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swis2-VHDL20_DWLI_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 4204
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swis2-VHDL20_DWMG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 6409
swis2-VHDL20_DWMG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 6420
swis2-VHDL20_DWMG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 5801
swis2-VHDL20_DWMG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:45 6440
swis2-VHDL20_DWMG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 5639
swis2-VHDL20_DWMG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 5807
swis2-VHDL20_DWMG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:45 5984
swis2-VHDL20_DWMG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 5138
swis2-VHDL20_DWMG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:45 5763
swis2-VHDL20_DWMO_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 4412
swis2-VHDL20_DWMO_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 5120
swis2-VHDL20_DWMO_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 5134
swis2-VHDL20_DWMO_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 5164
swis2-VHDL20_DWMO_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:45 5276
swis2-VHDL20_DWMO_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 4442
swis2-VHDL20_DWMO_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 4595
swis2-VHDL20_DWMO_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:45 4745
swis2-VHDL20_DWMO_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 4468
swis2-VHDL20_DWMO_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:45 4440
swis2-VHDL20_DWMP_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 5269
swis2-VHDL20_DWMP_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 5797
swis2-VHDL20_DWMP_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 5807
swis2-VHDL20_DWMP_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 5883
swis2-VHDL20_DWMP_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:45 5905
swis2-VHDL20_DWMP_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 5263
swis2-VHDL20_DWMP_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 5452
swis2-VHDL20_DWMP_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:45 5680
swis2-VHDL20_DWMP_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 5549
swis2-VHDL20_DWMP_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:45 5554
swis2-VHDL20_DWPG_121730-1812121730-dsw--0-ia5 12-Dec-2018 17:30 3221
swis2-VHDL20_DWPG_121750-1812121750-dsw--0-ia5 12-Dec-2018 18:30 3221
swis2-VHDL20_DWPG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 3030
swis2-VHDL20_DWPG_122030-1812122030-dsw--0-ia5 12-Dec-2018 20:30 3093
swis2-VHDL20_DWPG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 3291
swis2-VHDL20_DWPG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 3359
swis2-VHDL20_DWPG_130630-1812130630-dsw--0-ia5 13-Dec-2018 06:30 3359
swis2-VHDL20_DWPG_130730-1812130730-dsw--0-ia5 13-Dec-2018 07:30 3359
swis2-VHDL20_DWPG_130750-1812130750-dsw--0-ia5 13-Dec-2018 08:30 3359
swis2-VHDL20_DWPG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 3431
swis2-VHDL20_DWPG_131030-1812131030-dsw--0-ia5 13-Dec-2018 10:30 3431
swis2-VHDL20_DWPG_131130-1812131130-dsw--0-ia5 13-Dec-2018 11:30 3431
swis2-VHDL20_DWPG_131230-1812131230-dsw--0-ia5 13-Dec-2018 12:30 3353
swis2-VHDL20_DWPG_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3122
swis2-VHDL20_DWPG_131430-1812131430-dsw--0-ia5 13-Dec-2018 14:30 3122
swis2-VHDL20_DWPG_131450-1812131450-dsw--0-ia5 13-Dec-2018 15:30 3111
swis2-VHDL20_DWPG_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:30 3144
swis2-VHDL20_DWPG_131730-1812131730-dsw--0-ia5 13-Dec-2018 17:30 3144
swis2-VHDL20_DWPG_131750-1812131750-dsw--0-ia5 13-Dec-2018 18:30 3033
swis2-VHDL20_DWPG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 3063
swis2-VHDL20_DWPG_132030-1812132030-dsw--0-ia5 13-Dec-2018 20:30 3063
swis2-VHDL20_DWPG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 2964
swis2-VHDL20_DWPG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 3090
swis2-VHDL20_DWPG_140630-1812140630-dsw--0-ia5 14-Dec-2018 06:30 3090
swis2-VHDL20_DWPG_140730-1812140730-dsw--0-ia5 14-Dec-2018 07:30 3069
swis2-VHDL20_DWPG_140750-1812140750-dsw--0-ia5 14-Dec-2018 08:30 3069
swis2-VHDL20_DWPG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 3199
swis2-VHDL20_DWPG_141030-1812141030-dsw--0-ia5 14-Dec-2018 10:30 3199
swis2-VHDL20_DWPG_141130-1812141130-dsw--0-ia5 14-Dec-2018 11:31 3199
swis2-VHDL20_DWPG_141230-1812141230-dsw--0-ia5 14-Dec-2018 12:30 3194
swis2-VHDL20_DWPG_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 3063
swis2-VHDL20_DWPG_141430-1812141430-dsw--0-ia5 14-Dec-2018 14:30 3063
swis2-VHDL20_DWPG_141450-1812141450-dsw--0-ia5 14-Dec-2018 15:30 3063
swis2-VHDL20_DWPG_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:30 3330
swis2-VHDL20_DWPH_121730-1812121730-dsw--0-ia5 12-Dec-2018 17:30 3374
swis2-VHDL20_DWPH_121750-1812121750-dsw--0-ia5 12-Dec-2018 18:30 3374
swis2-VHDL20_DWPH_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:30 3014
swis2-VHDL20_DWPH_122030-1812122030-dsw--0-ia5 12-Dec-2018 20:30 2976
swis2-VHDL20_DWPH_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:30 3387
swis2-VHDL20_DWPH_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:30 3414
swis2-VHDL20_DWPH_130630-1812130630-dsw--0-ia5 13-Dec-2018 06:30 3414
swis2-VHDL20_DWPH_130730-1812130730-dsw--0-ia5 13-Dec-2018 07:30 3414
swis2-VHDL20_DWPH_130750-1812130750-dsw--0-ia5 13-Dec-2018 08:30 3414
swis2-VHDL20_DWPH_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:30 3585
swis2-VHDL20_DWPH_131030-1812131030-dsw--0-ia5 13-Dec-2018 10:30 3585
swis2-VHDL20_DWPH_131130-1812131130-dsw--0-ia5 13-Dec-2018 11:30 3585
swis2-VHDL20_DWPH_131230-1812131230-dsw--0-ia5 13-Dec-2018 12:30 3625
swis2-VHDL20_DWPH_131300-1812131300-dsw--0-ia5 13-Dec-2018 13:30 3574
swis2-VHDL20_DWPH_131430-1812131430-dsw--0-ia5 13-Dec-2018 14:30 3574
swis2-VHDL20_DWPH_131450-1812131450-dsw--0-ia5 13-Dec-2018 15:30 3574
swis2-VHDL20_DWPH_131500-1812131500-dsw--0-ia5 13-Dec-2018 16:30 3623
swis2-VHDL20_DWPH_131730-1812131730-dsw--0-ia5 13-Dec-2018 17:30 3623
swis2-VHDL20_DWPH_131750-1812131750-dsw--0-ia5 13-Dec-2018 18:30 3407
swis2-VHDL20_DWPH_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:30 3404
swis2-VHDL20_DWPH_132030-1812132030-dsw--0-ia5 13-Dec-2018 20:30 3404
swis2-VHDL20_DWPH_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:30 3506
swis2-VHDL20_DWPH_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:30 3735
swis2-VHDL20_DWPH_140630-1812140630-dsw--0-ia5 14-Dec-2018 06:30 3735
swis2-VHDL20_DWPH_140730-1812140730-dsw--0-ia5 14-Dec-2018 07:30 3713
swis2-VHDL20_DWPH_140750-1812140750-dsw--0-ia5 14-Dec-2018 08:30 3713
swis2-VHDL20_DWPH_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:30 3497
swis2-VHDL20_DWPH_141030-1812141030-dsw--0-ia5 14-Dec-2018 10:30 3497
swis2-VHDL20_DWPH_141130-1812141130-dsw--0-ia5 14-Dec-2018 11:31 3517
swis2-VHDL20_DWPH_141230-1812141230-dsw--0-ia5 14-Dec-2018 12:30 3579
swis2-VHDL20_DWPH_141300-1812141300-dsw--0-ia5 14-Dec-2018 13:30 3380
swis2-VHDL20_DWPH_141430-1812141430-dsw--0-ia5 14-Dec-2018 14:30 3380
swis2-VHDL20_DWPH_141450-1812141450-dsw--0-ia5 14-Dec-2018 15:30 3380
swis2-VHDL20_DWPH_141500-1812141500-dsw--0-ia5 14-Dec-2018 16:30 3469
swis2-VHDL20_DWSG_121800-1812121800-dsw--0-ia5 12-Dec-2018 19:45 4508
swis2-VHDL20_DWSG_130200-1812130200-dsw--0-ia5 13-Dec-2018 03:45 4535
swis2-VHDL20_DWSG_130400-1812130400-dsw--0-ia5 13-Dec-2018 05:45 4345
swis2-VHDL20_DWSG_130800-1812130800-dsw--0-ia5 13-Dec-2018 09:45 4078
swis2-VHDL20_DWSG_131300-1812131300-dsw--0-ia5 13-Dec-2018 14:45 4598
swis2-VHDL20_DWSG_131800-1812131800-dsw--0-ia5 13-Dec-2018 19:45 4488
swis2-VHDL20_DWSG_140200-1812140200-dsw--0-ia5 14-Dec-2018 03:45 4650
swis2-VHDL20_DWSG_140400-1812140400-dsw--0-ia5 14-Dec-2018 05:45 4793
swis2-VHDL20_DWSG_140800-1812140800-dsw--0-ia5 14-Dec-2018 09:45 4941
swis2-VHDL20_DWSG_141300-1812141300-dsw--0-ia5 14-Dec-2018 14:45 4916