Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_190600 19-Jun-2018 11:01 3670
FPDL13_DWMZ_200600 20-Jun-2018 10:20 8407
SXDL31_DWAV_181800 18-Jun-2018 16:52 10234
SXDL31_DWAV_190800 19-Jun-2018 07:14 9076
SXDL31_DWAV_191800 19-Jun-2018 16:49 12040
SXDL31_DWAV_200800 20-Jun-2018 07:14 14382
SXDL33_DWAV_190000 19-Jun-2018 09:55 7769
SXDL33_DWAV_200000 20-Jun-2018 10:32 4356
ber01-VHDL13_DWEH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:28 2128
ber01-VHDL13_DWEH_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:28 2077
ber01-VHDL13_DWEH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:28 2074
ber01-VHDL13_DWEH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 2436
ber01-VHDL13_DWEH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:58 2478
ber01-VHDL13_DWEH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:28 2391
ber01-VHDL13_DWEH_190800_COR-1806190800-dsw--0-ia5 19-Jun-2018 10:32 2441
ber01-VHDL13_DWEH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:28 2447
ber01-VHDL13_DWEH_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:28 2465
ber01-VHDL13_DWEH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:28 2151
ber01-VHDL13_DWEH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 2263
ber01-VHDL13_DWEH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:58 2536
ber01-VHDL13_DWEH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:28 2515
ber01-VHDL13_DWEH_200800_COR-1806200800-dsw--0-ia5 20-Jun-2018 10:02 2519
ber01-VHDL13_DWHG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2044
ber01-VHDL13_DWHG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1826
ber01-VHDL13_DWHG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2110
ber01-VHDL13_DWHG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2096
ber01-VHDL13_DWHG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2097
ber01-VHDL13_DWHG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2092
ber01-VHDL13_DWHG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1899
ber01-VHDL13_DWHG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2203
ber01-VHDL13_DWHG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2271
ber01-VHDL13_DWHG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2421
ber01-VHDL13_DWHH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2202
ber01-VHDL13_DWHH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1991
ber01-VHDL13_DWHH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2237
ber01-VHDL13_DWHH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2232
ber01-VHDL13_DWHH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2397
ber01-VHDL13_DWHH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2391
ber01-VHDL13_DWHH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2099
ber01-VHDL13_DWHH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2339
ber01-VHDL13_DWHH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2347
ber01-VHDL13_DWHH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2637
ber01-VHDL13_DWLG_181133-1806181133-dsw--0-ia5 18-Jun-2018 11:33 2397
ber01-VHDL13_DWLG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2354
ber01-VHDL13_DWLG_181333-1806181333-dsw--0-ia5 18-Jun-2018 13:33 2312
ber01-VHDL13_DWLG_181433-1806181433-dsw--0-ia5 18-Jun-2018 14:33 2312
ber01-VHDL13_DWLG_181533-1806181533-dsw--0-ia5 18-Jun-2018 15:33 2312
ber01-VHDL13_DWLG_181633-1806181633-dsw--0-ia5 18-Jun-2018 16:33 2312
ber01-VHDL13_DWLG_181733-1806181733-dsw--0-ia5 18-Jun-2018 17:33 2152
ber01-VHDL13_DWLG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 2124
ber01-VHDL13_DWLG_181933-1806181933-dsw--0-ia5 18-Jun-2018 19:33 2152
ber01-VHDL13_DWLG_182033-1806182033-dsw--0-ia5 18-Jun-2018 20:33 2152
ber01-VHDL13_DWLG_190033-1806190033-dsw--0-ia5 19-Jun-2018 00:33 2499
ber01-VHDL13_DWLG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2471
ber01-VHDL13_DWLG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2490
ber01-VHDL13_DWLG_190533-1806190533-dsw--0-ia5 19-Jun-2018 05:33 2518
ber01-VHDL13_DWLG_190633-1806190633-dsw--0-ia5 19-Jun-2018 06:33 2519
ber01-VHDL13_DWLG_190733-1806190733-dsw--0-ia5 19-Jun-2018 07:33 2512
ber01-VHDL13_DWLG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2475
ber01-VHDL13_DWLG_190933-1806190933-dsw--0-ia5 19-Jun-2018 09:33 2508
ber01-VHDL13_DWLG_191033-1806191033-dsw--0-ia5 19-Jun-2018 10:33 2477
ber01-VHDL13_DWLG_191133-1806191133-dsw--0-ia5 19-Jun-2018 11:33 2477
ber01-VHDL13_DWLG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2434
ber01-VHDL13_DWLG_191333-1806191333-dsw--0-ia5 19-Jun-2018 13:33 2464
ber01-VHDL13_DWLG_191433-1806191433-dsw--0-ia5 19-Jun-2018 14:33 2464
ber01-VHDL13_DWLG_191533-1806191533-dsw--0-ia5 19-Jun-2018 15:33 2464
ber01-VHDL13_DWLG_191633-1806191633-dsw--0-ia5 19-Jun-2018 16:33 2453
ber01-VHDL13_DWLG_191733-1806191733-dsw--0-ia5 19-Jun-2018 17:33 2272
ber01-VHDL13_DWLG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2244
ber01-VHDL13_DWLG_191933-1806191933-dsw--0-ia5 19-Jun-2018 19:33 2272
ber01-VHDL13_DWLG_192033-1806192033-dsw--0-ia5 19-Jun-2018 20:33 2272
ber01-VHDL13_DWLG_200033-1806200033-dsw--0-ia5 20-Jun-2018 00:33 2874
ber01-VHDL13_DWLG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2846
ber01-VHDL13_DWLG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2849
ber01-VHDL13_DWLG_200533-1806200533-dsw--0-ia5 20-Jun-2018 05:33 2877
ber01-VHDL13_DWLG_200633-1806200633-dsw--0-ia5 20-Jun-2018 06:33 2863
ber01-VHDL13_DWLG_200733-1806200733-dsw--0-ia5 20-Jun-2018 07:33 2897
ber01-VHDL13_DWLG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2866
ber01-VHDL13_DWLG_200933-1806200933-dsw--0-ia5 20-Jun-2018 09:33 2897
ber01-VHDL13_DWLG_201033-1806201033-dsw--0-ia5 20-Jun-2018 10:33 2884
ber01-VHDL13_DWLH_181133-1806181133-dsw--0-ia5 18-Jun-2018 11:33 2342
ber01-VHDL13_DWLH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2299
ber01-VHDL13_DWLH_181333-1806181333-dsw--0-ia5 18-Jun-2018 13:33 2266
ber01-VHDL13_DWLH_181433-1806181433-dsw--0-ia5 18-Jun-2018 14:33 2266
ber01-VHDL13_DWLH_181533-1806181533-dsw--0-ia5 18-Jun-2018 15:33 2266
ber01-VHDL13_DWLH_181633-1806181633-dsw--0-ia5 18-Jun-2018 16:33 2266
ber01-VHDL13_DWLH_181733-1806181733-dsw--0-ia5 18-Jun-2018 17:33 2141
ber01-VHDL13_DWLH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 2113
ber01-VHDL13_DWLH_181933-1806181933-dsw--0-ia5 18-Jun-2018 19:33 2141
ber01-VHDL13_DWLH_182033-1806182033-dsw--0-ia5 18-Jun-2018 20:33 2141
ber01-VHDL13_DWLH_190033-1806190033-dsw--0-ia5 19-Jun-2018 00:33 2516
ber01-VHDL13_DWLH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2488
ber01-VHDL13_DWLH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2521
ber01-VHDL13_DWLH_190533-1806190533-dsw--0-ia5 19-Jun-2018 05:33 2530
ber01-VHDL13_DWLH_190633-1806190633-dsw--0-ia5 19-Jun-2018 06:33 2531
ber01-VHDL13_DWLH_190733-1806190733-dsw--0-ia5 19-Jun-2018 07:33 2527
ber01-VHDL13_DWLH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2493
ber01-VHDL13_DWLH_190933-1806190933-dsw--0-ia5 19-Jun-2018 09:33 2523
ber01-VHDL13_DWLH_191033-1806191033-dsw--0-ia5 19-Jun-2018 10:33 2491
ber01-VHDL13_DWLH_191133-1806191133-dsw--0-ia5 19-Jun-2018 11:33 2491
ber01-VHDL13_DWLH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2459
ber01-VHDL13_DWLH_191333-1806191333-dsw--0-ia5 19-Jun-2018 13:33 2497
ber01-VHDL13_DWLH_191433-1806191433-dsw--0-ia5 19-Jun-2018 14:33 2497
ber01-VHDL13_DWLH_191533-1806191533-dsw--0-ia5 19-Jun-2018 15:33 2497
ber01-VHDL13_DWLH_191633-1806191633-dsw--0-ia5 19-Jun-2018 16:33 2491
ber01-VHDL13_DWLH_191733-1806191733-dsw--0-ia5 19-Jun-2018 17:33 2289
ber01-VHDL13_DWLH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2261
ber01-VHDL13_DWLH_191933-1806191933-dsw--0-ia5 19-Jun-2018 19:33 2289
ber01-VHDL13_DWLH_192033-1806192033-dsw--0-ia5 19-Jun-2018 20:33 2289
ber01-VHDL13_DWLH_200033-1806200033-dsw--0-ia5 20-Jun-2018 00:33 2949
ber01-VHDL13_DWLH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2921
ber01-VHDL13_DWLH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2961
ber01-VHDL13_DWLH_200533-1806200533-dsw--0-ia5 20-Jun-2018 05:33 2989
ber01-VHDL13_DWLH_200633-1806200633-dsw--0-ia5 20-Jun-2018 06:33 2993
ber01-VHDL13_DWLH_200733-1806200733-dsw--0-ia5 20-Jun-2018 07:33 2884
ber01-VHDL13_DWLH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2856
ber01-VHDL13_DWLH_200933-1806200933-dsw--0-ia5 20-Jun-2018 09:33 2884
ber01-VHDL13_DWLH_201033-1806201033-dsw--0-ia5 20-Jun-2018 10:33 2872
ber01-VHDL13_DWLI_181133-1806181133-dsw--0-ia5 18-Jun-2018 11:33 2348
ber01-VHDL13_DWLI_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2305
ber01-VHDL13_DWLI_181333-1806181333-dsw--0-ia5 18-Jun-2018 13:33 2274
ber01-VHDL13_DWLI_181433-1806181433-dsw--0-ia5 18-Jun-2018 14:33 2274
ber01-VHDL13_DWLI_181533-1806181533-dsw--0-ia5 18-Jun-2018 15:33 2274
ber01-VHDL13_DWLI_181633-1806181633-dsw--0-ia5 18-Jun-2018 16:33 2274
ber01-VHDL13_DWLI_181733-1806181733-dsw--0-ia5 18-Jun-2018 17:33 2134
ber01-VHDL13_DWLI_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 2106
ber01-VHDL13_DWLI_181933-1806181933-dsw--0-ia5 18-Jun-2018 19:33 2134
ber01-VHDL13_DWLI_182033-1806182033-dsw--0-ia5 18-Jun-2018 20:33 2134
ber01-VHDL13_DWLI_190033-1806190033-dsw--0-ia5 19-Jun-2018 00:33 2393
ber01-VHDL13_DWLI_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2365
ber01-VHDL13_DWLI_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2387
ber01-VHDL13_DWLI_190533-1806190533-dsw--0-ia5 19-Jun-2018 05:33 2415
ber01-VHDL13_DWLI_190633-1806190633-dsw--0-ia5 19-Jun-2018 06:33 2416
ber01-VHDL13_DWLI_190733-1806190733-dsw--0-ia5 19-Jun-2018 07:33 2410
ber01-VHDL13_DWLI_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2376
ber01-VHDL13_DWLI_190933-1806190933-dsw--0-ia5 19-Jun-2018 09:33 2406
ber01-VHDL13_DWLI_191033-1806191033-dsw--0-ia5 19-Jun-2018 10:33 2376
ber01-VHDL13_DWLI_191133-1806191133-dsw--0-ia5 19-Jun-2018 11:33 2376
ber01-VHDL13_DWLI_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2333
ber01-VHDL13_DWLI_191333-1806191333-dsw--0-ia5 19-Jun-2018 13:33 2374
ber01-VHDL13_DWLI_191433-1806191433-dsw--0-ia5 19-Jun-2018 14:33 2374
ber01-VHDL13_DWLI_191533-1806191533-dsw--0-ia5 19-Jun-2018 15:33 2374
ber01-VHDL13_DWLI_191633-1806191633-dsw--0-ia5 19-Jun-2018 16:33 2366
ber01-VHDL13_DWLI_191733-1806191733-dsw--0-ia5 19-Jun-2018 17:33 2172
ber01-VHDL13_DWLI_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2144
ber01-VHDL13_DWLI_191933-1806191933-dsw--0-ia5 19-Jun-2018 19:33 2172
ber01-VHDL13_DWLI_192033-1806192033-dsw--0-ia5 19-Jun-2018 20:33 2172
ber01-VHDL13_DWLI_200033-1806200033-dsw--0-ia5 20-Jun-2018 00:33 2682
ber01-VHDL13_DWLI_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2654
ber01-VHDL13_DWLI_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2652
ber01-VHDL13_DWLI_200533-1806200533-dsw--0-ia5 20-Jun-2018 05:33 2680
ber01-VHDL13_DWLI_200633-1806200633-dsw--0-ia5 20-Jun-2018 06:33 2662
ber01-VHDL13_DWLI_200733-1806200733-dsw--0-ia5 20-Jun-2018 07:33 2644
ber01-VHDL13_DWLI_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2616
ber01-VHDL13_DWLI_200933-1806200933-dsw--0-ia5 20-Jun-2018 09:33 2644
ber01-VHDL13_DWLI_201033-1806201033-dsw--0-ia5 20-Jun-2018 10:33 2631
ber01-VHDL13_DWMG_181100-1806181100-dsw--0-ia5 18-Jun-2018 11:30 2208
ber01-VHDL13_DWMG_181200-1806181200-dsw--0-ia5 18-Jun-2018 12:30 2262
ber01-VHDL13_DWMG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2262
ber01-VHDL13_DWMG_181400-1806181400-dsw--0-ia5 18-Jun-2018 14:30 1922
ber01-VHDL13_DWMG_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:30 1922
ber01-VHDL13_DWMG_181600-1806181600-dsw--0-ia5 18-Jun-2018 16:30 1922
ber01-VHDL13_DWMG_181700-1806181700-dsw--0-ia5 18-Jun-2018 17:30 1650
ber01-VHDL13_DWMG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1650
ber01-VHDL13_DWMG_181900-1806181900-dsw--0-ia5 18-Jun-2018 19:30 1650
ber01-VHDL13_DWMG_182000-1806182000-dsw--0-ia5 18-Jun-2018 20:30 1650
ber01-VHDL13_DWMG_182100-1806182100-dsw--0-ia5 18-Jun-2018 21:30 1650
ber01-VHDL13_DWMG_182200-1806182200-dsw--0-ia5 18-Jun-2018 22:30 1727
ber01-VHDL13_DWMG_182300-1806182300-dsw--0-ia5 18-Jun-2018 23:30 1727
ber01-VHDL13_DWMG_190000-1806190000-dsw--0-ia5 19-Jun-2018 00:30 1727
ber01-VHDL13_DWMG_190100-1806190100-dsw--0-ia5 19-Jun-2018 01:30 1727
ber01-VHDL13_DWMG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1706
ber01-VHDL13_DWMG_190300-1806190300-dsw--0-ia5 19-Jun-2018 03:30 1706
ber01-VHDL13_DWMG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1647
ber01-VHDL13_DWMG_190500-1806190500-dsw--0-ia5 19-Jun-2018 05:30 1674
ber01-VHDL13_DWMG_190600-1806190600-dsw--0-ia5 19-Jun-2018 06:30 1674
ber01-VHDL13_DWMG_190700-1806190700-dsw--0-ia5 19-Jun-2018 07:30 1648
ber01-VHDL13_DWMG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1786
ber01-VHDL13_DWMG_190900-1806190900-dsw--0-ia5 19-Jun-2018 09:30 1822
ber01-VHDL13_DWMG_191000-1806191000-dsw--0-ia5 19-Jun-2018 10:30 1821
ber01-VHDL13_DWMG_191100-1806191100-dsw--0-ia5 19-Jun-2018 11:30 1821
ber01-VHDL13_DWMG_191200-1806191200-dsw--0-ia5 19-Jun-2018 12:30 1780
ber01-VHDL13_DWMG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1780
ber01-VHDL13_DWMG_191400-1806191400-dsw--0-ia5 19-Jun-2018 14:30 1920
ber01-VHDL13_DWMG_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:30 1920
ber01-VHDL13_DWMG_191600-1806191600-dsw--0-ia5 19-Jun-2018 16:30 1920
ber01-VHDL13_DWMG_191700-1806191700-dsw--0-ia5 19-Jun-2018 17:30 1856
ber01-VHDL13_DWMG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1856
ber01-VHDL13_DWMG_191900-1806191900-dsw--0-ia5 19-Jun-2018 19:30 1937
ber01-VHDL13_DWMG_192000-1806192000-dsw--0-ia5 19-Jun-2018 20:30 1937
ber01-VHDL13_DWMG_192100-1806192100-dsw--0-ia5 19-Jun-2018 21:30 1937
ber01-VHDL13_DWMG_192200-1806192200-dsw--0-ia5 19-Jun-2018 22:30 2096
ber01-VHDL13_DWMG_192300-1806192300-dsw--0-ia5 19-Jun-2018 23:30 2096
ber01-VHDL13_DWMG_200000-1806200000-dsw--0-ia5 20-Jun-2018 00:30 2096
ber01-VHDL13_DWMG_200100-1806200100-dsw--0-ia5 20-Jun-2018 01:30 2096
ber01-VHDL13_DWMG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2065
ber01-VHDL13_DWMG_200300-1806200300-dsw--0-ia5 20-Jun-2018 03:30 2065
ber01-VHDL13_DWMG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2069
ber01-VHDL13_DWMG_200500-1806200500-dsw--0-ia5 20-Jun-2018 05:30 2242
ber01-VHDL13_DWMG_200600-1806200600-dsw--0-ia5 20-Jun-2018 06:30 2273
ber01-VHDL13_DWMG_200700-1806200700-dsw--0-ia5 20-Jun-2018 07:30 2372
ber01-VHDL13_DWMG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2485
ber01-VHDL13_DWMG_200900-1806200900-dsw--0-ia5 20-Jun-2018 09:30 2557
ber01-VHDL13_DWMG_201000-1806201000-dsw--0-ia5 20-Jun-2018 10:30 2578
ber01-VHDL13_DWMO_181100-1806181100-dsw--0-ia5 18-Jun-2018 11:30 1967
ber01-VHDL13_DWMO_181200-1806181200-dsw--0-ia5 18-Jun-2018 12:30 1967
ber01-VHDL13_DWMO_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1967
ber01-VHDL13_DWMO_181400-1806181400-dsw--0-ia5 18-Jun-2018 14:30 1841
ber01-VHDL13_DWMO_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:30 1841
ber01-VHDL13_DWMO_181600-1806181600-dsw--0-ia5 18-Jun-2018 16:30 1841
ber01-VHDL13_DWMO_181700-1806181700-dsw--0-ia5 18-Jun-2018 17:30 1611
ber01-VHDL13_DWMO_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1611
ber01-VHDL13_DWMO_181900-1806181900-dsw--0-ia5 18-Jun-2018 19:30 1611
ber01-VHDL13_DWMO_182000-1806182000-dsw--0-ia5 18-Jun-2018 20:30 1611
ber01-VHDL13_DWMO_182100-1806182100-dsw--0-ia5 18-Jun-2018 21:30 1611
ber01-VHDL13_DWMO_182200-1806182200-dsw--0-ia5 18-Jun-2018 22:30 1702
ber01-VHDL13_DWMO_182300-1806182300-dsw--0-ia5 18-Jun-2018 23:30 1702
ber01-VHDL13_DWMO_190000-1806190000-dsw--0-ia5 19-Jun-2018 00:30 1702
ber01-VHDL13_DWMO_190100-1806190100-dsw--0-ia5 19-Jun-2018 01:30 1702
ber01-VHDL13_DWMO_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1730
ber01-VHDL13_DWMO_190300-1806190300-dsw--0-ia5 19-Jun-2018 03:30 1730
ber01-VHDL13_DWMO_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1741
ber01-VHDL13_DWMO_190500-1806190500-dsw--0-ia5 19-Jun-2018 05:30 1796
ber01-VHDL13_DWMO_190600-1806190600-dsw--0-ia5 19-Jun-2018 06:30 1796
ber01-VHDL13_DWMO_190700-1806190700-dsw--0-ia5 19-Jun-2018 07:30 1723
ber01-VHDL13_DWMO_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1869
ber01-VHDL13_DWMO_190900-1806190900-dsw--0-ia5 19-Jun-2018 09:30 1933
ber01-VHDL13_DWMO_191000-1806191000-dsw--0-ia5 19-Jun-2018 10:30 2015
ber01-VHDL13_DWMO_191100-1806191100-dsw--0-ia5 19-Jun-2018 11:30 2015
ber01-VHDL13_DWMO_191200-1806191200-dsw--0-ia5 19-Jun-2018 12:30 1983
ber01-VHDL13_DWMO_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1983
ber01-VHDL13_DWMO_191400-1806191400-dsw--0-ia5 19-Jun-2018 14:30 1860
ber01-VHDL13_DWMO_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:30 1860
ber01-VHDL13_DWMO_191600-1806191600-dsw--0-ia5 19-Jun-2018 16:30 1860
ber01-VHDL13_DWMO_191700-1806191700-dsw--0-ia5 19-Jun-2018 17:30 1771
ber01-VHDL13_DWMO_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1772
ber01-VHDL13_DWMO_191900-1806191900-dsw--0-ia5 19-Jun-2018 19:30 1772
ber01-VHDL13_DWMO_192000-1806192000-dsw--0-ia5 19-Jun-2018 20:30 1822
ber01-VHDL13_DWMO_192100-1806192100-dsw--0-ia5 19-Jun-2018 21:30 1822
ber01-VHDL13_DWMO_192200-1806192200-dsw--0-ia5 19-Jun-2018 22:30 1969
ber01-VHDL13_DWMO_192300-1806192300-dsw--0-ia5 19-Jun-2018 23:30 1969
ber01-VHDL13_DWMO_200000-1806200000-dsw--0-ia5 20-Jun-2018 00:30 1969
ber01-VHDL13_DWMO_200100-1806200100-dsw--0-ia5 20-Jun-2018 01:30 1969
ber01-VHDL13_DWMO_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1969
ber01-VHDL13_DWMO_200300-1806200300-dsw--0-ia5 20-Jun-2018 03:30 2041
ber01-VHDL13_DWMO_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2041
ber01-VHDL13_DWMO_200500-1806200500-dsw--0-ia5 20-Jun-2018 05:30 2059
ber01-VHDL13_DWMO_200600-1806200600-dsw--0-ia5 20-Jun-2018 06:30 2143
ber01-VHDL13_DWMO_200700-1806200700-dsw--0-ia5 20-Jun-2018 07:30 2143
ber01-VHDL13_DWMO_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2393
ber01-VHDL13_DWMO_200900-1806200900-dsw--0-ia5 20-Jun-2018 09:30 2498
ber01-VHDL13_DWMO_201000-1806201000-dsw--0-ia5 20-Jun-2018 10:30 2493
ber01-VHDL13_DWMP_181100-1806181100-dsw--0-ia5 18-Jun-2018 11:30 2179
ber01-VHDL13_DWMP_181200-1806181200-dsw--0-ia5 18-Jun-2018 12:30 2179
ber01-VHDL13_DWMP_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2179
ber01-VHDL13_DWMP_181400-1806181400-dsw--0-ia5 18-Jun-2018 14:30 1818
ber01-VHDL13_DWMP_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:30 1818
ber01-VHDL13_DWMP_181600-1806181600-dsw--0-ia5 18-Jun-2018 16:30 1818
ber01-VHDL13_DWMP_181700-1806181700-dsw--0-ia5 18-Jun-2018 17:30 1641
ber01-VHDL13_DWMP_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1641
ber01-VHDL13_DWMP_181900-1806181900-dsw--0-ia5 18-Jun-2018 19:30 1641
ber01-VHDL13_DWMP_182000-1806182000-dsw--0-ia5 18-Jun-2018 20:30 1641
ber01-VHDL13_DWMP_182100-1806182100-dsw--0-ia5 18-Jun-2018 21:30 1641
ber01-VHDL13_DWMP_182200-1806182200-dsw--0-ia5 18-Jun-2018 22:30 1795
ber01-VHDL13_DWMP_182300-1806182300-dsw--0-ia5 18-Jun-2018 23:30 1795
ber01-VHDL13_DWMP_190000-1806190000-dsw--0-ia5 19-Jun-2018 00:30 1795
ber01-VHDL13_DWMP_190100-1806190100-dsw--0-ia5 19-Jun-2018 01:30 1795
ber01-VHDL13_DWMP_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1749
ber01-VHDL13_DWMP_190300-1806190300-dsw--0-ia5 19-Jun-2018 03:30 1749
ber01-VHDL13_DWMP_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1739
ber01-VHDL13_DWMP_190500-1806190500-dsw--0-ia5 19-Jun-2018 05:30 1868
ber01-VHDL13_DWMP_190600-1806190600-dsw--0-ia5 19-Jun-2018 06:30 1869
ber01-VHDL13_DWMP_190700-1806190700-dsw--0-ia5 19-Jun-2018 07:30 1707
ber01-VHDL13_DWMP_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1753
ber01-VHDL13_DWMP_190900-1806190900-dsw--0-ia5 19-Jun-2018 09:30 1778
ber01-VHDL13_DWMP_191000-1806191000-dsw--0-ia5 19-Jun-2018 10:30 1812
ber01-VHDL13_DWMP_191100-1806191100-dsw--0-ia5 19-Jun-2018 11:30 1812
ber01-VHDL13_DWMP_191200-1806191200-dsw--0-ia5 19-Jun-2018 12:30 1791
ber01-VHDL13_DWMP_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1791
ber01-VHDL13_DWMP_191400-1806191400-dsw--0-ia5 19-Jun-2018 14:30 1752
ber01-VHDL13_DWMP_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:30 1752
ber01-VHDL13_DWMP_191600-1806191600-dsw--0-ia5 19-Jun-2018 16:30 1752
ber01-VHDL13_DWMP_191700-1806191700-dsw--0-ia5 19-Jun-2018 17:30 1792
ber01-VHDL13_DWMP_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1792
ber01-VHDL13_DWMP_191900-1806191900-dsw--0-ia5 19-Jun-2018 19:30 1792
ber01-VHDL13_DWMP_192000-1806192000-dsw--0-ia5 19-Jun-2018 20:30 1811
ber01-VHDL13_DWMP_192100-1806192100-dsw--0-ia5 19-Jun-2018 21:30 1811
ber01-VHDL13_DWMP_192200-1806192200-dsw--0-ia5 19-Jun-2018 22:30 2094
ber01-VHDL13_DWMP_192300-1806192300-dsw--0-ia5 19-Jun-2018 23:30 2094
ber01-VHDL13_DWMP_200000-1806200000-dsw--0-ia5 20-Jun-2018 00:30 2094
ber01-VHDL13_DWMP_200100-1806200100-dsw--0-ia5 20-Jun-2018 01:30 2094
ber01-VHDL13_DWMP_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2094
ber01-VHDL13_DWMP_200300-1806200300-dsw--0-ia5 20-Jun-2018 03:30 2024
ber01-VHDL13_DWMP_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2173
ber01-VHDL13_DWMP_200500-1806200500-dsw--0-ia5 20-Jun-2018 05:30 2200
ber01-VHDL13_DWMP_200600-1806200600-dsw--0-ia5 20-Jun-2018 06:30 2193
ber01-VHDL13_DWMP_200700-1806200700-dsw--0-ia5 20-Jun-2018 07:30 2193
ber01-VHDL13_DWMP_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2382
ber01-VHDL13_DWMP_200900-1806200900-dsw--0-ia5 20-Jun-2018 09:30 2342
ber01-VHDL13_DWMP_201000-1806201000-dsw--0-ia5 20-Jun-2018 10:30 2307
ber01-VHDL13_DWOG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:00 3366
ber01-VHDL13_DWOG_181700-1806181700-dsw--0-ia5 18-Jun-2018 17:30 3453
ber01-VHDL13_DWOG_190100-1806190100-dsw--0-ia5 19-Jun-2018 01:45 3486
ber01-VHDL13_DWOG_190300-1806190300-dsw--0-ia5 19-Jun-2018 03:00 3486
ber01-VHDL13_DWOG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:15 3552
ber01-VHDL13_DWOG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:00 3538
ber01-VHDL13_DWOG_191700-1806191700-dsw--0-ia5 19-Jun-2018 17:30 3203
ber01-VHDL13_DWOG_200100-1806200100-dsw--0-ia5 20-Jun-2018 01:45 3273
ber01-VHDL13_DWOG_200300-1806200300-dsw--0-ia5 20-Jun-2018 03:00 3273
ber01-VHDL13_DWOG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:15 4192
ber01-VHDL13_DWOH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:28 2194
ber01-VHDL13_DWOH_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:28 2069
ber01-VHDL13_DWOH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:28 2060
ber01-VHDL13_DWOH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 2383
ber01-VHDL13_DWOH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:58 2394
ber01-VHDL13_DWOH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:28 2412
ber01-VHDL13_DWOH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:28 2460
ber01-VHDL13_DWOH_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:28 2449
ber01-VHDL13_DWOH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:28 2075
ber01-VHDL13_DWOH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 2217
ber01-VHDL13_DWOH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:58 2222
ber01-VHDL13_DWOH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:28 2336
ber01-VHDL13_DWOH_200800_COR-1806200800-dsw--0-ia5 20-Jun-2018 10:02 2340
ber01-VHDL13_DWOI_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:28 2183
ber01-VHDL13_DWOI_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:28 2096
ber01-VHDL13_DWOI_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:28 2076
ber01-VHDL13_DWOI_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 2243
ber01-VHDL13_DWOI_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:58 2340
ber01-VHDL13_DWOI_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:28 2406
ber01-VHDL13_DWOI_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:28 2439
ber01-VHDL13_DWOI_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:28 2427
ber01-VHDL13_DWOI_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:28 2105
ber01-VHDL13_DWOI_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 2235
ber01-VHDL13_DWOI_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:58 2235
ber01-VHDL13_DWOI_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:28 2360
ber01-VHDL13_DWOI_200800_COR-1806200800-dsw--0-ia5 20-Jun-2018 10:02 2364
ber01-VHDL13_DWON_181215-1806181215-dsw--0-ia5 18-Jun-2018 12:15 3289
ber01-VHDL13_DWON_181316-1806181316-dsw--0-ia5 18-Jun-2018 13:16 3289
ber01-VHDL13_DWON_181717-1806181717-dsw--0-ia5 18-Jun-2018 17:18 3855
ber01-VHDL13_DWON_181827-1806181827-dsw--0-ia5 18-Jun-2018 18:27 3232
ber01-VHDL13_DWON_181831-1806181831-dsw--0-ia5 18-Jun-2018 18:31 3232
ber01-VHDL13_DWON_190137-1806190137-dsw--0-ia5 19-Jun-2018 01:37 3505
ber01-VHDL13_DWON_190144-1806190144-dsw--0-ia5 19-Jun-2018 01:44 3506
ber01-VHDL13_DWON_190145-1806190145-dsw--0-ia5 19-Jun-2018 01:45 3506
ber01-VHDL13_DWON_190307-1806190307-dsw--0-ia5 19-Jun-2018 03:07 3518
ber01-VHDL13_DWON_190338-1806190338-dsw--0-ia5 19-Jun-2018 03:38 3518
ber01-VHDL13_DWON_190501-1806190501-dsw--0-ia5 19-Jun-2018 05:01 3572
ber01-VHDL13_DWON_190644-1806190644-dsw--0-ia5 19-Jun-2018 06:44 3662
ber01-VHDL13_DWON_191106-1806191106-dsw--0-ia5 19-Jun-2018 11:06 3652
ber01-VHDL13_DWON_191112-1806191112-dsw--0-ia5 19-Jun-2018 11:13 3652
ber01-VHDL13_DWON_191422-1806191422-dsw--0-ia5 19-Jun-2018 14:22 3910
ber01-VHDL13_DWON_191428-1806191428-dsw--0-ia5 19-Jun-2018 14:28 3910
ber01-VHDL13_DWON_191712-1806191712-dsw--0-ia5 19-Jun-2018 17:12 3358
ber01-VHDL13_DWON_192101-1806192101-dsw--0-ia5 19-Jun-2018 21:01 3124
ber01-VHDL13_DWON_200138-1806200138-dsw--0-ia5 20-Jun-2018 01:38 3439
ber01-VHDL13_DWON_200328-1806200328-dsw--0-ia5 20-Jun-2018 03:28 3439
ber01-VHDL13_DWON_200332-1806200332-dsw--0-ia5 20-Jun-2018 03:32 3376
ber01-VHDL13_DWON_200503-1806200503-dsw--0-ia5 20-Jun-2018 05:03 3552
ber01-VHDL13_DWON_200628-1806200628-dsw--0-ia5 20-Jun-2018 06:28 4367
ber01-VHDL13_DWON_201111-1806201111-dsw--0-ia5 20-Jun-2018 11:11 4333
ber01-VHDL13_DWPG_180200_COR-1806180200-dsw--0-ia5 18-Jun-2018 19:49 2197
ber01-VHDL13_DWPG_181130-1806181130-dsw--0-ia5 18-Jun-2018 11:30 2078
ber01-VHDL13_DWPG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2167
ber01-VHDL13_DWPG_181330-1806181330-dsw--0-ia5 18-Jun-2018 13:30 2167
ber01-VHDL13_DWPG_181450-1806181450-dsw--0-ia5 18-Jun-2018 14:30 2167
ber01-VHDL13_DWPG_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:30 2096
ber01-VHDL13_DWPG_181630-1806181630-dsw--0-ia5 18-Jun-2018 16:30 2096
ber01-VHDL13_DWPG_181750-1806181750-dsw--0-ia5 18-Jun-2018 17:30 2096
ber01-VHDL13_DWPG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 2214
ber01-VHDL13_DWPG_181800_COR-1806181800-dsw--0-ia5 18-Jun-2018 19:51 2197
ber01-VHDL13_DWPG_181930-1806181930-dsw--0-ia5 18-Jun-2018 19:30 2193
ber01-VHDL13_DWPG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2471
ber01-VHDL13_DWPG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2466
ber01-VHDL13_DWPG_190530-1806190530-dsw--0-ia5 19-Jun-2018 05:30 2465
ber01-VHDL13_DWPG_190630-1806190630-dsw--0-ia5 19-Jun-2018 06:30 2465
ber01-VHDL13_DWPG_190750-1806190750-dsw--0-ia5 19-Jun-2018 07:30 2614
ber01-VHDL13_DWPG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2594
ber01-VHDL13_DWPG_190930-1806190930-dsw--0-ia5 19-Jun-2018 09:30 2594
ber01-VHDL13_DWPG_191030-1806191030-dsw--0-ia5 19-Jun-2018 10:30 2594
ber01-VHDL13_DWPG_191130-1806191130-dsw--0-ia5 19-Jun-2018 11:30 2528
ber01-VHDL13_DWPG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2535
ber01-VHDL13_DWPG_191330-1806191330-dsw--0-ia5 19-Jun-2018 13:30 2535
ber01-VHDL13_DWPG_191450-1806191450-dsw--0-ia5 19-Jun-2018 14:30 2535
ber01-VHDL13_DWPG_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:30 2387
ber01-VHDL13_DWPG_191630-1806191630-dsw--0-ia5 19-Jun-2018 16:30 2387
ber01-VHDL13_DWPG_191750-1806191750-dsw--0-ia5 19-Jun-2018 17:30 2274
ber01-VHDL13_DWPG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2274
ber01-VHDL13_DWPG_191930-1806191930-dsw--0-ia5 19-Jun-2018 19:30 2274
ber01-VHDL13_DWPG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2953
ber01-VHDL13_DWPG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 3111
ber01-VHDL13_DWPG_200530-1806200530-dsw--0-ia5 20-Jun-2018 05:30 3110
ber01-VHDL13_DWPG_200630-1806200630-dsw--0-ia5 20-Jun-2018 06:30 3110
ber01-VHDL13_DWPG_200750-1806200750-dsw--0-ia5 20-Jun-2018 07:30 3110
ber01-VHDL13_DWPG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 3104
ber01-VHDL13_DWPG_200930-1806200930-dsw--0-ia5 20-Jun-2018 09:30 2026
ber01-VHDL13_DWPG_201030-1806201030-dsw--0-ia5 20-Jun-2018 10:30 3101
ber01-VHDL13_DWPH_181130-1806181130-dsw--0-ia5 18-Jun-2018 11:30 2433
ber01-VHDL13_DWPH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 2477
ber01-VHDL13_DWPH_181330-1806181330-dsw--0-ia5 18-Jun-2018 13:30 2477
ber01-VHDL13_DWPH_181450-1806181450-dsw--0-ia5 18-Jun-2018 14:30 2477
ber01-VHDL13_DWPH_181500-1806181500-dsw--0-ia5 18-Jun-2018 15:30 2394
ber01-VHDL13_DWPH_181630-1806181630-dsw--0-ia5 18-Jun-2018 16:30 2394
ber01-VHDL13_DWPH_181750-1806181750-dsw--0-ia5 18-Jun-2018 17:30 2394
ber01-VHDL13_DWPH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 2394
ber01-VHDL13_DWPH_181800_COR-1806181800-dsw--0-ia5 18-Jun-2018 19:12 2611
ber01-VHDL13_DWPH_181930-1806181930-dsw--0-ia5 18-Jun-2018 19:30 2607
ber01-VHDL13_DWPH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2817
ber01-VHDL13_DWPH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2686
ber01-VHDL13_DWPH_190530-1806190530-dsw--0-ia5 19-Jun-2018 05:30 2686
ber01-VHDL13_DWPH_190630-1806190630-dsw--0-ia5 19-Jun-2018 06:30 2686
ber01-VHDL13_DWPH_190750-1806190750-dsw--0-ia5 19-Jun-2018 07:30 2686
ber01-VHDL13_DWPH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2670
ber01-VHDL13_DWPH_190930-1806190930-dsw--0-ia5 19-Jun-2018 09:30 2670
ber01-VHDL13_DWPH_191030-1806191030-dsw--0-ia5 19-Jun-2018 10:30 2670
ber01-VHDL13_DWPH_191130-1806191130-dsw--0-ia5 19-Jun-2018 11:30 2674
ber01-VHDL13_DWPH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2658
ber01-VHDL13_DWPH_191330-1806191330-dsw--0-ia5 19-Jun-2018 13:30 2658
ber01-VHDL13_DWPH_191450-1806191450-dsw--0-ia5 19-Jun-2018 14:30 2658
ber01-VHDL13_DWPH_191500-1806191500-dsw--0-ia5 19-Jun-2018 15:30 2459
ber01-VHDL13_DWPH_191630-1806191630-dsw--0-ia5 19-Jun-2018 16:30 2485
ber01-VHDL13_DWPH_191750-1806191750-dsw--0-ia5 19-Jun-2018 17:30 2485
ber01-VHDL13_DWPH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 2309
ber01-VHDL13_DWPH_191930-1806191930-dsw--0-ia5 19-Jun-2018 19:30 2309
ber01-VHDL13_DWPH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 3023
ber01-VHDL13_DWPH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 3324
ber01-VHDL13_DWPH_200530-1806200530-dsw--0-ia5 20-Jun-2018 05:30 3324
ber01-VHDL13_DWPH_200630-1806200630-dsw--0-ia5 20-Jun-2018 06:30 3324
ber01-VHDL13_DWPH_200750-1806200750-dsw--0-ia5 20-Jun-2018 07:30 3324
ber01-VHDL13_DWPH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 3422
ber01-VHDL13_DWPH_200800_COR-1806200800-dsw--0-ia5 20-Jun-2018 09:59 2307
ber01-VHDL13_DWPH_200930-1806200930-dsw--0-ia5 20-Jun-2018 09:30 2311
ber01-VHDL13_DWPH_201030-1806201030-dsw--0-ia5 20-Jun-2018 10:30 3423
ber01-VHDL13_DWSG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1895
ber01-VHDL13_DWSG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1781
ber01-VHDL13_DWSG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2082
ber01-VHDL13_DWSG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2095
ber01-VHDL13_DWSG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2051
ber01-VHDL13_DWSG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1905
ber01-VHDL13_DWSG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1588
ber01-VHDL13_DWSG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1750
ber01-VHDL13_DWSG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1756
ber01-VHDL13_DWSG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 1906
ber01-VHDL13_DWSN_181300-1806181300-dsw--0-ia5 18-Jun-2018 13:30 1694
ber01-VHDL13_DWSN_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1576
ber01-VHDL13_DWSN_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1726
ber01-VHDL13_DWSN_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1836
ber01-VHDL13_DWSN_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1814
ber01-VHDL13_DWSN_191300-1806191300-dsw--0-ia5 19-Jun-2018 13:30 1728
ber01-VHDL13_DWSN_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1319
ber01-VHDL13_DWSN_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1460
ber01-VHDL13_DWSN_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1459
ber01-VHDL13_DWSN_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 1555
ber01-VHDL13_DWSO_181300-1806181300-dsw--0-ia5 18-Jun-2018 13:30 1838
ber01-VHDL13_DWSO_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1719
ber01-VHDL13_DWSO_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1900
ber01-VHDL13_DWSO_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2039
ber01-VHDL13_DWSO_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2001
ber01-VHDL13_DWSO_191300-1806191300-dsw--0-ia5 19-Jun-2018 13:30 1844
ber01-VHDL13_DWSO_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1469
ber01-VHDL13_DWSO_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1628
ber01-VHDL13_DWSO_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1628
ber01-VHDL13_DWSO_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 1723
ber01-VHDL13_DWSP_181300-1806181300-dsw--0-ia5 18-Jun-2018 13:30 1955
ber01-VHDL13_DWSP_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1718
ber01-VHDL13_DWSP_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1853
ber01-VHDL13_DWSP_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1864
ber01-VHDL13_DWSP_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1865
ber01-VHDL13_DWSP_191300-1806191300-dsw--0-ia5 19-Jun-2018 13:30 1782
ber01-VHDL13_DWSP_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1519
ber01-VHDL13_DWSP_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1687
ber01-VHDL13_DWSP_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1686
ber01-VHDL13_DWSP_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 1781
ber01-VHDL17_DWOG_181200-1806181200-dsw--0-ia5 18-Jun-2018 11:35 3149
ber01-VHDL17_DWOG_191200-1806191200-dsw--0-ia5 19-Jun-2018 11:59 2401
ber01-VHDL17_DWOG_201200-1806201200-dsw--0-ia5 20-Jun-2018 11:24 3215
gts01-VHDL12_DWON_181330-1806181216-afsv--77-ia5 18-Jun-2018 12:16 2530
gts01-VHDL12_DWON_181815-1806181745-afsv--28-ia5 18-Jun-2018 17:45 3108
gts01-VHDL12_DWON_190115-1806190145-afsv--67-ia5 19-Jun-2018 01:45 3015
gts01-VHDL12_DWON_190530-1806190530-afsv--89-ia5 19-Jun-2018 05:30 3081
gts01-VHDL12_DWON_190815-1806190815-afsv--79-ia5 19-Jun-2018 08:15 3175
gts01-VHDL12_DWON_191330-1806191230-afsv--41-ia5 19-Jun-2018 12:30 3165
gts01-VHDL12_DWON_191815-1806191745-afsv--82-ia5 19-Jun-2018 17:45 2861
gts01-VHDL12_DWON_200115-1806200145-afsv--01-ia5 20-Jun-2018 01:45 3010
gts01-VHDL12_DWON_200530-1806200530-afsv--27-ia5 20-Jun-2018 05:30 3125
gts01-VHDL12_DWON_200815-1806200815-afsv--07-ia5 20-Jun-2018 08:15 3708
pid-VHDL12_DWEH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 374
pid-VHDL12_DWEH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 1978
pid-VHDL12_DWHG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1748
pid-VHDL12_DWHG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1732
pid-VHDL12_DWHG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1846
pid-VHDL12_DWHG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1912
pid-VHDL12_DWHH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1871
pid-VHDL12_DWHH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1866
pid-VHDL12_DWHH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2021
pid-VHDL12_DWHH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2029
pid-VHDL12_DWLG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1769
pid-VHDL12_DWLG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1539
pid-VHDL12_DWLG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2019
pid-VHDL12_DWLG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2035
pid-VHDL12_DWLG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2031
pid-VHDL12_DWLG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1985
pid-VHDL12_DWLG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1795
pid-VHDL12_DWLG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2541
pid-VHDL12_DWLG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2544
pid-VHDL12_DWLG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2564
pid-VHDL12_DWLH_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1678
pid-VHDL12_DWLH_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1492
pid-VHDL12_DWLH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2051
pid-VHDL12_DWLH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2065
pid-VHDL12_DWLH_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2059
pid-VHDL12_DWLH_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 2023
pid-VHDL12_DWLH_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1825
pid-VHDL12_DWLH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2624
pid-VHDL12_DWLH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2664
pid-VHDL12_DWLH_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2559
pid-VHDL12_DWLI_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1724
pid-VHDL12_DWLI_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1525
pid-VHDL12_DWLI_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1998
pid-VHDL12_DWLI_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2016
pid-VHDL12_DWLI_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 2013
pid-VHDL12_DWLI_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1968
pid-VHDL12_DWLI_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1779
pid-VHDL12_DWLI_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2362
pid-VHDL12_DWLI_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2360
pid-VHDL12_DWLI_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2324
pid-VHDL12_DWMG_181300-1806181300-dsw--0-ia5 18-Jun-2018 12:30 1674
pid-VHDL12_DWMG_181800-1806181800-dsw--0-ia5 18-Jun-2018 18:30 1336
pid-VHDL12_DWMG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1446
pid-VHDL12_DWMG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 1387
pid-VHDL12_DWMG_190800-1806190800-dsw--0-ia5 19-Jun-2018 08:30 1526
pid-VHDL12_DWMG_191300-1806191300-dsw--0-ia5 19-Jun-2018 12:30 1485
pid-VHDL12_DWMG_191800-1806191800-dsw--0-ia5 19-Jun-2018 18:30 1478
pid-VHDL12_DWMG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1743
pid-VHDL12_DWMG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 1747
pid-VHDL12_DWMG_200800-1806200800-dsw--0-ia5 20-Jun-2018 08:30 2163
pid-VHDL12_DWOG_190100-1806190100-dsw--0-ia5 19-Jun-2018 01:45 2901
pid-VHDL12_DWOG_190300-1806190300-dsw--0-ia5 19-Jun-2018 03:00 2901
pid-VHDL12_DWOG_200100-1806200100-dsw--0-ia5 20-Jun-2018 01:45 2770
pid-VHDL12_DWOG_200300-1806200300-dsw--0-ia5 20-Jun-2018 03:00 2770
pid-VHDL12_DWOH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 1932
pid-VHDL12_DWOH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 1932
pid-VHDL12_DWOI_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:28 1883
pid-VHDL12_DWOI_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:28 1966
pid-VHDL12_DWPG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2095
pid-VHDL12_DWPG_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2002
pid-VHDL12_DWPG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2654
pid-VHDL12_DWPG_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2812
pid-VHDL12_DWPH_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 2374
pid-VHDL12_DWPH_190400-1806190400-dsw--0-ia5 19-Jun-2018 04:30 2162
pid-VHDL12_DWPH_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 2680
pid-VHDL12_DWPH_200400-1806200400-dsw--0-ia5 20-Jun-2018 04:30 2981
pid-VHDL12_DWSG_190200-1806190200-dsw--0-ia5 19-Jun-2018 02:30 1808
pid-VHDL12_DWSG_200200-1806200200-dsw--0-ia5 20-Jun-2018 02:30 1510