Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_030600                                 03-Jul-2020 08:57                5292
FPDL13_DWMZ_040600                                 04-Jul-2020 07:59                3424
SXDL31_DWAV_030800                                 03-Jul-2020 06:41                7951
SXDL31_DWAV_031800                                 03-Jul-2020 15:27               12954
SXDL31_DWAV_040800                                 04-Jul-2020 06:45                9308
SXDL31_DWAV_041800                                 04-Jul-2020 16:48               13013
SXDL33_DWAV_030000                                 03-Jul-2020 09:41               10275
SXDL33_DWAV_040000                                 04-Jul-2020 09:47                9208
ber01-FWDL39_DWMS_031230-2007031230-dsw--0-ia5     03-Jul-2020 12:15                 825
ber01-FWDL39_DWMS_041230-2007041230-dsw--0-ia5     04-Jul-2020 12:27                 727
ber01-VHDL13_DWEH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:28                2510
ber01-VHDL13_DWEH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:58                2486
ber01-VHDL13_DWEH_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2490
ber01-VHDL13_DWEH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:28                2772
ber01-VHDL13_DWEH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:28                2831
ber01-VHDL13_DWEH_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:28                2784
ber01-VHDL13_DWEH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:28                2569
ber01-VHDL13_DWEH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:28                2620
ber01-VHDL13_DWEH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:58                2757
ber01-VHDL13_DWEH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:28                2799
ber01-VHDL13_DWEH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:28                2893
ber01-VHDL13_DWEH_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:28                3059
ber01-VHDL13_DWEH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:28                2638
ber01-VHDL13_DWHG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2653
ber01-VHDL13_DWHG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2677
ber01-VHDL13_DWHG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2812
ber01-VHDL13_DWHG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2790
ber01-VHDL13_DWHG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                2718
ber01-VHDL13_DWHG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2831
ber01-VHDL13_DWHG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2788
ber01-VHDL13_DWHG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2890
ber01-VHDL13_DWHG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2865
ber01-VHDL13_DWHG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2782
ber01-VHDL13_DWHH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2454
ber01-VHDL13_DWHH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2484
ber01-VHDL13_DWHH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2575
ber01-VHDL13_DWHH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2569
ber01-VHDL13_DWHH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                2451
ber01-VHDL13_DWHH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2744
ber01-VHDL13_DWHH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2730
ber01-VHDL13_DWHH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2766
ber01-VHDL13_DWHH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2681
ber01-VHDL13_DWHH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2664
ber01-VHDL13_DWLG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                1926
ber01-VHDL13_DWLG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                1832
ber01-VHDL13_DWLG_030533-2007030533-dsw--0-ia5     03-Jul-2020 05:33                1860
ber01-VHDL13_DWLG_030633-2007030633-dsw--0-ia5     03-Jul-2020 06:33                1866
ber01-VHDL13_DWLG_030733-2007030733-dsw--0-ia5     03-Jul-2020 07:33                1959
ber01-VHDL13_DWLG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                1928
ber01-VHDL13_DWLG_030933-2007030933-dsw--0-ia5     03-Jul-2020 09:33                1959
ber01-VHDL13_DWLG_031033-2007031033-dsw--0-ia5     03-Jul-2020 10:33                1959
ber01-VHDL13_DWLG_031133-2007031133-dsw--0-ia5     03-Jul-2020 11:33                1921
ber01-VHDL13_DWLG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                1892
ber01-VHDL13_DWLG_031333-2007031333-dsw--0-ia5     03-Jul-2020 13:33                1922
ber01-VHDL13_DWLG_031433-2007031433-dsw--0-ia5     03-Jul-2020 14:33                1922
ber01-VHDL13_DWLG_031533-2007031533-dsw--0-ia5     03-Jul-2020 15:33                1922
ber01-VHDL13_DWLG_031633-2007031633-dsw--0-ia5     03-Jul-2020 16:33                1922
ber01-VHDL13_DWLG_031733-2007031733-dsw--0-ia5     03-Jul-2020 17:33                1763
ber01-VHDL13_DWLG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1735
ber01-VHDL13_DWLG_031933-2007031933-dsw--0-ia5     03-Jul-2020 19:33                1763
ber01-VHDL13_DWLG_032033-2007032033-dsw--0-ia5     03-Jul-2020 20:33                1763
ber01-VHDL13_DWLG_040033-2007040033-dsw--0-ia5     04-Jul-2020 00:33                1955
ber01-VHDL13_DWLG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1927
ber01-VHDL13_DWLG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2007
ber01-VHDL13_DWLG_040533-2007040533-dsw--0-ia5     04-Jul-2020 05:33                2035
ber01-VHDL13_DWLG_040633-2007040633-dsw--0-ia5     04-Jul-2020 06:33                2035
ber01-VHDL13_DWLG_040733-2007040733-dsw--0-ia5     04-Jul-2020 07:33                2138
ber01-VHDL13_DWLG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2107
ber01-VHDL13_DWLG_040933-2007040933-dsw--0-ia5     04-Jul-2020 09:33                2138
ber01-VHDL13_DWLG_041033-2007041033-dsw--0-ia5     04-Jul-2020 10:33                2167
ber01-VHDL13_DWLG_041133-2007041133-dsw--0-ia5     04-Jul-2020 11:33                2167
ber01-VHDL13_DWLG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2145
ber01-VHDL13_DWLG_041333-2007041333-dsw--0-ia5     04-Jul-2020 13:33                2111
ber01-VHDL13_DWLG_041433-2007041433-dsw--0-ia5     04-Jul-2020 14:33                2111
ber01-VHDL13_DWLG_041533-2007041533-dsw--0-ia5     04-Jul-2020 15:33                2111
ber01-VHDL13_DWLG_041633-2007041633-dsw--0-ia5     04-Jul-2020 16:33                2136
ber01-VHDL13_DWLG_041733-2007041733-dsw--0-ia5     04-Jul-2020 17:33                2136
ber01-VHDL13_DWLG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1865
ber01-VHDL13_DWLG_041933-2007041933-dsw--0-ia5     04-Jul-2020 19:33                1893
ber01-VHDL13_DWLG_042033-2007042033-dsw--0-ia5     04-Jul-2020 20:33                1893
ber01-VHDL13_DWLG_050033-2007050033-dsw--0-ia5     05-Jul-2020 00:33                2125
ber01-VHDL13_DWLH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2133
ber01-VHDL13_DWLH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2119
ber01-VHDL13_DWLH_030533-2007030533-dsw--0-ia5     03-Jul-2020 05:33                2147
ber01-VHDL13_DWLH_030633-2007030633-dsw--0-ia5     03-Jul-2020 06:33                2079
ber01-VHDL13_DWLH_030733-2007030733-dsw--0-ia5     03-Jul-2020 07:33                2193
ber01-VHDL13_DWLH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2165
ber01-VHDL13_DWLH_030933-2007030933-dsw--0-ia5     03-Jul-2020 09:33                2193
ber01-VHDL13_DWLH_031033-2007031033-dsw--0-ia5     03-Jul-2020 10:33                2193
ber01-VHDL13_DWLH_031133-2007031133-dsw--0-ia5     03-Jul-2020 11:33                2173
ber01-VHDL13_DWLH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2150
ber01-VHDL13_DWLH_031333-2007031333-dsw--0-ia5     03-Jul-2020 13:33                2177
ber01-VHDL13_DWLH_031433-2007031433-dsw--0-ia5     03-Jul-2020 14:33                2177
ber01-VHDL13_DWLH_031533-2007031533-dsw--0-ia5     03-Jul-2020 15:33                2177
ber01-VHDL13_DWLH_031633-2007031633-dsw--0-ia5     03-Jul-2020 16:33                2177
ber01-VHDL13_DWLH_031733-2007031733-dsw--0-ia5     03-Jul-2020 17:33                2162
ber01-VHDL13_DWLH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                2134
ber01-VHDL13_DWLH_031933-2007031933-dsw--0-ia5     03-Jul-2020 19:33                2162
ber01-VHDL13_DWLH_032033-2007032033-dsw--0-ia5     03-Jul-2020 20:33                2162
ber01-VHDL13_DWLH_040033-2007040033-dsw--0-ia5     04-Jul-2020 00:33                2517
ber01-VHDL13_DWLH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2489
ber01-VHDL13_DWLH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2436
ber01-VHDL13_DWLH_040533-2007040533-dsw--0-ia5     04-Jul-2020 05:33                2478
ber01-VHDL13_DWLH_040633-2007040633-dsw--0-ia5     04-Jul-2020 06:33                2469
ber01-VHDL13_DWLH_040733-2007040733-dsw--0-ia5     04-Jul-2020 07:33                2422
ber01-VHDL13_DWLH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2394
ber01-VHDL13_DWLH_040933-2007040933-dsw--0-ia5     04-Jul-2020 09:33                2422
ber01-VHDL13_DWLH_041033-2007041033-dsw--0-ia5     04-Jul-2020 10:33                2403
ber01-VHDL13_DWLH_041133-2007041133-dsw--0-ia5     04-Jul-2020 11:33                2411
ber01-VHDL13_DWLH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2390
ber01-VHDL13_DWLH_041333-2007041333-dsw--0-ia5     04-Jul-2020 13:33                2346
ber01-VHDL13_DWLH_041433-2007041433-dsw--0-ia5     04-Jul-2020 14:33                2346
ber01-VHDL13_DWLH_041533-2007041533-dsw--0-ia5     04-Jul-2020 15:33                2346
ber01-VHDL13_DWLH_041633-2007041633-dsw--0-ia5     04-Jul-2020 16:33                2357
ber01-VHDL13_DWLH_041733-2007041733-dsw--0-ia5     04-Jul-2020 17:33                2357
ber01-VHDL13_DWLH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2144
ber01-VHDL13_DWLH_041933-2007041933-dsw--0-ia5     04-Jul-2020 19:33                2172
ber01-VHDL13_DWLH_042033-2007042033-dsw--0-ia5     04-Jul-2020 20:33                2172
ber01-VHDL13_DWLH_050033-2007050033-dsw--0-ia5     05-Jul-2020 00:33                2274
ber01-VHDL13_DWLI_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                1927
ber01-VHDL13_DWLI_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                1857
ber01-VHDL13_DWLI_030533-2007030533-dsw--0-ia5     03-Jul-2020 05:33                1885
ber01-VHDL13_DWLI_030633-2007030633-dsw--0-ia5     03-Jul-2020 06:33                1915
ber01-VHDL13_DWLI_030733-2007030733-dsw--0-ia5     03-Jul-2020 07:33                1958
ber01-VHDL13_DWLI_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                1930
ber01-VHDL13_DWLI_030933-2007030933-dsw--0-ia5     03-Jul-2020 09:33                1958
ber01-VHDL13_DWLI_031033-2007031033-dsw--0-ia5     03-Jul-2020 10:33                1958
ber01-VHDL13_DWLI_031133-2007031133-dsw--0-ia5     03-Jul-2020 11:33                1931
ber01-VHDL13_DWLI_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                1918
ber01-VHDL13_DWLI_031333-2007031333-dsw--0-ia5     03-Jul-2020 13:33                1951
ber01-VHDL13_DWLI_031433-2007031433-dsw--0-ia5     03-Jul-2020 14:33                1951
ber01-VHDL13_DWLI_031533-2007031533-dsw--0-ia5     03-Jul-2020 15:33                1951
ber01-VHDL13_DWLI_031633-2007031633-dsw--0-ia5     03-Jul-2020 16:33                1951
ber01-VHDL13_DWLI_031733-2007031733-dsw--0-ia5     03-Jul-2020 17:33                1834
ber01-VHDL13_DWLI_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1806
ber01-VHDL13_DWLI_031933-2007031933-dsw--0-ia5     03-Jul-2020 19:33                1834
ber01-VHDL13_DWLI_032033-2007032033-dsw--0-ia5     03-Jul-2020 20:33                1834
ber01-VHDL13_DWLI_040033-2007040033-dsw--0-ia5     04-Jul-2020 00:33                2184
ber01-VHDL13_DWLI_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2156
ber01-VHDL13_DWLI_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2102
ber01-VHDL13_DWLI_040533-2007040533-dsw--0-ia5     04-Jul-2020 05:33                2130
ber01-VHDL13_DWLI_040633-2007040633-dsw--0-ia5     04-Jul-2020 06:33                2130
ber01-VHDL13_DWLI_040733-2007040733-dsw--0-ia5     04-Jul-2020 07:33                2279
ber01-VHDL13_DWLI_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2251
ber01-VHDL13_DWLI_040933-2007040933-dsw--0-ia5     04-Jul-2020 09:33                2279
ber01-VHDL13_DWLI_041033-2007041033-dsw--0-ia5     04-Jul-2020 10:33                2269
ber01-VHDL13_DWLI_041133-2007041133-dsw--0-ia5     04-Jul-2020 11:33                2269
ber01-VHDL13_DWLI_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2248
ber01-VHDL13_DWLI_041333-2007041333-dsw--0-ia5     04-Jul-2020 13:33                2148
ber01-VHDL13_DWLI_041433-2007041433-dsw--0-ia5     04-Jul-2020 14:33                2148
ber01-VHDL13_DWLI_041533-2007041533-dsw--0-ia5     04-Jul-2020 15:33                2148
ber01-VHDL13_DWLI_041633-2007041633-dsw--0-ia5     04-Jul-2020 16:33                2159
ber01-VHDL13_DWLI_041733-2007041733-dsw--0-ia5     04-Jul-2020 17:33                2159
ber01-VHDL13_DWLI_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1891
ber01-VHDL13_DWLI_041933-2007041933-dsw--0-ia5     04-Jul-2020 19:33                1919
ber01-VHDL13_DWLI_042033-2007042033-dsw--0-ia5     04-Jul-2020 20:33                1919
ber01-VHDL13_DWLI_050033-2007050033-dsw--0-ia5     05-Jul-2020 00:33                2099
ber01-VHDL13_DWMG_030100-2007030100-dsw--0-ia5     03-Jul-2020 01:30                2930
ber01-VHDL13_DWMG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2390
ber01-VHDL13_DWMG_030300-2007030300-dsw--0-ia5     03-Jul-2020 03:30                2344
ber01-VHDL13_DWMG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2392
ber01-VHDL13_DWMG_030500-2007030500-dsw--0-ia5     03-Jul-2020 05:30                2392
ber01-VHDL13_DWMG_030600-2007030600-dsw--0-ia5     03-Jul-2020 06:30                2340
ber01-VHDL13_DWMG_030700-2007030700-dsw--0-ia5     03-Jul-2020 07:30                2340
ber01-VHDL13_DWMG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2335
ber01-VHDL13_DWMG_030900-2007030900-dsw--0-ia5     03-Jul-2020 09:30                2335
ber01-VHDL13_DWMG_031000-2007031000-dsw--0-ia5     03-Jul-2020 10:30                2302
ber01-VHDL13_DWMG_031100-2007031100-dsw--0-ia5     03-Jul-2020 11:30                2302
ber01-VHDL13_DWMG_031200-2007031200-dsw--0-ia5     03-Jul-2020 12:30                2333
ber01-VHDL13_DWMG_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                2308
ber01-VHDL13_DWMG_031400-2007031400-dsw--0-ia5     03-Jul-2020 14:30                2308
ber01-VHDL13_DWMG_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:30                2118
ber01-VHDL13_DWMG_031600-2007031600-dsw--0-ia5     03-Jul-2020 16:30                2118
ber01-VHDL13_DWMG_031700-2007031700-dsw--0-ia5     03-Jul-2020 17:30                1897
ber01-VHDL13_DWMG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1875
ber01-VHDL13_DWMG_031900-2007031900-dsw--0-ia5     03-Jul-2020 19:30                1875
ber01-VHDL13_DWMG_032000-2007032000-dsw--0-ia5     03-Jul-2020 20:30                1875
ber01-VHDL13_DWMG_032100-2007032100-dsw--0-ia5     03-Jul-2020 21:30                1875
ber01-VHDL13_DWMG_032200-2007032200-dsw--0-ia5     03-Jul-2020 22:30                1881
ber01-VHDL13_DWMG_032300-2007032300-dsw--0-ia5     03-Jul-2020 23:30                1881
ber01-VHDL13_DWMG_040000-2007040000-dsw--0-ia5     04-Jul-2020 00:30                1881
ber01-VHDL13_DWMG_040100-2007040100-dsw--0-ia5     04-Jul-2020 01:30                1881
ber01-VHDL13_DWMG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1881
ber01-VHDL13_DWMG_040300-2007040300-dsw--0-ia5     04-Jul-2020 03:30                1885
ber01-VHDL13_DWMG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                1956
ber01-VHDL13_DWMG_040500-2007040500-dsw--0-ia5     04-Jul-2020 05:30                2053
ber01-VHDL13_DWMG_040600-2007040600-dsw--0-ia5     04-Jul-2020 06:30                2060
ber01-VHDL13_DWMG_040700-2007040700-dsw--0-ia5     04-Jul-2020 07:30                2060
ber01-VHDL13_DWMG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2281
ber01-VHDL13_DWMG_040900-2007040900-dsw--0-ia5     04-Jul-2020 09:30                2281
ber01-VHDL13_DWMG_041000-2007041000-dsw--0-ia5     04-Jul-2020 10:30                2341
ber01-VHDL13_DWMG_041100-2007041100-dsw--0-ia5     04-Jul-2020 11:30                2341
ber01-VHDL13_DWMG_041200-2007041200-dsw--0-ia5     04-Jul-2020 12:30                2341
ber01-VHDL13_DWMG_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                2295
ber01-VHDL13_DWMG_041400-2007041400-dsw--0-ia5     04-Jul-2020 14:30                2288
ber01-VHDL13_DWMG_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                2288
ber01-VHDL13_DWMG_041600-2007041600-dsw--0-ia5     04-Jul-2020 16:30                2288
ber01-VHDL13_DWMG_041700-2007041700-dsw--0-ia5     04-Jul-2020 17:30                1974
ber01-VHDL13_DWMG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2022
ber01-VHDL13_DWMG_041900-2007041900-dsw--0-ia5     04-Jul-2020 19:30                1977
ber01-VHDL13_DWMG_042000-2007042000-dsw--0-ia5     04-Jul-2020 20:30                1977
ber01-VHDL13_DWMG_042100-2007042100-dsw--0-ia5     04-Jul-2020 21:30                1977
ber01-VHDL13_DWMG_042200-2007042200-dsw--0-ia5     04-Jul-2020 22:30                2034
ber01-VHDL13_DWMG_042300-2007042300-dsw--0-ia5     04-Jul-2020 23:30                2034
ber01-VHDL13_DWMG_050000-2007050000-dsw--0-ia5     05-Jul-2020 00:30                2034
ber01-VHDL13_DWMO_030100-2007030100-dsw--0-ia5     03-Jul-2020 01:30                2166
ber01-VHDL13_DWMO_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2166
ber01-VHDL13_DWMO_030300-2007030300-dsw--0-ia5     03-Jul-2020 03:30                2319
ber01-VHDL13_DWMO_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2177
ber01-VHDL13_DWMO_030500-2007030500-dsw--0-ia5     03-Jul-2020 05:30                2177
ber01-VHDL13_DWMO_030600-2007030600-dsw--0-ia5     03-Jul-2020 06:30                2092
ber01-VHDL13_DWMO_030700-2007030700-dsw--0-ia5     03-Jul-2020 07:30                2092
ber01-VHDL13_DWMO_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2109
ber01-VHDL13_DWMO_030900-2007030900-dsw--0-ia5     03-Jul-2020 09:30                2081
ber01-VHDL13_DWMO_031000-2007031000-dsw--0-ia5     03-Jul-2020 10:30                2058
ber01-VHDL13_DWMO_031100-2007031100-dsw--0-ia5     03-Jul-2020 11:30                2058
ber01-VHDL13_DWMO_031200-2007031200-dsw--0-ia5     03-Jul-2020 12:30                2058
ber01-VHDL13_DWMO_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                2071
ber01-VHDL13_DWMO_031400-2007031400-dsw--0-ia5     03-Jul-2020 14:30                2071
ber01-VHDL13_DWMO_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:30                1857
ber01-VHDL13_DWMO_031600-2007031600-dsw--0-ia5     03-Jul-2020 16:30                1857
ber01-VHDL13_DWMO_031700-2007031700-dsw--0-ia5     03-Jul-2020 17:30                1857
ber01-VHDL13_DWMO_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1857
ber01-VHDL13_DWMO_031900-2007031900-dsw--0-ia5     03-Jul-2020 19:30                1857
ber01-VHDL13_DWMO_032000-2007032000-dsw--0-ia5     03-Jul-2020 20:30                1857
ber01-VHDL13_DWMO_032100-2007032100-dsw--0-ia5     03-Jul-2020 21:30                1857
ber01-VHDL13_DWMO_032200-2007032200-dsw--0-ia5     03-Jul-2020 22:30                2014
ber01-VHDL13_DWMO_032300-2007032300-dsw--0-ia5     03-Jul-2020 23:30                2014
ber01-VHDL13_DWMO_040000-2007040000-dsw--0-ia5     04-Jul-2020 00:30                2014
ber01-VHDL13_DWMO_040100-2007040100-dsw--0-ia5     04-Jul-2020 01:30                2014
ber01-VHDL13_DWMO_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2014
ber01-VHDL13_DWMO_040300-2007040300-dsw--0-ia5     04-Jul-2020 03:30                2014
ber01-VHDL13_DWMO_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2089
ber01-VHDL13_DWMO_040500-2007040500-dsw--0-ia5     04-Jul-2020 05:30                2149
ber01-VHDL13_DWMO_040600-2007040600-dsw--0-ia5     04-Jul-2020 06:30                2213
ber01-VHDL13_DWMO_040700-2007040700-dsw--0-ia5     04-Jul-2020 07:30                2213
ber01-VHDL13_DWMO_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2410
ber01-VHDL13_DWMO_040900-2007040900-dsw--0-ia5     04-Jul-2020 09:30                2382
ber01-VHDL13_DWMO_041000-2007041000-dsw--0-ia5     04-Jul-2020 10:30                2440
ber01-VHDL13_DWMO_041100-2007041100-dsw--0-ia5     04-Jul-2020 11:30                2440
ber01-VHDL13_DWMO_041200-2007041200-dsw--0-ia5     04-Jul-2020 12:30                2440
ber01-VHDL13_DWMO_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                2435
ber01-VHDL13_DWMO_041400-2007041400-dsw--0-ia5     04-Jul-2020 14:30                2438
ber01-VHDL13_DWMO_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                2438
ber01-VHDL13_DWMO_041600-2007041600-dsw--0-ia5     04-Jul-2020 16:30                2438
ber01-VHDL13_DWMO_041700-2007041700-dsw--0-ia5     04-Jul-2020 17:30                2054
ber01-VHDL13_DWMO_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2085
ber01-VHDL13_DWMO_041900-2007041900-dsw--0-ia5     04-Jul-2020 19:30                2085
ber01-VHDL13_DWMO_042000-2007042000-dsw--0-ia5     04-Jul-2020 20:30                2029
ber01-VHDL13_DWMO_042100-2007042100-dsw--0-ia5     04-Jul-2020 21:30                2029
ber01-VHDL13_DWMO_042200-2007042200-dsw--0-ia5     04-Jul-2020 22:30                2160
ber01-VHDL13_DWMO_042300-2007042300-dsw--0-ia5     04-Jul-2020 23:30                2160
ber01-VHDL13_DWMO_050000-2007050000-dsw--0-ia5     05-Jul-2020 00:30                2160
ber01-VHDL13_DWMP_030100-2007030100-dsw--0-ia5     03-Jul-2020 01:30                2818
ber01-VHDL13_DWMP_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2818
ber01-VHDL13_DWMP_030300-2007030300-dsw--0-ia5     03-Jul-2020 03:30                2205
ber01-VHDL13_DWMP_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2256
ber01-VHDL13_DWMP_030500-2007030500-dsw--0-ia5     03-Jul-2020 05:30                2256
ber01-VHDL13_DWMP_030600-2007030600-dsw--0-ia5     03-Jul-2020 06:30                2172
ber01-VHDL13_DWMP_030700-2007030700-dsw--0-ia5     03-Jul-2020 07:30                2172
ber01-VHDL13_DWMP_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2155
ber01-VHDL13_DWMP_030900-2007030900-dsw--0-ia5     03-Jul-2020 09:30                2155
ber01-VHDL13_DWMP_031000-2007031000-dsw--0-ia5     03-Jul-2020 10:30                2107
ber01-VHDL13_DWMP_031100-2007031100-dsw--0-ia5     03-Jul-2020 11:30                2107
ber01-VHDL13_DWMP_031200-2007031200-dsw--0-ia5     03-Jul-2020 12:30                2135
ber01-VHDL13_DWMP_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                2163
ber01-VHDL13_DWMP_031400-2007031400-dsw--0-ia5     03-Jul-2020 14:30                2163
ber01-VHDL13_DWMP_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:30                1963
ber01-VHDL13_DWMP_031600-2007031600-dsw--0-ia5     03-Jul-2020 16:30                1963
ber01-VHDL13_DWMP_031700-2007031700-dsw--0-ia5     03-Jul-2020 17:30                1764
ber01-VHDL13_DWMP_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1747
ber01-VHDL13_DWMP_031900-2007031900-dsw--0-ia5     03-Jul-2020 19:30                1747
ber01-VHDL13_DWMP_032000-2007032000-dsw--0-ia5     03-Jul-2020 20:30                1747
ber01-VHDL13_DWMP_032100-2007032100-dsw--0-ia5     03-Jul-2020 21:30                1747
ber01-VHDL13_DWMP_032200-2007032200-dsw--0-ia5     03-Jul-2020 22:30                1752
ber01-VHDL13_DWMP_032300-2007032300-dsw--0-ia5     03-Jul-2020 23:30                1752
ber01-VHDL13_DWMP_040000-2007040000-dsw--0-ia5     04-Jul-2020 00:30                1752
ber01-VHDL13_DWMP_040100-2007040100-dsw--0-ia5     04-Jul-2020 01:30                1752
ber01-VHDL13_DWMP_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1752
ber01-VHDL13_DWMP_040300-2007040300-dsw--0-ia5     04-Jul-2020 03:30                1752
ber01-VHDL13_DWMP_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                1756
ber01-VHDL13_DWMP_040500-2007040500-dsw--0-ia5     04-Jul-2020 05:30                1756
ber01-VHDL13_DWMP_040600-2007040600-dsw--0-ia5     04-Jul-2020 06:30                1874
ber01-VHDL13_DWMP_040700-2007040700-dsw--0-ia5     04-Jul-2020 07:30                1874
ber01-VHDL13_DWMP_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2028
ber01-VHDL13_DWMP_040900-2007040900-dsw--0-ia5     04-Jul-2020 09:30                2028
ber01-VHDL13_DWMP_041000-2007041000-dsw--0-ia5     04-Jul-2020 10:30                2010
ber01-VHDL13_DWMP_041100-2007041100-dsw--0-ia5     04-Jul-2020 11:30                2010
ber01-VHDL13_DWMP_041200-2007041200-dsw--0-ia5     04-Jul-2020 12:30                2010
ber01-VHDL13_DWMP_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                1947
ber01-VHDL13_DWMP_041400-2007041400-dsw--0-ia5     04-Jul-2020 14:30                1894
ber01-VHDL13_DWMP_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                1894
ber01-VHDL13_DWMP_041600-2007041600-dsw--0-ia5     04-Jul-2020 16:30                1894
ber01-VHDL13_DWMP_041700-2007041700-dsw--0-ia5     04-Jul-2020 17:30                1756
ber01-VHDL13_DWMP_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1748
ber01-VHDL13_DWMP_041900-2007041900-dsw--0-ia5     04-Jul-2020 19:30                1748
ber01-VHDL13_DWMP_042000-2007042000-dsw--0-ia5     04-Jul-2020 20:30                1715
ber01-VHDL13_DWMP_042100-2007042100-dsw--0-ia5     04-Jul-2020 21:30                1715
ber01-VHDL13_DWMP_042200-2007042200-dsw--0-ia5     04-Jul-2020 22:30                1763
ber01-VHDL13_DWMP_042300-2007042300-dsw--0-ia5     04-Jul-2020 23:30                1763
ber01-VHDL13_DWMP_050000-2007050000-dsw--0-ia5     05-Jul-2020 00:30                1763
ber01-VHDL13_DWOG_030100-2007030100-dsw--0-ia5     03-Jul-2020 01:45                3637
ber01-VHDL13_DWOG_030300-2007030300-dsw--0-ia5     03-Jul-2020 03:00                3637
ber01-VHDL13_DWOG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:15                4112
ber01-VHDL13_DWOG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:00                4340
ber01-VHDL13_DWOG_031700-2007031700-dsw--0-ia5     03-Jul-2020 17:30                4095
ber01-VHDL13_DWOG_040100-2007040100-dsw--0-ia5     04-Jul-2020 01:45                4144
ber01-VHDL13_DWOG_040300-2007040300-dsw--0-ia5     04-Jul-2020 03:00                4032
ber01-VHDL13_DWOG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:15                4152
ber01-VHDL13_DWOG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:00                4110
ber01-VHDL13_DWOG_041700-2007041700-dsw--0-ia5     04-Jul-2020 17:30                4163
ber01-VHDL13_DWOH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:28                2236
ber01-VHDL13_DWOH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:58                2215
ber01-VHDL13_DWOH_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2219
ber01-VHDL13_DWOH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:28                2438
ber01-VHDL13_DWOH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:28                2521
ber01-VHDL13_DWOH_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:28                2429
ber01-VHDL13_DWOH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:28                2263
ber01-VHDL13_DWOH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:28                2528
ber01-VHDL13_DWOH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:58                2716
ber01-VHDL13_DWOH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:28                2718
ber01-VHDL13_DWOH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:28                2749
ber01-VHDL13_DWOH_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:28                2768
ber01-VHDL13_DWOH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:28                2441
ber01-VHDL13_DWOI_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:28                2287
ber01-VHDL13_DWOI_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:58                2303
ber01-VHDL13_DWOI_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2307
ber01-VHDL13_DWOI_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:28                2522
ber01-VHDL13_DWOI_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:28                2653
ber01-VHDL13_DWOI_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:28                2579
ber01-VHDL13_DWOI_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:28                2401
ber01-VHDL13_DWOI_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:28                2686
ber01-VHDL13_DWOI_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:58                2874
ber01-VHDL13_DWOI_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:28                2912
ber01-VHDL13_DWOI_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:28                2880
ber01-VHDL13_DWOI_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:28                2942
ber01-VHDL13_DWOI_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:28                2569
ber01-VHDL13_DWON_030139-2007030139-dsw--0-ia5     03-Jul-2020 01:39                3554
ber01-VHDL13_DWON_030337-2007030337-dsw--0-ia5     03-Jul-2020 03:37                3555
ber01-VHDL13_DWON_030530-2007030530-dsw--0-ia5     03-Jul-2020 05:30                3603
ber01-VHDL13_DWON_030652-2007030652-dsw--0-ia5     03-Jul-2020 06:52                4620
ber01-VHDL13_DWON_031115-2007031115-dsw--0-ia5     03-Jul-2020 11:15                4727
ber01-VHDL13_DWON_031530-2007031530-dsw--0-ia5     03-Jul-2020 15:30                4646
ber01-VHDL13_DWON_031655-2007031655-dsw--0-ia5     03-Jul-2020 16:55                3987
ber01-VHDL13_DWON_031844-2007031844-dsw--0-ia5     03-Jul-2020 18:44                3960
ber01-VHDL13_DWON_032139-2007032139-dsw--0-ia5     03-Jul-2020 21:39                3960
ber01-VHDL13_DWON_032335-2007032335-dsw--0-ia5     03-Jul-2020 23:35                3769
ber01-VHDL13_DWON_040126-2007040126-dsw--0-ia5     04-Jul-2020 01:26                3744
ber01-VHDL13_DWON_040244-2007040244-dsw--0-ia5     04-Jul-2020 02:44                3669
ber01-VHDL13_DWON_040516-2007040516-dsw--0-ia5     04-Jul-2020 05:16                4079
ber01-VHDL13_DWON_040748-2007040748-dsw--0-ia5     04-Jul-2020 07:48                4326
ber01-VHDL13_DWON_041042-2007041042-dsw--0-ia5     04-Jul-2020 10:42                4277
ber01-VHDL13_DWON_041204-2007041204-dsw--0-ia5     04-Jul-2020 12:04                4379
ber01-VHDL13_DWON_041419-2007041419-dsw--0-ia5     04-Jul-2020 14:19                4219
ber01-VHDL13_DWON_041706-2007041706-dsw--0-ia5     04-Jul-2020 17:06                3938
ber01-VHDL13_DWON_042037-2007042037-dsw--0-ia5     04-Jul-2020 20:37                3938
ber01-VHDL13_DWON_042108-2007042108-dsw--0-ia5     04-Jul-2020 21:09                4229
ber01-VHDL13_DWON_042317-2007042317-dsw--0-ia5     04-Jul-2020 23:17                4479
ber01-VHDL13_DWPG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2009
ber01-VHDL13_DWPG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2314
ber01-VHDL13_DWPG_030530-2007030530-dsw--0-ia5     03-Jul-2020 05:30                2312
ber01-VHDL13_DWPG_030630-2007030630-dsw--0-ia5     03-Jul-2020 06:30                2270
ber01-VHDL13_DWPG_030730-2007030730-dsw--0-ia5     03-Jul-2020 07:30                2270
ber01-VHDL13_DWPG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2429
ber01-VHDL13_DWPG_030930-2007030930-dsw--0-ia5     03-Jul-2020 09:30                2428
ber01-VHDL13_DWPG_031030-2007031030-dsw--0-ia5     03-Jul-2020 10:30                2428
ber01-VHDL13_DWPG_031130-2007031130-dsw--0-ia5     03-Jul-2020 11:30                2418
ber01-VHDL13_DWPG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2371
ber01-VHDL13_DWPG_031330-2007031330-dsw--0-ia5     03-Jul-2020 13:30                2370
ber01-VHDL13_DWPG_031430-2007031430-dsw--0-ia5     03-Jul-2020 14:30                2370
ber01-VHDL13_DWPG_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:30                2253
ber01-VHDL13_DWPG_031630-2007031630-dsw--0-ia5     03-Jul-2020 16:30                2252
ber01-VHDL13_DWPG_031730-2007031730-dsw--0-ia5     03-Jul-2020 17:30                2252
ber01-VHDL13_DWPG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                2105
ber01-VHDL13_DWPG_031930-2007031930-dsw--0-ia5     03-Jul-2020 19:30                2104
ber01-VHDL13_DWPG_032030-2007032030-dsw--0-ia5     03-Jul-2020 20:30                2104
ber01-VHDL13_DWPG_040030-2007040030-dsw--0-ia5     04-Jul-2020 00:30                2283
ber01-VHDL13_DWPG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2418
ber01-VHDL13_DWPG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2564
ber01-VHDL13_DWPG_040530-2007040530-dsw--0-ia5     04-Jul-2020 05:30                2562
ber01-VHDL13_DWPG_040630-2007040630-dsw--0-ia5     04-Jul-2020 06:30                2562
ber01-VHDL13_DWPG_040730-2007040730-dsw--0-ia5     04-Jul-2020 07:30                2562
ber01-VHDL13_DWPG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2567
ber01-VHDL13_DWPG_040930-2007040930-dsw--0-ia5     04-Jul-2020 09:30                2566
ber01-VHDL13_DWPG_041030-2007041030-dsw--0-ia5     04-Jul-2020 10:30                2566
ber01-VHDL13_DWPG_041130-2007041130-dsw--0-ia5     04-Jul-2020 11:30                2568
ber01-VHDL13_DWPG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2451
ber01-VHDL13_DWPG_041330-2007041330-dsw--0-ia5     04-Jul-2020 13:30                2450
ber01-VHDL13_DWPG_041430-2007041430-dsw--0-ia5     04-Jul-2020 14:30                2450
ber01-VHDL13_DWPG_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                2370
ber01-VHDL13_DWPG_041630-2007041630-dsw--0-ia5     04-Jul-2020 16:30                2369
ber01-VHDL13_DWPG_041730-2007041730-dsw--0-ia5     04-Jul-2020 17:30                2369
ber01-VHDL13_DWPG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2166
ber01-VHDL13_DWPG_041930-2007041930-dsw--0-ia5     04-Jul-2020 19:30                2165
ber01-VHDL13_DWPG_042030-2007042030-dsw--0-ia5     04-Jul-2020 20:30                2165
ber01-VHDL13_DWPG_050030-2007050030-dsw--0-ia5     05-Jul-2020 00:30                2878
ber01-VHDL13_DWPH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2423
ber01-VHDL13_DWPH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2380
ber01-VHDL13_DWPH_030530-2007030530-dsw--0-ia5     03-Jul-2020 05:30                2380
ber01-VHDL13_DWPH_030630-2007030630-dsw--0-ia5     03-Jul-2020 06:30                2191
ber01-VHDL13_DWPH_030730-2007030730-dsw--0-ia5     03-Jul-2020 07:30                2516
ber01-VHDL13_DWPH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2847
ber01-VHDL13_DWPH_030930-2007030930-dsw--0-ia5     03-Jul-2020 09:30                2847
ber01-VHDL13_DWPH_031030-2007031030-dsw--0-ia5     03-Jul-2020 10:30                2847
ber01-VHDL13_DWPH_031130-2007031130-dsw--0-ia5     03-Jul-2020 11:30                2835
ber01-VHDL13_DWPH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2930
ber01-VHDL13_DWPH_031330-2007031330-dsw--0-ia5     03-Jul-2020 13:30                2930
ber01-VHDL13_DWPH_031430-2007031430-dsw--0-ia5     03-Jul-2020 14:30                2930
ber01-VHDL13_DWPH_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:30                2979
ber01-VHDL13_DWPH_031630-2007031630-dsw--0-ia5     03-Jul-2020 16:30                2979
ber01-VHDL13_DWPH_031730-2007031730-dsw--0-ia5     03-Jul-2020 17:30                2979
ber01-VHDL13_DWPH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                2705
ber01-VHDL13_DWPH_031930-2007031930-dsw--0-ia5     03-Jul-2020 19:30                2705
ber01-VHDL13_DWPH_032030-2007032030-dsw--0-ia5     03-Jul-2020 20:30                2705
ber01-VHDL13_DWPH_040030-2007040030-dsw--0-ia5     04-Jul-2020 00:30                2684
ber01-VHDL13_DWPH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                2788
ber01-VHDL13_DWPH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2817
ber01-VHDL13_DWPH_040530-2007040530-dsw--0-ia5     04-Jul-2020 05:30                2817
ber01-VHDL13_DWPH_040630-2007040630-dsw--0-ia5     04-Jul-2020 06:30                2817
ber01-VHDL13_DWPH_040730-2007040730-dsw--0-ia5     04-Jul-2020 07:30                2817
ber01-VHDL13_DWPH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2710
ber01-VHDL13_DWPH_040930-2007040930-dsw--0-ia5     04-Jul-2020 09:30                2710
ber01-VHDL13_DWPH_041030-2007041030-dsw--0-ia5     04-Jul-2020 10:30                2710
ber01-VHDL13_DWPH_041130-2007041130-dsw--0-ia5     04-Jul-2020 11:30                2782
ber01-VHDL13_DWPH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2765
ber01-VHDL13_DWPH_041330-2007041330-dsw--0-ia5     04-Jul-2020 13:30                2765
ber01-VHDL13_DWPH_041430-2007041430-dsw--0-ia5     04-Jul-2020 14:30                2765
ber01-VHDL13_DWPH_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                2796
ber01-VHDL13_DWPH_041630-2007041630-dsw--0-ia5     04-Jul-2020 16:30                2796
ber01-VHDL13_DWPH_041730-2007041730-dsw--0-ia5     04-Jul-2020 17:30                2796
ber01-VHDL13_DWPH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2287
ber01-VHDL13_DWPH_041930-2007041930-dsw--0-ia5     04-Jul-2020 19:30                2287
ber01-VHDL13_DWPH_042030-2007042030-dsw--0-ia5     04-Jul-2020 20:30                2287
ber01-VHDL13_DWPH_050030-2007050030-dsw--0-ia5     05-Jul-2020 00:30                2901
ber01-VHDL13_DWSG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2174
ber01-VHDL13_DWSG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2186
ber01-VHDL13_DWSG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                2072
ber01-VHDL13_DWSG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:30                2144
ber01-VHDL13_DWSG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1794
ber01-VHDL13_DWSG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1948
ber01-VHDL13_DWSG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2482
ber01-VHDL13_DWSG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2484
ber01-VHDL13_DWSG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:30                2416
ber01-VHDL13_DWSG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2095
ber01-VHDL13_DWSN_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                1782
ber01-VHDL13_DWSN_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                1747
ber01-VHDL13_DWSN_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                1714
ber01-VHDL13_DWSN_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                1747
ber01-VHDL13_DWSN_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1530
ber01-VHDL13_DWSN_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1682
ber01-VHDL13_DWSN_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                1939
ber01-VHDL13_DWSN_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                1896
ber01-VHDL13_DWSN_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                1771
ber01-VHDL13_DWSN_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1547
ber01-VHDL13_DWSO_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                1910
ber01-VHDL13_DWSO_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                1973
ber01-VHDL13_DWSO_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                1927
ber01-VHDL13_DWSO_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                2046
ber01-VHDL13_DWSO_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1712
ber01-VHDL13_DWSO_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1898
ber01-VHDL13_DWSO_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                2371
ber01-VHDL13_DWSO_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                2361
ber01-VHDL13_DWSO_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                2188
ber01-VHDL13_DWSO_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1980
ber01-VHDL13_DWSP_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:30                2210
ber01-VHDL13_DWSP_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:30                2073
ber01-VHDL13_DWSP_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:30                1874
ber01-VHDL13_DWSP_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:30                1953
ber01-VHDL13_DWSP_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:30                1681
ber01-VHDL13_DWSP_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:30                1856
ber01-VHDL13_DWSP_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:30                1883
ber01-VHDL13_DWSP_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:30                1885
ber01-VHDL13_DWSP_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:30                1869
ber01-VHDL13_DWSP_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                1677
ber01-VHDL17_DWOG_031200-2007031200-dsw--0-ia5     03-Jul-2020 10:26                3379
ber01-VHDL17_DWOG_041200-2007041200-dsw--0-ia5     04-Jul-2020 10:28                3288
ber01-VHDL20_DWHG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2843
ber01-VHDL20_DWHG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:45                2866
ber01-VHDL20_DWHG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                3001
ber01-VHDL20_DWHG_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:45                2979
ber01-VHDL20_DWHG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2907
ber01-VHDL20_DWHG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                3021
ber01-VHDL20_DWHG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:45                2977
ber01-VHDL20_DWHG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                3079
ber01-VHDL20_DWHG_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:45                3054
ber01-VHDL20_DWHG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2971
ber01-VHDL20_DWHH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2647
ber01-VHDL20_DWHH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:45                2677
ber01-VHDL20_DWHH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2768
ber01-VHDL20_DWHH_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:45                2762
ber01-VHDL20_DWHH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2644
ber01-VHDL20_DWHH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                2937
ber01-VHDL20_DWHH_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:45                2923
ber01-VHDL20_DWHH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                2959
ber01-VHDL20_DWHH_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:45                2874
ber01-VHDL20_DWHH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2857
gts01-VHDL12_DWON_030115-2007030145-afsv--80-ia5   03-Jul-2020 01:45                3139
gts01-VHDL12_DWON_030530-2007030530-afsv--96-ia5   03-Jul-2020 05:30                3140
gts01-VHDL12_DWON_030815-2007030815-afsv--76-ia5   03-Jul-2020 08:15                3954
gts01-VHDL12_DWON_031330-2007031230-afsv--13-ia5   03-Jul-2020 12:30                4065
gts01-VHDL12_DWON_031815-2007031745-afsv--56-ia5   03-Jul-2020 17:45                3287
gts01-VHDL12_DWON_040115-2007040145-afsv--91-ia5   04-Jul-2020 01:45                3391
gts01-VHDL12_DWON_040530-2007040530-afsv--97-ia5   04-Jul-2020 05:30                3723
gts01-VHDL12_DWON_040815-2007040815-afsv--72-ia5   04-Jul-2020 08:15                3976
gts01-VHDL12_DWON_041330-2007041230-afsv--12-ia5   04-Jul-2020 12:30                3915
gts01-VHDL12_DWON_041815-2007041745-afsv--54-ia5   04-Jul-2020 17:45                3421
pid-VHDL12_DWEH_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:28                2100
pid-VHDL12_DWEH_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:28                2290
pid-VHDL12_DWHG_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                2256
pid-VHDL12_DWHG_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                2278
pid-VHDL12_DWHG_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                2310
pid-VHDL12_DWHG_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                2265
pid-VHDL12_DWHH_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                2063
pid-VHDL12_DWHH_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                2093
pid-VHDL12_DWHH_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                2242
pid-VHDL12_DWHH_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                2228
pid-VHDL12_DWLG_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                1575
pid-VHDL12_DWLG_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                1481
pid-VHDL12_DWLG_030800-2007030800-dsw--0-ia5       03-Jul-2020 08:30                1574
pid-VHDL12_DWLG_031300-2007031300-dsw--0-ia5       03-Jul-2020 12:30                1545
pid-VHDL12_DWLG_031800-2007031800-dsw--0-ia5       03-Jul-2020 18:30                1388
pid-VHDL12_DWLG_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                1637
pid-VHDL12_DWLG_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                1688
pid-VHDL12_DWLG_040800-2007040800-dsw--0-ia5       04-Jul-2020 08:30                1800
pid-VHDL12_DWLG_041300-2007041300-dsw--0-ia5       04-Jul-2020 12:30                1835
pid-VHDL12_DWLG_041800-2007041800-dsw--0-ia5       04-Jul-2020 18:30                1530
pid-VHDL12_DWLH_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                1781
pid-VHDL12_DWLH_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                1768
pid-VHDL12_DWLH_030800-2007030800-dsw--0-ia5       03-Jul-2020 08:30                1851
pid-VHDL12_DWLH_031300-2007031300-dsw--0-ia5       03-Jul-2020 12:30                1841
pid-VHDL12_DWLH_031800-2007031800-dsw--0-ia5       03-Jul-2020 18:30                1825
pid-VHDL12_DWLH_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                2225
pid-VHDL12_DWLH_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                2122
pid-VHDL12_DWLH_040800-2007040800-dsw--0-ia5       04-Jul-2020 08:30                2089
pid-VHDL12_DWLH_041300-2007041300-dsw--0-ia5       04-Jul-2020 12:30                2085
pid-VHDL12_DWLH_041800-2007041800-dsw--0-ia5       04-Jul-2020 18:30                1828
pid-VHDL12_DWLI_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                1596
pid-VHDL12_DWLI_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                1526
pid-VHDL12_DWLI_030800-2007030800-dsw--0-ia5       03-Jul-2020 08:30                1627
pid-VHDL12_DWLI_031300-2007031300-dsw--0-ia5       03-Jul-2020 12:30                1622
pid-VHDL12_DWLI_031800-2007031800-dsw--0-ia5       03-Jul-2020 18:30                1510
pid-VHDL12_DWLI_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                1885
pid-VHDL12_DWLI_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                1783
pid-VHDL12_DWLI_040800-2007040800-dsw--0-ia5       04-Jul-2020 08:30                1941
pid-VHDL12_DWLI_041300-2007041300-dsw--0-ia5       04-Jul-2020 12:30                1938
pid-VHDL12_DWLI_041800-2007041800-dsw--0-ia5       04-Jul-2020 18:30                1570
pid-VHDL12_DWMG_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                2103
pid-VHDL12_DWMG_030400-2007030400-dsw--0-ia5       03-Jul-2020 04:30                2105
pid-VHDL12_DWMG_030800-2007030800-dsw--0-ia5       03-Jul-2020 08:30                2029
pid-VHDL12_DWMG_031300-2007031300-dsw--0-ia5       03-Jul-2020 12:30                2027
pid-VHDL12_DWMG_031800-2007031800-dsw--0-ia5       03-Jul-2020 18:30                1582
pid-VHDL12_DWMG_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                1705
pid-VHDL12_DWMG_040400-2007040400-dsw--0-ia5       04-Jul-2020 04:30                1780
pid-VHDL12_DWMG_040800-2007040800-dsw--0-ia5       04-Jul-2020 08:30                2018
pid-VHDL12_DWMG_041300-2007041300-dsw--0-ia5       04-Jul-2020 12:30                2078
pid-VHDL12_DWMG_041800-2007041800-dsw--0-ia5       04-Jul-2020 18:30                1759
pid-VHDL12_DWOG_030100-2007030100-dsw--0-ia5       03-Jul-2020 01:45                3136
pid-VHDL12_DWOG_030300-2007030300-dsw--0-ia5       03-Jul-2020 03:00                3136
pid-VHDL12_DWOG_040100-2007040100-dsw--0-ia5       04-Jul-2020 01:45                3688
pid-VHDL12_DWOG_040300-2007040300-dsw--0-ia5       04-Jul-2020 03:00                3567
pid-VHDL12_DWOH_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:28                1780
pid-VHDL12_DWOH_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:28                2227
pid-VHDL12_DWOI_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:28                1832
pid-VHDL12_DWOI_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:28                2395
pid-VHDL12_DWSG_030200-2007030200-dsw--0-ia5       03-Jul-2020 02:30                1768
pid-VHDL12_DWSG_040200-2007040200-dsw--0-ia5       04-Jul-2020 02:30                1670
swis2-VHDL20_DWEG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2396
swis2-VHDL20_DWEG_030400-2007030400-dsw--0-ia5     03-Jul-2020 05:15                2422
swis2-VHDL20_DWEG_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2426
swis2-VHDL20_DWEG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2645
swis2-VHDL20_DWEG_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:45                2736
swis2-VHDL20_DWEG_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:45                2636
swis2-VHDL20_DWEG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2476
swis2-VHDL20_DWEG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                2688
swis2-VHDL20_DWEG_040400-2007040400-dsw--0-ia5     04-Jul-2020 05:15                2923
swis2-VHDL20_DWEG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                2925
swis2-VHDL20_DWEG_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:45                2964
swis2-VHDL20_DWEG_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:45                2975
swis2-VHDL20_DWEG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2654
swis2-VHDL20_DWEH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2702
swis2-VHDL20_DWEH_030400-2007030400-dsw--0-ia5     03-Jul-2020 05:15                2692
swis2-VHDL20_DWEH_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2696
swis2-VHDL20_DWEH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2978
swis2-VHDL20_DWEH_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:45                3037
swis2-VHDL20_DWEH_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:45                2990
swis2-VHDL20_DWEH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2797
swis2-VHDL20_DWEH_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                2812
swis2-VHDL20_DWEH_040400-2007040400-dsw--0-ia5     04-Jul-2020 05:15                2963
swis2-VHDL20_DWEH_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                3005
swis2-VHDL20_DWEH_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:45                3099
swis2-VHDL20_DWEH_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:45                3265
swis2-VHDL20_DWEH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2866
swis2-VHDL20_DWEI_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2448
swis2-VHDL20_DWEI_030400-2007030400-dsw--0-ia5     03-Jul-2020 05:15                2516
swis2-VHDL20_DWEI_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16                2520
swis2-VHDL20_DWEI_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2729
swis2-VHDL20_DWEI_031300-2007031300-dsw--0-ia5     03-Jul-2020 12:45                2866
swis2-VHDL20_DWEI_031500-2007031500-dsw--0-ia5     03-Jul-2020 15:45                2792
swis2-VHDL20_DWEI_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2614
swis2-VHDL20_DWEI_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                2847
swis2-VHDL20_DWEI_040400-2007040400-dsw--0-ia5     04-Jul-2020 05:15                3087
swis2-VHDL20_DWEI_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                3119
swis2-VHDL20_DWEI_041300-2007041300-dsw--0-ia5     04-Jul-2020 12:45                3093
swis2-VHDL20_DWEI_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:45                3155
swis2-VHDL20_DWEI_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2782
swis2-VHDL20_DWHG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2843
swis2-VHDL20_DWHG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:45                2866
swis2-VHDL20_DWHG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                3001
swis2-VHDL20_DWHG_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:45                2979
swis2-VHDL20_DWHG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2907
swis2-VHDL20_DWHG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                3021
swis2-VHDL20_DWHG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:45                2977
swis2-VHDL20_DWHG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                3079
swis2-VHDL20_DWHG_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:45                3054
swis2-VHDL20_DWHG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2971
swis2-VHDL20_DWHH_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2647
swis2-VHDL20_DWHH_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:45                2677
swis2-VHDL20_DWHH_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2768
swis2-VHDL20_DWHH_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:45                2762
swis2-VHDL20_DWHH_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2644
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swis2-VHDL20_DWPH_041130-2007041130-dsw--0-ia5     04-Jul-2020 11:30                2969
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swis2-VHDL20_DWPH_041330-2007041330-dsw--0-ia5     04-Jul-2020 13:30                2952
swis2-VHDL20_DWPH_041430-2007041430-dsw--0-ia5     04-Jul-2020 14:30                2952
swis2-VHDL20_DWPH_041500-2007041500-dsw--0-ia5     04-Jul-2020 15:30                2983
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swis2-VHDL20_DWPH_041730-2007041730-dsw--0-ia5     04-Jul-2020 17:30                2983
swis2-VHDL20_DWPH_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:30                2474
swis2-VHDL20_DWPH_041930-2007041930-dsw--0-ia5     04-Jul-2020 19:30                2474
swis2-VHDL20_DWPH_042030-2007042030-dsw--0-ia5     04-Jul-2020 20:30                2474
swis2-VHDL20_DWSG_030200-2007030200-dsw--0-ia5     03-Jul-2020 02:45                2408
swis2-VHDL20_DWSG_030400-2007030400-dsw--0-ia5     03-Jul-2020 04:45                2417
swis2-VHDL20_DWSG_030800-2007030800-dsw--0-ia5     03-Jul-2020 08:45                2302
swis2-VHDL20_DWSG_031300-2007031300-dsw--0-ia5     03-Jul-2020 13:45                2376
swis2-VHDL20_DWSG_031800-2007031800-dsw--0-ia5     03-Jul-2020 18:45                2026
swis2-VHDL20_DWSG_040200-2007040200-dsw--0-ia5     04-Jul-2020 02:45                2182
swis2-VHDL20_DWSG_040400-2007040400-dsw--0-ia5     04-Jul-2020 04:45                2713
swis2-VHDL20_DWSG_040800-2007040800-dsw--0-ia5     04-Jul-2020 08:45                2714
swis2-VHDL20_DWSG_041300-2007041300-dsw--0-ia5     04-Jul-2020 13:45                2561
swis2-VHDL20_DWSG_041800-2007041800-dsw--0-ia5     04-Jul-2020 18:45                2327
wst04-VHDL20_DWEG_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              246845
wst04-VHDL20_DWEG_030400-2007030400-omedes--0.pdf  03-Jul-2020 05:15              247476
wst04-VHDL20_DWEG_030400_COR-2007030400-omedes-..> 03-Jul-2020 05:16              247466
wst04-VHDL20_DWEG_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              245275
wst04-VHDL20_DWEG_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              246166
wst04-VHDL20_DWEG_031500-2007031500-omedes--0.pdf  03-Jul-2020 15:45              245573
wst04-VHDL20_DWEG_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:45              244995
wst04-VHDL20_DWEG_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              246036
wst04-VHDL20_DWEG_040400-2007040400-omedes--0.pdf  04-Jul-2020 05:15              246252
wst04-VHDL20_DWEG_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              248033
wst04-VHDL20_DWEG_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              248151
wst04-VHDL20_DWEG_041500-2007041500-omedes--0.pdf  04-Jul-2020 15:45              247860
wst04-VHDL20_DWEG_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              247433
wst04-VHDL20_DWEH_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              237738
wst04-VHDL20_DWEH_030400-2007030400-omedes--0.pdf  03-Jul-2020 05:15              237876
wst04-VHDL20_DWEH_030400_COR-2007030400-omedes-..> 03-Jul-2020 05:16              237876
wst04-VHDL20_DWEH_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              245153
wst04-VHDL20_DWEH_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              245509
wst04-VHDL20_DWEH_031500-2007031500-omedes--0.pdf  03-Jul-2020 15:45              245525
wst04-VHDL20_DWEH_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:45              244693
wst04-VHDL20_DWEH_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              245512
wst04-VHDL20_DWEH_040400-2007040400-omedes--0.pdf  04-Jul-2020 05:15              244677
wst04-VHDL20_DWEH_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              249521
wst04-VHDL20_DWEH_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              249607
wst04-VHDL20_DWEH_041500-2007041500-omedes--0.pdf  04-Jul-2020 15:45              250172
wst04-VHDL20_DWEH_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              249508
wst04-VHDL20_DWEI_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              339492
wst04-VHDL20_DWEI_030400-2007030400-omedes--0.pdf  03-Jul-2020 05:15              339601
wst04-VHDL20_DWEI_030400_COR-2007030400-omedes-..> 03-Jul-2020 05:16              339601
wst04-VHDL20_DWEI_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              335479
wst04-VHDL20_DWEI_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              336373
wst04-VHDL20_DWEI_031500-2007031500-omedes--0.pdf  03-Jul-2020 15:45              336247
wst04-VHDL20_DWEI_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:45              335598
wst04-VHDL20_DWEI_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              336804
wst04-VHDL20_DWEI_040400-2007040400-omedes--0.pdf  04-Jul-2020 05:15              336471
wst04-VHDL20_DWEI_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              343390
wst04-VHDL20_DWEI_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              343460
wst04-VHDL20_DWEI_041500-2007041500-omedes--0.pdf  04-Jul-2020 15:45              343258
wst04-VHDL20_DWEI_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              342187
wst04-VHDL20_DWHG_030200-2007030200-oflxs888--0..> 03-Jul-2020 02:45              338605
wst04-VHDL20_DWHG_030400-2007030400-oflxs888--0..> 03-Jul-2020 04:45              338479
wst04-VHDL20_DWHG_030800-2007030800-oflxs888--0..> 03-Jul-2020 08:45              335763
wst04-VHDL20_DWHG_031300-2007031300-oflxs888--0..> 03-Jul-2020 13:45              335236
wst04-VHDL20_DWHG_031800-2007031800-oflxs888--0..> 03-Jul-2020 18:45              335184
wst04-VHDL20_DWHG_040200-2007040200-oflxs888--0..> 04-Jul-2020 02:45              335630
wst04-VHDL20_DWHG_040400-2007040400-oflxs888--0..> 04-Jul-2020 04:45              335615
wst04-VHDL20_DWHG_040800-2007040800-oflxs888--0..> 04-Jul-2020 08:45              333998
wst04-VHDL20_DWHG_041300-2007041300-oflxs888--0..> 04-Jul-2020 13:45              333429
wst04-VHDL20_DWHG_041800-2007041800-oflxs888--0..> 04-Jul-2020 18:45              333468
wst04-VHDL20_DWHH_030200-2007030200-oflxs888--0..> 03-Jul-2020 02:45              329985
wst04-VHDL20_DWHH_030400-2007030400-oflxs888--0..> 03-Jul-2020 04:45              329911
wst04-VHDL20_DWHH_030800-2007030800-oflxs888--0..> 03-Jul-2020 08:45              341141
wst04-VHDL20_DWHH_031300-2007031300-oflxs888--0..> 03-Jul-2020 13:45              340730
wst04-VHDL20_DWHH_031800-2007031800-oflxs888--0..> 03-Jul-2020 18:45              340646
wst04-VHDL20_DWHH_040200-2007040200-oflxs888--0..> 04-Jul-2020 02:45              340831
wst04-VHDL20_DWHH_040400-2007040400-oflxs888--0..> 04-Jul-2020 04:45              340810
wst04-VHDL20_DWHH_040800-2007040800-oflxs888--0..> 04-Jul-2020 08:45              336067
wst04-VHDL20_DWHH_041300-2007041300-oflxs888--0..> 04-Jul-2020 13:45              335999
wst04-VHDL20_DWHH_041800-2007041800-oflxs888--0..> 04-Jul-2020 18:45              336098
wst04-VHDL20_DWLG_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:40              241525
wst04-VHDL20_DWLG_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:40              240967
wst04-VHDL20_DWLG_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:40              243676
wst04-VHDL20_DWLG_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:40              243414
wst04-VHDL20_DWLG_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:40              243358
wst04-VHDL20_DWLG_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:40              243493
wst04-VHDL20_DWLG_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:40              243600
wst04-VHDL20_DWLG_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:40              240818
wst04-VHDL20_DWLG_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:40              241051
wst04-VHDL20_DWLG_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:40              240855
wst04-VHDL20_DWLH_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:40              243253
wst04-VHDL20_DWLH_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:40              242392
wst04-VHDL20_DWLH_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:40              238849
wst04-VHDL20_DWLH_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:40              238716
wst04-VHDL20_DWLH_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:40              239174
wst04-VHDL20_DWLH_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:40              239075
wst04-VHDL20_DWLH_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:40              238687
wst04-VHDL20_DWLH_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:40              242501
wst04-VHDL20_DWLH_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:40              242737
wst04-VHDL20_DWLH_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:40              242607
wst04-VHDL20_DWLI_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:40              243873
wst04-VHDL20_DWLI_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:40              243321
wst04-VHDL20_DWLI_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:40              239708
wst04-VHDL20_DWLI_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:40              239504
wst04-VHDL20_DWLI_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:40              239711
wst04-VHDL20_DWLI_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:40              239993
wst04-VHDL20_DWLI_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:40              239742
wst04-VHDL20_DWLI_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:40              242449
wst04-VHDL20_DWLI_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:40              242701
wst04-VHDL20_DWLI_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:40              242438
wst04-VHDL20_DWMG_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              246481
wst04-VHDL20_DWMG_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:45              245917
wst04-VHDL20_DWMG_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              246175
wst04-VHDL20_DWMG_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              246237
wst04-VHDL20_DWMG_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:46              245045
wst04-VHDL20_DWMG_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              246101
wst04-VHDL20_DWMG_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:45              245773
wst04-VHDL20_DWMG_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              247112
wst04-VHDL20_DWMG_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              247173
wst04-VHDL20_DWMG_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              246918
wst04-VHDL20_DWMO_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              249074
wst04-VHDL20_DWMO_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:45              249506
wst04-VHDL20_DWMO_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              245145
wst04-VHDL20_DWMO_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              245141
wst04-VHDL20_DWMO_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:46              245317
wst04-VHDL20_DWMO_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              245488
wst04-VHDL20_DWMO_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:45              246174
wst04-VHDL20_DWMO_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              247666
wst04-VHDL20_DWMO_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              247997
wst04-VHDL20_DWMO_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              247668
wst04-VHDL20_DWMP_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              246617
wst04-VHDL20_DWMP_030200_COR-2007030200-omedes-..> 03-Jul-2020 02:53              245246
wst04-VHDL20_DWMP_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:45              245333
wst04-VHDL20_DWMP_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              245997
wst04-VHDL20_DWMP_031300-2007031300-omedes--0.pdf  03-Jul-2020 12:45              245967
wst04-VHDL20_DWMP_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:46              245527
wst04-VHDL20_DWMP_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              245511
wst04-VHDL20_DWMP_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:45              245596
wst04-VHDL20_DWMP_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              247052
wst04-VHDL20_DWMP_041300-2007041300-omedes--0.pdf  04-Jul-2020 12:45              247028
wst04-VHDL20_DWMP_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              246852
wst04-VHDL20_DWPG_030200-2007030200-oflxs892--0..> 03-Jul-2020 02:30              333877
wst04-VHDL20_DWPG_030400-2007030400-oflxs892--0..> 03-Jul-2020 04:30              335259
wst04-VHDL20_DWPG_030530-2007030530-oflxs892--0..> 03-Jul-2020 05:30              334803
wst04-VHDL20_DWPG_030630-2007030630-oflxs892--0..> 03-Jul-2020 06:30              334333
wst04-VHDL20_DWPG_030730-2007030730-oflxs892--0..> 03-Jul-2020 07:30              334717
wst04-VHDL20_DWPG_030800-2007030800-oflxs892--0..> 03-Jul-2020 08:30              367272
wst04-VHDL20_DWPG_030930-2007030930-oflxs892--0..> 03-Jul-2020 09:30              322690
wst04-VHDL20_DWPG_031030-2007031030-oflxs892--0..> 03-Jul-2020 10:30              322690
wst04-VHDL20_DWPG_031130-2007031130-oflxs892--0..> 03-Jul-2020 11:30              322703
wst04-VHDL20_DWPG_031300-2007031300-oflxs892--0..> 03-Jul-2020 12:30              322720
wst04-VHDL20_DWPG_031330-2007031330-oflxs892--0..> 03-Jul-2020 13:30              322702
wst04-VHDL20_DWPG_031430-2007031430-oflxs892--0..> 03-Jul-2020 14:30              323128
wst04-VHDL20_DWPG_031500-2007031500-oflxs892--0..> 03-Jul-2020 15:30              322600
wst04-VHDL20_DWPG_031630-2007031630-oflxs892--0..> 03-Jul-2020 16:30              322584
wst04-VHDL20_DWPG_031730-2007031730-oflxs892--0..> 03-Jul-2020 17:30              322948
wst04-VHDL20_DWPG_031800-2007031800-oflxs892--0..> 03-Jul-2020 18:30              321949
wst04-VHDL20_DWPG_031930-2007031930-oflxs892--0..> 03-Jul-2020 19:30              321931
wst04-VHDL20_DWPG_032030-2007032030-oflxs892--0..> 03-Jul-2020 20:30              321931
wst04-VHDL20_DWPG_040200-2007040200-oflxs892--0..> 04-Jul-2020 02:30              322528
wst04-VHDL20_DWPG_040400-2007040400-oflxs892--0..> 04-Jul-2020 04:30              322760
wst04-VHDL20_DWPG_040530-2007040530-oflxs892--0..> 04-Jul-2020 05:30              322615
wst04-VHDL20_DWPG_040630-2007040630-oflxs892--0..> 04-Jul-2020 06:30              322615
wst04-VHDL20_DWPG_040730-2007040730-oflxs892--0..> 04-Jul-2020 07:30              322982
wst04-VHDL20_DWPG_040800-2007040800-oflxs892--0..> 04-Jul-2020 08:30              379287
wst04-VHDL20_DWPG_040930-2007040930-oflxs892--0..> 04-Jul-2020 09:30              335029
wst04-VHDL20_DWPG_041030-2007041030-oflxs892--0..> 04-Jul-2020 10:30              335029
wst04-VHDL20_DWPG_041130-2007041130-oflxs892--0..> 04-Jul-2020 11:30              334776
wst04-VHDL20_DWPG_041300-2007041300-oflxs892--0..> 04-Jul-2020 12:30              335315
wst04-VHDL20_DWPG_041330-2007041330-oflxs892--0..> 04-Jul-2020 13:30              335261
wst04-VHDL20_DWPG_041430-2007041430-oflxs892--0..> 04-Jul-2020 14:30              335668
wst04-VHDL20_DWPG_041500-2007041500-oflxs892--0..> 04-Jul-2020 15:30              335277
wst04-VHDL20_DWPG_041630-2007041630-oflxs892--0..> 04-Jul-2020 16:30              335246
wst04-VHDL20_DWPG_041730-2007041730-oflxs892--0..> 04-Jul-2020 17:30              335246
wst04-VHDL20_DWPG_041800-2007041800-oflxs892--0..> 04-Jul-2020 18:30              334498
wst04-VHDL20_DWPG_041930-2007041930-oflxs892--0..> 04-Jul-2020 19:30              334490
wst04-VHDL20_DWPG_042030-2007042030-oflxs892--0..> 04-Jul-2020 20:30              334490
wst04-VHDL20_DWPH_030200-2007030200-oflxs892--0..> 03-Jul-2020 02:30              247534
wst04-VHDL20_DWPH_030400-2007030400-oflxs892--0..> 03-Jul-2020 04:30              247470
wst04-VHDL20_DWPH_030530-2007030530-oflxs892--0..> 03-Jul-2020 05:30              247415
wst04-VHDL20_DWPH_030630-2007030630-oflxs892--0..> 03-Jul-2020 06:30              247325
wst04-VHDL20_DWPH_030730-2007030730-oflxs892--0..> 03-Jul-2020 07:30              247941
wst04-VHDL20_DWPH_030800-2007030800-oflxs892--0..> 03-Jul-2020 08:30              289489
wst04-VHDL20_DWPH_030930-2007030930-oflxs892--0..> 03-Jul-2020 09:30              244869
wst04-VHDL20_DWPH_031030-2007031030-oflxs892--0..> 03-Jul-2020 10:30              244869
wst04-VHDL20_DWPH_031130-2007031130-oflxs892--0..> 03-Jul-2020 11:30              244874
wst04-VHDL20_DWPH_031300-2007031300-oflxs892--0..> 03-Jul-2020 12:30              244936
wst04-VHDL20_DWPH_031330-2007031330-oflxs892--0..> 03-Jul-2020 13:30              244912
wst04-VHDL20_DWPH_031430-2007031430-oflxs892--0..> 03-Jul-2020 14:30              244553
wst04-VHDL20_DWPH_031500-2007031500-oflxs892--0..> 03-Jul-2020 15:30              244612
wst04-VHDL20_DWPH_031630-2007031630-oflxs892--0..> 03-Jul-2020 16:30              244583
wst04-VHDL20_DWPH_031730-2007031730-oflxs892--0..> 03-Jul-2020 17:30              244951
wst04-VHDL20_DWPH_031800-2007031800-oflxs892--0..> 03-Jul-2020 18:30              288444
wst04-VHDL20_DWPH_031930-2007031930-oflxs892--0..> 03-Jul-2020 19:30              243801
wst04-VHDL20_DWPH_032030-2007032030-oflxs892--0..> 03-Jul-2020 20:30              243802
wst04-VHDL20_DWPH_040200-2007040200-oflxs892--0..> 04-Jul-2020 02:30              244579
wst04-VHDL20_DWPH_040400-2007040400-oflxs892--0..> 04-Jul-2020 04:30              244430
wst04-VHDL20_DWPH_040530-2007040530-oflxs892--0..> 04-Jul-2020 05:30              244365
wst04-VHDL20_DWPH_040630-2007040630-oflxs892--0..> 04-Jul-2020 06:30              244365
wst04-VHDL20_DWPH_040730-2007040730-oflxs892--0..> 04-Jul-2020 07:30              244365
wst04-VHDL20_DWPH_040800-2007040800-oflxs892--0..> 04-Jul-2020 08:30              289398
wst04-VHDL20_DWPH_040930-2007040930-oflxs892--0..> 04-Jul-2020 09:30              244808
wst04-VHDL20_DWPH_041030-2007041030-oflxs892--0..> 04-Jul-2020 10:30              244808
wst04-VHDL20_DWPH_041130-2007041130-oflxs892--0..> 04-Jul-2020 11:30              245359
wst04-VHDL20_DWPH_041300-2007041300-oflxs892--0..> 04-Jul-2020 12:30              245342
wst04-VHDL20_DWPH_041330-2007041330-oflxs892--0..> 04-Jul-2020 13:30              245300
wst04-VHDL20_DWPH_041430-2007041430-oflxs892--0..> 04-Jul-2020 14:30              245300
wst04-VHDL20_DWPH_041500-2007041500-oflxs892--0..> 04-Jul-2020 15:30              245409
wst04-VHDL20_DWPH_041630-2007041630-oflxs892--0..> 04-Jul-2020 16:30              245381
wst04-VHDL20_DWPH_041730-2007041730-oflxs892--0..> 04-Jul-2020 17:30              245381
wst04-VHDL20_DWPH_041800-2007041800-oflxs892--0..> 04-Jul-2020 18:30              288867
wst04-VHDL20_DWPH_041930-2007041930-oflxs892--0..> 04-Jul-2020 19:30              244241
wst04-VHDL20_DWPH_042030-2007042030-oflxs892--0..> 04-Jul-2020 20:30              244241
wst04-VHDL20_DWSG_030200-2007030200-omedes--0.pdf  03-Jul-2020 02:45              245838
wst04-VHDL20_DWSG_030400-2007030400-omedes--0.pdf  03-Jul-2020 04:45              245584
wst04-VHDL20_DWSG_030800-2007030800-omedes--0.pdf  03-Jul-2020 08:45              244152
wst04-VHDL20_DWSG_031300-2007031300-omedes--0.pdf  03-Jul-2020 13:45              243587
wst04-VHDL20_DWSG_031800-2007031800-omedes--0.pdf  03-Jul-2020 18:45              242847
wst04-VHDL20_DWSG_040200-2007040200-omedes--0.pdf  04-Jul-2020 02:45              243544
wst04-VHDL20_DWSG_040400-2007040400-omedes--0.pdf  04-Jul-2020 04:45              243757
wst04-VHDL20_DWSG_040800-2007040800-omedes--0.pdf  04-Jul-2020 08:45              242227
wst04-VHDL20_DWSG_041300-2007041300-omedes--0.pdf  04-Jul-2020 13:45              241761
wst04-VHDL20_DWSG_041800-2007041800-omedes--0.pdf  04-Jul-2020 18:45              242057