Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_260600 26-Feb-2026 13:15:08 3265
FPDL13_DWMZ_270600 27-Feb-2026 13:52:56 2848
SXDL31_DWAV_260800 26-Feb-2026 07:41:34 7337
SXDL31_DWAV_261800 26-Feb-2026 17:38:53 5416
SXDL31_DWAV_270800 27-Feb-2026 08:59:35 12242
SXDL31_DWAV_271800 27-Feb-2026 17:28:14 5334
SXDL31_DWAV_LATEST 27-Feb-2026 17:28:14 5334
SXDL33_DWAV_260000 26-Feb-2026 10:28:49 9240
SXDL33_DWAV_270000 27-Feb-2026 09:00:15 7561
SXDL33_DWAV_LATEST 27-Feb-2026 09:00:15 7561
ber01-FWDL39_DWMS_261230-2602261230-dsw--0-ia5 26-Feb-2026 11:54:42 1473
ber01-FWDL39_DWMS_271230-2602271230-dsw--0-ia5 27-Feb-2026 12:57:42 1335
ber01-VHDL13_DWEH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:18 2267
ber01-VHDL13_DWEH_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:16 2287
ber01-VHDL13_DWEH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2278
ber01-VHDL13_DWEH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:16 2570
ber01-VHDL13_DWEH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:11 2781
ber01-VHDL13_DWEH_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:16 2796
ber01-VHDL13_DWEH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:17 2925
ber01-VHDL13_DWEH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:16 2792
ber01-VHDL13_DWHG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2466
ber01-VHDL13_DWHG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2473
ber01-VHDL13_DWHG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2462
ber01-VHDL13_DWHG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:10 2332
ber01-VHDL13_DWHG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2324
ber01-VHDL13_DWHG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2369
ber01-VHDL13_DWHG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2633
ber01-VHDL13_DWHG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2848
ber01-VHDL13_DWHH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2587
ber01-VHDL13_DWHH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2592
ber01-VHDL13_DWHH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2493
ber01-VHDL13_DWHH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:10 2500
ber01-VHDL13_DWHH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2477
ber01-VHDL13_DWHH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:07 2490
ber01-VHDL13_DWHH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 2381
ber01-VHDL13_DWHH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2475
ber01-VHDL13_DWLG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2214
ber01-VHDL13_DWLG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2324
ber01-VHDL13_DWLG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2175
ber01-VHDL13_DWLG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1895
ber01-VHDL13_DWLG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2258
ber01-VHDL13_DWLG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 1934
ber01-VHDL13_DWLG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 1920
ber01-VHDL13_DWLG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1817
ber01-VHDL13_DWLH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2348
ber01-VHDL13_DWLH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2553
ber01-VHDL13_DWLH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2726
ber01-VHDL13_DWLH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2328
ber01-VHDL13_DWLH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2513
ber01-VHDL13_DWLH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2399
ber01-VHDL13_DWLH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2399
ber01-VHDL13_DWLH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 2245
ber01-VHDL13_DWLI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2811
ber01-VHDL13_DWLI_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2661
ber01-VHDL13_DWLI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2495
ber01-VHDL13_DWLI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2241
ber01-VHDL13_DWLI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2447
ber01-VHDL13_DWLI_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2130
ber01-VHDL13_DWLI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 2142
ber01-VHDL13_DWLI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1855
ber01-VHDL13_DWMG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2929
ber01-VHDL13_DWMG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 2946
ber01-VHDL13_DWMG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2945
ber01-VHDL13_DWMG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2499
ber01-VHDL13_DWMG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2765
ber01-VHDL13_DWMG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2775
ber01-VHDL13_DWMG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2540
ber01-VHDL13_DWMG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2209
ber01-VHDL13_DWMO_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 3012
ber01-VHDL13_DWMO_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 2989
ber01-VHDL13_DWMO_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 3077
ber01-VHDL13_DWMO_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2389
ber01-VHDL13_DWMO_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2770
ber01-VHDL13_DWMO_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2762
ber01-VHDL13_DWMO_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2774
ber01-VHDL13_DWMO_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2360
ber01-VHDL13_DWMP_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2996
ber01-VHDL13_DWMP_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:03 3008
ber01-VHDL13_DWMP_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2874
ber01-VHDL13_DWMP_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2385
ber01-VHDL13_DWMP_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:10 2699
ber01-VHDL13_DWMP_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:02 2690
ber01-VHDL13_DWMP_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2465
ber01-VHDL13_DWMP_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2210
ber01-VHDL13_DWOG_260300-2602260300-dsw--0-ia5 26-Feb-2026 04:00:02 3697
ber01-VHDL13_DWOG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:03 3017
ber01-VHDL13_DWOG_261700-2602261700-dsw--0-ia5 26-Feb-2026 19:00:01 3326
ber01-VHDL13_DWOG_270300-2602270300-dsw--0-ia5 27-Feb-2026 04:00:06 3986
ber01-VHDL13_DWOG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 3774
ber01-VHDL13_DWOG_271700-2602271700-dsw--0-ia5 27-Feb-2026 19:00:07 3360
ber01-VHDL13_DWOH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:12 2220
ber01-VHDL13_DWOH_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:12 2113
ber01-VHDL13_DWOH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2184
ber01-VHDL13_DWOH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:16 2243
ber01-VHDL13_DWOH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:11 2554
ber01-VHDL13_DWOH_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:11 2548
ber01-VHDL13_DWOH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:17 2678
ber01-VHDL13_DWOH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:16 2505
ber01-VHDL13_DWOI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:28:12 2234
ber01-VHDL13_DWOI_260400-2602260400-dsw--0-ia5 26-Feb-2026 05:58:16 2160
ber01-VHDL13_DWOI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:28:16 2268
ber01-VHDL13_DWOI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:28:12 2336
ber01-VHDL13_DWOI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:28:16 2565
ber01-VHDL13_DWOI_270400-2602270400-dsw--0-ia5 27-Feb-2026 05:58:16 2615
ber01-VHDL13_DWOI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:28:12 2651
ber01-VHDL13_DWOI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:28:12 2542
ber01-VHDL13_DWON_260358-2602260358-dsw--0-ia5 26-Feb-2026 03:58:12 3861
ber01-VHDL13_DWON_260613-2602260613-dsw--0-ia5 26-Feb-2026 06:13:41 3346
ber01-VHDL13_DWON_260649-2602260649-dsw--0-ia5 26-Feb-2026 06:50:02 3346
ber01-VHDL13_DWON_260911-2602260911-dsw--0-ia5 26-Feb-2026 09:11:58 3290
ber01-VHDL13_DWON_260946-2602260946-dsw--0-ia5 26-Feb-2026 09:46:37 3290
ber01-VHDL13_DWON_261553-2602261553-dsw--0-ia5 26-Feb-2026 15:53:21 2947
ber01-VHDL13_DWON_261742-2602261742-dsw--0-ia5 26-Feb-2026 17:43:01 2947
ber01-VHDL13_DWON_262240-2602262240-dsw--0-ia5 26-Feb-2026 22:40:17 3080
ber01-VHDL13_DWON_270232-2602270232-dsw--0-ia5 27-Feb-2026 02:32:47 3486
ber01-VHDL13_DWON_270635-2602270635-dsw--0-ia5 27-Feb-2026 06:35:21 3769
ber01-VHDL13_DWON_270710-2602270710-dsw--0-ia5 27-Feb-2026 07:10:43 3769
ber01-VHDL13_DWON_270919-2602270919-dsw--0-ia5 27-Feb-2026 09:19:57 3689
ber01-VHDL13_DWON_270958-2602270958-dsw--0-ia5 27-Feb-2026 09:58:26 3689
ber01-VHDL13_DWON_271555-2602271555-dsw--0-ia5 27-Feb-2026 15:55:22 2818
ber01-VHDL13_DWON_271729-2602271729-dsw--0-ia5 27-Feb-2026 17:29:22 2818
ber01-VHDL13_DWPG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2213
ber01-VHDL13_DWPG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2298
ber01-VHDL13_DWPG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2192
ber01-VHDL13_DWPG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1896
ber01-VHDL13_DWPG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2039
ber01-VHDL13_DWPG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2051
ber01-VHDL13_DWPG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:06 1945
ber01-VHDL13_DWPG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1819
ber01-VHDL13_DWPH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:07 2249
ber01-VHDL13_DWPH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:01 2138
ber01-VHDL13_DWPH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2138
ber01-VHDL13_DWPH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 1903
ber01-VHDL13_DWPH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2194
ber01-VHDL13_DWPH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:00 2205
ber01-VHDL13_DWPH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2068
ber01-VHDL13_DWPH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:07 1860
ber01-VHDL13_DWSG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:30:02 2870
ber01-VHDL13_DWSG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2663
ber01-VHDL13_DWSG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:30:08 2618
ber01-VHDL13_DWSG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:30:05 2408
ber01-VHDL13_DWSG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:30:01 2513
ber01-VHDL13_DWSG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2474
ber01-VHDL13_DWSG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:30:07 2402
ber01-VHDL13_DWSG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:30:03 2179
ber01-VHDL17_DWOG_261200-2602261200-dsw--0-ia5 26-Feb-2026 11:51:11 2913
ber01-VHDL17_DWOG_271200-2602271200-dsw--0-ia5 27-Feb-2026 11:52:51 2512
swis2-VHDL20_DWEG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2499
swis2-VHDL20_DWEG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2433
swis2-VHDL20_DWEG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2662
swis2-VHDL20_DWEG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2569
swis2-VHDL20_DWEG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2830
swis2-VHDL20_DWEG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 2871
swis2-VHDL20_DWEG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3159
swis2-VHDL20_DWEG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2832
swis2-VHDL20_DWEH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2591
swis2-VHDL20_DWEH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2622
swis2-VHDL20_DWEH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2781
swis2-VHDL20_DWEH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2924
swis2-VHDL20_DWEH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 3102
swis2-VHDL20_DWEH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 3134
swis2-VHDL20_DWEH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3431
swis2-VHDL20_DWEH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 3147
swis2-VHDL20_DWEI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2526
swis2-VHDL20_DWEI_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:15:01 2511
swis2-VHDL20_DWEI_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:06 2793
swis2-VHDL20_DWEI_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2687
swis2-VHDL20_DWEI_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2857
swis2-VHDL20_DWEI_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:15:07 2969
swis2-VHDL20_DWEI_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3179
swis2-VHDL20_DWEI_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2894
swis2-VHDL20_DWHG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2652
swis2-VHDL20_DWHG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2656
swis2-VHDL20_DWHG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2996
swis2-VHDL20_DWHG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:06 2515
swis2-VHDL20_DWHG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:06 2510
swis2-VHDL20_DWHG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:06 2552
swis2-VHDL20_DWHG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 3167
swis2-VHDL20_DWHG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 3031
swis2-VHDL20_DWHH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:07 2773
swis2-VHDL20_DWHH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:07 2778
swis2-VHDL20_DWHH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 3036
swis2-VHDL20_DWHH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:06 2686
swis2-VHDL20_DWHH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:06 2663
swis2-VHDL20_DWHH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:07 2676
swis2-VHDL20_DWHH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:08 2924
swis2-VHDL20_DWHH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2661
swis2-VHDL20_DWLG_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2559
swis2-VHDL20_DWLG_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2668
swis2-VHDL20_DWLG_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 2665
swis2-VHDL20_DWLG_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2239
swis2-VHDL20_DWLG_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2602
swis2-VHDL20_DWLG_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2276
swis2-VHDL20_DWLG_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2408
swis2-VHDL20_DWLG_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2159
swis2-VHDL20_DWLH_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 2700
swis2-VHDL20_DWLH_260400-2602260400-dsw--0-ia5 26-Feb-2026 06:00:17 2902
swis2-VHDL20_DWLH_260800-2602260800-dsw--0-ia5 26-Feb-2026 09:45:02 3225
swis2-VHDL20_DWLH_261800-2602261800-dsw--0-ia5 26-Feb-2026 19:45:02 2677
swis2-VHDL20_DWLH_270200-2602270200-dsw--0-ia5 27-Feb-2026 03:45:02 2862
swis2-VHDL20_DWLH_270400-2602270400-dsw--0-ia5 27-Feb-2026 06:00:11 2748
swis2-VHDL20_DWLH_270800-2602270800-dsw--0-ia5 27-Feb-2026 09:45:02 2898
swis2-VHDL20_DWLH_271800-2602271800-dsw--0-ia5 27-Feb-2026 19:45:02 2594
swis2-VHDL20_DWLI_260200-2602260200-dsw--0-ia5 26-Feb-2026 03:45:05 3158
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