Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_170600 17-Oct-2019 08:13 3042
FPDL13_DWMZ_180600 18-Oct-2019 10:26 5514
SXDL31_DWAV_170800 17-Oct-2019 07:35 12840
SXDL31_DWAV_171800 17-Oct-2019 17:31 8230
SXDL31_DWAV_180800 18-Oct-2019 07:23 8297
SXDL31_DWAV_181800 18-Oct-2019 17:05 13519
SXDL33_DWAV_170000 17-Oct-2019 11:06 6652
SXDL33_DWAV_180000 18-Oct-2019 10:22 10272
ber01-FWDL39_DWMS_171230-1910171230-dsw--0-ia5 17-Oct-2019 12:34 812
ber01-FWDL39_DWMS_181230-1910181230-dsw--0-ia5 18-Oct-2019 12:28 857
ber01-VHDL13_DWEH_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:58 2687
ber01-VHDL13_DWEH_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:28 3098
ber01-VHDL13_DWEH_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:28 3053
ber01-VHDL13_DWEH_171500-1910171500-dsw--0-ia5 17-Oct-2019 15:28 3019
ber01-VHDL13_DWEH_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:28 2826
ber01-VHDL13_DWEH_171800_COR-1910171800-dsw--0-ia5 17-Oct-2019 19:37 2827
ber01-VHDL13_DWEH_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:28 2677
ber01-VHDL13_DWEH_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:58 2856
ber01-VHDL13_DWEH_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:28 2778
ber01-VHDL13_DWEH_180800_COR-1910180800-dsw--0-ia5 18-Oct-2019 10:12 2802
ber01-VHDL13_DWEH_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:28 2914
ber01-VHDL13_DWEH_181500-1910181500-dsw--0-ia5 18-Oct-2019 15:28 2914
ber01-VHDL13_DWEH_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:28 2561
ber01-VHDL13_DWEH_181800_COR-1910181800-dsw--0-ia5 18-Oct-2019 19:14 1992
ber01-VHDL13_DWEH_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:28 2152
ber01-VHDL13_DWHG_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 1845
ber01-VHDL13_DWHG_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2388
ber01-VHDL13_DWHG_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2440
ber01-VHDL13_DWHG_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 2211
ber01-VHDL13_DWHG_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2505
ber01-VHDL13_DWHG_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2501
ber01-VHDL13_DWHG_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 2429
ber01-VHDL13_DWHG_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 2364
ber01-VHDL13_DWHG_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 1632
ber01-VHDL13_DWHG_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 1694
ber01-VHDL13_DWHH_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 1986
ber01-VHDL13_DWHH_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2460
ber01-VHDL13_DWHH_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2502
ber01-VHDL13_DWHH_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 2222
ber01-VHDL13_DWHH_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2640
ber01-VHDL13_DWHH_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2633
ber01-VHDL13_DWHH_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 2654
ber01-VHDL13_DWHH_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 2594
ber01-VHDL13_DWHH_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 1834
ber01-VHDL13_DWHH_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 1832
ber01-VHDL13_DWLG_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 1937
ber01-VHDL13_DWLG_170533-1910170533-dsw--0-ia5 17-Oct-2019 05:33 1965
ber01-VHDL13_DWLG_170633-1910170633-dsw--0-ia5 17-Oct-2019 06:33 1982
ber01-VHDL13_DWLG_170733-1910170733-dsw--0-ia5 17-Oct-2019 07:33 1982
ber01-VHDL13_DWLG_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2047
ber01-VHDL13_DWLG_170933-1910170933-dsw--0-ia5 17-Oct-2019 09:33 2078
ber01-VHDL13_DWLG_171033-1910171033-dsw--0-ia5 17-Oct-2019 10:33 2125
ber01-VHDL13_DWLG_171133-1910171133-dsw--0-ia5 17-Oct-2019 11:33 2125
ber01-VHDL13_DWLG_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2057
ber01-VHDL13_DWLG_171333-1910171333-dsw--0-ia5 17-Oct-2019 13:33 2085
ber01-VHDL13_DWLG_171433-1910171433-dsw--0-ia5 17-Oct-2019 14:33 1985
ber01-VHDL13_DWLG_171533-1910171533-dsw--0-ia5 17-Oct-2019 15:33 1985
ber01-VHDL13_DWLG_171633-1910171633-dsw--0-ia5 17-Oct-2019 16:33 1985
ber01-VHDL13_DWLG_171733-1910171733-dsw--0-ia5 17-Oct-2019 17:33 1840
ber01-VHDL13_DWLG_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 1812
ber01-VHDL13_DWLG_171933-1910171933-dsw--0-ia5 17-Oct-2019 19:33 1840
ber01-VHDL13_DWLG_172033-1910172033-dsw--0-ia5 17-Oct-2019 20:33 1840
ber01-VHDL13_DWLG_180033-1910180033-dsw--0-ia5 18-Oct-2019 00:33 2013
ber01-VHDL13_DWLG_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2365
ber01-VHDL13_DWLG_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2364
ber01-VHDL13_DWLG_180533-1910180533-dsw--0-ia5 18-Oct-2019 05:33 2392
ber01-VHDL13_DWLG_180633-1910180633-dsw--0-ia5 18-Oct-2019 06:33 2510
ber01-VHDL13_DWLG_180733-1910180733-dsw--0-ia5 18-Oct-2019 07:33 2500
ber01-VHDL13_DWLG_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 2469
ber01-VHDL13_DWLG_180933-1910180933-dsw--0-ia5 18-Oct-2019 09:33 2500
ber01-VHDL13_DWLG_181033-1910181033-dsw--0-ia5 18-Oct-2019 10:33 2495
ber01-VHDL13_DWLG_181133-1910181133-dsw--0-ia5 18-Oct-2019 11:33 2495
ber01-VHDL13_DWLG_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 2273
ber01-VHDL13_DWLG_181333-1910181333-dsw--0-ia5 18-Oct-2019 13:33 2301
ber01-VHDL13_DWLG_181433-1910181433-dsw--0-ia5 18-Oct-2019 14:33 2344
ber01-VHDL13_DWLG_181533-1910181533-dsw--0-ia5 18-Oct-2019 15:33 2344
ber01-VHDL13_DWLG_181633-1910181633-dsw--0-ia5 18-Oct-2019 16:33 2354
ber01-VHDL13_DWLG_181733-1910181733-dsw--0-ia5 18-Oct-2019 17:33 1979
ber01-VHDL13_DWLG_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 1945
ber01-VHDL13_DWLG_181933-1910181933-dsw--0-ia5 18-Oct-2019 19:33 1973
ber01-VHDL13_DWLG_182033-1910182033-dsw--0-ia5 18-Oct-2019 20:33 1973
ber01-VHDL13_DWLG_190033-1910190033-dsw--0-ia5 19-Oct-2019 00:33 1955
ber01-VHDL13_DWLG_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 1962
ber01-VHDL13_DWLH_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 2181
ber01-VHDL13_DWLH_170533-1910170533-dsw--0-ia5 17-Oct-2019 05:33 2209
ber01-VHDL13_DWLH_170633-1910170633-dsw--0-ia5 17-Oct-2019 06:33 2333
ber01-VHDL13_DWLH_170733-1910170733-dsw--0-ia5 17-Oct-2019 07:33 2379
ber01-VHDL13_DWLH_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2377
ber01-VHDL13_DWLH_170933-1910170933-dsw--0-ia5 17-Oct-2019 09:33 2405
ber01-VHDL13_DWLH_171033-1910171033-dsw--0-ia5 17-Oct-2019 10:33 2371
ber01-VHDL13_DWLH_171133-1910171133-dsw--0-ia5 17-Oct-2019 11:33 2371
ber01-VHDL13_DWLH_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2364
ber01-VHDL13_DWLH_171333-1910171333-dsw--0-ia5 17-Oct-2019 13:33 2392
ber01-VHDL13_DWLH_171433-1910171433-dsw--0-ia5 17-Oct-2019 14:33 2319
ber01-VHDL13_DWLH_171533-1910171533-dsw--0-ia5 17-Oct-2019 15:33 2319
ber01-VHDL13_DWLH_171633-1910171633-dsw--0-ia5 17-Oct-2019 16:33 2319
ber01-VHDL13_DWLH_171733-1910171733-dsw--0-ia5 17-Oct-2019 17:33 2156
ber01-VHDL13_DWLH_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 2128
ber01-VHDL13_DWLH_171933-1910171933-dsw--0-ia5 17-Oct-2019 19:33 2156
ber01-VHDL13_DWLH_172033-1910172033-dsw--0-ia5 17-Oct-2019 20:33 2156
ber01-VHDL13_DWLH_180033-1910180033-dsw--0-ia5 18-Oct-2019 00:33 2366
ber01-VHDL13_DWLH_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2847
ber01-VHDL13_DWLH_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2797
ber01-VHDL13_DWLH_180533-1910180533-dsw--0-ia5 18-Oct-2019 05:33 2825
ber01-VHDL13_DWLH_180633-1910180633-dsw--0-ia5 18-Oct-2019 06:33 3326
ber01-VHDL13_DWLH_180733-1910180733-dsw--0-ia5 18-Oct-2019 07:33 3255
ber01-VHDL13_DWLH_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 3227
ber01-VHDL13_DWLH_180933-1910180933-dsw--0-ia5 18-Oct-2019 09:33 3255
ber01-VHDL13_DWLH_181033-1910181033-dsw--0-ia5 18-Oct-2019 10:33 3243
ber01-VHDL13_DWLH_181133-1910181133-dsw--0-ia5 18-Oct-2019 11:33 3243
ber01-VHDL13_DWLH_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 3261
ber01-VHDL13_DWLH_181333-1910181333-dsw--0-ia5 18-Oct-2019 13:33 3289
ber01-VHDL13_DWLH_181433-1910181433-dsw--0-ia5 18-Oct-2019 14:33 3059
ber01-VHDL13_DWLH_181533-1910181533-dsw--0-ia5 18-Oct-2019 15:33 3059
ber01-VHDL13_DWLH_181633-1910181633-dsw--0-ia5 18-Oct-2019 16:33 2879
ber01-VHDL13_DWLH_181733-1910181733-dsw--0-ia5 18-Oct-2019 17:33 2167
ber01-VHDL13_DWLH_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 2131
ber01-VHDL13_DWLH_181933-1910181933-dsw--0-ia5 18-Oct-2019 19:33 2159
ber01-VHDL13_DWLH_182033-1910182033-dsw--0-ia5 18-Oct-2019 20:33 2159
ber01-VHDL13_DWLH_190033-1910190033-dsw--0-ia5 19-Oct-2019 00:33 2353
ber01-VHDL13_DWLH_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 2292
ber01-VHDL13_DWLI_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 1917
ber01-VHDL13_DWLI_170533-1910170533-dsw--0-ia5 17-Oct-2019 05:33 1945
ber01-VHDL13_DWLI_170633-1910170633-dsw--0-ia5 17-Oct-2019 06:33 2102
ber01-VHDL13_DWLI_170733-1910170733-dsw--0-ia5 17-Oct-2019 07:33 2148
ber01-VHDL13_DWLI_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2321
ber01-VHDL13_DWLI_170933-1910170933-dsw--0-ia5 17-Oct-2019 09:33 2349
ber01-VHDL13_DWLI_171033-1910171033-dsw--0-ia5 17-Oct-2019 10:33 2319
ber01-VHDL13_DWLI_171133-1910171133-dsw--0-ia5 17-Oct-2019 11:33 2319
ber01-VHDL13_DWLI_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2251
ber01-VHDL13_DWLI_171333-1910171333-dsw--0-ia5 17-Oct-2019 13:33 2279
ber01-VHDL13_DWLI_171433-1910171433-dsw--0-ia5 17-Oct-2019 14:33 2208
ber01-VHDL13_DWLI_171533-1910171533-dsw--0-ia5 17-Oct-2019 15:33 2208
ber01-VHDL13_DWLI_171633-1910171633-dsw--0-ia5 17-Oct-2019 16:33 2208
ber01-VHDL13_DWLI_171733-1910171733-dsw--0-ia5 17-Oct-2019 17:33 2064
ber01-VHDL13_DWLI_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 2036
ber01-VHDL13_DWLI_171933-1910171933-dsw--0-ia5 17-Oct-2019 19:33 2064
ber01-VHDL13_DWLI_172033-1910172033-dsw--0-ia5 17-Oct-2019 20:33 2064
ber01-VHDL13_DWLI_180033-1910180033-dsw--0-ia5 18-Oct-2019 00:33 2273
ber01-VHDL13_DWLI_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2425
ber01-VHDL13_DWLI_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2371
ber01-VHDL13_DWLI_180533-1910180533-dsw--0-ia5 18-Oct-2019 05:33 2399
ber01-VHDL13_DWLI_180633-1910180633-dsw--0-ia5 18-Oct-2019 06:33 2766
ber01-VHDL13_DWLI_180733-1910180733-dsw--0-ia5 18-Oct-2019 07:33 2695
ber01-VHDL13_DWLI_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 2667
ber01-VHDL13_DWLI_180933-1910180933-dsw--0-ia5 18-Oct-2019 09:33 2695
ber01-VHDL13_DWLI_181033-1910181033-dsw--0-ia5 18-Oct-2019 10:33 2744
ber01-VHDL13_DWLI_181133-1910181133-dsw--0-ia5 18-Oct-2019 11:33 2744
ber01-VHDL13_DWLI_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 2666
ber01-VHDL13_DWLI_181333-1910181333-dsw--0-ia5 18-Oct-2019 13:33 2694
ber01-VHDL13_DWLI_181433-1910181433-dsw--0-ia5 18-Oct-2019 14:33 2564
ber01-VHDL13_DWLI_181533-1910181533-dsw--0-ia5 18-Oct-2019 15:33 2564
ber01-VHDL13_DWLI_181633-1910181633-dsw--0-ia5 18-Oct-2019 16:33 2561
ber01-VHDL13_DWLI_181733-1910181733-dsw--0-ia5 18-Oct-2019 17:33 1981
ber01-VHDL13_DWLI_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 1950
ber01-VHDL13_DWLI_181933-1910181933-dsw--0-ia5 18-Oct-2019 19:33 1978
ber01-VHDL13_DWLI_182033-1910182033-dsw--0-ia5 18-Oct-2019 20:33 1978
ber01-VHDL13_DWLI_190033-1910190033-dsw--0-ia5 19-Oct-2019 00:33 1986
ber01-VHDL13_DWLI_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 1972
ber01-VHDL13_DWMG_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 2794
ber01-VHDL13_DWMG_170500-1910170500-dsw--0-ia5 17-Oct-2019 05:30 2644
ber01-VHDL13_DWMG_170600-1910170600-dsw--0-ia5 17-Oct-2019 06:30 2643
ber01-VHDL13_DWMG_170700-1910170700-dsw--0-ia5 17-Oct-2019 07:30 2752
ber01-VHDL13_DWMG_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2744
ber01-VHDL13_DWMG_170900-1910170900-dsw--0-ia5 17-Oct-2019 09:30 2570
ber01-VHDL13_DWMG_171000-1910171000-dsw--0-ia5 17-Oct-2019 10:30 2500
ber01-VHDL13_DWMG_171100-1910171100-dsw--0-ia5 17-Oct-2019 11:30 2500
ber01-VHDL13_DWMG_171200-1910171200-dsw--0-ia5 17-Oct-2019 12:30 2500
ber01-VHDL13_DWMG_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2500
ber01-VHDL13_DWMG_171400-1910171400-dsw--0-ia5 17-Oct-2019 14:30 2433
ber01-VHDL13_DWMG_171500-1910171500-dsw--0-ia5 17-Oct-2019 15:30 2433
ber01-VHDL13_DWMG_171600-1910171600-dsw--0-ia5 17-Oct-2019 16:30 2290
ber01-VHDL13_DWMG_171700-1910171700-dsw--0-ia5 17-Oct-2019 17:30 2290
ber01-VHDL13_DWMG_171800-1910171800-dsw--0-ia5 17-Oct-2019 18:30 2290
ber01-VHDL13_DWMG_171900-1910171900-dsw--0-ia5 17-Oct-2019 19:30 2374
ber01-VHDL13_DWMG_172000-1910172000-dsw--0-ia5 17-Oct-2019 20:30 2368
ber01-VHDL13_DWMG_172100-1910172100-dsw--0-ia5 17-Oct-2019 21:30 2368
ber01-VHDL13_DWMG_172200-1910172200-dsw--0-ia5 17-Oct-2019 22:30 2637
ber01-VHDL13_DWMG_172300-1910172300-dsw--0-ia5 17-Oct-2019 23:30 2847
ber01-VHDL13_DWMG_180000-1910180000-dsw--0-ia5 18-Oct-2019 00:30 2847
ber01-VHDL13_DWMG_180100-1910180100-dsw--0-ia5 18-Oct-2019 01:30 2847
ber01-VHDL13_DWMG_180200-1910180200-dsw--0-ia5 18-Oct-2019 02:30 2847
ber01-VHDL13_DWMG_180300-1910180300-dsw--0-ia5 18-Oct-2019 03:30 2847
ber01-VHDL13_DWMG_180400-1910180400-dsw--0-ia5 18-Oct-2019 04:30 2839
ber01-VHDL13_DWMG_180500-1910180500-dsw--0-ia5 18-Oct-2019 05:30 2839
ber01-VHDL13_DWMG_180600-1910180600-dsw--0-ia5 18-Oct-2019 06:30 2839
ber01-VHDL13_DWMG_180700-1910180700-dsw--0-ia5 18-Oct-2019 07:30 2839
ber01-VHDL13_DWMG_180800-1910180800-dsw--0-ia5 18-Oct-2019 08:30 3232
ber01-VHDL13_DWMG_180900-1910180900-dsw--0-ia5 18-Oct-2019 09:30 3232
ber01-VHDL13_DWMG_181000-1910181000-dsw--0-ia5 18-Oct-2019 10:30 3232
ber01-VHDL13_DWMG_181100-1910181100-dsw--0-ia5 18-Oct-2019 11:30 3232
ber01-VHDL13_DWMG_181200-1910181200-dsw--0-ia5 18-Oct-2019 12:30 3232
ber01-VHDL13_DWMG_181300-1910181300-dsw--0-ia5 18-Oct-2019 12:30 3232
ber01-VHDL13_DWMG_181400-1910181400-dsw--0-ia5 18-Oct-2019 14:30 3075
ber01-VHDL13_DWMG_181500-1910181500-dsw--0-ia5 18-Oct-2019 15:30 3078
ber01-VHDL13_DWMG_181600-1910181600-dsw--0-ia5 18-Oct-2019 16:30 2584
ber01-VHDL13_DWMG_181700-1910181700-dsw--0-ia5 18-Oct-2019 17:30 2584
ber01-VHDL13_DWMG_181800-1910181800-dsw--0-ia5 18-Oct-2019 18:30 2584
ber01-VHDL13_DWMG_181900-1910181900-dsw--0-ia5 18-Oct-2019 19:30 2614
ber01-VHDL13_DWMG_182000-1910182000-dsw--0-ia5 18-Oct-2019 20:30 2632
ber01-VHDL13_DWMG_182100-1910182100-dsw--0-ia5 18-Oct-2019 21:30 2632
ber01-VHDL13_DWMG_182200-1910182200-dsw--0-ia5 18-Oct-2019 22:30 2741
ber01-VHDL13_DWMG_182300-1910182300-dsw--0-ia5 18-Oct-2019 23:30 2779
ber01-VHDL13_DWMG_190000-1910190000-dsw--0-ia5 19-Oct-2019 00:30 2779
ber01-VHDL13_DWMG_190100-1910190100-dsw--0-ia5 19-Oct-2019 01:30 2779
ber01-VHDL13_DWMG_190200-1910190200-dsw--0-ia5 19-Oct-2019 02:30 2779
ber01-VHDL13_DWMG_190300-1910190300-dsw--0-ia5 19-Oct-2019 03:30 2779
ber01-VHDL13_DWMO_170400-1910170400-dsw--0-ia5 17-Oct-2019 04:30 2459
ber01-VHDL13_DWMO_170500-1910170500-dsw--0-ia5 17-Oct-2019 05:30 2395
ber01-VHDL13_DWMO_170600-1910170600-dsw--0-ia5 17-Oct-2019 06:30 2395
ber01-VHDL13_DWMO_170700-1910170700-dsw--0-ia5 17-Oct-2019 07:30 2473
ber01-VHDL13_DWMO_170800-1910170800-dsw--0-ia5 17-Oct-2019 08:30 2601
ber01-VHDL13_DWMO_170900-1910170900-dsw--0-ia5 17-Oct-2019 09:30 2524
ber01-VHDL13_DWMO_171000-1910171000-dsw--0-ia5 17-Oct-2019 10:30 2465
ber01-VHDL13_DWMO_171100-1910171100-dsw--0-ia5 17-Oct-2019 11:30 2465
ber01-VHDL13_DWMO_171200-1910171200-dsw--0-ia5 17-Oct-2019 12:30 2465
ber01-VHDL13_DWMO_171300-1910171300-dsw--0-ia5 17-Oct-2019 12:30 2465
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