Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_230600 23-Jun-2019 08:16 7211
FPDL13_DWMZ_240600 24-Jun-2019 09:04 4626
SXDL31_DWAV_230800 23-Jun-2019 06:39 5014
SXDL31_DWAV_231800 23-Jun-2019 16:33 11289
SXDL31_DWAV_240800 24-Jun-2019 07:18 7035
SXDL31_DWAV_241800 24-Jun-2019 16:52 7995
SXDL33_DWAV_230000 23-Jun-2019 10:13 9120
SXDL33_DWAV_240000 24-Jun-2019 08:54 6161
ber01-FWDL39_DWMS_231230-1906231230-dsw--0-ia5 23-Jun-2019 12:32 1145
ber01-FWDL39_DWMS_241230-1906241230-dsw--0-ia5 24-Jun-2019 12:12 987
ber01-VHDL13_DWEH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:28 1880
ber01-VHDL13_DWEH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:58 2008
ber01-VHDL13_DWEH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:28 2207
ber01-VHDL13_DWEH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:28 2202
ber01-VHDL13_DWEH_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:28 2155
ber01-VHDL13_DWEH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:28 1903
ber01-VHDL13_DWEH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:28 2226
ber01-VHDL13_DWEH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:58 2191
ber01-VHDL13_DWEH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:28 2475
ber01-VHDL13_DWEH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:28 2532
ber01-VHDL13_DWEH_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:28 2298
ber01-VHDL13_DWEH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:28 2228
ber01-VHDL13_DWHG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1627
ber01-VHDL13_DWHG_230200_COR-1906230200-dsw--0-ia5 23-Jun-2019 02:37 1801
ber01-VHDL13_DWHG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1911
ber01-VHDL13_DWHG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1920
ber01-VHDL13_DWHG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 2069
ber01-VHDL13_DWHG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1911
ber01-VHDL13_DWHG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2566
ber01-VHDL13_DWHG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 2577
ber01-VHDL13_DWHG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 2650
ber01-VHDL13_DWHG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 2442
ber01-VHDL13_DWHG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2053
ber01-VHDL13_DWHH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1688
ber01-VHDL13_DWHH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1849
ber01-VHDL13_DWHH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1853
ber01-VHDL13_DWHH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1856
ber01-VHDL13_DWHH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1688
ber01-VHDL13_DWHH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2529
ber01-VHDL13_DWHH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 2535
ber01-VHDL13_DWHH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 2460
ber01-VHDL13_DWHH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 2434
ber01-VHDL13_DWHH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2108
ber01-VHDL13_DWLG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1662
ber01-VHDL13_DWLG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1703
ber01-VHDL13_DWLG_230533-1906230533-dsw--0-ia5 23-Jun-2019 05:33 1731
ber01-VHDL13_DWLG_230633-1906230633-dsw--0-ia5 23-Jun-2019 06:33 1731
ber01-VHDL13_DWLG_230733-1906230733-dsw--0-ia5 23-Jun-2019 07:33 1728
ber01-VHDL13_DWLG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1697
ber01-VHDL13_DWLG_230933-1906230933-dsw--0-ia5 23-Jun-2019 09:33 1728
ber01-VHDL13_DWLG_231033-1906231033-dsw--0-ia5 23-Jun-2019 10:33 1707
ber01-VHDL13_DWLG_231133-1906231133-dsw--0-ia5 23-Jun-2019 11:33 1713
ber01-VHDL13_DWLG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1673
ber01-VHDL13_DWLG_231333-1906231333-dsw--0-ia5 23-Jun-2019 13:33 1656
ber01-VHDL13_DWLG_231433-1906231433-dsw--0-ia5 23-Jun-2019 14:33 1656
ber01-VHDL13_DWLG_231533-1906231533-dsw--0-ia5 23-Jun-2019 15:33 1656
ber01-VHDL13_DWLG_231633-1906231633-dsw--0-ia5 23-Jun-2019 16:33 1656
ber01-VHDL13_DWLG_231733-1906231733-dsw--0-ia5 23-Jun-2019 17:33 1429
ber01-VHDL13_DWLG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1401
ber01-VHDL13_DWLG_231933-1906231933-dsw--0-ia5 23-Jun-2019 19:33 1429
ber01-VHDL13_DWLG_232033-1906232033-dsw--0-ia5 23-Jun-2019 20:33 1429
ber01-VHDL13_DWLG_240033-1906240033-dsw--0-ia5 24-Jun-2019 00:33 1845
ber01-VHDL13_DWLG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1822
ber01-VHDL13_DWLG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1640
ber01-VHDL13_DWLG_240533-1906240533-dsw--0-ia5 24-Jun-2019 05:33 1668
ber01-VHDL13_DWLG_240633-1906240633-dsw--0-ia5 24-Jun-2019 06:33 1728
ber01-VHDL13_DWLG_240733-1906240733-dsw--0-ia5 24-Jun-2019 07:33 1725
ber01-VHDL13_DWLG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1720
ber01-VHDL13_DWLG_240933-1906240933-dsw--0-ia5 24-Jun-2019 09:33 1751
ber01-VHDL13_DWLG_241033-1906241033-dsw--0-ia5 24-Jun-2019 10:33 1751
ber01-VHDL13_DWLG_241133-1906241133-dsw--0-ia5 24-Jun-2019 11:33 1735
ber01-VHDL13_DWLG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1706
ber01-VHDL13_DWLG_241333-1906241333-dsw--0-ia5 24-Jun-2019 13:33 1700
ber01-VHDL13_DWLG_241433-1906241433-dsw--0-ia5 24-Jun-2019 14:33 1700
ber01-VHDL13_DWLG_241533-1906241533-dsw--0-ia5 24-Jun-2019 15:33 1700
ber01-VHDL13_DWLG_241633-1906241633-dsw--0-ia5 24-Jun-2019 16:33 1700
ber01-VHDL13_DWLG_241733-1906241733-dsw--0-ia5 24-Jun-2019 17:33 1700
ber01-VHDL13_DWLG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1528
ber01-VHDL13_DWLG_241933-1906241933-dsw--0-ia5 24-Jun-2019 19:33 1556
ber01-VHDL13_DWLG_242033-1906242033-dsw--0-ia5 24-Jun-2019 20:33 1556
ber01-VHDL13_DWLG_250033-1906250033-dsw--0-ia5 25-Jun-2019 00:33 1756
ber01-VHDL13_DWLH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1599
ber01-VHDL13_DWLH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1637
ber01-VHDL13_DWLH_230533-1906230533-dsw--0-ia5 23-Jun-2019 05:33 1665
ber01-VHDL13_DWLH_230633-1906230633-dsw--0-ia5 23-Jun-2019 06:33 1665
ber01-VHDL13_DWLH_230733-1906230733-dsw--0-ia5 23-Jun-2019 07:33 1662
ber01-VHDL13_DWLH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1634
ber01-VHDL13_DWLH_230933-1906230933-dsw--0-ia5 23-Jun-2019 09:33 1662
ber01-VHDL13_DWLH_231033-1906231033-dsw--0-ia5 23-Jun-2019 10:33 1657
ber01-VHDL13_DWLH_231133-1906231133-dsw--0-ia5 23-Jun-2019 11:33 1704
ber01-VHDL13_DWLH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1664
ber01-VHDL13_DWLH_231333-1906231333-dsw--0-ia5 23-Jun-2019 13:33 1651
ber01-VHDL13_DWLH_231433-1906231433-dsw--0-ia5 23-Jun-2019 14:33 1651
ber01-VHDL13_DWLH_231533-1906231533-dsw--0-ia5 23-Jun-2019 15:33 1651
ber01-VHDL13_DWLH_231633-1906231633-dsw--0-ia5 23-Jun-2019 16:33 1651
ber01-VHDL13_DWLH_231733-1906231733-dsw--0-ia5 23-Jun-2019 17:33 1425
ber01-VHDL13_DWLH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1397
ber01-VHDL13_DWLH_231933-1906231933-dsw--0-ia5 23-Jun-2019 19:33 1425
ber01-VHDL13_DWLH_232033-1906232033-dsw--0-ia5 23-Jun-2019 20:33 1425
ber01-VHDL13_DWLH_240033-1906240033-dsw--0-ia5 24-Jun-2019 00:33 1886
ber01-VHDL13_DWLH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1863
ber01-VHDL13_DWLH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1646
ber01-VHDL13_DWLH_240533-1906240533-dsw--0-ia5 24-Jun-2019 05:33 1674
ber01-VHDL13_DWLH_240633-1906240633-dsw--0-ia5 24-Jun-2019 06:33 1737
ber01-VHDL13_DWLH_240733-1906240733-dsw--0-ia5 24-Jun-2019 07:33 1734
ber01-VHDL13_DWLH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1732
ber01-VHDL13_DWLH_240933-1906240933-dsw--0-ia5 24-Jun-2019 09:33 1760
ber01-VHDL13_DWLH_241033-1906241033-dsw--0-ia5 24-Jun-2019 10:33 1748
ber01-VHDL13_DWLH_241133-1906241133-dsw--0-ia5 24-Jun-2019 11:33 1737
ber01-VHDL13_DWLH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1709
ber01-VHDL13_DWLH_241333-1906241333-dsw--0-ia5 24-Jun-2019 13:33 1703
ber01-VHDL13_DWLH_241433-1906241433-dsw--0-ia5 24-Jun-2019 14:33 1703
ber01-VHDL13_DWLH_241533-1906241533-dsw--0-ia5 24-Jun-2019 15:33 1703
ber01-VHDL13_DWLH_241633-1906241633-dsw--0-ia5 24-Jun-2019 16:33 1703
ber01-VHDL13_DWLH_241733-1906241733-dsw--0-ia5 24-Jun-2019 17:33 1703
ber01-VHDL13_DWLH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1535
ber01-VHDL13_DWLH_241933-1906241933-dsw--0-ia5 24-Jun-2019 19:33 1563
ber01-VHDL13_DWLH_242033-1906242033-dsw--0-ia5 24-Jun-2019 20:33 1563
ber01-VHDL13_DWLH_250033-1906250033-dsw--0-ia5 25-Jun-2019 00:33 1747
ber01-VHDL13_DWLI_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1674
ber01-VHDL13_DWLI_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1715
ber01-VHDL13_DWLI_230533-1906230533-dsw--0-ia5 23-Jun-2019 05:33 1743
ber01-VHDL13_DWLI_230633-1906230633-dsw--0-ia5 23-Jun-2019 06:33 1743
ber01-VHDL13_DWLI_230733-1906230733-dsw--0-ia5 23-Jun-2019 07:33 1740
ber01-VHDL13_DWLI_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1712
ber01-VHDL13_DWLI_230933-1906230933-dsw--0-ia5 23-Jun-2019 09:33 1740
ber01-VHDL13_DWLI_231033-1906231033-dsw--0-ia5 23-Jun-2019 10:33 1707
ber01-VHDL13_DWLI_231133-1906231133-dsw--0-ia5 23-Jun-2019 11:33 1715
ber01-VHDL13_DWLI_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1805
ber01-VHDL13_DWLI_231333-1906231333-dsw--0-ia5 23-Jun-2019 13:33 1658
ber01-VHDL13_DWLI_231433-1906231433-dsw--0-ia5 23-Jun-2019 14:33 1658
ber01-VHDL13_DWLI_231533-1906231533-dsw--0-ia5 23-Jun-2019 15:33 1658
ber01-VHDL13_DWLI_231633-1906231633-dsw--0-ia5 23-Jun-2019 16:33 1658
ber01-VHDL13_DWLI_231733-1906231733-dsw--0-ia5 23-Jun-2019 17:33 1431
ber01-VHDL13_DWLI_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1403
ber01-VHDL13_DWLI_231933-1906231933-dsw--0-ia5 23-Jun-2019 19:33 1431
ber01-VHDL13_DWLI_232033-1906232033-dsw--0-ia5 23-Jun-2019 20:33 1431
ber01-VHDL13_DWLI_240033-1906240033-dsw--0-ia5 24-Jun-2019 00:33 1848
ber01-VHDL13_DWLI_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1825
ber01-VHDL13_DWLI_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1644
ber01-VHDL13_DWLI_240533-1906240533-dsw--0-ia5 24-Jun-2019 05:33 1672
ber01-VHDL13_DWLI_240633-1906240633-dsw--0-ia5 24-Jun-2019 06:33 1736
ber01-VHDL13_DWLI_240733-1906240733-dsw--0-ia5 24-Jun-2019 07:33 1733
ber01-VHDL13_DWLI_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1731
ber01-VHDL13_DWLI_240933-1906240933-dsw--0-ia5 24-Jun-2019 09:33 1759
ber01-VHDL13_DWLI_241033-1906241033-dsw--0-ia5 24-Jun-2019 10:33 1759
ber01-VHDL13_DWLI_241133-1906241133-dsw--0-ia5 24-Jun-2019 11:33 1743
ber01-VHDL13_DWLI_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1714
ber01-VHDL13_DWLI_241333-1906241333-dsw--0-ia5 24-Jun-2019 13:33 1708
ber01-VHDL13_DWLI_241433-1906241433-dsw--0-ia5 24-Jun-2019 14:33 1708
ber01-VHDL13_DWLI_241533-1906241533-dsw--0-ia5 24-Jun-2019 15:33 1708
ber01-VHDL13_DWLI_241633-1906241633-dsw--0-ia5 24-Jun-2019 16:33 1708
ber01-VHDL13_DWLI_241733-1906241733-dsw--0-ia5 24-Jun-2019 17:33 1708
ber01-VHDL13_DWLI_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1536
ber01-VHDL13_DWLI_241933-1906241933-dsw--0-ia5 24-Jun-2019 19:33 1564
ber01-VHDL13_DWLI_242033-1906242033-dsw--0-ia5 24-Jun-2019 20:33 1564
ber01-VHDL13_DWLI_250033-1906250033-dsw--0-ia5 25-Jun-2019 00:33 1764
ber01-VHDL13_DWMG_230100-1906230100-dsw--0-ia5 23-Jun-2019 01:30 2342
ber01-VHDL13_DWMG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 2308
ber01-VHDL13_DWMG_230300-1906230300-dsw--0-ia5 23-Jun-2019 03:30 2308
ber01-VHDL13_DWMG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 2312
ber01-VHDL13_DWMG_230500-1906230500-dsw--0-ia5 23-Jun-2019 05:30 2312
ber01-VHDL13_DWMG_230600-1906230600-dsw--0-ia5 23-Jun-2019 06:30 2248
ber01-VHDL13_DWMG_230700-1906230700-dsw--0-ia5 23-Jun-2019 07:30 2248
ber01-VHDL13_DWMG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 2244
ber01-VHDL13_DWMG_230900-1906230900-dsw--0-ia5 23-Jun-2019 09:30 2244
ber01-VHDL13_DWMG_231000-1906231000-dsw--0-ia5 23-Jun-2019 10:30 2244
ber01-VHDL13_DWMG_231100-1906231100-dsw--0-ia5 23-Jun-2019 11:30 2176
ber01-VHDL13_DWMG_231200-1906231200-dsw--0-ia5 23-Jun-2019 12:30 2176
ber01-VHDL13_DWMG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 2176
ber01-VHDL13_DWMG_231400-1906231400-dsw--0-ia5 23-Jun-2019 14:30 2176
ber01-VHDL13_DWMG_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:30 1928
ber01-VHDL13_DWMG_231600-1906231600-dsw--0-ia5 23-Jun-2019 16:30 1928
ber01-VHDL13_DWMG_231700-1906231700-dsw--0-ia5 23-Jun-2019 17:30 1896
ber01-VHDL13_DWMG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1896
ber01-VHDL13_DWMG_231900-1906231900-dsw--0-ia5 23-Jun-2019 19:30 1896
ber01-VHDL13_DWMG_232000-1906232000-dsw--0-ia5 23-Jun-2019 20:30 1896
ber01-VHDL13_DWMG_232100-1906232100-dsw--0-ia5 23-Jun-2019 21:30 1840
ber01-VHDL13_DWMG_232200-1906232200-dsw--0-ia5 23-Jun-2019 22:30 1895
ber01-VHDL13_DWMG_232300-1906232300-dsw--0-ia5 23-Jun-2019 23:30 1868
ber01-VHDL13_DWMG_240000-1906240000-dsw--0-ia5 24-Jun-2019 00:30 1868
ber01-VHDL13_DWMG_240100-1906240100-dsw--0-ia5 24-Jun-2019 01:30 1868
ber01-VHDL13_DWMG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1868
ber01-VHDL13_DWMG_240300-1906240300-dsw--0-ia5 24-Jun-2019 03:30 1706
ber01-VHDL13_DWMG_240400-1906240400-dsw--0-ia5 24-Jun-2019 06:27 2260
ber01-VHDL13_DWMG_240500-1906240500-dsw--0-ia5 24-Jun-2019 05:30 1736
ber01-VHDL13_DWMG_240600-1906240600-dsw--0-ia5 24-Jun-2019 06:30 1989
ber01-VHDL13_DWMG_240700-1906240700-dsw--0-ia5 24-Jun-2019 07:30 1970
ber01-VHDL13_DWMG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 2123
ber01-VHDL13_DWMG_240900-1906240900-dsw--0-ia5 24-Jun-2019 09:30 2123
ber01-VHDL13_DWMG_241000-1906241000-dsw--0-ia5 24-Jun-2019 10:30 2112
ber01-VHDL13_DWMG_241100-1906241100-dsw--0-ia5 24-Jun-2019 11:30 2112
ber01-VHDL13_DWMG_241200-1906241200-dsw--0-ia5 24-Jun-2019 12:30 2112
ber01-VHDL13_DWMG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 2112
ber01-VHDL13_DWMG_241400-1906241400-dsw--0-ia5 24-Jun-2019 14:30 2237
ber01-VHDL13_DWMG_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:30 2192
ber01-VHDL13_DWMG_241600-1906241600-dsw--0-ia5 24-Jun-2019 16:30 2192
ber01-VHDL13_DWMG_241700-1906241700-dsw--0-ia5 24-Jun-2019 17:30 2192
ber01-VHDL13_DWMG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2052
ber01-VHDL13_DWMG_241900-1906241900-dsw--0-ia5 24-Jun-2019 19:30 2057
ber01-VHDL13_DWMG_242000-1906242000-dsw--0-ia5 24-Jun-2019 20:30 2087
ber01-VHDL13_DWMG_242100-1906242100-dsw--0-ia5 24-Jun-2019 21:30 2087
ber01-VHDL13_DWMG_242200-1906242200-dsw--0-ia5 24-Jun-2019 22:30 2211
ber01-VHDL13_DWMG_242300-1906242300-dsw--0-ia5 24-Jun-2019 23:30 2211
ber01-VHDL13_DWMG_250000-1906250000-dsw--0-ia5 25-Jun-2019 00:30 2211
ber01-VHDL13_DWMO_230100-1906230100-dsw--0-ia5 23-Jun-2019 01:30 2427
ber01-VHDL13_DWMO_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 2420
ber01-VHDL13_DWMO_230300-1906230300-dsw--0-ia5 23-Jun-2019 03:30 2420
ber01-VHDL13_DWMO_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 2428
ber01-VHDL13_DWMO_230500-1906230500-dsw--0-ia5 23-Jun-2019 05:30 2428
ber01-VHDL13_DWMO_230600-1906230600-dsw--0-ia5 23-Jun-2019 06:30 2356
ber01-VHDL13_DWMO_230700-1906230700-dsw--0-ia5 23-Jun-2019 07:30 2356
ber01-VHDL13_DWMO_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 2373
ber01-VHDL13_DWMO_230900-1906230900-dsw--0-ia5 23-Jun-2019 09:30 2345
ber01-VHDL13_DWMO_231000-1906231000-dsw--0-ia5 23-Jun-2019 10:30 2345
ber01-VHDL13_DWMO_231100-1906231100-dsw--0-ia5 23-Jun-2019 11:30 2049
ber01-VHDL13_DWMO_231200-1906231200-dsw--0-ia5 23-Jun-2019 12:30 2049
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ber01-VHDL13_DWMP_241100-1906241100-dsw--0-ia5 24-Jun-2019 11:30 2032
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ber01-VHDL13_DWOG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:00 3467
ber01-VHDL13_DWOG_231700-1906231700-dsw--0-ia5 23-Jun-2019 17:30 2952
ber01-VHDL13_DWOG_240100-1906240100-dsw--0-ia5 24-Jun-2019 01:45 3313
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ber01-VHDL13_DWOG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:15 3447
ber01-VHDL13_DWOG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:00 3591
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ber01-VHDL13_DWOH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:28 2523
ber01-VHDL13_DWOH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:28 2529
ber01-VHDL13_DWOH_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:28 2365
ber01-VHDL13_DWOH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:28 2243
ber01-VHDL13_DWOI_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:28 1987
ber01-VHDL13_DWOI_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:58 1919
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ber01-VHDL13_DWOI_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:28 1998
ber01-VHDL13_DWOI_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:28 2020
ber01-VHDL13_DWOI_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:28 1900
ber01-VHDL13_DWOI_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:28 2179
ber01-VHDL13_DWOI_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:58 2111
ber01-VHDL13_DWOI_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:28 2469
ber01-VHDL13_DWOI_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:28 2436
ber01-VHDL13_DWOI_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:28 2326
ber01-VHDL13_DWOI_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:28 2225
ber01-VHDL13_DWON_230255-1906230255-dsw--0-ia5 23-Jun-2019 02:55 3477
ber01-VHDL13_DWON_230518-1906230518-dsw--0-ia5 23-Jun-2019 05:19 3504
ber01-VHDL13_DWON_230554-1906230554-dsw--0-ia5 23-Jun-2019 05:55 3770
ber01-VHDL13_DWON_231524-1906231524-dsw--0-ia5 23-Jun-2019 15:24 3533
ber01-VHDL13_DWON_231603-1906231603-dsw--0-ia5 23-Jun-2019 16:03 2923
ber01-VHDL13_DWON_231635-1906231635-dsw--0-ia5 23-Jun-2019 16:35 2923
ber01-VHDL13_DWON_231827-1906231827-dsw--0-ia5 23-Jun-2019 18:27 3078
ber01-VHDL13_DWON_232103-1906232103-dsw--0-ia5 23-Jun-2019 21:04 3078
ber01-VHDL13_DWON_240016-1906240016-dsw--0-ia5 24-Jun-2019 00:16 3353
ber01-VHDL13_DWON_240139-1906240139-dsw--0-ia5 24-Jun-2019 01:39 3353
ber01-VHDL13_DWON_240358-1906240358-dsw--0-ia5 24-Jun-2019 03:58 3369
ber01-VHDL13_DWON_240526-1906240526-dsw--0-ia5 24-Jun-2019 05:26 3550
ber01-VHDL13_DWON_240530-1906240530-dsw--0-ia5 24-Jun-2019 05:30 3940
ber01-VHDL13_DWON_240533-1906240533-dsw--0-ia5 24-Jun-2019 05:33 3938
ber01-VHDL13_DWON_240731-1906240731-dsw--0-ia5 24-Jun-2019 07:31 3938
ber01-VHDL13_DWON_241104-1906241104-dsw--0-ia5 24-Jun-2019 11:04 3938
ber01-VHDL13_DWON_241512-1906241512-dsw--0-ia5 24-Jun-2019 15:13 3799
ber01-VHDL13_DWON_241700-1906241700-dsw--0-ia5 24-Jun-2019 17:00 3656
ber01-VHDL13_DWON_241837-1906241837-dsw--0-ia5 24-Jun-2019 18:37 3656
ber01-VHDL13_DWON_242132-1906242132-dsw--0-ia5 24-Jun-2019 21:32 3704
ber01-VHDL13_DWON_250021-1906250021-dsw--0-ia5 25-Jun-2019 00:21 4114
ber01-VHDL13_DWPG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1741
ber01-VHDL13_DWPG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1650
ber01-VHDL13_DWPG_230530-1906230530-dsw--0-ia5 23-Jun-2019 05:30 1722
ber01-VHDL13_DWPG_230630-1906230630-dsw--0-ia5 23-Jun-2019 06:30 1722
ber01-VHDL13_DWPG_230750-1906230750-dsw--0-ia5 23-Jun-2019 07:30 1722
ber01-VHDL13_DWPG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1665
ber01-VHDL13_DWPG_230930-1906230930-dsw--0-ia5 23-Jun-2019 09:30 1665
ber01-VHDL13_DWPG_231030-1906231030-dsw--0-ia5 23-Jun-2019 10:30 1665
ber01-VHDL13_DWPG_231130-1906231130-dsw--0-ia5 23-Jun-2019 11:30 1666
ber01-VHDL13_DWPG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1778
ber01-VHDL13_DWPG_231330-1906231330-dsw--0-ia5 23-Jun-2019 13:30 1778
ber01-VHDL13_DWPG_231450-1906231450-dsw--0-ia5 23-Jun-2019 14:30 1778
ber01-VHDL13_DWPG_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:30 1853
ber01-VHDL13_DWPG_231630-1906231630-dsw--0-ia5 23-Jun-2019 16:30 1853
ber01-VHDL13_DWPG_231750-1906231750-dsw--0-ia5 23-Jun-2019 17:30 1853
ber01-VHDL13_DWPG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1745
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ber01-VHDL13_DWPG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2122
ber01-VHDL13_DWPG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 2146
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ber01-VHDL13_DWPG_240630-1906240630-dsw--0-ia5 24-Jun-2019 06:30 2145
ber01-VHDL13_DWPG_240750-1906240750-dsw--0-ia5 24-Jun-2019 07:30 2145
ber01-VHDL13_DWPG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 2329
ber01-VHDL13_DWPG_240930-1906240930-dsw--0-ia5 24-Jun-2019 09:30 2329
ber01-VHDL13_DWPG_241030-1906241030-dsw--0-ia5 24-Jun-2019 10:30 2337
ber01-VHDL13_DWPG_241130-1906241130-dsw--0-ia5 24-Jun-2019 11:30 2337
ber01-VHDL13_DWPG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 2348
ber01-VHDL13_DWPG_241330-1906241330-dsw--0-ia5 24-Jun-2019 13:30 2348
ber01-VHDL13_DWPG_241450-1906241450-dsw--0-ia5 24-Jun-2019 14:30 2348
ber01-VHDL13_DWPG_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:30 2278
ber01-VHDL13_DWPG_241630-1906241630-dsw--0-ia5 24-Jun-2019 16:30 2278
ber01-VHDL13_DWPG_241750-1906241750-dsw--0-ia5 24-Jun-2019 17:30 2278
ber01-VHDL13_DWPG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2196
ber01-VHDL13_DWPG_241930-1906241930-dsw--0-ia5 24-Jun-2019 19:30 2196
ber01-VHDL13_DWPH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1842
ber01-VHDL13_DWPH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1805
ber01-VHDL13_DWPH_230530-1906230530-dsw--0-ia5 23-Jun-2019 05:30 1794
ber01-VHDL13_DWPH_230630-1906230630-dsw--0-ia5 23-Jun-2019 06:30 1794
ber01-VHDL13_DWPH_230750-1906230750-dsw--0-ia5 23-Jun-2019 07:30 1794
ber01-VHDL13_DWPH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1840
ber01-VHDL13_DWPH_230930-1906230930-dsw--0-ia5 23-Jun-2019 09:30 1840
ber01-VHDL13_DWPH_231030-1906231030-dsw--0-ia5 23-Jun-2019 10:30 1840
ber01-VHDL13_DWPH_231130-1906231130-dsw--0-ia5 23-Jun-2019 11:30 1841
ber01-VHDL13_DWPH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1926
ber01-VHDL13_DWPH_231330-1906231330-dsw--0-ia5 23-Jun-2019 13:30 1926
ber01-VHDL13_DWPH_231450-1906231450-dsw--0-ia5 23-Jun-2019 14:30 1926
ber01-VHDL13_DWPH_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:30 1972
ber01-VHDL13_DWPH_231630-1906231630-dsw--0-ia5 23-Jun-2019 16:30 1972
ber01-VHDL13_DWPH_231750-1906231750-dsw--0-ia5 23-Jun-2019 17:30 1972
ber01-VHDL13_DWPH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1944
ber01-VHDL13_DWPH_231930-1906231930-dsw--0-ia5 23-Jun-2019 19:30 1944
ber01-VHDL13_DWPH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2321
ber01-VHDL13_DWPH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 2345
ber01-VHDL13_DWPH_240530-1906240530-dsw--0-ia5 24-Jun-2019 05:30 2345
ber01-VHDL13_DWPH_240630-1906240630-dsw--0-ia5 24-Jun-2019 06:30 2345
ber01-VHDL13_DWPH_240750-1906240750-dsw--0-ia5 24-Jun-2019 07:30 2345
ber01-VHDL13_DWPH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 2289
ber01-VHDL13_DWPH_240930-1906240930-dsw--0-ia5 24-Jun-2019 09:30 2289
ber01-VHDL13_DWPH_241030-1906241030-dsw--0-ia5 24-Jun-2019 10:30 2299
ber01-VHDL13_DWPH_241130-1906241130-dsw--0-ia5 24-Jun-2019 11:30 2299
ber01-VHDL13_DWPH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 2342
ber01-VHDL13_DWPH_241330-1906241330-dsw--0-ia5 24-Jun-2019 13:30 2342
ber01-VHDL13_DWPH_241450-1906241450-dsw--0-ia5 24-Jun-2019 14:30 2342
ber01-VHDL13_DWPH_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:30 2205
ber01-VHDL13_DWPH_241630-1906241630-dsw--0-ia5 24-Jun-2019 16:30 2205
ber01-VHDL13_DWPH_241750-1906241750-dsw--0-ia5 24-Jun-2019 17:30 2205
ber01-VHDL13_DWPH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2101
ber01-VHDL13_DWPH_241930-1906241930-dsw--0-ia5 24-Jun-2019 19:30 2101
ber01-VHDL13_DWSG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1758
ber01-VHDL13_DWSG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1877
ber01-VHDL13_DWSG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1802
ber01-VHDL13_DWSG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1749
ber01-VHDL13_DWSG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1515
ber01-VHDL13_DWSG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1673
ber01-VHDL13_DWSG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1681
ber01-VHDL13_DWSG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1766
ber01-VHDL13_DWSG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1878
ber01-VHDL13_DWSG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1630
ber01-VHDL13_DWSN_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 2083
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gts01-VHDL12_DWON_230115-1906230145-afsv--68-ia5 23-Jun-2019 01:45 2978
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gts01-VHDL12_DWON_241815-1906241745-afsv--72-ia5 24-Jun-2019 17:45 2884
pid-VHDL12_DWEH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:28 1578
pid-VHDL12_DWEH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:28 1908
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pid-VHDL12_DWHH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1321
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pid-VHDL12_DWHH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2144
pid-VHDL12_DWHH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 2150
pid-VHDL12_DWLG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1362
pid-VHDL12_DWLG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1403
pid-VHDL12_DWLG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1400
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pid-VHDL12_DWLG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1088
pid-VHDL12_DWLG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1466
pid-VHDL12_DWLG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1335
pid-VHDL12_DWLG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1418
pid-VHDL12_DWLG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1401
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pid-VHDL12_DWLH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1354
pid-VHDL12_DWLH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1087
pid-VHDL12_DWLH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1480
pid-VHDL12_DWLH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1345
pid-VHDL12_DWLH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1431
pid-VHDL12_DWLH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1408
pid-VHDL12_DWLH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1234
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pid-VHDL12_DWLI_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:30 1412
pid-VHDL12_DWLI_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1492
pid-VHDL12_DWLI_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1090
pid-VHDL12_DWLI_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1468
pid-VHDL12_DWLI_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1339
pid-VHDL12_DWLI_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1426
pid-VHDL12_DWLI_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1409
pid-VHDL12_DWLI_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 1231
pid-VHDL12_DWMG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1978
pid-VHDL12_DWMG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 1982
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pid-VHDL12_DWMG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 1890
pid-VHDL12_DWMG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 1610
pid-VHDL12_DWMG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1597
pid-VHDL12_DWMG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 1452
pid-VHDL12_DWMG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 1676
pid-VHDL12_DWMG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 1665
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pid-VHDL12_DWOH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:28 1837
pid-VHDL12_DWOI_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:28 1683
pid-VHDL12_DWOI_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:28 1868
pid-VHDL12_DWSG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 1542
pid-VHDL12_DWSG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 1387
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swis2-VHDL20_DWEH_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:45 3680
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swis2-VHDL20_DWHH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:45 2857
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swis2-VHDL20_DWLG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:45 3206
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swis2-VHDL20_DWLG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:45 2945
swis2-VHDL20_DWLG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:45 3366
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swis2-VHDL20_DWLG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 3267
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swis2-VHDL20_DWLG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:45 3072
swis2-VHDL20_DWLH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:45 3144
swis2-VHDL20_DWLH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:45 3182
swis2-VHDL20_DWLH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:45 3179
swis2-VHDL20_DWLH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:45 3209
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swis2-VHDL20_DWLH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:45 3408
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swis2-VHDL20_DWLH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 3277
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swis2-VHDL20_DWLH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:45 3080
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swis2-VHDL20_DWLI_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:45 3349
swis2-VHDL20_DWLI_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:45 2947
swis2-VHDL20_DWLI_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:45 3369
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swis2-VHDL20_DWLI_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 3275
swis2-VHDL20_DWLI_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:45 3258
swis2-VHDL20_DWLI_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:45 3080
swis2-VHDL20_DWMG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:45 4719
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swis2-VHDL20_DWMO_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 4030
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swis2-VHDL20_DWMP_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:45 4906
swis2-VHDL20_DWMP_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:45 4590
swis2-VHDL20_DWMP_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:45 4650
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swis2-VHDL20_DWMP_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 4751
swis2-VHDL20_DWMP_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:45 4743
swis2-VHDL20_DWMP_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:45 4770
swis2-VHDL20_DWPG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 2511
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swis2-VHDL20_DWPG_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 2581
swis2-VHDL20_DWPG_231330-1906231330-dsw--0-ia5 23-Jun-2019 13:30 2581
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swis2-VHDL20_DWPG_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:30 2656
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swis2-VHDL20_DWPG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 2578
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swis2-VHDL20_DWPG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 2892
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swis2-VHDL20_DWPG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 3099
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swis2-VHDL20_DWPG_241030-1906241030-dsw--0-ia5 24-Jun-2019 10:30 3170
swis2-VHDL20_DWPG_241130-1906241130-dsw--0-ia5 24-Jun-2019 11:30 3170
swis2-VHDL20_DWPG_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 3151
swis2-VHDL20_DWPG_241330-1906241330-dsw--0-ia5 24-Jun-2019 13:30 3151
swis2-VHDL20_DWPG_241450-1906241450-dsw--0-ia5 24-Jun-2019 14:30 3151
swis2-VHDL20_DWPG_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:30 3081
swis2-VHDL20_DWPG_241630-1906241630-dsw--0-ia5 24-Jun-2019 16:30 3081
swis2-VHDL20_DWPG_241750-1906241750-dsw--0-ia5 24-Jun-2019 17:30 3081
swis2-VHDL20_DWPG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 3029
swis2-VHDL20_DWPG_241930-1906241930-dsw--0-ia5 24-Jun-2019 19:30 3029
swis2-VHDL20_DWPH_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:30 2612
swis2-VHDL20_DWPH_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:30 2575
swis2-VHDL20_DWPH_230530-1906230530-dsw--0-ia5 23-Jun-2019 05:30 2564
swis2-VHDL20_DWPH_230630-1906230630-dsw--0-ia5 23-Jun-2019 06:30 2564
swis2-VHDL20_DWPH_230750-1906230750-dsw--0-ia5 23-Jun-2019 07:30 2564
swis2-VHDL20_DWPH_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:31 2610
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swis2-VHDL20_DWPH_231030-1906231030-dsw--0-ia5 23-Jun-2019 10:30 2673
swis2-VHDL20_DWPH_231130-1906231130-dsw--0-ia5 23-Jun-2019 11:30 2674
swis2-VHDL20_DWPH_231300-1906231300-dsw--0-ia5 23-Jun-2019 12:30 2759
swis2-VHDL20_DWPH_231330-1906231330-dsw--0-ia5 23-Jun-2019 13:30 2759
swis2-VHDL20_DWPH_231450-1906231450-dsw--0-ia5 23-Jun-2019 14:30 2759
swis2-VHDL20_DWPH_231500-1906231500-dsw--0-ia5 23-Jun-2019 15:30 2805
swis2-VHDL20_DWPH_231630-1906231630-dsw--0-ia5 23-Jun-2019 16:30 2805
swis2-VHDL20_DWPH_231750-1906231750-dsw--0-ia5 23-Jun-2019 17:30 2805
swis2-VHDL20_DWPH_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:30 2777
swis2-VHDL20_DWPH_231930-1906231930-dsw--0-ia5 23-Jun-2019 19:30 2777
swis2-VHDL20_DWPH_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:30 3091
swis2-VHDL20_DWPH_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:30 3115
swis2-VHDL20_DWPH_240530-1906240530-dsw--0-ia5 24-Jun-2019 05:30 3115
swis2-VHDL20_DWPH_240630-1906240630-dsw--0-ia5 24-Jun-2019 06:30 3115
swis2-VHDL20_DWPH_240750-1906240750-dsw--0-ia5 24-Jun-2019 07:30 3115
swis2-VHDL20_DWPH_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:30 3059
swis2-VHDL20_DWPH_240930-1906240930-dsw--0-ia5 24-Jun-2019 09:30 3122
swis2-VHDL20_DWPH_241030-1906241030-dsw--0-ia5 24-Jun-2019 10:30 3132
swis2-VHDL20_DWPH_241130-1906241130-dsw--0-ia5 24-Jun-2019 11:30 3132
swis2-VHDL20_DWPH_241300-1906241300-dsw--0-ia5 24-Jun-2019 12:30 3175
swis2-VHDL20_DWPH_241330-1906241330-dsw--0-ia5 24-Jun-2019 13:30 3175
swis2-VHDL20_DWPH_241450-1906241450-dsw--0-ia5 24-Jun-2019 14:30 3175
swis2-VHDL20_DWPH_241500-1906241500-dsw--0-ia5 24-Jun-2019 15:30 3038
swis2-VHDL20_DWPH_241630-1906241630-dsw--0-ia5 24-Jun-2019 16:30 3038
swis2-VHDL20_DWPH_241750-1906241750-dsw--0-ia5 24-Jun-2019 17:30 3038
swis2-VHDL20_DWPH_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:30 2934
swis2-VHDL20_DWPH_241930-1906241930-dsw--0-ia5 24-Jun-2019 19:30 2934
swis2-VHDL20_DWSG_230200-1906230200-dsw--0-ia5 23-Jun-2019 02:45 3319
swis2-VHDL20_DWSG_230400-1906230400-dsw--0-ia5 23-Jun-2019 04:45 3438
swis2-VHDL20_DWSG_230800-1906230800-dsw--0-ia5 23-Jun-2019 08:45 3362
swis2-VHDL20_DWSG_231300-1906231300-dsw--0-ia5 23-Jun-2019 13:45 3311
swis2-VHDL20_DWSG_231800-1906231800-dsw--0-ia5 23-Jun-2019 18:45 3077
swis2-VHDL20_DWSG_240200-1906240200-dsw--0-ia5 24-Jun-2019 02:45 3234
swis2-VHDL20_DWSG_240400-1906240400-dsw--0-ia5 24-Jun-2019 04:45 3242
swis2-VHDL20_DWSG_240800-1906240800-dsw--0-ia5 24-Jun-2019 08:45 3326
swis2-VHDL20_DWSG_241300-1906241300-dsw--0-ia5 24-Jun-2019 13:45 3440
swis2-VHDL20_DWSG_241800-1906241800-dsw--0-ia5 24-Jun-2019 18:45 3192