Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Jul-2025 13:13:10 4476
FPDL13_DWMZ_050600 05-Jul-2025 12:22:44 2707
SXDL31_DWAV_040800 04-Jul-2025 07:41:08 12216
SXDL31_DWAV_041800 04-Jul-2025 16:40:20 5756
SXDL31_DWAV_050800 05-Jul-2025 07:20:38 7351
SXDL31_DWAV_051800 05-Jul-2025 17:00:50 10268
SXDL31_DWAV_LATEST 05-Jul-2025 17:00:50 10268
SXDL33_DWAV_040000 04-Jul-2025 09:44:29 6019
SXDL33_DWAV_050000 05-Jul-2025 08:54:05 6899
SXDL33_DWAV_LATEST 05-Jul-2025 08:54:05 6899
ber01-FWDL39_DWMS_041230-2507041230-dsw--0-ia5 04-Jul-2025 11:49:06 881
ber01-FWDL39_DWMS_051230-2507051230-dsw--0-ia5 05-Jul-2025 11:55:01 1236
ber01-VHDL13_DWEH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:12 2216
ber01-VHDL13_DWEH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:12 2209
ber01-VHDL13_DWEH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:11 2391
ber01-VHDL13_DWEH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:06 2349
ber01-VHDL13_DWEH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2646
ber01-VHDL13_DWEH_050800_COR-2507050800-dsw--0-ia5 05-Jul-2025 14:28:36 3110
ber01-VHDL13_DWEH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:11 2833
ber01-VHDL13_DWEH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:28:11 3089
ber01-VHDL13_DWEH_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:58:11 3038
ber01-VHDL13_DWHG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:07 2983
ber01-VHDL13_DWHG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2728
ber01-VHDL13_DWHG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:08 3067
ber01-VHDL13_DWHG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3070
ber01-VHDL13_DWHG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:07 3331
ber01-VHDL13_DWHG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2659
ber01-VHDL13_DWHG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:06 2691
ber01-VHDL13_DWHG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:12 2700
ber01-VHDL13_DWHH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:07 3031
ber01-VHDL13_DWHH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2602
ber01-VHDL13_DWHH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:08 3081
ber01-VHDL13_DWHH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3084
ber01-VHDL13_DWHH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:08 3305
ber01-VHDL13_DWHH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2702
ber01-VHDL13_DWHH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:06 2727
ber01-VHDL13_DWHH_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:12 2731
ber01-VHDL13_DWLG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1943
ber01-VHDL13_DWLG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1820
ber01-VHDL13_DWLG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 2065
ber01-VHDL13_DWLG_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2300
ber01-VHDL13_DWLG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2241
ber01-VHDL13_DWLG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2062
ber01-VHDL13_DWLG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:06 2262
ber01-VHDL13_DWLG_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:59:58 2344
ber01-VHDL13_DWLH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2003
ber01-VHDL13_DWLH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1975
ber01-VHDL13_DWLH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 2349
ber01-VHDL13_DWLH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2722
ber01-VHDL13_DWLH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2752
ber01-VHDL13_DWLH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2301
ber01-VHDL13_DWLH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:06 2592
ber01-VHDL13_DWLH_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:59:58 2668
ber01-VHDL13_DWLI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1798
ber01-VHDL13_DWLI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1693
ber01-VHDL13_DWLI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 1977
ber01-VHDL13_DWLI_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2190
ber01-VHDL13_DWLI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2195
ber01-VHDL13_DWLI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 1981
ber01-VHDL13_DWLI_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:06 2135
ber01-VHDL13_DWLI_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:59:58 2383
ber01-VHDL13_DWMG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2568
ber01-VHDL13_DWMG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2450
ber01-VHDL13_DWMG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2497
ber01-VHDL13_DWMG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2500
ber01-VHDL13_DWMG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2763
ber01-VHDL13_DWMG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2649
ber01-VHDL13_DWMG_051800_COR-2507051800-dsw--0-ia5 05-Jul-2025 19:41:57 3100
ber01-VHDL13_DWMG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 3108
ber01-VHDL13_DWMG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:02 3124
ber01-VHDL13_DWMO_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2101
ber01-VHDL13_DWMO_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2049
ber01-VHDL13_DWMO_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2326
ber01-VHDL13_DWMO_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2333
ber01-VHDL13_DWMO_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2573
ber01-VHDL13_DWMO_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2209
ber01-VHDL13_DWMO_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 2480
ber01-VHDL13_DWMO_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:02 2535
ber01-VHDL13_DWMP_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2581
ber01-VHDL13_DWMP_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2575
ber01-VHDL13_DWMP_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2890
ber01-VHDL13_DWMP_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2895
ber01-VHDL13_DWMP_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 3108
ber01-VHDL13_DWMP_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2920
ber01-VHDL13_DWMP_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 3316
ber01-VHDL13_DWMP_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:02 3321
ber01-VHDL13_DWOG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 3383
ber01-VHDL13_DWOG_041700-2507041700-dsw--0-ia5 04-Jul-2025 18:00:06 3098
ber01-VHDL13_DWOG_050300-2507050300-dsw--0-ia5 05-Jul-2025 03:00:14 3224
ber01-VHDL13_DWOG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 4012
ber01-VHDL13_DWOG_051700-2507051700-dsw--0-ia5 05-Jul-2025 18:00:02 3408
ber01-VHDL13_DWOG_060300-2507060300-dsw--0-ia5 06-Jul-2025 03:00:03 3381
ber01-VHDL13_DWOH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:12 2057
ber01-VHDL13_DWOH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:12 1973
ber01-VHDL13_DWOH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:06 2194
ber01-VHDL13_DWOH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:12 2180
ber01-VHDL13_DWOH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2586
ber01-VHDL13_DWOH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:11 2550
ber01-VHDL13_DWOH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:28:06 2962
ber01-VHDL13_DWOH_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:58:07 2911
ber01-VHDL13_DWOI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:06 2122
ber01-VHDL13_DWOI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:06 2085
ber01-VHDL13_DWOI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:11 2337
ber01-VHDL13_DWOI_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:12 2355
ber01-VHDL13_DWOI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2661
ber01-VHDL13_DWOI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:07 2538
ber01-VHDL13_DWOI_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:28:11 3033
ber01-VHDL13_DWOI_060400-2507060400-dsw--0-ia5 06-Jul-2025 04:58:11 2920
ber01-VHDL13_DWON_040530-2507040530-dsw--0-ia5 04-Jul-2025 05:30:09 3794
ber01-VHDL13_DWON_040545-2507040545-dsw--0-ia5 04-Jul-2025 05:45:36 3700
ber01-VHDL13_DWON_040620-2507040620-dsw--0-ia5 04-Jul-2025 06:20:32 3629
ber01-VHDL13_DWON_040735-2507040735-dsw--0-ia5 04-Jul-2025 07:35:16 3449
ber01-VHDL13_DWON_041410-2507041410-dsw--0-ia5 04-Jul-2025 14:10:33 3631
ber01-VHDL13_DWON_041415-2507041415-dsw--0-ia5 04-Jul-2025 14:15:17 3625
ber01-VHDL13_DWON_041722-2507041722-dsw--0-ia5 04-Jul-2025 17:22:16 3108
ber01-VHDL13_DWON_050128-2507050128-dsw--0-ia5 05-Jul-2025 01:28:53 3035
ber01-VHDL13_DWON_050251-2507050251-dsw--0-ia5 05-Jul-2025 02:51:23 3035
ber01-VHDL13_DWON_050511-2507050511-dsw--0-ia5 05-Jul-2025 05:11:11 3595
ber01-VHDL13_DWON_050618-2507050618-dsw--0-ia5 05-Jul-2025 06:18:07 3651
ber01-VHDL13_DWON_050750-2507050750-dsw--0-ia5 05-Jul-2025 07:50:47 3786
ber01-VHDL13_DWON_051027-2507051027-dsw--0-ia5 05-Jul-2025 10:28:02 3786
ber01-VHDL13_DWON_051432-2507051432-dsw--0-ia5 05-Jul-2025 14:33:04 3542
ber01-VHDL13_DWON_051741-2507051741-dsw--0-ia5 05-Jul-2025 17:41:31 2995
ber01-VHDL13_DWON_060014-2507060014-dsw--0-ia5 06-Jul-2025 00:14:47 2955
ber01-VHDL13_DWON_060239-2507060239-dsw--0-ia5 06-Jul-2025 02:39:36 2955
ber01-VHDL13_DWPG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2026
ber01-VHDL13_DWPG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1784
ber01-VHDL13_DWPG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2216
ber01-VHDL13_DWPG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2674
ber01-VHDL13_DWPG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2650
ber01-VHDL13_DWPG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2171
ber01-VHDL13_DWPG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 2439
ber01-VHDL13_DWPG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:02 2721
ber01-VHDL13_DWPH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2028
ber01-VHDL13_DWPH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 2029
ber01-VHDL13_DWPH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2276
ber01-VHDL13_DWPH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2703
ber01-VHDL13_DWPH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2713
ber01-VHDL13_DWPH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2219
ber01-VHDL13_DWPH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 2804
ber01-VHDL13_DWPH_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:02 3004
ber01-VHDL13_DWSG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1949
ber01-VHDL13_DWSG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 2229
ber01-VHDL13_DWSG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2569
ber01-VHDL13_DWSG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2587
ber01-VHDL13_DWSG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2945
ber01-VHDL13_DWSG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2511
ber01-VHDL13_DWSG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:30:02 2781
ber01-VHDL13_DWSG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:12 2841
ber01-VHDL13_DWSN_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1102
ber01-VHDL13_DWSO_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1110
ber01-VHDL13_DWSP_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1124
ber01-VHDL17_DWOG_041200-2507041200-dsw--0-ia5 04-Jul-2025 11:04:37 2856
ber01-VHDL17_DWOG_051200-2507051200-dsw--0-ia5 05-Jul-2025 11:01:42 2503
swis2-VHDL20_DWEG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:02 2138
swis2-VHDL20_DWEG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2236
swis2-VHDL20_DWEG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2158
swis2-VHDL20_DWEG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2326
swis2-VHDL20_DWEG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:01 2388
swis2-VHDL20_DWEG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2765
swis2-VHDL20_DWEG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2735
swis2-VHDL20_DWEG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:08 3094
swis2-VHDL20_DWEH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:12 2256
swis2-VHDL20_DWEH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2394
swis2-VHDL20_DWEH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:11 2409
swis2-VHDL20_DWEH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:24 2555
swis2-VHDL20_DWEH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:13 2527
swis2-VHDL20_DWEH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:11 2824
swis2-VHDL20_DWEH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:12 3033
swis2-VHDL20_DWEH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:14 3253
swis2-VHDL20_DWEI_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:12 2072
swis2-VHDL20_DWEI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2301
swis2-VHDL20_DWEI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2270
swis2-VHDL20_DWEI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2470
swis2-VHDL20_DWEI_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:13 2540
swis2-VHDL20_DWEI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2840
swis2-VHDL20_DWEI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2723
swis2-VHDL20_DWEI_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:08 3166
swis2-VHDL20_DWHG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 3166
swis2-VHDL20_DWHG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2911
swis2-VHDL20_DWHG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 3253
swis2-VHDL20_DWHG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3253
swis2-VHDL20_DWHG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3514
swis2-VHDL20_DWHG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2842
swis2-VHDL20_DWHG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:08 2877
swis2-VHDL20_DWHG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:12 2883
swis2-VHDL20_DWHH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 3217
swis2-VHDL20_DWHH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2788
swis2-VHDL20_DWHH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 3267
swis2-VHDL20_DWHH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3270
swis2-VHDL20_DWHH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3491
swis2-VHDL20_DWHH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2888
swis2-VHDL20_DWHH_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:08 2913
swis2-VHDL20_DWHH_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:12 2917
swis2-VHDL20_DWLG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2167
swis2-VHDL20_DWLG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2041
swis2-VHDL20_DWLG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2286
swis2-VHDL20_DWLG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:26 2521
swis2-VHDL20_DWLG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2465
swis2-VHDL20_DWLG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2283
swis2-VHDL20_DWLG_060200-2507060200-dsw--0-ia5 06-Jul-2025 02:45:00 2483
swis2-VHDL20_DWLG_060400-2507060400-dsw--0-ia5 06-Jul-2025 05:00:22 2565
swis2-VHDL20_DWLH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2224
swis2-VHDL20_DWLH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2196
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