Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_220600                                 22-Oct-2018 11:32                3231
FPDL13_DWMZ_230600                                 23-Oct-2018 08:31                4420
SXDL31_DWAV_220800                                 22-Oct-2018 07:35                9975
SXDL31_DWAV_221800                                 22-Oct-2018 16:44               18262
SXDL31_DWAV_230800                                 23-Oct-2018 07:39                7758
SXDL31_DWAV_231800                                 23-Oct-2018 16:59                9212
SXDL33_DWAV_220000                                 22-Oct-2018 09:33                6382
SXDL33_DWAV_230000                                 23-Oct-2018 09:35                9403
ber01-VHDL13_DWEH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:28                2583
ber01-VHDL13_DWEH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:28                2445
ber01-VHDL13_DWEH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:58                2790
ber01-VHDL13_DWEH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:28                2669
ber01-VHDL13_DWEH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:28                2720
ber01-VHDL13_DWEH_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:28                2580
ber01-VHDL13_DWEH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:28                2544
ber01-VHDL13_DWEH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:28                2977
ber01-VHDL13_DWEH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:58                2897
ber01-VHDL13_DWEH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:28                2752
ber01-VHDL13_DWEH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:28                2683
ber01-VHDL13_DWEH_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:28                2660
ber01-VHDL13_DWHG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2695
ber01-VHDL13_DWHG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2876
ber01-VHDL13_DWHG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2789
ber01-VHDL13_DWHG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2996
ber01-VHDL13_DWHG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2909
ber01-VHDL13_DWHG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2684
ber01-VHDL13_DWHG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2953
ber01-VHDL13_DWHG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                3028
ber01-VHDL13_DWHG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2744
ber01-VHDL13_DWHG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2722
ber01-VHDL13_DWHH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2934
ber01-VHDL13_DWHH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                3093
ber01-VHDL13_DWHH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                3054
ber01-VHDL13_DWHH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                3122
ber01-VHDL13_DWHH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                3087
ber01-VHDL13_DWHH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2943
ber01-VHDL13_DWHH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2940
ber01-VHDL13_DWHH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2961
ber01-VHDL13_DWHH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2796
ber01-VHDL13_DWHH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2814
ber01-VHDL13_DWLG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2320
ber01-VHDL13_DWLG_211933-1810211933-dsw--0-ia5     21-Oct-2018 19:33                2348
ber01-VHDL13_DWLG_212033-1810212033-dsw--0-ia5     21-Oct-2018 20:33                2348
ber01-VHDL13_DWLG_220033-1810220033-dsw--0-ia5     22-Oct-2018 00:33                2486
ber01-VHDL13_DWLG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2651
ber01-VHDL13_DWLG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2747
ber01-VHDL13_DWLG_220533-1810220533-dsw--0-ia5     22-Oct-2018 05:33                2836
ber01-VHDL13_DWLG_220633-1810220633-dsw--0-ia5     22-Oct-2018 06:33                2836
ber01-VHDL13_DWLG_220733-1810220733-dsw--0-ia5     22-Oct-2018 07:33                2833
ber01-VHDL13_DWLG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2802
ber01-VHDL13_DWLG_220933-1810220933-dsw--0-ia5     22-Oct-2018 09:33                2833
ber01-VHDL13_DWLG_221033-1810221033-dsw--0-ia5     22-Oct-2018 10:33                2893
ber01-VHDL13_DWLG_221133-1810221133-dsw--0-ia5     22-Oct-2018 11:33                2893
ber01-VHDL13_DWLG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2877
ber01-VHDL13_DWLG_221333-1810221333-dsw--0-ia5     22-Oct-2018 13:33                2874
ber01-VHDL13_DWLG_221433-1810221433-dsw--0-ia5     22-Oct-2018 14:33                2874
ber01-VHDL13_DWLG_221533-1810221533-dsw--0-ia5     22-Oct-2018 15:33                2869
ber01-VHDL13_DWLG_221633-1810221633-dsw--0-ia5     22-Oct-2018 16:33                2868
ber01-VHDL13_DWLG_221733-1810221733-dsw--0-ia5     22-Oct-2018 17:33                2657
ber01-VHDL13_DWLG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2629
ber01-VHDL13_DWLG_221933-1810221933-dsw--0-ia5     22-Oct-2018 19:33                2686
ber01-VHDL13_DWLG_222033-1810222033-dsw--0-ia5     22-Oct-2018 20:33                2686
ber01-VHDL13_DWLG_230033-1810230033-dsw--0-ia5     23-Oct-2018 00:33                2606
ber01-VHDL13_DWLG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2737
ber01-VHDL13_DWLG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2795
ber01-VHDL13_DWLG_230533-1810230533-dsw--0-ia5     23-Oct-2018 05:33                2823
ber01-VHDL13_DWLG_230633-1810230633-dsw--0-ia5     23-Oct-2018 06:33                2823
ber01-VHDL13_DWLG_230733-1810230733-dsw--0-ia5     23-Oct-2018 07:33                3043
ber01-VHDL13_DWLG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                3012
ber01-VHDL13_DWLG_230933-1810230933-dsw--0-ia5     23-Oct-2018 09:33                3043
ber01-VHDL13_DWLG_231033-1810231033-dsw--0-ia5     23-Oct-2018 10:33                3043
ber01-VHDL13_DWLG_231133-1810231133-dsw--0-ia5     23-Oct-2018 11:33                3032
ber01-VHDL13_DWLG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2997
ber01-VHDL13_DWLG_231333-1810231333-dsw--0-ia5     23-Oct-2018 13:33                2997
ber01-VHDL13_DWLG_231433-1810231433-dsw--0-ia5     23-Oct-2018 14:33                2997
ber01-VHDL13_DWLG_231533-1810231533-dsw--0-ia5     23-Oct-2018 15:33                2997
ber01-VHDL13_DWLG_231633-1810231633-dsw--0-ia5     23-Oct-2018 16:33                2937
ber01-VHDL13_DWLG_231733-1810231733-dsw--0-ia5     23-Oct-2018 17:33                2591
ber01-VHDL13_DWLH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2195
ber01-VHDL13_DWLH_211933-1810211933-dsw--0-ia5     21-Oct-2018 19:33                2223
ber01-VHDL13_DWLH_212033-1810212033-dsw--0-ia5     21-Oct-2018 20:33                2223
ber01-VHDL13_DWLH_220033-1810220033-dsw--0-ia5     22-Oct-2018 00:33                2297
ber01-VHDL13_DWLH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2585
ber01-VHDL13_DWLH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2848
ber01-VHDL13_DWLH_220533-1810220533-dsw--0-ia5     22-Oct-2018 05:33                2876
ber01-VHDL13_DWLH_220633-1810220633-dsw--0-ia5     22-Oct-2018 06:33                2876
ber01-VHDL13_DWLH_220733-1810220733-dsw--0-ia5     22-Oct-2018 07:33                2849
ber01-VHDL13_DWLH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2821
ber01-VHDL13_DWLH_220933-1810220933-dsw--0-ia5     22-Oct-2018 09:33                2849
ber01-VHDL13_DWLH_221033-1810221033-dsw--0-ia5     22-Oct-2018 10:33                2953
ber01-VHDL13_DWLH_221133-1810221133-dsw--0-ia5     22-Oct-2018 11:33                2953
ber01-VHDL13_DWLH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2928
ber01-VHDL13_DWLH_221333-1810221333-dsw--0-ia5     22-Oct-2018 13:33                2861
ber01-VHDL13_DWLH_221433-1810221433-dsw--0-ia5     22-Oct-2018 14:33                2796
ber01-VHDL13_DWLH_221533-1810221533-dsw--0-ia5     22-Oct-2018 15:33                2796
ber01-VHDL13_DWLH_221633-1810221633-dsw--0-ia5     22-Oct-2018 16:33                2796
ber01-VHDL13_DWLH_221733-1810221733-dsw--0-ia5     22-Oct-2018 17:33                2672
ber01-VHDL13_DWLH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2644
ber01-VHDL13_DWLH_221933-1810221933-dsw--0-ia5     22-Oct-2018 19:33                2698
ber01-VHDL13_DWLH_222033-1810222033-dsw--0-ia5     22-Oct-2018 20:33                2698
ber01-VHDL13_DWLH_230033-1810230033-dsw--0-ia5     23-Oct-2018 00:33                2544
ber01-VHDL13_DWLH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2583
ber01-VHDL13_DWLH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2583
ber01-VHDL13_DWLH_230533-1810230533-dsw--0-ia5     23-Oct-2018 05:33                2611
ber01-VHDL13_DWLH_230633-1810230633-dsw--0-ia5     23-Oct-2018 06:33                2611
ber01-VHDL13_DWLH_230733-1810230733-dsw--0-ia5     23-Oct-2018 07:33                2416
ber01-VHDL13_DWLH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2388
ber01-VHDL13_DWLH_230933-1810230933-dsw--0-ia5     23-Oct-2018 09:33                2416
ber01-VHDL13_DWLH_231033-1810231033-dsw--0-ia5     23-Oct-2018 10:33                2416
ber01-VHDL13_DWLH_231133-1810231133-dsw--0-ia5     23-Oct-2018 11:33                2380
ber01-VHDL13_DWLH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2404
ber01-VHDL13_DWLH_231333-1810231333-dsw--0-ia5     23-Oct-2018 13:33                2405
ber01-VHDL13_DWLH_231433-1810231433-dsw--0-ia5     23-Oct-2018 14:33                2405
ber01-VHDL13_DWLH_231533-1810231533-dsw--0-ia5     23-Oct-2018 15:33                2405
ber01-VHDL13_DWLH_231633-1810231633-dsw--0-ia5     23-Oct-2018 16:33                2374
ber01-VHDL13_DWLH_231733-1810231733-dsw--0-ia5     23-Oct-2018 17:33                2091
ber01-VHDL13_DWLI_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2074
ber01-VHDL13_DWLI_211933-1810211933-dsw--0-ia5     21-Oct-2018 19:33                2102
ber01-VHDL13_DWLI_212033-1810212033-dsw--0-ia5     21-Oct-2018 20:33                2102
ber01-VHDL13_DWLI_220033-1810220033-dsw--0-ia5     22-Oct-2018 00:33                2230
ber01-VHDL13_DWLI_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2251
ber01-VHDL13_DWLI_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2461
ber01-VHDL13_DWLI_220533-1810220533-dsw--0-ia5     22-Oct-2018 05:33                2489
ber01-VHDL13_DWLI_220633-1810220633-dsw--0-ia5     22-Oct-2018 06:33                2489
ber01-VHDL13_DWLI_220733-1810220733-dsw--0-ia5     22-Oct-2018 07:33                2486
ber01-VHDL13_DWLI_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2456
ber01-VHDL13_DWLI_220933-1810220933-dsw--0-ia5     22-Oct-2018 09:33                2484
ber01-VHDL13_DWLI_221033-1810221033-dsw--0-ia5     22-Oct-2018 10:33                2501
ber01-VHDL13_DWLI_221133-1810221133-dsw--0-ia5     22-Oct-2018 11:33                2501
ber01-VHDL13_DWLI_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2458
ber01-VHDL13_DWLI_221333-1810221333-dsw--0-ia5     22-Oct-2018 13:33                2463
ber01-VHDL13_DWLI_221433-1810221433-dsw--0-ia5     22-Oct-2018 14:33                2463
ber01-VHDL13_DWLI_221533-1810221533-dsw--0-ia5     22-Oct-2018 15:33                2426
ber01-VHDL13_DWLI_221633-1810221633-dsw--0-ia5     22-Oct-2018 16:33                2426
ber01-VHDL13_DWLI_221733-1810221733-dsw--0-ia5     22-Oct-2018 17:33                2283
ber01-VHDL13_DWLI_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2255
ber01-VHDL13_DWLI_221933-1810221933-dsw--0-ia5     22-Oct-2018 19:33                2312
ber01-VHDL13_DWLI_222033-1810222033-dsw--0-ia5     22-Oct-2018 20:33                2312
ber01-VHDL13_DWLI_230033-1810230033-dsw--0-ia5     23-Oct-2018 00:33                2216
ber01-VHDL13_DWLI_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2292
ber01-VHDL13_DWLI_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2313
ber01-VHDL13_DWLI_230533-1810230533-dsw--0-ia5     23-Oct-2018 05:33                2341
ber01-VHDL13_DWLI_230633-1810230633-dsw--0-ia5     23-Oct-2018 06:33                2341
ber01-VHDL13_DWLI_230733-1810230733-dsw--0-ia5     23-Oct-2018 07:33                2337
ber01-VHDL13_DWLI_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2309
ber01-VHDL13_DWLI_230933-1810230933-dsw--0-ia5     23-Oct-2018 09:33                2337
ber01-VHDL13_DWLI_231033-1810231033-dsw--0-ia5     23-Oct-2018 10:33                2337
ber01-VHDL13_DWLI_231133-1810231133-dsw--0-ia5     23-Oct-2018 11:33                2339
ber01-VHDL13_DWLI_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2295
ber01-VHDL13_DWLI_231333-1810231333-dsw--0-ia5     23-Oct-2018 13:33                2296
ber01-VHDL13_DWLI_231433-1810231433-dsw--0-ia5     23-Oct-2018 14:33                2296
ber01-VHDL13_DWLI_231533-1810231533-dsw--0-ia5     23-Oct-2018 15:33                2296
ber01-VHDL13_DWLI_231633-1810231633-dsw--0-ia5     23-Oct-2018 16:33                2299
ber01-VHDL13_DWLI_231733-1810231733-dsw--0-ia5     23-Oct-2018 17:33                1932
ber01-VHDL13_DWMG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2753
ber01-VHDL13_DWMG_211900-1810211900-dsw--0-ia5     21-Oct-2018 19:30                2753
ber01-VHDL13_DWMG_212000-1810212000-dsw--0-ia5     21-Oct-2018 20:30                2641
ber01-VHDL13_DWMG_212100-1810212100-dsw--0-ia5     21-Oct-2018 21:30                2641
ber01-VHDL13_DWMG_212200-1810212200-dsw--0-ia5     21-Oct-2018 22:30                2682
ber01-VHDL13_DWMG_212300-1810212300-dsw--0-ia5     21-Oct-2018 23:30                2682
ber01-VHDL13_DWMG_220000-1810220000-dsw--0-ia5     22-Oct-2018 00:30                2682
ber01-VHDL13_DWMG_220100-1810220100-dsw--0-ia5     22-Oct-2018 01:30                2682
ber01-VHDL13_DWMG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2667
ber01-VHDL13_DWMG_220300-1810220300-dsw--0-ia5     22-Oct-2018 03:30                2603
ber01-VHDL13_DWMG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2570
ber01-VHDL13_DWMG_220500-1810220500-dsw--0-ia5     22-Oct-2018 05:30                2570
ber01-VHDL13_DWMG_220600-1810220600-dsw--0-ia5     22-Oct-2018 06:30                2570
ber01-VHDL13_DWMG_220700-1810220700-dsw--0-ia5     22-Oct-2018 07:30                2570
ber01-VHDL13_DWMG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                3014
ber01-VHDL13_DWMG_220900-1810220900-dsw--0-ia5     22-Oct-2018 09:30                2897
ber01-VHDL13_DWMG_221000-1810221000-dsw--0-ia5     22-Oct-2018 10:30                2897
ber01-VHDL13_DWMG_221100-1810221100-dsw--0-ia5     22-Oct-2018 11:30                2897
ber01-VHDL13_DWMG_221200-1810221200-dsw--0-ia5     22-Oct-2018 12:30                2902
ber01-VHDL13_DWMG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2902
ber01-VHDL13_DWMG_221400-1810221400-dsw--0-ia5     22-Oct-2018 14:30                2891
ber01-VHDL13_DWMG_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                2909
ber01-VHDL13_DWMG_221600-1810221600-dsw--0-ia5     22-Oct-2018 16:30                2909
ber01-VHDL13_DWMG_221700-1810221700-dsw--0-ia5     22-Oct-2018 17:30                2806
ber01-VHDL13_DWMG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2834
ber01-VHDL13_DWMG_221900-1810221900-dsw--0-ia5     22-Oct-2018 19:30                2834
ber01-VHDL13_DWMG_222000-1810222000-dsw--0-ia5     22-Oct-2018 20:30                2834
ber01-VHDL13_DWMG_222100-1810222100-dsw--0-ia5     22-Oct-2018 21:30                2739
ber01-VHDL13_DWMG_222200-1810222200-dsw--0-ia5     22-Oct-2018 22:30                3618
ber01-VHDL13_DWMG_222300-1810222300-dsw--0-ia5     22-Oct-2018 23:30                3612
ber01-VHDL13_DWMG_230000-1810230000-dsw--0-ia5     23-Oct-2018 00:30                3612
ber01-VHDL13_DWMG_230100-1810230100-dsw--0-ia5     23-Oct-2018 01:30                3468
ber01-VHDL13_DWMG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                3615
ber01-VHDL13_DWMG_230300-1810230300-dsw--0-ia5     23-Oct-2018 03:30                3615
ber01-VHDL13_DWMG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                3559
ber01-VHDL13_DWMG_230500-1810230500-dsw--0-ia5     23-Oct-2018 05:30                3559
ber01-VHDL13_DWMG_230600-1810230600-dsw--0-ia5     23-Oct-2018 06:30                3559
ber01-VHDL13_DWMG_230700-1810230700-dsw--0-ia5     23-Oct-2018 07:30                3559
ber01-VHDL13_DWMG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                3299
ber01-VHDL13_DWMG_230900-1810230900-dsw--0-ia5     23-Oct-2018 09:30                3299
ber01-VHDL13_DWMG_231000-1810231000-dsw--0-ia5     23-Oct-2018 10:30                3259
ber01-VHDL13_DWMG_231100-1810231100-dsw--0-ia5     23-Oct-2018 11:30                3259
ber01-VHDL13_DWMG_231200-1810231200-dsw--0-ia5     23-Oct-2018 12:30                3332
ber01-VHDL13_DWMG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                3332
ber01-VHDL13_DWMG_231400-1810231400-dsw--0-ia5     23-Oct-2018 14:30                3332
ber01-VHDL13_DWMG_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                3332
ber01-VHDL13_DWMG_231600-1810231600-dsw--0-ia5     23-Oct-2018 16:30                3332
ber01-VHDL13_DWMG_231700-1810231700-dsw--0-ia5     23-Oct-2018 17:30                2874
ber01-VHDL13_DWMO_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2515
ber01-VHDL13_DWMO_211900-1810211900-dsw--0-ia5     21-Oct-2018 19:30                2515
ber01-VHDL13_DWMO_212000-1810212000-dsw--0-ia5     21-Oct-2018 20:30                2374
ber01-VHDL13_DWMO_212100-1810212100-dsw--0-ia5     21-Oct-2018 21:30                2356
ber01-VHDL13_DWMO_212200-1810212200-dsw--0-ia5     21-Oct-2018 22:30                2495
ber01-VHDL13_DWMO_212300-1810212300-dsw--0-ia5     21-Oct-2018 23:30                2495
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ber01-VHDL13_DWMO_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2827
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ber01-VHDL13_DWMO_221100-1810221100-dsw--0-ia5     22-Oct-2018 11:30                2749
ber01-VHDL13_DWMO_221200-1810221200-dsw--0-ia5     22-Oct-2018 12:30                2752
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ber01-VHDL13_DWMO_221400-1810221400-dsw--0-ia5     22-Oct-2018 14:30                2509
ber01-VHDL13_DWMO_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                2495
ber01-VHDL13_DWMO_221600-1810221600-dsw--0-ia5     22-Oct-2018 16:30                2495
ber01-VHDL13_DWMO_221700-1810221700-dsw--0-ia5     22-Oct-2018 17:30                2445
ber01-VHDL13_DWMO_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2445
ber01-VHDL13_DWMO_221900-1810221900-dsw--0-ia5     22-Oct-2018 19:30                2479
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ber01-VHDL13_DWMO_222100-1810222100-dsw--0-ia5     22-Oct-2018 21:30                2574
ber01-VHDL13_DWMO_222200-1810222200-dsw--0-ia5     22-Oct-2018 22:30                2909
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ber01-VHDL13_DWMO_230000-1810230000-dsw--0-ia5     23-Oct-2018 00:30                2909
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ber01-VHDL13_DWMO_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2881
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ber01-VHDL13_DWMO_230600-1810230600-dsw--0-ia5     23-Oct-2018 06:30                2881
ber01-VHDL13_DWMO_230700-1810230700-dsw--0-ia5     23-Oct-2018 07:30                2881
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ber01-VHDL13_DWMO_231100-1810231100-dsw--0-ia5     23-Oct-2018 11:30                2820
ber01-VHDL13_DWMO_231200-1810231200-dsw--0-ia5     23-Oct-2018 12:30                2820
ber01-VHDL13_DWMO_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2820
ber01-VHDL13_DWMO_231400-1810231400-dsw--0-ia5     23-Oct-2018 14:30                2814
ber01-VHDL13_DWMO_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                2814
ber01-VHDL13_DWMO_231600-1810231600-dsw--0-ia5     23-Oct-2018 16:30                2814
ber01-VHDL13_DWMO_231700-1810231700-dsw--0-ia5     23-Oct-2018 17:30                2393
ber01-VHDL13_DWMP_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2694
ber01-VHDL13_DWMP_211900-1810211900-dsw--0-ia5     21-Oct-2018 19:30                2694
ber01-VHDL13_DWMP_212000-1810212000-dsw--0-ia5     21-Oct-2018 20:30                2578
ber01-VHDL13_DWMP_212100-1810212100-dsw--0-ia5     21-Oct-2018 21:30                2578
ber01-VHDL13_DWMP_212200-1810212200-dsw--0-ia5     21-Oct-2018 22:30                2828
ber01-VHDL13_DWMP_212300-1810212300-dsw--0-ia5     21-Oct-2018 23:30                2816
ber01-VHDL13_DWMP_220000-1810220000-dsw--0-ia5     22-Oct-2018 00:30                2816
ber01-VHDL13_DWMP_220100-1810220100-dsw--0-ia5     22-Oct-2018 01:30                2816
ber01-VHDL13_DWMP_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2835
ber01-VHDL13_DWMP_220300-1810220300-dsw--0-ia5     22-Oct-2018 03:30                2878
ber01-VHDL13_DWMP_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2823
ber01-VHDL13_DWMP_220500-1810220500-dsw--0-ia5     22-Oct-2018 05:30                2823
ber01-VHDL13_DWMP_220600-1810220600-dsw--0-ia5     22-Oct-2018 06:30                2823
ber01-VHDL13_DWMP_220700-1810220700-dsw--0-ia5     22-Oct-2018 07:30                2823
ber01-VHDL13_DWMP_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2874
ber01-VHDL13_DWMP_220900-1810220900-dsw--0-ia5     22-Oct-2018 09:30                2809
ber01-VHDL13_DWMP_221000-1810221000-dsw--0-ia5     22-Oct-2018 10:30                2809
ber01-VHDL13_DWMP_221100-1810221100-dsw--0-ia5     22-Oct-2018 11:30                2809
ber01-VHDL13_DWMP_221200-1810221200-dsw--0-ia5     22-Oct-2018 12:30                2785
ber01-VHDL13_DWMP_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2785
ber01-VHDL13_DWMP_221400-1810221400-dsw--0-ia5     22-Oct-2018 14:30                2726
ber01-VHDL13_DWMP_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                2744
ber01-VHDL13_DWMP_221600-1810221600-dsw--0-ia5     22-Oct-2018 16:30                2744
ber01-VHDL13_DWMP_221700-1810221700-dsw--0-ia5     22-Oct-2018 17:30                2734
ber01-VHDL13_DWMP_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2734
ber01-VHDL13_DWMP_221900-1810221900-dsw--0-ia5     22-Oct-2018 19:30                2867
ber01-VHDL13_DWMP_222000-1810222000-dsw--0-ia5     22-Oct-2018 20:30                2867
ber01-VHDL13_DWMP_222100-1810222100-dsw--0-ia5     22-Oct-2018 21:30                2800
ber01-VHDL13_DWMP_222200-1810222200-dsw--0-ia5     22-Oct-2018 22:30                3666
ber01-VHDL13_DWMP_222300-1810222300-dsw--0-ia5     22-Oct-2018 23:30                3666
ber01-VHDL13_DWMP_230000-1810230000-dsw--0-ia5     23-Oct-2018 00:30                3666
ber01-VHDL13_DWMP_230100-1810230100-dsw--0-ia5     23-Oct-2018 01:30                3583
ber01-VHDL13_DWMP_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                3583
ber01-VHDL13_DWMP_230300-1810230300-dsw--0-ia5     23-Oct-2018 03:30                3583
ber01-VHDL13_DWMP_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                3563
ber01-VHDL13_DWMP_230500-1810230500-dsw--0-ia5     23-Oct-2018 05:30                3563
ber01-VHDL13_DWMP_230600-1810230600-dsw--0-ia5     23-Oct-2018 06:30                3563
ber01-VHDL13_DWMP_230700-1810230700-dsw--0-ia5     23-Oct-2018 07:30                3563
ber01-VHDL13_DWMP_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                3556
ber01-VHDL13_DWMP_230900-1810230900-dsw--0-ia5     23-Oct-2018 09:30                3495
ber01-VHDL13_DWMP_231000-1810231000-dsw--0-ia5     23-Oct-2018 10:30                3495
ber01-VHDL13_DWMP_231100-1810231100-dsw--0-ia5     23-Oct-2018 11:30                3400
ber01-VHDL13_DWMP_231200-1810231200-dsw--0-ia5     23-Oct-2018 12:30                3400
ber01-VHDL13_DWMP_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                3400
ber01-VHDL13_DWMP_231400-1810231400-dsw--0-ia5     23-Oct-2018 14:30                3397
ber01-VHDL13_DWMP_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                3397
ber01-VHDL13_DWMP_231600-1810231600-dsw--0-ia5     23-Oct-2018 16:30                3397
ber01-VHDL13_DWMP_231700-1810231700-dsw--0-ia5     23-Oct-2018 17:30                3064
ber01-VHDL13_DWOG_220100-1810220100-dsw--0-ia5     22-Oct-2018 01:45                4398
ber01-VHDL13_DWOG_220300-1810220300-dsw--0-ia5     22-Oct-2018 03:00                4903
ber01-VHDL13_DWOG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:15                5065
ber01-VHDL13_DWOG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:00                4872
ber01-VHDL13_DWOG_221700-1810221700-dsw--0-ia5     22-Oct-2018 17:30                4627
ber01-VHDL13_DWOG_230100-1810230100-dsw--0-ia5     23-Oct-2018 01:45                5867
ber01-VHDL13_DWOG_230300-1810230300-dsw--0-ia5     23-Oct-2018 03:00                5986
ber01-VHDL13_DWOG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:15                5984
ber01-VHDL13_DWOG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:00                5301
ber01-VHDL13_DWOG_231700-1810231700-dsw--0-ia5     23-Oct-2018 17:30                4663
ber01-VHDL13_DWOH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:28                2714
ber01-VHDL13_DWOH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:28                2584
ber01-VHDL13_DWOH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:58                2877
ber01-VHDL13_DWOH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:28                2550
ber01-VHDL13_DWOH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:28                2542
ber01-VHDL13_DWOH_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:28                2532
ber01-VHDL13_DWOH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:28                2369
ber01-VHDL13_DWOH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:28                2917
ber01-VHDL13_DWOH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:58                2878
ber01-VHDL13_DWOH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:28                2704
ber01-VHDL13_DWOH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:28                2705
ber01-VHDL13_DWOH_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:28                2630
ber01-VHDL13_DWOI_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:28                2746
ber01-VHDL13_DWOI_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:28                2492
ber01-VHDL13_DWOI_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:58                2559
ber01-VHDL13_DWOI_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:28                2261
ber01-VHDL13_DWOI_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:28                2245
ber01-VHDL13_DWOI_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:28                2188
ber01-VHDL13_DWOI_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:28                2186
ber01-VHDL13_DWOI_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:28                2543
ber01-VHDL13_DWOI_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:58                2497
ber01-VHDL13_DWOI_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:28                2490
ber01-VHDL13_DWOI_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:28                2668
ber01-VHDL13_DWOI_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:28                2581
ber01-VHDL13_DWON_212045-1810212045-dsw--0-ia5     21-Oct-2018 20:45                4244
ber01-VHDL13_DWON_220121-1810220121-dsw--0-ia5     22-Oct-2018 01:21                4320
ber01-VHDL13_DWON_220253-1810220253-dsw--0-ia5     22-Oct-2018 02:53                4350
ber01-VHDL13_DWON_220257-1810220257-dsw--0-ia5     22-Oct-2018 02:57                4350
ber01-VHDL13_DWON_220526-1810220526-dsw--0-ia5     22-Oct-2018 05:26                4272
ber01-VHDL13_DWON_220655-1810220655-dsw--0-ia5     22-Oct-2018 06:55                4344
ber01-VHDL13_DWON_221149-1810221149-dsw--0-ia5     22-Oct-2018 11:49                4287
ber01-VHDL13_DWON_221439-1810221439-dsw--0-ia5     22-Oct-2018 14:39                4565
ber01-VHDL13_DWON_221648-1810221648-dsw--0-ia5     22-Oct-2018 16:48                4502
ber01-VHDL13_DWON_221931-1810221931-dsw--0-ia5     22-Oct-2018 19:31                4613
ber01-VHDL13_DWON_222137-1810222137-dsw--0-ia5     22-Oct-2018 21:37                4613
ber01-VHDL13_DWON_222217-1810222217-dsw--0-ia5     22-Oct-2018 22:17                4697
ber01-VHDL13_DWON_230246-1810230246-dsw--0-ia5     23-Oct-2018 02:47                4697
ber01-VHDL13_DWON_230514-1810230514-dsw--0-ia5     23-Oct-2018 05:14                4897
ber01-VHDL13_DWON_230532-1810230532-dsw--0-ia5     23-Oct-2018 05:32                5029
ber01-VHDL13_DWON_230638-1810230638-dsw--0-ia5     23-Oct-2018 06:38                4930
ber01-VHDL13_DWON_230859-1810230859-dsw--0-ia5     23-Oct-2018 08:59                4972
ber01-VHDL13_DWON_231107-1810231107-dsw--0-ia5     23-Oct-2018 11:07                4965
ber01-VHDL13_DWON_231434-1810231434-dsw--0-ia5     23-Oct-2018 14:34                4068
ber01-VHDL13_DWON_231711-1810231711-dsw--0-ia5     23-Oct-2018 17:11                4060
ber01-VHDL13_DWPG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2739
ber01-VHDL13_DWPG_211930-1810211930-dsw--0-ia5     21-Oct-2018 19:30                2739
ber01-VHDL13_DWPG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2983
ber01-VHDL13_DWPG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                3081
ber01-VHDL13_DWPG_220530-1810220530-dsw--0-ia5     22-Oct-2018 05:30                3053
ber01-VHDL13_DWPG_220630-1810220630-dsw--0-ia5     22-Oct-2018 06:30                3039
ber01-VHDL13_DWPG_220750-1810220750-dsw--0-ia5     22-Oct-2018 07:30                3109
ber01-VHDL13_DWPG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2773
ber01-VHDL13_DWPG_220930-1810220930-dsw--0-ia5     22-Oct-2018 09:30                2773
ber01-VHDL13_DWPG_221030-1810221030-dsw--0-ia5     22-Oct-2018 10:30                2773
ber01-VHDL13_DWPG_221130-1810221130-dsw--0-ia5     22-Oct-2018 11:30                2766
ber01-VHDL13_DWPG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2824
ber01-VHDL13_DWPG_221330-1810221330-dsw--0-ia5     22-Oct-2018 13:30                2824
ber01-VHDL13_DWPG_221450-1810221450-dsw--0-ia5     22-Oct-2018 14:30                2824
ber01-VHDL13_DWPG_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                2914
ber01-VHDL13_DWPG_221630-1810221630-dsw--0-ia5     22-Oct-2018 16:30                2914
ber01-VHDL13_DWPG_221750-1810221750-dsw--0-ia5     22-Oct-2018 17:30                2914
ber01-VHDL13_DWPG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2833
ber01-VHDL13_DWPG_221930-1810221930-dsw--0-ia5     22-Oct-2018 19:30                2833
ber01-VHDL13_DWPG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2631
ber01-VHDL13_DWPG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2491
ber01-VHDL13_DWPG_230530-1810230530-dsw--0-ia5     23-Oct-2018 05:30                2490
ber01-VHDL13_DWPG_230630-1810230630-dsw--0-ia5     23-Oct-2018 06:30                2392
ber01-VHDL13_DWPG_230750-1810230750-dsw--0-ia5     23-Oct-2018 07:30                2392
ber01-VHDL13_DWPG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2434
ber01-VHDL13_DWPG_230930-1810230930-dsw--0-ia5     23-Oct-2018 09:30                2434
ber01-VHDL13_DWPG_231030-1810231030-dsw--0-ia5     23-Oct-2018 10:30                2434
ber01-VHDL13_DWPG_231130-1810231130-dsw--0-ia5     23-Oct-2018 11:30                2380
ber01-VHDL13_DWPG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2523
ber01-VHDL13_DWPG_231330-1810231330-dsw--0-ia5     23-Oct-2018 13:30                2523
ber01-VHDL13_DWPG_231450-1810231450-dsw--0-ia5     23-Oct-2018 14:30                2523
ber01-VHDL13_DWPG_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                2669
ber01-VHDL13_DWPG_231630-1810231630-dsw--0-ia5     23-Oct-2018 16:30                2669
ber01-VHDL13_DWPG_231750-1810231750-dsw--0-ia5     23-Oct-2018 17:30                2669
ber01-VHDL13_DWPH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2968
ber01-VHDL13_DWPH_211930-1810211930-dsw--0-ia5     21-Oct-2018 19:30                2968
ber01-VHDL13_DWPH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                3528
ber01-VHDL13_DWPH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                3848
ber01-VHDL13_DWPH_220530-1810220530-dsw--0-ia5     22-Oct-2018 05:30                3763
ber01-VHDL13_DWPH_220630-1810220630-dsw--0-ia5     22-Oct-2018 06:30                3728
ber01-VHDL13_DWPH_220750-1810220750-dsw--0-ia5     22-Oct-2018 07:30                3728
ber01-VHDL13_DWPH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                3457
ber01-VHDL13_DWPH_220930-1810220930-dsw--0-ia5     22-Oct-2018 09:30                3457
ber01-VHDL13_DWPH_221030-1810221030-dsw--0-ia5     22-Oct-2018 10:30                3457
ber01-VHDL13_DWPH_221130-1810221130-dsw--0-ia5     22-Oct-2018 11:30                3388
ber01-VHDL13_DWPH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                3568
ber01-VHDL13_DWPH_221330-1810221330-dsw--0-ia5     22-Oct-2018 13:30                3568
ber01-VHDL13_DWPH_221450-1810221450-dsw--0-ia5     22-Oct-2018 14:30                3568
ber01-VHDL13_DWPH_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                3536
ber01-VHDL13_DWPH_221630-1810221630-dsw--0-ia5     22-Oct-2018 16:30                3536
ber01-VHDL13_DWPH_221750-1810221750-dsw--0-ia5     22-Oct-2018 17:30                3536
ber01-VHDL13_DWPH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                3375
ber01-VHDL13_DWPH_221930-1810221930-dsw--0-ia5     22-Oct-2018 19:30                3375
ber01-VHDL13_DWPH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2875
ber01-VHDL13_DWPH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2773
ber01-VHDL13_DWPH_230530-1810230530-dsw--0-ia5     23-Oct-2018 05:30                2773
ber01-VHDL13_DWPH_230630-1810230630-dsw--0-ia5     23-Oct-2018 06:30                2884
ber01-VHDL13_DWPH_230750-1810230750-dsw--0-ia5     23-Oct-2018 07:30                2884
ber01-VHDL13_DWPH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2925
ber01-VHDL13_DWPH_230930-1810230930-dsw--0-ia5     23-Oct-2018 09:30                2925
ber01-VHDL13_DWPH_231030-1810231030-dsw--0-ia5     23-Oct-2018 10:30                2925
ber01-VHDL13_DWPH_231130-1810231130-dsw--0-ia5     23-Oct-2018 11:30                2943
ber01-VHDL13_DWPH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                3086
ber01-VHDL13_DWPH_231330-1810231330-dsw--0-ia5     23-Oct-2018 13:30                3086
ber01-VHDL13_DWPH_231450-1810231450-dsw--0-ia5     23-Oct-2018 14:30                3086
ber01-VHDL13_DWPH_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                3170
ber01-VHDL13_DWPH_231630-1810231630-dsw--0-ia5     23-Oct-2018 16:30                3170
ber01-VHDL13_DWPH_231750-1810231750-dsw--0-ia5     23-Oct-2018 17:30                3170
ber01-VHDL13_DWSG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2500
ber01-VHDL13_DWSG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2780
ber01-VHDL13_DWSG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2409
ber01-VHDL13_DWSG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2545
ber01-VHDL13_DWSG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                2590
ber01-VHDL13_DWSG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2446
ber01-VHDL13_DWSG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2760
ber01-VHDL13_DWSG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2822
ber01-VHDL13_DWSG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2833
ber01-VHDL13_DWSG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                2835
ber01-VHDL13_DWSN_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                1841
ber01-VHDL13_DWSN_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2021
ber01-VHDL13_DWSN_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2010
ber01-VHDL13_DWSN_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2011
ber01-VHDL13_DWSN_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:30                2131
ber01-VHDL13_DWSN_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                1894
ber01-VHDL13_DWSN_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2108
ber01-VHDL13_DWSN_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2513
ber01-VHDL13_DWSN_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2492
ber01-VHDL13_DWSN_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:30                2339
ber01-VHDL13_DWSO_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2278
ber01-VHDL13_DWSO_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2454
ber01-VHDL13_DWSO_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2152
ber01-VHDL13_DWSO_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2246
ber01-VHDL13_DWSO_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:30                2260
ber01-VHDL13_DWSO_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2159
ber01-VHDL13_DWSO_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2457
ber01-VHDL13_DWSO_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2750
ber01-VHDL13_DWSO_230400_COR-1810230400-dsw--0-ia5 23-Oct-2018 04:36                2728
ber01-VHDL13_DWSO_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2756
ber01-VHDL13_DWSO_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:30                2679
ber01-VHDL13_DWSP_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                2064
ber01-VHDL13_DWSP_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                2305
ber01-VHDL13_DWSP_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                2294
ber01-VHDL13_DWSP_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                2144
ber01-VHDL13_DWSP_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:30                2268
ber01-VHDL13_DWSP_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                2317
ber01-VHDL13_DWSP_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                2497
ber01-VHDL13_DWSP_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                2505
ber01-VHDL13_DWSP_230400_COR-1810230400-dsw--0-ia5 23-Oct-2018 04:36                2713
ber01-VHDL13_DWSP_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                2709
ber01-VHDL13_DWSP_230800_COR-1810230800-dsw--0-ia5 23-Oct-2018 08:37                2568
ber01-VHDL13_DWSP_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:30                2431
ber01-VHDL17_DWOG_221200-1810221200-dsw--0-ia5     22-Oct-2018 11:31                2951
ber01-VHDL17_DWOG_231200-1810231200-dsw--0-ia5     23-Oct-2018 12:09                3315
ber01-VHDL20_DWHG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4512
ber01-VHDL20_DWHG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4700
ber01-VHDL20_DWHG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4606
ber01-VHDL20_DWHG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4813
ber01-VHDL20_DWHG_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:45                4726
ber01-VHDL20_DWHG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4509
ber01-VHDL20_DWHG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4783
ber01-VHDL20_DWHG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4851
ber01-VHDL20_DWHG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4567
ber01-VHDL20_DWHG_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:45                4545
ber01-VHDL20_DWHH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                3996
ber01-VHDL20_DWHH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4163
ber01-VHDL20_DWHH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4116
ber01-VHDL20_DWHH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4184
ber01-VHDL20_DWHH_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:45                4149
ber01-VHDL20_DWHH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4011
ber01-VHDL20_DWHH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4011
ber01-VHDL20_DWHH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4025
ber01-VHDL20_DWHH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                3860
ber01-VHDL20_DWHH_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:45                3878
gts01-VHDL12_DWON_220115-1810220145-afsv--66-ia5   22-Oct-2018 01:45                3838
gts01-VHDL12_DWON_220530-1810220530-afsv--95-ia5   22-Oct-2018 05:30                3800
gts01-VHDL12_DWON_220815-1810220815-afsv--69-ia5   22-Oct-2018 08:15                3876
gts01-VHDL12_DWON_221330-1810221230-afsv--44-ia5   22-Oct-2018 12:30                3817
gts01-VHDL12_DWON_221815-1810221745-afsv--85-ia5   22-Oct-2018 17:45                4036
gts01-VHDL12_DWON_230115-1810230145-afsv--14-ia5   23-Oct-2018 01:45                4214
gts01-VHDL12_DWON_230530-1810230530-afsv--39-ia5   23-Oct-2018 05:30                4417
gts01-VHDL12_DWON_230815-1810230815-afsv--22-ia5   23-Oct-2018 08:15                4305
gts01-VHDL12_DWON_231330-1810231230-afsv--87-ia5   23-Oct-2018 12:30                4342
gts01-VHDL12_DWON_231815-1810231745-afsv--31-ia5   23-Oct-2018 17:45                3371
pid-VHDL12_DWEH_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:28                2082
pid-VHDL12_DWEH_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:28                2558
pid-VHDL12_DWHG_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2464
pid-VHDL12_DWHG_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2375
pid-VHDL12_DWHG_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2525
pid-VHDL12_DWHG_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2598
pid-VHDL12_DWHH_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2703
pid-VHDL12_DWHH_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2664
pid-VHDL12_DWHH_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2526
pid-VHDL12_DWHH_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2547
pid-VHDL12_DWLG_211800-1810211800-dsw--0-ia5       21-Oct-2018 18:30                1866
pid-VHDL12_DWLG_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2272
pid-VHDL12_DWLG_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2368
pid-VHDL12_DWLG_220800-1810220800-dsw--0-ia5       22-Oct-2018 08:30                2426
pid-VHDL12_DWLG_221300-1810221300-dsw--0-ia5       22-Oct-2018 12:30                2498
pid-VHDL12_DWLG_221800-1810221800-dsw--0-ia5       22-Oct-2018 18:30                2250
pid-VHDL12_DWLG_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2418
pid-VHDL12_DWLG_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2476
pid-VHDL12_DWLG_230800-1810230800-dsw--0-ia5       23-Oct-2018 08:30                2696
pid-VHDL12_DWLG_231300-1810231300-dsw--0-ia5       23-Oct-2018 12:30                2678
pid-VHDL12_DWLH_211800-1810211800-dsw--0-ia5       21-Oct-2018 18:30                1784
pid-VHDL12_DWLH_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2216
pid-VHDL12_DWLH_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2479
pid-VHDL12_DWLH_220800-1810220800-dsw--0-ia5       22-Oct-2018 08:30                2452
pid-VHDL12_DWLH_221300-1810221300-dsw--0-ia5       22-Oct-2018 12:30                2559
pid-VHDL12_DWLH_221800-1810221800-dsw--0-ia5       22-Oct-2018 18:30                2275
pid-VHDL12_DWLH_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2258
pid-VHDL12_DWLH_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2258
pid-VHDL12_DWLH_230800-1810230800-dsw--0-ia5       23-Oct-2018 08:30                2063
pid-VHDL12_DWLH_231300-1810231300-dsw--0-ia5       23-Oct-2018 12:30                2079
pid-VHDL12_DWLI_211800-1810211800-dsw--0-ia5       21-Oct-2018 18:30                1720
pid-VHDL12_DWLI_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                1904
pid-VHDL12_DWLI_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2114
pid-VHDL12_DWLI_220800-1810220800-dsw--0-ia5       22-Oct-2018 08:30                2109
pid-VHDL12_DWLI_221300-1810221300-dsw--0-ia5       22-Oct-2018 12:30                2111
pid-VHDL12_DWLI_221800-1810221800-dsw--0-ia5       22-Oct-2018 18:30                1908
pid-VHDL12_DWLI_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                1970
pid-VHDL12_DWLI_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                1991
pid-VHDL12_DWLI_230800-1810230800-dsw--0-ia5       23-Oct-2018 08:30                1987
pid-VHDL12_DWLI_231300-1810231300-dsw--0-ia5       23-Oct-2018 12:30                1973
pid-VHDL12_DWMG_211800-1810211800-dsw--0-ia5       21-Oct-2018 18:30                2103
pid-VHDL12_DWMG_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2274
pid-VHDL12_DWMG_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2177
pid-VHDL12_DWMG_220800-1810220800-dsw--0-ia5       22-Oct-2018 08:30                2621
pid-VHDL12_DWMG_221300-1810221300-dsw--0-ia5       22-Oct-2018 12:30                2559
pid-VHDL12_DWMG_221800-1810221800-dsw--0-ia5       22-Oct-2018 18:30                2383
pid-VHDL12_DWMG_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                3162
pid-VHDL12_DWMG_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                3106
pid-VHDL12_DWMG_230800-1810230800-dsw--0-ia5       23-Oct-2018 08:30                2843
pid-VHDL12_DWMG_231300-1810231300-dsw--0-ia5       23-Oct-2018 12:30                2852
pid-VHDL12_DWOG_220100-1810220100-dsw--0-ia5       22-Oct-2018 01:45                3807
pid-VHDL12_DWOG_220300-1810220300-dsw--0-ia5       22-Oct-2018 03:00                4312
pid-VHDL12_DWOG_230100-1810230100-dsw--0-ia5       23-Oct-2018 01:45                5256
pid-VHDL12_DWOG_230300-1810230300-dsw--0-ia5       23-Oct-2018 03:00                5375
pid-VHDL12_DWOH_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:28                2193
pid-VHDL12_DWOH_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:28                2579
pid-VHDL12_DWOI_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:28                2102
pid-VHDL12_DWOI_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:28                2181
pid-VHDL12_DWPG_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2656
pid-VHDL12_DWPG_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                2754
pid-VHDL12_DWPG_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2333
pid-VHDL12_DWPG_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2200
pid-VHDL12_DWPH_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                3142
pid-VHDL12_DWPH_220400-1810220400-dsw--0-ia5       22-Oct-2018 04:30                3462
pid-VHDL12_DWPH_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2438
pid-VHDL12_DWPH_230400-1810230400-dsw--0-ia5       23-Oct-2018 04:30                2336
pid-VHDL12_DWSG_220200-1810220200-dsw--0-ia5       22-Oct-2018 02:30                2422
pid-VHDL12_DWSG_230200-1810230200-dsw--0-ia5       23-Oct-2018 02:30                2306
swis2-VHDL20_DWEG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4639
swis2-VHDL20_DWEG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4373
swis2-VHDL20_DWEG_220400-1810220400-dsw--0-ia5     22-Oct-2018 05:15                4705
swis2-VHDL20_DWEG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4384
swis2-VHDL20_DWEG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4377
swis2-VHDL20_DWEG_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:45                4369
swis2-VHDL20_DWEG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4208
swis2-VHDL20_DWEG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4709
swis2-VHDL20_DWEG_230400-1810230400-dsw--0-ia5     23-Oct-2018 05:15                4715
swis2-VHDL20_DWEG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4550
swis2-VHDL20_DWEG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                4537
swis2-VHDL20_DWEG_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:45                4459
swis2-VHDL20_DWEH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4518
swis2-VHDL20_DWEH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4342
swis2-VHDL20_DWEH_220400-1810220400-dsw--0-ia5     22-Oct-2018 05:15                4640
swis2-VHDL20_DWEH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                5236
swis2-VHDL20_DWEH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4554
swis2-VHDL20_DWEH_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:45                4420
swis2-VHDL20_DWEH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4413
swis2-VHDL20_DWEH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4792
swis2-VHDL20_DWEH_230400-1810230400-dsw--0-ia5     23-Oct-2018 05:15                4745
swis2-VHDL20_DWEH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                5296
swis2-VHDL20_DWEH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                4519
swis2-VHDL20_DWEH_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:45                4496
swis2-VHDL20_DWEI_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4673
swis2-VHDL20_DWEI_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4279
swis2-VHDL20_DWEI_220400-1810220400-dsw--0-ia5     22-Oct-2018 05:15                4400
swis2-VHDL20_DWEI_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4094
swis2-VHDL20_DWEI_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4085
swis2-VHDL20_DWEI_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:45                4026
swis2-VHDL20_DWEI_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4021
swis2-VHDL20_DWEI_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4338
swis2-VHDL20_DWEI_230400-1810230400-dsw--0-ia5     23-Oct-2018 05:15                4337
swis2-VHDL20_DWEI_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4325
swis2-VHDL20_DWEI_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:46                4516
swis2-VHDL20_DWEI_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:45                4427
swis2-VHDL20_DWHG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4512
swis2-VHDL20_DWHG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4700
swis2-VHDL20_DWHG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4606
swis2-VHDL20_DWHG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4813
swis2-VHDL20_DWHG_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:45                4726
swis2-VHDL20_DWHG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4509
swis2-VHDL20_DWHG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4783
swis2-VHDL20_DWHG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4851
swis2-VHDL20_DWHG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4567
swis2-VHDL20_DWHG_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:45                4545
swis2-VHDL20_DWHH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                3996
swis2-VHDL20_DWHH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4163
swis2-VHDL20_DWHH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4116
swis2-VHDL20_DWHH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4184
swis2-VHDL20_DWHH_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:45                4149
swis2-VHDL20_DWHH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4011
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swis2-VHDL20_DWLG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4507
swis2-VHDL20_DWLG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4579
swis2-VHDL20_DWLG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4331
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swis2-VHDL20_DWLG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4708
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swis2-VHDL20_DWLH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4524
swis2-VHDL20_DWLH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4631
swis2-VHDL20_DWLH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4347
swis2-VHDL20_DWLH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4286
swis2-VHDL20_DWLH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4277
swis2-VHDL20_DWLH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4082
swis2-VHDL20_DWLH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                4098
swis2-VHDL20_DWLI_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                3773
swis2-VHDL20_DWLI_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                3950
swis2-VHDL20_DWLI_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4163
swis2-VHDL20_DWLI_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4158
swis2-VHDL20_DWLI_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4160
swis2-VHDL20_DWLI_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                3957
swis2-VHDL20_DWLI_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                3994
swis2-VHDL20_DWLI_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4006
swis2-VHDL20_DWLI_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4002
swis2-VHDL20_DWLI_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                3988
swis2-VHDL20_DWMG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                5725
swis2-VHDL20_DWMG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                5597
swis2-VHDL20_DWMG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                5544
swis2-VHDL20_DWMG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                5352
swis2-VHDL20_DWMG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                5876
swis2-VHDL20_DWMG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                5801
swis2-VHDL20_DWMG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                6594
swis2-VHDL20_DWMG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                6530
swis2-VHDL20_DWMG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                5637
swis2-VHDL20_DWMG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                6300
swis2-VHDL20_DWMO_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4526
swis2-VHDL20_DWMO_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4489
swis2-VHDL20_DWMO_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                4401
swis2-VHDL20_DWMO_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4809
swis2-VHDL20_DWMO_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                4658
swis2-VHDL20_DWMO_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4392
swis2-VHDL20_DWMO_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4880
swis2-VHDL20_DWMO_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4828
swis2-VHDL20_DWMO_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4739
swis2-VHDL20_DWMO_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                4827
swis2-VHDL20_DWMP_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                5442
swis2-VHDL20_DWMP_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                5553
swis2-VHDL20_DWMP_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                5542
swis2-VHDL20_DWMP_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                5590
swis2-VHDL20_DWMP_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:45                5501
swis2-VHDL20_DWMP_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                5394
swis2-VHDL20_DWMP_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                6294
swis2-VHDL20_DWMP_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                6276
swis2-VHDL20_DWMP_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                6208
swis2-VHDL20_DWMP_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:45                6113
swis2-VHDL20_DWPG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                3840
swis2-VHDL20_DWPG_211930-1810211930-dsw--0-ia5     21-Oct-2018 19:30                3840
swis2-VHDL20_DWPG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                4212
swis2-VHDL20_DWPG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                4041
swis2-VHDL20_DWPG_220530-1810220530-dsw--0-ia5     22-Oct-2018 05:30                4014
swis2-VHDL20_DWPG_220630-1810220630-dsw--0-ia5     22-Oct-2018 06:30                4000
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swis2-VHDL20_DWPG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                3735
swis2-VHDL20_DWPG_220930-1810220930-dsw--0-ia5     22-Oct-2018 09:31                3798
swis2-VHDL20_DWPG_221030-1810221030-dsw--0-ia5     22-Oct-2018 10:30                3798
swis2-VHDL20_DWPG_221130-1810221130-dsw--0-ia5     22-Oct-2018 11:30                3791
swis2-VHDL20_DWPG_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                3819
swis2-VHDL20_DWPG_221330-1810221330-dsw--0-ia5     22-Oct-2018 13:30                3819
swis2-VHDL20_DWPG_221450-1810221450-dsw--0-ia5     22-Oct-2018 14:30                3819
swis2-VHDL20_DWPG_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                3909
swis2-VHDL20_DWPG_221630-1810221630-dsw--0-ia5     22-Oct-2018 16:30                3909
swis2-VHDL20_DWPG_221750-1810221750-dsw--0-ia5     22-Oct-2018 17:30                3909
swis2-VHDL20_DWPG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                3858
swis2-VHDL20_DWPG_221930-1810221930-dsw--0-ia5     22-Oct-2018 19:30                3858
swis2-VHDL20_DWPG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                3737
swis2-VHDL20_DWPG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                3453
swis2-VHDL20_DWPG_230530-1810230530-dsw--0-ia5     23-Oct-2018 05:30                3453
swis2-VHDL20_DWPG_230630-1810230630-dsw--0-ia5     23-Oct-2018 06:30                3355
swis2-VHDL20_DWPG_230750-1810230750-dsw--0-ia5     23-Oct-2018 07:30                3355
swis2-VHDL20_DWPG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                3398
swis2-VHDL20_DWPG_230930-1810230930-dsw--0-ia5     23-Oct-2018 09:31                3461
swis2-VHDL20_DWPG_231030-1810231030-dsw--0-ia5     23-Oct-2018 10:30                3461
swis2-VHDL20_DWPG_231130-1810231130-dsw--0-ia5     23-Oct-2018 11:30                3407
swis2-VHDL20_DWPG_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                3520
swis2-VHDL20_DWPG_231330-1810231330-dsw--0-ia5     23-Oct-2018 13:30                3520
swis2-VHDL20_DWPG_231450-1810231450-dsw--0-ia5     23-Oct-2018 14:30                3520
swis2-VHDL20_DWPG_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                3666
swis2-VHDL20_DWPG_231630-1810231630-dsw--0-ia5     23-Oct-2018 16:30                3666
swis2-VHDL20_DWPG_231750-1810231750-dsw--0-ia5     23-Oct-2018 17:30                3666
swis2-VHDL20_DWPH_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:30                3993
swis2-VHDL20_DWPH_211930-1810211930-dsw--0-ia5     21-Oct-2018 19:30                3993
swis2-VHDL20_DWPH_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:30                4582
swis2-VHDL20_DWPH_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:30                4810
swis2-VHDL20_DWPH_220530-1810220530-dsw--0-ia5     22-Oct-2018 05:30                4725
swis2-VHDL20_DWPH_220630-1810220630-dsw--0-ia5     22-Oct-2018 06:30                4690
swis2-VHDL20_DWPH_220750-1810220750-dsw--0-ia5     22-Oct-2018 07:30                4690
swis2-VHDL20_DWPH_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:30                4419
swis2-VHDL20_DWPH_220930-1810220930-dsw--0-ia5     22-Oct-2018 09:31                4482
swis2-VHDL20_DWPH_221030-1810221030-dsw--0-ia5     22-Oct-2018 10:30                4482
swis2-VHDL20_DWPH_221130-1810221130-dsw--0-ia5     22-Oct-2018 11:30                4413
swis2-VHDL20_DWPH_221300-1810221300-dsw--0-ia5     22-Oct-2018 12:30                4593
swis2-VHDL20_DWPH_221330-1810221330-dsw--0-ia5     22-Oct-2018 13:30                4593
swis2-VHDL20_DWPH_221450-1810221450-dsw--0-ia5     22-Oct-2018 14:30                4593
swis2-VHDL20_DWPH_221500-1810221500-dsw--0-ia5     22-Oct-2018 15:30                4561
swis2-VHDL20_DWPH_221630-1810221630-dsw--0-ia5     22-Oct-2018 16:30                4561
swis2-VHDL20_DWPH_221750-1810221750-dsw--0-ia5     22-Oct-2018 17:30                4561
swis2-VHDL20_DWPH_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:30                4400
swis2-VHDL20_DWPH_221930-1810221930-dsw--0-ia5     22-Oct-2018 19:30                4400
swis2-VHDL20_DWPH_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:30                4030
swis2-VHDL20_DWPH_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:30                3735
swis2-VHDL20_DWPH_230530-1810230530-dsw--0-ia5     23-Oct-2018 05:30                3735
swis2-VHDL20_DWPH_230630-1810230630-dsw--0-ia5     23-Oct-2018 06:30                3846
swis2-VHDL20_DWPH_230750-1810230750-dsw--0-ia5     23-Oct-2018 07:30                3846
swis2-VHDL20_DWPH_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:30                3887
swis2-VHDL20_DWPH_230930-1810230930-dsw--0-ia5     23-Oct-2018 09:30                3950
swis2-VHDL20_DWPH_231030-1810231030-dsw--0-ia5     23-Oct-2018 10:30                3950
swis2-VHDL20_DWPH_231130-1810231130-dsw--0-ia5     23-Oct-2018 11:30                3968
swis2-VHDL20_DWPH_231300-1810231300-dsw--0-ia5     23-Oct-2018 12:30                4111
swis2-VHDL20_DWPH_231330-1810231330-dsw--0-ia5     23-Oct-2018 13:30                4111
swis2-VHDL20_DWPH_231450-1810231450-dsw--0-ia5     23-Oct-2018 14:30                4111
swis2-VHDL20_DWPH_231500-1810231500-dsw--0-ia5     23-Oct-2018 15:30                4195
swis2-VHDL20_DWPH_231630-1810231630-dsw--0-ia5     23-Oct-2018 16:30                4195
swis2-VHDL20_DWPH_231750-1810231750-dsw--0-ia5     23-Oct-2018 17:30                4195
swis2-VHDL20_DWSG_211800-1810211800-dsw--0-ia5     21-Oct-2018 18:45                4062
swis2-VHDL20_DWSG_220200-1810220200-dsw--0-ia5     22-Oct-2018 02:45                4341
swis2-VHDL20_DWSG_220400-1810220400-dsw--0-ia5     22-Oct-2018 04:45                3970
swis2-VHDL20_DWSG_220800-1810220800-dsw--0-ia5     22-Oct-2018 08:45                4105
swis2-VHDL20_DWSG_221300-1810221300-dsw--0-ia5     22-Oct-2018 13:45                4152
swis2-VHDL20_DWSG_221800-1810221800-dsw--0-ia5     22-Oct-2018 18:45                4008
swis2-VHDL20_DWSG_230200-1810230200-dsw--0-ia5     23-Oct-2018 02:45                4321
swis2-VHDL20_DWSG_230400-1810230400-dsw--0-ia5     23-Oct-2018 04:45                4383
swis2-VHDL20_DWSG_230800-1810230800-dsw--0-ia5     23-Oct-2018 08:45                4393
swis2-VHDL20_DWSG_231300-1810231300-dsw--0-ia5     23-Oct-2018 13:45                4380