Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_030600 03-Jul-2020 08:57 5292
FPDL13_DWMZ_040600 04-Jul-2020 07:59 3424
SXDL31_DWAV_030800 03-Jul-2020 06:41 7951
SXDL31_DWAV_031800 03-Jul-2020 15:27 12954
SXDL31_DWAV_040800 04-Jul-2020 06:45 9308
SXDL31_DWAV_041800 04-Jul-2020 16:48 13013
SXDL33_DWAV_030000 03-Jul-2020 09:41 10275
SXDL33_DWAV_040000 04-Jul-2020 09:47 9208
ber01-FWDL39_DWMS_031230-2007031230-dsw--0-ia5 03-Jul-2020 12:15 825
ber01-FWDL39_DWMS_041230-2007041230-dsw--0-ia5 04-Jul-2020 12:27 727
ber01-VHDL13_DWEH_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:28 2510
ber01-VHDL13_DWEH_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:58 2486
ber01-VHDL13_DWEH_030400_COR-2007030400-dsw--0-ia5 03-Jul-2020 05:16 2490
ber01-VHDL13_DWEH_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:28 2772
ber01-VHDL13_DWEH_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:28 2831
ber01-VHDL13_DWEH_031500-2007031500-dsw--0-ia5 03-Jul-2020 15:28 2784
ber01-VHDL13_DWEH_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:28 2569
ber01-VHDL13_DWEH_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:28 2620
ber01-VHDL13_DWEH_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:58 2757
ber01-VHDL13_DWEH_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:28 2799
ber01-VHDL13_DWEH_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:28 2893
ber01-VHDL13_DWEH_041500-2007041500-dsw--0-ia5 04-Jul-2020 15:28 3059
ber01-VHDL13_DWEH_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:28 2638
ber01-VHDL13_DWHG_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 2653
ber01-VHDL13_DWHG_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 2677
ber01-VHDL13_DWHG_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 2812
ber01-VHDL13_DWHG_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:30 2790
ber01-VHDL13_DWHG_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 2718
ber01-VHDL13_DWHG_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 2831
ber01-VHDL13_DWHG_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 2788
ber01-VHDL13_DWHG_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2890
ber01-VHDL13_DWHG_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:30 2865
ber01-VHDL13_DWHG_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 2782
ber01-VHDL13_DWHH_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 2454
ber01-VHDL13_DWHH_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 2484
ber01-VHDL13_DWHH_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 2575
ber01-VHDL13_DWHH_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:30 2569
ber01-VHDL13_DWHH_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 2451
ber01-VHDL13_DWHH_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 2744
ber01-VHDL13_DWHH_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 2730
ber01-VHDL13_DWHH_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2766
ber01-VHDL13_DWHH_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:30 2681
ber01-VHDL13_DWHH_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 2664
ber01-VHDL13_DWLG_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 1926
ber01-VHDL13_DWLG_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 1832
ber01-VHDL13_DWLG_030533-2007030533-dsw--0-ia5 03-Jul-2020 05:33 1860
ber01-VHDL13_DWLG_030633-2007030633-dsw--0-ia5 03-Jul-2020 06:33 1866
ber01-VHDL13_DWLG_030733-2007030733-dsw--0-ia5 03-Jul-2020 07:33 1959
ber01-VHDL13_DWLG_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 1928
ber01-VHDL13_DWLG_030933-2007030933-dsw--0-ia5 03-Jul-2020 09:33 1959
ber01-VHDL13_DWLG_031033-2007031033-dsw--0-ia5 03-Jul-2020 10:33 1959
ber01-VHDL13_DWLG_031133-2007031133-dsw--0-ia5 03-Jul-2020 11:33 1921
ber01-VHDL13_DWLG_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:30 1892
ber01-VHDL13_DWLG_031333-2007031333-dsw--0-ia5 03-Jul-2020 13:33 1922
ber01-VHDL13_DWLG_031433-2007031433-dsw--0-ia5 03-Jul-2020 14:33 1922
ber01-VHDL13_DWLG_031533-2007031533-dsw--0-ia5 03-Jul-2020 15:33 1922
ber01-VHDL13_DWLG_031633-2007031633-dsw--0-ia5 03-Jul-2020 16:33 1922
ber01-VHDL13_DWLG_031733-2007031733-dsw--0-ia5 03-Jul-2020 17:33 1763
ber01-VHDL13_DWLG_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 1735
ber01-VHDL13_DWLG_031933-2007031933-dsw--0-ia5 03-Jul-2020 19:33 1763
ber01-VHDL13_DWLG_032033-2007032033-dsw--0-ia5 03-Jul-2020 20:33 1763
ber01-VHDL13_DWLG_040033-2007040033-dsw--0-ia5 04-Jul-2020 00:33 1955
ber01-VHDL13_DWLG_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 1927
ber01-VHDL13_DWLG_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 2007
ber01-VHDL13_DWLG_040533-2007040533-dsw--0-ia5 04-Jul-2020 05:33 2035
ber01-VHDL13_DWLG_040633-2007040633-dsw--0-ia5 04-Jul-2020 06:33 2035
ber01-VHDL13_DWLG_040733-2007040733-dsw--0-ia5 04-Jul-2020 07:33 2138
ber01-VHDL13_DWLG_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2107
ber01-VHDL13_DWLG_040933-2007040933-dsw--0-ia5 04-Jul-2020 09:33 2138
ber01-VHDL13_DWLG_041033-2007041033-dsw--0-ia5 04-Jul-2020 10:33 2167
ber01-VHDL13_DWLG_041133-2007041133-dsw--0-ia5 04-Jul-2020 11:33 2167
ber01-VHDL13_DWLG_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:30 2145
ber01-VHDL13_DWLG_041333-2007041333-dsw--0-ia5 04-Jul-2020 13:33 2111
ber01-VHDL13_DWLG_041433-2007041433-dsw--0-ia5 04-Jul-2020 14:33 2111
ber01-VHDL13_DWLG_041533-2007041533-dsw--0-ia5 04-Jul-2020 15:33 2111
ber01-VHDL13_DWLG_041633-2007041633-dsw--0-ia5 04-Jul-2020 16:33 2136
ber01-VHDL13_DWLG_041733-2007041733-dsw--0-ia5 04-Jul-2020 17:33 2136
ber01-VHDL13_DWLG_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 1865
ber01-VHDL13_DWLG_041933-2007041933-dsw--0-ia5 04-Jul-2020 19:33 1893
ber01-VHDL13_DWLG_042033-2007042033-dsw--0-ia5 04-Jul-2020 20:33 1893
ber01-VHDL13_DWLG_050033-2007050033-dsw--0-ia5 05-Jul-2020 00:33 2125
ber01-VHDL13_DWLH_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 2133
ber01-VHDL13_DWLH_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 2119
ber01-VHDL13_DWLH_030533-2007030533-dsw--0-ia5 03-Jul-2020 05:33 2147
ber01-VHDL13_DWLH_030633-2007030633-dsw--0-ia5 03-Jul-2020 06:33 2079
ber01-VHDL13_DWLH_030733-2007030733-dsw--0-ia5 03-Jul-2020 07:33 2193
ber01-VHDL13_DWLH_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 2165
ber01-VHDL13_DWLH_030933-2007030933-dsw--0-ia5 03-Jul-2020 09:33 2193
ber01-VHDL13_DWLH_031033-2007031033-dsw--0-ia5 03-Jul-2020 10:33 2193
ber01-VHDL13_DWLH_031133-2007031133-dsw--0-ia5 03-Jul-2020 11:33 2173
ber01-VHDL13_DWLH_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:30 2150
ber01-VHDL13_DWLH_031333-2007031333-dsw--0-ia5 03-Jul-2020 13:33 2177
ber01-VHDL13_DWLH_031433-2007031433-dsw--0-ia5 03-Jul-2020 14:33 2177
ber01-VHDL13_DWLH_031533-2007031533-dsw--0-ia5 03-Jul-2020 15:33 2177
ber01-VHDL13_DWLH_031633-2007031633-dsw--0-ia5 03-Jul-2020 16:33 2177
ber01-VHDL13_DWLH_031733-2007031733-dsw--0-ia5 03-Jul-2020 17:33 2162
ber01-VHDL13_DWLH_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 2134
ber01-VHDL13_DWLH_031933-2007031933-dsw--0-ia5 03-Jul-2020 19:33 2162
ber01-VHDL13_DWLH_032033-2007032033-dsw--0-ia5 03-Jul-2020 20:33 2162
ber01-VHDL13_DWLH_040033-2007040033-dsw--0-ia5 04-Jul-2020 00:33 2517
ber01-VHDL13_DWLH_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 2489
ber01-VHDL13_DWLH_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 2436
ber01-VHDL13_DWLH_040533-2007040533-dsw--0-ia5 04-Jul-2020 05:33 2478
ber01-VHDL13_DWLH_040633-2007040633-dsw--0-ia5 04-Jul-2020 06:33 2469
ber01-VHDL13_DWLH_040733-2007040733-dsw--0-ia5 04-Jul-2020 07:33 2422
ber01-VHDL13_DWLH_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2394
ber01-VHDL13_DWLH_040933-2007040933-dsw--0-ia5 04-Jul-2020 09:33 2422
ber01-VHDL13_DWLH_041033-2007041033-dsw--0-ia5 04-Jul-2020 10:33 2403
ber01-VHDL13_DWLH_041133-2007041133-dsw--0-ia5 04-Jul-2020 11:33 2411
ber01-VHDL13_DWLH_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:30 2390
ber01-VHDL13_DWLH_041333-2007041333-dsw--0-ia5 04-Jul-2020 13:33 2346
ber01-VHDL13_DWLH_041433-2007041433-dsw--0-ia5 04-Jul-2020 14:33 2346
ber01-VHDL13_DWLH_041533-2007041533-dsw--0-ia5 04-Jul-2020 15:33 2346
ber01-VHDL13_DWLH_041633-2007041633-dsw--0-ia5 04-Jul-2020 16:33 2357
ber01-VHDL13_DWLH_041733-2007041733-dsw--0-ia5 04-Jul-2020 17:33 2357
ber01-VHDL13_DWLH_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 2144
ber01-VHDL13_DWLH_041933-2007041933-dsw--0-ia5 04-Jul-2020 19:33 2172
ber01-VHDL13_DWLH_042033-2007042033-dsw--0-ia5 04-Jul-2020 20:33 2172
ber01-VHDL13_DWLH_050033-2007050033-dsw--0-ia5 05-Jul-2020 00:33 2274
ber01-VHDL13_DWLI_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 1927
ber01-VHDL13_DWLI_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 1857
ber01-VHDL13_DWLI_030533-2007030533-dsw--0-ia5 03-Jul-2020 05:33 1885
ber01-VHDL13_DWLI_030633-2007030633-dsw--0-ia5 03-Jul-2020 06:33 1915
ber01-VHDL13_DWLI_030733-2007030733-dsw--0-ia5 03-Jul-2020 07:33 1958
ber01-VHDL13_DWLI_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 1930
ber01-VHDL13_DWLI_030933-2007030933-dsw--0-ia5 03-Jul-2020 09:33 1958
ber01-VHDL13_DWLI_031033-2007031033-dsw--0-ia5 03-Jul-2020 10:33 1958
ber01-VHDL13_DWLI_031133-2007031133-dsw--0-ia5 03-Jul-2020 11:33 1931
ber01-VHDL13_DWLI_031300-2007031300-dsw--0-ia5 03-Jul-2020 12:30 1918
ber01-VHDL13_DWLI_031333-2007031333-dsw--0-ia5 03-Jul-2020 13:33 1951
ber01-VHDL13_DWLI_031433-2007031433-dsw--0-ia5 03-Jul-2020 14:33 1951
ber01-VHDL13_DWLI_031533-2007031533-dsw--0-ia5 03-Jul-2020 15:33 1951
ber01-VHDL13_DWLI_031633-2007031633-dsw--0-ia5 03-Jul-2020 16:33 1951
ber01-VHDL13_DWLI_031733-2007031733-dsw--0-ia5 03-Jul-2020 17:33 1834
ber01-VHDL13_DWLI_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 1806
ber01-VHDL13_DWLI_031933-2007031933-dsw--0-ia5 03-Jul-2020 19:33 1834
ber01-VHDL13_DWLI_032033-2007032033-dsw--0-ia5 03-Jul-2020 20:33 1834
ber01-VHDL13_DWLI_040033-2007040033-dsw--0-ia5 04-Jul-2020 00:33 2184
ber01-VHDL13_DWLI_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 2156
ber01-VHDL13_DWLI_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 2102
ber01-VHDL13_DWLI_040533-2007040533-dsw--0-ia5 04-Jul-2020 05:33 2130
ber01-VHDL13_DWLI_040633-2007040633-dsw--0-ia5 04-Jul-2020 06:33 2130
ber01-VHDL13_DWLI_040733-2007040733-dsw--0-ia5 04-Jul-2020 07:33 2279
ber01-VHDL13_DWLI_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2251
ber01-VHDL13_DWLI_040933-2007040933-dsw--0-ia5 04-Jul-2020 09:33 2279
ber01-VHDL13_DWLI_041033-2007041033-dsw--0-ia5 04-Jul-2020 10:33 2269
ber01-VHDL13_DWLI_041133-2007041133-dsw--0-ia5 04-Jul-2020 11:33 2269
ber01-VHDL13_DWLI_041300-2007041300-dsw--0-ia5 04-Jul-2020 12:30 2248
ber01-VHDL13_DWLI_041333-2007041333-dsw--0-ia5 04-Jul-2020 13:33 2148
ber01-VHDL13_DWLI_041433-2007041433-dsw--0-ia5 04-Jul-2020 14:33 2148
ber01-VHDL13_DWLI_041533-2007041533-dsw--0-ia5 04-Jul-2020 15:33 2148
ber01-VHDL13_DWLI_041633-2007041633-dsw--0-ia5 04-Jul-2020 16:33 2159
ber01-VHDL13_DWLI_041733-2007041733-dsw--0-ia5 04-Jul-2020 17:33 2159
ber01-VHDL13_DWLI_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 1891
ber01-VHDL13_DWLI_041933-2007041933-dsw--0-ia5 04-Jul-2020 19:33 1919
ber01-VHDL13_DWLI_042033-2007042033-dsw--0-ia5 04-Jul-2020 20:33 1919
ber01-VHDL13_DWLI_050033-2007050033-dsw--0-ia5 05-Jul-2020 00:33 2099
ber01-VHDL13_DWMG_030100-2007030100-dsw--0-ia5 03-Jul-2020 01:30 2930
ber01-VHDL13_DWMG_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 2390
ber01-VHDL13_DWMG_030300-2007030300-dsw--0-ia5 03-Jul-2020 03:30 2344
ber01-VHDL13_DWMG_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 2392
ber01-VHDL13_DWMG_030500-2007030500-dsw--0-ia5 03-Jul-2020 05:30 2392
ber01-VHDL13_DWMG_030600-2007030600-dsw--0-ia5 03-Jul-2020 06:30 2340
ber01-VHDL13_DWMG_030700-2007030700-dsw--0-ia5 03-Jul-2020 07:30 2340
ber01-VHDL13_DWMG_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 2335
ber01-VHDL13_DWMG_030900-2007030900-dsw--0-ia5 03-Jul-2020 09:30 2335
ber01-VHDL13_DWMG_031000-2007031000-dsw--0-ia5 03-Jul-2020 10:30 2302
ber01-VHDL13_DWMG_031100-2007031100-dsw--0-ia5 03-Jul-2020 11:30 2302
ber01-VHDL13_DWMG_031200-2007031200-dsw--0-ia5 03-Jul-2020 12:30 2333
ber01-VHDL13_DWMG_031300-2007031300-dsw--0-ia5 03-Jul-2020 13:30 2308
ber01-VHDL13_DWMG_031400-2007031400-dsw--0-ia5 03-Jul-2020 14:30 2308
ber01-VHDL13_DWMG_031500-2007031500-dsw--0-ia5 03-Jul-2020 15:30 2118
ber01-VHDL13_DWMG_031600-2007031600-dsw--0-ia5 03-Jul-2020 16:30 2118
ber01-VHDL13_DWMG_031700-2007031700-dsw--0-ia5 03-Jul-2020 17:30 1897
ber01-VHDL13_DWMG_031800-2007031800-dsw--0-ia5 03-Jul-2020 18:30 1875
ber01-VHDL13_DWMG_031900-2007031900-dsw--0-ia5 03-Jul-2020 19:30 1875
ber01-VHDL13_DWMG_032000-2007032000-dsw--0-ia5 03-Jul-2020 20:30 1875
ber01-VHDL13_DWMG_032100-2007032100-dsw--0-ia5 03-Jul-2020 21:30 1875
ber01-VHDL13_DWMG_032200-2007032200-dsw--0-ia5 03-Jul-2020 22:30 1881
ber01-VHDL13_DWMG_032300-2007032300-dsw--0-ia5 03-Jul-2020 23:30 1881
ber01-VHDL13_DWMG_040000-2007040000-dsw--0-ia5 04-Jul-2020 00:30 1881
ber01-VHDL13_DWMG_040100-2007040100-dsw--0-ia5 04-Jul-2020 01:30 1881
ber01-VHDL13_DWMG_040200-2007040200-dsw--0-ia5 04-Jul-2020 02:30 1881
ber01-VHDL13_DWMG_040300-2007040300-dsw--0-ia5 04-Jul-2020 03:30 1885
ber01-VHDL13_DWMG_040400-2007040400-dsw--0-ia5 04-Jul-2020 04:30 1956
ber01-VHDL13_DWMG_040500-2007040500-dsw--0-ia5 04-Jul-2020 05:30 2053
ber01-VHDL13_DWMG_040600-2007040600-dsw--0-ia5 04-Jul-2020 06:30 2060
ber01-VHDL13_DWMG_040700-2007040700-dsw--0-ia5 04-Jul-2020 07:30 2060
ber01-VHDL13_DWMG_040800-2007040800-dsw--0-ia5 04-Jul-2020 08:30 2281
ber01-VHDL13_DWMG_040900-2007040900-dsw--0-ia5 04-Jul-2020 09:30 2281
ber01-VHDL13_DWMG_041000-2007041000-dsw--0-ia5 04-Jul-2020 10:30 2341
ber01-VHDL13_DWMG_041100-2007041100-dsw--0-ia5 04-Jul-2020 11:30 2341
ber01-VHDL13_DWMG_041200-2007041200-dsw--0-ia5 04-Jul-2020 12:30 2341
ber01-VHDL13_DWMG_041300-2007041300-dsw--0-ia5 04-Jul-2020 13:30 2295
ber01-VHDL13_DWMG_041400-2007041400-dsw--0-ia5 04-Jul-2020 14:30 2288
ber01-VHDL13_DWMG_041500-2007041500-dsw--0-ia5 04-Jul-2020 15:30 2288
ber01-VHDL13_DWMG_041600-2007041600-dsw--0-ia5 04-Jul-2020 16:30 2288
ber01-VHDL13_DWMG_041700-2007041700-dsw--0-ia5 04-Jul-2020 17:30 1974
ber01-VHDL13_DWMG_041800-2007041800-dsw--0-ia5 04-Jul-2020 18:30 2022
ber01-VHDL13_DWMG_041900-2007041900-dsw--0-ia5 04-Jul-2020 19:30 1977
ber01-VHDL13_DWMG_042000-2007042000-dsw--0-ia5 04-Jul-2020 20:30 1977
ber01-VHDL13_DWMG_042100-2007042100-dsw--0-ia5 04-Jul-2020 21:30 1977
ber01-VHDL13_DWMG_042200-2007042200-dsw--0-ia5 04-Jul-2020 22:30 2034
ber01-VHDL13_DWMG_042300-2007042300-dsw--0-ia5 04-Jul-2020 23:30 2034
ber01-VHDL13_DWMG_050000-2007050000-dsw--0-ia5 05-Jul-2020 00:30 2034
ber01-VHDL13_DWMO_030100-2007030100-dsw--0-ia5 03-Jul-2020 01:30 2166
ber01-VHDL13_DWMO_030200-2007030200-dsw--0-ia5 03-Jul-2020 02:30 2166
ber01-VHDL13_DWMO_030300-2007030300-dsw--0-ia5 03-Jul-2020 03:30 2319
ber01-VHDL13_DWMO_030400-2007030400-dsw--0-ia5 03-Jul-2020 04:30 2177
ber01-VHDL13_DWMO_030500-2007030500-dsw--0-ia5 03-Jul-2020 05:30 2177
ber01-VHDL13_DWMO_030600-2007030600-dsw--0-ia5 03-Jul-2020 06:30 2092
ber01-VHDL13_DWMO_030700-2007030700-dsw--0-ia5 03-Jul-2020 07:30 2092
ber01-VHDL13_DWMO_030800-2007030800-dsw--0-ia5 03-Jul-2020 08:30 2109
ber01-VHDL13_DWMO_030900-2007030900-dsw--0-ia5 03-Jul-2020 09:30 2081
ber01-VHDL13_DWMO_031000-2007031000-dsw--0-ia5 03-Jul-2020 10:30 2058
ber01-VHDL13_DWMO_031100-2007031100-dsw--0-ia5 03-Jul-2020 11:30 2058
ber01-VHDL13_DWMO_031200-2007031200-dsw--0-ia5 03-Jul-2020 12:30 2058
ber01-VHDL13_DWMO_031300-2007031300-dsw--0-ia5 03-Jul-2020 13:30 2071
ber01-VHDL13_DWMO_031400-2007031400-dsw--0-ia5 03-Jul-2020 14:30 2071
ber01-VHDL13_DWMO_031500-2007031500-dsw--0-ia5 03-Jul-2020 15:30 1857
ber01-VHDL13_DWMO_031600-2007031600-dsw--0-ia5 03-Jul-2020 16:30 1857
ber01-VHDL13_DWMO_031700-2007031700-dsw--0-ia5 03-Jul-2020 17:30 1857
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