Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_170600                                 17-Oct-2019 08:13                3042
FPDL13_DWMZ_180600                                 18-Oct-2019 10:26                5514
SXDL31_DWAV_170800                                 17-Oct-2019 07:35               12840
SXDL31_DWAV_171800                                 17-Oct-2019 17:31                8230
SXDL31_DWAV_180800                                 18-Oct-2019 07:23                8297
SXDL31_DWAV_181800                                 18-Oct-2019 17:05               13519
SXDL33_DWAV_170000                                 17-Oct-2019 11:06                6652
SXDL33_DWAV_180000                                 18-Oct-2019 10:22               10272
ber01-FWDL39_DWMS_171230-1910171230-dsw--0-ia5     17-Oct-2019 12:34                 812
ber01-FWDL39_DWMS_181230-1910181230-dsw--0-ia5     18-Oct-2019 12:28                 857
ber01-VHDL13_DWEH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:58                2687
ber01-VHDL13_DWEH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:28                3098
ber01-VHDL13_DWEH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:28                3053
ber01-VHDL13_DWEH_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:28                3019
ber01-VHDL13_DWEH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:28                2826
ber01-VHDL13_DWEH_171800_COR-1910171800-dsw--0-ia5 17-Oct-2019 19:37                2827
ber01-VHDL13_DWEH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:28                2677
ber01-VHDL13_DWEH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:58                2856
ber01-VHDL13_DWEH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:28                2778
ber01-VHDL13_DWEH_180800_COR-1910180800-dsw--0-ia5 18-Oct-2019 10:12                2802
ber01-VHDL13_DWEH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:28                2914
ber01-VHDL13_DWEH_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:28                2914
ber01-VHDL13_DWEH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:28                2561
ber01-VHDL13_DWEH_181800_COR-1910181800-dsw--0-ia5 18-Oct-2019 19:14                1992
ber01-VHDL13_DWEH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:28                2152
ber01-VHDL13_DWHG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                1845
ber01-VHDL13_DWHG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2388
ber01-VHDL13_DWHG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2440
ber01-VHDL13_DWHG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2211
ber01-VHDL13_DWHG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2505
ber01-VHDL13_DWHG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2501
ber01-VHDL13_DWHG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2429
ber01-VHDL13_DWHG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2364
ber01-VHDL13_DWHG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                1632
ber01-VHDL13_DWHG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                1694
ber01-VHDL13_DWHH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                1986
ber01-VHDL13_DWHH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2460
ber01-VHDL13_DWHH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2502
ber01-VHDL13_DWHH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2222
ber01-VHDL13_DWHH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2640
ber01-VHDL13_DWHH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2633
ber01-VHDL13_DWHH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2654
ber01-VHDL13_DWHH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2594
ber01-VHDL13_DWHH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                1834
ber01-VHDL13_DWHH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                1832
ber01-VHDL13_DWLG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                1937
ber01-VHDL13_DWLG_170533-1910170533-dsw--0-ia5     17-Oct-2019 05:33                1965
ber01-VHDL13_DWLG_170633-1910170633-dsw--0-ia5     17-Oct-2019 06:33                1982
ber01-VHDL13_DWLG_170733-1910170733-dsw--0-ia5     17-Oct-2019 07:33                1982
ber01-VHDL13_DWLG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2047
ber01-VHDL13_DWLG_170933-1910170933-dsw--0-ia5     17-Oct-2019 09:33                2078
ber01-VHDL13_DWLG_171033-1910171033-dsw--0-ia5     17-Oct-2019 10:33                2125
ber01-VHDL13_DWLG_171133-1910171133-dsw--0-ia5     17-Oct-2019 11:33                2125
ber01-VHDL13_DWLG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2057
ber01-VHDL13_DWLG_171333-1910171333-dsw--0-ia5     17-Oct-2019 13:33                2085
ber01-VHDL13_DWLG_171433-1910171433-dsw--0-ia5     17-Oct-2019 14:33                1985
ber01-VHDL13_DWLG_171533-1910171533-dsw--0-ia5     17-Oct-2019 15:33                1985
ber01-VHDL13_DWLG_171633-1910171633-dsw--0-ia5     17-Oct-2019 16:33                1985
ber01-VHDL13_DWLG_171733-1910171733-dsw--0-ia5     17-Oct-2019 17:33                1840
ber01-VHDL13_DWLG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                1812
ber01-VHDL13_DWLG_171933-1910171933-dsw--0-ia5     17-Oct-2019 19:33                1840
ber01-VHDL13_DWLG_172033-1910172033-dsw--0-ia5     17-Oct-2019 20:33                1840
ber01-VHDL13_DWLG_180033-1910180033-dsw--0-ia5     18-Oct-2019 00:33                2013
ber01-VHDL13_DWLG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2365
ber01-VHDL13_DWLG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2364
ber01-VHDL13_DWLG_180533-1910180533-dsw--0-ia5     18-Oct-2019 05:33                2392
ber01-VHDL13_DWLG_180633-1910180633-dsw--0-ia5     18-Oct-2019 06:33                2510
ber01-VHDL13_DWLG_180733-1910180733-dsw--0-ia5     18-Oct-2019 07:33                2500
ber01-VHDL13_DWLG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2469
ber01-VHDL13_DWLG_180933-1910180933-dsw--0-ia5     18-Oct-2019 09:33                2500
ber01-VHDL13_DWLG_181033-1910181033-dsw--0-ia5     18-Oct-2019 10:33                2495
ber01-VHDL13_DWLG_181133-1910181133-dsw--0-ia5     18-Oct-2019 11:33                2495
ber01-VHDL13_DWLG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2273
ber01-VHDL13_DWLG_181333-1910181333-dsw--0-ia5     18-Oct-2019 13:33                2301
ber01-VHDL13_DWLG_181433-1910181433-dsw--0-ia5     18-Oct-2019 14:33                2344
ber01-VHDL13_DWLG_181533-1910181533-dsw--0-ia5     18-Oct-2019 15:33                2344
ber01-VHDL13_DWLG_181633-1910181633-dsw--0-ia5     18-Oct-2019 16:33                2354
ber01-VHDL13_DWLG_181733-1910181733-dsw--0-ia5     18-Oct-2019 17:33                1979
ber01-VHDL13_DWLG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                1945
ber01-VHDL13_DWLG_181933-1910181933-dsw--0-ia5     18-Oct-2019 19:33                1973
ber01-VHDL13_DWLG_182033-1910182033-dsw--0-ia5     18-Oct-2019 20:33                1973
ber01-VHDL13_DWLG_190033-1910190033-dsw--0-ia5     19-Oct-2019 00:33                1955
ber01-VHDL13_DWLG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                1962
ber01-VHDL13_DWLH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2181
ber01-VHDL13_DWLH_170533-1910170533-dsw--0-ia5     17-Oct-2019 05:33                2209
ber01-VHDL13_DWLH_170633-1910170633-dsw--0-ia5     17-Oct-2019 06:33                2333
ber01-VHDL13_DWLH_170733-1910170733-dsw--0-ia5     17-Oct-2019 07:33                2379
ber01-VHDL13_DWLH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2377
ber01-VHDL13_DWLH_170933-1910170933-dsw--0-ia5     17-Oct-2019 09:33                2405
ber01-VHDL13_DWLH_171033-1910171033-dsw--0-ia5     17-Oct-2019 10:33                2371
ber01-VHDL13_DWLH_171133-1910171133-dsw--0-ia5     17-Oct-2019 11:33                2371
ber01-VHDL13_DWLH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2364
ber01-VHDL13_DWLH_171333-1910171333-dsw--0-ia5     17-Oct-2019 13:33                2392
ber01-VHDL13_DWLH_171433-1910171433-dsw--0-ia5     17-Oct-2019 14:33                2319
ber01-VHDL13_DWLH_171533-1910171533-dsw--0-ia5     17-Oct-2019 15:33                2319
ber01-VHDL13_DWLH_171633-1910171633-dsw--0-ia5     17-Oct-2019 16:33                2319
ber01-VHDL13_DWLH_171733-1910171733-dsw--0-ia5     17-Oct-2019 17:33                2156
ber01-VHDL13_DWLH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2128
ber01-VHDL13_DWLH_171933-1910171933-dsw--0-ia5     17-Oct-2019 19:33                2156
ber01-VHDL13_DWLH_172033-1910172033-dsw--0-ia5     17-Oct-2019 20:33                2156
ber01-VHDL13_DWLH_180033-1910180033-dsw--0-ia5     18-Oct-2019 00:33                2366
ber01-VHDL13_DWLH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2847
ber01-VHDL13_DWLH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2797
ber01-VHDL13_DWLH_180533-1910180533-dsw--0-ia5     18-Oct-2019 05:33                2825
ber01-VHDL13_DWLH_180633-1910180633-dsw--0-ia5     18-Oct-2019 06:33                3326
ber01-VHDL13_DWLH_180733-1910180733-dsw--0-ia5     18-Oct-2019 07:33                3255
ber01-VHDL13_DWLH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3227
ber01-VHDL13_DWLH_180933-1910180933-dsw--0-ia5     18-Oct-2019 09:33                3255
ber01-VHDL13_DWLH_181033-1910181033-dsw--0-ia5     18-Oct-2019 10:33                3243
ber01-VHDL13_DWLH_181133-1910181133-dsw--0-ia5     18-Oct-2019 11:33                3243
ber01-VHDL13_DWLH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                3261
ber01-VHDL13_DWLH_181333-1910181333-dsw--0-ia5     18-Oct-2019 13:33                3289
ber01-VHDL13_DWLH_181433-1910181433-dsw--0-ia5     18-Oct-2019 14:33                3059
ber01-VHDL13_DWLH_181533-1910181533-dsw--0-ia5     18-Oct-2019 15:33                3059
ber01-VHDL13_DWLH_181633-1910181633-dsw--0-ia5     18-Oct-2019 16:33                2879
ber01-VHDL13_DWLH_181733-1910181733-dsw--0-ia5     18-Oct-2019 17:33                2167
ber01-VHDL13_DWLH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2131
ber01-VHDL13_DWLH_181933-1910181933-dsw--0-ia5     18-Oct-2019 19:33                2159
ber01-VHDL13_DWLH_182033-1910182033-dsw--0-ia5     18-Oct-2019 20:33                2159
ber01-VHDL13_DWLH_190033-1910190033-dsw--0-ia5     19-Oct-2019 00:33                2353
ber01-VHDL13_DWLH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2292
ber01-VHDL13_DWLI_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                1917
ber01-VHDL13_DWLI_170533-1910170533-dsw--0-ia5     17-Oct-2019 05:33                1945
ber01-VHDL13_DWLI_170633-1910170633-dsw--0-ia5     17-Oct-2019 06:33                2102
ber01-VHDL13_DWLI_170733-1910170733-dsw--0-ia5     17-Oct-2019 07:33                2148
ber01-VHDL13_DWLI_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2321
ber01-VHDL13_DWLI_170933-1910170933-dsw--0-ia5     17-Oct-2019 09:33                2349
ber01-VHDL13_DWLI_171033-1910171033-dsw--0-ia5     17-Oct-2019 10:33                2319
ber01-VHDL13_DWLI_171133-1910171133-dsw--0-ia5     17-Oct-2019 11:33                2319
ber01-VHDL13_DWLI_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2251
ber01-VHDL13_DWLI_171333-1910171333-dsw--0-ia5     17-Oct-2019 13:33                2279
ber01-VHDL13_DWLI_171433-1910171433-dsw--0-ia5     17-Oct-2019 14:33                2208
ber01-VHDL13_DWLI_171533-1910171533-dsw--0-ia5     17-Oct-2019 15:33                2208
ber01-VHDL13_DWLI_171633-1910171633-dsw--0-ia5     17-Oct-2019 16:33                2208
ber01-VHDL13_DWLI_171733-1910171733-dsw--0-ia5     17-Oct-2019 17:33                2064
ber01-VHDL13_DWLI_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2036
ber01-VHDL13_DWLI_171933-1910171933-dsw--0-ia5     17-Oct-2019 19:33                2064
ber01-VHDL13_DWLI_172033-1910172033-dsw--0-ia5     17-Oct-2019 20:33                2064
ber01-VHDL13_DWLI_180033-1910180033-dsw--0-ia5     18-Oct-2019 00:33                2273
ber01-VHDL13_DWLI_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2425
ber01-VHDL13_DWLI_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2371
ber01-VHDL13_DWLI_180533-1910180533-dsw--0-ia5     18-Oct-2019 05:33                2399
ber01-VHDL13_DWLI_180633-1910180633-dsw--0-ia5     18-Oct-2019 06:33                2766
ber01-VHDL13_DWLI_180733-1910180733-dsw--0-ia5     18-Oct-2019 07:33                2695
ber01-VHDL13_DWLI_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2667
ber01-VHDL13_DWLI_180933-1910180933-dsw--0-ia5     18-Oct-2019 09:33                2695
ber01-VHDL13_DWLI_181033-1910181033-dsw--0-ia5     18-Oct-2019 10:33                2744
ber01-VHDL13_DWLI_181133-1910181133-dsw--0-ia5     18-Oct-2019 11:33                2744
ber01-VHDL13_DWLI_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2666
ber01-VHDL13_DWLI_181333-1910181333-dsw--0-ia5     18-Oct-2019 13:33                2694
ber01-VHDL13_DWLI_181433-1910181433-dsw--0-ia5     18-Oct-2019 14:33                2564
ber01-VHDL13_DWLI_181533-1910181533-dsw--0-ia5     18-Oct-2019 15:33                2564
ber01-VHDL13_DWLI_181633-1910181633-dsw--0-ia5     18-Oct-2019 16:33                2561
ber01-VHDL13_DWLI_181733-1910181733-dsw--0-ia5     18-Oct-2019 17:33                1981
ber01-VHDL13_DWLI_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                1950
ber01-VHDL13_DWLI_181933-1910181933-dsw--0-ia5     18-Oct-2019 19:33                1978
ber01-VHDL13_DWLI_182033-1910182033-dsw--0-ia5     18-Oct-2019 20:33                1978
ber01-VHDL13_DWLI_190033-1910190033-dsw--0-ia5     19-Oct-2019 00:33                1986
ber01-VHDL13_DWLI_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                1972
ber01-VHDL13_DWMG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2794
ber01-VHDL13_DWMG_170500-1910170500-dsw--0-ia5     17-Oct-2019 05:30                2644
ber01-VHDL13_DWMG_170600-1910170600-dsw--0-ia5     17-Oct-2019 06:30                2643
ber01-VHDL13_DWMG_170700-1910170700-dsw--0-ia5     17-Oct-2019 07:30                2752
ber01-VHDL13_DWMG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2744
ber01-VHDL13_DWMG_170900-1910170900-dsw--0-ia5     17-Oct-2019 09:30                2570
ber01-VHDL13_DWMG_171000-1910171000-dsw--0-ia5     17-Oct-2019 10:30                2500
ber01-VHDL13_DWMG_171100-1910171100-dsw--0-ia5     17-Oct-2019 11:30                2500
ber01-VHDL13_DWMG_171200-1910171200-dsw--0-ia5     17-Oct-2019 12:30                2500
ber01-VHDL13_DWMG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2500
ber01-VHDL13_DWMG_171400-1910171400-dsw--0-ia5     17-Oct-2019 14:30                2433
ber01-VHDL13_DWMG_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                2433
ber01-VHDL13_DWMG_171600-1910171600-dsw--0-ia5     17-Oct-2019 16:30                2290
ber01-VHDL13_DWMG_171700-1910171700-dsw--0-ia5     17-Oct-2019 17:30                2290
ber01-VHDL13_DWMG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2290
ber01-VHDL13_DWMG_171900-1910171900-dsw--0-ia5     17-Oct-2019 19:30                2374
ber01-VHDL13_DWMG_172000-1910172000-dsw--0-ia5     17-Oct-2019 20:30                2368
ber01-VHDL13_DWMG_172100-1910172100-dsw--0-ia5     17-Oct-2019 21:30                2368
ber01-VHDL13_DWMG_172200-1910172200-dsw--0-ia5     17-Oct-2019 22:30                2637
ber01-VHDL13_DWMG_172300-1910172300-dsw--0-ia5     17-Oct-2019 23:30                2847
ber01-VHDL13_DWMG_180000-1910180000-dsw--0-ia5     18-Oct-2019 00:30                2847
ber01-VHDL13_DWMG_180100-1910180100-dsw--0-ia5     18-Oct-2019 01:30                2847
ber01-VHDL13_DWMG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2847
ber01-VHDL13_DWMG_180300-1910180300-dsw--0-ia5     18-Oct-2019 03:30                2847
ber01-VHDL13_DWMG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2839
ber01-VHDL13_DWMG_180500-1910180500-dsw--0-ia5     18-Oct-2019 05:30                2839
ber01-VHDL13_DWMG_180600-1910180600-dsw--0-ia5     18-Oct-2019 06:30                2839
ber01-VHDL13_DWMG_180700-1910180700-dsw--0-ia5     18-Oct-2019 07:30                2839
ber01-VHDL13_DWMG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3232
ber01-VHDL13_DWMG_180900-1910180900-dsw--0-ia5     18-Oct-2019 09:30                3232
ber01-VHDL13_DWMG_181000-1910181000-dsw--0-ia5     18-Oct-2019 10:30                3232
ber01-VHDL13_DWMG_181100-1910181100-dsw--0-ia5     18-Oct-2019 11:30                3232
ber01-VHDL13_DWMG_181200-1910181200-dsw--0-ia5     18-Oct-2019 12:30                3232
ber01-VHDL13_DWMG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                3232
ber01-VHDL13_DWMG_181400-1910181400-dsw--0-ia5     18-Oct-2019 14:30                3075
ber01-VHDL13_DWMG_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                3078
ber01-VHDL13_DWMG_181600-1910181600-dsw--0-ia5     18-Oct-2019 16:30                2584
ber01-VHDL13_DWMG_181700-1910181700-dsw--0-ia5     18-Oct-2019 17:30                2584
ber01-VHDL13_DWMG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2584
ber01-VHDL13_DWMG_181900-1910181900-dsw--0-ia5     18-Oct-2019 19:30                2614
ber01-VHDL13_DWMG_182000-1910182000-dsw--0-ia5     18-Oct-2019 20:30                2632
ber01-VHDL13_DWMG_182100-1910182100-dsw--0-ia5     18-Oct-2019 21:30                2632
ber01-VHDL13_DWMG_182200-1910182200-dsw--0-ia5     18-Oct-2019 22:30                2741
ber01-VHDL13_DWMG_182300-1910182300-dsw--0-ia5     18-Oct-2019 23:30                2779
ber01-VHDL13_DWMG_190000-1910190000-dsw--0-ia5     19-Oct-2019 00:30                2779
ber01-VHDL13_DWMG_190100-1910190100-dsw--0-ia5     19-Oct-2019 01:30                2779
ber01-VHDL13_DWMG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2779
ber01-VHDL13_DWMG_190300-1910190300-dsw--0-ia5     19-Oct-2019 03:30                2779
ber01-VHDL13_DWMO_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2459
ber01-VHDL13_DWMO_170500-1910170500-dsw--0-ia5     17-Oct-2019 05:30                2395
ber01-VHDL13_DWMO_170600-1910170600-dsw--0-ia5     17-Oct-2019 06:30                2395
ber01-VHDL13_DWMO_170700-1910170700-dsw--0-ia5     17-Oct-2019 07:30                2473
ber01-VHDL13_DWMO_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2601
ber01-VHDL13_DWMO_170900-1910170900-dsw--0-ia5     17-Oct-2019 09:30                2524
ber01-VHDL13_DWMO_171000-1910171000-dsw--0-ia5     17-Oct-2019 10:30                2465
ber01-VHDL13_DWMO_171100-1910171100-dsw--0-ia5     17-Oct-2019 11:30                2465
ber01-VHDL13_DWMO_171200-1910171200-dsw--0-ia5     17-Oct-2019 12:30                2465
ber01-VHDL13_DWMO_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2465
ber01-VHDL13_DWMO_171400-1910171400-dsw--0-ia5     17-Oct-2019 14:30                2393
ber01-VHDL13_DWMO_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                2393
ber01-VHDL13_DWMO_171600-1910171600-dsw--0-ia5     17-Oct-2019 16:30                2136
ber01-VHDL13_DWMO_171700-1910171700-dsw--0-ia5     17-Oct-2019 17:30                2136
ber01-VHDL13_DWMO_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2136
ber01-VHDL13_DWMO_171900-1910171900-dsw--0-ia5     17-Oct-2019 19:30                2136
ber01-VHDL13_DWMO_172000-1910172000-dsw--0-ia5     17-Oct-2019 20:30                2193
ber01-VHDL13_DWMO_172100-1910172100-dsw--0-ia5     17-Oct-2019 21:30                2193
ber01-VHDL13_DWMO_172200-1910172200-dsw--0-ia5     17-Oct-2019 22:30                2459
ber01-VHDL13_DWMO_172300-1910172300-dsw--0-ia5     17-Oct-2019 23:30                2512
ber01-VHDL13_DWMO_180000-1910180000-dsw--0-ia5     18-Oct-2019 00:30                2512
ber01-VHDL13_DWMO_180100-1910180100-dsw--0-ia5     18-Oct-2019 01:30                2512
ber01-VHDL13_DWMO_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2512
ber01-VHDL13_DWMO_180300-1910180300-dsw--0-ia5     18-Oct-2019 03:30                2512
ber01-VHDL13_DWMO_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2500
ber01-VHDL13_DWMO_180500-1910180500-dsw--0-ia5     18-Oct-2019 05:30                2500
ber01-VHDL13_DWMO_180600-1910180600-dsw--0-ia5     18-Oct-2019 06:30                2516
ber01-VHDL13_DWMO_180700-1910180700-dsw--0-ia5     18-Oct-2019 07:30                2516
ber01-VHDL13_DWMO_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2828
ber01-VHDL13_DWMO_180900-1910180900-dsw--0-ia5     18-Oct-2019 09:30                2800
ber01-VHDL13_DWMO_181000-1910181000-dsw--0-ia5     18-Oct-2019 10:30                2800
ber01-VHDL13_DWMO_181100-1910181100-dsw--0-ia5     18-Oct-2019 11:30                2800
ber01-VHDL13_DWMO_181200-1910181200-dsw--0-ia5     18-Oct-2019 12:30                2767
ber01-VHDL13_DWMO_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2767
ber01-VHDL13_DWMO_181400-1910181400-dsw--0-ia5     18-Oct-2019 14:30                2612
ber01-VHDL13_DWMO_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                2595
ber01-VHDL13_DWMO_181600-1910181600-dsw--0-ia5     18-Oct-2019 16:30                2113
ber01-VHDL13_DWMO_181700-1910181700-dsw--0-ia5     18-Oct-2019 17:30                2113
ber01-VHDL13_DWMO_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2113
ber01-VHDL13_DWMO_181900-1910181900-dsw--0-ia5     18-Oct-2019 19:30                2113
ber01-VHDL13_DWMO_182000-1910182000-dsw--0-ia5     18-Oct-2019 20:30                2059
ber01-VHDL13_DWMO_182100-1910182100-dsw--0-ia5     18-Oct-2019 21:30                2059
ber01-VHDL13_DWMO_182200-1910182200-dsw--0-ia5     18-Oct-2019 22:30                2218
ber01-VHDL13_DWMO_182300-1910182300-dsw--0-ia5     18-Oct-2019 23:30                2210
ber01-VHDL13_DWMO_190000-1910190000-dsw--0-ia5     19-Oct-2019 00:30                2210
ber01-VHDL13_DWMO_190100-1910190100-dsw--0-ia5     19-Oct-2019 01:30                2210
ber01-VHDL13_DWMO_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2210
ber01-VHDL13_DWMO_190300-1910190300-dsw--0-ia5     19-Oct-2019 03:30                2210
ber01-VHDL13_DWMP_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2284
ber01-VHDL13_DWMP_170500-1910170500-dsw--0-ia5     17-Oct-2019 05:30                2284
ber01-VHDL13_DWMP_170600-1910170600-dsw--0-ia5     17-Oct-2019 06:30                2118
ber01-VHDL13_DWMP_170700-1910170700-dsw--0-ia5     17-Oct-2019 07:30                2105
ber01-VHDL13_DWMP_170800-1910170800-dsw--0-ia5     17-Oct-2019 12:30                2037
ber01-VHDL13_DWMP_170900-1910170900-dsw--0-ia5     17-Oct-2019 09:30                2004
ber01-VHDL13_DWMP_171000-1910171000-dsw--0-ia5     17-Oct-2019 10:30                2037
ber01-VHDL13_DWMP_171100-1910171100-dsw--0-ia5     17-Oct-2019 11:30                2037
ber01-VHDL13_DWMP_171200-1910171200-dsw--0-ia5     17-Oct-2019 12:30                2037
ber01-VHDL13_DWMP_171400-1910171400-dsw--0-ia5     17-Oct-2019 14:30                2030
ber01-VHDL13_DWMP_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                2030
ber01-VHDL13_DWMP_171600-1910171600-dsw--0-ia5     17-Oct-2019 16:30                1965
ber01-VHDL13_DWMP_171700-1910171700-dsw--0-ia5     17-Oct-2019 17:30                1965
ber01-VHDL13_DWMP_171900-1910171900-dsw--0-ia5     17-Oct-2019 19:30                1965
ber01-VHDL13_DWMP_172000-1910172000-dsw--0-ia5     17-Oct-2019 20:30                1965
ber01-VHDL13_DWMP_172100-1910172100-dsw--0-ia5     17-Oct-2019 21:30                2077
ber01-VHDL13_DWMP_172200-1910172200-dsw--0-ia5     17-Oct-2019 22:30                2259
ber01-VHDL13_DWMP_172300-1910172300-dsw--0-ia5     17-Oct-2019 23:30                2377
ber01-VHDL13_DWMP_180000-1910180000-dsw--0-ia5     18-Oct-2019 00:30                2377
ber01-VHDL13_DWMP_180100-1910180100-dsw--0-ia5     18-Oct-2019 01:30                2377
ber01-VHDL13_DWMP_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2377
ber01-VHDL13_DWMP_180300-1910180300-dsw--0-ia5     18-Oct-2019 03:30                2377
ber01-VHDL13_DWMP_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2377
ber01-VHDL13_DWMP_180500-1910180500-dsw--0-ia5     18-Oct-2019 05:30                2377
ber01-VHDL13_DWMP_180600-1910180600-dsw--0-ia5     18-Oct-2019 06:30                2373
ber01-VHDL13_DWMP_180700-1910180700-dsw--0-ia5     18-Oct-2019 07:30                2373
ber01-VHDL13_DWMP_180800-1910180800-dsw--0-ia5     18-Oct-2019 12:30                2706
ber01-VHDL13_DWMP_180900-1910180900-dsw--0-ia5     18-Oct-2019 09:30                2715
ber01-VHDL13_DWMP_181000-1910181000-dsw--0-ia5     18-Oct-2019 10:30                2715
ber01-VHDL13_DWMP_181100-1910181100-dsw--0-ia5     18-Oct-2019 11:30                2715
ber01-VHDL13_DWMP_181200-1910181200-dsw--0-ia5     18-Oct-2019 12:30                2706
ber01-VHDL13_DWMP_181400-1910181400-dsw--0-ia5     18-Oct-2019 14:30                2669
ber01-VHDL13_DWMP_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                2652
ber01-VHDL13_DWMP_181600-1910181600-dsw--0-ia5     18-Oct-2019 16:30                2560
ber01-VHDL13_DWMP_181700-1910181700-dsw--0-ia5     18-Oct-2019 17:30                2560
ber01-VHDL13_DWMP_181900-1910181900-dsw--0-ia5     18-Oct-2019 19:30                2560
ber01-VHDL13_DWMP_182000-1910182000-dsw--0-ia5     18-Oct-2019 20:30                2508
ber01-VHDL13_DWMP_182100-1910182100-dsw--0-ia5     18-Oct-2019 21:30                2508
ber01-VHDL13_DWMP_182200-1910182200-dsw--0-ia5     18-Oct-2019 22:30                2562
ber01-VHDL13_DWMP_182300-1910182300-dsw--0-ia5     18-Oct-2019 23:30                2765
ber01-VHDL13_DWMP_190000-1910190000-dsw--0-ia5     19-Oct-2019 00:30                2765
ber01-VHDL13_DWMP_190100-1910190100-dsw--0-ia5     19-Oct-2019 01:30                2765
ber01-VHDL13_DWMP_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2765
ber01-VHDL13_DWMP_190300-1910190300-dsw--0-ia5     19-Oct-2019 03:30                2765
ber01-VHDL13_DWOG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:15                3446
ber01-VHDL13_DWOG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:00                3694
ber01-VHDL13_DWOG_171700-1910171700-dsw--0-ia5     17-Oct-2019 17:30                4305
ber01-VHDL13_DWOG_180100-1910180100-dsw--0-ia5     18-Oct-2019 01:45                5380
ber01-VHDL13_DWOG_180300-1910180300-dsw--0-ia5     18-Oct-2019 03:00                5384
ber01-VHDL13_DWOG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:15                5370
ber01-VHDL13_DWOG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:00                5306
ber01-VHDL13_DWOG_181700-1910181700-dsw--0-ia5     18-Oct-2019 17:30                4717
ber01-VHDL13_DWOG_190100-1910190100-dsw--0-ia5     19-Oct-2019 01:45                5422
ber01-VHDL13_DWOG_190300-1910190300-dsw--0-ia5     19-Oct-2019 03:00                5315
ber01-VHDL13_DWOH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:58                2605
ber01-VHDL13_DWOH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:28                2893
ber01-VHDL13_DWOH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:28                2874
ber01-VHDL13_DWOH_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:28                2768
ber01-VHDL13_DWOH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:28                2577
ber01-VHDL13_DWOH_171800_COR-1910171800-dsw--0-ia5 17-Oct-2019 19:37                2578
ber01-VHDL13_DWOH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:28                2563
ber01-VHDL13_DWOH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:58                2785
ber01-VHDL13_DWOH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:28                2799
ber01-VHDL13_DWOH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:28                2962
ber01-VHDL13_DWOH_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:28                2962
ber01-VHDL13_DWOH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:28                2429
ber01-VHDL13_DWOH_181800_COR-1910181800-dsw--0-ia5 18-Oct-2019 19:14                2156
ber01-VHDL13_DWOH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:28                2316
ber01-VHDL13_DWOI_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:58                2645
ber01-VHDL13_DWOI_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:28                3010
ber01-VHDL13_DWOI_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:28                2946
ber01-VHDL13_DWOI_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:28                2980
ber01-VHDL13_DWOI_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:28                2830
ber01-VHDL13_DWOI_171800_COR-1910171800-dsw--0-ia5 17-Oct-2019 19:37                2831
ber01-VHDL13_DWOI_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:28                2712
ber01-VHDL13_DWOI_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:58                2827
ber01-VHDL13_DWOI_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:28                2750
ber01-VHDL13_DWOI_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:28                2933
ber01-VHDL13_DWOI_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:28                2933
ber01-VHDL13_DWOI_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:28                2680
ber01-VHDL13_DWOI_181800_COR-1910181800-dsw--0-ia5 18-Oct-2019 19:14                2548
ber01-VHDL13_DWOI_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:28                2649
ber01-VHDL13_DWON_170517-1910170517-dsw--0-ia5     17-Oct-2019 05:17                3652
ber01-VHDL13_DWON_170750-1910170750-dsw--0-ia5     17-Oct-2019 07:50                3898
ber01-VHDL13_DWON_171012-1910171012-dsw--0-ia5     17-Oct-2019 10:12                3906
ber01-VHDL13_DWON_171330-1910171330-dsw--0-ia5     17-Oct-2019 13:30                3776
ber01-VHDL13_DWON_171458-1910171458-dsw--0-ia5     17-Oct-2019 14:58                3786
ber01-VHDL13_DWON_171732-1910171732-dsw--0-ia5     17-Oct-2019 17:32                3757
ber01-VHDL13_DWON_171828-1910171828-dsw--0-ia5     17-Oct-2019 18:28                3757
ber01-VHDL13_DWON_171830-1910171830-dsw--0-ia5     17-Oct-2019 18:30                3757
ber01-VHDL13_DWON_172044-1910172044-dsw--0-ia5     17-Oct-2019 20:44                4264
ber01-VHDL13_DWON_172308-1910172308-dsw--0-ia5     17-Oct-2019 23:08                4821
ber01-VHDL13_DWON_172312-1910172312-dsw--0-ia5     17-Oct-2019 23:12                4615
ber01-VHDL13_DWON_180046-1910180046-dsw--0-ia5     18-Oct-2019 00:46                4615
ber01-VHDL13_DWON_180207-1910180207-dsw--0-ia5     18-Oct-2019 02:07                4725
ber01-VHDL13_DWON_180350-1910180350-dsw--0-ia5     18-Oct-2019 03:51                4773
ber01-VHDL13_DWON_180420-1910180420-dsw--0-ia5     18-Oct-2019 04:20                4757
ber01-VHDL13_DWON_180429-1910180429-dsw--0-ia5     18-Oct-2019 04:29                4751
ber01-VHDL13_DWON_181159-1910181159-dsw--0-ia5     18-Oct-2019 11:59                4436
ber01-VHDL13_DWON_181714-1910181714-dsw--0-ia5     18-Oct-2019 17:14                4441
ber01-VHDL13_DWON_181729-1910181729-dsw--0-ia5     18-Oct-2019 17:29                3683
ber01-VHDL13_DWON_182008-1910182008-dsw--0-ia5     18-Oct-2019 20:08                3901
ber01-VHDL13_DWON_190032-1910190032-dsw--0-ia5     19-Oct-2019 00:32                3751
ber01-VHDL13_DWON_190033-1910190033-dsw--0-ia5     19-Oct-2019 00:34                3751
ber01-VHDL13_DWON_190111-1910190111-dsw--0-ia5     19-Oct-2019 01:11                3751
ber01-VHDL13_DWON_190242-1910190242-dsw--0-ia5     19-Oct-2019 02:42                3731
ber01-VHDL13_DWPG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2189
ber01-VHDL13_DWPG_170530-1910170530-dsw--0-ia5     17-Oct-2019 05:30                2187
ber01-VHDL13_DWPG_170630-1910170630-dsw--0-ia5     17-Oct-2019 06:30                2187
ber01-VHDL13_DWPG_170730-1910170730-dsw--0-ia5     17-Oct-2019 07:30                2187
ber01-VHDL13_DWPG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2694
ber01-VHDL13_DWPG_170930-1910170930-dsw--0-ia5     17-Oct-2019 09:30                2693
ber01-VHDL13_DWPG_171030-1910171030-dsw--0-ia5     17-Oct-2019 10:30                2693
ber01-VHDL13_DWPG_171130-1910171130-dsw--0-ia5     17-Oct-2019 11:30                2648
ber01-VHDL13_DWPG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2557
ber01-VHDL13_DWPG_171330-1910171330-dsw--0-ia5     17-Oct-2019 13:30                2556
ber01-VHDL13_DWPG_171430-1910171430-dsw--0-ia5     17-Oct-2019 14:30                2556
ber01-VHDL13_DWPG_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                2506
ber01-VHDL13_DWPG_171630-1910171630-dsw--0-ia5     17-Oct-2019 16:30                2505
ber01-VHDL13_DWPG_171730-1910171730-dsw--0-ia5     17-Oct-2019 17:30                2505
ber01-VHDL13_DWPG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2487
ber01-VHDL13_DWPG_171930-1910171930-dsw--0-ia5     17-Oct-2019 19:30                2486
ber01-VHDL13_DWPG_172030-1910172030-dsw--0-ia5     17-Oct-2019 20:30                2486
ber01-VHDL13_DWPG_180030-1910180030-dsw--0-ia5     18-Oct-2019 00:30                2459
ber01-VHDL13_DWPG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                3326
ber01-VHDL13_DWPG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2990
ber01-VHDL13_DWPG_180530-1910180530-dsw--0-ia5     18-Oct-2019 05:30                2988
ber01-VHDL13_DWPG_180630-1910180630-dsw--0-ia5     18-Oct-2019 06:30                2988
ber01-VHDL13_DWPG_180730-1910180730-dsw--0-ia5     18-Oct-2019 07:30                2988
ber01-VHDL13_DWPG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3021
ber01-VHDL13_DWPG_180930-1910180930-dsw--0-ia5     18-Oct-2019 09:30                3020
ber01-VHDL13_DWPG_181030-1910181030-dsw--0-ia5     18-Oct-2019 10:30                3020
ber01-VHDL13_DWPG_181130-1910181130-dsw--0-ia5     18-Oct-2019 11:30                2984
ber01-VHDL13_DWPG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                2991
ber01-VHDL13_DWPG_181330-1910181330-dsw--0-ia5     18-Oct-2019 13:30                2990
ber01-VHDL13_DWPG_181430-1910181430-dsw--0-ia5     18-Oct-2019 14:30                2990
ber01-VHDL13_DWPG_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                2919
ber01-VHDL13_DWPG_181630-1910181630-dsw--0-ia5     18-Oct-2019 16:30                2918
ber01-VHDL13_DWPG_181730-1910181730-dsw--0-ia5     18-Oct-2019 17:30                2918
ber01-VHDL13_DWPG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2451
ber01-VHDL13_DWPG_181930-1910181930-dsw--0-ia5     18-Oct-2019 19:30                2450
ber01-VHDL13_DWPG_182030-1910182030-dsw--0-ia5     18-Oct-2019 20:30                2450
ber01-VHDL13_DWPG_190030-1910190030-dsw--0-ia5     19-Oct-2019 00:30                2007
ber01-VHDL13_DWPG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                1967
ber01-VHDL13_DWPH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2085
ber01-VHDL13_DWPH_170530-1910170530-dsw--0-ia5     17-Oct-2019 05:30                2085
ber01-VHDL13_DWPH_170630-1910170630-dsw--0-ia5     17-Oct-2019 06:30                2085
ber01-VHDL13_DWPH_170730-1910170730-dsw--0-ia5     17-Oct-2019 07:30                2085
ber01-VHDL13_DWPH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2918
ber01-VHDL13_DWPH_170930-1910170930-dsw--0-ia5     17-Oct-2019 09:30                2918
ber01-VHDL13_DWPH_171030-1910171030-dsw--0-ia5     17-Oct-2019 10:30                2918
ber01-VHDL13_DWPH_171130-1910171130-dsw--0-ia5     17-Oct-2019 11:30                2982
ber01-VHDL13_DWPH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                2957
ber01-VHDL13_DWPH_171330-1910171330-dsw--0-ia5     17-Oct-2019 13:30                2957
ber01-VHDL13_DWPH_171430-1910171430-dsw--0-ia5     17-Oct-2019 14:30                2957
ber01-VHDL13_DWPH_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                2916
ber01-VHDL13_DWPH_171630-1910171630-dsw--0-ia5     17-Oct-2019 16:30                2916
ber01-VHDL13_DWPH_171730-1910171730-dsw--0-ia5     17-Oct-2019 17:30                2916
ber01-VHDL13_DWPH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2887
ber01-VHDL13_DWPH_171930-1910171930-dsw--0-ia5     17-Oct-2019 19:30                2887
ber01-VHDL13_DWPH_172030-1910172030-dsw--0-ia5     17-Oct-2019 20:30                2887
ber01-VHDL13_DWPH_180030-1910180030-dsw--0-ia5     18-Oct-2019 00:30                3251
ber01-VHDL13_DWPH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                3267
ber01-VHDL13_DWPH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                3079
ber01-VHDL13_DWPH_180530-1910180530-dsw--0-ia5     18-Oct-2019 05:30                3079
ber01-VHDL13_DWPH_180630-1910180630-dsw--0-ia5     18-Oct-2019 06:30                3079
ber01-VHDL13_DWPH_180730-1910180730-dsw--0-ia5     18-Oct-2019 07:30                3079
ber01-VHDL13_DWPH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3077
ber01-VHDL13_DWPH_180930-1910180930-dsw--0-ia5     18-Oct-2019 09:30                3077
ber01-VHDL13_DWPH_181030-1910181030-dsw--0-ia5     18-Oct-2019 10:30                3077
ber01-VHDL13_DWPH_181130-1910181130-dsw--0-ia5     18-Oct-2019 11:30                3087
ber01-VHDL13_DWPH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                3183
ber01-VHDL13_DWPH_181330-1910181330-dsw--0-ia5     18-Oct-2019 13:30                3183
ber01-VHDL13_DWPH_181430-1910181430-dsw--0-ia5     18-Oct-2019 14:30                3183
ber01-VHDL13_DWPH_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                3171
ber01-VHDL13_DWPH_181630-1910181630-dsw--0-ia5     18-Oct-2019 16:30                3171
ber01-VHDL13_DWPH_181730-1910181730-dsw--0-ia5     18-Oct-2019 17:30                3171
ber01-VHDL13_DWPH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2445
ber01-VHDL13_DWPH_181930-1910181930-dsw--0-ia5     18-Oct-2019 19:30                2445
ber01-VHDL13_DWPH_182030-1910182030-dsw--0-ia5     18-Oct-2019 20:30                2445
ber01-VHDL13_DWPH_190030-1910190030-dsw--0-ia5     19-Oct-2019 00:30                2160
ber01-VHDL13_DWPH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2164
ber01-VHDL13_DWSG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2844
ber01-VHDL13_DWSG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2876
ber01-VHDL13_DWSG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                3012
ber01-VHDL13_DWSG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2921
ber01-VHDL13_DWSG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2979
ber01-VHDL13_DWSG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                3189
ber01-VHDL13_DWSG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3091
ber01-VHDL13_DWSG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                3330
ber01-VHDL13_DWSG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2766
ber01-VHDL13_DWSG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2840
ber01-VHDL13_DWSN_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2048
ber01-VHDL13_DWSN_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2043
ber01-VHDL13_DWSN_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:30                2171
ber01-VHDL13_DWSN_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2352
ber01-VHDL13_DWSN_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2502
ber01-VHDL13_DWSN_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2773
ber01-VHDL13_DWSN_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2521
ber01-VHDL13_DWSN_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:30                2515
ber01-VHDL13_DWSN_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2182
ber01-VHDL13_DWSN_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2365
ber01-VHDL13_DWSO_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2588
ber01-VHDL13_DWSO_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2585
ber01-VHDL13_DWSO_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:30                2561
ber01-VHDL13_DWSO_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2601
ber01-VHDL13_DWSO_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2498
ber01-VHDL13_DWSO_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2752
ber01-VHDL13_DWSO_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2757
ber01-VHDL13_DWSO_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:30                3059
ber01-VHDL13_DWSO_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2500
ber01-VHDL13_DWSO_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2638
ber01-VHDL13_DWSP_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                2229
ber01-VHDL13_DWSP_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                2226
ber01-VHDL13_DWSP_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:30                2345
ber01-VHDL13_DWSP_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                2201
ber01-VHDL13_DWSP_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                2453
ber01-VHDL13_DWSP_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                2710
ber01-VHDL13_DWSP_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                2549
ber01-VHDL13_DWSP_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:30                2572
ber01-VHDL13_DWSP_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                2094
ber01-VHDL13_DWSP_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2280
ber01-VHDL17_DWOG_171200-1910171200-dsw--0-ia5     17-Oct-2019 12:01                3274
ber01-VHDL17_DWOG_181200-1910181200-dsw--0-ia5     18-Oct-2019 11:07                3483
ber01-VHDL20_DWHG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3645
ber01-VHDL20_DWHG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4188
ber01-VHDL20_DWHG_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:45                4240
ber01-VHDL20_DWHG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4009
ber01-VHDL20_DWHG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4314
ber01-VHDL20_DWHG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4290
ber01-VHDL20_DWHG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4218
ber01-VHDL20_DWHG_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:45                4153
ber01-VHDL20_DWHG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3434
ber01-VHDL20_DWHG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                3490
ber01-VHDL20_DWHH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3028
ber01-VHDL20_DWHH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                3502
ber01-VHDL20_DWHH_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:45                3544
ber01-VHDL20_DWHH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                3267
ber01-VHDL20_DWHH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                3692
ber01-VHDL20_DWHH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                3666
ber01-VHDL20_DWHH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                3687
ber01-VHDL20_DWHH_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:45                3627
ber01-VHDL20_DWHH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                2879
ber01-VHDL20_DWHH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                2872
gts01-VHDL12_DWON_170530-1910170530-afsv--72-ia5   17-Oct-2019 05:30                3210
gts01-VHDL12_DWON_170815-1910170815-afsv--44-ia5   17-Oct-2019 08:15                3466
gts01-VHDL12_DWON_171330-1910171230-afsv--95-ia5   17-Oct-2019 12:30                3474
gts01-VHDL12_DWON_171815-1910171745-afsv--44-ia5   17-Oct-2019 17:45                3114
gts01-VHDL12_DWON_180115-1910180145-afsv--92-ia5   18-Oct-2019 01:45                4079
gts01-VHDL12_DWON_180530-1910180530-afsv--19-ia5   18-Oct-2019 05:30                4219
gts01-VHDL12_DWON_180815-1910180815-afsv--91-ia5   18-Oct-2019 08:15                4219
gts01-VHDL12_DWON_181330-1910181230-afsv--37-ia5   18-Oct-2019 12:30                3894
gts01-VHDL12_DWON_181815-1910181745-afsv--81-ia5   18-Oct-2019 17:45                3116
gts01-VHDL12_DWON_190115-1910190145-afsv--24-ia5   19-Oct-2019 01:45                3343
pid-VHDL12_DWEH_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:28                2366
pid-VHDL12_DWEH_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:28                1796
pid-VHDL12_DWHG_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                1584
pid-VHDL12_DWHG_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2201
pid-VHDL12_DWHG_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2195
pid-VHDL12_DWHG_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                1434
pid-VHDL12_DWHH_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                1750
pid-VHDL12_DWHH_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2298
pid-VHDL12_DWHH_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2291
pid-VHDL12_DWHH_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                1588
pid-VHDL12_DWLG_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                1636
pid-VHDL12_DWLG_170800-1910170800-dsw--0-ia5       17-Oct-2019 08:30                1749
pid-VHDL12_DWLG_171300-1910171300-dsw--0-ia5       17-Oct-2019 12:30                1756
pid-VHDL12_DWLG_171800-1910171800-dsw--0-ia5       17-Oct-2019 18:30                1511
pid-VHDL12_DWLG_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2063
pid-VHDL12_DWLG_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2064
pid-VHDL12_DWLG_180800-1910180800-dsw--0-ia5       18-Oct-2019 08:30                2122
pid-VHDL12_DWLG_181300-1910181300-dsw--0-ia5       18-Oct-2019 12:30                1923
pid-VHDL12_DWLG_181800-1910181800-dsw--0-ia5       18-Oct-2019 18:30                1611
pid-VHDL12_DWLG_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                1627
pid-VHDL12_DWLH_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                1840
pid-VHDL12_DWLH_170800-1910170800-dsw--0-ia5       17-Oct-2019 08:30                2036
pid-VHDL12_DWLH_171300-1910171300-dsw--0-ia5       17-Oct-2019 12:30                2023
pid-VHDL12_DWLH_171800-1910171800-dsw--0-ia5       17-Oct-2019 18:30                1787
pid-VHDL12_DWLH_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2511
pid-VHDL12_DWLH_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2461
pid-VHDL12_DWLH_180800-1910180800-dsw--0-ia5       18-Oct-2019 08:30                2861
pid-VHDL12_DWLH_181300-1910181300-dsw--0-ia5       18-Oct-2019 12:30                2895
pid-VHDL12_DWLH_181800-1910181800-dsw--0-ia5       18-Oct-2019 18:30                1787
pid-VHDL12_DWLH_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                1955
pid-VHDL12_DWLI_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                1548
pid-VHDL12_DWLI_170800-1910170800-dsw--0-ia5       17-Oct-2019 08:30                1952
pid-VHDL12_DWLI_171300-1910171300-dsw--0-ia5       17-Oct-2019 12:30                1882
pid-VHDL12_DWLI_171800-1910171800-dsw--0-ia5       17-Oct-2019 18:30                1667
pid-VHDL12_DWLI_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2088
pid-VHDL12_DWLI_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2033
pid-VHDL12_DWLI_180800-1910180800-dsw--0-ia5       18-Oct-2019 08:30                2277
pid-VHDL12_DWLI_181300-1910181300-dsw--0-ia5       18-Oct-2019 12:30                2279
pid-VHDL12_DWLI_181800-1910181800-dsw--0-ia5       18-Oct-2019 18:30                1600
pid-VHDL12_DWLI_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                1650
pid-VHDL12_DWMG_170400-1910170400-dsw--0-ia5       17-Oct-2019 04:30                2261
pid-VHDL12_DWMG_170800-1910170800-dsw--0-ia5       17-Oct-2019 08:30                2211
pid-VHDL12_DWMG_171300-1910171300-dsw--0-ia5       17-Oct-2019 12:30                2141
pid-VHDL12_DWMG_171800-1910171800-dsw--0-ia5       17-Oct-2019 18:30                1931
pid-VHDL12_DWMG_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2419
pid-VHDL12_DWMG_180400-1910180400-dsw--0-ia5       18-Oct-2019 04:30                2411
pid-VHDL12_DWMG_180800-1910180800-dsw--0-ia5       18-Oct-2019 08:30                2804
pid-VHDL12_DWMG_181300-1910181300-dsw--0-ia5       18-Oct-2019 12:30                2804
pid-VHDL12_DWMG_181800-1910181800-dsw--0-ia5       18-Oct-2019 18:30                2136
pid-VHDL12_DWMG_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                2509
pid-VHDL12_DWOG_180100-1910180100-dsw--0-ia5       18-Oct-2019 01:45                4723
pid-VHDL12_DWOG_180300-1910180300-dsw--0-ia5       18-Oct-2019 03:00                4727
pid-VHDL12_DWOG_190100-1910190100-dsw--0-ia5       19-Oct-2019 01:45                4917
pid-VHDL12_DWOG_190300-1910190300-dsw--0-ia5       19-Oct-2019 03:00                4810
pid-VHDL12_DWOH_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:28                2291
pid-VHDL12_DWOH_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:28                1958
pid-VHDL12_DWOI_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:28                2441
pid-VHDL12_DWOI_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:28                2292
pid-VHDL12_DWSG_180200-1910180200-dsw--0-ia5       18-Oct-2019 02:30                2611
pid-VHDL12_DWSG_190200-1910190200-dsw--0-ia5       19-Oct-2019 02:30                2495
swis2-VHDL20_DWEG_170400-1910170400-dsw--0-ia5     17-Oct-2019 05:15                4410
swis2-VHDL20_DWEG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4701
swis2-VHDL20_DWEG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4690
swis2-VHDL20_DWEG_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:45                4583
swis2-VHDL20_DWEG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4398
swis2-VHDL20_DWEG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4329
swis2-VHDL20_DWEG_180400-1910180400-dsw--0-ia5     18-Oct-2019 05:15                4612
swis2-VHDL20_DWEG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4630
swis2-VHDL20_DWEG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4790
swis2-VHDL20_DWEG_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:45                4261
swis2-VHDL20_DWEG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3983
swis2-VHDL20_DWEG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                4095
swis2-VHDL20_DWEH_170400-1910170400-dsw--0-ia5     17-Oct-2019 05:15                4510
swis2-VHDL20_DWEH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                5632
swis2-VHDL20_DWEH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4888
swis2-VHDL20_DWEH_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:45                4836
swis2-VHDL20_DWEH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4665
swis2-VHDL20_DWEH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4472
swis2-VHDL20_DWEH_180400-1910180400-dsw--0-ia5     18-Oct-2019 05:15                4692
swis2-VHDL20_DWEH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                5319
swis2-VHDL20_DWEH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4755
swis2-VHDL20_DWEH_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:45                4393
swis2-VHDL20_DWEH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3842
swis2-VHDL20_DWEH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                3964
swis2-VHDL20_DWEI_170400-1910170400-dsw--0-ia5     17-Oct-2019 05:15                4463
swis2-VHDL20_DWEI_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4832
swis2-VHDL20_DWEI_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4766
swis2-VHDL20_DWEI_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:45                4797
swis2-VHDL20_DWEI_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4655
swis2-VHDL20_DWEI_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4480
swis2-VHDL20_DWEI_180400-1910180400-dsw--0-ia5     18-Oct-2019 05:15                4649
swis2-VHDL20_DWEI_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4568
swis2-VHDL20_DWEI_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4751
swis2-VHDL20_DWEI_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:45                4498
swis2-VHDL20_DWEI_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                4364
swis2-VHDL20_DWEI_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                4409
swis2-VHDL20_DWHG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3645
swis2-VHDL20_DWHG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4188
swis2-VHDL20_DWHG_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:45                4240
swis2-VHDL20_DWHG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4009
swis2-VHDL20_DWHG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4314
swis2-VHDL20_DWHG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4290
swis2-VHDL20_DWHG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4218
swis2-VHDL20_DWHG_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:45                4153
swis2-VHDL20_DWHG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3434
swis2-VHDL20_DWHG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                3490
swis2-VHDL20_DWHH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3028
swis2-VHDL20_DWHH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                3502
swis2-VHDL20_DWHH_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:45                3544
swis2-VHDL20_DWHH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                3267
swis2-VHDL20_DWHH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                3692
swis2-VHDL20_DWHH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                3666
swis2-VHDL20_DWHH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                3687
swis2-VHDL20_DWHH_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:45                3627
swis2-VHDL20_DWHH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                2879
swis2-VHDL20_DWHH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                2872
swis2-VHDL20_DWLG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3670
swis2-VHDL20_DWLG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                3780
swis2-VHDL20_DWLG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                3787
swis2-VHDL20_DWLG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                3542
swis2-VHDL20_DWLG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4095
swis2-VHDL20_DWLG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4094
swis2-VHDL20_DWLG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4196
swis2-VHDL20_DWLG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                3997
swis2-VHDL20_DWLG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3669
swis2-VHDL20_DWLG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                3686
swis2-VHDL20_DWLH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3912
swis2-VHDL20_DWLH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4108
swis2-VHDL20_DWLH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4095
swis2-VHDL20_DWLH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                3859
swis2-VHDL20_DWLH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4578
swis2-VHDL20_DWLH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4525
swis2-VHDL20_DWLH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4953
swis2-VHDL20_DWLH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4987
swis2-VHDL20_DWLH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3857
swis2-VHDL20_DWLH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                4018
swis2-VHDL20_DWLI_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                3647
swis2-VHDL20_DWLI_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4051
swis2-VHDL20_DWLI_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                3981
swis2-VHDL20_DWLI_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                3766
swis2-VHDL20_DWLI_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4155
swis2-VHDL20_DWLI_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4098
swis2-VHDL20_DWLI_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4392
swis2-VHDL20_DWLI_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4391
swis2-VHDL20_DWLI_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                3675
swis2-VHDL20_DWLI_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                3697
swis2-VHDL20_DWMG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                5754
swis2-VHDL20_DWMG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                5704
swis2-VHDL20_DWMG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                5460
swis2-VHDL20_DWMG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                5250
swis2-VHDL20_DWMG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                5696
swis2-VHDL20_DWMG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                5802
swis2-VHDL20_DWMG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                6195
swis2-VHDL20_DWMG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                6195
swis2-VHDL20_DWMG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                5547
swis2-VHDL20_DWMG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                5757
swis2-VHDL20_DWMO_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                4460
swis2-VHDL20_DWMO_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4574
swis2-VHDL20_DWMO_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4466
swis2-VHDL20_DWMO_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4137
swis2-VHDL20_DWMO_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4517
swis2-VHDL20_DWMO_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4505
swis2-VHDL20_DWMO_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4805
swis2-VHDL20_DWMO_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                4772
swis2-VHDL20_DWMO_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                4118
swis2-VHDL20_DWMO_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                4215
swis2-VHDL20_DWMP_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                4998
swis2-VHDL20_DWMP_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4808
swis2-VHDL20_DWMP_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:45                4743
swis2-VHDL20_DWMP_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4714
swis2-VHDL20_DWMP_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                5087
swis2-VHDL20_DWMP_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                5089
swis2-VHDL20_DWMP_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                5427
swis2-VHDL20_DWMP_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:45                5418
swis2-VHDL20_DWMP_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                5247
swis2-VHDL20_DWMP_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                5476
swis2-VHDL20_DWPG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                3152
swis2-VHDL20_DWPG_170530-1910170530-dsw--0-ia5     17-Oct-2019 05:30                3152
swis2-VHDL20_DWPG_170630-1910170630-dsw--0-ia5     17-Oct-2019 06:30                3152
swis2-VHDL20_DWPG_170730-1910170730-dsw--0-ia5     17-Oct-2019 07:30                3152
swis2-VHDL20_DWPG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:31                3659
swis2-VHDL20_DWPG_170930-1910170930-dsw--0-ia5     17-Oct-2019 09:30                3721
swis2-VHDL20_DWPG_171030-1910171030-dsw--0-ia5     17-Oct-2019 10:30                3721
swis2-VHDL20_DWPG_171130-1910171130-dsw--0-ia5     17-Oct-2019 11:30                3676
swis2-VHDL20_DWPG_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                3555
swis2-VHDL20_DWPG_171330-1910171330-dsw--0-ia5     17-Oct-2019 13:30                3584
swis2-VHDL20_DWPG_171430-1910171430-dsw--0-ia5     17-Oct-2019 14:30                3584
swis2-VHDL20_DWPG_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                3504
swis2-VHDL20_DWPG_171630-1910171630-dsw--0-ia5     17-Oct-2019 16:30                3533
swis2-VHDL20_DWPG_171730-1910171730-dsw--0-ia5     17-Oct-2019 17:30                3533
swis2-VHDL20_DWPG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                3515
swis2-VHDL20_DWPG_171930-1910171930-dsw--0-ia5     17-Oct-2019 19:30                3514
swis2-VHDL20_DWPG_172030-1910172030-dsw--0-ia5     17-Oct-2019 20:30                3514
swis2-VHDL20_DWPG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                4330
swis2-VHDL20_DWPG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                3951
swis2-VHDL20_DWPG_180530-1910180530-dsw--0-ia5     18-Oct-2019 05:30                3951
swis2-VHDL20_DWPG_180630-1910180630-dsw--0-ia5     18-Oct-2019 06:30                3951
swis2-VHDL20_DWPG_180730-1910180730-dsw--0-ia5     18-Oct-2019 07:30                3951
swis2-VHDL20_DWPG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                3984
swis2-VHDL20_DWPG_180930-1910180930-dsw--0-ia5     18-Oct-2019 09:30                4046
swis2-VHDL20_DWPG_181030-1910181030-dsw--0-ia5     18-Oct-2019 10:30                4046
swis2-VHDL20_DWPG_181130-1910181130-dsw--0-ia5     18-Oct-2019 11:30                4010
swis2-VHDL20_DWPG_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                3987
swis2-VHDL20_DWPG_181330-1910181330-dsw--0-ia5     18-Oct-2019 13:31                4016
swis2-VHDL20_DWPG_181430-1910181430-dsw--0-ia5     18-Oct-2019 14:30                4016
swis2-VHDL20_DWPG_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                3915
swis2-VHDL20_DWPG_181630-1910181630-dsw--0-ia5     18-Oct-2019 16:30                3944
swis2-VHDL20_DWPG_181730-1910181730-dsw--0-ia5     18-Oct-2019 17:30                3944
swis2-VHDL20_DWPG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                3477
swis2-VHDL20_DWPG_181930-1910181930-dsw--0-ia5     18-Oct-2019 19:30                3476
swis2-VHDL20_DWPG_182030-1910182030-dsw--0-ia5     18-Oct-2019 20:30                3476
swis2-VHDL20_DWPG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                2917
swis2-VHDL20_DWPH_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:30                3050
swis2-VHDL20_DWPH_170530-1910170530-dsw--0-ia5     17-Oct-2019 05:30                3050
swis2-VHDL20_DWPH_170630-1910170630-dsw--0-ia5     17-Oct-2019 06:30                3050
swis2-VHDL20_DWPH_170730-1910170730-dsw--0-ia5     17-Oct-2019 07:30                3050
swis2-VHDL20_DWPH_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:30                3883
swis2-VHDL20_DWPH_170930-1910170930-dsw--0-ia5     17-Oct-2019 09:30                3946
swis2-VHDL20_DWPH_171030-1910171030-dsw--0-ia5     17-Oct-2019 10:30                3946
swis2-VHDL20_DWPH_171130-1910171130-dsw--0-ia5     17-Oct-2019 11:30                4010
swis2-VHDL20_DWPH_171300-1910171300-dsw--0-ia5     17-Oct-2019 12:30                3985
swis2-VHDL20_DWPH_171330-1910171330-dsw--0-ia5     17-Oct-2019 13:30                3985
swis2-VHDL20_DWPH_171430-1910171430-dsw--0-ia5     17-Oct-2019 14:31                3985
swis2-VHDL20_DWPH_171500-1910171500-dsw--0-ia5     17-Oct-2019 15:30                3944
swis2-VHDL20_DWPH_171630-1910171630-dsw--0-ia5     17-Oct-2019 16:31                3944
swis2-VHDL20_DWPH_171730-1910171730-dsw--0-ia5     17-Oct-2019 17:30                3944
swis2-VHDL20_DWPH_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:30                3915
swis2-VHDL20_DWPH_171930-1910171930-dsw--0-ia5     17-Oct-2019 19:30                3915
swis2-VHDL20_DWPH_172030-1910172030-dsw--0-ia5     17-Oct-2019 20:30                3915
swis2-VHDL20_DWPH_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:30                4296
swis2-VHDL20_DWPH_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:30                4042
swis2-VHDL20_DWPH_180530-1910180530-dsw--0-ia5     18-Oct-2019 05:30                4042
swis2-VHDL20_DWPH_180630-1910180630-dsw--0-ia5     18-Oct-2019 06:30                4042
swis2-VHDL20_DWPH_180730-1910180730-dsw--0-ia5     18-Oct-2019 07:30                4042
swis2-VHDL20_DWPH_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:30                4040
swis2-VHDL20_DWPH_180930-1910180930-dsw--0-ia5     18-Oct-2019 09:31                4103
swis2-VHDL20_DWPH_181030-1910181030-dsw--0-ia5     18-Oct-2019 10:30                4103
swis2-VHDL20_DWPH_181130-1910181130-dsw--0-ia5     18-Oct-2019 11:30                4113
swis2-VHDL20_DWPH_181300-1910181300-dsw--0-ia5     18-Oct-2019 12:30                4209
swis2-VHDL20_DWPH_181330-1910181330-dsw--0-ia5     18-Oct-2019 13:30                4209
swis2-VHDL20_DWPH_181430-1910181430-dsw--0-ia5     18-Oct-2019 14:30                4209
swis2-VHDL20_DWPH_181500-1910181500-dsw--0-ia5     18-Oct-2019 15:30                4197
swis2-VHDL20_DWPH_181630-1910181630-dsw--0-ia5     18-Oct-2019 16:30                4197
swis2-VHDL20_DWPH_181730-1910181730-dsw--0-ia5     18-Oct-2019 17:30                4197
swis2-VHDL20_DWPH_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:30                3471
swis2-VHDL20_DWPH_181930-1910181930-dsw--0-ia5     18-Oct-2019 19:30                3471
swis2-VHDL20_DWPH_182030-1910182030-dsw--0-ia5     18-Oct-2019 20:30                3471
swis2-VHDL20_DWPH_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:30                3113
swis2-VHDL20_DWSG_170400-1910170400-dsw--0-ia5     17-Oct-2019 04:45                4605
swis2-VHDL20_DWSG_170800-1910170800-dsw--0-ia5     17-Oct-2019 08:45                4635
swis2-VHDL20_DWSG_171300-1910171300-dsw--0-ia5     17-Oct-2019 13:45                4775
swis2-VHDL20_DWSG_171800-1910171800-dsw--0-ia5     17-Oct-2019 18:45                4684
swis2-VHDL20_DWSG_180200-1910180200-dsw--0-ia5     18-Oct-2019 02:45                4733
swis2-VHDL20_DWSG_180400-1910180400-dsw--0-ia5     18-Oct-2019 04:45                4950
swis2-VHDL20_DWSG_180800-1910180800-dsw--0-ia5     18-Oct-2019 08:45                4849
swis2-VHDL20_DWSG_181300-1910181300-dsw--0-ia5     18-Oct-2019 13:45                5093
swis2-VHDL20_DWSG_181800-1910181800-dsw--0-ia5     18-Oct-2019 18:45                4529
swis2-VHDL20_DWSG_190200-1910190200-dsw--0-ia5     19-Oct-2019 02:45                4597