Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_290600                                 29-Jan-2023 17:59                6085
FPDL13_DWMZ_300600                                 30-Jan-2023 13:05                2981
SXDL31_DWAV_291800                                 29-Jan-2023 18:21               10971
SXDL31_DWAV_300800                                 30-Jan-2023 08:25               17203
SXDL31_DWAV_301800                                 30-Jan-2023 17:40               15725
SXDL31_DWAV_310800                                 31-Jan-2023 12:23               13150
SXDL31_DWAV_LATEST                                 31-Jan-2023 12:23               13150
SXDL33_DWAV_300000                                 30-Jan-2023 10:24               11968
SXDL33_DWAV_310000                                 31-Jan-2023 11:33               16788
SXDL33_DWAV_LATEST                                 31-Jan-2023 11:33               16788
ber01-FWDL39_DWMS_301230-2301301230-dsw--0-ia5     30-Jan-2023 13:42                1858
ber01-FWDL39_DWMS_311230-2301311230-dsw--0-ia5     31-Jan-2023 13:38                1892
ber01-VHDL13_DWEH_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:28                4927
ber01-VHDL13_DWEH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:28                5102
ber01-VHDL13_DWEH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:28                4483
ber01-VHDL13_DWEH_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:58                4491
ber01-VHDL13_DWEH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:28                4153
ber01-VHDL13_DWEH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:28                4198
ber01-VHDL13_DWEH_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                4191
ber01-VHDL13_DWEH_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:28                3338
ber01-VHDL13_DWEH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:28                3036
ber01-VHDL13_DWEH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:28                3315
ber01-VHDL13_DWEH_310400-2301310400-dsw--0-ia5     31-Jan-2023 05:58                3404
ber01-VHDL13_DWEH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:28                3857
ber01-VHDL13_DWEH_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:01                3885
ber01-VHDL13_DWEH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:28                3830
ber01-VHDL13_DWHG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3524
ber01-VHDL13_DWHG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                3655
ber01-VHDL13_DWHG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3664
ber01-VHDL13_DWHG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3471
ber01-VHDL13_DWHG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3547
ber01-VHDL13_DWHG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                2843
ber01-VHDL13_DWHG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3170
ber01-VHDL13_DWHG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3171
ber01-VHDL13_DWHG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3114
ber01-VHDL13_DWHG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3286
ber01-VHDL13_DWHH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                2653
ber01-VHDL13_DWHH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                2729
ber01-VHDL13_DWHH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                2746
ber01-VHDL13_DWHH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                2931
ber01-VHDL13_DWHH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                2934
ber01-VHDL13_DWHH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                2416
ber01-VHDL13_DWHH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                2621
ber01-VHDL13_DWHH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                2674
ber01-VHDL13_DWHH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                2543
ber01-VHDL13_DWHH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                2557
ber01-VHDL13_DWLG_291433-2301291433-dsw--0-ia5     29-Jan-2023 14:33                3905
ber01-VHDL13_DWLG_291533-2301291533-dsw--0-ia5     29-Jan-2023 15:33                4126
ber01-VHDL13_DWLG_291633-2301291633-dsw--0-ia5     29-Jan-2023 16:33                4126
ber01-VHDL13_DWLG_291733-2301291733-dsw--0-ia5     29-Jan-2023 17:33                4126
ber01-VHDL13_DWLG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3754
ber01-VHDL13_DWLG_291833-2301291833-dsw--0-ia5     29-Jan-2023 18:33                4126
ber01-VHDL13_DWLG_292033-2301292033-dsw--0-ia5     29-Jan-2023 20:33                3760
ber01-VHDL13_DWLG_292133-2301292133-dsw--0-ia5     29-Jan-2023 21:33                3760
ber01-VHDL13_DWLG_300133-2301300133-dsw--0-ia5     30-Jan-2023 01:33                4785
ber01-VHDL13_DWLG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4858
ber01-VHDL13_DWLG_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:59                4795
ber01-VHDL13_DWLG_300633-2301300633-dsw--0-ia5     30-Jan-2023 06:33                4801
ber01-VHDL13_DWLG_300733-2301300733-dsw--0-ia5     30-Jan-2023 07:33                4802
ber01-VHDL13_DWLG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4800
ber01-VHDL13_DWLG_300833-2301300833-dsw--0-ia5     30-Jan-2023 08:33                4367
ber01-VHDL13_DWLG_301033-2301301033-dsw--0-ia5     30-Jan-2023 10:33                4809
ber01-VHDL13_DWLG_301133-2301301133-dsw--0-ia5     30-Jan-2023 11:33                4440
ber01-VHDL13_DWLG_301233-2301301233-dsw--0-ia5     30-Jan-2023 12:33                4440
ber01-VHDL13_DWLG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3797
ber01-VHDL13_DWLG_301433-2301301433-dsw--0-ia5     30-Jan-2023 14:33                3803
ber01-VHDL13_DWLG_301533-2301301533-dsw--0-ia5     30-Jan-2023 15:33                3803
ber01-VHDL13_DWLG_301633-2301301633-dsw--0-ia5     30-Jan-2023 16:33                3803
ber01-VHDL13_DWLG_301733-2301301733-dsw--0-ia5     30-Jan-2023 17:33                3803
ber01-VHDL13_DWLG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3272
ber01-VHDL13_DWLG_301833-2301301833-dsw--0-ia5     30-Jan-2023 18:33                3278
ber01-VHDL13_DWLG_302033-2301302033-dsw--0-ia5     30-Jan-2023 20:33                3278
ber01-VHDL13_DWLG_302133-2301302133-dsw--0-ia5     30-Jan-2023 21:33                3278
ber01-VHDL13_DWLG_310133-2301310133-dsw--0-ia5     31-Jan-2023 01:33                3364
ber01-VHDL13_DWLG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3151
ber01-VHDL13_DWLG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3460
ber01-VHDL13_DWLG_310633-2301310633-dsw--0-ia5     31-Jan-2023 06:33                3466
ber01-VHDL13_DWLG_310733-2301310733-dsw--0-ia5     31-Jan-2023 07:33                3466
ber01-VHDL13_DWLG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3849
ber01-VHDL13_DWLG_310833-2301310833-dsw--0-ia5     31-Jan-2023 08:33                3858
ber01-VHDL13_DWLG_311033-2301311033-dsw--0-ia5     31-Jan-2023 10:33                3858
ber01-VHDL13_DWLG_311133-2301311133-dsw--0-ia5     31-Jan-2023 11:33                3858
ber01-VHDL13_DWLG_311233-2301311233-dsw--0-ia5     31-Jan-2023 12:33                3819
ber01-VHDL13_DWLG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3813
ber01-VHDL13_DWLH_291433-2301291433-dsw--0-ia5     29-Jan-2023 14:33                4246
ber01-VHDL13_DWLH_291533-2301291533-dsw--0-ia5     29-Jan-2023 15:33                4520
ber01-VHDL13_DWLH_291633-2301291633-dsw--0-ia5     29-Jan-2023 16:33                4520
ber01-VHDL13_DWLH_291733-2301291733-dsw--0-ia5     29-Jan-2023 17:33                4520
ber01-VHDL13_DWLH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                4273
ber01-VHDL13_DWLH_291833-2301291833-dsw--0-ia5     29-Jan-2023 18:33                4520
ber01-VHDL13_DWLH_292033-2301292033-dsw--0-ia5     29-Jan-2023 20:33                4282
ber01-VHDL13_DWLH_292133-2301292133-dsw--0-ia5     29-Jan-2023 21:33                4282
ber01-VHDL13_DWLH_300133-2301300133-dsw--0-ia5     30-Jan-2023 01:33                4900
ber01-VHDL13_DWLH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4856
ber01-VHDL13_DWLH_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:59                4722
ber01-VHDL13_DWLH_300633-2301300633-dsw--0-ia5     30-Jan-2023 06:33                4731
ber01-VHDL13_DWLH_300733-2301300733-dsw--0-ia5     30-Jan-2023 07:33                4731
ber01-VHDL13_DWLH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4244
ber01-VHDL13_DWLH_300833-2301300833-dsw--0-ia5     30-Jan-2023 08:33                3858
ber01-VHDL13_DWLH_301033-2301301033-dsw--0-ia5     30-Jan-2023 10:33                4253
ber01-VHDL13_DWLH_301133-2301301133-dsw--0-ia5     30-Jan-2023 11:33                4224
ber01-VHDL13_DWLH_301233-2301301233-dsw--0-ia5     30-Jan-2023 12:33                4224
ber01-VHDL13_DWLH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3694
ber01-VHDL13_DWLH_301433-2301301433-dsw--0-ia5     30-Jan-2023 14:33                3703
ber01-VHDL13_DWLH_301533-2301301533-dsw--0-ia5     30-Jan-2023 15:33                3703
ber01-VHDL13_DWLH_301633-2301301633-dsw--0-ia5     30-Jan-2023 16:33                3703
ber01-VHDL13_DWLH_301733-2301301733-dsw--0-ia5     30-Jan-2023 17:33                3703
ber01-VHDL13_DWLH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3059
ber01-VHDL13_DWLH_301833-2301301833-dsw--0-ia5     30-Jan-2023 18:33                3068
ber01-VHDL13_DWLH_302033-2301302033-dsw--0-ia5     30-Jan-2023 20:33                3068
ber01-VHDL13_DWLH_302133-2301302133-dsw--0-ia5     30-Jan-2023 21:33                3068
ber01-VHDL13_DWLH_310133-2301310133-dsw--0-ia5     31-Jan-2023 01:33                3170
ber01-VHDL13_DWLH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3026
ber01-VHDL13_DWLH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3322
ber01-VHDL13_DWLH_310633-2301310633-dsw--0-ia5     31-Jan-2023 06:33                3331
ber01-VHDL13_DWLH_310733-2301310733-dsw--0-ia5     31-Jan-2023 07:33                3331
ber01-VHDL13_DWLH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3637
ber01-VHDL13_DWLH_310833-2301310833-dsw--0-ia5     31-Jan-2023 08:33                3646
ber01-VHDL13_DWLH_311033-2301311033-dsw--0-ia5     31-Jan-2023 10:33                3646
ber01-VHDL13_DWLH_311133-2301311133-dsw--0-ia5     31-Jan-2023 11:33                3646
ber01-VHDL13_DWLH_311233-2301311233-dsw--0-ia5     31-Jan-2023 12:33                3599
ber01-VHDL13_DWLH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3590
ber01-VHDL13_DWLI_291433-2301291433-dsw--0-ia5     29-Jan-2023 14:33                3959
ber01-VHDL13_DWLI_291533-2301291533-dsw--0-ia5     29-Jan-2023 15:33                3962
ber01-VHDL13_DWLI_291633-2301291633-dsw--0-ia5     29-Jan-2023 16:33                3962
ber01-VHDL13_DWLI_291733-2301291733-dsw--0-ia5     29-Jan-2023 17:33                3962
ber01-VHDL13_DWLI_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3622
ber01-VHDL13_DWLI_291833-2301291833-dsw--0-ia5     29-Jan-2023 18:33                3962
ber01-VHDL13_DWLI_292033-2301292033-dsw--0-ia5     29-Jan-2023 20:33                3633
ber01-VHDL13_DWLI_292133-2301292133-dsw--0-ia5     29-Jan-2023 21:33                3633
ber01-VHDL13_DWLI_300133-2301300133-dsw--0-ia5     30-Jan-2023 01:33                4515
ber01-VHDL13_DWLI_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4488
ber01-VHDL13_DWLI_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:59                4388
ber01-VHDL13_DWLI_300633-2301300633-dsw--0-ia5     30-Jan-2023 06:33                4391
ber01-VHDL13_DWLI_300733-2301300733-dsw--0-ia5     30-Jan-2023 07:33                4391
ber01-VHDL13_DWLI_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3955
ber01-VHDL13_DWLI_300833-2301300833-dsw--0-ia5     30-Jan-2023 08:33                3641
ber01-VHDL13_DWLI_301033-2301301033-dsw--0-ia5     30-Jan-2023 10:33                3961
ber01-VHDL13_DWLI_301133-2301301133-dsw--0-ia5     30-Jan-2023 11:33                3936
ber01-VHDL13_DWLI_301233-2301301233-dsw--0-ia5     30-Jan-2023 12:33                3936
ber01-VHDL13_DWLI_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3475
ber01-VHDL13_DWLI_301433-2301301433-dsw--0-ia5     30-Jan-2023 14:33                3481
ber01-VHDL13_DWLI_301533-2301301533-dsw--0-ia5     30-Jan-2023 15:33                3481
ber01-VHDL13_DWLI_301633-2301301633-dsw--0-ia5     30-Jan-2023 16:33                3481
ber01-VHDL13_DWLI_301733-2301301733-dsw--0-ia5     30-Jan-2023 17:33                3481
ber01-VHDL13_DWLI_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                2950
ber01-VHDL13_DWLI_301833-2301301833-dsw--0-ia5     30-Jan-2023 18:33                2956
ber01-VHDL13_DWLI_302033-2301302033-dsw--0-ia5     30-Jan-2023 20:33                2956
ber01-VHDL13_DWLI_302133-2301302133-dsw--0-ia5     30-Jan-2023 21:33                2956
ber01-VHDL13_DWLI_310133-2301310133-dsw--0-ia5     31-Jan-2023 01:33                3078
ber01-VHDL13_DWLI_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                2907
ber01-VHDL13_DWLI_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3056
ber01-VHDL13_DWLI_310633-2301310633-dsw--0-ia5     31-Jan-2023 06:33                3059
ber01-VHDL13_DWLI_310733-2301310733-dsw--0-ia5     31-Jan-2023 07:33                3059
ber01-VHDL13_DWLI_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3433
ber01-VHDL13_DWLI_310833-2301310833-dsw--0-ia5     31-Jan-2023 08:33                3439
ber01-VHDL13_DWLI_311033-2301311033-dsw--0-ia5     31-Jan-2023 10:33                3439
ber01-VHDL13_DWLI_311133-2301311133-dsw--0-ia5     31-Jan-2023 11:33                3439
ber01-VHDL13_DWLI_311233-2301311233-dsw--0-ia5     31-Jan-2023 12:33                3384
ber01-VHDL13_DWLI_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3378
ber01-VHDL13_DWMG_291400-2301291400-dsw--0-ia5     29-Jan-2023 14:30                4109
ber01-VHDL13_DWMG_291500-2301291500-dsw--0-ia5     29-Jan-2023 15:30                3995
ber01-VHDL13_DWMG_291600-2301291600-dsw--0-ia5     29-Jan-2023 16:30                3995
ber01-VHDL13_DWMG_291700-2301291700-dsw--0-ia5     29-Jan-2023 17:30                3995
ber01-VHDL13_DWMG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3876
ber01-VHDL13_DWMG_292000-2301292000-dsw--0-ia5     29-Jan-2023 20:30                4042
ber01-VHDL13_DWMG_292100-2301292100-dsw--0-ia5     29-Jan-2023 21:30                4042
ber01-VHDL13_DWMG_292200-2301292200-dsw--0-ia5     29-Jan-2023 22:30                4042
ber01-VHDL13_DWMG_292300-2301292300-dsw--0-ia5     29-Jan-2023 23:30                4616
ber01-VHDL13_DWMG_300000-2301300000-dsw--0-ia5     30-Jan-2023 00:30                4616
ber01-VHDL13_DWMG_300100-2301300100-dsw--0-ia5     30-Jan-2023 01:30                4616
ber01-VHDL13_DWMG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4616
ber01-VHDL13_DWMG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4319
ber01-VHDL13_DWMG_300600-2301300600-dsw--0-ia5     30-Jan-2023 06:30                4319
ber01-VHDL13_DWMG_300700-2301300700-dsw--0-ia5     30-Jan-2023 07:30                4319
ber01-VHDL13_DWMG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4470
ber01-VHDL13_DWMG_301000-2301301000-dsw--0-ia5     30-Jan-2023 10:30                4470
ber01-VHDL13_DWMG_301100-2301301100-dsw--0-ia5     30-Jan-2023 11:30                4469
ber01-VHDL13_DWMG_301200-2301301200-dsw--0-ia5     30-Jan-2023 12:30                4469
ber01-VHDL13_DWMG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                4358
ber01-VHDL13_DWMG_301400-2301301400-dsw--0-ia5     30-Jan-2023 14:30                4358
ber01-VHDL13_DWMG_301500-2301301500-dsw--0-ia5     30-Jan-2023 15:30                4358
ber01-VHDL13_DWMG_301600-2301301600-dsw--0-ia5     30-Jan-2023 16:30                4292
ber01-VHDL13_DWMG_301700-2301301700-dsw--0-ia5     30-Jan-2023 17:30                4292
ber01-VHDL13_DWMG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                4221
ber01-VHDL13_DWMG_302000-2301302000-dsw--0-ia5     30-Jan-2023 20:30                4152
ber01-VHDL13_DWMG_302100-2301302100-dsw--0-ia5     30-Jan-2023 21:30                4152
ber01-VHDL13_DWMG_302200-2301302200-dsw--0-ia5     30-Jan-2023 22:30                4152
ber01-VHDL13_DWMG_302300-2301302300-dsw--0-ia5     30-Jan-2023 23:30                4054
ber01-VHDL13_DWMG_310000-2301310000-dsw--0-ia5     31-Jan-2023 00:30                4054
ber01-VHDL13_DWMG_310100-2301310100-dsw--0-ia5     31-Jan-2023 01:30                4054
ber01-VHDL13_DWMG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                4054
ber01-VHDL13_DWMG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3763
ber01-VHDL13_DWMG_310600-2301310600-dsw--0-ia5     31-Jan-2023 06:30                3763
ber01-VHDL13_DWMG_310700-2301310700-dsw--0-ia5     31-Jan-2023 07:30                3763
ber01-VHDL13_DWMG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3450
ber01-VHDL13_DWMG_311000-2301311000-dsw--0-ia5     31-Jan-2023 10:30                3450
ber01-VHDL13_DWMG_311100-2301311100-dsw--0-ia5     31-Jan-2023 11:30                3450
ber01-VHDL13_DWMG_311200-2301311200-dsw--0-ia5     31-Jan-2023 12:30                3450
ber01-VHDL13_DWMG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3421
ber01-VHDL13_DWMO_291400-2301291400-dsw--0-ia5     29-Jan-2023 14:30                4193
ber01-VHDL13_DWMO_291500-2301291500-dsw--0-ia5     29-Jan-2023 15:30                4193
ber01-VHDL13_DWMO_291600-2301291600-dsw--0-ia5     29-Jan-2023 16:30                3982
ber01-VHDL13_DWMO_291700-2301291700-dsw--0-ia5     29-Jan-2023 17:30                3982
ber01-VHDL13_DWMO_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3865
ber01-VHDL13_DWMO_292000-2301292000-dsw--0-ia5     29-Jan-2023 20:30                3865
ber01-VHDL13_DWMO_292100-2301292100-dsw--0-ia5     29-Jan-2023 21:30                3907
ber01-VHDL13_DWMO_292200-2301292200-dsw--0-ia5     29-Jan-2023 22:30                3907
ber01-VHDL13_DWMO_292300-2301292300-dsw--0-ia5     29-Jan-2023 23:30                4523
ber01-VHDL13_DWMO_300000-2301300000-dsw--0-ia5     30-Jan-2023 00:30                4523
ber01-VHDL13_DWMO_300100-2301300100-dsw--0-ia5     30-Jan-2023 01:30                4523
ber01-VHDL13_DWMO_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4523
ber01-VHDL13_DWMO_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4215
ber01-VHDL13_DWMO_300600-2301300600-dsw--0-ia5     30-Jan-2023 06:30                4215
ber01-VHDL13_DWMO_300700-2301300700-dsw--0-ia5     30-Jan-2023 07:30                4215
ber01-VHDL13_DWMO_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4292
ber01-VHDL13_DWMO_301000-2301301000-dsw--0-ia5     30-Jan-2023 10:30                4264
ber01-VHDL13_DWMO_301100-2301301100-dsw--0-ia5     30-Jan-2023 11:30                4264
ber01-VHDL13_DWMO_301200-2301301200-dsw--0-ia5     30-Jan-2023 12:30                4264
ber01-VHDL13_DWMO_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                4284
ber01-VHDL13_DWMO_301400-2301301400-dsw--0-ia5     30-Jan-2023 14:30                4284
ber01-VHDL13_DWMO_301500-2301301500-dsw--0-ia5     30-Jan-2023 15:30                4284
ber01-VHDL13_DWMO_301600-2301301600-dsw--0-ia5     30-Jan-2023 16:30                4284
ber01-VHDL13_DWMO_301700-2301301700-dsw--0-ia5     30-Jan-2023 17:30                4284
ber01-VHDL13_DWMO_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3871
ber01-VHDL13_DWMO_302000-2301302000-dsw--0-ia5     30-Jan-2023 20:30                3871
ber01-VHDL13_DWMO_302100-2301302100-dsw--0-ia5     30-Jan-2023 21:30                4003
ber01-VHDL13_DWMO_302200-2301302200-dsw--0-ia5     30-Jan-2023 22:30                4003
ber01-VHDL13_DWMO_302300-2301302300-dsw--0-ia5     30-Jan-2023 23:30                3999
ber01-VHDL13_DWMO_310000-2301310000-dsw--0-ia5     31-Jan-2023 00:30                3999
ber01-VHDL13_DWMO_310100-2301310100-dsw--0-ia5     31-Jan-2023 01:30                3999
ber01-VHDL13_DWMO_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3999
ber01-VHDL13_DWMO_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3729
ber01-VHDL13_DWMO_310600-2301310600-dsw--0-ia5     31-Jan-2023 06:30                3729
ber01-VHDL13_DWMO_310700-2301310700-dsw--0-ia5     31-Jan-2023 07:30                3729
ber01-VHDL13_DWMO_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3528
ber01-VHDL13_DWMO_311000-2301311000-dsw--0-ia5     31-Jan-2023 10:30                3500
ber01-VHDL13_DWMO_311100-2301311100-dsw--0-ia5     31-Jan-2023 11:30                3500
ber01-VHDL13_DWMO_311200-2301311200-dsw--0-ia5     31-Jan-2023 12:30                3500
ber01-VHDL13_DWMO_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3491
ber01-VHDL13_DWMP_291400-2301291400-dsw--0-ia5     29-Jan-2023 14:30                4016
ber01-VHDL13_DWMP_291500-2301291500-dsw--0-ia5     29-Jan-2023 15:30                4016
ber01-VHDL13_DWMP_291600-2301291600-dsw--0-ia5     29-Jan-2023 16:30                4027
ber01-VHDL13_DWMP_291700-2301291700-dsw--0-ia5     29-Jan-2023 17:30                4027
ber01-VHDL13_DWMP_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3852
ber01-VHDL13_DWMP_292000-2301292000-dsw--0-ia5     29-Jan-2023 20:30                3852
ber01-VHDL13_DWMP_292100-2301292100-dsw--0-ia5     29-Jan-2023 21:30                3657
ber01-VHDL13_DWMP_292200-2301292200-dsw--0-ia5     29-Jan-2023 22:30                3657
ber01-VHDL13_DWMP_292300-2301292300-dsw--0-ia5     29-Jan-2023 23:30                4201
ber01-VHDL13_DWMP_300000-2301300000-dsw--0-ia5     30-Jan-2023 00:30                4201
ber01-VHDL13_DWMP_300100-2301300100-dsw--0-ia5     30-Jan-2023 01:30                4201
ber01-VHDL13_DWMP_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4201
ber01-VHDL13_DWMP_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4112
ber01-VHDL13_DWMP_300600-2301300600-dsw--0-ia5     30-Jan-2023 06:30                4112
ber01-VHDL13_DWMP_300700-2301300700-dsw--0-ia5     30-Jan-2023 07:30                4112
ber01-VHDL13_DWMP_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4423
ber01-VHDL13_DWMP_301000-2301301000-dsw--0-ia5     30-Jan-2023 10:30                4423
ber01-VHDL13_DWMP_301100-2301301100-dsw--0-ia5     30-Jan-2023 11:30                4537
ber01-VHDL13_DWMP_301200-2301301200-dsw--0-ia5     30-Jan-2023 12:30                4537
ber01-VHDL13_DWMP_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                4475
ber01-VHDL13_DWMP_301400-2301301400-dsw--0-ia5     30-Jan-2023 14:30                4475
ber01-VHDL13_DWMP_301500-2301301500-dsw--0-ia5     30-Jan-2023 15:30                4475
ber01-VHDL13_DWMP_301600-2301301600-dsw--0-ia5     30-Jan-2023 16:30                4475
ber01-VHDL13_DWMP_301700-2301301700-dsw--0-ia5     30-Jan-2023 17:30                4475
ber01-VHDL13_DWMP_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                4055
ber01-VHDL13_DWMP_302000-2301302000-dsw--0-ia5     30-Jan-2023 20:30                4055
ber01-VHDL13_DWMP_302100-2301302100-dsw--0-ia5     30-Jan-2023 21:30                4143
ber01-VHDL13_DWMP_302200-2301302200-dsw--0-ia5     30-Jan-2023 22:30                4143
ber01-VHDL13_DWMP_302300-2301302300-dsw--0-ia5     30-Jan-2023 23:30                4027
ber01-VHDL13_DWMP_310000-2301310000-dsw--0-ia5     31-Jan-2023 00:30                4027
ber01-VHDL13_DWMP_310100-2301310100-dsw--0-ia5     31-Jan-2023 01:30                4027
ber01-VHDL13_DWMP_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                4027
ber01-VHDL13_DWMP_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3755
ber01-VHDL13_DWMP_310600-2301310600-dsw--0-ia5     31-Jan-2023 06:30                3755
ber01-VHDL13_DWMP_310700-2301310700-dsw--0-ia5     31-Jan-2023 07:30                3755
ber01-VHDL13_DWMP_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3631
ber01-VHDL13_DWMP_311000-2301311000-dsw--0-ia5     31-Jan-2023 10:30                3631
ber01-VHDL13_DWMP_311100-2301311100-dsw--0-ia5     31-Jan-2023 11:30                3631
ber01-VHDL13_DWMP_311200-2301311200-dsw--0-ia5     31-Jan-2023 12:30                3631
ber01-VHDL13_DWMP_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3600
ber01-VHDL13_DWOG_291700-2301291700-dsw--0-ia5     29-Jan-2023 18:30                6846
ber01-VHDL13_DWOG_300100-2301300100-dsw--0-ia5     30-Jan-2023 02:45                6746
ber01-VHDL13_DWOG_300300-2301300300-dsw--0-ia5     30-Jan-2023 04:00                6746
ber01-VHDL13_DWOG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:15                5553
ber01-VHDL13_DWOG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:00                5223
ber01-VHDL13_DWOG_301700-2301301700-dsw--0-ia5     30-Jan-2023 18:30                4952
ber01-VHDL13_DWOG_310100-2301310100-dsw--0-ia5     31-Jan-2023 02:45                4916
ber01-VHDL13_DWOG_310300-2301310300-dsw--0-ia5     31-Jan-2023 04:00                4873
ber01-VHDL13_DWOG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:15                4824
ber01-VHDL13_DWOG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:00                5837
ber01-VHDL13_DWOH_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:28                4692
ber01-VHDL13_DWOH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:28                5084
ber01-VHDL13_DWOH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:28                4273
ber01-VHDL13_DWOH_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:58                4142
ber01-VHDL13_DWOH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:28                3945
ber01-VHDL13_DWOH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:28                3919
ber01-VHDL13_DWOH_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                3913
ber01-VHDL13_DWOH_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:28                3347
ber01-VHDL13_DWOH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:28                3038
ber01-VHDL13_DWOH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:28                3280
ber01-VHDL13_DWOH_310400-2301310400-dsw--0-ia5     31-Jan-2023 05:58                3284
ber01-VHDL13_DWOH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:28                3722
ber01-VHDL13_DWOH_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:02                3828
ber01-VHDL13_DWOH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:28                3787
ber01-VHDL13_DWOI_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:28                4787
ber01-VHDL13_DWOI_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:28                5115
ber01-VHDL13_DWOI_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:28                4175
ber01-VHDL13_DWOI_300400-2301300400-dsw--0-ia5     30-Jan-2023 05:58                4080
ber01-VHDL13_DWOI_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:28                3864
ber01-VHDL13_DWOI_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:28                3853
ber01-VHDL13_DWOI_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                3847
ber01-VHDL13_DWOI_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:28                3101
ber01-VHDL13_DWOI_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:28                3137
ber01-VHDL13_DWOI_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:28                3490
ber01-VHDL13_DWOI_310400-2301310400-dsw--0-ia5     31-Jan-2023 05:58                3613
ber01-VHDL13_DWOI_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:28                3785
ber01-VHDL13_DWOI_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:02                3779
ber01-VHDL13_DWOI_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:28                3568
ber01-VHDL13_DWPG_291430-2301291430-dsw--0-ia5     29-Jan-2023 14:30                3381
ber01-VHDL13_DWPG_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:30                3466
ber01-VHDL13_DWPG_291530-2301291530-dsw--0-ia5     29-Jan-2023 15:30                3381
ber01-VHDL13_DWPG_291730-2301291730-dsw--0-ia5     29-Jan-2023 17:30                3465
ber01-VHDL13_DWPG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3361
ber01-VHDL13_DWPG_291830-2301291830-dsw--0-ia5     29-Jan-2023 18:30                3465
ber01-VHDL13_DWPG_292030-2301292030-dsw--0-ia5     29-Jan-2023 20:30                3360
ber01-VHDL13_DWPG_292130-2301292130-dsw--0-ia5     29-Jan-2023 21:30                3360
ber01-VHDL13_DWPG_300130-2301300130-dsw--0-ia5     30-Jan-2023 01:30                3617
ber01-VHDL13_DWPG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                3618
ber01-VHDL13_DWPG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3134
ber01-VHDL13_DWPG_300630-2301300630-dsw--0-ia5     30-Jan-2023 06:30                3132
ber01-VHDL13_DWPG_300730-2301300730-dsw--0-ia5     30-Jan-2023 07:30                3132
ber01-VHDL13_DWPG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3092
ber01-VHDL13_DWPG_300830-2301300830-dsw--0-ia5     30-Jan-2023 08:30                3132
ber01-VHDL13_DWPG_301030-2301301030-dsw--0-ia5     30-Jan-2023 10:30                3091
ber01-VHDL13_DWPG_301130-2301301130-dsw--0-ia5     30-Jan-2023 11:30                3091
ber01-VHDL13_DWPG_301230-2301301230-dsw--0-ia5     30-Jan-2023 12:30                3072
ber01-VHDL13_DWPG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3258
ber01-VHDL13_DWPG_301430-2301301430-dsw--0-ia5     30-Jan-2023 14:30                3257
ber01-VHDL13_DWPG_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:30                3808
ber01-VHDL13_DWPG_301530-2301301530-dsw--0-ia5     30-Jan-2023 15:30                3257
ber01-VHDL13_DWPG_301730-2301301730-dsw--0-ia5     30-Jan-2023 17:30                3807
ber01-VHDL13_DWPG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3351
ber01-VHDL13_DWPG_301830-2301301830-dsw--0-ia5     30-Jan-2023 18:30                3807
ber01-VHDL13_DWPG_302030-2301302030-dsw--0-ia5     30-Jan-2023 20:30                3350
ber01-VHDL13_DWPG_302130-2301302130-dsw--0-ia5     30-Jan-2023 21:30                3350
ber01-VHDL13_DWPG_310130-2301310130-dsw--0-ia5     31-Jan-2023 01:30                3529
ber01-VHDL13_DWPG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3338
ber01-VHDL13_DWPG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3417
ber01-VHDL13_DWPG_310630-2301310630-dsw--0-ia5     31-Jan-2023 06:30                3415
ber01-VHDL13_DWPG_310730-2301310730-dsw--0-ia5     31-Jan-2023 07:30                3415
ber01-VHDL13_DWPG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3514
ber01-VHDL13_DWPG_310830-2301310830-dsw--0-ia5     31-Jan-2023 08:30                3415
ber01-VHDL13_DWPG_311030-2301311030-dsw--0-ia5     31-Jan-2023 10:30                3513
ber01-VHDL13_DWPG_311130-2301311130-dsw--0-ia5     31-Jan-2023 11:30                3513
ber01-VHDL13_DWPG_311230-2301311230-dsw--0-ia5     31-Jan-2023 12:30                3482
ber01-VHDL13_DWPG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3609
ber01-VHDL13_DWPH_291430-2301291430-dsw--0-ia5     29-Jan-2023 14:30                4077
ber01-VHDL13_DWPH_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:30                4064
ber01-VHDL13_DWPH_291530-2301291530-dsw--0-ia5     29-Jan-2023 15:30                4077
ber01-VHDL13_DWPH_291730-2301291730-dsw--0-ia5     29-Jan-2023 17:30                4064
ber01-VHDL13_DWPH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3661
ber01-VHDL13_DWPH_291830-2301291830-dsw--0-ia5     29-Jan-2023 18:30                4064
ber01-VHDL13_DWPH_292030-2301292030-dsw--0-ia5     29-Jan-2023 20:30                3661
ber01-VHDL13_DWPH_292130-2301292130-dsw--0-ia5     29-Jan-2023 21:30                3661
ber01-VHDL13_DWPH_300130-2301300130-dsw--0-ia5     30-Jan-2023 01:30                3912
ber01-VHDL13_DWPH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                3912
ber01-VHDL13_DWPH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3877
ber01-VHDL13_DWPH_300630-2301300630-dsw--0-ia5     30-Jan-2023 06:30                3877
ber01-VHDL13_DWPH_300730-2301300730-dsw--0-ia5     30-Jan-2023 07:30                3877
ber01-VHDL13_DWPH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3801
ber01-VHDL13_DWPH_300830-2301300830-dsw--0-ia5     30-Jan-2023 08:30                3877
ber01-VHDL13_DWPH_301030-2301301030-dsw--0-ia5     30-Jan-2023 10:30                3801
ber01-VHDL13_DWPH_301130-2301301130-dsw--0-ia5     30-Jan-2023 11:30                3801
ber01-VHDL13_DWPH_301230-2301301230-dsw--0-ia5     30-Jan-2023 12:30                3790
ber01-VHDL13_DWPH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                4088
ber01-VHDL13_DWPH_301430-2301301430-dsw--0-ia5     30-Jan-2023 14:30                4088
ber01-VHDL13_DWPH_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:30                4414
ber01-VHDL13_DWPH_301530-2301301530-dsw--0-ia5     30-Jan-2023 15:30                4088
ber01-VHDL13_DWPH_301730-2301301730-dsw--0-ia5     30-Jan-2023 17:30                4414
ber01-VHDL13_DWPH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                4308
ber01-VHDL13_DWPH_301830-2301301830-dsw--0-ia5     30-Jan-2023 18:30                4414
ber01-VHDL13_DWPH_302030-2301302030-dsw--0-ia5     30-Jan-2023 20:30                4308
ber01-VHDL13_DWPH_302130-2301302130-dsw--0-ia5     30-Jan-2023 21:30                4308
ber01-VHDL13_DWPH_310130-2301310130-dsw--0-ia5     31-Jan-2023 01:30                4428
ber01-VHDL13_DWPH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                4297
ber01-VHDL13_DWPH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                4319
ber01-VHDL13_DWPH_310630-2301310630-dsw--0-ia5     31-Jan-2023 06:30                4319
ber01-VHDL13_DWPH_310730-2301310730-dsw--0-ia5     31-Jan-2023 07:30                4319
ber01-VHDL13_DWPH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                4362
ber01-VHDL13_DWPH_310830-2301310830-dsw--0-ia5     31-Jan-2023 08:30                4319
ber01-VHDL13_DWPH_311030-2301311030-dsw--0-ia5     31-Jan-2023 10:30                4362
ber01-VHDL13_DWPH_311130-2301311130-dsw--0-ia5     31-Jan-2023 11:30                4362
ber01-VHDL13_DWPH_311230-2301311230-dsw--0-ia5     31-Jan-2023 12:30                4349
ber01-VHDL13_DWPH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                4469
ber01-VHDL13_DWSG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3520
ber01-VHDL13_DWSG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                3670
ber01-VHDL13_DWSG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3822
ber01-VHDL13_DWSG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3905
ber01-VHDL13_DWSG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3673
ber01-VHDL13_DWSG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3058
ber01-VHDL13_DWSG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3215
ber01-VHDL13_DWSG_310200_COR-2301310200-dsw--0-ia5 31-Jan-2023 04:51                3208
ber01-VHDL13_DWSG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3593
ber01-VHDL13_DWSG_310400_COR-2301310400-dsw--0-ia5 31-Jan-2023 06:22                3580
ber01-VHDL13_DWSG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3762
ber01-VHDL13_DWSG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                3720
ber01-VHDL13_DWSN_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:30                2887
ber01-VHDL13_DWSN_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                2812
ber01-VHDL13_DWSN_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                2826
ber01-VHDL13_DWSN_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                2884
ber01-VHDL13_DWSN_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3017
ber01-VHDL13_DWSN_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:30                2540
ber01-VHDL13_DWSN_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                2249
ber01-VHDL13_DWSN_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                2151
ber01-VHDL13_DWSN_310200_COR-2301310200-dsw--0-ia5 31-Jan-2023 05:32                2685
ber01-VHDL13_DWSN_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                2681
ber01-VHDL13_DWSN_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                2636
ber01-VHDL13_DWSO_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:30                3541
ber01-VHDL13_DWSO_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                3384
ber01-VHDL13_DWSO_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                3598
ber01-VHDL13_DWSO_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3673
ber01-VHDL13_DWSO_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3556
ber01-VHDL13_DWSO_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:30                3628
ber01-VHDL13_DWSO_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3053
ber01-VHDL13_DWSO_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3174
ber01-VHDL13_DWSO_310200_COR-2301310200-dsw--0-ia5 31-Jan-2023 05:32                3445
ber01-VHDL13_DWSO_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3441
ber01-VHDL13_DWSO_310400_COR-2301310400-dsw--0-ia5 31-Jan-2023 06:24                3425
ber01-VHDL13_DWSO_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3522
ber01-VHDL13_DWSP_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:30                3006
ber01-VHDL13_DWSP_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                2674
ber01-VHDL13_DWSP_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                2972
ber01-VHDL13_DWSP_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3165
ber01-VHDL13_DWSP_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3259
ber01-VHDL13_DWSP_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:30                2964
ber01-VHDL13_DWSP_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                2576
ber01-VHDL13_DWSP_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                2335
ber01-VHDL13_DWSP_310200_COR-2301310200-dsw--0-ia5 31-Jan-2023 05:32                3086
ber01-VHDL13_DWSP_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3082
ber01-VHDL13_DWSP_310400_COR-2301310400-dsw--0-ia5 31-Jan-2023 06:25                3069
ber01-VHDL13_DWSP_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                2976
ber01-VHDL17_DWOG_301200-2301301200-dsw--0-ia5     30-Jan-2023 12:05                3167
ber01-VHDL17_DWOG_311200-2301311200-dsw--0-ia5     31-Jan-2023 12:27                4368
ber01-VHDL20_DWHG_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:46                4179
ber01-VHDL20_DWHG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                3964
ber01-VHDL20_DWHG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4095
ber01-VHDL20_DWHG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4080
ber01-VHDL20_DWHG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4104
ber01-VHDL20_DWHG_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:45                3961
ber01-VHDL20_DWHG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3257
ber01-VHDL20_DWHG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3584
ber01-VHDL20_DWHG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3654
ber01-VHDL20_DWHG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                3898
ber01-VHDL20_DWHH_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:46                3262
ber01-VHDL20_DWHH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                3021
ber01-VHDL20_DWHH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                2915
ber01-VHDL20_DWHH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3115
ber01-VHDL20_DWHH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                3477
ber01-VHDL20_DWHH_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:45                3303
ber01-VHDL20_DWHH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                2785
ber01-VHDL20_DWHH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                2807
ber01-VHDL20_DWHH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3102
ber01-VHDL20_DWHH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                3091
pid-VHDL12_DWHG_300200-2301300200-dsw--0-ia5       30-Jan-2023 03:30                3099
pid-VHDL12_DWHG_300400-2301300400-dsw--0-ia5       30-Jan-2023 06:00                3106
pid-VHDL12_DWHG_310200-2301310200-dsw--0-ia5       31-Jan-2023 03:30                2817
pid-VHDL12_DWHG_310400-2301310400-dsw--0-ia5       31-Jan-2023 06:00                2816
pid-VHDL12_DWHH_300200-2301300200-dsw--0-ia5       30-Jan-2023 03:30                2350
pid-VHDL12_DWHH_300400-2301300400-dsw--0-ia5       30-Jan-2023 06:00                2367
pid-VHDL12_DWHH_310200-2301310200-dsw--0-ia5       31-Jan-2023 03:30                2303
pid-VHDL12_DWHH_310400-2301310400-dsw--0-ia5       31-Jan-2023 06:00                2356
pid-VHDL12_DWMG_291800-2301291800-dsw--0-ia5       29-Jan-2023 19:30                3313
pid-VHDL12_DWMG_300200-2301300200-dsw--0-ia5       30-Jan-2023 03:30                4065
pid-VHDL12_DWMG_300400-2301300400-dsw--0-ia5       30-Jan-2023 06:00                3768
pid-VHDL12_DWMG_300800-2301300800-dsw--0-ia5       30-Jan-2023 09:30                3919
pid-VHDL12_DWMG_301300-2301301300-dsw--0-ia5       30-Jan-2023 13:30                3807
pid-VHDL12_DWMG_301800-2301301800-dsw--0-ia5       30-Jan-2023 19:30                3670
pid-VHDL12_DWMG_310200-2301310200-dsw--0-ia5       31-Jan-2023 03:30                3706
pid-VHDL12_DWMG_310400-2301310400-dsw--0-ia5       31-Jan-2023 06:00                3415
pid-VHDL12_DWMG_310800-2301310800-dsw--0-ia5       31-Jan-2023 09:30                3102
pid-VHDL12_DWMG_311300-2301311300-dsw--0-ia5       31-Jan-2023 13:30                3073
pid-VHDL12_DWSG_300200-2301300200-dsw--0-ia5       30-Jan-2023 03:30                3099
pid-VHDL12_DWSG_310200-2301310200-dsw--0-ia5       31-Jan-2023 03:30                2813
swis2-VHDL20_DWEG_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:45                5406
swis2-VHDL20_DWEG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                5801
swis2-VHDL20_DWEG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4938
swis2-VHDL20_DWEG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:15                4776
swis2-VHDL20_DWEG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4979
swis2-VHDL20_DWEG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4556
swis2-VHDL20_DWEG_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                4550
swis2-VHDL20_DWEG_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:45                3984
swis2-VHDL20_DWEG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3560
swis2-VHDL20_DWEG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3753
swis2-VHDL20_DWEG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:15                3800
swis2-VHDL20_DWEG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4637
swis2-VHDL20_DWEG_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:01                4717
swis2-VHDL20_DWEG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4275
swis2-VHDL20_DWEH_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:45                5719
swis2-VHDL20_DWEH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                5915
swis2-VHDL20_DWEH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5260
swis2-VHDL20_DWEH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:15                5017
swis2-VHDL20_DWEH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                5092
swis2-VHDL20_DWEH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4727
swis2-VHDL20_DWEH_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                4720
swis2-VHDL20_DWEH_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:45                3864
swis2-VHDL20_DWEH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3587
swis2-VHDL20_DWEH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3833
swis2-VHDL20_DWEH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:15                3932
swis2-VHDL20_DWEH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4797
swis2-VHDL20_DWEH_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:01                4723
swis2-VHDL20_DWEH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4330
swis2-VHDL20_DWEI_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:45                5529
swis2-VHDL20_DWEI_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                5857
swis2-VHDL20_DWEI_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4748
swis2-VHDL20_DWEI_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:15                4627
swis2-VHDL20_DWEI_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4920
swis2-VHDL20_DWEI_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4403
swis2-VHDL20_DWEI_301300_COR-2301301300-dsw--0-ia5 30-Jan-2023 14:25                4397
swis2-VHDL20_DWEI_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:45                3648
swis2-VHDL20_DWEI_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3689
swis2-VHDL20_DWEI_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3964
swis2-VHDL20_DWEI_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:15                4161
swis2-VHDL20_DWEI_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4844
swis2-VHDL20_DWEI_310800_COR-2301310800-dsw--0-ia5 31-Jan-2023 10:01                4477
swis2-VHDL20_DWEI_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4088
swis2-VHDL20_DWHG_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:46                4179
swis2-VHDL20_DWHG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                3964
swis2-VHDL20_DWHG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4095
swis2-VHDL20_DWHG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4080
swis2-VHDL20_DWHG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4104
swis2-VHDL20_DWHG_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:45                3961
swis2-VHDL20_DWHG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3257
swis2-VHDL20_DWHG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3584
swis2-VHDL20_DWHG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3654
swis2-VHDL20_DWHG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                3898
swis2-VHDL20_DWHH_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:46                3262
swis2-VHDL20_DWHH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                3021
swis2-VHDL20_DWHH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                2915
swis2-VHDL20_DWHH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3115
swis2-VHDL20_DWHH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                3477
swis2-VHDL20_DWHH_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:45                3303
swis2-VHDL20_DWHH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                2785
swis2-VHDL20_DWHH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                2807
swis2-VHDL20_DWHH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3102
swis2-VHDL20_DWHH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                3091
swis2-VHDL20_DWLG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4264
swis2-VHDL20_DWLG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5375
swis2-VHDL20_DWLG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                5316
swis2-VHDL20_DWLG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                5516
swis2-VHDL20_DWLG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4318
swis2-VHDL20_DWLG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3793
swis2-VHDL20_DWLG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3675
swis2-VHDL20_DWLG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3901
swis2-VHDL20_DWLG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4485
swis2-VHDL20_DWLG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4254
swis2-VHDL20_DWLH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4781
swis2-VHDL20_DWLH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5367
swis2-VHDL20_DWLH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                5230
swis2-VHDL20_DWLH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4946
swis2-VHDL20_DWLH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4202
swis2-VHDL20_DWLH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3567
swis2-VHDL20_DWLH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3537
swis2-VHDL20_DWLH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3765
swis2-VHDL20_DWLH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4306
swis2-VHDL20_DWLH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4033
swis2-VHDL20_DWLI_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4138
swis2-VHDL20_DWLI_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5006
swis2-VHDL20_DWLI_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4909
swis2-VHDL20_DWLI_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4675
swis2-VHDL20_DWLI_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                3999
swis2-VHDL20_DWLI_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3474
swis2-VHDL20_DWLI_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3434
swis2-VHDL20_DWLI_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3498
swis2-VHDL20_DWLI_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4106
swis2-VHDL20_DWLI_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                3823
swis2-VHDL20_DWMG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4446
swis2-VHDL20_DWMG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5073
swis2-VHDL20_DWMG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4807
swis2-VHDL20_DWMG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                5156
swis2-VHDL20_DWMG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4843
swis2-VHDL20_DWMG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                4688
swis2-VHDL20_DWMG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                4610
swis2-VHDL20_DWMG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                4182
swis2-VHDL20_DWMG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4106
swis2-VHDL20_DWMG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                3840
swis2-VHDL20_DWMO_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4446
swis2-VHDL20_DWMO_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                5026
swis2-VHDL20_DWMO_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4708
swis2-VHDL20_DWMO_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4959
swis2-VHDL20_DWMO_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4774
swis2-VHDL20_DWMO_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                4343
swis2-VHDL20_DWMO_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                4544
swis2-VHDL20_DWMO_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                4154
swis2-VHDL20_DWMO_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4169
swis2-VHDL20_DWMO_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                3916
swis2-VHDL20_DWMP_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                4403
swis2-VHDL20_DWMP_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4628
swis2-VHDL20_DWMP_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4600
swis2-VHDL20_DWMP_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                5115
swis2-VHDL20_DWMP_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:45                4963
swis2-VHDL20_DWMP_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                4546
swis2-VHDL20_DWMP_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                4562
swis2-VHDL20_DWMP_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                4174
swis2-VHDL20_DWMP_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4296
swis2-VHDL20_DWMP_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:45                4022
swis2-VHDL20_DWPG_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:30                4149
swis2-VHDL20_DWPG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                4045
swis2-VHDL20_DWPG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4135
swis2-VHDL20_DWPG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                3444
swis2-VHDL20_DWPG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                3536
swis2-VHDL20_DWPG_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                3701
swis2-VHDL20_DWPG_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:30                4383
swis2-VHDL20_DWPG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                3927
swis2-VHDL20_DWPG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                3782
swis2-VHDL20_DWPG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                3727
swis2-VHDL20_DWPG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                3960
swis2-VHDL20_DWPG_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                4054
swis2-VHDL20_DWPH_291500-2301291500-dsw--0-ia5     29-Jan-2023 16:30                4512
swis2-VHDL20_DWPH_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:30                4109
swis2-VHDL20_DWPH_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:30                4225
swis2-VHDL20_DWPH_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:00                4189
swis2-VHDL20_DWPH_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:30                4245
swis2-VHDL20_DWPH_301300-2301301300-dsw--0-ia5     30-Jan-2023 13:30                4532
swis2-VHDL20_DWPH_301500-2301301500-dsw--0-ia5     30-Jan-2023 16:30                4989
swis2-VHDL20_DWPH_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:30                4883
swis2-VHDL20_DWPH_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:30                4740
swis2-VHDL20_DWPH_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:00                4631
swis2-VHDL20_DWPH_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:30                4808
swis2-VHDL20_DWPH_311300-2301311300-dsw--0-ia5     31-Jan-2023 13:30                4915
swis2-VHDL20_DWSG_291300-2301291300-dsw--0-ia5     29-Jan-2023 14:46                4080
swis2-VHDL20_DWSG_291800-2301291800-dsw--0-ia5     29-Jan-2023 19:45                3981
swis2-VHDL20_DWSG_300200-2301300200-dsw--0-ia5     30-Jan-2023 03:45                4101
swis2-VHDL20_DWSG_300400-2301300400-dsw--0-ia5     30-Jan-2023 06:15                4297
swis2-VHDL20_DWSG_300800-2301300800-dsw--0-ia5     30-Jan-2023 09:45                4560
swis2-VHDL20_DWSG_301300-2301301300-dsw--0-ia5     30-Jan-2023 14:45                4150
swis2-VHDL20_DWSG_301800-2301301800-dsw--0-ia5     30-Jan-2023 19:45                3532
swis2-VHDL20_DWSG_310200-2301310200-dsw--0-ia5     31-Jan-2023 03:45                3680
swis2-VHDL20_DWSG_310400-2301310400-dsw--0-ia5     31-Jan-2023 06:15                4065
swis2-VHDL20_DWSG_310800-2301310800-dsw--0-ia5     31-Jan-2023 09:45                4395
wst04-VHDL20_DWEG_291500-2301291500-omedes--0.pdf  29-Jan-2023 16:45              261995
wst04-VHDL20_DWEG_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              261918
wst04-VHDL20_DWEG_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              262104
wst04-VHDL20_DWEG_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:15              261508
wst04-VHDL20_DWEG_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              263263
wst04-VHDL20_DWEG_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              262237
wst04-VHDL20_DWEG_301300_COR-2301301300-omedes-..> 30-Jan-2023 14:25              262231
wst04-VHDL20_DWEG_301500-2301301500-omedes--0.pdf  30-Jan-2023 16:45              261651
wst04-VHDL20_DWEG_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              261353
wst04-VHDL20_DWEG_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              262091
wst04-VHDL20_DWEG_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:15              261029
wst04-VHDL20_DWEG_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              259023
wst04-VHDL20_DWEG_310800_COR-2301310800-omedes-..> 31-Jan-2023 10:02              259035
wst04-VHDL20_DWEG_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              258267
wst04-VHDL20_DWEH_291500-2301291500-omedes--0.pdf  29-Jan-2023 16:45              260670
wst04-VHDL20_DWEH_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              260643
wst04-VHDL20_DWEH_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              260738
wst04-VHDL20_DWEH_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:15              260085
wst04-VHDL20_DWEH_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              264128
wst04-VHDL20_DWEH_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              263317
wst04-VHDL20_DWEH_301300_COR-2301301300-omedes-..> 30-Jan-2023 14:25              263325
wst04-VHDL20_DWEH_301500-2301301500-omedes--0.pdf  30-Jan-2023 16:45              262330
wst04-VHDL20_DWEH_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              262202
wst04-VHDL20_DWEH_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              263329
wst04-VHDL20_DWEH_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:15              262296
wst04-VHDL20_DWEH_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              262058
wst04-VHDL20_DWEH_310800_COR-2301310800-omedes-..> 31-Jan-2023 10:01              261903
wst04-VHDL20_DWEH_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              261245
wst04-VHDL20_DWEI_291500-2301291500-omedes--0.pdf  29-Jan-2023 16:45              362800
wst04-VHDL20_DWEI_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              362838
wst04-VHDL20_DWEI_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              361633
wst04-VHDL20_DWEI_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:15              361435
wst04-VHDL20_DWEI_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              360765
wst04-VHDL20_DWEI_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              359394
wst04-VHDL20_DWEI_301300_COR-2301301300-omedes-..> 30-Jan-2023 14:25              359413
wst04-VHDL20_DWEI_301500-2301301500-omedes--0.pdf  30-Jan-2023 16:45              358177
wst04-VHDL20_DWEI_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              358816
wst04-VHDL20_DWEI_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              359119
wst04-VHDL20_DWEI_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:15              358629
wst04-VHDL20_DWEI_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              351719
wst04-VHDL20_DWEI_310800_COR-2301310800-omedes-..> 31-Jan-2023 10:01              350855
wst04-VHDL20_DWEI_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              350080
wst04-VHDL20_DWHG_291300-2301291300-oflxs888--0..> 29-Jan-2023 14:46              354873
wst04-VHDL20_DWHG_291800-2301291800-oflxs888--0..> 29-Jan-2023 19:45              354535
wst04-VHDL20_DWHG_300200-2301300200-oflxs888--0..> 30-Jan-2023 03:45              354436
wst04-VHDL20_DWHG_300400-2301300400-oflxs888--0..> 30-Jan-2023 06:00              354395
wst04-VHDL20_DWHG_300800-2301300800-oflxs888--0..> 30-Jan-2023 09:45              365807
wst04-VHDL20_DWHG_301300-2301301300-oflxs888--0..> 30-Jan-2023 14:45              364934
wst04-VHDL20_DWHG_301800-2301301800-oflxs888--0..> 30-Jan-2023 19:45              363969
wst04-VHDL20_DWHG_310200-2301310200-oflxs888--0..> 31-Jan-2023 03:45              364190
wst04-VHDL20_DWHG_310400-2301310400-oflxs888--0..> 31-Jan-2023 06:00              364194
wst04-VHDL20_DWHG_310800-2301310800-oflxs888--0..> 31-Jan-2023 09:45              359964
wst04-VHDL20_DWHH_291300-2301291300-oflxs888--0..> 29-Jan-2023 14:46              358864
wst04-VHDL20_DWHH_291800-2301291800-oflxs888--0..> 29-Jan-2023 19:45              358558
wst04-VHDL20_DWHH_300200-2301300200-oflxs888--0..> 30-Jan-2023 03:45              358656
wst04-VHDL20_DWHH_300400-2301300400-oflxs888--0..> 30-Jan-2023 06:00              358723
wst04-VHDL20_DWHH_300800-2301300800-oflxs888--0..> 30-Jan-2023 09:45              348858
wst04-VHDL20_DWHH_301300-2301301300-oflxs888--0..> 30-Jan-2023 14:45              348383
wst04-VHDL20_DWHH_301800-2301301800-oflxs888--0..> 30-Jan-2023 19:45              347664
wst04-VHDL20_DWHH_310200-2301310200-oflxs888--0..> 31-Jan-2023 03:45              347866
wst04-VHDL20_DWHH_310400-2301310400-oflxs888--0..> 31-Jan-2023 06:00              348336
wst04-VHDL20_DWHH_310800-2301310800-oflxs888--0..> 31-Jan-2023 09:45              356399
wst04-VHDL20_DWLG_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:40              342364
wst04-VHDL20_DWLG_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:40              343536
wst04-VHDL20_DWLG_300400-2301300400-omedes--0.pdf  30-Jan-2023 05:59              343465
wst04-VHDL20_DWLG_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:40              355350
wst04-VHDL20_DWLG_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:40              352985
wst04-VHDL20_DWLG_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:40              352497
wst04-VHDL20_DWLG_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:40              352635
wst04-VHDL20_DWLG_310400-2301310400-omedes--0.pdf  31-Jan-2023 05:59              352583
wst04-VHDL20_DWLG_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:40              341243
wst04-VHDL20_DWLG_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:40              340705
wst04-VHDL20_DWLH_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:40              341198
wst04-VHDL20_DWLH_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:40              341909
wst04-VHDL20_DWLH_300400-2301300400-omedes--0.pdf  30-Jan-2023 05:59              341840
wst04-VHDL20_DWLH_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:40              346512
wst04-VHDL20_DWLH_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:40              344856
wst04-VHDL20_DWLH_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:40              343874
wst04-VHDL20_DWLH_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:40              343875
wst04-VHDL20_DWLH_310400-2301310400-omedes--0.pdf  31-Jan-2023 05:59              344217
wst04-VHDL20_DWLH_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:40              344392
wst04-VHDL20_DWLH_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:40              343289
wst04-VHDL20_DWLI_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:40              342564
wst04-VHDL20_DWLI_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:40              343696
wst04-VHDL20_DWLI_300400-2301300400-omedes--0.pdf  30-Jan-2023 05:59              343672
wst04-VHDL20_DWLI_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:40              352070
wst04-VHDL20_DWLI_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:40              350371
wst04-VHDL20_DWLI_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:40              349912
wst04-VHDL20_DWLI_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:40              349878
wst04-VHDL20_DWLI_310400-2301310400-omedes--0.pdf  31-Jan-2023 05:59              349717
wst04-VHDL20_DWLI_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:40              341087
wst04-VHDL20_DWLI_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:40              340536
wst04-VHDL20_DWMG_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              524079
wst04-VHDL20_DWMG_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              525667
wst04-VHDL20_DWMG_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:00              525419
wst04-VHDL20_DWMG_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              537092
wst04-VHDL20_DWMG_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              535984
wst04-VHDL20_DWMG_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              536519
wst04-VHDL20_DWMG_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              535598
wst04-VHDL20_DWMG_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:00              535266
wst04-VHDL20_DWMG_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              540082
wst04-VHDL20_DWMG_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              539726
wst04-VHDL20_DWMO_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              427599
wst04-VHDL20_DWMO_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              428353
wst04-VHDL20_DWMO_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:00              428774
wst04-VHDL20_DWMO_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              444214
wst04-VHDL20_DWMO_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              443865
wst04-VHDL20_DWMO_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              443749
wst04-VHDL20_DWMO_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              442972
wst04-VHDL20_DWMO_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:00              443297
wst04-VHDL20_DWMO_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              440079
wst04-VHDL20_DWMO_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              439922
wst04-VHDL20_DWMP_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              540601
wst04-VHDL20_DWMP_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              539999
wst04-VHDL20_DWMP_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:00              541841
wst04-VHDL20_DWMP_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              543381
wst04-VHDL20_DWMP_301300-2301301300-omedes--0.pdf  30-Jan-2023 13:45              542987
wst04-VHDL20_DWMP_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              543043
wst04-VHDL20_DWMP_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              539976
wst04-VHDL20_DWMP_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:00              540937
wst04-VHDL20_DWMP_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              547062
wst04-VHDL20_DWMP_311300-2301311300-omedes--0.pdf  31-Jan-2023 13:45              546164
wst04-VHDL20_DWPG_291500-2301291500-oflxs892--0..> 29-Jan-2023 16:30              355981
wst04-VHDL20_DWPG_291800-2301291800-oflxs892--0..> 29-Jan-2023 19:30              355560
wst04-VHDL20_DWPG_300200-2301300200-oflxs892--0..> 30-Jan-2023 03:30              355937
wst04-VHDL20_DWPG_300400-2301300400-oflxs892--0..> 30-Jan-2023 06:00              354575
wst04-VHDL20_DWPG_300800-2301300800-oflxs892--0..> 30-Jan-2023 09:30              413677
wst04-VHDL20_DWPG_301300-2301301300-oflxs892--0..> 30-Jan-2023 13:30              368846
wst04-VHDL20_DWPG_301500-2301301500-oflxs892--0..> 30-Jan-2023 16:30              369768
wst04-VHDL20_DWPG_301800-2301301800-oflxs892--0..> 30-Jan-2023 19:30              369119
wst04-VHDL20_DWPG_310200-2301310200-oflxs892--0..> 31-Jan-2023 03:30              368721
wst04-VHDL20_DWPG_310400-2301310400-oflxs892--0..> 31-Jan-2023 06:00              368715
wst04-VHDL20_DWPG_310800-2301310800-oflxs892--0..> 31-Jan-2023 09:30              407175
wst04-VHDL20_DWPG_311300-2301311300-oflxs892--0..> 31-Jan-2023 13:30              362159
wst04-VHDL20_DWPH_291500-2301291500-oflxs892--0..> 29-Jan-2023 16:30              263304
wst04-VHDL20_DWPH_291800-2301291800-oflxs892--0..> 29-Jan-2023 19:30              307445
wst04-VHDL20_DWPH_300200-2301300200-oflxs892--0..> 30-Jan-2023 03:30              262892
wst04-VHDL20_DWPH_300400-2301300400-oflxs892--0..> 30-Jan-2023 06:00              262886
wst04-VHDL20_DWPH_300800-2301300800-oflxs892--0..> 30-Jan-2023 09:30              303681
wst04-VHDL20_DWPH_301300-2301301300-oflxs892--0..> 30-Jan-2023 13:30              259188
wst04-VHDL20_DWPH_301500-2301301500-oflxs892--0..> 30-Jan-2023 16:30              259820
wst04-VHDL20_DWPH_301800-2301301800-oflxs892--0..> 30-Jan-2023 19:30              304395
wst04-VHDL20_DWPH_310200-2301310200-oflxs892--0..> 31-Jan-2023 03:30              259986
wst04-VHDL20_DWPH_310400-2301310400-oflxs892--0..> 31-Jan-2023 06:00              259110
wst04-VHDL20_DWPH_310800-2301310800-oflxs892--0..> 31-Jan-2023 09:30              308174
wst04-VHDL20_DWPH_311300-2301311300-oflxs892--0..> 31-Jan-2023 13:30              263643
wst04-VHDL20_DWSG_291300-2301291300-omedes--0.pdf  29-Jan-2023 14:46              345860
wst04-VHDL20_DWSG_291800-2301291800-omedes--0.pdf  29-Jan-2023 19:45              345876
wst04-VHDL20_DWSG_300200-2301300200-omedes--0.pdf  30-Jan-2023 03:45              346059
wst04-VHDL20_DWSG_300400-2301300400-omedes--0.pdf  30-Jan-2023 06:15              346299
wst04-VHDL20_DWSG_300800-2301300800-omedes--0.pdf  30-Jan-2023 09:45              346761
wst04-VHDL20_DWSG_301300-2301301300-omedes--0.pdf  30-Jan-2023 14:45              346080
wst04-VHDL20_DWSG_301800-2301301800-omedes--0.pdf  30-Jan-2023 19:45              344973
wst04-VHDL20_DWSG_310200-2301310200-omedes--0.pdf  31-Jan-2023 03:45              345165
wst04-VHDL20_DWSG_310400-2301310400-omedes--0.pdf  31-Jan-2023 06:15              346279
wst04-VHDL20_DWSG_310800-2301310800-omedes--0.pdf  31-Jan-2023 09:45              351189