Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_160600                                 16-Jun-2021 12:48                5263
FPDL13_DWMZ_170600                                 17-Jun-2021 09:41                5213
FPDL13_DWMZ_180600                                 18-Jun-2021 08:54                2944
SXDL31_DWAV_161800                                 16-Jun-2021 17:06               13327
SXDL31_DWAV_170800                                 17-Jun-2021 08:01               12083
SXDL31_DWAV_171800                                 17-Jun-2021 17:12               12844
SXDL31_DWAV_180800                                 18-Jun-2021 07:10               10779
SXDL31_DWAV_LATEST                                 18-Jun-2021 07:10               10779
SXDL33_DWAV_160000                                 16-Jun-2021 11:12                9324
SXDL33_DWAV_170000                                 17-Jun-2021 09:34                6997
SXDL33_DWAV_LATEST                                 17-Jun-2021 09:34                6997
ber01-FWDL39_DWMS_161230-2106161230-dsw--0-ia5     16-Jun-2021 12:28                 875
ber01-FWDL39_DWMS_171230-2106171230-dsw--0-ia5     17-Jun-2021 12:27                1031
ber01-VHDL13_DWEH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:28                3571
ber01-VHDL13_DWEH_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:28                3441
ber01-VHDL13_DWEH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:28                3362
ber01-VHDL13_DWEH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:28                3654
ber01-VHDL13_DWEH_170400-2106170400-dsw--0-ia5     17-Jun-2021 04:58                4109
ber01-VHDL13_DWEH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:28                4805
ber01-VHDL13_DWEH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:28                4795
ber01-VHDL13_DWEH_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:28                4741
ber01-VHDL13_DWEH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:28                4063
ber01-VHDL13_DWEH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:28                3882
ber01-VHDL13_DWEH_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:58                3817
ber01-VHDL13_DWEH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:28                3570
ber01-VHDL13_DWHG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2816
ber01-VHDL13_DWHG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2932
ber01-VHDL13_DWHG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                3023
ber01-VHDL13_DWHG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                3075
ber01-VHDL13_DWHG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                3075
ber01-VHDL13_DWHG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                3449
ber01-VHDL13_DWHG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2662
ber01-VHDL13_DWHG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                3040
ber01-VHDL13_DWHG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3036
ber01-VHDL13_DWHG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3027
ber01-VHDL13_DWHH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2793
ber01-VHDL13_DWHH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2694
ber01-VHDL13_DWHH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2630
ber01-VHDL13_DWHH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2612
ber01-VHDL13_DWHH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2612
ber01-VHDL13_DWHH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                3101
ber01-VHDL13_DWHH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2575
ber01-VHDL13_DWHH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2906
ber01-VHDL13_DWHH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                2946
ber01-VHDL13_DWHH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                2618
ber01-VHDL13_DWLG_160933-2106160933-dsw--0-ia5     16-Jun-2021 09:33                2035
ber01-VHDL13_DWLG_161033-2106161033-dsw--0-ia5     16-Jun-2021 10:33                2035
ber01-VHDL13_DWLG_161133-2106161133-dsw--0-ia5     16-Jun-2021 11:33                1958
ber01-VHDL13_DWLG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2112
ber01-VHDL13_DWLG_161333-2106161333-dsw--0-ia5     16-Jun-2021 13:33                2128
ber01-VHDL13_DWLG_161433-2106161433-dsw--0-ia5     16-Jun-2021 14:33                2128
ber01-VHDL13_DWLG_161533-2106161533-dsw--0-ia5     16-Jun-2021 15:33                2175
ber01-VHDL13_DWLG_161633-2106161633-dsw--0-ia5     16-Jun-2021 16:33                2175
ber01-VHDL13_DWLG_161733-2106161733-dsw--0-ia5     16-Jun-2021 17:33                2220
ber01-VHDL13_DWLG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1915
ber01-VHDL13_DWLG_161933-2106161933-dsw--0-ia5     16-Jun-2021 19:33                1923
ber01-VHDL13_DWLG_162033-2106162033-dsw--0-ia5     16-Jun-2021 20:33                1923
ber01-VHDL13_DWLG_170033-2106170033-dsw--0-ia5     17-Jun-2021 00:33                2189
ber01-VHDL13_DWLG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2111
ber01-VHDL13_DWLG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2098
ber01-VHDL13_DWLG_170533-2106170533-dsw--0-ia5     17-Jun-2021 05:33                2101
ber01-VHDL13_DWLG_170633-2106170633-dsw--0-ia5     17-Jun-2021 06:33                2101
ber01-VHDL13_DWLG_170733-2106170733-dsw--0-ia5     17-Jun-2021 07:33                2111
ber01-VHDL13_DWLG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2121
ber01-VHDL13_DWLG_170933-2106170933-dsw--0-ia5     17-Jun-2021 09:33                2127
ber01-VHDL13_DWLG_171033-2106171033-dsw--0-ia5     17-Jun-2021 10:33                2098
ber01-VHDL13_DWLG_171133-2106171133-dsw--0-ia5     17-Jun-2021 11:33                2098
ber01-VHDL13_DWLG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2095
ber01-VHDL13_DWLG_171333-2106171333-dsw--0-ia5     17-Jun-2021 13:33                2094
ber01-VHDL13_DWLG_171433-2106171433-dsw--0-ia5     17-Jun-2021 14:33                1986
ber01-VHDL13_DWLG_171533-2106171533-dsw--0-ia5     17-Jun-2021 15:33                1986
ber01-VHDL13_DWLG_171633-2106171633-dsw--0-ia5     17-Jun-2021 16:33                1986
ber01-VHDL13_DWLG_171733-2106171733-dsw--0-ia5     17-Jun-2021 17:33                1986
ber01-VHDL13_DWLG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                1886
ber01-VHDL13_DWLG_171933-2106171933-dsw--0-ia5     17-Jun-2021 19:33                1889
ber01-VHDL13_DWLG_172033-2106172033-dsw--0-ia5     17-Jun-2021 20:33                1889
ber01-VHDL13_DWLG_180033-2106180033-dsw--0-ia5     18-Jun-2021 00:33                2217
ber01-VHDL13_DWLG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2342
ber01-VHDL13_DWLG_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:59                2301
ber01-VHDL13_DWLG_180533-2106180533-dsw--0-ia5     18-Jun-2021 05:33                2304
ber01-VHDL13_DWLG_180633-2106180633-dsw--0-ia5     18-Jun-2021 06:33                2766
ber01-VHDL13_DWLG_180733-2106180733-dsw--0-ia5     18-Jun-2021 07:33                2764
ber01-VHDL13_DWLG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                2773
ber01-VHDL13_DWLH_160933-2106160933-dsw--0-ia5     16-Jun-2021 09:33                2241
ber01-VHDL13_DWLH_161033-2106161033-dsw--0-ia5     16-Jun-2021 10:33                2241
ber01-VHDL13_DWLH_161133-2106161133-dsw--0-ia5     16-Jun-2021 11:33                2147
ber01-VHDL13_DWLH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2157
ber01-VHDL13_DWLH_161333-2106161333-dsw--0-ia5     16-Jun-2021 13:33                2253
ber01-VHDL13_DWLH_161433-2106161433-dsw--0-ia5     16-Jun-2021 14:33                2253
ber01-VHDL13_DWLH_161533-2106161533-dsw--0-ia5     16-Jun-2021 15:33                2253
ber01-VHDL13_DWLH_161633-2106161633-dsw--0-ia5     16-Jun-2021 16:33                2253
ber01-VHDL13_DWLH_161733-2106161733-dsw--0-ia5     16-Jun-2021 17:33                2155
ber01-VHDL13_DWLH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1832
ber01-VHDL13_DWLH_161933-2106161933-dsw--0-ia5     16-Jun-2021 19:33                1843
ber01-VHDL13_DWLH_162033-2106162033-dsw--0-ia5     16-Jun-2021 20:33                1843
ber01-VHDL13_DWLH_170033-2106170033-dsw--0-ia5     17-Jun-2021 00:33                2110
ber01-VHDL13_DWLH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2045
ber01-VHDL13_DWLH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2146
ber01-VHDL13_DWLH_170533-2106170533-dsw--0-ia5     17-Jun-2021 05:33                2152
ber01-VHDL13_DWLH_170633-2106170633-dsw--0-ia5     17-Jun-2021 06:33                2152
ber01-VHDL13_DWLH_170733-2106170733-dsw--0-ia5     17-Jun-2021 07:33                2180
ber01-VHDL13_DWLH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2174
ber01-VHDL13_DWLH_170933-2106170933-dsw--0-ia5     17-Jun-2021 09:33                2151
ber01-VHDL13_DWLH_171033-2106171033-dsw--0-ia5     17-Jun-2021 10:33                2151
ber01-VHDL13_DWLH_171133-2106171133-dsw--0-ia5     17-Jun-2021 11:33                2151
ber01-VHDL13_DWLH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2145
ber01-VHDL13_DWLH_171333-2106171333-dsw--0-ia5     17-Jun-2021 13:33                2151
ber01-VHDL13_DWLH_171433-2106171433-dsw--0-ia5     17-Jun-2021 14:33                2047
ber01-VHDL13_DWLH_171533-2106171533-dsw--0-ia5     17-Jun-2021 15:33                2047
ber01-VHDL13_DWLH_171633-2106171633-dsw--0-ia5     17-Jun-2021 16:33                2047
ber01-VHDL13_DWLH_171733-2106171733-dsw--0-ia5     17-Jun-2021 17:33                2047
ber01-VHDL13_DWLH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                1940
ber01-VHDL13_DWLH_171933-2106171933-dsw--0-ia5     17-Jun-2021 19:33                1946
ber01-VHDL13_DWLH_172033-2106172033-dsw--0-ia5     17-Jun-2021 20:33                1946
ber01-VHDL13_DWLH_180033-2106180033-dsw--0-ia5     18-Jun-2021 00:33                2263
ber01-VHDL13_DWLH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2771
ber01-VHDL13_DWLH_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:59                2928
ber01-VHDL13_DWLH_180533-2106180533-dsw--0-ia5     18-Jun-2021 05:33                2934
ber01-VHDL13_DWLH_180633-2106180633-dsw--0-ia5     18-Jun-2021 06:33                3313
ber01-VHDL13_DWLH_180733-2106180733-dsw--0-ia5     18-Jun-2021 07:33                3310
ber01-VHDL13_DWLH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3319
ber01-VHDL13_DWLI_160933-2106160933-dsw--0-ia5     16-Jun-2021 09:33                2268
ber01-VHDL13_DWLI_161033-2106161033-dsw--0-ia5     16-Jun-2021 10:33                2268
ber01-VHDL13_DWLI_161133-2106161133-dsw--0-ia5     16-Jun-2021 11:33                2197
ber01-VHDL13_DWLI_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2221
ber01-VHDL13_DWLI_161333-2106161333-dsw--0-ia5     16-Jun-2021 13:33                2238
ber01-VHDL13_DWLI_161433-2106161433-dsw--0-ia5     16-Jun-2021 14:33                2238
ber01-VHDL13_DWLI_161533-2106161533-dsw--0-ia5     16-Jun-2021 15:33                2238
ber01-VHDL13_DWLI_161633-2106161633-dsw--0-ia5     16-Jun-2021 16:33                2238
ber01-VHDL13_DWLI_161733-2106161733-dsw--0-ia5     16-Jun-2021 17:33                2147
ber01-VHDL13_DWLI_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1888
ber01-VHDL13_DWLI_161933-2106161933-dsw--0-ia5     16-Jun-2021 19:33                1896
ber01-VHDL13_DWLI_162033-2106162033-dsw--0-ia5     16-Jun-2021 20:33                1896
ber01-VHDL13_DWLI_170033-2106170033-dsw--0-ia5     17-Jun-2021 00:33                2162
ber01-VHDL13_DWLI_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2052
ber01-VHDL13_DWLI_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2155
ber01-VHDL13_DWLI_170533-2106170533-dsw--0-ia5     17-Jun-2021 05:33                2158
ber01-VHDL13_DWLI_170633-2106170633-dsw--0-ia5     17-Jun-2021 06:33                2158
ber01-VHDL13_DWLI_170733-2106170733-dsw--0-ia5     17-Jun-2021 07:33                2184
ber01-VHDL13_DWLI_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2181
ber01-VHDL13_DWLI_170933-2106170933-dsw--0-ia5     17-Jun-2021 09:33                2184
ber01-VHDL13_DWLI_171033-2106171033-dsw--0-ia5     17-Jun-2021 10:33                2155
ber01-VHDL13_DWLI_171133-2106171133-dsw--0-ia5     17-Jun-2021 11:33                2155
ber01-VHDL13_DWLI_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2152
ber01-VHDL13_DWLI_171333-2106171333-dsw--0-ia5     17-Jun-2021 13:33                2155
ber01-VHDL13_DWLI_171433-2106171433-dsw--0-ia5     17-Jun-2021 14:33                2047
ber01-VHDL13_DWLI_171533-2106171533-dsw--0-ia5     17-Jun-2021 15:33                2047
ber01-VHDL13_DWLI_171633-2106171633-dsw--0-ia5     17-Jun-2021 16:33                2047
ber01-VHDL13_DWLI_171733-2106171733-dsw--0-ia5     17-Jun-2021 17:33                2047
ber01-VHDL13_DWLI_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                1943
ber01-VHDL13_DWLI_171933-2106171933-dsw--0-ia5     17-Jun-2021 19:33                1946
ber01-VHDL13_DWLI_172033-2106172033-dsw--0-ia5     17-Jun-2021 20:33                1946
ber01-VHDL13_DWLI_180033-2106180033-dsw--0-ia5     18-Jun-2021 00:33                2268
ber01-VHDL13_DWLI_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2724
ber01-VHDL13_DWLI_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:59                2798
ber01-VHDL13_DWLI_180533-2106180533-dsw--0-ia5     18-Jun-2021 05:33                2801
ber01-VHDL13_DWLI_180633-2106180633-dsw--0-ia5     18-Jun-2021 06:33                3147
ber01-VHDL13_DWLI_180733-2106180733-dsw--0-ia5     18-Jun-2021 07:33                3144
ber01-VHDL13_DWLI_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3156
ber01-VHDL13_DWMG_161000-2106161000-dsw--0-ia5     16-Jun-2021 10:30                2232
ber01-VHDL13_DWMG_161100-2106161100-dsw--0-ia5     16-Jun-2021 11:30                2232
ber01-VHDL13_DWMG_161200-2106161200-dsw--0-ia5     16-Jun-2021 12:30                2332
ber01-VHDL13_DWMG_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2186
ber01-VHDL13_DWMG_161400-2106161400-dsw--0-ia5     16-Jun-2021 14:30                2186
ber01-VHDL13_DWMG_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                2186
ber01-VHDL13_DWMG_161600-2106161600-dsw--0-ia5     16-Jun-2021 16:30                2186
ber01-VHDL13_DWMG_161700-2106161700-dsw--0-ia5     16-Jun-2021 17:30                1934
ber01-VHDL13_DWMG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1934
ber01-VHDL13_DWMG_161900-2106161900-dsw--0-ia5     16-Jun-2021 19:30                2066
ber01-VHDL13_DWMG_162000-2106162000-dsw--0-ia5     16-Jun-2021 20:30                2066
ber01-VHDL13_DWMG_162100-2106162100-dsw--0-ia5     16-Jun-2021 21:30                2066
ber01-VHDL13_DWMG_162200-2106162200-dsw--0-ia5     16-Jun-2021 22:30                2326
ber01-VHDL13_DWMG_162300-2106162300-dsw--0-ia5     16-Jun-2021 23:30                2326
ber01-VHDL13_DWMG_170000-2106170000-dsw--0-ia5     17-Jun-2021 00:30                2326
ber01-VHDL13_DWMG_170100-2106170100-dsw--0-ia5     17-Jun-2021 01:30                2326
ber01-VHDL13_DWMG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2361
ber01-VHDL13_DWMG_170300-2106170300-dsw--0-ia5     17-Jun-2021 03:30                2361
ber01-VHDL13_DWMG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2357
ber01-VHDL13_DWMG_170500-2106170500-dsw--0-ia5     17-Jun-2021 05:30                2357
ber01-VHDL13_DWMG_170600-2106170600-dsw--0-ia5     17-Jun-2021 06:30                2203
ber01-VHDL13_DWMG_170700-2106170700-dsw--0-ia5     17-Jun-2021 07:30                2345
ber01-VHDL13_DWMG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2345
ber01-VHDL13_DWMG_170900-2106170900-dsw--0-ia5     17-Jun-2021 09:30                2345
ber01-VHDL13_DWMG_171000-2106171000-dsw--0-ia5     17-Jun-2021 10:30                2345
ber01-VHDL13_DWMG_171100-2106171100-dsw--0-ia5     17-Jun-2021 11:30                2612
ber01-VHDL13_DWMG_171200-2106171200-dsw--0-ia5     17-Jun-2021 12:30                2612
ber01-VHDL13_DWMG_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                2675
ber01-VHDL13_DWMG_171400-2106171400-dsw--0-ia5     17-Jun-2021 14:30                2675
ber01-VHDL13_DWMG_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2675
ber01-VHDL13_DWMG_171600-2106171600-dsw--0-ia5     17-Jun-2021 16:30                2675
ber01-VHDL13_DWMG_171700-2106171700-dsw--0-ia5     17-Jun-2021 17:30                2430
ber01-VHDL13_DWMG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2430
ber01-VHDL13_DWMG_171900-2106171900-dsw--0-ia5     17-Jun-2021 19:30                2430
ber01-VHDL13_DWMG_172000-2106172000-dsw--0-ia5     17-Jun-2021 20:30                2494
ber01-VHDL13_DWMG_172100-2106172100-dsw--0-ia5     17-Jun-2021 21:30                2494
ber01-VHDL13_DWMG_172200-2106172200-dsw--0-ia5     17-Jun-2021 22:30                2744
ber01-VHDL13_DWMG_172300-2106172300-dsw--0-ia5     17-Jun-2021 23:30                2744
ber01-VHDL13_DWMG_180000-2106180000-dsw--0-ia5     18-Jun-2021 00:30                2744
ber01-VHDL13_DWMG_180100-2106180100-dsw--0-ia5     18-Jun-2021 01:30                2744
ber01-VHDL13_DWMG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2987
ber01-VHDL13_DWMG_180300-2106180300-dsw--0-ia5     18-Jun-2021 03:30                2987
ber01-VHDL13_DWMG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3028
ber01-VHDL13_DWMG_180500-2106180500-dsw--0-ia5     18-Jun-2021 05:30                3028
ber01-VHDL13_DWMG_180600-2106180600-dsw--0-ia5     18-Jun-2021 06:30                3028
ber01-VHDL13_DWMG_180700-2106180700-dsw--0-ia5     18-Jun-2021 07:30                3028
ber01-VHDL13_DWMG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3234
ber01-VHDL13_DWMG_180900-2106180900-dsw--0-ia5     18-Jun-2021 09:30                3234
ber01-VHDL13_DWMO_161000-2106161000-dsw--0-ia5     16-Jun-2021 10:30                2174
ber01-VHDL13_DWMO_161100-2106161100-dsw--0-ia5     16-Jun-2021 11:30                2174
ber01-VHDL13_DWMO_161200-2106161200-dsw--0-ia5     16-Jun-2021 12:30                2174
ber01-VHDL13_DWMO_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2108
ber01-VHDL13_DWMO_161400-2106161400-dsw--0-ia5     16-Jun-2021 14:30                2108
ber01-VHDL13_DWMO_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                2108
ber01-VHDL13_DWMO_161600-2106161600-dsw--0-ia5     16-Jun-2021 16:30                2108
ber01-VHDL13_DWMO_161700-2106161700-dsw--0-ia5     16-Jun-2021 17:30                1802
ber01-VHDL13_DWMO_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1802
ber01-VHDL13_DWMO_161900-2106161900-dsw--0-ia5     16-Jun-2021 19:30                1802
ber01-VHDL13_DWMO_162000-2106162000-dsw--0-ia5     16-Jun-2021 20:30                1916
ber01-VHDL13_DWMO_162100-2106162100-dsw--0-ia5     16-Jun-2021 21:30                1916
ber01-VHDL13_DWMO_162200-2106162200-dsw--0-ia5     16-Jun-2021 22:30                2308
ber01-VHDL13_DWMO_162300-2106162300-dsw--0-ia5     16-Jun-2021 23:30                2308
ber01-VHDL13_DWMO_170000-2106170000-dsw--0-ia5     17-Jun-2021 00:30                2308
ber01-VHDL13_DWMO_170100-2106170100-dsw--0-ia5     17-Jun-2021 01:30                2308
ber01-VHDL13_DWMO_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2308
ber01-VHDL13_DWMO_170300-2106170300-dsw--0-ia5     17-Jun-2021 03:30                2399
ber01-VHDL13_DWMO_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2420
ber01-VHDL13_DWMO_170500-2106170500-dsw--0-ia5     17-Jun-2021 05:30                2420
ber01-VHDL13_DWMO_170600-2106170600-dsw--0-ia5     17-Jun-2021 06:30                2420
ber01-VHDL13_DWMO_170700-2106170700-dsw--0-ia5     17-Jun-2021 07:30                2533
ber01-VHDL13_DWMO_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2561
ber01-VHDL13_DWMO_170900-2106170900-dsw--0-ia5     17-Jun-2021 09:30                2533
ber01-VHDL13_DWMO_171000-2106171000-dsw--0-ia5     17-Jun-2021 10:30                2533
ber01-VHDL13_DWMO_171100-2106171100-dsw--0-ia5     17-Jun-2021 11:30                2522
ber01-VHDL13_DWMO_171200-2106171200-dsw--0-ia5     17-Jun-2021 12:30                2522
ber01-VHDL13_DWMO_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                2817
ber01-VHDL13_DWMO_171400-2106171400-dsw--0-ia5     17-Jun-2021 14:30                2817
ber01-VHDL13_DWMO_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2817
ber01-VHDL13_DWMO_171600-2106171600-dsw--0-ia5     17-Jun-2021 16:30                2817
ber01-VHDL13_DWMO_171700-2106171700-dsw--0-ia5     17-Jun-2021 17:30                2510
ber01-VHDL13_DWMO_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2510
ber01-VHDL13_DWMO_171900-2106171900-dsw--0-ia5     17-Jun-2021 19:30                2510
ber01-VHDL13_DWMO_172000-2106172000-dsw--0-ia5     17-Jun-2021 20:30                2539
ber01-VHDL13_DWMO_172100-2106172100-dsw--0-ia5     17-Jun-2021 21:30                2539
ber01-VHDL13_DWMO_172200-2106172200-dsw--0-ia5     17-Jun-2021 22:30                2844
ber01-VHDL13_DWMO_172300-2106172300-dsw--0-ia5     17-Jun-2021 23:30                2844
ber01-VHDL13_DWMO_180000-2106180000-dsw--0-ia5     18-Jun-2021 00:30                2844
ber01-VHDL13_DWMO_180100-2106180100-dsw--0-ia5     18-Jun-2021 01:30                2844
ber01-VHDL13_DWMO_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2844
ber01-VHDL13_DWMO_180300-2106180300-dsw--0-ia5     18-Jun-2021 03:30                3066
ber01-VHDL13_DWMO_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3074
ber01-VHDL13_DWMO_180500-2106180500-dsw--0-ia5     18-Jun-2021 05:30                3074
ber01-VHDL13_DWMO_180600-2106180600-dsw--0-ia5     18-Jun-2021 06:30                3074
ber01-VHDL13_DWMO_180700-2106180700-dsw--0-ia5     18-Jun-2021 07:30                3074
ber01-VHDL13_DWMO_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3102
ber01-VHDL13_DWMO_180900-2106180900-dsw--0-ia5     18-Jun-2021 09:30                3074
ber01-VHDL13_DWMP_161000-2106161000-dsw--0-ia5     16-Jun-2021 10:30                2325
ber01-VHDL13_DWMP_161100-2106161100-dsw--0-ia5     16-Jun-2021 11:30                2325
ber01-VHDL13_DWMP_161200-2106161200-dsw--0-ia5     16-Jun-2021 12:30                2355
ber01-VHDL13_DWMP_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2279
ber01-VHDL13_DWMP_161400-2106161400-dsw--0-ia5     16-Jun-2021 14:30                2279
ber01-VHDL13_DWMP_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                2279
ber01-VHDL13_DWMP_161600-2106161600-dsw--0-ia5     16-Jun-2021 16:30                2279
ber01-VHDL13_DWMP_161700-2106161700-dsw--0-ia5     16-Jun-2021 17:30                2007
ber01-VHDL13_DWMP_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2007
ber01-VHDL13_DWMP_161900-2106161900-dsw--0-ia5     16-Jun-2021 19:30                2007
ber01-VHDL13_DWMP_162000-2106162000-dsw--0-ia5     16-Jun-2021 20:30                2007
ber01-VHDL13_DWMP_162100-2106162100-dsw--0-ia5     16-Jun-2021 21:30                1935
ber01-VHDL13_DWMP_162200-2106162200-dsw--0-ia5     16-Jun-2021 22:30                2241
ber01-VHDL13_DWMP_162300-2106162300-dsw--0-ia5     16-Jun-2021 23:30                2241
ber01-VHDL13_DWMP_170000-2106170000-dsw--0-ia5     17-Jun-2021 00:30                2241
ber01-VHDL13_DWMP_170100-2106170100-dsw--0-ia5     17-Jun-2021 01:30                2241
ber01-VHDL13_DWMP_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2241
ber01-VHDL13_DWMP_170300-2106170300-dsw--0-ia5     17-Jun-2021 03:30                2296
ber01-VHDL13_DWMP_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2308
ber01-VHDL13_DWMP_170500-2106170500-dsw--0-ia5     17-Jun-2021 05:30                2308
ber01-VHDL13_DWMP_170600-2106170600-dsw--0-ia5     17-Jun-2021 06:30                2223
ber01-VHDL13_DWMP_170700-2106170700-dsw--0-ia5     17-Jun-2021 07:30                2346
ber01-VHDL13_DWMP_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2321
ber01-VHDL13_DWMP_170900-2106170900-dsw--0-ia5     17-Jun-2021 09:30                2321
ber01-VHDL13_DWMP_171000-2106171000-dsw--0-ia5     17-Jun-2021 10:30                2321
ber01-VHDL13_DWMP_171100-2106171100-dsw--0-ia5     17-Jun-2021 11:30                2589
ber01-VHDL13_DWMP_171200-2106171200-dsw--0-ia5     17-Jun-2021 12:30                2589
ber01-VHDL13_DWMP_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                2543
ber01-VHDL13_DWMP_171400-2106171400-dsw--0-ia5     17-Jun-2021 14:30                2543
ber01-VHDL13_DWMP_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2543
ber01-VHDL13_DWMP_171600-2106171600-dsw--0-ia5     17-Jun-2021 16:30                2543
ber01-VHDL13_DWMP_171700-2106171700-dsw--0-ia5     17-Jun-2021 17:30                2291
ber01-VHDL13_DWMP_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2291
ber01-VHDL13_DWMP_171900-2106171900-dsw--0-ia5     17-Jun-2021 19:30                2291
ber01-VHDL13_DWMP_172000-2106172000-dsw--0-ia5     17-Jun-2021 20:30                2291
ber01-VHDL13_DWMP_172100-2106172100-dsw--0-ia5     17-Jun-2021 21:30                2352
ber01-VHDL13_DWMP_172200-2106172200-dsw--0-ia5     17-Jun-2021 22:30                2697
ber01-VHDL13_DWMP_172300-2106172300-dsw--0-ia5     17-Jun-2021 23:30                2697
ber01-VHDL13_DWMP_180000-2106180000-dsw--0-ia5     18-Jun-2021 00:30                2697
ber01-VHDL13_DWMP_180100-2106180100-dsw--0-ia5     18-Jun-2021 01:30                2697
ber01-VHDL13_DWMP_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2697
ber01-VHDL13_DWMP_180300-2106180300-dsw--0-ia5     18-Jun-2021 03:30                2983
ber01-VHDL13_DWMP_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                2991
ber01-VHDL13_DWMP_180500-2106180500-dsw--0-ia5     18-Jun-2021 05:30                2991
ber01-VHDL13_DWMP_180600-2106180600-dsw--0-ia5     18-Jun-2021 06:30                2991
ber01-VHDL13_DWMP_180700-2106180700-dsw--0-ia5     18-Jun-2021 07:30                2991
ber01-VHDL13_DWMP_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                2991
ber01-VHDL13_DWMP_180900-2106180900-dsw--0-ia5     18-Jun-2021 09:30                2991
ber01-VHDL13_DWOG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:00                4107
ber01-VHDL13_DWOG_161700-2106161700-dsw--0-ia5     16-Jun-2021 17:30                3874
ber01-VHDL13_DWOG_170100-2106170100-dsw--0-ia5     17-Jun-2021 01:45                4279
ber01-VHDL13_DWOG_170300-2106170300-dsw--0-ia5     17-Jun-2021 03:00                4147
ber01-VHDL13_DWOG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:15                3811
ber01-VHDL13_DWOG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:00                4406
ber01-VHDL13_DWOG_171700-2106171700-dsw--0-ia5     17-Jun-2021 17:30                4205
ber01-VHDL13_DWOG_180100-2106180100-dsw--0-ia5     18-Jun-2021 01:45                4217
ber01-VHDL13_DWOG_180300-2106180300-dsw--0-ia5     18-Jun-2021 03:00                4716
ber01-VHDL13_DWOG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:15                4414
ber01-VHDL13_DWOH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:28                2597
ber01-VHDL13_DWOH_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:28                2441
ber01-VHDL13_DWOH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:28                2371
ber01-VHDL13_DWOH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:28                2579
ber01-VHDL13_DWOH_170400-2106170400-dsw--0-ia5     17-Jun-2021 04:58                2909
ber01-VHDL13_DWOH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:28                3112
ber01-VHDL13_DWOH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:28                3037
ber01-VHDL13_DWOH_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:28                3133
ber01-VHDL13_DWOH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:28                3182
ber01-VHDL13_DWOH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:28                3447
ber01-VHDL13_DWOH_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:58                3502
ber01-VHDL13_DWOH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:28                3558
ber01-VHDL13_DWOI_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:28                3206
ber01-VHDL13_DWOI_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:28                3163
ber01-VHDL13_DWOI_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:28                3084
ber01-VHDL13_DWOI_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:28                3354
ber01-VHDL13_DWOI_170400-2106170400-dsw--0-ia5     17-Jun-2021 04:58                3624
ber01-VHDL13_DWOI_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:28                4134
ber01-VHDL13_DWOI_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:28                4074
ber01-VHDL13_DWOI_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:28                4066
ber01-VHDL13_DWOI_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:28                3707
ber01-VHDL13_DWOI_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:28                3942
ber01-VHDL13_DWOI_180400-2106180400-dsw--0-ia5     18-Jun-2021 04:58                3591
ber01-VHDL13_DWOI_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:28                3587
ber01-VHDL13_DWON_161158-2106161158-dsw--0-ia5     16-Jun-2021 11:58                4447
ber01-VHDL13_DWON_161454-2106161454-dsw--0-ia5     16-Jun-2021 14:54                4593
ber01-VHDL13_DWON_161719-2106161719-dsw--0-ia5     16-Jun-2021 17:19                3923
ber01-VHDL13_DWON_162241-2106162241-dsw--0-ia5     16-Jun-2021 22:41                4169
ber01-VHDL13_DWON_170149-2106170149-dsw--0-ia5     17-Jun-2021 01:49                4169
ber01-VHDL13_DWON_170342-2106170342-dsw--0-ia5     17-Jun-2021 03:42                4169
ber01-VHDL13_DWON_170529-2106170529-dsw--0-ia5     17-Jun-2021 05:29                4028
ber01-VHDL13_DWON_170533-2106170533-dsw--0-ia5     17-Jun-2021 05:33                3554
ber01-VHDL13_DWON_170620-2106170620-dsw--0-ia5     17-Jun-2021 06:20                4038
ber01-VHDL13_DWON_171114-2106171114-dsw--0-ia5     17-Jun-2021 11:14                3985
ber01-VHDL13_DWON_171324-2106171324-dsw--0-ia5     17-Jun-2021 13:24                3985
ber01-VHDL13_DWON_171538-2106171538-dsw--0-ia5     17-Jun-2021 15:38                3497
ber01-VHDL13_DWON_171729-2106171729-dsw--0-ia5     17-Jun-2021 17:29                3492
ber01-VHDL13_DWON_172112-2106172112-dsw--0-ia5     17-Jun-2021 21:12                3492
ber01-VHDL13_DWON_180129-2106180129-dsw--0-ia5     18-Jun-2021 01:29                3919
ber01-VHDL13_DWON_180253-2106180253-dsw--0-ia5     18-Jun-2021 02:53                3919
ber01-VHDL13_DWON_180528-2106180528-dsw--0-ia5     18-Jun-2021 05:28                3749
ber01-VHDL13_DWON_180851-2106180851-dsw--0-ia5     18-Jun-2021 08:51                3667
ber01-VHDL13_DWPG_161030-2106161030-dsw--0-ia5     16-Jun-2021 10:30                1894
ber01-VHDL13_DWPG_161130-2106161130-dsw--0-ia5     16-Jun-2021 11:30                1894
ber01-VHDL13_DWPG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                1861
ber01-VHDL13_DWPG_161330-2106161330-dsw--0-ia5     16-Jun-2021 13:30                1860
ber01-VHDL13_DWPG_161430-2106161430-dsw--0-ia5     16-Jun-2021 14:30                1860
ber01-VHDL13_DWPG_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                1786
ber01-VHDL13_DWPG_161630-2106161630-dsw--0-ia5     16-Jun-2021 16:30                1785
ber01-VHDL13_DWPG_161730-2106161730-dsw--0-ia5     16-Jun-2021 17:30                1638
ber01-VHDL13_DWPG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1639
ber01-VHDL13_DWPG_161930-2106161930-dsw--0-ia5     16-Jun-2021 19:30                1638
ber01-VHDL13_DWPG_162030-2106162030-dsw--0-ia5     16-Jun-2021 20:30                1638
ber01-VHDL13_DWPG_170030-2106170030-dsw--0-ia5     17-Jun-2021 00:30                1856
ber01-VHDL13_DWPG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                1970
ber01-VHDL13_DWPG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2157
ber01-VHDL13_DWPG_170530-2106170530-dsw--0-ia5     17-Jun-2021 05:30                2155
ber01-VHDL13_DWPG_170630-2106170630-dsw--0-ia5     17-Jun-2021 06:30                2126
ber01-VHDL13_DWPG_170730-2106170730-dsw--0-ia5     17-Jun-2021 07:30                2126
ber01-VHDL13_DWPG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2139
ber01-VHDL13_DWPG_170930-2106170930-dsw--0-ia5     17-Jun-2021 09:30                2138
ber01-VHDL13_DWPG_171030-2106171030-dsw--0-ia5     17-Jun-2021 10:30                2138
ber01-VHDL13_DWPG_171130-2106171130-dsw--0-ia5     17-Jun-2021 11:30                2188
ber01-VHDL13_DWPG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2189
ber01-VHDL13_DWPG_171330-2106171330-dsw--0-ia5     17-Jun-2021 13:30                2188
ber01-VHDL13_DWPG_171430-2106171430-dsw--0-ia5     17-Jun-2021 14:30                2188
ber01-VHDL13_DWPG_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2214
ber01-VHDL13_DWPG_171630-2106171630-dsw--0-ia5     17-Jun-2021 16:30                2213
ber01-VHDL13_DWPG_171730-2106171730-dsw--0-ia5     17-Jun-2021 17:30                2213
ber01-VHDL13_DWPG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2002
ber01-VHDL13_DWPG_171930-2106171930-dsw--0-ia5     17-Jun-2021 19:30                2020
ber01-VHDL13_DWPG_172030-2106172030-dsw--0-ia5     17-Jun-2021 20:30                2020
ber01-VHDL13_DWPG_180030-2106180030-dsw--0-ia5     18-Jun-2021 00:30                2270
ber01-VHDL13_DWPG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2404
ber01-VHDL13_DWPG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                2851
ber01-VHDL13_DWPG_180530-2106180530-dsw--0-ia5     18-Jun-2021 05:30                2849
ber01-VHDL13_DWPG_180630-2106180630-dsw--0-ia5     18-Jun-2021 06:30                2849
ber01-VHDL13_DWPG_180730-2106180730-dsw--0-ia5     18-Jun-2021 07:30                2849
ber01-VHDL13_DWPG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                2853
ber01-VHDL13_DWPG_180930-2106180930-dsw--0-ia5     18-Jun-2021 09:30                2849
ber01-VHDL13_DWPH_161030-2106161030-dsw--0-ia5     16-Jun-2021 10:30                2044
ber01-VHDL13_DWPH_161130-2106161130-dsw--0-ia5     16-Jun-2021 11:30                2044
ber01-VHDL13_DWPH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2008
ber01-VHDL13_DWPH_161330-2106161330-dsw--0-ia5     16-Jun-2021 13:30                2008
ber01-VHDL13_DWPH_161430-2106161430-dsw--0-ia5     16-Jun-2021 14:30                2008
ber01-VHDL13_DWPH_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                1920
ber01-VHDL13_DWPH_161630-2106161630-dsw--0-ia5     16-Jun-2021 16:30                1920
ber01-VHDL13_DWPH_161730-2106161730-dsw--0-ia5     16-Jun-2021 17:30                1753
ber01-VHDL13_DWPH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1753
ber01-VHDL13_DWPH_161930-2106161930-dsw--0-ia5     16-Jun-2021 19:30                1753
ber01-VHDL13_DWPH_162030-2106162030-dsw--0-ia5     16-Jun-2021 20:30                1753
ber01-VHDL13_DWPH_170030-2106170030-dsw--0-ia5     17-Jun-2021 00:30                2036
ber01-VHDL13_DWPH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2222
ber01-VHDL13_DWPH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2426
ber01-VHDL13_DWPH_170530-2106170530-dsw--0-ia5     17-Jun-2021 05:30                2426
ber01-VHDL13_DWPH_170630-2106170630-dsw--0-ia5     17-Jun-2021 06:30                2426
ber01-VHDL13_DWPH_170730-2106170730-dsw--0-ia5     17-Jun-2021 07:30                2426
ber01-VHDL13_DWPH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2438
ber01-VHDL13_DWPH_170930-2106170930-dsw--0-ia5     17-Jun-2021 09:30                2438
ber01-VHDL13_DWPH_171030-2106171030-dsw--0-ia5     17-Jun-2021 10:30                2438
ber01-VHDL13_DWPH_171130-2106171130-dsw--0-ia5     17-Jun-2021 11:30                2426
ber01-VHDL13_DWPH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2426
ber01-VHDL13_DWPH_171330-2106171330-dsw--0-ia5     17-Jun-2021 13:30                2426
ber01-VHDL13_DWPH_171430-2106171430-dsw--0-ia5     17-Jun-2021 14:30                2426
ber01-VHDL13_DWPH_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2519
ber01-VHDL13_DWPH_171630-2106171630-dsw--0-ia5     17-Jun-2021 16:30                2519
ber01-VHDL13_DWPH_171730-2106171730-dsw--0-ia5     17-Jun-2021 17:30                2511
ber01-VHDL13_DWPH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2168
ber01-VHDL13_DWPH_171930-2106171930-dsw--0-ia5     17-Jun-2021 19:30                2159
ber01-VHDL13_DWPH_172030-2106172030-dsw--0-ia5     17-Jun-2021 20:30                2159
ber01-VHDL13_DWPH_180030-2106180030-dsw--0-ia5     18-Jun-2021 00:30                2380
ber01-VHDL13_DWPH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2450
ber01-VHDL13_DWPH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3030
ber01-VHDL13_DWPH_180530-2106180530-dsw--0-ia5     18-Jun-2021 05:30                3030
ber01-VHDL13_DWPH_180630-2106180630-dsw--0-ia5     18-Jun-2021 06:30                3030
ber01-VHDL13_DWPH_180730-2106180730-dsw--0-ia5     18-Jun-2021 07:30                3030
ber01-VHDL13_DWPH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3125
ber01-VHDL13_DWPH_180930-2106180930-dsw--0-ia5     18-Jun-2021 09:30                3125
ber01-VHDL13_DWSG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2809
ber01-VHDL13_DWSG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2599
ber01-VHDL13_DWSG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                3051
ber01-VHDL13_DWSG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2910
ber01-VHDL13_DWSG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2878
ber01-VHDL13_DWSG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                3480
ber01-VHDL13_DWSG_171300_COR-2106171300-dsw--0-ia5 17-Jun-2021 14:15                3562
ber01-VHDL13_DWSG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                3003
ber01-VHDL13_DWSG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                3124
ber01-VHDL13_DWSG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3095
ber01-VHDL13_DWSG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3086
ber01-VHDL13_DWSN_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2031
ber01-VHDL13_DWSN_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1996
ber01-VHDL13_DWSN_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2313
ber01-VHDL13_DWSN_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2324
ber01-VHDL13_DWSN_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2290
ber01-VHDL13_DWSN_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                2595
ber01-VHDL13_DWSN_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2415
ber01-VHDL13_DWSN_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2878
ber01-VHDL13_DWSN_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                2948
ber01-VHDL13_DWSN_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                2947
ber01-VHDL13_DWSO_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2723
ber01-VHDL13_DWSO_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2625
ber01-VHDL13_DWSO_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                3045
ber01-VHDL13_DWSO_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2882
ber01-VHDL13_DWSO_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2856
ber01-VHDL13_DWSO_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                3426
ber01-VHDL13_DWSO_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                3010
ber01-VHDL13_DWSO_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                3186
ber01-VHDL13_DWSO_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3093
ber01-VHDL13_DWSO_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3093
ber01-VHDL13_DWSP_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:30                2139
ber01-VHDL13_DWSP_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                2069
ber01-VHDL13_DWSP_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2415
ber01-VHDL13_DWSP_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2417
ber01-VHDL13_DWSP_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2384
ber01-VHDL13_DWSP_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:30                2684
ber01-VHDL13_DWSP_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2514
ber01-VHDL13_DWSP_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2957
ber01-VHDL13_DWSP_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3059
ber01-VHDL13_DWSP_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3059
ber01-VHDL17_DWOG_161200-2106161200-dsw--0-ia5     16-Jun-2021 11:36                3144
ber01-VHDL17_DWOG_171200-2106171200-dsw--0-ia5     17-Jun-2021 11:49                2472
ber01-VHDL20_DWHG_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:45                3028
ber01-VHDL20_DWHG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                3144
ber01-VHDL20_DWHG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                3232
ber01-VHDL20_DWHG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                3287
ber01-VHDL20_DWHG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                3409
ber01-VHDL20_DWHG_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:45                3661
ber01-VHDL20_DWHG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2874
ber01-VHDL20_DWHG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3249
ber01-VHDL20_DWHG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3248
ber01-VHDL20_DWHG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3239
ber01-VHDL20_DWHH_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:45                3006
ber01-VHDL20_DWHH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2907
ber01-VHDL20_DWHH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2842
ber01-VHDL20_DWHH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2825
ber01-VHDL20_DWHH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2895
ber01-VHDL20_DWHH_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:45                3314
ber01-VHDL20_DWHH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2788
ber01-VHDL20_DWHH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3118
ber01-VHDL20_DWHH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3159
ber01-VHDL20_DWHH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                2831
gts01-VHDL12_DWON_161330-2106161230-afsv--33-ia5   16-Jun-2021 12:30                3986
gts01-VHDL12_DWON_161815-2106161745-afsv--70-ia5   16-Jun-2021 17:45                3302
gts01-VHDL12_DWON_170115-2106170145-afsv--96-ia5   17-Jun-2021 01:45                3633
gts01-VHDL12_DWON_170530-2106170530-afsv--09-ia5   17-Jun-2021 05:30                3486
gts01-VHDL12_DWON_170815-2106170815-afsv--86-ia5   17-Jun-2021 08:15                3530
gts01-VHDL12_DWON_171330-2106171230-afsv--26-ia5   17-Jun-2021 12:30                3477
gts01-VHDL12_DWON_171815-2106171745-afsv--71-ia5   17-Jun-2021 17:45                2972
gts01-VHDL12_DWON_180115-2106180145-afsv--99-ia5   18-Jun-2021 01:45                3520
gts01-VHDL12_DWON_180530-2106180530-afsv--09-ia5   18-Jun-2021 05:30                3346
gts01-VHDL12_DWON_180815-2106180815-afsv--77-ia5   18-Jun-2021 08:15                3346
pid-VHDL12_DWEH_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:28                3226
pid-VHDL12_DWEH_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:28                3505
pid-VHDL12_DWHG_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                2718
pid-VHDL12_DWHG_170400-2106170400-dsw--0-ia5       17-Jun-2021 05:00                2768
pid-VHDL12_DWHG_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2663
pid-VHDL12_DWHG_180400-2106180400-dsw--0-ia5       18-Jun-2021 05:00                2657
pid-VHDL12_DWHH_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                2331
pid-VHDL12_DWHH_170400-2106170400-dsw--0-ia5       17-Jun-2021 05:00                2313
pid-VHDL12_DWHH_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2501
pid-VHDL12_DWHH_180400-2106180400-dsw--0-ia5       18-Jun-2021 05:00                2541
pid-VHDL12_DWLG_161300-2106161300-dsw--0-ia5       16-Jun-2021 12:30                1676
pid-VHDL12_DWLG_161800-2106161800-dsw--0-ia5       16-Jun-2021 18:30                1434
pid-VHDL12_DWLG_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                1768
pid-VHDL12_DWLG_170400-2106170400-dsw--0-ia5       17-Jun-2021 04:59                1754
pid-VHDL12_DWLG_170800-2106170800-dsw--0-ia5       17-Jun-2021 08:30                1780
pid-VHDL12_DWLG_171300-2106171300-dsw--0-ia5       17-Jun-2021 12:30                1751
pid-VHDL12_DWLG_171800-2106171800-dsw--0-ia5       17-Jun-2021 18:30                1542
pid-VHDL12_DWLG_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                1903
pid-VHDL12_DWLG_180400-2106180400-dsw--0-ia5       18-Jun-2021 04:59                1862
pid-VHDL12_DWLG_180800-2106180800-dsw--0-ia5       18-Jun-2021 08:30                2337
pid-VHDL12_DWLH_161300-2106161300-dsw--0-ia5       16-Jun-2021 12:30                1736
pid-VHDL12_DWLH_161800-2106161800-dsw--0-ia5       16-Jun-2021 18:30                1360
pid-VHDL12_DWLH_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                1701
pid-VHDL12_DWLH_170400-2106170400-dsw--0-ia5       17-Jun-2021 04:59                1802
pid-VHDL12_DWLH_170800-2106170800-dsw--0-ia5       17-Jun-2021 08:30                1830
pid-VHDL12_DWLH_171300-2106171300-dsw--0-ia5       17-Jun-2021 12:30                1801
pid-VHDL12_DWLH_171800-2106171800-dsw--0-ia5       17-Jun-2021 18:30                1596
pid-VHDL12_DWLH_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2324
pid-VHDL12_DWLH_180400-2106180400-dsw--0-ia5       18-Jun-2021 04:59                2480
pid-VHDL12_DWLH_180800-2106180800-dsw--0-ia5       18-Jun-2021 08:30                2871
pid-VHDL12_DWLI_161300-2106161300-dsw--0-ia5       16-Jun-2021 12:30                1759
pid-VHDL12_DWLI_161800-2106161800-dsw--0-ia5       16-Jun-2021 18:30                1375
pid-VHDL12_DWLI_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                1710
pid-VHDL12_DWLI_170400-2106170400-dsw--0-ia5       17-Jun-2021 04:59                1812
pid-VHDL12_DWLI_170800-2106170800-dsw--0-ia5       17-Jun-2021 08:30                1838
pid-VHDL12_DWLI_171300-2106171300-dsw--0-ia5       17-Jun-2021 12:30                1809
pid-VHDL12_DWLI_171800-2106171800-dsw--0-ia5       17-Jun-2021 18:30                1600
pid-VHDL12_DWLI_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2291
pid-VHDL12_DWLI_180400-2106180400-dsw--0-ia5       18-Jun-2021 04:59                2365
pid-VHDL12_DWLI_180800-2106180800-dsw--0-ia5       18-Jun-2021 08:30                2723
pid-VHDL12_DWMG_161300-2106161300-dsw--0-ia5       16-Jun-2021 12:30                1944
pid-VHDL12_DWMG_161800-2106161800-dsw--0-ia5       16-Jun-2021 18:30                1610
pid-VHDL12_DWMG_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                1949
pid-VHDL12_DWMG_170400-2106170400-dsw--0-ia5       17-Jun-2021 05:00                1945
pid-VHDL12_DWMG_170800-2106170800-dsw--0-ia5       17-Jun-2021 08:30                1933
pid-VHDL12_DWMG_171300-2106171300-dsw--0-ia5       17-Jun-2021 12:30                2200
pid-VHDL12_DWMG_171800-2106171800-dsw--0-ia5       17-Jun-2021 18:30                2009
pid-VHDL12_DWMG_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2609
pid-VHDL12_DWMG_180400-2106180400-dsw--0-ia5       18-Jun-2021 05:00                2650
pid-VHDL12_DWMG_180800-2106180800-dsw--0-ia5       18-Jun-2021 08:30                2856
pid-VHDL12_DWOG_170100-2106170100-dsw--0-ia5       17-Jun-2021 01:45                3627
pid-VHDL12_DWOG_170300-2106170300-dsw--0-ia5       17-Jun-2021 03:00                3495
pid-VHDL12_DWOG_180100-2106180100-dsw--0-ia5       18-Jun-2021 01:45                3720
pid-VHDL12_DWOG_180300-2106180300-dsw--0-ia5       18-Jun-2021 03:00                4219
pid-VHDL12_DWOH_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:28                2178
pid-VHDL12_DWOH_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:28                3066
pid-VHDL12_DWOI_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:28                2927
pid-VHDL12_DWOI_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:28                3562
pid-VHDL12_DWSG_170200-2106170200-dsw--0-ia5       17-Jun-2021 02:30                2542
pid-VHDL12_DWSG_180200-2106180200-dsw--0-ia5       18-Jun-2021 02:30                2605
swis2-VHDL20_DWEG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2811
swis2-VHDL20_DWEG_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:45                2648
swis2-VHDL20_DWEG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2584
swis2-VHDL20_DWEG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2739
swis2-VHDL20_DWEG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:15                3116
swis2-VHDL20_DWEG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                3319
swis2-VHDL20_DWEG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                3252
swis2-VHDL20_DWEG_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:45                3340
swis2-VHDL20_DWEG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                3395
swis2-VHDL20_DWEG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3607
swis2-VHDL20_DWEG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:15                3709
swis2-VHDL20_DWEG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3765
swis2-VHDL20_DWEH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                3777
swis2-VHDL20_DWEH_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:45                3647
swis2-VHDL20_DWEH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                3593
swis2-VHDL20_DWEH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                3846
swis2-VHDL20_DWEH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:15                4315
swis2-VHDL20_DWEH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                5011
swis2-VHDL20_DWEH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                5001
swis2-VHDL20_DWEH_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:45                4947
swis2-VHDL20_DWEH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                4291
swis2-VHDL20_DWEH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                4074
swis2-VHDL20_DWEH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:15                4023
swis2-VHDL20_DWEH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3776
swis2-VHDL20_DWEI_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                3419
swis2-VHDL20_DWEI_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:45                3376
swis2-VHDL20_DWEI_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                3297
swis2-VHDL20_DWEI_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                3515
swis2-VHDL20_DWEI_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:15                3837
swis2-VHDL20_DWEI_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                4341
swis2-VHDL20_DWEI_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                4287
swis2-VHDL20_DWEI_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:45                4279
swis2-VHDL20_DWEI_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                3920
swis2-VHDL20_DWEI_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                4103
swis2-VHDL20_DWEI_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:15                3804
swis2-VHDL20_DWEI_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3794
swis2-VHDL20_DWHG_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:45                3028
swis2-VHDL20_DWHG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                3144
swis2-VHDL20_DWHG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                3232
swis2-VHDL20_DWHG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                3287
swis2-VHDL20_DWHG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                3409
swis2-VHDL20_DWHG_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:45                3661
swis2-VHDL20_DWHG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2874
swis2-VHDL20_DWHG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3249
swis2-VHDL20_DWHG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3248
swis2-VHDL20_DWHG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3239
swis2-VHDL20_DWHH_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:45                3006
swis2-VHDL20_DWHH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2907
swis2-VHDL20_DWHH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2842
swis2-VHDL20_DWHH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2825
swis2-VHDL20_DWHH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2895
swis2-VHDL20_DWHH_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:45                3314
swis2-VHDL20_DWHH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2788
swis2-VHDL20_DWHH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3118
swis2-VHDL20_DWHH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3159
swis2-VHDL20_DWHH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                2831
swis2-VHDL20_DWLG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2365
swis2-VHDL20_DWLG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2173
swis2-VHDL20_DWLG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2364
swis2-VHDL20_DWLG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2351
swis2-VHDL20_DWLG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2377
swis2-VHDL20_DWLG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2348
swis2-VHDL20_DWLG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2139
swis2-VHDL20_DWLG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                2595
swis2-VHDL20_DWLG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                2554
swis2-VHDL20_DWLG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3029
swis2-VHDL20_DWLH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2410
swis2-VHDL20_DWLH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2090
swis2-VHDL20_DWLH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2298
swis2-VHDL20_DWLH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2399
swis2-VHDL20_DWLH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2427
swis2-VHDL20_DWLH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2398
swis2-VHDL20_DWLH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2193
swis2-VHDL20_DWLH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3024
swis2-VHDL20_DWLH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3181
swis2-VHDL20_DWLH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3572
swis2-VHDL20_DWLI_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2474
swis2-VHDL20_DWLI_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2146
swis2-VHDL20_DWLI_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2305
swis2-VHDL20_DWLI_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2408
swis2-VHDL20_DWLI_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2434
swis2-VHDL20_DWLI_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2405
swis2-VHDL20_DWLI_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2196
swis2-VHDL20_DWLI_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                2977
swis2-VHDL20_DWLI_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3051
swis2-VHDL20_DWLI_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3409
swis2-VHDL20_DWMG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2615
swis2-VHDL20_DWMG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2217
swis2-VHDL20_DWMG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2633
swis2-VHDL20_DWMG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2637
swis2-VHDL20_DWMG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2625
swis2-VHDL20_DWMG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2892
swis2-VHDL20_DWMG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2710
swis2-VHDL20_DWMG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3267
swis2-VHDL20_DWMG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3307
swis2-VHDL20_DWMG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3514
swis2-VHDL20_DWMO_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2460
swis2-VHDL20_DWMO_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2088
swis2-VHDL20_DWMO_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2681
swis2-VHDL20_DWMO_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2706
swis2-VHDL20_DWMO_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2816
swis2-VHDL20_DWMO_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2805
swis2-VHDL20_DWMO_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2793
swis2-VHDL20_DWMO_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3348
swis2-VHDL20_DWMO_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3359
swis2-VHDL20_DWMO_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3356
swis2-VHDL20_DWMP_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:45                2639
swis2-VHDL20_DWMP_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2278
swis2-VHDL20_DWMP_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                2523
swis2-VHDL20_DWMP_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2589
swis2-VHDL20_DWMP_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                2602
swis2-VHDL20_DWMP_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:45                2870
swis2-VHDL20_DWMP_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                2571
swis2-VHDL20_DWMP_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3265
swis2-VHDL20_DWMP_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3271
swis2-VHDL20_DWMP_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3271
swis2-VHDL20_DWPG_161030-2106161030-dsw--0-ia5     16-Jun-2021 10:30                2081
swis2-VHDL20_DWPG_161130-2106161130-dsw--0-ia5     16-Jun-2021 11:30                2081
swis2-VHDL20_DWPG_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2047
swis2-VHDL20_DWPG_161330-2106161330-dsw--0-ia5     16-Jun-2021 13:30                2047
swis2-VHDL20_DWPG_161430-2106161430-dsw--0-ia5     16-Jun-2021 14:30                2047
swis2-VHDL20_DWPG_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                1972
swis2-VHDL20_DWPG_161630-2106161630-dsw--0-ia5     16-Jun-2021 16:30                1972
swis2-VHDL20_DWPG_161730-2106161730-dsw--0-ia5     16-Jun-2021 17:30                1825
swis2-VHDL20_DWPG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1826
swis2-VHDL20_DWPG_161930-2106161930-dsw--0-ia5     16-Jun-2021 19:30                1825
swis2-VHDL20_DWPG_162030-2106162030-dsw--0-ia5     16-Jun-2021 20:30                1825
swis2-VHDL20_DWPG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2157
swis2-VHDL20_DWPG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2342
swis2-VHDL20_DWPG_170530-2106170530-dsw--0-ia5     17-Jun-2021 05:30                2342
swis2-VHDL20_DWPG_170630-2106170630-dsw--0-ia5     17-Jun-2021 06:30                2313
swis2-VHDL20_DWPG_170730-2106170730-dsw--0-ia5     17-Jun-2021 07:30                2313
swis2-VHDL20_DWPG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2326
swis2-VHDL20_DWPG_170930-2106170930-dsw--0-ia5     17-Jun-2021 09:30                2325
swis2-VHDL20_DWPG_171030-2106171030-dsw--0-ia5     17-Jun-2021 10:30                2325
swis2-VHDL20_DWPG_171130-2106171130-dsw--0-ia5     17-Jun-2021 11:30                2375
swis2-VHDL20_DWPG_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2375
swis2-VHDL20_DWPG_171330-2106171330-dsw--0-ia5     17-Jun-2021 13:30                2375
swis2-VHDL20_DWPG_171430-2106171430-dsw--0-ia5     17-Jun-2021 14:30                2375
swis2-VHDL20_DWPG_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2400
swis2-VHDL20_DWPG_171630-2106171630-dsw--0-ia5     17-Jun-2021 16:30                2400
swis2-VHDL20_DWPG_171730-2106171730-dsw--0-ia5     17-Jun-2021 17:30                2400
swis2-VHDL20_DWPG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2189
swis2-VHDL20_DWPG_171930-2106171930-dsw--0-ia5     17-Jun-2021 19:30                2207
swis2-VHDL20_DWPG_172030-2106172030-dsw--0-ia5     17-Jun-2021 20:30                2207
swis2-VHDL20_DWPG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2591
swis2-VHDL20_DWPG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3036
swis2-VHDL20_DWPG_180530-2106180530-dsw--0-ia5     18-Jun-2021 05:30                3036
swis2-VHDL20_DWPG_180630-2106180630-dsw--0-ia5     18-Jun-2021 06:30                3036
swis2-VHDL20_DWPG_180730-2106180730-dsw--0-ia5     18-Jun-2021 07:30                3036
swis2-VHDL20_DWPG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3040
swis2-VHDL20_DWPG_180930-2106180930-dsw--0-ia5     18-Jun-2021 09:30                3036
swis2-VHDL20_DWPH_161030-2106161030-dsw--0-ia5     16-Jun-2021 10:30                2231
swis2-VHDL20_DWPH_161130-2106161130-dsw--0-ia5     16-Jun-2021 11:30                2231
swis2-VHDL20_DWPH_161300-2106161300-dsw--0-ia5     16-Jun-2021 12:30                2195
swis2-VHDL20_DWPH_161330-2106161330-dsw--0-ia5     16-Jun-2021 13:30                2195
swis2-VHDL20_DWPH_161430-2106161430-dsw--0-ia5     16-Jun-2021 14:30                2195
swis2-VHDL20_DWPH_161500-2106161500-dsw--0-ia5     16-Jun-2021 15:30                2107
swis2-VHDL20_DWPH_161630-2106161630-dsw--0-ia5     16-Jun-2021 16:30                2107
swis2-VHDL20_DWPH_161730-2106161730-dsw--0-ia5     16-Jun-2021 17:30                1940
swis2-VHDL20_DWPH_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:30                1940
swis2-VHDL20_DWPH_161930-2106161930-dsw--0-ia5     16-Jun-2021 19:30                1940
swis2-VHDL20_DWPH_162030-2106162030-dsw--0-ia5     16-Jun-2021 20:30                1940
swis2-VHDL20_DWPH_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:30                2409
swis2-VHDL20_DWPH_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:00                2613
swis2-VHDL20_DWPH_170530-2106170530-dsw--0-ia5     17-Jun-2021 05:30                2613
swis2-VHDL20_DWPH_170630-2106170630-dsw--0-ia5     17-Jun-2021 06:30                2613
swis2-VHDL20_DWPH_170730-2106170730-dsw--0-ia5     17-Jun-2021 07:30                2613
swis2-VHDL20_DWPH_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:30                2625
swis2-VHDL20_DWPH_170930-2106170930-dsw--0-ia5     17-Jun-2021 09:30                2625
swis2-VHDL20_DWPH_171030-2106171030-dsw--0-ia5     17-Jun-2021 10:30                2625
swis2-VHDL20_DWPH_171130-2106171130-dsw--0-ia5     17-Jun-2021 11:30                2613
swis2-VHDL20_DWPH_171300-2106171300-dsw--0-ia5     17-Jun-2021 12:30                2613
swis2-VHDL20_DWPH_171330-2106171330-dsw--0-ia5     17-Jun-2021 13:30                2613
swis2-VHDL20_DWPH_171430-2106171430-dsw--0-ia5     17-Jun-2021 14:30                2613
swis2-VHDL20_DWPH_171500-2106171500-dsw--0-ia5     17-Jun-2021 15:30                2706
swis2-VHDL20_DWPH_171630-2106171630-dsw--0-ia5     17-Jun-2021 16:30                2706
swis2-VHDL20_DWPH_171730-2106171730-dsw--0-ia5     17-Jun-2021 17:30                2698
swis2-VHDL20_DWPH_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:30                2355
swis2-VHDL20_DWPH_171930-2106171930-dsw--0-ia5     17-Jun-2021 19:30                2346
swis2-VHDL20_DWPH_172030-2106172030-dsw--0-ia5     17-Jun-2021 20:30                2346
swis2-VHDL20_DWPH_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:30                2637
swis2-VHDL20_DWPH_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:00                3217
swis2-VHDL20_DWPH_180530-2106180530-dsw--0-ia5     18-Jun-2021 05:30                3217
swis2-VHDL20_DWPH_180630-2106180630-dsw--0-ia5     18-Jun-2021 06:30                3217
swis2-VHDL20_DWPH_180730-2106180730-dsw--0-ia5     18-Jun-2021 07:30                3217
swis2-VHDL20_DWPH_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:30                3312
swis2-VHDL20_DWPH_180930-2106180930-dsw--0-ia5     18-Jun-2021 09:30                3312
swis2-VHDL20_DWSG_161300-2106161300-dsw--0-ia5     16-Jun-2021 13:45                3041
swis2-VHDL20_DWSG_161800-2106161800-dsw--0-ia5     16-Jun-2021 18:45                2831
swis2-VHDL20_DWSG_170200-2106170200-dsw--0-ia5     17-Jun-2021 02:45                3285
swis2-VHDL20_DWSG_170400-2106170400-dsw--0-ia5     17-Jun-2021 05:15                3141
swis2-VHDL20_DWSG_170800-2106170800-dsw--0-ia5     17-Jun-2021 08:45                3109
swis2-VHDL20_DWSG_171300-2106171300-dsw--0-ia5     17-Jun-2021 13:45                3763
swis2-VHDL20_DWSG_171800-2106171800-dsw--0-ia5     17-Jun-2021 18:45                3235
swis2-VHDL20_DWSG_180200-2106180200-dsw--0-ia5     18-Jun-2021 02:45                3358
swis2-VHDL20_DWSG_180400-2106180400-dsw--0-ia5     18-Jun-2021 05:15                3326
swis2-VHDL20_DWSG_180800-2106180800-dsw--0-ia5     18-Jun-2021 08:45                3316
wst04-VHDL20_DWEG_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              272564
wst04-VHDL20_DWEG_161500-2106161500-omedes--0.pdf  16-Jun-2021 15:45              272474
wst04-VHDL20_DWEG_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              272376
wst04-VHDL20_DWEG_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              272465
wst04-VHDL20_DWEG_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:15              274351
wst04-VHDL20_DWEG_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              274621
wst04-VHDL20_DWEG_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              270187
wst04-VHDL20_DWEG_171500-2106171500-omedes--0.pdf  17-Jun-2021 15:45              270302
wst04-VHDL20_DWEG_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              269819
wst04-VHDL20_DWEG_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              268925
wst04-VHDL20_DWEG_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:15              269546
wst04-VHDL20_DWEG_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              274134
wst04-VHDL20_DWEH_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              273460
wst04-VHDL20_DWEH_161500-2106161500-omedes--0.pdf  16-Jun-2021 15:45              273423
wst04-VHDL20_DWEH_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              273342
wst04-VHDL20_DWEH_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              274058
wst04-VHDL20_DWEH_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:15              274025
wst04-VHDL20_DWEH_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              274453
wst04-VHDL20_DWEH_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              272632
wst04-VHDL20_DWEH_171500-2106171500-omedes--0.pdf  17-Jun-2021 15:45              272622
wst04-VHDL20_DWEH_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              272158
wst04-VHDL20_DWEH_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              271839
wst04-VHDL20_DWEH_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:15              271304
wst04-VHDL20_DWEH_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              270711
wst04-VHDL20_DWEI_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              381985
wst04-VHDL20_DWEI_161500-2106161500-omedes--0.pdf  16-Jun-2021 15:45              381973
wst04-VHDL20_DWEI_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              381881
wst04-VHDL20_DWEI_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              382887
wst04-VHDL20_DWEI_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:15              382880
wst04-VHDL20_DWEI_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              383134
wst04-VHDL20_DWEI_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              377527
wst04-VHDL20_DWEI_171500-2106171500-omedes--0.pdf  17-Jun-2021 15:45              377589
wst04-VHDL20_DWEI_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              377362
wst04-VHDL20_DWEI_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              377313
wst04-VHDL20_DWEI_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:15              377196
wst04-VHDL20_DWEI_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              385865
wst04-VHDL20_DWHG_161300-2106161300-oflxs888--0..> 16-Jun-2021 13:45              372894
wst04-VHDL20_DWHG_161800-2106161800-oflxs888--0..> 16-Jun-2021 18:45              373711
wst04-VHDL20_DWHG_170200-2106170200-oflxs888--0..> 17-Jun-2021 02:45              374729
wst04-VHDL20_DWHG_170400-2106170400-oflxs888--0..> 17-Jun-2021 05:00              374844
wst04-VHDL20_DWHG_170800-2106170800-oflxs888--0..> 17-Jun-2021 08:45              375131
wst04-VHDL20_DWHG_171300-2106171300-oflxs888--0..> 17-Jun-2021 13:45              381593
wst04-VHDL20_DWHG_171800-2106171800-oflxs888--0..> 17-Jun-2021 18:45              380418
wst04-VHDL20_DWHG_180200-2106180200-oflxs888--0..> 18-Jun-2021 02:45              380457
wst04-VHDL20_DWHG_180400-2106180400-oflxs888--0..> 18-Jun-2021 05:00              380518
wst04-VHDL20_DWHG_180800-2106180800-oflxs888--0..> 18-Jun-2021 08:45              376273
wst04-VHDL20_DWHH_161300-2106161300-oflxs888--0..> 16-Jun-2021 13:45              362967
wst04-VHDL20_DWHH_161800-2106161800-oflxs888--0..> 16-Jun-2021 18:45              363524
wst04-VHDL20_DWHH_170200-2106170200-oflxs888--0..> 17-Jun-2021 02:45              364821
wst04-VHDL20_DWHH_170400-2106170400-oflxs888--0..> 17-Jun-2021 05:00              364875
wst04-VHDL20_DWHH_170800-2106170800-oflxs888--0..> 17-Jun-2021 08:45              364587
wst04-VHDL20_DWHH_171300-2106171300-oflxs888--0..> 17-Jun-2021 13:45              370398
wst04-VHDL20_DWHH_171800-2106171800-oflxs888--0..> 17-Jun-2021 18:45              369280
wst04-VHDL20_DWHH_180200-2106180200-oflxs888--0..> 18-Jun-2021 02:45              369051
wst04-VHDL20_DWHH_180400-2106180400-oflxs888--0..> 18-Jun-2021 05:00              369051
wst04-VHDL20_DWHH_180800-2106180800-oflxs888--0..> 18-Jun-2021 08:45              372176
wst04-VHDL20_DWLG_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:40              371833
wst04-VHDL20_DWLG_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:40              371118
wst04-VHDL20_DWLG_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:40              370702
wst04-VHDL20_DWLG_170400-2106170400-omedes--0.pdf  17-Jun-2021 04:59              370569
wst04-VHDL20_DWLG_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:40              370343
wst04-VHDL20_DWLG_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:40              371703
wst04-VHDL20_DWLG_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:40              371588
wst04-VHDL20_DWLG_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:40              371657
wst04-VHDL20_DWLG_180400-2106180400-omedes--0.pdf  18-Jun-2021 04:59              371949
wst04-VHDL20_DWLG_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:40              372283
wst04-VHDL20_DWLH_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:40              372373
wst04-VHDL20_DWLH_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:40              371548
wst04-VHDL20_DWLH_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:40              371585
wst04-VHDL20_DWLH_170400-2106170400-omedes--0.pdf  17-Jun-2021 04:59              371716
wst04-VHDL20_DWLH_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:40              371748
wst04-VHDL20_DWLH_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:40              374435
wst04-VHDL20_DWLH_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:40              374258
wst04-VHDL20_DWLH_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:40              374454
wst04-VHDL20_DWLH_180400-2106180400-omedes--0.pdf  18-Jun-2021 04:59              375423
wst04-VHDL20_DWLH_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:40              376833
wst04-VHDL20_DWLI_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:40              366926
wst04-VHDL20_DWLI_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:40              365761
wst04-VHDL20_DWLI_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:40              366134
wst04-VHDL20_DWLI_170400-2106170400-omedes--0.pdf  17-Jun-2021 04:59              366309
wst04-VHDL20_DWLI_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:40              366303
wst04-VHDL20_DWLI_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:40              368064
wst04-VHDL20_DWLI_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:40              367935
wst04-VHDL20_DWLI_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:40              368485
wst04-VHDL20_DWLI_180400-2106180400-omedes--0.pdf  18-Jun-2021 04:59              369018
wst04-VHDL20_DWLI_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:40              366386
wst04-VHDL20_DWMG_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              593841
wst04-VHDL20_DWMG_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              593320
wst04-VHDL20_DWMG_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              594043
wst04-VHDL20_DWMG_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:00              593735
wst04-VHDL20_DWMG_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              593723
wst04-VHDL20_DWMG_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              591848
wst04-VHDL20_DWMG_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              591347
wst04-VHDL20_DWMG_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              592071
wst04-VHDL20_DWMG_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:00              591856
wst04-VHDL20_DWMG_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              599658
wst04-VHDL20_DWMO_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              483559
wst04-VHDL20_DWMO_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              482962
wst04-VHDL20_DWMO_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              483474
wst04-VHDL20_DWMO_170400-2106170400-omedes--0.pdf  17-Jun-2021 04:45              483810
wst04-VHDL20_DWMO_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              483912
wst04-VHDL20_DWMO_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              478405
wst04-VHDL20_DWMO_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              478792
wst04-VHDL20_DWMO_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              479811
wst04-VHDL20_DWMO_180400-2106180400-omedes--0.pdf  18-Jun-2021 04:45              480254
wst04-VHDL20_DWMO_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              479396
wst04-VHDL20_DWMP_161300-2106161300-omedes--0.pdf  16-Jun-2021 12:45              601172
wst04-VHDL20_DWMP_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              600700
wst04-VHDL20_DWMP_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              600655
wst04-VHDL20_DWMP_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:00              601079
wst04-VHDL20_DWMP_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              601311
wst04-VHDL20_DWMP_171300-2106171300-omedes--0.pdf  17-Jun-2021 12:45              596730
wst04-VHDL20_DWMP_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              596267
wst04-VHDL20_DWMP_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              596057
wst04-VHDL20_DWMP_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:00              596860
wst04-VHDL20_DWMP_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              618414
wst04-VHDL20_DWPG_161030-2106161030-oflxs892--0..> 16-Jun-2021 10:30              379969
wst04-VHDL20_DWPG_161130-2106161130-oflxs892--0..> 16-Jun-2021 11:30              379969
wst04-VHDL20_DWPG_161300-2106161300-oflxs892--0..> 16-Jun-2021 12:30              380128
wst04-VHDL20_DWPG_161330-2106161330-oflxs892--0..> 16-Jun-2021 13:30              376496
wst04-VHDL20_DWPG_161430-2106161430-oflxs892--0..> 16-Jun-2021 14:30              376496
wst04-VHDL20_DWPG_161500-2106161500-oflxs892--0..> 16-Jun-2021 15:30              376330
wst04-VHDL20_DWPG_161630-2106161630-oflxs892--0..> 16-Jun-2021 16:30              376333
wst04-VHDL20_DWPG_161730-2106161730-oflxs892--0..> 16-Jun-2021 17:30              376244
wst04-VHDL20_DWPG_161800-2106161800-oflxs892--0..> 16-Jun-2021 18:30              375902
wst04-VHDL20_DWPG_161930-2106161930-oflxs892--0..> 16-Jun-2021 19:30              375877
wst04-VHDL20_DWPG_162030-2106162030-oflxs892--0..> 16-Jun-2021 20:30              375877
wst04-VHDL20_DWPG_170200-2106170200-oflxs892--0..> 17-Jun-2021 02:30              377230
wst04-VHDL20_DWPG_170400-2106170400-oflxs892--0..> 17-Jun-2021 05:00              376603
wst04-VHDL20_DWPG_170530-2106170530-oflxs892--0..> 17-Jun-2021 05:30              376564
wst04-VHDL20_DWPG_170630-2106170630-oflxs892--0..> 17-Jun-2021 06:30              376530
wst04-VHDL20_DWPG_170730-2106170730-oflxs892--0..> 17-Jun-2021 07:30              376890
wst04-VHDL20_DWPG_170800-2106170800-oflxs892--0..> 17-Jun-2021 08:30              421116
wst04-VHDL20_DWPG_170930-2106170930-oflxs892--0..> 17-Jun-2021 09:30              380028
wst04-VHDL20_DWPG_171030-2106171030-oflxs892--0..> 17-Jun-2021 10:30              380026
wst04-VHDL20_DWPG_171130-2106171130-oflxs892--0..> 17-Jun-2021 11:30              380066
wst04-VHDL20_DWPG_171300-2106171300-oflxs892--0..> 17-Jun-2021 12:30              380075
wst04-VHDL20_DWPG_171330-2106171330-oflxs892--0..> 17-Jun-2021 13:30              380066
wst04-VHDL20_DWPG_171430-2106171430-oflxs892--0..> 17-Jun-2021 14:30              380065
wst04-VHDL20_DWPG_171500-2106171500-oflxs892--0..> 17-Jun-2021 15:30              380093
wst04-VHDL20_DWPG_171630-2106171630-oflxs892--0..> 17-Jun-2021 16:30              380085
wst04-VHDL20_DWPG_171730-2106171730-oflxs892--0..> 17-Jun-2021 17:30              380445
wst04-VHDL20_DWPG_171800-2106171800-oflxs892--0..> 17-Jun-2021 18:30              379949
wst04-VHDL20_DWPG_171930-2106171930-oflxs892--0..> 17-Jun-2021 19:30              379933
wst04-VHDL20_DWPG_172030-2106172030-oflxs892--0..> 17-Jun-2021 20:30              379933
wst04-VHDL20_DWPG_180200-2106180200-oflxs892--0..> 18-Jun-2021 02:30              380913
wst04-VHDL20_DWPG_180400-2106180400-oflxs892--0..> 18-Jun-2021 05:00              381792
wst04-VHDL20_DWPG_180530-2106180530-oflxs892--0..> 18-Jun-2021 05:30              381771
wst04-VHDL20_DWPG_180630-2106180630-oflxs892--0..> 18-Jun-2021 06:30              381771
wst04-VHDL20_DWPG_180730-2106180730-oflxs892--0..> 18-Jun-2021 07:30              381771
wst04-VHDL20_DWPG_180800-2106180800-oflxs892--0..> 18-Jun-2021 08:30              426297
wst04-VHDL20_DWPG_180930-2106180930-oflxs892--0..> 18-Jun-2021 09:30              377753
wst04-VHDL20_DWPH_161030-2106161030-oflxs892--0..> 16-Jun-2021 10:30              274685
wst04-VHDL20_DWPH_161130-2106161130-oflxs892--0..> 16-Jun-2021 11:30              274685
wst04-VHDL20_DWPH_161300-2106161300-oflxs892--0..> 16-Jun-2021 12:30              274814
wst04-VHDL20_DWPH_161330-2106161330-oflxs892--0..> 16-Jun-2021 13:30              272177
wst04-VHDL20_DWPH_161430-2106161430-oflxs892--0..> 16-Jun-2021 14:30              272177
wst04-VHDL20_DWPH_161500-2106161500-oflxs892--0..> 16-Jun-2021 15:30              272038
wst04-VHDL20_DWPH_161630-2106161630-oflxs892--0..> 16-Jun-2021 16:30              272038
wst04-VHDL20_DWPH_161730-2106161730-oflxs892--0..> 16-Jun-2021 17:30              271918
wst04-VHDL20_DWPH_161800-2106161800-oflxs892--0..> 16-Jun-2021 18:30              316523
wst04-VHDL20_DWPH_161930-2106161930-oflxs892--0..> 16-Jun-2021 19:30              271918
wst04-VHDL20_DWPH_162030-2106162030-oflxs892--0..> 16-Jun-2021 20:30              271918
wst04-VHDL20_DWPH_170200-2106170200-oflxs892--0..> 17-Jun-2021 02:30              272511
wst04-VHDL20_DWPH_170400-2106170400-oflxs892--0..> 17-Jun-2021 05:00              272361
wst04-VHDL20_DWPH_170530-2106170530-oflxs892--0..> 17-Jun-2021 05:30              272338
wst04-VHDL20_DWPH_170630-2106170630-oflxs892--0..> 17-Jun-2021 06:30              272338
wst04-VHDL20_DWPH_170730-2106170730-oflxs892--0..> 17-Jun-2021 07:30              272338
wst04-VHDL20_DWPH_170800-2106170800-oflxs892--0..> 17-Jun-2021 08:30              316920
wst04-VHDL20_DWPH_170930-2106170930-oflxs892--0..> 17-Jun-2021 09:30              274645
wst04-VHDL20_DWPH_171030-2106171030-oflxs892--0..> 17-Jun-2021 10:30              274645
wst04-VHDL20_DWPH_171130-2106171130-oflxs892--0..> 17-Jun-2021 11:30              274613
wst04-VHDL20_DWPH_171300-2106171300-oflxs892--0..> 17-Jun-2021 12:30              274606
wst04-VHDL20_DWPH_171330-2106171330-oflxs892--0..> 17-Jun-2021 13:30              274613
wst04-VHDL20_DWPH_171430-2106171430-oflxs892--0..> 17-Jun-2021 14:30              274613
wst04-VHDL20_DWPH_171500-2106171500-oflxs892--0..> 17-Jun-2021 15:30              274699
wst04-VHDL20_DWPH_171630-2106171630-oflxs892--0..> 17-Jun-2021 16:30              274673
wst04-VHDL20_DWPH_171730-2106171730-oflxs892--0..> 17-Jun-2021 17:30              274681
wst04-VHDL20_DWPH_171800-2106171800-oflxs892--0..> 17-Jun-2021 18:30              319043
wst04-VHDL20_DWPH_171930-2106171930-oflxs892--0..> 17-Jun-2021 19:30              274402
wst04-VHDL20_DWPH_172030-2106172030-oflxs892--0..> 17-Jun-2021 20:30              274402
wst04-VHDL20_DWPH_180200-2106180200-oflxs892--0..> 18-Jun-2021 02:30              274952
wst04-VHDL20_DWPH_180400-2106180400-oflxs892--0..> 18-Jun-2021 05:00              275417
wst04-VHDL20_DWPH_180530-2106180530-oflxs892--0..> 18-Jun-2021 05:30              275378
wst04-VHDL20_DWPH_180630-2106180630-oflxs892--0..> 18-Jun-2021 06:30              275378
wst04-VHDL20_DWPH_180730-2106180730-oflxs892--0..> 18-Jun-2021 07:30              275378
wst04-VHDL20_DWPH_180800-2106180800-oflxs892--0..> 18-Jun-2021 08:30              320038
wst04-VHDL20_DWPH_180930-2106180930-oflxs892--0..> 18-Jun-2021 09:30              272009
wst04-VHDL20_DWSG_161300-2106161300-omedes--0.pdf  16-Jun-2021 13:45              385140
wst04-VHDL20_DWSG_161800-2106161800-omedes--0.pdf  16-Jun-2021 18:45              385016
wst04-VHDL20_DWSG_170200-2106170200-omedes--0.pdf  17-Jun-2021 02:45              385246
wst04-VHDL20_DWSG_170400-2106170400-omedes--0.pdf  17-Jun-2021 05:15              385192
wst04-VHDL20_DWSG_170800-2106170800-omedes--0.pdf  17-Jun-2021 08:45              385133
wst04-VHDL20_DWSG_171300-2106171300-omedes--0.pdf  17-Jun-2021 13:45              380246
wst04-VHDL20_DWSG_171800-2106171800-omedes--0.pdf  17-Jun-2021 18:45              380040
wst04-VHDL20_DWSG_180200-2106180200-omedes--0.pdf  18-Jun-2021 02:45              379741
wst04-VHDL20_DWSG_180400-2106180400-omedes--0.pdf  18-Jun-2021 05:15              379659
wst04-VHDL20_DWSG_180800-2106180800-omedes--0.pdf  18-Jun-2021 08:45              387040