Index of /weather/text_forecasts/txt/


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FPDL13_DWMZ_120600                                 12-Jul-2020 11:35                3962
FPDL13_DWMZ_130600                                 13-Jul-2020 07:52                4089
SXDL31_DWAV_120800                                 12-Jul-2020 06:38                6191
SXDL31_DWAV_121800                                 12-Jul-2020 16:47               10458
SXDL31_DWAV_130800                                 13-Jul-2020 07:27               11436
SXDL31_DWAV_131800                                 13-Jul-2020 16:48               13234
SXDL33_DWAV_120000                                 12-Jul-2020 09:44               13090
SXDL33_DWAV_130000                                 13-Jul-2020 08:29                6978
ber01-FWDL39_DWMS_121230-2007121230-dsw--0-ia5     12-Jul-2020 11:33                1069
ber01-FWDL39_DWMS_131230-2007131230-dsw--0-ia5     13-Jul-2020 11:55                1213
ber01-VHDL13_DWEH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:28                2209
ber01-VHDL13_DWEH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:58                2112
ber01-VHDL13_DWEH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:28                2136
ber01-VHDL13_DWEH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:28                2132
ber01-VHDL13_DWEH_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:28                2116
ber01-VHDL13_DWEH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:28                1962
ber01-VHDL13_DWEH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:28                2182
ber01-VHDL13_DWEH_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:58                2562
ber01-VHDL13_DWEH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:28                2628
ber01-VHDL13_DWEH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:28                2602
ber01-VHDL13_DWEH_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:28                2576
ber01-VHDL13_DWEH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:28                2350
ber01-VHDL13_DWHG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                2556
ber01-VHDL13_DWHG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2507
ber01-VHDL13_DWHG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                2445
ber01-VHDL13_DWHG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                2433
ber01-VHDL13_DWHG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                2250
ber01-VHDL13_DWHG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                2482
ber01-VHDL13_DWHG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                2469
ber01-VHDL13_DWHG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2497
ber01-VHDL13_DWHG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2473
ber01-VHDL13_DWHG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2178
ber01-VHDL13_DWHH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                2458
ber01-VHDL13_DWHH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2455
ber01-VHDL13_DWHH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                2388
ber01-VHDL13_DWHH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                2377
ber01-VHDL13_DWHH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                2171
ber01-VHDL13_DWHH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                2317
ber01-VHDL13_DWHH_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                2308
ber01-VHDL13_DWHH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2377
ber01-VHDL13_DWHH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2331
ber01-VHDL13_DWHH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2096
ber01-VHDL13_DWLG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1845
ber01-VHDL13_DWLG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                1851
ber01-VHDL13_DWLG_120533-2007120533-dsw--0-ia5     12-Jul-2020 05:33                1879
ber01-VHDL13_DWLG_120633-2007120633-dsw--0-ia5     12-Jul-2020 06:33                1879
ber01-VHDL13_DWLG_120733-2007120733-dsw--0-ia5     12-Jul-2020 07:33                1879
ber01-VHDL13_DWLG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1801
ber01-VHDL13_DWLG_120933-2007120933-dsw--0-ia5     12-Jul-2020 09:33                1832
ber01-VHDL13_DWLG_121033-2007121033-dsw--0-ia5     12-Jul-2020 10:33                1777
ber01-VHDL13_DWLG_121133-2007121133-dsw--0-ia5     12-Jul-2020 11:33                1777
ber01-VHDL13_DWLG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                1758
ber01-VHDL13_DWLG_121333-2007121333-dsw--0-ia5     12-Jul-2020 13:33                1756
ber01-VHDL13_DWLG_121433-2007121433-dsw--0-ia5     12-Jul-2020 14:33                1756
ber01-VHDL13_DWLG_121533-2007121533-dsw--0-ia5     12-Jul-2020 15:33                1756
ber01-VHDL13_DWLG_121633-2007121633-dsw--0-ia5     12-Jul-2020 16:33                1756
ber01-VHDL13_DWLG_121733-2007121733-dsw--0-ia5     12-Jul-2020 17:33                1705
ber01-VHDL13_DWLG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1677
ber01-VHDL13_DWLG_121933-2007121933-dsw--0-ia5     12-Jul-2020 19:33                1705
ber01-VHDL13_DWLG_122033-2007122033-dsw--0-ia5     12-Jul-2020 20:33                1705
ber01-VHDL13_DWLG_130033-2007130033-dsw--0-ia5     13-Jul-2020 00:33                1782
ber01-VHDL13_DWLG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1748
ber01-VHDL13_DWLG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                1850
ber01-VHDL13_DWLG_130533-2007130533-dsw--0-ia5     13-Jul-2020 05:33                1878
ber01-VHDL13_DWLG_130633-2007130633-dsw--0-ia5     13-Jul-2020 06:33                1878
ber01-VHDL13_DWLG_130733-2007130733-dsw--0-ia5     13-Jul-2020 07:33                1817
ber01-VHDL13_DWLG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                1786
ber01-VHDL13_DWLG_130933-2007130933-dsw--0-ia5     13-Jul-2020 09:33                1848
ber01-VHDL13_DWLG_131033-2007131033-dsw--0-ia5     13-Jul-2020 10:33                1848
ber01-VHDL13_DWLG_131133-2007131133-dsw--0-ia5     13-Jul-2020 11:33                1881
ber01-VHDL13_DWLG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                1817
ber01-VHDL13_DWLG_131333-2007131333-dsw--0-ia5     13-Jul-2020 13:33                1845
ber01-VHDL13_DWLG_131433-2007131433-dsw--0-ia5     13-Jul-2020 14:33                1845
ber01-VHDL13_DWLG_131533-2007131533-dsw--0-ia5     13-Jul-2020 15:33                1845
ber01-VHDL13_DWLG_131633-2007131633-dsw--0-ia5     13-Jul-2020 16:33                1790
ber01-VHDL13_DWLG_131733-2007131733-dsw--0-ia5     13-Jul-2020 17:33                1729
ber01-VHDL13_DWLG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                1701
ber01-VHDL13_DWLG_131933-2007131933-dsw--0-ia5     13-Jul-2020 19:33                1729
ber01-VHDL13_DWLG_132033-2007132033-dsw--0-ia5     13-Jul-2020 20:33                1729
ber01-VHDL13_DWLG_140033-2007140033-dsw--0-ia5     14-Jul-2020 00:33                1869
ber01-VHDL13_DWLH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1854
ber01-VHDL13_DWLH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                1860
ber01-VHDL13_DWLH_120533-2007120533-dsw--0-ia5     12-Jul-2020 05:33                1888
ber01-VHDL13_DWLH_120633-2007120633-dsw--0-ia5     12-Jul-2020 06:33                1888
ber01-VHDL13_DWLH_120733-2007120733-dsw--0-ia5     12-Jul-2020 07:33                1888
ber01-VHDL13_DWLH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1813
ber01-VHDL13_DWLH_120933-2007120933-dsw--0-ia5     12-Jul-2020 09:33                1841
ber01-VHDL13_DWLH_121033-2007121033-dsw--0-ia5     12-Jul-2020 10:33                1776
ber01-VHDL13_DWLH_121133-2007121133-dsw--0-ia5     12-Jul-2020 11:33                1776
ber01-VHDL13_DWLH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                1779
ber01-VHDL13_DWLH_121333-2007121333-dsw--0-ia5     12-Jul-2020 13:33                1756
ber01-VHDL13_DWLH_121433-2007121433-dsw--0-ia5     12-Jul-2020 14:33                1756
ber01-VHDL13_DWLH_121533-2007121533-dsw--0-ia5     12-Jul-2020 15:33                1756
ber01-VHDL13_DWLH_121633-2007121633-dsw--0-ia5     12-Jul-2020 16:33                1756
ber01-VHDL13_DWLH_121733-2007121733-dsw--0-ia5     12-Jul-2020 17:33                1653
ber01-VHDL13_DWLH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1625
ber01-VHDL13_DWLH_121933-2007121933-dsw--0-ia5     12-Jul-2020 19:33                1653
ber01-VHDL13_DWLH_122033-2007122033-dsw--0-ia5     12-Jul-2020 20:33                1653
ber01-VHDL13_DWLH_130033-2007130033-dsw--0-ia5     13-Jul-2020 00:33                1793
ber01-VHDL13_DWLH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1755
ber01-VHDL13_DWLH_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                1827
ber01-VHDL13_DWLH_130533-2007130533-dsw--0-ia5     13-Jul-2020 05:33                1855
ber01-VHDL13_DWLH_130633-2007130633-dsw--0-ia5     13-Jul-2020 06:33                1855
ber01-VHDL13_DWLH_130733-2007130733-dsw--0-ia5     13-Jul-2020 07:33                1814
ber01-VHDL13_DWLH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                1786
ber01-VHDL13_DWLH_130933-2007130933-dsw--0-ia5     13-Jul-2020 09:33                1815
ber01-VHDL13_DWLH_131033-2007131033-dsw--0-ia5     13-Jul-2020 10:33                1815
ber01-VHDL13_DWLH_131133-2007131133-dsw--0-ia5     13-Jul-2020 11:33                2027
ber01-VHDL13_DWLH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2096
ber01-VHDL13_DWLH_131333-2007131333-dsw--0-ia5     13-Jul-2020 13:33                2124
ber01-VHDL13_DWLH_131433-2007131433-dsw--0-ia5     13-Jul-2020 14:33                2124
ber01-VHDL13_DWLH_131533-2007131533-dsw--0-ia5     13-Jul-2020 15:33                2124
ber01-VHDL13_DWLH_131633-2007131633-dsw--0-ia5     13-Jul-2020 16:33                2067
ber01-VHDL13_DWLH_131733-2007131733-dsw--0-ia5     13-Jul-2020 17:33                2001
ber01-VHDL13_DWLH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                1973
ber01-VHDL13_DWLH_131933-2007131933-dsw--0-ia5     13-Jul-2020 19:33                2001
ber01-VHDL13_DWLH_132033-2007132033-dsw--0-ia5     13-Jul-2020 20:33                2001
ber01-VHDL13_DWLH_140033-2007140033-dsw--0-ia5     14-Jul-2020 00:33                2105
ber01-VHDL13_DWLI_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1838
ber01-VHDL13_DWLI_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                1844
ber01-VHDL13_DWLI_120533-2007120533-dsw--0-ia5     12-Jul-2020 05:33                1872
ber01-VHDL13_DWLI_120633-2007120633-dsw--0-ia5     12-Jul-2020 06:33                1872
ber01-VHDL13_DWLI_120733-2007120733-dsw--0-ia5     12-Jul-2020 07:33                1872
ber01-VHDL13_DWLI_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1797
ber01-VHDL13_DWLI_120933-2007120933-dsw--0-ia5     12-Jul-2020 09:33                1825
ber01-VHDL13_DWLI_121033-2007121033-dsw--0-ia5     12-Jul-2020 10:33                1770
ber01-VHDL13_DWLI_121133-2007121133-dsw--0-ia5     12-Jul-2020 11:33                1770
ber01-VHDL13_DWLI_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                1765
ber01-VHDL13_DWLI_121333-2007121333-dsw--0-ia5     12-Jul-2020 13:33                1763
ber01-VHDL13_DWLI_121433-2007121433-dsw--0-ia5     12-Jul-2020 14:33                1763
ber01-VHDL13_DWLI_121533-2007121533-dsw--0-ia5     12-Jul-2020 15:33                1763
ber01-VHDL13_DWLI_121633-2007121633-dsw--0-ia5     12-Jul-2020 16:33                1763
ber01-VHDL13_DWLI_121733-2007121733-dsw--0-ia5     12-Jul-2020 17:33                1643
ber01-VHDL13_DWLI_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1615
ber01-VHDL13_DWLI_121933-2007121933-dsw--0-ia5     12-Jul-2020 19:33                1643
ber01-VHDL13_DWLI_122033-2007122033-dsw--0-ia5     12-Jul-2020 20:33                1643
ber01-VHDL13_DWLI_130033-2007130033-dsw--0-ia5     13-Jul-2020 00:33                1788
ber01-VHDL13_DWLI_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1754
ber01-VHDL13_DWLI_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                1828
ber01-VHDL13_DWLI_130533-2007130533-dsw--0-ia5     13-Jul-2020 05:33                1856
ber01-VHDL13_DWLI_130633-2007130633-dsw--0-ia5     13-Jul-2020 06:33                1856
ber01-VHDL13_DWLI_130733-2007130733-dsw--0-ia5     13-Jul-2020 07:33                1795
ber01-VHDL13_DWLI_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                1767
ber01-VHDL13_DWLI_130933-2007130933-dsw--0-ia5     13-Jul-2020 09:33                1814
ber01-VHDL13_DWLI_131033-2007131033-dsw--0-ia5     13-Jul-2020 10:33                1814
ber01-VHDL13_DWLI_131133-2007131133-dsw--0-ia5     13-Jul-2020 11:33                1964
ber01-VHDL13_DWLI_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2116
ber01-VHDL13_DWLI_131333-2007131333-dsw--0-ia5     13-Jul-2020 13:33                2144
ber01-VHDL13_DWLI_131433-2007131433-dsw--0-ia5     13-Jul-2020 14:33                2144
ber01-VHDL13_DWLI_131533-2007131533-dsw--0-ia5     13-Jul-2020 15:33                2144
ber01-VHDL13_DWLI_131633-2007131633-dsw--0-ia5     13-Jul-2020 16:33                2089
ber01-VHDL13_DWLI_131733-2007131733-dsw--0-ia5     13-Jul-2020 17:33                2017
ber01-VHDL13_DWLI_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                1989
ber01-VHDL13_DWLI_131933-2007131933-dsw--0-ia5     13-Jul-2020 19:33                2017
ber01-VHDL13_DWLI_132033-2007132033-dsw--0-ia5     13-Jul-2020 20:33                2017
ber01-VHDL13_DWLI_140033-2007140033-dsw--0-ia5     14-Jul-2020 00:33                2121
ber01-VHDL13_DWMG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                2170
ber01-VHDL13_DWMG_120300-2007120300-dsw--0-ia5     12-Jul-2020 03:30                2170
ber01-VHDL13_DWMG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2057
ber01-VHDL13_DWMG_120500-2007120500-dsw--0-ia5     12-Jul-2020 05:30                2057
ber01-VHDL13_DWMG_120600-2007120600-dsw--0-ia5     12-Jul-2020 06:30                2057
ber01-VHDL13_DWMG_120700-2007120700-dsw--0-ia5     12-Jul-2020 07:30                2057
ber01-VHDL13_DWMG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                2163
ber01-VHDL13_DWMG_120900-2007120900-dsw--0-ia5     12-Jul-2020 09:30                2163
ber01-VHDL13_DWMG_121000-2007121000-dsw--0-ia5     12-Jul-2020 10:30                2163
ber01-VHDL13_DWMG_121100-2007121100-dsw--0-ia5     12-Jul-2020 11:30                2163
ber01-VHDL13_DWMG_121200-2007121200-dsw--0-ia5     12-Jul-2020 12:30                2050
ber01-VHDL13_DWMG_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:30                1777
ber01-VHDL13_DWMG_121400-2007121400-dsw--0-ia5     12-Jul-2020 14:30                1777
ber01-VHDL13_DWMG_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:30                1777
ber01-VHDL13_DWMG_121600-2007121600-dsw--0-ia5     12-Jul-2020 16:30                1775
ber01-VHDL13_DWMG_121700-2007121700-dsw--0-ia5     12-Jul-2020 17:30                1678
ber01-VHDL13_DWMG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1771
ber01-VHDL13_DWMG_121900-2007121900-dsw--0-ia5     12-Jul-2020 19:30                1771
ber01-VHDL13_DWMG_122000-2007122000-dsw--0-ia5     12-Jul-2020 20:30                1771
ber01-VHDL13_DWMG_122100-2007122100-dsw--0-ia5     12-Jul-2020 21:30                1771
ber01-VHDL13_DWMG_122200-2007122200-dsw--0-ia5     12-Jul-2020 22:30                2101
ber01-VHDL13_DWMG_122300-2007122300-dsw--0-ia5     12-Jul-2020 23:30                2101
ber01-VHDL13_DWMG_130000-2007130000-dsw--0-ia5     13-Jul-2020 00:30                2101
ber01-VHDL13_DWMG_130100-2007130100-dsw--0-ia5     13-Jul-2020 01:30                2101
ber01-VHDL13_DWMG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                2101
ber01-VHDL13_DWMG_130300-2007130300-dsw--0-ia5     13-Jul-2020 03:30                2101
ber01-VHDL13_DWMG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                2105
ber01-VHDL13_DWMG_130500-2007130500-dsw--0-ia5     13-Jul-2020 05:30                2105
ber01-VHDL13_DWMG_130600-2007130600-dsw--0-ia5     13-Jul-2020 06:30                2105
ber01-VHDL13_DWMG_130700-2007130700-dsw--0-ia5     13-Jul-2020 07:30                2105
ber01-VHDL13_DWMG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2211
ber01-VHDL13_DWMG_130900-2007130900-dsw--0-ia5     13-Jul-2020 09:30                2211
ber01-VHDL13_DWMG_131000-2007131000-dsw--0-ia5     13-Jul-2020 10:30                2211
ber01-VHDL13_DWMG_131100-2007131100-dsw--0-ia5     13-Jul-2020 11:30                2211
ber01-VHDL13_DWMG_131200-2007131200-dsw--0-ia5     13-Jul-2020 12:30                2318
ber01-VHDL13_DWMG_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:30                2472
ber01-VHDL13_DWMG_131400-2007131400-dsw--0-ia5     13-Jul-2020 14:30                2506
ber01-VHDL13_DWMG_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:30                2506
ber01-VHDL13_DWMG_131600-2007131600-dsw--0-ia5     13-Jul-2020 16:30                2506
ber01-VHDL13_DWMG_131700-2007131700-dsw--0-ia5     13-Jul-2020 17:30                2349
ber01-VHDL13_DWMG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2349
ber01-VHDL13_DWMG_131900-2007131900-dsw--0-ia5     13-Jul-2020 19:30                2349
ber01-VHDL13_DWMG_132000-2007132000-dsw--0-ia5     13-Jul-2020 20:30                2357
ber01-VHDL13_DWMG_132100-2007132100-dsw--0-ia5     13-Jul-2020 21:30                2357
ber01-VHDL13_DWMG_132200-2007132200-dsw--0-ia5     13-Jul-2020 22:30                2521
ber01-VHDL13_DWMG_132300-2007132300-dsw--0-ia5     13-Jul-2020 23:30                2521
ber01-VHDL13_DWMG_140000-2007140000-dsw--0-ia5     14-Jul-2020 00:30                2521
ber01-VHDL13_DWMG_140100-2007140100-dsw--0-ia5     14-Jul-2020 01:30                2521
ber01-VHDL13_DWMO_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                2156
ber01-VHDL13_DWMO_120300-2007120300-dsw--0-ia5     12-Jul-2020 03:30                2156
ber01-VHDL13_DWMO_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2159
ber01-VHDL13_DWMO_120500-2007120500-dsw--0-ia5     12-Jul-2020 05:30                2159
ber01-VHDL13_DWMO_120600-2007120600-dsw--0-ia5     12-Jul-2020 06:30                2159
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ber01-VHDL13_DWMP_120500-2007120500-dsw--0-ia5     12-Jul-2020 05:30                2142
ber01-VHDL13_DWMP_120600-2007120600-dsw--0-ia5     12-Jul-2020 06:30                2142
ber01-VHDL13_DWMP_120700-2007120700-dsw--0-ia5     12-Jul-2020 07:30                2142
ber01-VHDL13_DWMP_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                2201
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ber01-VHDL13_DWMP_121100-2007121100-dsw--0-ia5     12-Jul-2020 11:30                2201
ber01-VHDL13_DWMP_121200-2007121200-dsw--0-ia5     12-Jul-2020 12:30                2105
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ber01-VHDL13_DWMP_121400-2007121400-dsw--0-ia5     12-Jul-2020 14:30                1816
ber01-VHDL13_DWMP_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:30                1816
ber01-VHDL13_DWMP_121600-2007121600-dsw--0-ia5     12-Jul-2020 16:30                1814
ber01-VHDL13_DWMP_121700-2007121700-dsw--0-ia5     12-Jul-2020 17:30                1717
ber01-VHDL13_DWMP_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1774
ber01-VHDL13_DWMP_121900-2007121900-dsw--0-ia5     12-Jul-2020 19:30                1774
ber01-VHDL13_DWMP_122000-2007122000-dsw--0-ia5     12-Jul-2020 20:30                1774
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ber01-VHDL13_DWMP_130500-2007130500-dsw--0-ia5     13-Jul-2020 05:30                2082
ber01-VHDL13_DWMP_130600-2007130600-dsw--0-ia5     13-Jul-2020 06:30                2082
ber01-VHDL13_DWMP_130700-2007130700-dsw--0-ia5     13-Jul-2020 07:30                2082
ber01-VHDL13_DWMP_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2084
ber01-VHDL13_DWMP_130900-2007130900-dsw--0-ia5     13-Jul-2020 09:30                2084
ber01-VHDL13_DWMP_131000-2007131000-dsw--0-ia5     13-Jul-2020 10:30                2084
ber01-VHDL13_DWMP_131100-2007131100-dsw--0-ia5     13-Jul-2020 11:30                2084
ber01-VHDL13_DWMP_131200-2007131200-dsw--0-ia5     13-Jul-2020 12:30                2189
ber01-VHDL13_DWMP_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:30                2519
ber01-VHDL13_DWMP_131400-2007131400-dsw--0-ia5     13-Jul-2020 14:30                2572
ber01-VHDL13_DWMP_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:30                2572
ber01-VHDL13_DWMP_131600-2007131600-dsw--0-ia5     13-Jul-2020 16:30                2572
ber01-VHDL13_DWMP_131700-2007131700-dsw--0-ia5     13-Jul-2020 17:30                2415
ber01-VHDL13_DWMP_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2415
ber01-VHDL13_DWMP_131900-2007131900-dsw--0-ia5     13-Jul-2020 19:30                2415
ber01-VHDL13_DWMP_132000-2007132000-dsw--0-ia5     13-Jul-2020 20:30                2411
ber01-VHDL13_DWMP_132100-2007132100-dsw--0-ia5     13-Jul-2020 21:30                2411
ber01-VHDL13_DWMP_132200-2007132200-dsw--0-ia5     13-Jul-2020 22:30                2588
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ber01-VHDL13_DWOG_120100-2007120100-dsw--0-ia5     12-Jul-2020 01:45                3360
ber01-VHDL13_DWOG_120300-2007120300-dsw--0-ia5     12-Jul-2020 03:00                3360
ber01-VHDL13_DWOG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:15                3640
ber01-VHDL13_DWOG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:00                3663
ber01-VHDL13_DWOG_121700-2007121700-dsw--0-ia5     12-Jul-2020 17:30                3437
ber01-VHDL13_DWOG_130100-2007130100-dsw--0-ia5     13-Jul-2020 01:45                3751
ber01-VHDL13_DWOG_130300-2007130300-dsw--0-ia5     13-Jul-2020 03:00                3671
ber01-VHDL13_DWOG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:15                3777
ber01-VHDL13_DWOG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:00                3986
ber01-VHDL13_DWOG_131700-2007131700-dsw--0-ia5     13-Jul-2020 17:30                3993
ber01-VHDL13_DWOH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:28                1839
ber01-VHDL13_DWOH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:58                1800
ber01-VHDL13_DWOH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:28                1849
ber01-VHDL13_DWOH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:28                1845
ber01-VHDL13_DWOH_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:28                1826
ber01-VHDL13_DWOH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:28                1694
ber01-VHDL13_DWOH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:28                1908
ber01-VHDL13_DWOH_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:58                2363
ber01-VHDL13_DWOH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:28                2430
ber01-VHDL13_DWOH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:28                2403
ber01-VHDL13_DWOH_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:28                2364
ber01-VHDL13_DWOH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:28                2181
ber01-VHDL13_DWOI_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:28                1968
ber01-VHDL13_DWOI_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:58                1917
ber01-VHDL13_DWOI_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:28                2010
ber01-VHDL13_DWOI_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:28                2000
ber01-VHDL13_DWOI_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:28                1984
ber01-VHDL13_DWOI_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:28                1859
ber01-VHDL13_DWOI_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:28                1976
ber01-VHDL13_DWOI_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:58                2444
ber01-VHDL13_DWOI_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:28                2516
ber01-VHDL13_DWOI_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:28                2483
ber01-VHDL13_DWOI_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:28                2444
ber01-VHDL13_DWOI_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:28                2325
ber01-VHDL13_DWON_120253-2007120253-dsw--0-ia5     12-Jul-2020 02:53                3544
ber01-VHDL13_DWON_120516-2007120516-dsw--0-ia5     12-Jul-2020 05:16                4051
ber01-VHDL13_DWON_120644-2007120644-dsw--0-ia5     12-Jul-2020 06:44                4413
ber01-VHDL13_DWON_120821-2007120821-dsw--0-ia5     12-Jul-2020 08:21                4413
ber01-VHDL13_DWON_121123-2007121123-dsw--0-ia5     12-Jul-2020 11:23                4471
ber01-VHDL13_DWON_121527-2007121527-dsw--0-ia5     12-Jul-2020 15:27                4242
ber01-VHDL13_DWON_121723-2007121723-dsw--0-ia5     12-Jul-2020 17:23                3485
ber01-VHDL13_DWON_121828-2007121828-dsw--0-ia5     12-Jul-2020 18:28                3759
ber01-VHDL13_DWON_121844-2007121844-dsw--0-ia5     12-Jul-2020 18:44                3759
ber01-VHDL13_DWON_122005-2007122005-dsw--0-ia5     12-Jul-2020 20:05                3775
ber01-VHDL13_DWON_122150-2007122150-dsw--0-ia5     12-Jul-2020 21:50                3773
ber01-VHDL13_DWON_130002-2007130002-dsw--0-ia5     13-Jul-2020 00:02                4201
ber01-VHDL13_DWON_130210-2007130210-dsw--0-ia5     13-Jul-2020 02:10                4056
ber01-VHDL13_DWON_130229-2007130229-dsw--0-ia5     13-Jul-2020 02:29                4056
ber01-VHDL13_DWON_130259-2007130259-dsw--0-ia5     13-Jul-2020 02:59                4056
ber01-VHDL13_DWON_130518-2007130518-dsw--0-ia5     13-Jul-2020 05:18                3724
ber01-VHDL13_DWON_130658-2007130658-dsw--0-ia5     13-Jul-2020 06:58                4727
ber01-VHDL13_DWON_131033-2007131033-dsw--0-ia5     13-Jul-2020 10:33                4769
ber01-VHDL13_DWON_131135-2007131135-dsw--0-ia5     13-Jul-2020 11:35                4769
ber01-VHDL13_DWON_131435-2007131435-dsw--0-ia5     13-Jul-2020 14:36                4565
ber01-VHDL13_DWON_131704-2007131704-dsw--0-ia5     13-Jul-2020 17:04                4135
ber01-VHDL13_DWON_131833-2007131833-dsw--0-ia5     13-Jul-2020 18:33                3884
ber01-VHDL13_DWON_132159-2007132159-dsw--0-ia5     13-Jul-2020 21:59                3862
ber01-VHDL13_DWON_140002-2007140002-dsw--0-ia5     14-Jul-2020 00:02                4343
ber01-VHDL13_DWON_140136-2007140136-dsw--0-ia5     14-Jul-2020 01:36                4245
ber01-VHDL13_DWON_140137-2007140137-dsw--0-ia5     14-Jul-2020 01:37                4223
ber01-VHDL13_DWPG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1969
ber01-VHDL13_DWPG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2029
ber01-VHDL13_DWPG_120530-2007120530-dsw--0-ia5     12-Jul-2020 05:30                2024
ber01-VHDL13_DWPG_120630-2007120630-dsw--0-ia5     12-Jul-2020 06:30                2024
ber01-VHDL13_DWPG_120730-2007120730-dsw--0-ia5     12-Jul-2020 07:30                2024
ber01-VHDL13_DWPG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1975
ber01-VHDL13_DWPG_120930-2007120930-dsw--0-ia5     12-Jul-2020 09:30                1974
ber01-VHDL13_DWPG_121030-2007121030-dsw--0-ia5     12-Jul-2020 10:30                1974
ber01-VHDL13_DWPG_121130-2007121130-dsw--0-ia5     12-Jul-2020 11:30                1927
ber01-VHDL13_DWPG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                1932
ber01-VHDL13_DWPG_121330-2007121330-dsw--0-ia5     12-Jul-2020 13:30                1931
ber01-VHDL13_DWPG_121430-2007121430-dsw--0-ia5     12-Jul-2020 14:30                1931
ber01-VHDL13_DWPG_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:30                1931
ber01-VHDL13_DWPG_121630-2007121630-dsw--0-ia5     12-Jul-2020 16:30                1930
ber01-VHDL13_DWPG_121730-2007121730-dsw--0-ia5     12-Jul-2020 17:30                1930
ber01-VHDL13_DWPG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                2174
ber01-VHDL13_DWPG_121930-2007121930-dsw--0-ia5     12-Jul-2020 19:30                2173
ber01-VHDL13_DWPG_122030-2007122030-dsw--0-ia5     12-Jul-2020 20:30                2173
ber01-VHDL13_DWPG_130030-2007130030-dsw--0-ia5     13-Jul-2020 00:30                2186
ber01-VHDL13_DWPG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                2207
ber01-VHDL13_DWPG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                2207
ber01-VHDL13_DWPG_130530-2007130530-dsw--0-ia5     13-Jul-2020 05:30                2186
ber01-VHDL13_DWPG_130630-2007130630-dsw--0-ia5     13-Jul-2020 06:30                2176
ber01-VHDL13_DWPG_130730-2007130730-dsw--0-ia5     13-Jul-2020 07:30                2176
ber01-VHDL13_DWPG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2241
ber01-VHDL13_DWPG_130800_COR-2007130800-dsw--0-ia5 13-Jul-2020 10:35                2172
ber01-VHDL13_DWPG_130930-2007130930-dsw--0-ia5     13-Jul-2020 09:30                2240
ber01-VHDL13_DWPG_131030-2007131030-dsw--0-ia5     13-Jul-2020 10:30                2240
ber01-VHDL13_DWPG_131130-2007131130-dsw--0-ia5     13-Jul-2020 11:30                2178
ber01-VHDL13_DWPG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2115
ber01-VHDL13_DWPG_131330-2007131330-dsw--0-ia5     13-Jul-2020 13:30                2114
ber01-VHDL13_DWPG_131430-2007131430-dsw--0-ia5     13-Jul-2020 14:30                2114
ber01-VHDL13_DWPG_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:30                2107
ber01-VHDL13_DWPG_131630-2007131630-dsw--0-ia5     13-Jul-2020 16:30                2106
ber01-VHDL13_DWPG_131730-2007131730-dsw--0-ia5     13-Jul-2020 17:30                2106
ber01-VHDL13_DWPG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2083
ber01-VHDL13_DWPG_131930-2007131930-dsw--0-ia5     13-Jul-2020 19:30                2082
ber01-VHDL13_DWPG_132030-2007132030-dsw--0-ia5     13-Jul-2020 20:30                2082
ber01-VHDL13_DWPG_140030-2007140030-dsw--0-ia5     14-Jul-2020 00:30                2380
ber01-VHDL13_DWPH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                2106
ber01-VHDL13_DWPH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                2326
ber01-VHDL13_DWPH_120530-2007120530-dsw--0-ia5     12-Jul-2020 05:30                2378
ber01-VHDL13_DWPH_120630-2007120630-dsw--0-ia5     12-Jul-2020 06:30                2378
ber01-VHDL13_DWPH_120730-2007120730-dsw--0-ia5     12-Jul-2020 07:30                2378
ber01-VHDL13_DWPH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                2424
ber01-VHDL13_DWPH_120930-2007120930-dsw--0-ia5     12-Jul-2020 09:30                2424
ber01-VHDL13_DWPH_121030-2007121030-dsw--0-ia5     12-Jul-2020 10:30                2424
ber01-VHDL13_DWPH_121130-2007121130-dsw--0-ia5     12-Jul-2020 11:30                2400
ber01-VHDL13_DWPH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                2266
ber01-VHDL13_DWPH_121330-2007121330-dsw--0-ia5     12-Jul-2020 13:30                2279
ber01-VHDL13_DWPH_121430-2007121430-dsw--0-ia5     12-Jul-2020 14:30                2279
ber01-VHDL13_DWPH_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:30                2265
ber01-VHDL13_DWPH_121630-2007121630-dsw--0-ia5     12-Jul-2020 16:30                2265
ber01-VHDL13_DWPH_121730-2007121730-dsw--0-ia5     12-Jul-2020 17:30                1963
ber01-VHDL13_DWPH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                2100
ber01-VHDL13_DWPH_121930-2007121930-dsw--0-ia5     12-Jul-2020 19:30                2100
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ber01-VHDL13_DWPH_130030-2007130030-dsw--0-ia5     13-Jul-2020 00:30                2142
ber01-VHDL13_DWPH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                2105
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ber01-VHDL13_DWPH_130530-2007130530-dsw--0-ia5     13-Jul-2020 05:30                2046
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ber01-VHDL13_DWPH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                2187
ber01-VHDL13_DWPH_130800_COR-2007130800-dsw--0-ia5 13-Jul-2020 10:36                2123
ber01-VHDL13_DWPH_130930-2007130930-dsw--0-ia5     13-Jul-2020 09:30                2187
ber01-VHDL13_DWPH_131030-2007131030-dsw--0-ia5     13-Jul-2020 10:30                2187
ber01-VHDL13_DWPH_131130-2007131130-dsw--0-ia5     13-Jul-2020 11:30                2143
ber01-VHDL13_DWPH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2104
ber01-VHDL13_DWPH_131330-2007131330-dsw--0-ia5     13-Jul-2020 13:30                2104
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ber01-VHDL13_DWPH_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:30                2096
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ber01-VHDL13_DWPH_131730-2007131730-dsw--0-ia5     13-Jul-2020 17:30                2096
ber01-VHDL13_DWPH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2314
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ber01-VHDL13_DWSG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1706
ber01-VHDL13_DWSG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:30                1768
ber01-VHDL13_DWSG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1727
ber01-VHDL13_DWSG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1992
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ber01-VHDL13_DWSG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:30                2593
ber01-VHDL13_DWSG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2229
ber01-VHDL13_DWSN_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1695
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ber01-VHDL13_DWSN_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1668
ber01-VHDL13_DWSN_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:30                1692
ber01-VHDL13_DWSN_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1533
ber01-VHDL13_DWSN_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1785
ber01-VHDL13_DWSN_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                1855
ber01-VHDL13_DWSN_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                1851
ber01-VHDL13_DWSN_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:30                1931
ber01-VHDL13_DWSN_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                1714
ber01-VHDL13_DWSO_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1744
ber01-VHDL13_DWSO_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                1739
ber01-VHDL13_DWSO_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1710
ber01-VHDL13_DWSO_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:30                1737
ber01-VHDL13_DWSO_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1695
ber01-VHDL13_DWSO_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1951
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ber01-VHDL13_DWSO_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:30                2504
ber01-VHDL13_DWSO_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2126
ber01-VHDL13_DWSP_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:30                1763
ber01-VHDL13_DWSP_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:30                1728
ber01-VHDL13_DWSP_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:30                1703
ber01-VHDL13_DWSP_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:30                1729
ber01-VHDL13_DWSP_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:30                1588
ber01-VHDL13_DWSP_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:30                1817
ber01-VHDL13_DWSP_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:30                1812
ber01-VHDL13_DWSP_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:30                1808
ber01-VHDL13_DWSP_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:30                2416
ber01-VHDL13_DWSP_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:30                2086
ber01-VHDL17_DWOG_121200-2007121200-dsw--0-ia5     12-Jul-2020 10:50                2938
ber01-VHDL17_DWOG_131200-2007131200-dsw--0-ia5     13-Jul-2020 11:02                2711
ber01-VHDL20_DWHG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2746
ber01-VHDL20_DWHG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:45                2696
ber01-VHDL20_DWHG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2634
ber01-VHDL20_DWHG_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:45                2622
ber01-VHDL20_DWHG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                2439
ber01-VHDL20_DWHG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2672
ber01-VHDL20_DWHG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:45                2658
ber01-VHDL20_DWHG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2686
ber01-VHDL20_DWHG_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:45                2651
ber01-VHDL20_DWHG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2367
ber01-VHDL20_DWHH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2651
ber01-VHDL20_DWHH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:45                2648
ber01-VHDL20_DWHH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2581
ber01-VHDL20_DWHH_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:45                2570
ber01-VHDL20_DWHH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                2364
ber01-VHDL20_DWHH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2510
ber01-VHDL20_DWHH_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:45                2501
ber01-VHDL20_DWHH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2570
ber01-VHDL20_DWHH_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:45                2513
ber01-VHDL20_DWHH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2289
gts01-VHDL12_DWON_120115-2007120145-afsv--30-ia5   12-Jul-2020 01:45                3291
gts01-VHDL12_DWON_120530-2007120530-afsv--48-ia5   12-Jul-2020 05:30                3809
gts01-VHDL12_DWON_120815-2007120815-afsv--29-ia5   12-Jul-2020 08:15                3852
gts01-VHDL12_DWON_121330-2007121230-afsv--70-ia5   12-Jul-2020 12:30                3914
gts01-VHDL12_DWON_121815-2007121745-afsv--06-ia5   12-Jul-2020 17:45                2845
gts01-VHDL12_DWON_130115-2007130145-afsv--48-ia5   13-Jul-2020 01:45                3808
gts01-VHDL12_DWON_130530-2007130530-afsv--63-ia5   13-Jul-2020 05:30                3319
gts01-VHDL12_DWON_130815-2007130815-afsv--34-ia5   13-Jul-2020 08:15                4234
gts01-VHDL12_DWON_131330-2007131230-afsv--78-ia5   13-Jul-2020 12:30                4277
gts01-VHDL12_DWON_131815-2007131745-afsv--22-ia5   13-Jul-2020 17:45                3607
pid-VHDL12_DWEH_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:28                1889
pid-VHDL12_DWEH_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:28                 390
pid-VHDL12_DWHG_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                2109
pid-VHDL12_DWHG_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                2058
pid-VHDL12_DWHG_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                2153
pid-VHDL12_DWHG_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                2138
pid-VHDL12_DWHH_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1993
pid-VHDL12_DWHH_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                1990
pid-VHDL12_DWHH_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                2027
pid-VHDL12_DWHH_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                2018
pid-VHDL12_DWLG_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1511
pid-VHDL12_DWLG_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                1517
pid-VHDL12_DWLG_120800-2007120800-dsw--0-ia5       12-Jul-2020 08:30                1470
pid-VHDL12_DWLG_121300-2007121300-dsw--0-ia5       12-Jul-2020 12:30                1424
pid-VHDL12_DWLG_121800-2007121800-dsw--0-ia5       12-Jul-2020 18:30                1343
pid-VHDL12_DWLG_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                1480
pid-VHDL12_DWLG_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                1576
pid-VHDL12_DWLG_130800-2007130800-dsw--0-ia5       13-Jul-2020 08:30                1515
pid-VHDL12_DWLG_131300-2007131300-dsw--0-ia5       13-Jul-2020 12:30                1543
pid-VHDL12_DWLG_131800-2007131800-dsw--0-ia5       13-Jul-2020 18:30                1439
pid-VHDL12_DWLH_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1524
pid-VHDL12_DWLH_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                1530
pid-VHDL12_DWLH_120800-2007120800-dsw--0-ia5       12-Jul-2020 08:30                1483
pid-VHDL12_DWLH_121300-2007121300-dsw--0-ia5       12-Jul-2020 12:30                1449
pid-VHDL12_DWLH_121800-2007121800-dsw--0-ia5       12-Jul-2020 18:30                1295
pid-VHDL12_DWLH_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                1492
pid-VHDL12_DWLH_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                1564
pid-VHDL12_DWLH_130800-2007130800-dsw--0-ia5       13-Jul-2020 08:30                1523
pid-VHDL12_DWLH_131300-2007131300-dsw--0-ia5       13-Jul-2020 12:30                1833
pid-VHDL12_DWLH_131800-2007131800-dsw--0-ia5       13-Jul-2020 18:30                1723
pid-VHDL12_DWLI_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1504
pid-VHDL12_DWLI_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                1510
pid-VHDL12_DWLI_120800-2007120800-dsw--0-ia5       12-Jul-2020 08:30                1463
pid-VHDL12_DWLI_121300-2007121300-dsw--0-ia5       12-Jul-2020 12:30                1431
pid-VHDL12_DWLI_121800-2007121800-dsw--0-ia5       12-Jul-2020 18:30                1281
pid-VHDL12_DWLI_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                1486
pid-VHDL12_DWLI_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                1553
pid-VHDL12_DWLI_130800-2007130800-dsw--0-ia5       13-Jul-2020 08:30                1492
pid-VHDL12_DWLI_131300-2007131300-dsw--0-ia5       13-Jul-2020 12:30                1841
pid-VHDL12_DWLI_131800-2007131800-dsw--0-ia5       13-Jul-2020 18:30                1726
pid-VHDL12_DWMG_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1870
pid-VHDL12_DWMG_120400-2007120400-dsw--0-ia5       12-Jul-2020 04:30                1757
pid-VHDL12_DWMG_120800-2007120800-dsw--0-ia5       12-Jul-2020 08:30                1863
pid-VHDL12_DWMG_121300-2007121300-dsw--0-ia5       12-Jul-2020 12:30                1750
pid-VHDL12_DWMG_121800-2007121800-dsw--0-ia5       12-Jul-2020 18:30                1439
pid-VHDL12_DWMG_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                1670
pid-VHDL12_DWMG_130400-2007130400-dsw--0-ia5       13-Jul-2020 04:30                1674
pid-VHDL12_DWMG_130800-2007130800-dsw--0-ia5       13-Jul-2020 08:30                1780
pid-VHDL12_DWMG_131300-2007131300-dsw--0-ia5       13-Jul-2020 12:30                1887
pid-VHDL12_DWMG_131800-2007131800-dsw--0-ia5       13-Jul-2020 18:30                1884
pid-VHDL12_DWOG_120100-2007120100-dsw--0-ia5       12-Jul-2020 01:45                3019
pid-VHDL12_DWOG_120300-2007120300-dsw--0-ia5       12-Jul-2020 03:00                3019
pid-VHDL12_DWOG_130100-2007130100-dsw--0-ia5       13-Jul-2020 01:45                3247
pid-VHDL12_DWOG_130300-2007130300-dsw--0-ia5       13-Jul-2020 03:00                3167
pid-VHDL12_DWOH_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:28                1596
pid-VHDL12_DWOH_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:28                1546
pid-VHDL12_DWOI_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:28                1726
pid-VHDL12_DWOI_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:28                1686
pid-VHDL12_DWSG_120200-2007120200-dsw--0-ia5       12-Jul-2020 02:30                1382
pid-VHDL12_DWSG_130200-2007130200-dsw--0-ia5       13-Jul-2020 02:30                1640
swis2-VHDL20_DWEG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                1999
swis2-VHDL20_DWEG_120400-2007120400-dsw--0-ia5     12-Jul-2020 05:15                2007
swis2-VHDL20_DWEG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2056
swis2-VHDL20_DWEG_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:45                2053
swis2-VHDL20_DWEG_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:45                2033
swis2-VHDL20_DWEG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                1907
swis2-VHDL20_DWEG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2068
swis2-VHDL20_DWEG_130400-2007130400-dsw--0-ia5     13-Jul-2020 05:15                2570
swis2-VHDL20_DWEG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2637
swis2-VHDL20_DWEG_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:45                2612
swis2-VHDL20_DWEG_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:45                2571
swis2-VHDL20_DWEG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2394
swis2-VHDL20_DWEH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2401
swis2-VHDL20_DWEH_120400-2007120400-dsw--0-ia5     12-Jul-2020 05:15                2318
swis2-VHDL20_DWEH_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2342
swis2-VHDL20_DWEH_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:45                2338
swis2-VHDL20_DWEH_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:45                2322
swis2-VHDL20_DWEH_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                2189
swis2-VHDL20_DWEH_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2374
swis2-VHDL20_DWEH_130400-2007130400-dsw--0-ia5     13-Jul-2020 05:15                2768
swis2-VHDL20_DWEH_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2834
swis2-VHDL20_DWEH_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:45                2808
swis2-VHDL20_DWEH_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:45                2782
swis2-VHDL20_DWEH_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2579
swis2-VHDL20_DWEI_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2129
swis2-VHDL20_DWEI_120400-2007120400-dsw--0-ia5     12-Jul-2020 05:15                2130
swis2-VHDL20_DWEI_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2217
swis2-VHDL20_DWEI_121300-2007121300-dsw--0-ia5     12-Jul-2020 12:45                2213
swis2-VHDL20_DWEI_121500-2007121500-dsw--0-ia5     12-Jul-2020 15:45                2197
swis2-VHDL20_DWEI_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                2072
swis2-VHDL20_DWEI_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2137
swis2-VHDL20_DWEI_130400-2007130400-dsw--0-ia5     13-Jul-2020 05:15                2657
swis2-VHDL20_DWEI_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2723
swis2-VHDL20_DWEI_131300-2007131300-dsw--0-ia5     13-Jul-2020 12:45                2696
swis2-VHDL20_DWEI_131500-2007131500-dsw--0-ia5     13-Jul-2020 15:45                2657
swis2-VHDL20_DWEI_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2538
swis2-VHDL20_DWHG_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2746
swis2-VHDL20_DWHG_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:45                2696
swis2-VHDL20_DWHG_120800-2007120800-dsw--0-ia5     12-Jul-2020 08:45                2634
swis2-VHDL20_DWHG_121300-2007121300-dsw--0-ia5     12-Jul-2020 13:45                2622
swis2-VHDL20_DWHG_121800-2007121800-dsw--0-ia5     12-Jul-2020 18:45                2439
swis2-VHDL20_DWHG_130200-2007130200-dsw--0-ia5     13-Jul-2020 02:45                2672
swis2-VHDL20_DWHG_130400-2007130400-dsw--0-ia5     13-Jul-2020 04:45                2658
swis2-VHDL20_DWHG_130800-2007130800-dsw--0-ia5     13-Jul-2020 08:45                2686
swis2-VHDL20_DWHG_131300-2007131300-dsw--0-ia5     13-Jul-2020 13:45                2651
swis2-VHDL20_DWHG_131800-2007131800-dsw--0-ia5     13-Jul-2020 18:45                2367
swis2-VHDL20_DWHH_120200-2007120200-dsw--0-ia5     12-Jul-2020 02:45                2651
swis2-VHDL20_DWHH_120400-2007120400-dsw--0-ia5     12-Jul-2020 04:45                2648
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wst04-VHDL20_DWEG_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              239240
wst04-VHDL20_DWEG_120400-2007120400-omedes--0.pdf  12-Jul-2020 05:15              238809
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wst04-VHDL20_DWEG_121500-2007121500-omedes--0.pdf  12-Jul-2020 15:45              240439
wst04-VHDL20_DWEG_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              240814
wst04-VHDL20_DWEG_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              242017
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wst04-VHDL20_DWEH_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              238446
wst04-VHDL20_DWEH_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:45              238635
wst04-VHDL20_DWEH_121500-2007121500-omedes--0.pdf  12-Jul-2020 15:45              238597
wst04-VHDL20_DWEH_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              238479
wst04-VHDL20_DWEH_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              239542
wst04-VHDL20_DWEH_130400-2007130400-omedes--0.pdf  13-Jul-2020 05:15              240168
wst04-VHDL20_DWEH_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              240092
wst04-VHDL20_DWEH_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:45              240067
wst04-VHDL20_DWEH_131500-2007131500-omedes--0.pdf  13-Jul-2020 15:45              239978
wst04-VHDL20_DWEH_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              239391
wst04-VHDL20_DWEI_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              331374
wst04-VHDL20_DWEI_120400-2007120400-omedes--0.pdf  12-Jul-2020 05:15              330500
wst04-VHDL20_DWEI_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              333841
wst04-VHDL20_DWEI_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:45              334042
wst04-VHDL20_DWEI_121500-2007121500-omedes--0.pdf  12-Jul-2020 15:45              334000
wst04-VHDL20_DWEI_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              334426
wst04-VHDL20_DWEI_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              335764
wst04-VHDL20_DWEI_130400-2007130400-omedes--0.pdf  13-Jul-2020 05:15              336262
wst04-VHDL20_DWEI_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              337273
wst04-VHDL20_DWEI_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:45              337421
wst04-VHDL20_DWEI_131500-2007131500-omedes--0.pdf  13-Jul-2020 15:45              336333
wst04-VHDL20_DWEI_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              336728
wst04-VHDL20_DWHG_120200-2007120200-oflxs888--0..> 12-Jul-2020 02:45              334310
wst04-VHDL20_DWHG_120400-2007120400-oflxs888--0..> 12-Jul-2020 04:45              334194
wst04-VHDL20_DWHG_120800-2007120800-oflxs888--0..> 12-Jul-2020 08:45              334370
wst04-VHDL20_DWHG_121300-2007121300-oflxs888--0..> 12-Jul-2020 13:45              334431
wst04-VHDL20_DWHG_121800-2007121800-oflxs888--0..> 12-Jul-2020 18:45              333635
wst04-VHDL20_DWHG_130200-2007130200-oflxs888--0..> 13-Jul-2020 02:45              333872
wst04-VHDL20_DWHG_130400-2007130400-oflxs888--0..> 13-Jul-2020 04:45              333847
wst04-VHDL20_DWHG_130800-2007130800-oflxs888--0..> 13-Jul-2020 08:45              337331
wst04-VHDL20_DWHG_131300-2007131300-oflxs888--0..> 13-Jul-2020 13:45              337155
wst04-VHDL20_DWHG_131800-2007131800-oflxs888--0..> 13-Jul-2020 18:45              336105
wst04-VHDL20_DWHH_120200-2007120200-oflxs888--0..> 12-Jul-2020 02:45              323125
wst04-VHDL20_DWHH_120400-2007120400-oflxs888--0..> 12-Jul-2020 04:45              323185
wst04-VHDL20_DWHH_120800-2007120800-oflxs888--0..> 12-Jul-2020 08:45              330508
wst04-VHDL20_DWHH_121300-2007121300-oflxs888--0..> 12-Jul-2020 13:45              331108
wst04-VHDL20_DWHH_121800-2007121800-oflxs888--0..> 12-Jul-2020 18:45              330312
wst04-VHDL20_DWHH_130200-2007130200-oflxs888--0..> 13-Jul-2020 02:45              330965
wst04-VHDL20_DWHH_130400-2007130400-oflxs888--0..> 13-Jul-2020 04:45              331009
wst04-VHDL20_DWHH_130800-2007130800-oflxs888--0..> 13-Jul-2020 08:45              332463
wst04-VHDL20_DWHH_131300-2007131300-oflxs888--0..> 13-Jul-2020 13:45              332800
wst04-VHDL20_DWHH_131800-2007131800-oflxs888--0..> 13-Jul-2020 18:45              331414
wst04-VHDL20_DWLG_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:40              239527
wst04-VHDL20_DWLG_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:40              239758
wst04-VHDL20_DWLG_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:40              241933
wst04-VHDL20_DWLG_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:40              241673
wst04-VHDL20_DWLG_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:40              242037
wst04-VHDL20_DWLG_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:40              242992
wst04-VHDL20_DWLG_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:40              242618
wst04-VHDL20_DWLG_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:40              242327
wst04-VHDL20_DWLG_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:40              241684
wst04-VHDL20_DWLG_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:40              241183
wst04-VHDL20_DWLH_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:40              243775
wst04-VHDL20_DWLH_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:40              243909
wst04-VHDL20_DWLH_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:40              244633
wst04-VHDL20_DWLH_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:40              244360
wst04-VHDL20_DWLH_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:40              244715
wst04-VHDL20_DWLH_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:40              245369
wst04-VHDL20_DWLH_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:40              245547
wst04-VHDL20_DWLH_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:40              249519
wst04-VHDL20_DWLH_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:40              249063
wst04-VHDL20_DWLH_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:40              249141
wst04-VHDL20_DWLI_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:40              244896
wst04-VHDL20_DWLI_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:40              245095
wst04-VHDL20_DWLI_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:40              239342
wst04-VHDL20_DWLI_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:40              239042
wst04-VHDL20_DWLI_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:40              239326
wst04-VHDL20_DWLI_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:40              239960
wst04-VHDL20_DWLI_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:40              239624
wst04-VHDL20_DWLI_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:40              243110
wst04-VHDL20_DWLI_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:40              242694
wst04-VHDL20_DWLI_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:40              242303
wst04-VHDL20_DWMG_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              248980
wst04-VHDL20_DWMG_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:45              248420
wst04-VHDL20_DWMG_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              246332
wst04-VHDL20_DWMG_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:45              246190
wst04-VHDL20_DWMG_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              244227
wst04-VHDL20_DWMG_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              245682
wst04-VHDL20_DWMG_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:45              245209
wst04-VHDL20_DWMG_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              246542
wst04-VHDL20_DWMG_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:45              247214
wst04-VHDL20_DWMG_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              247739
wst04-VHDL20_DWMO_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              246005
wst04-VHDL20_DWMO_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:45              246438
wst04-VHDL20_DWMO_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              246394
wst04-VHDL20_DWMO_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:45              246344
wst04-VHDL20_DWMO_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              245174
wst04-VHDL20_DWMO_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              245659
wst04-VHDL20_DWMO_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:45              246073
wst04-VHDL20_DWMO_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              249718
wst04-VHDL20_DWMO_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:45              249678
wst04-VHDL20_DWMO_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              249429
wst04-VHDL20_DWMP_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              247993
wst04-VHDL20_DWMP_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:45              248054
wst04-VHDL20_DWMP_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              246258
wst04-VHDL20_DWMP_121300-2007121300-omedes--0.pdf  12-Jul-2020 12:45              246261
wst04-VHDL20_DWMP_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              244958
wst04-VHDL20_DWMP_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              245329
wst04-VHDL20_DWMP_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:45              245397
wst04-VHDL20_DWMP_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              246791
wst04-VHDL20_DWMP_131300-2007131300-omedes--0.pdf  13-Jul-2020 12:45              247088
wst04-VHDL20_DWMP_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              246942
wst04-VHDL20_DWPG_120200-2007120200-oflxs892--0..> 12-Jul-2020 02:30              327495
wst04-VHDL20_DWPG_120400-2007120400-oflxs892--0..> 12-Jul-2020 04:30              326889
wst04-VHDL20_DWPG_120530-2007120530-oflxs892--0..> 12-Jul-2020 05:30              326853
wst04-VHDL20_DWPG_120630-2007120630-oflxs892--0..> 12-Jul-2020 06:30              326853
wst04-VHDL20_DWPG_120730-2007120730-oflxs892--0..> 12-Jul-2020 07:30              326853
wst04-VHDL20_DWPG_120800-2007120800-oflxs892--0..> 12-Jul-2020 08:30              372400
wst04-VHDL20_DWPG_120930-2007120930-oflxs892--0..> 12-Jul-2020 09:30              327853
wst04-VHDL20_DWPG_121030-2007121030-oflxs892--0..> 12-Jul-2020 10:30              327853
wst04-VHDL20_DWPG_121130-2007121130-oflxs892--0..> 12-Jul-2020 11:30              327859
wst04-VHDL20_DWPG_121300-2007121300-oflxs892--0..> 12-Jul-2020 12:30              328353
wst04-VHDL20_DWPG_121330-2007121330-oflxs892--0..> 12-Jul-2020 13:30              328347
wst04-VHDL20_DWPG_121430-2007121430-oflxs892--0..> 12-Jul-2020 14:30              328347
wst04-VHDL20_DWPG_121500-2007121500-oflxs892--0..> 12-Jul-2020 15:30              328351
wst04-VHDL20_DWPG_121630-2007121630-oflxs892--0..> 12-Jul-2020 16:30              328351
wst04-VHDL20_DWPG_121730-2007121730-oflxs892--0..> 12-Jul-2020 17:30              328351
wst04-VHDL20_DWPG_121800-2007121800-oflxs892--0..> 12-Jul-2020 18:30              328073
wst04-VHDL20_DWPG_121930-2007121930-oflxs892--0..> 12-Jul-2020 19:30              328050
wst04-VHDL20_DWPG_122030-2007122030-oflxs892--0..> 12-Jul-2020 20:30              328050
wst04-VHDL20_DWPG_130200-2007130200-oflxs892--0..> 13-Jul-2020 02:30              327767
wst04-VHDL20_DWPG_130400-2007130400-oflxs892--0..> 13-Jul-2020 04:30              328478
wst04-VHDL20_DWPG_130530-2007130530-oflxs892--0..> 13-Jul-2020 05:30              327987
wst04-VHDL20_DWPG_130630-2007130630-oflxs892--0..> 13-Jul-2020 06:30              327991
wst04-VHDL20_DWPG_130730-2007130730-oflxs892--0..> 13-Jul-2020 07:30              327991
wst04-VHDL20_DWPG_130800-2007130800-oflxs892--0..> 13-Jul-2020 08:30              387753
wst04-VHDL20_DWPG_130930-2007130930-oflxs892--0..> 13-Jul-2020 09:30              343171
wst04-VHDL20_DWPG_131030-2007131030-oflxs892--0..> 13-Jul-2020 10:30              343171
wst04-VHDL20_DWPG_131130-2007131130-oflxs892--0..> 13-Jul-2020 11:30              343081
wst04-VHDL20_DWPG_131300-2007131300-oflxs892--0..> 13-Jul-2020 12:30              343008
wst04-VHDL20_DWPG_131330-2007131330-oflxs892--0..> 13-Jul-2020 13:30              342991
wst04-VHDL20_DWPG_131430-2007131430-oflxs892--0..> 13-Jul-2020 14:30              342991
wst04-VHDL20_DWPG_131500-2007131500-oflxs892--0..> 13-Jul-2020 15:30              343001
wst04-VHDL20_DWPG_131630-2007131630-oflxs892--0..> 13-Jul-2020 16:30              342993
wst04-VHDL20_DWPG_131730-2007131730-oflxs892--0..> 13-Jul-2020 17:30              342993
wst04-VHDL20_DWPG_131800-2007131800-oflxs892--0..> 13-Jul-2020 18:30              343329
wst04-VHDL20_DWPG_131930-2007131930-oflxs892--0..> 13-Jul-2020 19:30              343318
wst04-VHDL20_DWPG_132030-2007132030-oflxs892--0..> 13-Jul-2020 20:30              343318
wst04-VHDL20_DWPH_120200-2007120200-oflxs892--0..> 12-Jul-2020 02:30              242662
wst04-VHDL20_DWPH_120400-2007120400-oflxs892--0..> 12-Jul-2020 04:30              244021
wst04-VHDL20_DWPH_120530-2007120530-oflxs892--0..> 12-Jul-2020 05:30              243539
wst04-VHDL20_DWPH_120630-2007120630-oflxs892--0..> 12-Jul-2020 06:30              243539
wst04-VHDL20_DWPH_120730-2007120730-oflxs892--0..> 12-Jul-2020 07:30              243539
wst04-VHDL20_DWPH_120800-2007120800-oflxs892--0..> 12-Jul-2020 08:30              285726
wst04-VHDL20_DWPH_120930-2007120930-oflxs892--0..> 12-Jul-2020 09:30              241143
wst04-VHDL20_DWPH_121030-2007121030-oflxs892--0..> 12-Jul-2020 10:30              241143
wst04-VHDL20_DWPH_121130-2007121130-oflxs892--0..> 12-Jul-2020 11:30              241123
wst04-VHDL20_DWPH_121300-2007121300-oflxs892--0..> 12-Jul-2020 12:30              240642
wst04-VHDL20_DWPH_121330-2007121330-oflxs892--0..> 12-Jul-2020 13:30              240654
wst04-VHDL20_DWPH_121430-2007121430-oflxs892--0..> 12-Jul-2020 14:30              240654
wst04-VHDL20_DWPH_121500-2007121500-oflxs892--0..> 12-Jul-2020 15:30              240191
wst04-VHDL20_DWPH_121630-2007121630-oflxs892--0..> 12-Jul-2020 16:30              240173
wst04-VHDL20_DWPH_121730-2007121730-oflxs892--0..> 12-Jul-2020 17:30              239555
wst04-VHDL20_DWPH_121800-2007121800-oflxs892--0..> 12-Jul-2020 18:30              284251
wst04-VHDL20_DWPH_121930-2007121930-oflxs892--0..> 12-Jul-2020 19:30              239633
wst04-VHDL20_DWPH_122030-2007122030-oflxs892--0..> 12-Jul-2020 20:30              239633
wst04-VHDL20_DWPH_130200-2007130200-oflxs892--0..> 13-Jul-2020 02:30              240068
wst04-VHDL20_DWPH_130400-2007130400-oflxs892--0..> 13-Jul-2020 04:30              240683
wst04-VHDL20_DWPH_130530-2007130530-oflxs892--0..> 13-Jul-2020 05:30              240610
wst04-VHDL20_DWPH_130630-2007130630-oflxs892--0..> 13-Jul-2020 06:30              240687
wst04-VHDL20_DWPH_130730-2007130730-oflxs892--0..> 13-Jul-2020 07:30              240687
wst04-VHDL20_DWPH_130800-2007130800-oflxs892--0..> 13-Jul-2020 08:30              292551
wst04-VHDL20_DWPH_130930-2007130930-oflxs892--0..> 13-Jul-2020 09:30              247953
wst04-VHDL20_DWPH_131030-2007131030-oflxs892--0..> 13-Jul-2020 10:30              247953
wst04-VHDL20_DWPH_131130-2007131130-oflxs892--0..> 13-Jul-2020 11:30              247942
wst04-VHDL20_DWPH_131300-2007131300-oflxs892--0..> 13-Jul-2020 12:30              247439
wst04-VHDL20_DWPH_131330-2007131330-oflxs892--0..> 13-Jul-2020 13:30              247438
wst04-VHDL20_DWPH_131430-2007131430-oflxs892--0..> 13-Jul-2020 14:30              247438
wst04-VHDL20_DWPH_131500-2007131500-oflxs892--0..> 13-Jul-2020 15:30              247413
wst04-VHDL20_DWPH_131630-2007131630-oflxs892--0..> 13-Jul-2020 16:30              247435
wst04-VHDL20_DWPH_131730-2007131730-oflxs892--0..> 13-Jul-2020 17:30              247435
wst04-VHDL20_DWPH_131800-2007131800-oflxs892--0..> 13-Jul-2020 18:30              292073
wst04-VHDL20_DWPH_131930-2007131930-oflxs892--0..> 13-Jul-2020 19:30              247462
wst04-VHDL20_DWPH_132030-2007132030-oflxs892--0..> 13-Jul-2020 20:30              247462
wst04-VHDL20_DWSG_120200-2007120200-omedes--0.pdf  12-Jul-2020 02:45              249496
wst04-VHDL20_DWSG_120400-2007120400-omedes--0.pdf  12-Jul-2020 04:45              249538
wst04-VHDL20_DWSG_120800-2007120800-omedes--0.pdf  12-Jul-2020 08:45              246739
wst04-VHDL20_DWSG_121300-2007121300-omedes--0.pdf  12-Jul-2020 13:45              247657
wst04-VHDL20_DWSG_121800-2007121800-omedes--0.pdf  12-Jul-2020 18:45              246976
wst04-VHDL20_DWSG_130200-2007130200-omedes--0.pdf  13-Jul-2020 02:45              247324
wst04-VHDL20_DWSG_130400-2007130400-omedes--0.pdf  13-Jul-2020 04:45              247477
wst04-VHDL20_DWSG_130800-2007130800-omedes--0.pdf  13-Jul-2020 08:45              245462
wst04-VHDL20_DWSG_131300-2007131300-omedes--0.pdf  13-Jul-2020 13:45              246579
wst04-VHDL20_DWSG_131800-2007131800-omedes--0.pdf  13-Jul-2020 18:45              246237