Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_020600 02-Oct-2022 13:45 2326
FPDL13_DWMZ_030600 03-Oct-2022 14:59 5879
SXDL31_DWAV_020800 02-Oct-2022 06:50 12678
SXDL31_DWAV_021800 02-Oct-2022 17:13 9574
SXDL31_DWAV_030800 03-Oct-2022 07:10 8296
SXDL31_DWAV_031800 03-Oct-2022 16:40 11909
SXDL31_DWAV_LATEST 03-Oct-2022 16:40 11909
SXDL33_DWAV_020000 02-Oct-2022 09:32 10808
SXDL33_DWAV_030000 03-Oct-2022 11:27 12422
SXDL33_DWAV_LATEST 03-Oct-2022 11:27 12422
ber01-FWDL39_DWMS_021230-2210021230-dsw--0-ia5 02-Oct-2022 12:10 1644
ber01-FWDL39_DWMS_031230-2210031230-dsw--0-ia5 03-Oct-2022 11:50 1529
ber01-VHDL13_DWEH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:28 2429
ber01-VHDL13_DWEH_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:58 2389
ber01-VHDL13_DWEH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:28 2402
ber01-VHDL13_DWEH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:28 2356
ber01-VHDL13_DWEH_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:28 2005
ber01-VHDL13_DWEH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:28 1879
ber01-VHDL13_DWEH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:28 2174
ber01-VHDL13_DWEH_030400-2210030400-dsw--0-ia5 03-Oct-2022 04:58 2132
ber01-VHDL13_DWEH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:28 2066
ber01-VHDL13_DWEH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:28 2073
ber01-VHDL13_DWEH_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:28 2088
ber01-VHDL13_DWEH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:28 1933
ber01-VHDL13_DWHG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2526
ber01-VHDL13_DWHG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2527
ber01-VHDL13_DWHG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2609
ber01-VHDL13_DWHG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 2478
ber01-VHDL13_DWHG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2166
ber01-VHDL13_DWHG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2249
ber01-VHDL13_DWHG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2243
ber01-VHDL13_DWHG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2481
ber01-VHDL13_DWHG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2668
ber01-VHDL13_DWHG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2509
ber01-VHDL13_DWHH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2407
ber01-VHDL13_DWHH_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2412
ber01-VHDL13_DWHH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2499
ber01-VHDL13_DWHH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 2429
ber01-VHDL13_DWHH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2117
ber01-VHDL13_DWHH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2156
ber01-VHDL13_DWHH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2153
ber01-VHDL13_DWHH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2414
ber01-VHDL13_DWHH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2505
ber01-VHDL13_DWHH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2467
ber01-VHDL13_DWLG_020033-2210020033-dsw--0-ia5 02-Oct-2022 00:33 1519
ber01-VHDL13_DWLG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 1513
ber01-VHDL13_DWLG_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:59 1936
ber01-VHDL13_DWLG_020533-2210020533-dsw--0-ia5 02-Oct-2022 05:33 1942
ber01-VHDL13_DWLG_020633-2210020633-dsw--0-ia5 02-Oct-2022 06:33 1991
ber01-VHDL13_DWLG_020733-2210020733-dsw--0-ia5 02-Oct-2022 07:33 2001
ber01-VHDL13_DWLG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 1992
ber01-VHDL13_DWLG_020933-2210020933-dsw--0-ia5 02-Oct-2022 09:33 2001
ber01-VHDL13_DWLG_021033-2210021033-dsw--0-ia5 02-Oct-2022 10:33 1944
ber01-VHDL13_DWLG_021133-2210021133-dsw--0-ia5 02-Oct-2022 11:33 1941
ber01-VHDL13_DWLG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 1896
ber01-VHDL13_DWLG_021333-2210021333-dsw--0-ia5 02-Oct-2022 13:33 1902
ber01-VHDL13_DWLG_021433-2210021433-dsw--0-ia5 02-Oct-2022 14:33 1902
ber01-VHDL13_DWLG_021533-2210021533-dsw--0-ia5 02-Oct-2022 15:33 1902
ber01-VHDL13_DWLG_021633-2210021633-dsw--0-ia5 02-Oct-2022 16:33 1906
ber01-VHDL13_DWLG_021733-2210021733-dsw--0-ia5 02-Oct-2022 17:33 1657
ber01-VHDL13_DWLG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 1651
ber01-VHDL13_DWLG_021933-2210021933-dsw--0-ia5 02-Oct-2022 19:33 1657
ber01-VHDL13_DWLG_022033-2210022033-dsw--0-ia5 02-Oct-2022 20:33 1657
ber01-VHDL13_DWLG_030033-2210030033-dsw--0-ia5 03-Oct-2022 00:33 1642
ber01-VHDL13_DWLG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 1899
ber01-VHDL13_DWLG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 1883
ber01-VHDL13_DWLG_030533-2210030533-dsw--0-ia5 03-Oct-2022 05:33 1889
ber01-VHDL13_DWLG_030633-2210030633-dsw--0-ia5 03-Oct-2022 06:33 1889
ber01-VHDL13_DWLG_030733-2210030733-dsw--0-ia5 03-Oct-2022 07:33 1886
ber01-VHDL13_DWLG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 1877
ber01-VHDL13_DWLG_030933-2210030933-dsw--0-ia5 03-Oct-2022 09:33 1886
ber01-VHDL13_DWLG_031033-2210031033-dsw--0-ia5 03-Oct-2022 10:33 1877
ber01-VHDL13_DWLG_031133-2210031133-dsw--0-ia5 03-Oct-2022 11:33 1877
ber01-VHDL13_DWLG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 1879
ber01-VHDL13_DWLG_031333-2210031333-dsw--0-ia5 03-Oct-2022 13:33 1885
ber01-VHDL13_DWLG_031433-2210031433-dsw--0-ia5 03-Oct-2022 14:33 1672
ber01-VHDL13_DWLG_031533-2210031533-dsw--0-ia5 03-Oct-2022 15:33 1672
ber01-VHDL13_DWLG_031633-2210031633-dsw--0-ia5 03-Oct-2022 16:33 1672
ber01-VHDL13_DWLG_031733-2210031733-dsw--0-ia5 03-Oct-2022 17:33 1609
ber01-VHDL13_DWLG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 1603
ber01-VHDL13_DWLG_031933-2210031933-dsw--0-ia5 03-Oct-2022 19:33 1609
ber01-VHDL13_DWLG_032033-2210032033-dsw--0-ia5 03-Oct-2022 20:33 1609
ber01-VHDL13_DWLH_020033-2210020033-dsw--0-ia5 02-Oct-2022 00:33 1706
ber01-VHDL13_DWLH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 1676
ber01-VHDL13_DWLH_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:59 1833
ber01-VHDL13_DWLH_020533-2210020533-dsw--0-ia5 02-Oct-2022 05:33 1842
ber01-VHDL13_DWLH_020633-2210020633-dsw--0-ia5 02-Oct-2022 06:33 1853
ber01-VHDL13_DWLH_020733-2210020733-dsw--0-ia5 02-Oct-2022 07:33 1853
ber01-VHDL13_DWLH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 1844
ber01-VHDL13_DWLH_020933-2210020933-dsw--0-ia5 02-Oct-2022 09:33 1853
ber01-VHDL13_DWLH_021033-2210021033-dsw--0-ia5 02-Oct-2022 10:33 1824
ber01-VHDL13_DWLH_021133-2210021133-dsw--0-ia5 02-Oct-2022 11:33 1826
ber01-VHDL13_DWLH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 1757
ber01-VHDL13_DWLH_021333-2210021333-dsw--0-ia5 02-Oct-2022 13:33 1766
ber01-VHDL13_DWLH_021433-2210021433-dsw--0-ia5 02-Oct-2022 14:33 1766
ber01-VHDL13_DWLH_021533-2210021533-dsw--0-ia5 02-Oct-2022 15:33 1766
ber01-VHDL13_DWLH_021633-2210021633-dsw--0-ia5 02-Oct-2022 16:33 1403
ber01-VHDL13_DWLH_021733-2210021733-dsw--0-ia5 02-Oct-2022 17:33 1403
ber01-VHDL13_DWLH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 1394
ber01-VHDL13_DWLH_021933-2210021933-dsw--0-ia5 02-Oct-2022 19:33 1403
ber01-VHDL13_DWLH_022033-2210022033-dsw--0-ia5 02-Oct-2022 20:33 1403
ber01-VHDL13_DWLH_030033-2210030033-dsw--0-ia5 03-Oct-2022 00:33 1460
ber01-VHDL13_DWLH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 1542
ber01-VHDL13_DWLH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 1592
ber01-VHDL13_DWLH_030533-2210030533-dsw--0-ia5 03-Oct-2022 05:33 1601
ber01-VHDL13_DWLH_030633-2210030633-dsw--0-ia5 03-Oct-2022 06:33 1601
ber01-VHDL13_DWLH_030733-2210030733-dsw--0-ia5 03-Oct-2022 07:33 1598
ber01-VHDL13_DWLH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 1589
ber01-VHDL13_DWLH_030933-2210030933-dsw--0-ia5 03-Oct-2022 09:33 1598
ber01-VHDL13_DWLH_031033-2210031033-dsw--0-ia5 03-Oct-2022 10:33 1584
ber01-VHDL13_DWLH_031133-2210031133-dsw--0-ia5 03-Oct-2022 11:33 1584
ber01-VHDL13_DWLH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 1562
ber01-VHDL13_DWLH_031333-2210031333-dsw--0-ia5 03-Oct-2022 13:33 1571
ber01-VHDL13_DWLH_031433-2210031433-dsw--0-ia5 03-Oct-2022 14:33 1564
ber01-VHDL13_DWLH_031533-2210031533-dsw--0-ia5 03-Oct-2022 15:33 1564
ber01-VHDL13_DWLH_031633-2210031633-dsw--0-ia5 03-Oct-2022 16:33 1564
ber01-VHDL13_DWLH_031733-2210031733-dsw--0-ia5 03-Oct-2022 17:33 1496
ber01-VHDL13_DWLH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 1487
ber01-VHDL13_DWLH_031933-2210031933-dsw--0-ia5 03-Oct-2022 19:33 1496
ber01-VHDL13_DWLH_032033-2210032033-dsw--0-ia5 03-Oct-2022 20:33 1496
ber01-VHDL13_DWLI_020033-2210020033-dsw--0-ia5 02-Oct-2022 00:33 1525
ber01-VHDL13_DWLI_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 1519
ber01-VHDL13_DWLI_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:59 1616
ber01-VHDL13_DWLI_020533-2210020533-dsw--0-ia5 02-Oct-2022 05:33 1619
ber01-VHDL13_DWLI_020633-2210020633-dsw--0-ia5 02-Oct-2022 06:33 1630
ber01-VHDL13_DWLI_020733-2210020733-dsw--0-ia5 02-Oct-2022 07:33 1630
ber01-VHDL13_DWLI_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 1624
ber01-VHDL13_DWLI_020933-2210020933-dsw--0-ia5 02-Oct-2022 09:33 1630
ber01-VHDL13_DWLI_021033-2210021033-dsw--0-ia5 02-Oct-2022 10:33 1572
ber01-VHDL13_DWLI_021133-2210021133-dsw--0-ia5 02-Oct-2022 11:33 1559
ber01-VHDL13_DWLI_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 1508
ber01-VHDL13_DWLI_021333-2210021333-dsw--0-ia5 02-Oct-2022 13:33 1514
ber01-VHDL13_DWLI_021433-2210021433-dsw--0-ia5 02-Oct-2022 14:33 1514
ber01-VHDL13_DWLI_021533-2210021533-dsw--0-ia5 02-Oct-2022 15:33 1514
ber01-VHDL13_DWLI_021633-2210021633-dsw--0-ia5 02-Oct-2022 16:33 1518
ber01-VHDL13_DWLI_021733-2210021733-dsw--0-ia5 02-Oct-2022 17:33 1355
ber01-VHDL13_DWLI_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 1349
ber01-VHDL13_DWLI_021933-2210021933-dsw--0-ia5 02-Oct-2022 19:33 1355
ber01-VHDL13_DWLI_022033-2210022033-dsw--0-ia5 02-Oct-2022 20:33 1355
ber01-VHDL13_DWLI_030033-2210030033-dsw--0-ia5 03-Oct-2022 00:33 1413
ber01-VHDL13_DWLI_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 1540
ber01-VHDL13_DWLI_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 1567
ber01-VHDL13_DWLI_030533-2210030533-dsw--0-ia5 03-Oct-2022 05:33 1570
ber01-VHDL13_DWLI_030633-2210030633-dsw--0-ia5 03-Oct-2022 06:33 1570
ber01-VHDL13_DWLI_030733-2210030733-dsw--0-ia5 03-Oct-2022 07:33 1566
ber01-VHDL13_DWLI_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 1560
ber01-VHDL13_DWLI_030933-2210030933-dsw--0-ia5 03-Oct-2022 09:33 1566
ber01-VHDL13_DWLI_031033-2210031033-dsw--0-ia5 03-Oct-2022 10:33 1552
ber01-VHDL13_DWLI_031133-2210031133-dsw--0-ia5 03-Oct-2022 11:33 1552
ber01-VHDL13_DWLI_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 1547
ber01-VHDL13_DWLI_031333-2210031333-dsw--0-ia5 03-Oct-2022 13:33 1553
ber01-VHDL13_DWLI_031433-2210031433-dsw--0-ia5 03-Oct-2022 14:33 1556
ber01-VHDL13_DWLI_031533-2210031533-dsw--0-ia5 03-Oct-2022 15:33 1556
ber01-VHDL13_DWLI_031633-2210031633-dsw--0-ia5 03-Oct-2022 16:33 1556
ber01-VHDL13_DWLI_031733-2210031733-dsw--0-ia5 03-Oct-2022 17:33 1612
ber01-VHDL13_DWLI_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 1606
ber01-VHDL13_DWLI_031933-2210031933-dsw--0-ia5 03-Oct-2022 19:33 1612
ber01-VHDL13_DWLI_032033-2210032033-dsw--0-ia5 03-Oct-2022 20:33 1612
ber01-VHDL13_DWMG_012200-2210012200-dsw--0-ia5 01-Oct-2022 22:30 3433
ber01-VHDL13_DWMG_012300-2210012300-dsw--0-ia5 01-Oct-2022 23:30 3433
ber01-VHDL13_DWMG_020000-2210020000-dsw--0-ia5 02-Oct-2022 00:30 3433
ber01-VHDL13_DWMG_020100-2210020100-dsw--0-ia5 02-Oct-2022 01:30 3433
ber01-VHDL13_DWMG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 3433
ber01-VHDL13_DWMG_020300-2210020300-dsw--0-ia5 02-Oct-2022 03:30 3433
ber01-VHDL13_DWMG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3591
ber01-VHDL13_DWMG_020500-2210020500-dsw--0-ia5 02-Oct-2022 05:30 3674
ber01-VHDL13_DWMG_020600-2210020600-dsw--0-ia5 02-Oct-2022 06:30 3745
ber01-VHDL13_DWMG_020700-2210020700-dsw--0-ia5 02-Oct-2022 07:30 3745
ber01-VHDL13_DWMG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 3764
ber01-VHDL13_DWMG_020900-2210020900-dsw--0-ia5 02-Oct-2022 09:30 3764
ber01-VHDL13_DWMG_021000-2210021000-dsw--0-ia5 02-Oct-2022 10:30 3764
ber01-VHDL13_DWMG_021100-2210021100-dsw--0-ia5 02-Oct-2022 11:30 3863
ber01-VHDL13_DWMG_021200-2210021200-dsw--0-ia5 02-Oct-2022 12:30 3859
ber01-VHDL13_DWMG_021300-2210021300-dsw--0-ia5 02-Oct-2022 13:30 3859
ber01-VHDL13_DWMG_021400-2210021400-dsw--0-ia5 02-Oct-2022 14:30 3643
ber01-VHDL13_DWMG_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 3643
ber01-VHDL13_DWMG_021600-2210021600-dsw--0-ia5 02-Oct-2022 16:30 3643
ber01-VHDL13_DWMG_021700-2210021700-dsw--0-ia5 02-Oct-2022 17:30 2775
ber01-VHDL13_DWMG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2775
ber01-VHDL13_DWMG_021900-2210021900-dsw--0-ia5 02-Oct-2022 19:30 2870
ber01-VHDL13_DWMG_022000-2210022000-dsw--0-ia5 02-Oct-2022 20:30 2887
ber01-VHDL13_DWMG_022100-2210022100-dsw--0-ia5 02-Oct-2022 21:30 2887
ber01-VHDL13_DWMG_022200-2210022200-dsw--0-ia5 02-Oct-2022 22:30 2605
ber01-VHDL13_DWMG_022300-2210022300-dsw--0-ia5 02-Oct-2022 23:30 2605
ber01-VHDL13_DWMG_030000-2210030000-dsw--0-ia5 03-Oct-2022 00:30 2605
ber01-VHDL13_DWMG_030100-2210030100-dsw--0-ia5 03-Oct-2022 01:30 2605
ber01-VHDL13_DWMG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2605
ber01-VHDL13_DWMG_030300-2210030300-dsw--0-ia5 03-Oct-2022 03:30 2394
ber01-VHDL13_DWMG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2549
ber01-VHDL13_DWMG_030500-2210030500-dsw--0-ia5 03-Oct-2022 05:30 2549
ber01-VHDL13_DWMG_030600-2210030600-dsw--0-ia5 03-Oct-2022 06:30 2549
ber01-VHDL13_DWMG_030700-2210030700-dsw--0-ia5 03-Oct-2022 07:30 2549
ber01-VHDL13_DWMG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2613
ber01-VHDL13_DWMG_030900-2210030900-dsw--0-ia5 03-Oct-2022 09:30 2613
ber01-VHDL13_DWMG_031000-2210031000-dsw--0-ia5 03-Oct-2022 10:30 2514
ber01-VHDL13_DWMG_031100-2210031100-dsw--0-ia5 03-Oct-2022 11:30 2514
ber01-VHDL13_DWMG_031200-2210031200-dsw--0-ia5 03-Oct-2022 12:30 2514
ber01-VHDL13_DWMG_031300-2210031300-dsw--0-ia5 03-Oct-2022 13:30 2514
ber01-VHDL13_DWMG_031400-2210031400-dsw--0-ia5 03-Oct-2022 14:30 2338
ber01-VHDL13_DWMG_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:30 2338
ber01-VHDL13_DWMG_031600-2210031600-dsw--0-ia5 03-Oct-2022 16:30 2338
ber01-VHDL13_DWMG_031700-2210031700-dsw--0-ia5 03-Oct-2022 17:30 2207
ber01-VHDL13_DWMG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2207
ber01-VHDL13_DWMG_031900-2210031900-dsw--0-ia5 03-Oct-2022 19:30 2339
ber01-VHDL13_DWMG_032000-2210032000-dsw--0-ia5 03-Oct-2022 20:30 2351
ber01-VHDL13_DWMG_032100-2210032100-dsw--0-ia5 03-Oct-2022 21:30 2351
ber01-VHDL13_DWMO_012200-2210012200-dsw--0-ia5 01-Oct-2022 22:30 2636
ber01-VHDL13_DWMO_012300-2210012300-dsw--0-ia5 01-Oct-2022 23:30 2636
ber01-VHDL13_DWMO_020000-2210020000-dsw--0-ia5 02-Oct-2022 00:30 2636
ber01-VHDL13_DWMO_020100-2210020100-dsw--0-ia5 02-Oct-2022 01:30 2636
ber01-VHDL13_DWMO_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2636
ber01-VHDL13_DWMO_020300-2210020300-dsw--0-ia5 02-Oct-2022 03:30 2636
ber01-VHDL13_DWMO_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2628
ber01-VHDL13_DWMO_020500-2210020500-dsw--0-ia5 02-Oct-2022 05:30 2628
ber01-VHDL13_DWMO_020600-2210020600-dsw--0-ia5 02-Oct-2022 06:30 2733
ber01-VHDL13_DWMO_020700-2210020700-dsw--0-ia5 02-Oct-2022 07:30 2733
ber01-VHDL13_DWMO_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2758
ber01-VHDL13_DWMO_020900-2210020900-dsw--0-ia5 02-Oct-2022 09:30 2730
ber01-VHDL13_DWMO_021000-2210021000-dsw--0-ia5 02-Oct-2022 10:30 2730
ber01-VHDL13_DWMO_021100-2210021100-dsw--0-ia5 02-Oct-2022 11:30 2856
ber01-VHDL13_DWMO_021200-2210021200-dsw--0-ia5 02-Oct-2022 12:30 2856
ber01-VHDL13_DWMO_021300-2210021300-dsw--0-ia5 02-Oct-2022 13:30 2832
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ber01-VHDL13_DWMO_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 2710
ber01-VHDL13_DWMO_021600-2210021600-dsw--0-ia5 02-Oct-2022 16:30 2710
ber01-VHDL13_DWMO_021700-2210021700-dsw--0-ia5 02-Oct-2022 17:30 2710
ber01-VHDL13_DWMO_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2223
ber01-VHDL13_DWMO_021900-2210021900-dsw--0-ia5 02-Oct-2022 19:30 2240
ber01-VHDL13_DWMO_022000-2210022000-dsw--0-ia5 02-Oct-2022 20:30 2257
ber01-VHDL13_DWMO_022100-2210022100-dsw--0-ia5 02-Oct-2022 21:30 2257
ber01-VHDL13_DWMO_022200-2210022200-dsw--0-ia5 02-Oct-2022 22:30 2242
ber01-VHDL13_DWMO_022300-2210022300-dsw--0-ia5 02-Oct-2022 23:30 2242
ber01-VHDL13_DWMO_030000-2210030000-dsw--0-ia5 03-Oct-2022 00:30 2242
ber01-VHDL13_DWMO_030100-2210030100-dsw--0-ia5 03-Oct-2022 01:30 2242
ber01-VHDL13_DWMO_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2242
ber01-VHDL13_DWMO_030300-2210030300-dsw--0-ia5 03-Oct-2022 03:30 2225
ber01-VHDL13_DWMO_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2289
ber01-VHDL13_DWMO_030500-2210030500-dsw--0-ia5 03-Oct-2022 05:30 2592
ber01-VHDL13_DWMO_030600-2210030600-dsw--0-ia5 03-Oct-2022 06:30 2592
ber01-VHDL13_DWMO_030700-2210030700-dsw--0-ia5 03-Oct-2022 07:30 2592
ber01-VHDL13_DWMO_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2738
ber01-VHDL13_DWMO_030900-2210030900-dsw--0-ia5 03-Oct-2022 09:30 2710
ber01-VHDL13_DWMO_031000-2210031000-dsw--0-ia5 03-Oct-2022 10:30 2647
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ber01-VHDL13_DWMO_031600-2210031600-dsw--0-ia5 03-Oct-2022 16:30 2440
ber01-VHDL13_DWMO_031700-2210031700-dsw--0-ia5 03-Oct-2022 17:30 2215
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ber01-VHDL13_DWMO_031900-2210031900-dsw--0-ia5 03-Oct-2022 19:30 2215
ber01-VHDL13_DWMO_032000-2210032000-dsw--0-ia5 03-Oct-2022 20:30 2370
ber01-VHDL13_DWMO_032100-2210032100-dsw--0-ia5 03-Oct-2022 21:30 2370
ber01-VHDL13_DWMP_012200-2210012200-dsw--0-ia5 01-Oct-2022 22:30 3504
ber01-VHDL13_DWMP_012300-2210012300-dsw--0-ia5 01-Oct-2022 23:30 3504
ber01-VHDL13_DWMP_020000-2210020000-dsw--0-ia5 02-Oct-2022 00:30 3504
ber01-VHDL13_DWMP_020100-2210020100-dsw--0-ia5 02-Oct-2022 01:30 3504
ber01-VHDL13_DWMP_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 3504
ber01-VHDL13_DWMP_020300-2210020300-dsw--0-ia5 02-Oct-2022 03:30 3504
ber01-VHDL13_DWMP_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3666
ber01-VHDL13_DWMP_020500-2210020500-dsw--0-ia5 02-Oct-2022 05:30 3666
ber01-VHDL13_DWMP_020600-2210020600-dsw--0-ia5 02-Oct-2022 06:30 3717
ber01-VHDL13_DWMP_020700-2210020700-dsw--0-ia5 02-Oct-2022 07:30 3717
ber01-VHDL13_DWMP_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 3741
ber01-VHDL13_DWMP_020900-2210020900-dsw--0-ia5 02-Oct-2022 09:30 3741
ber01-VHDL13_DWMP_021000-2210021000-dsw--0-ia5 02-Oct-2022 10:30 3741
ber01-VHDL13_DWMP_021100-2210021100-dsw--0-ia5 02-Oct-2022 11:30 3722
ber01-VHDL13_DWMP_021200-2210021200-dsw--0-ia5 02-Oct-2022 12:30 3766
ber01-VHDL13_DWMP_021300-2210021300-dsw--0-ia5 02-Oct-2022 13:30 3766
ber01-VHDL13_DWMP_021400-2210021400-dsw--0-ia5 02-Oct-2022 14:30 3538
ber01-VHDL13_DWMP_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 3538
ber01-VHDL13_DWMP_021600-2210021600-dsw--0-ia5 02-Oct-2022 16:30 3538
ber01-VHDL13_DWMP_021700-2210021700-dsw--0-ia5 02-Oct-2022 17:30 2715
ber01-VHDL13_DWMP_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2715
ber01-VHDL13_DWMP_021900-2210021900-dsw--0-ia5 02-Oct-2022 19:30 2857
ber01-VHDL13_DWMP_022000-2210022000-dsw--0-ia5 02-Oct-2022 20:30 2857
ber01-VHDL13_DWMP_022100-2210022100-dsw--0-ia5 02-Oct-2022 21:30 2857
ber01-VHDL13_DWMP_022200-2210022200-dsw--0-ia5 02-Oct-2022 22:30 2605
ber01-VHDL13_DWMP_022300-2210022300-dsw--0-ia5 02-Oct-2022 23:30 2605
ber01-VHDL13_DWMP_030000-2210030000-dsw--0-ia5 03-Oct-2022 00:30 2605
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ber01-VHDL13_DWMP_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2605
ber01-VHDL13_DWMP_030300-2210030300-dsw--0-ia5 03-Oct-2022 03:30 2411
ber01-VHDL13_DWMP_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2540
ber01-VHDL13_DWMP_030500-2210030500-dsw--0-ia5 03-Oct-2022 05:30 2540
ber01-VHDL13_DWMP_030600-2210030600-dsw--0-ia5 03-Oct-2022 06:30 2540
ber01-VHDL13_DWMP_030700-2210030700-dsw--0-ia5 03-Oct-2022 07:30 2540
ber01-VHDL13_DWMP_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2594
ber01-VHDL13_DWMP_030900-2210030900-dsw--0-ia5 03-Oct-2022 09:30 2594
ber01-VHDL13_DWMP_031000-2210031000-dsw--0-ia5 03-Oct-2022 10:30 2479
ber01-VHDL13_DWMP_031100-2210031100-dsw--0-ia5 03-Oct-2022 11:30 2479
ber01-VHDL13_DWMP_031200-2210031200-dsw--0-ia5 03-Oct-2022 12:30 2479
ber01-VHDL13_DWMP_031300-2210031300-dsw--0-ia5 03-Oct-2022 13:30 2479
ber01-VHDL13_DWMP_031400-2210031400-dsw--0-ia5 03-Oct-2022 14:30 2178
ber01-VHDL13_DWMP_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:30 2178
ber01-VHDL13_DWMP_031600-2210031600-dsw--0-ia5 03-Oct-2022 16:30 2178
ber01-VHDL13_DWMP_031700-2210031700-dsw--0-ia5 03-Oct-2022 17:30 2054
ber01-VHDL13_DWMP_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2054
ber01-VHDL13_DWMP_031900-2210031900-dsw--0-ia5 03-Oct-2022 19:30 2054
ber01-VHDL13_DWMP_032000-2210032000-dsw--0-ia5 03-Oct-2022 20:30 2144
ber01-VHDL13_DWMP_032100-2210032100-dsw--0-ia5 03-Oct-2022 21:30 2144
ber01-VHDL13_DWOG_020100-2210020100-dsw--0-ia5 02-Oct-2022 01:45 6057
ber01-VHDL13_DWOG_020300-2210020300-dsw--0-ia5 02-Oct-2022 03:00 5994
ber01-VHDL13_DWOG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:15 5963
ber01-VHDL13_DWOG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:00 5368
ber01-VHDL13_DWOG_021700-2210021700-dsw--0-ia5 02-Oct-2022 17:30 4134
ber01-VHDL13_DWOG_030100-2210030100-dsw--0-ia5 03-Oct-2022 01:45 4589
ber01-VHDL13_DWOG_030300-2210030300-dsw--0-ia5 03-Oct-2022 03:01 4167
ber01-VHDL13_DWOG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:15 4048
ber01-VHDL13_DWOG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:00 3928
ber01-VHDL13_DWOG_031700-2210031700-dsw--0-ia5 03-Oct-2022 17:30 3128
ber01-VHDL13_DWOH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:28 2426
ber01-VHDL13_DWOH_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:58 2394
ber01-VHDL13_DWOH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:28 2402
ber01-VHDL13_DWOH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:28 2413
ber01-VHDL13_DWOH_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:28 1976
ber01-VHDL13_DWOH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:28 1774
ber01-VHDL13_DWOH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:28 2064
ber01-VHDL13_DWOH_030400-2210030400-dsw--0-ia5 03-Oct-2022 04:58 2042
ber01-VHDL13_DWOH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:28 1939
ber01-VHDL13_DWOH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:28 2000
ber01-VHDL13_DWOH_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:28 2076
ber01-VHDL13_DWOH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:28 1902
ber01-VHDL13_DWOI_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:28 2889
ber01-VHDL13_DWOI_020400-2210020400-dsw--0-ia5 02-Oct-2022 04:58 2769
ber01-VHDL13_DWOI_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:28 2809
ber01-VHDL13_DWOI_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:28 2776
ber01-VHDL13_DWOI_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:28 2316
ber01-VHDL13_DWOI_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:28 1836
ber01-VHDL13_DWOI_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:28 2127
ber01-VHDL13_DWOI_030400-2210030400-dsw--0-ia5 03-Oct-2022 04:58 2069
ber01-VHDL13_DWOI_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:28 2061
ber01-VHDL13_DWOI_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:28 2135
ber01-VHDL13_DWOI_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:28 2199
ber01-VHDL13_DWOI_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:28 2069
ber01-VHDL13_DWPG_020030-2210020030-dsw--0-ia5 02-Oct-2022 00:30 2241
ber01-VHDL13_DWPG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2243
ber01-VHDL13_DWPG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2478
ber01-VHDL13_DWPG_020530-2210020530-dsw--0-ia5 02-Oct-2022 05:30 2476
ber01-VHDL13_DWPG_020630-2210020630-dsw--0-ia5 02-Oct-2022 06:30 2476
ber01-VHDL13_DWPG_020730-2210020730-dsw--0-ia5 02-Oct-2022 07:30 2476
ber01-VHDL13_DWPG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2414
ber01-VHDL13_DWPG_020930-2210020930-dsw--0-ia5 02-Oct-2022 09:30 2413
ber01-VHDL13_DWPG_021030-2210021030-dsw--0-ia5 02-Oct-2022 10:30 2433
ber01-VHDL13_DWPG_021130-2210021130-dsw--0-ia5 02-Oct-2022 11:30 2525
ber01-VHDL13_DWPG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 2521
ber01-VHDL13_DWPG_021330-2210021330-dsw--0-ia5 02-Oct-2022 13:30 2520
ber01-VHDL13_DWPG_021430-2210021430-dsw--0-ia5 02-Oct-2022 14:30 2520
ber01-VHDL13_DWPG_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 2017
ber01-VHDL13_DWPG_021630-2210021630-dsw--0-ia5 02-Oct-2022 16:30 2016
ber01-VHDL13_DWPG_021730-2210021730-dsw--0-ia5 02-Oct-2022 17:30 2016
ber01-VHDL13_DWPG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 1811
ber01-VHDL13_DWPG_021930-2210021930-dsw--0-ia5 02-Oct-2022 19:30 1810
ber01-VHDL13_DWPG_022030-2210022030-dsw--0-ia5 02-Oct-2022 20:30 1810
ber01-VHDL13_DWPG_030030-2210030030-dsw--0-ia5 03-Oct-2022 00:30 1936
ber01-VHDL13_DWPG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 1935
ber01-VHDL13_DWPG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2235
ber01-VHDL13_DWPG_030530-2210030530-dsw--0-ia5 03-Oct-2022 05:30 2233
ber01-VHDL13_DWPG_030630-2210030630-dsw--0-ia5 03-Oct-2022 06:30 2233
ber01-VHDL13_DWPG_030730-2210030730-dsw--0-ia5 03-Oct-2022 07:30 2233
ber01-VHDL13_DWPG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2196
ber01-VHDL13_DWPG_030930-2210030930-dsw--0-ia5 03-Oct-2022 09:30 2195
ber01-VHDL13_DWPG_031030-2210031030-dsw--0-ia5 03-Oct-2022 10:30 2195
ber01-VHDL13_DWPG_031130-2210031130-dsw--0-ia5 03-Oct-2022 11:30 2206
ber01-VHDL13_DWPG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2172
ber01-VHDL13_DWPG_031330-2210031330-dsw--0-ia5 03-Oct-2022 13:30 2171
ber01-VHDL13_DWPG_031430-2210031430-dsw--0-ia5 03-Oct-2022 14:30 2171
ber01-VHDL13_DWPG_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:30 1977
ber01-VHDL13_DWPG_031630-2210031630-dsw--0-ia5 03-Oct-2022 16:30 1976
ber01-VHDL13_DWPG_031730-2210031730-dsw--0-ia5 03-Oct-2022 17:30 1976
ber01-VHDL13_DWPG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 1790
ber01-VHDL13_DWPG_031930-2210031930-dsw--0-ia5 03-Oct-2022 19:30 1789
ber01-VHDL13_DWPG_032030-2210032030-dsw--0-ia5 03-Oct-2022 20:30 1789
ber01-VHDL13_DWPH_020030-2210020030-dsw--0-ia5 02-Oct-2022 00:30 2993
ber01-VHDL13_DWPH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2993
ber01-VHDL13_DWPH_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3304
ber01-VHDL13_DWPH_020530-2210020530-dsw--0-ia5 02-Oct-2022 05:30 3304
ber01-VHDL13_DWPH_020630-2210020630-dsw--0-ia5 02-Oct-2022 06:30 3304
ber01-VHDL13_DWPH_020730-2210020730-dsw--0-ia5 02-Oct-2022 07:30 3326
ber01-VHDL13_DWPH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 3302
ber01-VHDL13_DWPH_020930-2210020930-dsw--0-ia5 02-Oct-2022 09:30 3302
ber01-VHDL13_DWPH_021030-2210021030-dsw--0-ia5 02-Oct-2022 10:30 3302
ber01-VHDL13_DWPH_021130-2210021130-dsw--0-ia5 02-Oct-2022 11:30 3396
ber01-VHDL13_DWPH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 3382
ber01-VHDL13_DWPH_021330-2210021330-dsw--0-ia5 02-Oct-2022 13:30 3382
ber01-VHDL13_DWPH_021430-2210021430-dsw--0-ia5 02-Oct-2022 14:30 3382
ber01-VHDL13_DWPH_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 2898
ber01-VHDL13_DWPH_021630-2210021630-dsw--0-ia5 02-Oct-2022 16:30 2898
ber01-VHDL13_DWPH_021730-2210021730-dsw--0-ia5 02-Oct-2022 17:30 2898
ber01-VHDL13_DWPH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2323
ber01-VHDL13_DWPH_021930-2210021930-dsw--0-ia5 02-Oct-2022 19:30 2323
ber01-VHDL13_DWPH_022030-2210022030-dsw--0-ia5 02-Oct-2022 20:30 2323
ber01-VHDL13_DWPH_030030-2210030030-dsw--0-ia5 03-Oct-2022 00:30 2282
ber01-VHDL13_DWPH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2377
ber01-VHDL13_DWPH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2856
ber01-VHDL13_DWPH_030530-2210030530-dsw--0-ia5 03-Oct-2022 05:30 2856
ber01-VHDL13_DWPH_030630-2210030630-dsw--0-ia5 03-Oct-2022 06:30 2856
ber01-VHDL13_DWPH_030730-2210030730-dsw--0-ia5 03-Oct-2022 07:30 2856
ber01-VHDL13_DWPH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2846
ber01-VHDL13_DWPH_030930-2210030930-dsw--0-ia5 03-Oct-2022 09:30 2846
ber01-VHDL13_DWPH_031030-2210031030-dsw--0-ia5 03-Oct-2022 10:30 2846
ber01-VHDL13_DWPH_031130-2210031130-dsw--0-ia5 03-Oct-2022 11:30 2899
ber01-VHDL13_DWPH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2874
ber01-VHDL13_DWPH_031330-2210031330-dsw--0-ia5 03-Oct-2022 13:30 2874
ber01-VHDL13_DWPH_031430-2210031430-dsw--0-ia5 03-Oct-2022 14:30 2874
ber01-VHDL13_DWPH_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:30 2432
ber01-VHDL13_DWPH_031630-2210031630-dsw--0-ia5 03-Oct-2022 16:30 2432
ber01-VHDL13_DWPH_031730-2210031730-dsw--0-ia5 03-Oct-2022 17:30 2432
ber01-VHDL13_DWPH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2011
ber01-VHDL13_DWPH_031930-2210031930-dsw--0-ia5 03-Oct-2022 19:30 2011
ber01-VHDL13_DWPH_032030-2210032030-dsw--0-ia5 03-Oct-2022 20:30 2011
ber01-VHDL13_DWSG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 3251
ber01-VHDL13_DWSG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3211
ber01-VHDL13_DWSG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 3224
ber01-VHDL13_DWSG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 3165
ber01-VHDL13_DWSG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2389
ber01-VHDL13_DWSG_021800_COR-2210021800-dsw--0-ia5 02-Oct-2022 19:08 2579
ber01-VHDL13_DWSG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2296
ber01-VHDL13_DWSG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2181
ber01-VHDL13_DWSG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2163
ber01-VHDL13_DWSG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2391
ber01-VHDL13_DWSG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 2145
ber01-VHDL13_DWSN_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2391
ber01-VHDL13_DWSN_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2309
ber01-VHDL13_DWSN_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2435
ber01-VHDL13_DWSN_021300-2210021300-dsw--0-ia5 02-Oct-2022 13:30 2292
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ber01-VHDL13_DWSO_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2402
ber01-VHDL13_DWSO_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2193
ber01-VHDL13_DWSO_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2147
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pid-VHDL12_DWMG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 3412
pid-VHDL12_DWMG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2328
pid-VHDL12_DWMG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2285
pid-VHDL12_DWMG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2117
pid-VHDL12_DWMG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2181
pid-VHDL12_DWMG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2082
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swis2-VHDL20_DWHH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 2342
swis2-VHDL20_DWHH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2522
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swis2-VHDL20_DWLG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 1900
swis2-VHDL20_DWLG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 2148
swis2-VHDL20_DWLG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2132
swis2-VHDL20_DWLG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 2129
swis2-VHDL20_DWLG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 2128
swis2-VHDL20_DWLG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 1852
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swis2-VHDL20_DWLH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:45 2006
swis2-VHDL20_DWLH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 1643
swis2-VHDL20_DWLH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 1791
swis2-VHDL20_DWLH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 1841
swis2-VHDL20_DWLH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 1838
swis2-VHDL20_DWLH_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 1811
swis2-VHDL20_DWLH_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 1736
swis2-VHDL20_DWLI_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:45 1768
swis2-VHDL20_DWLI_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 1862
swis2-VHDL20_DWLI_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:45 1873
swis2-VHDL20_DWLI_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:45 1757
swis2-VHDL20_DWLI_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 1598
swis2-VHDL20_DWLI_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 1789
swis2-VHDL20_DWLI_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 1813
swis2-VHDL20_DWLI_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 1809
swis2-VHDL20_DWLI_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 1796
swis2-VHDL20_DWLI_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 1855
swis2-VHDL20_DWMG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:45 3643
swis2-VHDL20_DWMG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3802
swis2-VHDL20_DWMG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:45 3975
swis2-VHDL20_DWMG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:45 4070
swis2-VHDL20_DWMG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 2986
swis2-VHDL20_DWMG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 2815
swis2-VHDL20_DWMG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2760
swis2-VHDL20_DWMG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 2824
swis2-VHDL20_DWMG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 2725
swis2-VHDL20_DWMG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 2418
swis2-VHDL20_DWMO_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:45 2851
swis2-VHDL20_DWMO_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2843
swis2-VHDL20_DWMO_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:45 2942
swis2-VHDL20_DWMO_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:45 3068
swis2-VHDL20_DWMO_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 2435
swis2-VHDL20_DWMO_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 2457
swis2-VHDL20_DWMO_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2504
swis2-VHDL20_DWMO_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 2922
swis2-VHDL20_DWMO_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 2859
swis2-VHDL20_DWMO_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 2427
swis2-VHDL20_DWMP_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:45 3716
swis2-VHDL20_DWMP_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3878
swis2-VHDL20_DWMP_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:45 3953
swis2-VHDL20_DWMP_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:45 3978
swis2-VHDL20_DWMP_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:45 2957
swis2-VHDL20_DWMP_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:45 2817
swis2-VHDL20_DWMP_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2752
swis2-VHDL20_DWMP_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:45 2806
swis2-VHDL20_DWMP_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:45 2691
swis2-VHDL20_DWMP_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:45 2258
swis2-VHDL20_DWPG_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 2423
swis2-VHDL20_DWPG_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 2656
swis2-VHDL20_DWPG_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 2594
swis2-VHDL20_DWPG_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 2700
swis2-VHDL20_DWPG_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 2196
swis2-VHDL20_DWPG_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 1991
swis2-VHDL20_DWPG_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2115
swis2-VHDL20_DWPG_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 2413
swis2-VHDL20_DWPG_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 2376
swis2-VHDL20_DWPG_031300-2210031300-dsw--0-ia5 03-Oct-2022 12:30 2351
swis2-VHDL20_DWPG_031500-2210031500-dsw--0-ia5 03-Oct-2022 15:30 2156
swis2-VHDL20_DWPG_031800-2210031800-dsw--0-ia5 03-Oct-2022 18:30 1970
swis2-VHDL20_DWPH_020200-2210020200-dsw--0-ia5 02-Oct-2022 02:30 3173
swis2-VHDL20_DWPH_020400-2210020400-dsw--0-ia5 02-Oct-2022 05:00 3484
swis2-VHDL20_DWPH_020800-2210020800-dsw--0-ia5 02-Oct-2022 08:30 3482
swis2-VHDL20_DWPH_021300-2210021300-dsw--0-ia5 02-Oct-2022 12:30 3562
swis2-VHDL20_DWPH_021500-2210021500-dsw--0-ia5 02-Oct-2022 15:30 3078
swis2-VHDL20_DWPH_021800-2210021800-dsw--0-ia5 02-Oct-2022 18:30 2503
swis2-VHDL20_DWPH_030200-2210030200-dsw--0-ia5 03-Oct-2022 02:30 2557
swis2-VHDL20_DWPH_030400-2210030400-dsw--0-ia5 03-Oct-2022 05:00 3036
swis2-VHDL20_DWPH_030800-2210030800-dsw--0-ia5 03-Oct-2022 08:30 3026
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