Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_010600                                 01-Dec-2023 14:58                9580
FPDL13_DWMZ_020600                                 02-Dec-2023 12:29                2363
SXDL31_DWAV_010800                                 01-Dec-2023 09:07               11940
SXDL31_DWAV_011800                                 01-Dec-2023 15:37               10073
SXDL31_DWAV_020800                                 02-Dec-2023 09:06               11830
SXDL31_DWAV_301800                                 30-Nov-2023 17:45                5644
SXDL31_DWAV_LATEST                                 02-Dec-2023 09:06               11830
SXDL33_DWAV_010000                                 01-Dec-2023 12:02               11415
SXDL33_DWAV_020000                                 02-Dec-2023 12:06               18191
SXDL33_DWAV_LATEST                                 02-Dec-2023 12:06               18191
ber01-FWDL39_DWMS_011230-2312011230-dsw--0-ia5     01-Dec-2023 12:46                1100
ber01-FWDL39_DWMS_021230-2312021230-dsw--0-ia5     02-Dec-2023 13:06                1328
ber01-VHDL13_DWEH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:28                3419
ber01-VHDL13_DWEH_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:58                3482
ber01-VHDL13_DWEH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:28                4246
ber01-VHDL13_DWEH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:28                3549
ber01-VHDL13_DWEH_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:28                3514
ber01-VHDL13_DWEH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:28                3214
ber01-VHDL13_DWEH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:28                3889
ber01-VHDL13_DWEH_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:58                3957
ber01-VHDL13_DWEH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:28                3959
ber01-VHDL13_DWEH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:28                4921
ber01-VHDL13_DWEH_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:28                3608
ber01-VHDL13_DWEH_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                3133
ber01-VHDL13_DWEH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:28                3128
ber01-VHDL13_DWHG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3077
ber01-VHDL13_DWHG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3081
ber01-VHDL13_DWHG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3211
ber01-VHDL13_DWHG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3269
ber01-VHDL13_DWHG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2838
ber01-VHDL13_DWHG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3056
ber01-VHDL13_DWHG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3061
ber01-VHDL13_DWHG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2871
ber01-VHDL13_DWHG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                2848
ber01-VHDL13_DWHG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2558
ber01-VHDL13_DWHH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3047
ber01-VHDL13_DWHH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3025
ber01-VHDL13_DWHH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2929
ber01-VHDL13_DWHH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3002
ber01-VHDL13_DWHH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2667
ber01-VHDL13_DWHH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2917
ber01-VHDL13_DWHH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2883
ber01-VHDL13_DWHH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2612
ber01-VHDL13_DWHH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                2652
ber01-VHDL13_DWHH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2752
ber01-VHDL13_DWLG_010133-2312010133-dsw--0-ia5     01-Dec-2023 01:33                2192
ber01-VHDL13_DWLG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2545
ber01-VHDL13_DWLG_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:59                1888
ber01-VHDL13_DWLG_010633-2312010633-dsw--0-ia5     01-Dec-2023 06:33                1894
ber01-VHDL13_DWLG_010733-2312010733-dsw--0-ia5     01-Dec-2023 07:33                1894
ber01-VHDL13_DWLG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                1862
ber01-VHDL13_DWLG_010833-2312010833-dsw--0-ia5     01-Dec-2023 08:33                1871
ber01-VHDL13_DWLG_011033-2312011033-dsw--0-ia5     01-Dec-2023 10:33                1871
ber01-VHDL13_DWLG_011133-2312011133-dsw--0-ia5     01-Dec-2023 11:33                1871
ber01-VHDL13_DWLG_011233-2312011233-dsw--0-ia5     01-Dec-2023 12:33                1986
ber01-VHDL13_DWLG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                1980
ber01-VHDL13_DWLG_011433-2312011433-dsw--0-ia5     01-Dec-2023 14:33                1986
ber01-VHDL13_DWLG_011533-2312011533-dsw--0-ia5     01-Dec-2023 15:33                1745
ber01-VHDL13_DWLG_011633-2312011633-dsw--0-ia5     01-Dec-2023 16:33                1745
ber01-VHDL13_DWLG_011733-2312011733-dsw--0-ia5     01-Dec-2023 17:33                1745
ber01-VHDL13_DWLG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                1805
ber01-VHDL13_DWLG_011833-2312011833-dsw--0-ia5     01-Dec-2023 18:33                1811
ber01-VHDL13_DWLG_012033-2312012033-dsw--0-ia5     01-Dec-2023 20:33                1811
ber01-VHDL13_DWLG_012133-2312012133-dsw--0-ia5     01-Dec-2023 21:33                1811
ber01-VHDL13_DWLG_020133-2312020133-dsw--0-ia5     02-Dec-2023 01:33                1967
ber01-VHDL13_DWLG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2543
ber01-VHDL13_DWLG_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:59                2597
ber01-VHDL13_DWLG_020633-2312020633-dsw--0-ia5     02-Dec-2023 06:33                2603
ber01-VHDL13_DWLG_020733-2312020733-dsw--0-ia5     02-Dec-2023 07:33                2603
ber01-VHDL13_DWLG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2534
ber01-VHDL13_DWLG_020833-2312020833-dsw--0-ia5     02-Dec-2023 08:33                2546
ber01-VHDL13_DWLG_021033-2312021033-dsw--0-ia5     02-Dec-2023 10:33                2543
ber01-VHDL13_DWLG_021133-2312021133-dsw--0-ia5     02-Dec-2023 11:33                2570
ber01-VHDL13_DWLG_021233-2312021233-dsw--0-ia5     02-Dec-2023 12:33                2627
ber01-VHDL13_DWLG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                2111
ber01-VHDL13_DWLG_021433-2312021433-dsw--0-ia5     02-Dec-2023 14:33                2120
ber01-VHDL13_DWLG_021533-2312021533-dsw--0-ia5     02-Dec-2023 15:33                2120
ber01-VHDL13_DWLG_301633-2311301633-dsw--0-ia5     30-Nov-2023 16:33                2245
ber01-VHDL13_DWLG_301733-2311301733-dsw--0-ia5     30-Nov-2023 17:33                2245
ber01-VHDL13_DWLG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2004
ber01-VHDL13_DWLG_301833-2311301833-dsw--0-ia5     30-Nov-2023 18:33                2010
ber01-VHDL13_DWLG_302033-2311302033-dsw--0-ia5     30-Nov-2023 20:33                2010
ber01-VHDL13_DWLG_302133-2311302133-dsw--0-ia5     30-Nov-2023 21:33                2010
ber01-VHDL13_DWLH_010133-2312010133-dsw--0-ia5     01-Dec-2023 01:33                2070
ber01-VHDL13_DWLH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2349
ber01-VHDL13_DWLH_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:59                1681
ber01-VHDL13_DWLH_010633-2312010633-dsw--0-ia5     01-Dec-2023 06:33                1690
ber01-VHDL13_DWLH_010733-2312010733-dsw--0-ia5     01-Dec-2023 07:33                1690
ber01-VHDL13_DWLH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                1681
ber01-VHDL13_DWLH_010833-2312010833-dsw--0-ia5     01-Dec-2023 08:33                1690
ber01-VHDL13_DWLH_011033-2312011033-dsw--0-ia5     01-Dec-2023 10:33                1690
ber01-VHDL13_DWLH_011133-2312011133-dsw--0-ia5     01-Dec-2023 11:33                1690
ber01-VHDL13_DWLH_011233-2312011233-dsw--0-ia5     01-Dec-2023 12:33                1658
ber01-VHDL13_DWLH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                1649
ber01-VHDL13_DWLH_011433-2312011433-dsw--0-ia5     01-Dec-2023 14:33                1658
ber01-VHDL13_DWLH_011533-2312011533-dsw--0-ia5     01-Dec-2023 15:33                1635
ber01-VHDL13_DWLH_011633-2312011633-dsw--0-ia5     01-Dec-2023 16:33                1635
ber01-VHDL13_DWLH_011733-2312011733-dsw--0-ia5     01-Dec-2023 17:33                1635
ber01-VHDL13_DWLH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                1861
ber01-VHDL13_DWLH_011833-2312011833-dsw--0-ia5     01-Dec-2023 18:33                1870
ber01-VHDL13_DWLH_012033-2312012033-dsw--0-ia5     01-Dec-2023 20:33                1870
ber01-VHDL13_DWLH_012133-2312012133-dsw--0-ia5     01-Dec-2023 21:33                1870
ber01-VHDL13_DWLH_020133-2312020133-dsw--0-ia5     02-Dec-2023 01:33                2131
ber01-VHDL13_DWLH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2604
ber01-VHDL13_DWLH_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:59                2567
ber01-VHDL13_DWLH_020633-2312020633-dsw--0-ia5     02-Dec-2023 06:33                2576
ber01-VHDL13_DWLH_020733-2312020733-dsw--0-ia5     02-Dec-2023 07:33                2651
ber01-VHDL13_DWLH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2579
ber01-VHDL13_DWLH_020833-2312020833-dsw--0-ia5     02-Dec-2023 08:33                2588
ber01-VHDL13_DWLH_021033-2312021033-dsw--0-ia5     02-Dec-2023 10:33                2588
ber01-VHDL13_DWLH_021133-2312021133-dsw--0-ia5     02-Dec-2023 11:33                2494
ber01-VHDL13_DWLH_021233-2312021233-dsw--0-ia5     02-Dec-2023 12:33                2376
ber01-VHDL13_DWLH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                1879
ber01-VHDL13_DWLH_021433-2312021433-dsw--0-ia5     02-Dec-2023 14:33                1889
ber01-VHDL13_DWLH_021533-2312021533-dsw--0-ia5     02-Dec-2023 15:33                1889
ber01-VHDL13_DWLH_301633-2311301633-dsw--0-ia5     30-Nov-2023 16:33                2303
ber01-VHDL13_DWLH_301733-2311301733-dsw--0-ia5     30-Nov-2023 17:33                2303
ber01-VHDL13_DWLH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                1993
ber01-VHDL13_DWLH_301833-2311301833-dsw--0-ia5     30-Nov-2023 18:33                2002
ber01-VHDL13_DWLH_302033-2311302033-dsw--0-ia5     30-Nov-2023 20:33                2002
ber01-VHDL13_DWLH_302133-2311302133-dsw--0-ia5     30-Nov-2023 21:33                2002
ber01-VHDL13_DWLI_010133-2312010133-dsw--0-ia5     01-Dec-2023 01:33                2326
ber01-VHDL13_DWLI_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2488
ber01-VHDL13_DWLI_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:59                1952
ber01-VHDL13_DWLI_010633-2312010633-dsw--0-ia5     01-Dec-2023 06:33                1955
ber01-VHDL13_DWLI_010733-2312010733-dsw--0-ia5     01-Dec-2023 07:33                1955
ber01-VHDL13_DWLI_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                1949
ber01-VHDL13_DWLI_010833-2312010833-dsw--0-ia5     01-Dec-2023 08:33                1955
ber01-VHDL13_DWLI_011033-2312011033-dsw--0-ia5     01-Dec-2023 10:33                1955
ber01-VHDL13_DWLI_011133-2312011133-dsw--0-ia5     01-Dec-2023 11:33                1955
ber01-VHDL13_DWLI_011233-2312011233-dsw--0-ia5     01-Dec-2023 12:33                1921
ber01-VHDL13_DWLI_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                1915
ber01-VHDL13_DWLI_011433-2312011433-dsw--0-ia5     01-Dec-2023 14:33                1921
ber01-VHDL13_DWLI_011533-2312011533-dsw--0-ia5     01-Dec-2023 15:33                1796
ber01-VHDL13_DWLI_011633-2312011633-dsw--0-ia5     01-Dec-2023 16:33                1796
ber01-VHDL13_DWLI_011733-2312011733-dsw--0-ia5     01-Dec-2023 17:33                1796
ber01-VHDL13_DWLI_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                1745
ber01-VHDL13_DWLI_011833-2312011833-dsw--0-ia5     01-Dec-2023 18:33                1751
ber01-VHDL13_DWLI_012033-2312012033-dsw--0-ia5     01-Dec-2023 20:33                1751
ber01-VHDL13_DWLI_012133-2312012133-dsw--0-ia5     01-Dec-2023 21:33                1751
ber01-VHDL13_DWLI_020133-2312020133-dsw--0-ia5     02-Dec-2023 01:33                1984
ber01-VHDL13_DWLI_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2496
ber01-VHDL13_DWLI_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:59                2485
ber01-VHDL13_DWLI_020633-2312020633-dsw--0-ia5     02-Dec-2023 06:33                2488
ber01-VHDL13_DWLI_020733-2312020733-dsw--0-ia5     02-Dec-2023 07:33                2488
ber01-VHDL13_DWLI_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2269
ber01-VHDL13_DWLI_020833-2312020833-dsw--0-ia5     02-Dec-2023 08:33                2275
ber01-VHDL13_DWLI_021033-2312021033-dsw--0-ia5     02-Dec-2023 10:33                2275
ber01-VHDL13_DWLI_021133-2312021133-dsw--0-ia5     02-Dec-2023 11:33                2326
ber01-VHDL13_DWLI_021233-2312021233-dsw--0-ia5     02-Dec-2023 12:33                2326
ber01-VHDL13_DWLI_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                1881
ber01-VHDL13_DWLI_021433-2312021433-dsw--0-ia5     02-Dec-2023 14:33                1888
ber01-VHDL13_DWLI_021533-2312021533-dsw--0-ia5     02-Dec-2023 15:33                1888
ber01-VHDL13_DWLI_301633-2311301633-dsw--0-ia5     30-Nov-2023 16:33                2351
ber01-VHDL13_DWLI_301733-2311301733-dsw--0-ia5     30-Nov-2023 17:33                2351
ber01-VHDL13_DWLI_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2166
ber01-VHDL13_DWLI_301833-2311301833-dsw--0-ia5     30-Nov-2023 18:33                2172
ber01-VHDL13_DWLI_302033-2311302033-dsw--0-ia5     30-Nov-2023 20:33                2172
ber01-VHDL13_DWLI_302133-2311302133-dsw--0-ia5     30-Nov-2023 21:33                2172
ber01-VHDL13_DWMG_010000-2312010000-dsw--0-ia5     01-Dec-2023 00:30                4332
ber01-VHDL13_DWMG_010100-2312010100-dsw--0-ia5     01-Dec-2023 01:30                4332
ber01-VHDL13_DWMG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                4332
ber01-VHDL13_DWMG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                4046
ber01-VHDL13_DWMG_010600-2312010600-dsw--0-ia5     01-Dec-2023 06:30                4046
ber01-VHDL13_DWMG_010700-2312010700-dsw--0-ia5     01-Dec-2023 07:30                4049
ber01-VHDL13_DWMG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3923
ber01-VHDL13_DWMG_011000-2312011000-dsw--0-ia5     01-Dec-2023 10:30                3995
ber01-VHDL13_DWMG_011100-2312011100-dsw--0-ia5     01-Dec-2023 11:30                3979
ber01-VHDL13_DWMG_011200-2312011200-dsw--0-ia5     01-Dec-2023 12:30                4081
ber01-VHDL13_DWMG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                4080
ber01-VHDL13_DWMG_011400-2312011400-dsw--0-ia5     01-Dec-2023 14:30                3551
ber01-VHDL13_DWMG_011500-2312011500-dsw--0-ia5     01-Dec-2023 15:30                3106
ber01-VHDL13_DWMG_011600-2312011600-dsw--0-ia5     01-Dec-2023 16:30                3106
ber01-VHDL13_DWMG_011700-2312011700-dsw--0-ia5     01-Dec-2023 17:30                3106
ber01-VHDL13_DWMG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                3106
ber01-VHDL13_DWMG_012000-2312012000-dsw--0-ia5     01-Dec-2023 20:30                3106
ber01-VHDL13_DWMG_012100-2312012100-dsw--0-ia5     01-Dec-2023 21:30                3106
ber01-VHDL13_DWMG_012200-2312012200-dsw--0-ia5     01-Dec-2023 22:30                3106
ber01-VHDL13_DWMG_012300-2312012300-dsw--0-ia5     01-Dec-2023 23:30                3325
ber01-VHDL13_DWMG_020000-2312020000-dsw--0-ia5     02-Dec-2023 00:30                3478
ber01-VHDL13_DWMG_020100-2312020100-dsw--0-ia5     02-Dec-2023 01:30                3478
ber01-VHDL13_DWMG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3478
ber01-VHDL13_DWMG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3501
ber01-VHDL13_DWMG_020600-2312020600-dsw--0-ia5     02-Dec-2023 06:30                3501
ber01-VHDL13_DWMG_020700-2312020700-dsw--0-ia5     02-Dec-2023 07:30                3501
ber01-VHDL13_DWMG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3561
ber01-VHDL13_DWMG_021000-2312021000-dsw--0-ia5     02-Dec-2023 10:30                3561
ber01-VHDL13_DWMG_021100-2312021100-dsw--0-ia5     02-Dec-2023 11:30                3561
ber01-VHDL13_DWMG_021200-2312021200-dsw--0-ia5     02-Dec-2023 12:30                3561
ber01-VHDL13_DWMG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3563
ber01-VHDL13_DWMG_021400-2312021400-dsw--0-ia5     02-Dec-2023 14:30                3559
ber01-VHDL13_DWMG_021500-2312021500-dsw--0-ia5     02-Dec-2023 15:30                3495
ber01-VHDL13_DWMG_301600-2311301600-dsw--0-ia5     30-Nov-2023 16:30                4518
ber01-VHDL13_DWMG_301700-2311301700-dsw--0-ia5     30-Nov-2023 17:30                3618
ber01-VHDL13_DWMG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3618
ber01-VHDL13_DWMG_302000-2311302000-dsw--0-ia5     30-Nov-2023 20:30                4559
ber01-VHDL13_DWMG_302100-2311302100-dsw--0-ia5     30-Nov-2023 21:30                4559
ber01-VHDL13_DWMG_302200-2311302200-dsw--0-ia5     30-Nov-2023 22:30                4559
ber01-VHDL13_DWMG_302300-2311302300-dsw--0-ia5     30-Nov-2023 23:30                4331
ber01-VHDL13_DWMO_010000-2312010000-dsw--0-ia5     01-Dec-2023 00:30                3147
ber01-VHDL13_DWMO_010100-2312010100-dsw--0-ia5     01-Dec-2023 01:30                3147
ber01-VHDL13_DWMO_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3147
ber01-VHDL13_DWMO_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3191
ber01-VHDL13_DWMO_010600-2312010600-dsw--0-ia5     01-Dec-2023 06:30                3113
ber01-VHDL13_DWMO_010700-2312010700-dsw--0-ia5     01-Dec-2023 07:30                3116
ber01-VHDL13_DWMO_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3040
ber01-VHDL13_DWMO_011000-2312011000-dsw--0-ia5     01-Dec-2023 10:30                3087
ber01-VHDL13_DWMO_011100-2312011100-dsw--0-ia5     01-Dec-2023 11:30                3087
ber01-VHDL13_DWMO_011200-2312011200-dsw--0-ia5     01-Dec-2023 12:30                3073
ber01-VHDL13_DWMO_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3125
ber01-VHDL13_DWMO_011400-2312011400-dsw--0-ia5     01-Dec-2023 14:30                3125
ber01-VHDL13_DWMO_011500-2312011500-dsw--0-ia5     01-Dec-2023 15:30                2781
ber01-VHDL13_DWMO_011600-2312011600-dsw--0-ia5     01-Dec-2023 16:30                2781
ber01-VHDL13_DWMO_011700-2312011700-dsw--0-ia5     01-Dec-2023 17:30                2781
ber01-VHDL13_DWMO_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2781
ber01-VHDL13_DWMO_012000-2312012000-dsw--0-ia5     01-Dec-2023 20:30                2781
ber01-VHDL13_DWMO_012100-2312012100-dsw--0-ia5     01-Dec-2023 21:30                2781
ber01-VHDL13_DWMO_012200-2312012200-dsw--0-ia5     01-Dec-2023 22:30                2777
ber01-VHDL13_DWMO_012300-2312012300-dsw--0-ia5     01-Dec-2023 23:30                3044
ber01-VHDL13_DWMO_020000-2312020000-dsw--0-ia5     02-Dec-2023 00:30                3044
ber01-VHDL13_DWMO_020100-2312020100-dsw--0-ia5     02-Dec-2023 01:30                3044
ber01-VHDL13_DWMO_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3044
ber01-VHDL13_DWMO_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3006
ber01-VHDL13_DWMO_020600-2312020600-dsw--0-ia5     02-Dec-2023 06:30                3006
ber01-VHDL13_DWMO_020700-2312020700-dsw--0-ia5     02-Dec-2023 07:30                3006
ber01-VHDL13_DWMO_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3034
ber01-VHDL13_DWMO_021000-2312021000-dsw--0-ia5     02-Dec-2023 10:30                3259
ber01-VHDL13_DWMO_021100-2312021100-dsw--0-ia5     02-Dec-2023 11:30                3259
ber01-VHDL13_DWMO_021200-2312021200-dsw--0-ia5     02-Dec-2023 12:30                3259
ber01-VHDL13_DWMO_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3259
ber01-VHDL13_DWMO_021400-2312021400-dsw--0-ia5     02-Dec-2023 14:30                3259
ber01-VHDL13_DWMO_021500-2312021500-dsw--0-ia5     02-Dec-2023 15:30                3259
ber01-VHDL13_DWMO_301600-2311301600-dsw--0-ia5     30-Nov-2023 16:30                3293
ber01-VHDL13_DWMO_301700-2311301700-dsw--0-ia5     30-Nov-2023 17:30                2747
ber01-VHDL13_DWMO_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2747
ber01-VHDL13_DWMO_302000-2311302000-dsw--0-ia5     30-Nov-2023 20:30                2747
ber01-VHDL13_DWMO_302100-2311302100-dsw--0-ia5     30-Nov-2023 21:30                3372
ber01-VHDL13_DWMO_302200-2311302200-dsw--0-ia5     30-Nov-2023 22:30                3372
ber01-VHDL13_DWMO_302300-2311302300-dsw--0-ia5     30-Nov-2023 23:30                3411
ber01-VHDL13_DWMP_010000-2312010000-dsw--0-ia5     01-Dec-2023 00:30                4170
ber01-VHDL13_DWMP_010100-2312010100-dsw--0-ia5     01-Dec-2023 01:30                4170
ber01-VHDL13_DWMP_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                4170
ber01-VHDL13_DWMP_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3955
ber01-VHDL13_DWMP_010600-2312010600-dsw--0-ia5     01-Dec-2023 06:30                3955
ber01-VHDL13_DWMP_010700-2312010700-dsw--0-ia5     01-Dec-2023 07:30                3967
ber01-VHDL13_DWMP_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3883
ber01-VHDL13_DWMP_011000-2312011000-dsw--0-ia5     01-Dec-2023 10:30                3862
ber01-VHDL13_DWMP_011100-2312011100-dsw--0-ia5     01-Dec-2023 11:30                3848
ber01-VHDL13_DWMP_011200-2312011200-dsw--0-ia5     01-Dec-2023 12:30                3890
ber01-VHDL13_DWMP_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3890
ber01-VHDL13_DWMP_011400-2312011400-dsw--0-ia5     01-Dec-2023 14:30                3890
ber01-VHDL13_DWMP_011500-2312011500-dsw--0-ia5     01-Dec-2023 15:30                2859
ber01-VHDL13_DWMP_011600-2312011600-dsw--0-ia5     01-Dec-2023 16:30                2853
ber01-VHDL13_DWMP_011700-2312011700-dsw--0-ia5     01-Dec-2023 17:30                2853
ber01-VHDL13_DWMP_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2853
ber01-VHDL13_DWMP_012000-2312012000-dsw--0-ia5     01-Dec-2023 20:30                2853
ber01-VHDL13_DWMP_012100-2312012100-dsw--0-ia5     01-Dec-2023 21:30                2853
ber01-VHDL13_DWMP_012200-2312012200-dsw--0-ia5     01-Dec-2023 22:30                2853
ber01-VHDL13_DWMP_012300-2312012300-dsw--0-ia5     01-Dec-2023 23:30                3260
ber01-VHDL13_DWMP_020000-2312020000-dsw--0-ia5     02-Dec-2023 00:30                3213
ber01-VHDL13_DWMP_020100-2312020100-dsw--0-ia5     02-Dec-2023 01:30                3213
ber01-VHDL13_DWMP_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3213
ber01-VHDL13_DWMP_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3231
ber01-VHDL13_DWMP_020600-2312020600-dsw--0-ia5     02-Dec-2023 06:30                3231
ber01-VHDL13_DWMP_020700-2312020700-dsw--0-ia5     02-Dec-2023 07:30                3231
ber01-VHDL13_DWMP_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3231
ber01-VHDL13_DWMP_021000-2312021000-dsw--0-ia5     02-Dec-2023 10:30                3534
ber01-VHDL13_DWMP_021100-2312021100-dsw--0-ia5     02-Dec-2023 11:30                3534
ber01-VHDL13_DWMP_021200-2312021200-dsw--0-ia5     02-Dec-2023 12:30                3534
ber01-VHDL13_DWMP_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3533
ber01-VHDL13_DWMP_021400-2312021400-dsw--0-ia5     02-Dec-2023 14:30                3533
ber01-VHDL13_DWMP_021500-2312021500-dsw--0-ia5     02-Dec-2023 15:30                3619
ber01-VHDL13_DWMP_301600-2311301600-dsw--0-ia5     30-Nov-2023 16:30                4480
ber01-VHDL13_DWMP_301700-2311301700-dsw--0-ia5     30-Nov-2023 17:30                3640
ber01-VHDL13_DWMP_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3640
ber01-VHDL13_DWMP_302000-2311302000-dsw--0-ia5     30-Nov-2023 20:30                4210
ber01-VHDL13_DWMP_302100-2311302100-dsw--0-ia5     30-Nov-2023 21:30                4210
ber01-VHDL13_DWMP_302200-2311302200-dsw--0-ia5     30-Nov-2023 22:30                4210
ber01-VHDL13_DWMP_302300-2311302300-dsw--0-ia5     30-Nov-2023 23:30                4362
ber01-VHDL13_DWOG_010100-2312010100-dsw--0-ia5     01-Dec-2023 02:45                5892
ber01-VHDL13_DWOG_010300-2312010300-dsw--0-ia5     01-Dec-2023 04:00                5447
ber01-VHDL13_DWOG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:15                5089
ber01-VHDL13_DWOG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:00                5427
ber01-VHDL13_DWOG_011700-2312011700-dsw--0-ia5     01-Dec-2023 18:30                5009
ber01-VHDL13_DWOG_020100-2312020100-dsw--0-ia5     02-Dec-2023 02:45                6383
ber01-VHDL13_DWOG_020300-2312020300-dsw--0-ia5     02-Dec-2023 04:00                6390
ber01-VHDL13_DWOG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:15                5686
ber01-VHDL13_DWOG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:00                6020
ber01-VHDL13_DWOG_301700-2311301700-dsw--0-ia5     30-Nov-2023 18:30                4742
ber01-VHDL13_DWOH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:28                3050
ber01-VHDL13_DWOH_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:58                3145
ber01-VHDL13_DWOH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:28                3659
ber01-VHDL13_DWOH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:28                3112
ber01-VHDL13_DWOH_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:28                3126
ber01-VHDL13_DWOH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:28                2851
ber01-VHDL13_DWOH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:28                3485
ber01-VHDL13_DWOH_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:58                3410
ber01-VHDL13_DWOH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:28                3571
ber01-VHDL13_DWOH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:28                3937
ber01-VHDL13_DWOH_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:28                3043
ber01-VHDL13_DWOH_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                3175
ber01-VHDL13_DWOH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:28                3093
ber01-VHDL13_DWOI_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:28                3028
ber01-VHDL13_DWOI_010400-2312010400-dsw--0-ia5     01-Dec-2023 05:58                2883
ber01-VHDL13_DWOI_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:28                3650
ber01-VHDL13_DWOI_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:28                3084
ber01-VHDL13_DWOI_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:28                2841
ber01-VHDL13_DWOI_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:28                2636
ber01-VHDL13_DWOI_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:28                3034
ber01-VHDL13_DWOI_020400-2312020400-dsw--0-ia5     02-Dec-2023 05:58                3039
ber01-VHDL13_DWOI_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:28                3090
ber01-VHDL13_DWOI_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:28                3258
ber01-VHDL13_DWOI_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:28                2858
ber01-VHDL13_DWOI_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                2743
ber01-VHDL13_DWOI_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:28                2701
ber01-VHDL13_DWON_010147-2312010147-dsw--0-ia5     01-Dec-2023 01:47                4600
ber01-VHDL13_DWON_010352-2312010352-dsw--0-ia5     01-Dec-2023 03:53                4600
ber01-VHDL13_DWON_010629-2312010629-dsw--0-ia5     01-Dec-2023 06:30                4600
ber01-VHDL13_DWON_010731-2312010731-dsw--0-ia5     01-Dec-2023 07:31                4398
ber01-VHDL13_DWON_010734-2312010734-dsw--0-ia5     01-Dec-2023 07:34                4430
ber01-VHDL13_DWON_011109-2312011109-dsw--0-ia5     01-Dec-2023 11:09                4430
ber01-VHDL13_DWON_011238-2312011238-dsw--0-ia5     01-Dec-2023 12:38                4369
ber01-VHDL13_DWON_011558-2312011558-dsw--0-ia5     01-Dec-2023 15:58                4017
ber01-VHDL13_DWON_011757-2312011757-dsw--0-ia5     01-Dec-2023 17:57                3824
ber01-VHDL13_DWON_012101-2312012101-dsw--0-ia5     01-Dec-2023 21:01                3848
ber01-VHDL13_DWON_020010-2312020010-dsw--0-ia5     02-Dec-2023 00:10                4179
ber01-VHDL13_DWON_020235-2312020235-dsw--0-ia5     02-Dec-2023 02:35                4179
ber01-VHDL13_DWON_020354-2312020354-dsw--0-ia5     02-Dec-2023 03:54                4179
ber01-VHDL13_DWON_020626-2312020626-dsw--0-ia5     02-Dec-2023 06:26                3754
ber01-VHDL13_DWON_020829-2312020829-dsw--0-ia5     02-Dec-2023 08:29                4263
ber01-VHDL13_DWON_021101-2312021101-dsw--0-ia5     02-Dec-2023 11:01                4219
ber01-VHDL13_DWON_021217-2312021217-dsw--0-ia5     02-Dec-2023 12:17                4199
ber01-VHDL13_DWON_021539-2312021539-dsw--0-ia5     02-Dec-2023 15:39                3880
ber01-VHDL13_DWON_301556-2311301556-dsw--0-ia5     30-Nov-2023 15:56                4566
ber01-VHDL13_DWON_301608-2311301608-dsw--0-ia5     30-Nov-2023 16:08                4565
ber01-VHDL13_DWON_301758-2311301758-dsw--0-ia5     30-Nov-2023 17:59                3759
ber01-VHDL13_DWON_301929-2311301929-dsw--0-ia5     30-Nov-2023 19:29                4060
ber01-VHDL13_DWPG_010130-2312010130-dsw--0-ia5     01-Dec-2023 01:30                2532
ber01-VHDL13_DWPG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2644
ber01-VHDL13_DWPG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2626
ber01-VHDL13_DWPG_010630-2312010630-dsw--0-ia5     01-Dec-2023 06:30                2624
ber01-VHDL13_DWPG_010730-2312010730-dsw--0-ia5     01-Dec-2023 07:30                2624
ber01-VHDL13_DWPG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2257
ber01-VHDL13_DWPG_010830-2312010830-dsw--0-ia5     01-Dec-2023 08:30                2624
ber01-VHDL13_DWPG_011030-2312011030-dsw--0-ia5     01-Dec-2023 10:30                2256
ber01-VHDL13_DWPG_011130-2312011130-dsw--0-ia5     01-Dec-2023 11:30                2256
ber01-VHDL13_DWPG_011230-2312011230-dsw--0-ia5     01-Dec-2023 12:30                2219
ber01-VHDL13_DWPG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                2135
ber01-VHDL13_DWPG_011430-2312011430-dsw--0-ia5     01-Dec-2023 14:30                2134
ber01-VHDL13_DWPG_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:30                1954
ber01-VHDL13_DWPG_011530-2312011530-dsw--0-ia5     01-Dec-2023 15:30                2134
ber01-VHDL13_DWPG_011730-2312011730-dsw--0-ia5     01-Dec-2023 17:30                1953
ber01-VHDL13_DWPG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                1703
ber01-VHDL13_DWPG_011830-2312011830-dsw--0-ia5     01-Dec-2023 18:30                1953
ber01-VHDL13_DWPG_012030-2312012030-dsw--0-ia5     01-Dec-2023 20:30                1702
ber01-VHDL13_DWPG_012130-2312012130-dsw--0-ia5     01-Dec-2023 21:30                1702
ber01-VHDL13_DWPG_020130-2312020130-dsw--0-ia5     02-Dec-2023 01:30                1920
ber01-VHDL13_DWPG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2605
ber01-VHDL13_DWPG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2956
ber01-VHDL13_DWPG_020630-2312020630-dsw--0-ia5     02-Dec-2023 06:30                2954
ber01-VHDL13_DWPG_020730-2312020730-dsw--0-ia5     02-Dec-2023 07:30                2969
ber01-VHDL13_DWPG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2771
ber01-VHDL13_DWPG_020830-2312020830-dsw--0-ia5     02-Dec-2023 08:30                2998
ber01-VHDL13_DWPG_021030-2312021030-dsw--0-ia5     02-Dec-2023 10:30                2749
ber01-VHDL13_DWPG_021130-2312021130-dsw--0-ia5     02-Dec-2023 11:30                2749
ber01-VHDL13_DWPG_021230-2312021230-dsw--0-ia5     02-Dec-2023 12:30                2749
ber01-VHDL13_DWPG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                2718
ber01-VHDL13_DWPG_021430-2312021430-dsw--0-ia5     02-Dec-2023 14:30                2717
ber01-VHDL13_DWPG_021530-2312021530-dsw--0-ia5     02-Dec-2023 15:30                2717
ber01-VHDL13_DWPG_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:30                2879
ber01-VHDL13_DWPG_301730-2311301730-dsw--0-ia5     30-Nov-2023 17:30                2878
ber01-VHDL13_DWPG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2627
ber01-VHDL13_DWPG_301830-2311301830-dsw--0-ia5     30-Nov-2023 18:30                2878
ber01-VHDL13_DWPG_302030-2311302030-dsw--0-ia5     30-Nov-2023 20:30                2626
ber01-VHDL13_DWPG_302130-2311302130-dsw--0-ia5     30-Nov-2023 21:30                2626
ber01-VHDL13_DWPH_010130-2312010130-dsw--0-ia5     01-Dec-2023 01:30                2874
ber01-VHDL13_DWPH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2985
ber01-VHDL13_DWPH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2821
ber01-VHDL13_DWPH_010630-2312010630-dsw--0-ia5     01-Dec-2023 06:30                2821
ber01-VHDL13_DWPH_010730-2312010730-dsw--0-ia5     01-Dec-2023 07:30                2821
ber01-VHDL13_DWPH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2710
ber01-VHDL13_DWPH_010830-2312010830-dsw--0-ia5     01-Dec-2023 08:30                2821
ber01-VHDL13_DWPH_011030-2312011030-dsw--0-ia5     01-Dec-2023 10:30                2710
ber01-VHDL13_DWPH_011130-2312011130-dsw--0-ia5     01-Dec-2023 11:30                2710
ber01-VHDL13_DWPH_011230-2312011230-dsw--0-ia5     01-Dec-2023 12:30                2813
ber01-VHDL13_DWPH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                2821
ber01-VHDL13_DWPH_011430-2312011430-dsw--0-ia5     01-Dec-2023 14:30                2821
ber01-VHDL13_DWPH_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:30                2651
ber01-VHDL13_DWPH_011530-2312011530-dsw--0-ia5     01-Dec-2023 15:30                2821
ber01-VHDL13_DWPH_011730-2312011730-dsw--0-ia5     01-Dec-2023 17:30                2651
ber01-VHDL13_DWPH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2430
ber01-VHDL13_DWPH_011830-2312011830-dsw--0-ia5     01-Dec-2023 18:30                2651
ber01-VHDL13_DWPH_012030-2312012030-dsw--0-ia5     01-Dec-2023 20:30                2430
ber01-VHDL13_DWPH_012130-2312012130-dsw--0-ia5     01-Dec-2023 21:30                2430
ber01-VHDL13_DWPH_020130-2312020130-dsw--0-ia5     02-Dec-2023 01:30                2530
ber01-VHDL13_DWPH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3152
ber01-VHDL13_DWPH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3488
ber01-VHDL13_DWPH_020630-2312020630-dsw--0-ia5     02-Dec-2023 06:30                3488
ber01-VHDL13_DWPH_020730-2312020730-dsw--0-ia5     02-Dec-2023 07:30                3491
ber01-VHDL13_DWPH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3158
ber01-VHDL13_DWPH_020830-2312020830-dsw--0-ia5     02-Dec-2023 08:30                3491
ber01-VHDL13_DWPH_021030-2312021030-dsw--0-ia5     02-Dec-2023 10:30                3158
ber01-VHDL13_DWPH_021130-2312021130-dsw--0-ia5     02-Dec-2023 11:30                3158
ber01-VHDL13_DWPH_021230-2312021230-dsw--0-ia5     02-Dec-2023 12:30                3158
ber01-VHDL13_DWPH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3067
ber01-VHDL13_DWPH_021430-2312021430-dsw--0-ia5     02-Dec-2023 14:30                3067
ber01-VHDL13_DWPH_021530-2312021530-dsw--0-ia5     02-Dec-2023 15:30                3067
ber01-VHDL13_DWPH_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:30                3539
ber01-VHDL13_DWPH_301730-2311301730-dsw--0-ia5     30-Nov-2023 17:30                3539
ber01-VHDL13_DWPH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3055
ber01-VHDL13_DWPH_301830-2311301830-dsw--0-ia5     30-Nov-2023 18:30                3539
ber01-VHDL13_DWPH_302030-2311302030-dsw--0-ia5     30-Nov-2023 20:30                3055
ber01-VHDL13_DWPH_302130-2311302130-dsw--0-ia5     30-Nov-2023 21:30                3055
ber01-VHDL13_DWSG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3522
ber01-VHDL13_DWSG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3070
ber01-VHDL13_DWSG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3212
ber01-VHDL13_DWSG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3155
ber01-VHDL13_DWSG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2815
ber01-VHDL13_DWSG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3121
ber01-VHDL13_DWSG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3127
ber01-VHDL13_DWSG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3202
ber01-VHDL13_DWSG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3180
ber01-VHDL13_DWSG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3098
ber01-VHDL13_DWSN_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2177
ber01-VHDL13_DWSN_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2099
ber01-VHDL13_DWSN_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2245
ber01-VHDL13_DWSN_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:30                2174
ber01-VHDL13_DWSN_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2175
ber01-VHDL13_DWSN_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2351
ber01-VHDL13_DWSN_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2431
ber01-VHDL13_DWSN_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2423
ber01-VHDL13_DWSN_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:30                2360
ber01-VHDL13_DWSN_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                1949
ber01-VHDL13_DWSO_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2848
ber01-VHDL13_DWSO_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2726
ber01-VHDL13_DWSO_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2947
ber01-VHDL13_DWSO_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:30                2715
ber01-VHDL13_DWSO_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2411
ber01-VHDL13_DWSO_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2722
ber01-VHDL13_DWSO_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2802
ber01-VHDL13_DWSO_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2795
ber01-VHDL13_DWSO_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:30                2731
ber01-VHDL13_DWSO_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2722
ber01-VHDL13_DWSP_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                2637
ber01-VHDL13_DWSP_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2515
ber01-VHDL13_DWSP_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2745
ber01-VHDL13_DWSP_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:30                2644
ber01-VHDL13_DWSP_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2274
ber01-VHDL13_DWSP_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2527
ber01-VHDL13_DWSP_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2607
ber01-VHDL13_DWSP_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                2600
ber01-VHDL13_DWSP_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:30                2536
ber01-VHDL13_DWSP_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                2531
ber01-VHDL17_DWOG_011200-2312011200-dsw--0-ia5     01-Dec-2023 12:37                3569
ber01-VHDL17_DWOG_021200-2312021200-dsw--0-ia5     02-Dec-2023 13:29                3921
ber01-VHDL20_DWHG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3501
ber01-VHDL20_DWHG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3499
ber01-VHDL20_DWHG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3869
ber01-VHDL20_DWHG_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:45                3687
ber01-VHDL20_DWHG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3256
ber01-VHDL20_DWHG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3474
ber01-VHDL20_DWHG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3451
ber01-VHDL20_DWHG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3451
ber01-VHDL20_DWHG_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:45                3235
ber01-VHDL20_DWHG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                2982
ber01-VHDL20_DWHH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3478
ber01-VHDL20_DWHH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3452
ber01-VHDL20_DWHH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3560
ber01-VHDL20_DWHH_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:45                3434
ber01-VHDL20_DWHH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3099
ber01-VHDL20_DWHH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3349
ber01-VHDL20_DWHH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3271
ber01-VHDL20_DWHH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3204
ber01-VHDL20_DWHH_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:45                3048
ber01-VHDL20_DWHH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3183
pid-VHDL12_DWHG_010200-2312010200-dsw--0-ia5       01-Dec-2023 03:30                2608
pid-VHDL12_DWHG_010400-2312010400-dsw--0-ia5       01-Dec-2023 06:00                2610
pid-VHDL12_DWHG_020200-2312020200-dsw--0-ia5       02-Dec-2023 03:30                2620
pid-VHDL12_DWHG_020400-2312020400-dsw--0-ia5       02-Dec-2023 06:00                2623
pid-VHDL12_DWHH_010200-2312010200-dsw--0-ia5       01-Dec-2023 03:30                2639
pid-VHDL12_DWHH_010400-2312010400-dsw--0-ia5       01-Dec-2023 06:00                2617
pid-VHDL12_DWHH_020200-2312020200-dsw--0-ia5       02-Dec-2023 03:30                2452
pid-VHDL12_DWHH_020400-2312020400-dsw--0-ia5       02-Dec-2023 06:00                2418
pid-VHDL12_DWMG_010200-2312010200-dsw--0-ia5       01-Dec-2023 03:30                3969
pid-VHDL12_DWMG_010400-2312010400-dsw--0-ia5       01-Dec-2023 06:00                3683
pid-VHDL12_DWMG_010800-2312010800-dsw--0-ia5       01-Dec-2023 09:30                3567
pid-VHDL12_DWMG_011300-2312011300-dsw--0-ia5       01-Dec-2023 13:30                3623
pid-VHDL12_DWMG_011800-2312011800-dsw--0-ia5       01-Dec-2023 19:30                2627
pid-VHDL12_DWMG_020200-2312020200-dsw--0-ia5       02-Dec-2023 03:30                3039
pid-VHDL12_DWMG_020400-2312020400-dsw--0-ia5       02-Dec-2023 06:00                3062
pid-VHDL12_DWMG_020800-2312020800-dsw--0-ia5       02-Dec-2023 09:30                3122
pid-VHDL12_DWMG_021300-2312021300-dsw--0-ia5       02-Dec-2023 13:30                3124
pid-VHDL12_DWMG_301800-2311301800-dsw--0-ia5       30-Nov-2023 19:30                3223
pid-VHDL12_DWSG_010200-2312010200-dsw--0-ia5       01-Dec-2023 03:30                3069
pid-VHDL12_DWSG_020200-2312020200-dsw--0-ia5       02-Dec-2023 03:30                2642
swis2-VHDL20_DWEG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3492
swis2-VHDL20_DWEG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:15                3674
swis2-VHDL20_DWEG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3852
swis2-VHDL20_DWEG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                3644
swis2-VHDL20_DWEG_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:45                3686
swis2-VHDL20_DWEG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3414
swis2-VHDL20_DWEG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3847
swis2-VHDL20_DWEG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:15                3922
swis2-VHDL20_DWEG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                4414
swis2-VHDL20_DWEG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                4452
swis2-VHDL20_DWEG_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:45                3692
swis2-VHDL20_DWEG_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                3696
swis2-VHDL20_DWEG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3617
swis2-VHDL20_DWEH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3819
swis2-VHDL20_DWEH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:15                3987
swis2-VHDL20_DWEH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                4178
swis2-VHDL20_DWEH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                4057
swis2-VHDL20_DWEH_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:45                4019
swis2-VHDL20_DWEH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3741
swis2-VHDL20_DWEH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                4295
swis2-VHDL20_DWEH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:15                4429
swis2-VHDL20_DWEH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                4826
swis2-VHDL20_DWEH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                5396
swis2-VHDL20_DWEH_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:45                3710
swis2-VHDL20_DWEH_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                3714
swis2-VHDL20_DWEH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3731
swis2-VHDL20_DWEI_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3537
swis2-VHDL20_DWEI_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:15                3449
swis2-VHDL20_DWEI_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3860
swis2-VHDL20_DWEI_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                3653
swis2-VHDL20_DWEI_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:45                3407
swis2-VHDL20_DWEI_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3202
swis2-VHDL20_DWEI_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3411
swis2-VHDL20_DWEI_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:15                3530
swis2-VHDL20_DWEI_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                4008
swis2-VHDL20_DWEI_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                3752
swis2-VHDL20_DWEI_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:45                3304
swis2-VHDL20_DWEI_301500_COR-2311301500-dsw--0-ia5 30-Nov-2023 16:30                3308
swis2-VHDL20_DWEI_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3266
swis2-VHDL20_DWHG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3501
swis2-VHDL20_DWHG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3499
swis2-VHDL20_DWHG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3869
swis2-VHDL20_DWHG_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:45                3687
swis2-VHDL20_DWHG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3256
swis2-VHDL20_DWHG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3474
swis2-VHDL20_DWHG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3451
swis2-VHDL20_DWHG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3451
swis2-VHDL20_DWHG_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:45                3235
swis2-VHDL20_DWHG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                2982
swis2-VHDL20_DWHH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3478
swis2-VHDL20_DWHH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3452
swis2-VHDL20_DWHH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3560
swis2-VHDL20_DWHH_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:45                3434
swis2-VHDL20_DWHH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3099
swis2-VHDL20_DWHH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3349
swis2-VHDL20_DWHH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3271
swis2-VHDL20_DWHH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3204
swis2-VHDL20_DWHH_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:45                3048
swis2-VHDL20_DWHH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3183
swis2-VHDL20_DWLG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3004
swis2-VHDL20_DWLG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2340
swis2-VHDL20_DWLG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                2475
swis2-VHDL20_DWLG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                2432
swis2-VHDL20_DWLG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                2257
swis2-VHDL20_DWLG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                2998
swis2-VHDL20_DWLG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3053
swis2-VHDL20_DWLG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3191
swis2-VHDL20_DWLG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                2531
swis2-VHDL20_DWLG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                2455
swis2-VHDL20_DWLH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                2816
swis2-VHDL20_DWLH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2140
swis2-VHDL20_DWLH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                2303
swis2-VHDL20_DWLH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                2108
swis2-VHDL20_DWLH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                2320
swis2-VHDL20_DWLH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3066
swis2-VHDL20_DWLH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2988
swis2-VHDL20_DWLH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3247
swis2-VHDL20_DWLH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                2301
swis2-VHDL20_DWLH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                2452
swis2-VHDL20_DWLI_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                2947
swis2-VHDL20_DWLI_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                2404
swis2-VHDL20_DWLI_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                2564
swis2-VHDL20_DWLI_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                2370
swis2-VHDL20_DWLI_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                2200
swis2-VHDL20_DWLI_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                2954
swis2-VHDL20_DWLI_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                2891
swis2-VHDL20_DWLI_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                2878
swis2-VHDL20_DWLI_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                2291
swis2-VHDL20_DWLI_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                2616
swis2-VHDL20_DWMG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                4830
swis2-VHDL20_DWMG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                4442
swis2-VHDL20_DWMG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                4559
swis2-VHDL20_DWMG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                4491
swis2-VHDL20_DWMG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3517
swis2-VHDL20_DWMG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3887
swis2-VHDL20_DWMG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3942
swis2-VHDL20_DWMG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                4236
swis2-VHDL20_DWMG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                3998
swis2-VHDL20_DWMG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                4106
swis2-VHDL20_DWMO_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                3549
swis2-VHDL20_DWMO_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3591
swis2-VHDL20_DWMO_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3658
swis2-VHDL20_DWMO_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                3542
swis2-VHDL20_DWMO_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3198
swis2-VHDL20_DWMO_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3461
swis2-VHDL20_DWMO_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3450
swis2-VHDL20_DWMO_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3941
swis2-VHDL20_DWMO_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                3701
swis2-VHDL20_DWMO_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3149
swis2-VHDL20_DWMP_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                4670
swis2-VHDL20_DWMP_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                4351
swis2-VHDL20_DWMP_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                4513
swis2-VHDL20_DWMP_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:45                4289
swis2-VHDL20_DWMP_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3246
swis2-VHDL20_DWMP_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3624
swis2-VHDL20_DWMP_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3671
swis2-VHDL20_DWMP_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                4216
swis2-VHDL20_DWMP_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:45                3974
swis2-VHDL20_DWMP_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                4125
swis2-VHDL20_DWPG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3044
swis2-VHDL20_DWPG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3023
swis2-VHDL20_DWPG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                2813
swis2-VHDL20_DWPG_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                2698
swis2-VHDL20_DWPG_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:30                2492
swis2-VHDL20_DWPG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                2242
swis2-VHDL20_DWPG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                2991
swis2-VHDL20_DWPG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3297
swis2-VHDL20_DWPG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3453
swis2-VHDL20_DWPG_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3529
swis2-VHDL20_DWPG_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:30                3480
swis2-VHDL20_DWPG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3229
swis2-VHDL20_DWPH_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:30                3519
swis2-VHDL20_DWPH_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:00                3300
swis2-VHDL20_DWPH_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:30                3464
swis2-VHDL20_DWPH_011300-2312011300-dsw--0-ia5     01-Dec-2023 13:30                3575
swis2-VHDL20_DWPH_011500-2312011500-dsw--0-ia5     01-Dec-2023 16:30                3346
swis2-VHDL20_DWPH_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:30                3125
swis2-VHDL20_DWPH_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:30                3598
swis2-VHDL20_DWPH_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:00                3919
swis2-VHDL20_DWPH_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:30                3971
swis2-VHDL20_DWPH_021300-2312021300-dsw--0-ia5     02-Dec-2023 13:30                3998
swis2-VHDL20_DWPH_301500-2311301500-dsw--0-ia5     30-Nov-2023 16:30                4312
swis2-VHDL20_DWPH_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:30                3828
swis2-VHDL20_DWSG_010200-2312010200-dsw--0-ia5     01-Dec-2023 03:45                4000
swis2-VHDL20_DWSG_010400-2312010400-dsw--0-ia5     01-Dec-2023 06:15                3472
swis2-VHDL20_DWSG_010800-2312010800-dsw--0-ia5     01-Dec-2023 09:45                3824
swis2-VHDL20_DWSG_011300-2312011300-dsw--0-ia5     01-Dec-2023 14:45                3559
swis2-VHDL20_DWSG_011800-2312011800-dsw--0-ia5     01-Dec-2023 19:45                3219
swis2-VHDL20_DWSG_020200-2312020200-dsw--0-ia5     02-Dec-2023 03:45                3516
swis2-VHDL20_DWSG_020400-2312020400-dsw--0-ia5     02-Dec-2023 06:15                3591
swis2-VHDL20_DWSG_020800-2312020800-dsw--0-ia5     02-Dec-2023 09:45                3886
swis2-VHDL20_DWSG_021300-2312021300-dsw--0-ia5     02-Dec-2023 14:45                3670
swis2-VHDL20_DWSG_301800-2311301800-dsw--0-ia5     30-Nov-2023 19:45                3624
wst04-VHDL20_DWEG_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              249822
wst04-VHDL20_DWEG_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:15              249486
wst04-VHDL20_DWEG_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              250479
wst04-VHDL20_DWEG_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              252822
wst04-VHDL20_DWEG_011500-2312011500-omedes--0.pdf  01-Dec-2023 16:45              252880
wst04-VHDL20_DWEG_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              251977
wst04-VHDL20_DWEG_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              253843
wst04-VHDL20_DWEG_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:15              253177
wst04-VHDL20_DWEG_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              254434
wst04-VHDL20_DWEG_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              254578
wst04-VHDL20_DWEG_301500-2311301500-omedes--0.pdf  30-Nov-2023 16:45              249380
wst04-VHDL20_DWEG_301500_COR-2311301500-omedes-..> 30-Nov-2023 16:30              249380
wst04-VHDL20_DWEG_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              249195
wst04-VHDL20_DWEH_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              248079
wst04-VHDL20_DWEH_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:15              248170
wst04-VHDL20_DWEH_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              248920
wst04-VHDL20_DWEH_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              253490
wst04-VHDL20_DWEH_011500-2312011500-omedes--0.pdf  01-Dec-2023 16:45              253536
wst04-VHDL20_DWEH_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              253197
wst04-VHDL20_DWEH_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              254269
wst04-VHDL20_DWEH_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:15              253617
wst04-VHDL20_DWEH_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              253793
wst04-VHDL20_DWEH_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              252543
wst04-VHDL20_DWEH_301500-2311301500-omedes--0.pdf  30-Nov-2023 16:45              247778
wst04-VHDL20_DWEH_301500_COR-2311301500-omedes-..> 30-Nov-2023 16:30              247778
wst04-VHDL20_DWEH_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              248027
wst04-VHDL20_DWEI_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              338278
wst04-VHDL20_DWEI_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:15              338112
wst04-VHDL20_DWEI_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              338776
wst04-VHDL20_DWEI_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              341870
wst04-VHDL20_DWEI_011500-2312011500-omedes--0.pdf  01-Dec-2023 16:45              341553
wst04-VHDL20_DWEI_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              341303
wst04-VHDL20_DWEI_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              341631
wst04-VHDL20_DWEI_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:15              341525
wst04-VHDL20_DWEI_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              342200
wst04-VHDL20_DWEI_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              345340
wst04-VHDL20_DWEI_301500-2311301500-omedes--0.pdf  30-Nov-2023 16:45              338322
wst04-VHDL20_DWEI_301500_COR-2311301500-omedes-..> 30-Nov-2023 16:30              338322
wst04-VHDL20_DWEI_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              337741
wst04-VHDL20_DWHG_010200-2312010200-zblks888--0..> 01-Dec-2023 03:45              331885
wst04-VHDL20_DWHG_010400-2312010400-zblks888--0..> 01-Dec-2023 06:00              331856
wst04-VHDL20_DWHG_010800-2312010800-zblks888--0..> 01-Dec-2023 09:45              333984
wst04-VHDL20_DWHG_011300-2312011300-zblks888--0..> 01-Dec-2023 14:45              338258
wst04-VHDL20_DWHG_011800-2312011800-zblks888--0..> 01-Dec-2023 19:45              337639
wst04-VHDL20_DWHG_020200-2312020200-zblks888--0..> 02-Dec-2023 03:45              337609
wst04-VHDL20_DWHG_020400-2312020400-zblks888--0..> 02-Dec-2023 06:00              337582
wst04-VHDL20_DWHG_020800-2312020800-zblks888--0..> 02-Dec-2023 09:45              337741
wst04-VHDL20_DWHG_021300-2312021300-zblks888--0..> 02-Dec-2023 14:45              333841
wst04-VHDL20_DWHG_301800-2311301800-zblks888--0..> 30-Nov-2023 19:45              331519
wst04-VHDL20_DWHH_010200-2312010200-zblks888--0..> 01-Dec-2023 03:45              334132
wst04-VHDL20_DWHH_010400-2312010400-zblks888--0..> 01-Dec-2023 06:00              334092
wst04-VHDL20_DWHH_010800-2312010800-zblks888--0..> 01-Dec-2023 09:45              334652
wst04-VHDL20_DWHH_011300-2312011300-zblks888--0..> 01-Dec-2023 14:45              327358
wst04-VHDL20_DWHH_011800-2312011800-zblks888--0..> 01-Dec-2023 19:45              327019
wst04-VHDL20_DWHH_020200-2312020200-zblks888--0..> 02-Dec-2023 03:45              326882
wst04-VHDL20_DWHH_020400-2312020400-zblks888--0..> 02-Dec-2023 06:00              326939
wst04-VHDL20_DWHH_020800-2312020800-zblks888--0..> 02-Dec-2023 09:45              326729
wst04-VHDL20_DWHH_021300-2312021300-zblks888--0..> 02-Dec-2023 14:45              327079
wst04-VHDL20_DWHH_301800-2311301800-zblks888--0..> 30-Nov-2023 19:45              333751
wst04-VHDL20_DWLG_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:40              329304
wst04-VHDL20_DWLG_010400-2312010400-omedes--0.pdf  01-Dec-2023 05:59              328275
wst04-VHDL20_DWLG_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:40              328246
wst04-VHDL20_DWLG_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:40              329572
wst04-VHDL20_DWLG_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:40              329295
wst04-VHDL20_DWLG_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:40              330910
wst04-VHDL20_DWLG_020400-2312020400-omedes--0.pdf  02-Dec-2023 05:59              331095
wst04-VHDL20_DWLG_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:40              331546
wst04-VHDL20_DWLG_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:40              320037
wst04-VHDL20_DWLG_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:40              328777
wst04-VHDL20_DWLH_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:40              330348
wst04-VHDL20_DWLH_010400-2312010400-omedes--0.pdf  01-Dec-2023 05:59              328221
wst04-VHDL20_DWLH_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:40              328235
wst04-VHDL20_DWLH_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:40              322849
wst04-VHDL20_DWLH_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:40              322792
wst04-VHDL20_DWLH_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:40              323893
wst04-VHDL20_DWLH_020400-2312020400-omedes--0.pdf  02-Dec-2023 05:59              324379
wst04-VHDL20_DWLH_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:40              324588
wst04-VHDL20_DWLH_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:40              323306
wst04-VHDL20_DWLH_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:40              329419
wst04-VHDL20_DWLI_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:40              325841
wst04-VHDL20_DWLI_010400-2312010400-omedes--0.pdf  01-Dec-2023 05:59              324526
wst04-VHDL20_DWLI_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:40              324526
wst04-VHDL20_DWLI_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:40              322879
wst04-VHDL20_DWLI_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:40              322006
wst04-VHDL20_DWLI_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:40              324188
wst04-VHDL20_DWLI_020400-2312020400-omedes--0.pdf  02-Dec-2023 05:59              324288
wst04-VHDL20_DWLI_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:40              324248
wst04-VHDL20_DWLI_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:40              323479
wst04-VHDL20_DWLI_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:40              325026
wst04-VHDL20_DWMG_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              538384
wst04-VHDL20_DWMG_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:00              537314
wst04-VHDL20_DWMG_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              538241
wst04-VHDL20_DWMG_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              537728
wst04-VHDL20_DWMG_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              535883
wst04-VHDL20_DWMG_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              536862
wst04-VHDL20_DWMG_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:00              536807
wst04-VHDL20_DWMG_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              537199
wst04-VHDL20_DWMG_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              538055
wst04-VHDL20_DWMG_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              536912
wst04-VHDL20_DWMO_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              431189
wst04-VHDL20_DWMO_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:00              429912
wst04-VHDL20_DWMO_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              429527
wst04-VHDL20_DWMO_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              428758
wst04-VHDL20_DWMO_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              428403
wst04-VHDL20_DWMO_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              428791
wst04-VHDL20_DWMO_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:00              429199
wst04-VHDL20_DWMO_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              429524
wst04-VHDL20_DWMO_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              423130
wst04-VHDL20_DWMO_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              429136
wst04-VHDL20_DWMP_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              554620
wst04-VHDL20_DWMP_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:00              556254
wst04-VHDL20_DWMP_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              557010
wst04-VHDL20_DWMP_011300-2312011300-omedes--0.pdf  01-Dec-2023 13:45              559172
wst04-VHDL20_DWMP_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              556588
wst04-VHDL20_DWMP_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              556331
wst04-VHDL20_DWMP_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:00              557632
wst04-VHDL20_DWMP_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              559210
wst04-VHDL20_DWMP_021300-2312021300-omedes--0.pdf  02-Dec-2023 13:45              563482
wst04-VHDL20_DWMP_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              556783
wst04-VHDL20_DWPG_010200-2312010200-zblks892--0..> 01-Dec-2023 03:30              327559
wst04-VHDL20_DWPG_010400-2312010400-zblks892--0..> 01-Dec-2023 06:00              326979
wst04-VHDL20_DWPG_010800-2312010800-zblks892--0..> 01-Dec-2023 09:30              371627
wst04-VHDL20_DWPG_011300-2312011300-zblks892--0..> 01-Dec-2023 13:30              331617
wst04-VHDL20_DWPG_011500-2312011500-zblks892--0..> 01-Dec-2023 16:30              331586
wst04-VHDL20_DWPG_011800-2312011800-zblks892--0..> 01-Dec-2023 19:30              331389
wst04-VHDL20_DWPG_020200-2312020200-zblks892--0..> 02-Dec-2023 03:30              331801
wst04-VHDL20_DWPG_020400-2312020400-zblks892--0..> 02-Dec-2023 06:00              332367
wst04-VHDL20_DWPG_020800-2312020800-zblks892--0..> 02-Dec-2023 09:30              377210
wst04-VHDL20_DWPG_021300-2312021300-zblks892--0..> 02-Dec-2023 13:30              324697
wst04-VHDL20_DWPG_301500-2311301500-zblks892--0..> 30-Nov-2023 16:30              327661
wst04-VHDL20_DWPG_301800-2311301800-zblks892--0..> 30-Nov-2023 19:30              327491
wst04-VHDL20_DWPH_010200-2312010200-zblks892--0..> 01-Dec-2023 03:30              246966
wst04-VHDL20_DWPH_010400-2312010400-zblks892--0..> 01-Dec-2023 06:00              246126
wst04-VHDL20_DWPH_010800-2312010800-zblks892--0..> 01-Dec-2023 09:30              290692
wst04-VHDL20_DWPH_011300-2312011300-zblks892--0..> 01-Dec-2023 13:30              246736
wst04-VHDL20_DWPH_011500-2312011500-zblks892--0..> 01-Dec-2023 16:30              246752
wst04-VHDL20_DWPH_011800-2312011800-zblks892--0..> 01-Dec-2023 19:30              290575
wst04-VHDL20_DWPH_020200-2312020200-zblks892--0..> 02-Dec-2023 03:30              246210
wst04-VHDL20_DWPH_020400-2312020400-zblks892--0..> 02-Dec-2023 06:00              247417
wst04-VHDL20_DWPH_020800-2312020800-zblks892--0..> 02-Dec-2023 09:30              292054
wst04-VHDL20_DWPH_021300-2312021300-zblks892--0..> 02-Dec-2023 13:30              243887
wst04-VHDL20_DWPH_301500-2311301500-zblks892--0..> 30-Nov-2023 16:30              247338
wst04-VHDL20_DWPH_301800-2311301800-zblks892--0..> 30-Nov-2023 19:30              291352
wst04-VHDL20_DWSG_010200-2312010200-omedes--0.pdf  01-Dec-2023 03:45              347870
wst04-VHDL20_DWSG_010400-2312010400-omedes--0.pdf  01-Dec-2023 06:15              347151
wst04-VHDL20_DWSG_010800-2312010800-omedes--0.pdf  01-Dec-2023 09:45              347295
wst04-VHDL20_DWSG_011300-2312011300-omedes--0.pdf  01-Dec-2023 14:45              346778
wst04-VHDL20_DWSG_011800-2312011800-omedes--0.pdf  01-Dec-2023 19:45              346459
wst04-VHDL20_DWSG_020200-2312020200-omedes--0.pdf  02-Dec-2023 03:45              346898
wst04-VHDL20_DWSG_020400-2312020400-omedes--0.pdf  02-Dec-2023 06:15              346993
wst04-VHDL20_DWSG_020800-2312020800-omedes--0.pdf  02-Dec-2023 09:45              346796
wst04-VHDL20_DWSG_021300-2312021300-omedes--0.pdf  02-Dec-2023 14:45              344518
wst04-VHDL20_DWSG_301800-2311301800-omedes--0.pdf  30-Nov-2023 19:45              346790