Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_010600                                 01-Dec-2021 09:17                3015
FPDL13_DWMZ_020600                                 02-Dec-2021 09:14                2496
FPDL13_DWMZ_030600                                 03-Dec-2021 07:53                2429
SXDL31_DWAV_010800                                 01-Dec-2021 08:54               10910
SXDL31_DWAV_011800                                 01-Dec-2021 17:41               19625
SXDL31_DWAV_020800                                 02-Dec-2021 08:41               11045
SXDL31_DWAV_021800                                 02-Dec-2021 17:38               20341
SXDL31_DWAV_LATEST                                 02-Dec-2021 17:38               20341
SXDL33_DWAV_010000                                 01-Dec-2021 10:57                6974
SXDL33_DWAV_020000                                 02-Dec-2021 12:18                7967
SXDL33_DWAV_LATEST                                 02-Dec-2021 12:18                7967
ber01-FWDL39_DWMS_011230-2112011230-dsw--0-ia5     01-Dec-2021 13:38                1491
ber01-FWDL39_DWMS_021230-2112021230-dsw--0-ia5     02-Dec-2021 13:20                1231
ber01-VHDL13_DWEH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:28                3953
ber01-VHDL13_DWEH_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 10:01                4076
ber01-VHDL13_DWEH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:28                4538
ber01-VHDL13_DWEH_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:28                4415
ber01-VHDL13_DWEH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:28                3655
ber01-VHDL13_DWEH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:28                3547
ber01-VHDL13_DWEH_020400-2112020400-dsw--0-ia5     02-Dec-2021 05:58                3795
ber01-VHDL13_DWEH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:28                3854
ber01-VHDL13_DWEH_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:51                3800
ber01-VHDL13_DWEH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:28                4346
ber01-VHDL13_DWEH_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:28                4082
ber01-VHDL13_DWEH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:28                3502
ber01-VHDL13_DWEH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:28                3938
ber01-VHDL13_DWEH_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:58                4104
ber01-VHDL13_DWHG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3315
ber01-VHDL13_DWHG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3458
ber01-VHDL13_DWHG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3033
ber01-VHDL13_DWHG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3040
ber01-VHDL13_DWHG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3022
ber01-VHDL13_DWHG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3022
ber01-VHDL13_DWHG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3165
ber01-VHDL13_DWHG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2836
ber01-VHDL13_DWHG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                2930
ber01-VHDL13_DWHG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2934
ber01-VHDL13_DWHH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3389
ber01-VHDL13_DWHH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3444
ber01-VHDL13_DWHH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                2995
ber01-VHDL13_DWHH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                2923
ber01-VHDL13_DWHH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2872
ber01-VHDL13_DWHH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                2872
ber01-VHDL13_DWHH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                2931
ber01-VHDL13_DWHH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2691
ber01-VHDL13_DWHH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                2581
ber01-VHDL13_DWHH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2566
ber01-VHDL13_DWLG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                2925
ber01-VHDL13_DWLG_010833-2112010833-dsw--0-ia5     01-Dec-2021 08:33                2934
ber01-VHDL13_DWLG_011033-2112011033-dsw--0-ia5     01-Dec-2021 10:33                2934
ber01-VHDL13_DWLG_011133-2112011133-dsw--0-ia5     01-Dec-2021 11:33                3206
ber01-VHDL13_DWLG_011233-2112011233-dsw--0-ia5     01-Dec-2021 12:33                3206
ber01-VHDL13_DWLG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3215
ber01-VHDL13_DWLG_011433-2112011433-dsw--0-ia5     01-Dec-2021 14:33                3221
ber01-VHDL13_DWLG_011533-2112011533-dsw--0-ia5     01-Dec-2021 15:33                3221
ber01-VHDL13_DWLG_011633-2112011633-dsw--0-ia5     01-Dec-2021 16:33                3221
ber01-VHDL13_DWLG_011733-2112011733-dsw--0-ia5     01-Dec-2021 17:33                3221
ber01-VHDL13_DWLG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                2776
ber01-VHDL13_DWLG_011833-2112011833-dsw--0-ia5     01-Dec-2021 18:33                2787
ber01-VHDL13_DWLG_012033-2112012033-dsw--0-ia5     01-Dec-2021 20:33                2782
ber01-VHDL13_DWLG_012133-2112012133-dsw--0-ia5     01-Dec-2021 21:33                2782
ber01-VHDL13_DWLG_020133-2112020133-dsw--0-ia5     02-Dec-2021 01:33                2814
ber01-VHDL13_DWLG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                2808
ber01-VHDL13_DWLG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2588
ber01-VHDL13_DWLG_020633-2112020633-dsw--0-ia5     02-Dec-2021 06:33                2594
ber01-VHDL13_DWLG_020733-2112020733-dsw--0-ia5     02-Dec-2021 07:33                2785
ber01-VHDL13_DWLG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                2927
ber01-VHDL13_DWLG_020833-2112020833-dsw--0-ia5     02-Dec-2021 08:33                2785
ber01-VHDL13_DWLG_021033-2112021033-dsw--0-ia5     02-Dec-2021 10:33                2936
ber01-VHDL13_DWLG_021133-2112021133-dsw--0-ia5     02-Dec-2021 11:33                2862
ber01-VHDL13_DWLG_021233-2112021233-dsw--0-ia5     02-Dec-2021 12:33                2862
ber01-VHDL13_DWLG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                2906
ber01-VHDL13_DWLG_021433-2112021433-dsw--0-ia5     02-Dec-2021 14:33                2912
ber01-VHDL13_DWLG_021533-2112021533-dsw--0-ia5     02-Dec-2021 15:33                2835
ber01-VHDL13_DWLG_021633-2112021633-dsw--0-ia5     02-Dec-2021 16:33                2835
ber01-VHDL13_DWLG_021733-2112021733-dsw--0-ia5     02-Dec-2021 17:33                3217
ber01-VHDL13_DWLG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3068
ber01-VHDL13_DWLG_021833-2112021833-dsw--0-ia5     02-Dec-2021 18:33                3074
ber01-VHDL13_DWLG_022033-2112022033-dsw--0-ia5     02-Dec-2021 20:33                3074
ber01-VHDL13_DWLG_022133-2112022133-dsw--0-ia5     02-Dec-2021 21:33                3074
ber01-VHDL13_DWLG_030133-2112030133-dsw--0-ia5     03-Dec-2021 01:33                3284
ber01-VHDL13_DWLG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3278
ber01-VHDL13_DWLG_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:59                3263
ber01-VHDL13_DWLG_030633-2112030633-dsw--0-ia5     03-Dec-2021 06:33                3269
ber01-VHDL13_DWLG_030733-2112030733-dsw--0-ia5     03-Dec-2021 07:33                3269
ber01-VHDL13_DWLH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3328
ber01-VHDL13_DWLH_010833-2112010833-dsw--0-ia5     01-Dec-2021 08:33                3337
ber01-VHDL13_DWLH_011033-2112011033-dsw--0-ia5     01-Dec-2021 10:33                3337
ber01-VHDL13_DWLH_011133-2112011133-dsw--0-ia5     01-Dec-2021 11:33                3451
ber01-VHDL13_DWLH_011233-2112011233-dsw--0-ia5     01-Dec-2021 12:33                3451
ber01-VHDL13_DWLH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3498
ber01-VHDL13_DWLH_011433-2112011433-dsw--0-ia5     01-Dec-2021 14:33                3507
ber01-VHDL13_DWLH_011533-2112011533-dsw--0-ia5     01-Dec-2021 15:33                3507
ber01-VHDL13_DWLH_011633-2112011633-dsw--0-ia5     01-Dec-2021 16:33                3507
ber01-VHDL13_DWLH_011733-2112011733-dsw--0-ia5     01-Dec-2021 17:33                3507
ber01-VHDL13_DWLH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                2755
ber01-VHDL13_DWLH_011833-2112011833-dsw--0-ia5     01-Dec-2021 18:33                2753
ber01-VHDL13_DWLH_012033-2112012033-dsw--0-ia5     01-Dec-2021 20:33                2764
ber01-VHDL13_DWLH_012133-2112012133-dsw--0-ia5     01-Dec-2021 21:33                2764
ber01-VHDL13_DWLH_020133-2112020133-dsw--0-ia5     02-Dec-2021 01:33                2678
ber01-VHDL13_DWLH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                2670
ber01-VHDL13_DWLH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2542
ber01-VHDL13_DWLH_020633-2112020633-dsw--0-ia5     02-Dec-2021 06:33                2551
ber01-VHDL13_DWLH_020733-2112020733-dsw--0-ia5     02-Dec-2021 07:33                3413
ber01-VHDL13_DWLH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3519
ber01-VHDL13_DWLH_020833-2112020833-dsw--0-ia5     02-Dec-2021 08:33                3528
ber01-VHDL13_DWLH_021033-2112021033-dsw--0-ia5     02-Dec-2021 10:33                3528
ber01-VHDL13_DWLH_021133-2112021133-dsw--0-ia5     02-Dec-2021 11:33                3456
ber01-VHDL13_DWLH_021233-2112021233-dsw--0-ia5     02-Dec-2021 12:33                3456
ber01-VHDL13_DWLH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3511
ber01-VHDL13_DWLH_021433-2112021433-dsw--0-ia5     02-Dec-2021 14:33                3520
ber01-VHDL13_DWLH_021533-2112021533-dsw--0-ia5     02-Dec-2021 15:33                3447
ber01-VHDL13_DWLH_021633-2112021633-dsw--0-ia5     02-Dec-2021 16:33                3447
ber01-VHDL13_DWLH_021733-2112021733-dsw--0-ia5     02-Dec-2021 17:33                3447
ber01-VHDL13_DWLH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3395
ber01-VHDL13_DWLH_021833-2112021833-dsw--0-ia5     02-Dec-2021 18:33                3404
ber01-VHDL13_DWLH_022033-2112022033-dsw--0-ia5     02-Dec-2021 20:33                3404
ber01-VHDL13_DWLH_022133-2112022133-dsw--0-ia5     02-Dec-2021 21:33                3404
ber01-VHDL13_DWLH_030133-2112030133-dsw--0-ia5     03-Dec-2021 01:33                3646
ber01-VHDL13_DWLH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3637
ber01-VHDL13_DWLH_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:59                3619
ber01-VHDL13_DWLH_030633-2112030633-dsw--0-ia5     03-Dec-2021 06:33                3628
ber01-VHDL13_DWLH_030733-2112030733-dsw--0-ia5     03-Dec-2021 07:33                4065
ber01-VHDL13_DWLI_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                2860
ber01-VHDL13_DWLI_010833-2112010833-dsw--0-ia5     01-Dec-2021 08:33                2866
ber01-VHDL13_DWLI_011033-2112011033-dsw--0-ia5     01-Dec-2021 10:33                2866
ber01-VHDL13_DWLI_011133-2112011133-dsw--0-ia5     01-Dec-2021 11:33                3001
ber01-VHDL13_DWLI_011233-2112011233-dsw--0-ia5     01-Dec-2021 12:33                3001
ber01-VHDL13_DWLI_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                2991
ber01-VHDL13_DWLI_011433-2112011433-dsw--0-ia5     01-Dec-2021 14:33                2997
ber01-VHDL13_DWLI_011533-2112011533-dsw--0-ia5     01-Dec-2021 15:33                2997
ber01-VHDL13_DWLI_011633-2112011633-dsw--0-ia5     01-Dec-2021 16:33                2997
ber01-VHDL13_DWLI_011733-2112011733-dsw--0-ia5     01-Dec-2021 17:33                2997
ber01-VHDL13_DWLI_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                2591
ber01-VHDL13_DWLI_011833-2112011833-dsw--0-ia5     01-Dec-2021 18:33                2601
ber01-VHDL13_DWLI_012033-2112012033-dsw--0-ia5     01-Dec-2021 20:33                2597
ber01-VHDL13_DWLI_012133-2112012133-dsw--0-ia5     01-Dec-2021 21:33                2597
ber01-VHDL13_DWLI_020133-2112020133-dsw--0-ia5     02-Dec-2021 01:33                2394
ber01-VHDL13_DWLI_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                2388
ber01-VHDL13_DWLI_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2428
ber01-VHDL13_DWLI_020633-2112020633-dsw--0-ia5     02-Dec-2021 06:33                2431
ber01-VHDL13_DWLI_020733-2112020733-dsw--0-ia5     02-Dec-2021 07:33                3077
ber01-VHDL13_DWLI_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3066
ber01-VHDL13_DWLI_020833-2112020833-dsw--0-ia5     02-Dec-2021 08:33                3072
ber01-VHDL13_DWLI_021033-2112021033-dsw--0-ia5     02-Dec-2021 10:33                3072
ber01-VHDL13_DWLI_021133-2112021133-dsw--0-ia5     02-Dec-2021 11:33                3016
ber01-VHDL13_DWLI_021233-2112021233-dsw--0-ia5     02-Dec-2021 12:33                3016
ber01-VHDL13_DWLI_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3044
ber01-VHDL13_DWLI_021433-2112021433-dsw--0-ia5     02-Dec-2021 14:33                3050
ber01-VHDL13_DWLI_021533-2112021533-dsw--0-ia5     02-Dec-2021 15:33                3007
ber01-VHDL13_DWLI_021633-2112021633-dsw--0-ia5     02-Dec-2021 16:33                3007
ber01-VHDL13_DWLI_021733-2112021733-dsw--0-ia5     02-Dec-2021 17:33                3199
ber01-VHDL13_DWLI_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3137
ber01-VHDL13_DWLI_021833-2112021833-dsw--0-ia5     02-Dec-2021 18:33                3143
ber01-VHDL13_DWLI_022033-2112022033-dsw--0-ia5     02-Dec-2021 20:33                3143
ber01-VHDL13_DWLI_022133-2112022133-dsw--0-ia5     02-Dec-2021 21:33                3143
ber01-VHDL13_DWLI_030133-2112030133-dsw--0-ia5     03-Dec-2021 01:33                3369
ber01-VHDL13_DWLI_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3363
ber01-VHDL13_DWLI_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:59                3315
ber01-VHDL13_DWLI_030633-2112030633-dsw--0-ia5     03-Dec-2021 06:33                3318
ber01-VHDL13_DWLI_030733-2112030733-dsw--0-ia5     03-Dec-2021 07:33                3318
ber01-VHDL13_DWMG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                4030
ber01-VHDL13_DWMG_011000-2112011000-dsw--0-ia5     01-Dec-2021 10:30                4038
ber01-VHDL13_DWMG_011100-2112011100-dsw--0-ia5     01-Dec-2021 11:30                4038
ber01-VHDL13_DWMG_011200-2112011200-dsw--0-ia5     01-Dec-2021 12:30                4038
ber01-VHDL13_DWMG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                4016
ber01-VHDL13_DWMG_011400-2112011400-dsw--0-ia5     01-Dec-2021 14:30                4016
ber01-VHDL13_DWMG_011500-2112011500-dsw--0-ia5     01-Dec-2021 15:30                3526
ber01-VHDL13_DWMG_011600-2112011600-dsw--0-ia5     01-Dec-2021 16:30                3754
ber01-VHDL13_DWMG_011700-2112011700-dsw--0-ia5     01-Dec-2021 17:30                3754
ber01-VHDL13_DWMG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3548
ber01-VHDL13_DWMG_012000-2112012000-dsw--0-ia5     01-Dec-2021 20:30                3548
ber01-VHDL13_DWMG_012100-2112012100-dsw--0-ia5     01-Dec-2021 21:30                3651
ber01-VHDL13_DWMG_012200-2112012200-dsw--0-ia5     01-Dec-2021 22:30                3651
ber01-VHDL13_DWMG_012300-2112012300-dsw--0-ia5     01-Dec-2021 23:30                3775
ber01-VHDL13_DWMG_020000-2112020000-dsw--0-ia5     02-Dec-2021 00:30                3775
ber01-VHDL13_DWMG_020100-2112020100-dsw--0-ia5     02-Dec-2021 01:30                3775
ber01-VHDL13_DWMG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3693
ber01-VHDL13_DWMG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3600
ber01-VHDL13_DWMG_020600-2112020600-dsw--0-ia5     02-Dec-2021 06:30                3600
ber01-VHDL13_DWMG_020700-2112020700-dsw--0-ia5     02-Dec-2021 07:30                3600
ber01-VHDL13_DWMG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3568
ber01-VHDL13_DWMG_021000-2112021000-dsw--0-ia5     02-Dec-2021 10:30                3558
ber01-VHDL13_DWMG_021100-2112021100-dsw--0-ia5     02-Dec-2021 11:30                3558
ber01-VHDL13_DWMG_021200-2112021200-dsw--0-ia5     02-Dec-2021 12:30                3558
ber01-VHDL13_DWMG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3531
ber01-VHDL13_DWMG_021400-2112021400-dsw--0-ia5     02-Dec-2021 14:30                3703
ber01-VHDL13_DWMG_021500-2112021500-dsw--0-ia5     02-Dec-2021 15:30                3703
ber01-VHDL13_DWMG_021600-2112021600-dsw--0-ia5     02-Dec-2021 16:30                3128
ber01-VHDL13_DWMG_021700-2112021700-dsw--0-ia5     02-Dec-2021 17:30                3128
ber01-VHDL13_DWMG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3068
ber01-VHDL13_DWMG_022000-2112022000-dsw--0-ia5     02-Dec-2021 20:30                3068
ber01-VHDL13_DWMG_022100-2112022100-dsw--0-ia5     02-Dec-2021 21:30                3068
ber01-VHDL13_DWMG_022200-2112022200-dsw--0-ia5     02-Dec-2021 22:30                3090
ber01-VHDL13_DWMG_022300-2112022300-dsw--0-ia5     02-Dec-2021 23:30                3213
ber01-VHDL13_DWMG_030000-2112030000-dsw--0-ia5     03-Dec-2021 00:30                3201
ber01-VHDL13_DWMG_030100-2112030100-dsw--0-ia5     03-Dec-2021 01:30                3259
ber01-VHDL13_DWMG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3237
ber01-VHDL13_DWMG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3428
ber01-VHDL13_DWMG_030600-2112030600-dsw--0-ia5     03-Dec-2021 06:30                3428
ber01-VHDL13_DWMG_030700-2112030700-dsw--0-ia5     03-Dec-2021 07:30                3449
ber01-VHDL13_DWMO_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3492
ber01-VHDL13_DWMO_011000-2112011000-dsw--0-ia5     01-Dec-2021 10:30                3734
ber01-VHDL13_DWMO_011100-2112011100-dsw--0-ia5     01-Dec-2021 11:30                3734
ber01-VHDL13_DWMO_011200-2112011200-dsw--0-ia5     01-Dec-2021 12:30                3734
ber01-VHDL13_DWMO_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3642
ber01-VHDL13_DWMO_011400-2112011400-dsw--0-ia5     01-Dec-2021 14:30                3642
ber01-VHDL13_DWMO_011500-2112011500-dsw--0-ia5     01-Dec-2021 15:30                3213
ber01-VHDL13_DWMO_011600-2112011600-dsw--0-ia5     01-Dec-2021 16:30                3213
ber01-VHDL13_DWMO_011700-2112011700-dsw--0-ia5     01-Dec-2021 17:30                3379
ber01-VHDL13_DWMO_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3229
ber01-VHDL13_DWMO_012000-2112012000-dsw--0-ia5     01-Dec-2021 20:30                3229
ber01-VHDL13_DWMO_012100-2112012100-dsw--0-ia5     01-Dec-2021 21:30                3341
ber01-VHDL13_DWMO_012200-2112012200-dsw--0-ia5     01-Dec-2021 22:30                3341
ber01-VHDL13_DWMO_012300-2112012300-dsw--0-ia5     01-Dec-2021 23:30                3487
ber01-VHDL13_DWMO_020000-2112020000-dsw--0-ia5     02-Dec-2021 00:30                3487
ber01-VHDL13_DWMO_020100-2112020100-dsw--0-ia5     02-Dec-2021 01:30                3487
ber01-VHDL13_DWMO_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3487
ber01-VHDL13_DWMO_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3403
ber01-VHDL13_DWMO_020600-2112020600-dsw--0-ia5     02-Dec-2021 06:30                3403
ber01-VHDL13_DWMO_020700-2112020700-dsw--0-ia5     02-Dec-2021 07:30                3403
ber01-VHDL13_DWMO_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3431
ber01-VHDL13_DWMO_021000-2112021000-dsw--0-ia5     02-Dec-2021 10:30                3348
ber01-VHDL13_DWMO_021100-2112021100-dsw--0-ia5     02-Dec-2021 11:30                3348
ber01-VHDL13_DWMO_021200-2112021200-dsw--0-ia5     02-Dec-2021 12:30                3348
ber01-VHDL13_DWMO_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3324
ber01-VHDL13_DWMO_021400-2112021400-dsw--0-ia5     02-Dec-2021 14:30                3410
ber01-VHDL13_DWMO_021500-2112021500-dsw--0-ia5     02-Dec-2021 15:30                3410
ber01-VHDL13_DWMO_021600-2112021600-dsw--0-ia5     02-Dec-2021 16:30                3017
ber01-VHDL13_DWMO_021700-2112021700-dsw--0-ia5     02-Dec-2021 17:30                3017
ber01-VHDL13_DWMO_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2935
ber01-VHDL13_DWMO_022000-2112022000-dsw--0-ia5     02-Dec-2021 20:30                2935
ber01-VHDL13_DWMO_022100-2112022100-dsw--0-ia5     02-Dec-2021 21:30                2935
ber01-VHDL13_DWMO_022200-2112022200-dsw--0-ia5     02-Dec-2021 22:30                3039
ber01-VHDL13_DWMO_022300-2112022300-dsw--0-ia5     02-Dec-2021 23:30                3223
ber01-VHDL13_DWMO_030000-2112030000-dsw--0-ia5     03-Dec-2021 00:30                3129
ber01-VHDL13_DWMO_030100-2112030100-dsw--0-ia5     03-Dec-2021 01:30                3230
ber01-VHDL13_DWMO_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3211
ber01-VHDL13_DWMO_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3227
ber01-VHDL13_DWMO_030600-2112030600-dsw--0-ia5     03-Dec-2021 06:30                3227
ber01-VHDL13_DWMO_030700-2112030700-dsw--0-ia5     03-Dec-2021 07:30                3191
ber01-VHDL13_DWMP_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3953
ber01-VHDL13_DWMP_011000-2112011000-dsw--0-ia5     01-Dec-2021 10:30                4251
ber01-VHDL13_DWMP_011100-2112011100-dsw--0-ia5     01-Dec-2021 11:30                4251
ber01-VHDL13_DWMP_011200-2112011200-dsw--0-ia5     01-Dec-2021 12:30                4251
ber01-VHDL13_DWMP_011400-2112011400-dsw--0-ia5     01-Dec-2021 14:30                4227
ber01-VHDL13_DWMP_011500-2112011500-dsw--0-ia5     01-Dec-2021 15:30                3706
ber01-VHDL13_DWMP_011600-2112011600-dsw--0-ia5     01-Dec-2021 16:30                3706
ber01-VHDL13_DWMP_011700-2112011700-dsw--0-ia5     01-Dec-2021 17:30                3850
ber01-VHDL13_DWMP_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3656
ber01-VHDL13_DWMP_012000-2112012000-dsw--0-ia5     01-Dec-2021 20:30                3656
ber01-VHDL13_DWMP_012100-2112012100-dsw--0-ia5     01-Dec-2021 21:30                3656
ber01-VHDL13_DWMP_012200-2112012200-dsw--0-ia5     01-Dec-2021 22:30                3725
ber01-VHDL13_DWMP_012300-2112012300-dsw--0-ia5     01-Dec-2021 23:30                3859
ber01-VHDL13_DWMP_020000-2112020000-dsw--0-ia5     02-Dec-2021 00:30                3859
ber01-VHDL13_DWMP_020100-2112020100-dsw--0-ia5     02-Dec-2021 01:30                3859
ber01-VHDL13_DWMP_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3859
ber01-VHDL13_DWMP_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3580
ber01-VHDL13_DWMP_020600-2112020600-dsw--0-ia5     02-Dec-2021 06:30                3580
ber01-VHDL13_DWMP_020700-2112020700-dsw--0-ia5     02-Dec-2021 07:30                3580
ber01-VHDL13_DWMP_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3580
ber01-VHDL13_DWMP_021000-2112021000-dsw--0-ia5     02-Dec-2021 10:30                3670
ber01-VHDL13_DWMP_021100-2112021100-dsw--0-ia5     02-Dec-2021 11:30                3670
ber01-VHDL13_DWMP_021200-2112021200-dsw--0-ia5     02-Dec-2021 12:30                3670
ber01-VHDL13_DWMP_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3641
ber01-VHDL13_DWMP_021400-2112021400-dsw--0-ia5     02-Dec-2021 14:30                3815
ber01-VHDL13_DWMP_021500-2112021500-dsw--0-ia5     02-Dec-2021 15:30                3815
ber01-VHDL13_DWMP_021600-2112021600-dsw--0-ia5     02-Dec-2021 16:30                3143
ber01-VHDL13_DWMP_021700-2112021700-dsw--0-ia5     02-Dec-2021 17:30                3143
ber01-VHDL13_DWMP_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3091
ber01-VHDL13_DWMP_022000-2112022000-dsw--0-ia5     02-Dec-2021 20:30                3091
ber01-VHDL13_DWMP_022100-2112022100-dsw--0-ia5     02-Dec-2021 21:30                3091
ber01-VHDL13_DWMP_022200-2112022200-dsw--0-ia5     02-Dec-2021 22:30                3029
ber01-VHDL13_DWMP_022300-2112022300-dsw--0-ia5     02-Dec-2021 23:30                3135
ber01-VHDL13_DWMP_030000-2112030000-dsw--0-ia5     03-Dec-2021 00:30                3112
ber01-VHDL13_DWMP_030100-2112030100-dsw--0-ia5     03-Dec-2021 01:30                3098
ber01-VHDL13_DWMP_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3076
ber01-VHDL13_DWMP_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3228
ber01-VHDL13_DWMP_030600-2112030600-dsw--0-ia5     03-Dec-2021 06:30                3228
ber01-VHDL13_DWMP_030700-2112030700-dsw--0-ia5     03-Dec-2021 07:30                3236
ber01-VHDL13_DWOG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:15                4727
ber01-VHDL13_DWOG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:00                4969
ber01-VHDL13_DWOG_011700-2112011700-dsw--0-ia5     01-Dec-2021 18:30                5880
ber01-VHDL13_DWOG_020100-2112020100-dsw--0-ia5     02-Dec-2021 02:45                5561
ber01-VHDL13_DWOG_020300-2112020300-dsw--0-ia5     02-Dec-2021 04:00                5561
ber01-VHDL13_DWOG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:15                4789
ber01-VHDL13_DWOG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:00                4564
ber01-VHDL13_DWOG_021700-2112021700-dsw--0-ia5     02-Dec-2021 18:30                5510
ber01-VHDL13_DWOG_030100-2112030100-dsw--0-ia5     03-Dec-2021 02:45                6052
ber01-VHDL13_DWOG_030300-2112030300-dsw--0-ia5     03-Dec-2021 04:00                6052
ber01-VHDL13_DWOH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:28                3991
ber01-VHDL13_DWOH_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 10:01                4149
ber01-VHDL13_DWOH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:28                4641
ber01-VHDL13_DWOH_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:28                4360
ber01-VHDL13_DWOH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:28                3629
ber01-VHDL13_DWOH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:28                3524
ber01-VHDL13_DWOH_020400-2112020400-dsw--0-ia5     02-Dec-2021 05:58                3983
ber01-VHDL13_DWOH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:28                4043
ber01-VHDL13_DWOH_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:53                3957
ber01-VHDL13_DWOH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:28                4413
ber01-VHDL13_DWOH_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:28                4175
ber01-VHDL13_DWOH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:28                3644
ber01-VHDL13_DWOH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:28                3882
ber01-VHDL13_DWOH_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:58                3843
ber01-VHDL13_DWOI_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:28                3614
ber01-VHDL13_DWOI_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 10:01                3797
ber01-VHDL13_DWOI_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:28                4240
ber01-VHDL13_DWOI_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:28                4237
ber01-VHDL13_DWOI_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:28                3553
ber01-VHDL13_DWOI_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:28                3552
ber01-VHDL13_DWOI_020400-2112020400-dsw--0-ia5     02-Dec-2021 05:58                3718
ber01-VHDL13_DWOI_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:28                3735
ber01-VHDL13_DWOI_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:51                3720
ber01-VHDL13_DWOI_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:28                4286
ber01-VHDL13_DWOI_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:28                3938
ber01-VHDL13_DWOI_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:28                3433
ber01-VHDL13_DWOI_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:28                3871
ber01-VHDL13_DWOI_030400-2112030400-dsw--0-ia5     03-Dec-2021 05:58                3922
ber01-VHDL13_DWON_010903-2112010903-dsw--0-ia5     01-Dec-2021 09:03                4292
ber01-VHDL13_DWON_010951-2112010951-dsw--0-ia5     01-Dec-2021 09:51                4292
ber01-VHDL13_DWON_011050-2112011050-dsw--0-ia5     01-Dec-2021 10:50                4376
ber01-VHDL13_DWON_011227-2112011227-dsw--0-ia5     01-Dec-2021 12:27                4428
ber01-VHDL13_DWON_011607-2112011607-dsw--0-ia5     01-Dec-2021 16:07                4097
ber01-VHDL13_DWON_011741-2112011741-dsw--0-ia5     01-Dec-2021 17:41                3866
ber01-VHDL13_DWON_011742-2112011742-dsw--0-ia5     01-Dec-2021 17:42                3866
ber01-VHDL13_DWON_020229-2112020229-dsw--0-ia5     02-Dec-2021 02:29                3608
ber01-VHDL13_DWON_020629-2112020629-dsw--0-ia5     02-Dec-2021 06:29                3672
ber01-VHDL13_DWON_020821-2112020821-dsw--0-ia5     02-Dec-2021 08:21                4226
ber01-VHDL13_DWON_021240-2112021240-dsw--0-ia5     02-Dec-2021 12:40                4175
ber01-VHDL13_DWON_021535-2112021535-dsw--0-ia5     02-Dec-2021 15:35                3560
ber01-VHDL13_DWON_021536-2112021536-dsw--0-ia5     02-Dec-2021 15:36                3560
ber01-VHDL13_DWON_021701-2112021701-dsw--0-ia5     02-Dec-2021 17:01                4122
ber01-VHDL13_DWON_021715-2112021715-dsw--0-ia5     02-Dec-2021 17:15                4122
ber01-VHDL13_DWON_021738-2112021738-dsw--0-ia5     02-Dec-2021 17:38                4122
ber01-VHDL13_DWON_022226-2112022226-dsw--0-ia5     02-Dec-2021 22:26                4122
ber01-VHDL13_DWON_030132-2112030132-dsw--0-ia5     03-Dec-2021 01:32                4547
ber01-VHDL13_DWON_030349-2112030349-dsw--0-ia5     03-Dec-2021 03:49                4547
ber01-VHDL13_DWON_030433-2112030433-dsw--0-ia5     03-Dec-2021 04:34                4283
ber01-VHDL13_DWON_030633-2112030633-dsw--0-ia5     03-Dec-2021 06:33                4498
ber01-VHDL13_DWPG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3379
ber01-VHDL13_DWPG_010830-2112010830-dsw--0-ia5     01-Dec-2021 08:30                3321
ber01-VHDL13_DWPG_011030-2112011030-dsw--0-ia5     01-Dec-2021 10:30                3378
ber01-VHDL13_DWPG_011130-2112011130-dsw--0-ia5     01-Dec-2021 11:30                3378
ber01-VHDL13_DWPG_011230-2112011230-dsw--0-ia5     01-Dec-2021 12:30                3307
ber01-VHDL13_DWPG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3360
ber01-VHDL13_DWPG_011430-2112011430-dsw--0-ia5     01-Dec-2021 14:30                3935
ber01-VHDL13_DWPG_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:30                4015
ber01-VHDL13_DWPG_011530-2112011530-dsw--0-ia5     01-Dec-2021 15:30                3933
ber01-VHDL13_DWPG_011730-2112011730-dsw--0-ia5     01-Dec-2021 17:30                4014
ber01-VHDL13_DWPG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3658
ber01-VHDL13_DWPG_011830-2112011830-dsw--0-ia5     01-Dec-2021 18:30                4014
ber01-VHDL13_DWPG_012030-2112012030-dsw--0-ia5     01-Dec-2021 20:30                3657
ber01-VHDL13_DWPG_012130-2112012130-dsw--0-ia5     01-Dec-2021 21:30                3657
ber01-VHDL13_DWPG_020130-2112020130-dsw--0-ia5     02-Dec-2021 01:30                3140
ber01-VHDL13_DWPG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3106
ber01-VHDL13_DWPG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3107
ber01-VHDL13_DWPG_020400_COR-2112020400-dsw--0-ia5 02-Dec-2021 06:07                3361
ber01-VHDL13_DWPG_020630-2112020630-dsw--0-ia5     02-Dec-2021 06:30                3355
ber01-VHDL13_DWPG_020730-2112020730-dsw--0-ia5     02-Dec-2021 07:30                3355
ber01-VHDL13_DWPG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3356
ber01-VHDL13_DWPG_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:36                3269
ber01-VHDL13_DWPG_020830-2112020830-dsw--0-ia5     02-Dec-2021 08:30                3355
ber01-VHDL13_DWPG_021030-2112021030-dsw--0-ia5     02-Dec-2021 10:30                3264
ber01-VHDL13_DWPG_021130-2112021130-dsw--0-ia5     02-Dec-2021 11:30                3264
ber01-VHDL13_DWPG_021230-2112021230-dsw--0-ia5     02-Dec-2021 12:30                3163
ber01-VHDL13_DWPG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3170
ber01-VHDL13_DWPG_021430-2112021430-dsw--0-ia5     02-Dec-2021 14:30                2970
ber01-VHDL13_DWPG_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:30                2944
ber01-VHDL13_DWPG_021530-2112021530-dsw--0-ia5     02-Dec-2021 15:30                3096
ber01-VHDL13_DWPG_021730-2112021730-dsw--0-ia5     02-Dec-2021 17:30                2943
ber01-VHDL13_DWPG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2801
ber01-VHDL13_DWPG_021830-2112021830-dsw--0-ia5     02-Dec-2021 18:30                2975
ber01-VHDL13_DWPG_022030-2112022030-dsw--0-ia5     02-Dec-2021 20:30                2800
ber01-VHDL13_DWPG_022130-2112022130-dsw--0-ia5     02-Dec-2021 21:30                2800
ber01-VHDL13_DWPG_030130-2112030130-dsw--0-ia5     03-Dec-2021 01:30                3516
ber01-VHDL13_DWPG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3517
ber01-VHDL13_DWPG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3277
ber01-VHDL13_DWPG_030630-2112030630-dsw--0-ia5     03-Dec-2021 06:30                3297
ber01-VHDL13_DWPG_030730-2112030730-dsw--0-ia5     03-Dec-2021 07:30                3297
ber01-VHDL13_DWPH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                4109
ber01-VHDL13_DWPH_010830-2112010830-dsw--0-ia5     01-Dec-2021 08:30                4089
ber01-VHDL13_DWPH_011030-2112011030-dsw--0-ia5     01-Dec-2021 10:30                4109
ber01-VHDL13_DWPH_011130-2112011130-dsw--0-ia5     01-Dec-2021 11:30                4109
ber01-VHDL13_DWPH_011230-2112011230-dsw--0-ia5     01-Dec-2021 12:30                4125
ber01-VHDL13_DWPH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                4368
ber01-VHDL13_DWPH_011430-2112011430-dsw--0-ia5     01-Dec-2021 14:30                4357
ber01-VHDL13_DWPH_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:30                4471
ber01-VHDL13_DWPH_011530-2112011530-dsw--0-ia5     01-Dec-2021 15:30                4355
ber01-VHDL13_DWPH_011730-2112011730-dsw--0-ia5     01-Dec-2021 17:30                4464
ber01-VHDL13_DWPH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3979
ber01-VHDL13_DWPH_011830-2112011830-dsw--0-ia5     01-Dec-2021 18:30                4464
ber01-VHDL13_DWPH_012030-2112012030-dsw--0-ia5     01-Dec-2021 20:30                3979
ber01-VHDL13_DWPH_012130-2112012130-dsw--0-ia5     01-Dec-2021 21:30                3979
ber01-VHDL13_DWPH_020130-2112020130-dsw--0-ia5     02-Dec-2021 01:30                3878
ber01-VHDL13_DWPH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3782
ber01-VHDL13_DWPH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3782
ber01-VHDL13_DWPH_020400_COR-2112020400-dsw--0-ia5 02-Dec-2021 06:08                3787
ber01-VHDL13_DWPH_020630-2112020630-dsw--0-ia5     02-Dec-2021 06:30                3783
ber01-VHDL13_DWPH_020730-2112020730-dsw--0-ia5     02-Dec-2021 07:30                3735
ber01-VHDL13_DWPH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3735
ber01-VHDL13_DWPH_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:36                3788
ber01-VHDL13_DWPH_020830-2112020830-dsw--0-ia5     02-Dec-2021 08:30                3735
ber01-VHDL13_DWPH_021030-2112021030-dsw--0-ia5     02-Dec-2021 10:30                3784
ber01-VHDL13_DWPH_021130-2112021130-dsw--0-ia5     02-Dec-2021 11:30                3784
ber01-VHDL13_DWPH_021230-2112021230-dsw--0-ia5     02-Dec-2021 12:30                3691
ber01-VHDL13_DWPH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3588
ber01-VHDL13_DWPH_021430-2112021430-dsw--0-ia5     02-Dec-2021 14:30                3551
ber01-VHDL13_DWPH_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:30                3911
ber01-VHDL13_DWPH_021530-2112021530-dsw--0-ia5     02-Dec-2021 15:30                3968
ber01-VHDL13_DWPH_021730-2112021730-dsw--0-ia5     02-Dec-2021 17:30                3930
ber01-VHDL13_DWPH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3634
ber01-VHDL13_DWPH_021830-2112021830-dsw--0-ia5     02-Dec-2021 18:30                4087
ber01-VHDL13_DWPH_022030-2112022030-dsw--0-ia5     02-Dec-2021 20:30                3634
ber01-VHDL13_DWPH_022130-2112022130-dsw--0-ia5     02-Dec-2021 21:30                3634
ber01-VHDL13_DWPH_030130-2112030130-dsw--0-ia5     03-Dec-2021 01:30                4119
ber01-VHDL13_DWPH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                4119
ber01-VHDL13_DWPH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                4147
ber01-VHDL13_DWPH_030630-2112030630-dsw--0-ia5     03-Dec-2021 06:30                4147
ber01-VHDL13_DWPH_030730-2112030730-dsw--0-ia5     03-Dec-2021 07:30                4147
ber01-VHDL13_DWSG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                4028
ber01-VHDL13_DWSG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                4396
ber01-VHDL13_DWSG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3890
ber01-VHDL13_DWSG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3545
ber01-VHDL13_DWSG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3827
ber01-VHDL13_DWSG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3596
ber01-VHDL13_DWSG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                3503
ber01-VHDL13_DWSG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3363
ber01-VHDL13_DWSG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3894
ber01-VHDL13_DWSG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                4015
ber01-VHDL13_DWSN_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                2271
ber01-VHDL13_DWSN_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:30                2618
ber01-VHDL13_DWSN_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                2417
ber01-VHDL13_DWSN_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                2617
ber01-VHDL13_DWSN_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2387
ber01-VHDL13_DWSN_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                2477
ber01-VHDL13_DWSN_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:30                2448
ber01-VHDL13_DWSN_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2527
ber01-VHDL13_DWSN_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                2746
ber01-VHDL13_DWSN_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2878
ber01-VHDL13_DWSO_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3923
ber01-VHDL13_DWSO_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:30                4274
ber01-VHDL13_DWSO_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3804
ber01-VHDL13_DWSO_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3721
ber01-VHDL13_DWSO_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3656
ber01-VHDL13_DWSO_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3421
ber01-VHDL13_DWSO_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:30                3303
ber01-VHDL13_DWSO_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3046
ber01-VHDL13_DWSO_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3319
ber01-VHDL13_DWSO_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3443
ber01-VHDL13_DWSP_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3226
ber01-VHDL13_DWSP_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:30                3352
ber01-VHDL13_DWSP_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                3064
ber01-VHDL13_DWSP_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3235
ber01-VHDL13_DWSP_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3210
ber01-VHDL13_DWSP_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3015
ber01-VHDL13_DWSP_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:30                2891
ber01-VHDL13_DWSP_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                2651
ber01-VHDL13_DWSP_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                2917
ber01-VHDL13_DWSP_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2975
ber01-VHDL17_DWOG_011200-2112011200-dsw--0-ia5     01-Dec-2021 12:21                3318
ber01-VHDL17_DWOG_021200-2112021200-dsw--0-ia5     02-Dec-2021 15:17                3887
ber01-VHDL17_DWOG_021200_COR-2112021200-dsw--0-ia5 02-Dec-2021 15:26                3891
ber01-VHDL20_DWHG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                3959
ber01-VHDL20_DWHG_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:45                3887
ber01-VHDL20_DWHG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3460
ber01-VHDL20_DWHG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3467
ber01-VHDL20_DWHG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3470
ber01-VHDL20_DWHG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3896
ber01-VHDL20_DWHG_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:45                3615
ber01-VHDL20_DWHG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3286
ber01-VHDL20_DWHG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3355
ber01-VHDL20_DWHG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3354
ber01-VHDL20_DWHH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4037
ber01-VHDL20_DWHH_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:45                3874
ber01-VHDL20_DWHH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3425
ber01-VHDL20_DWHH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3357
ber01-VHDL20_DWHH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3313
ber01-VHDL20_DWHH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3636
ber01-VHDL20_DWHH_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:45                3391
ber01-VHDL20_DWHH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3156
ber01-VHDL20_DWHH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3052
ber01-VHDL20_DWHH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2935
gts01-VHDL12_DWON_010815-2112010915-afsv--38-ia5   01-Dec-2021 09:15                3912
gts01-VHDL12_DWON_011330-2112011330-afsv--88-ia5   01-Dec-2021 13:30                4050
gts01-VHDL12_DWON_011815-2112011845-afsv--22-ia5   01-Dec-2021 18:45                3385
gts01-VHDL12_DWON_020115-2112020245-afsv--28-ia5   02-Dec-2021 02:45                3206
gts01-VHDL12_DWON_020530-2112020630-afsv--46-ia5   02-Dec-2021 06:30                3281
gts01-VHDL12_DWON_020815-2112020915-afsv--17-ia5   02-Dec-2021 09:15                3897
gts01-VHDL12_DWON_021330-2112021330-afsv--77-ia5   02-Dec-2021 13:30                3744
gts01-VHDL12_DWON_021815-2112021845-afsv--28-ia5   02-Dec-2021 18:45                3576
gts01-VHDL12_DWON_030115-2112030245-afsv--37-ia5   03-Dec-2021 02:45                3945
gts01-VHDL12_DWON_030530-2112030630-afsv--50-ia5   03-Dec-2021 06:30                3676
pid-VHDL12_DWHG_020200-2112020200-dsw--0-ia5       02-Dec-2021 03:30                2664
pid-VHDL12_DWHG_020400-2112020400-dsw--0-ia5       02-Dec-2021 06:00                2644
pid-VHDL12_DWHG_030200-2112030200-dsw--0-ia5       03-Dec-2021 03:30                2425
pid-VHDL12_DWHG_030400-2112030400-dsw--0-ia5       03-Dec-2021 06:00                2427
pid-VHDL12_DWHH_020200-2112020200-dsw--0-ia5       02-Dec-2021 03:30                2609
pid-VHDL12_DWHH_020400-2112020400-dsw--0-ia5       02-Dec-2021 06:00                2558
pid-VHDL12_DWHH_030200-2112030200-dsw--0-ia5       03-Dec-2021 03:30                2152
pid-VHDL12_DWHH_030400-2112030400-dsw--0-ia5       03-Dec-2021 06:00                2137
pid-VHDL12_DWMG_010800-2112010800-dsw--0-ia5       01-Dec-2021 09:30                3626
pid-VHDL12_DWMG_011300-2112011300-dsw--0-ia5       01-Dec-2021 13:30                3612
pid-VHDL12_DWMG_011800-2112011800-dsw--0-ia5       01-Dec-2021 19:30                3013
pid-VHDL12_DWMG_020200-2112020200-dsw--0-ia5       02-Dec-2021 03:30                3316
pid-VHDL12_DWMG_020400-2112020400-dsw--0-ia5       02-Dec-2021 06:00                3223
pid-VHDL12_DWMG_020800-2112020800-dsw--0-ia5       02-Dec-2021 09:30                3191
pid-VHDL12_DWMG_021300-2112021300-dsw--0-ia5       02-Dec-2021 13:30                3154
pid-VHDL12_DWMG_021800-2112021800-dsw--0-ia5       02-Dec-2021 19:30                2691
pid-VHDL12_DWMG_030200-2112030200-dsw--0-ia5       03-Dec-2021 03:30                2852
pid-VHDL12_DWMG_030400-2112030400-dsw--0-ia5       03-Dec-2021 06:00                3043
pid-VHDL12_DWOG_020100-2112020100-dsw--0-ia5       02-Dec-2021 02:45                5068
pid-VHDL12_DWOG_020300-2112020300-dsw--0-ia5       02-Dec-2021 04:00                5068
pid-VHDL12_DWOG_030100-2112030100-dsw--0-ia5       03-Dec-2021 02:45                5330
pid-VHDL12_DWOG_030300-2112030300-dsw--0-ia5       03-Dec-2021 04:00                5330
pid-VHDL12_DWSG_020200-2112020200-dsw--0-ia5       02-Dec-2021 03:30                3041
pid-VHDL12_DWSG_030200-2112030200-dsw--0-ia5       03-Dec-2021 03:30                3470
swis2-VHDL20_DWEG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                5126
swis2-VHDL20_DWEG_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 09:59                5129
swis2-VHDL20_DWEG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                5064
swis2-VHDL20_DWEG_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:45                4901
swis2-VHDL20_DWEG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4173
swis2-VHDL20_DWEG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3931
swis2-VHDL20_DWEG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:15                4545
swis2-VHDL20_DWEG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4976
swis2-VHDL20_DWEG_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:50                5011
swis2-VHDL20_DWEG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                4981
swis2-VHDL20_DWEG_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:45                4743
swis2-VHDL20_DWEG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                4095
swis2-VHDL20_DWEG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                4293
swis2-VHDL20_DWEG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:15                4477
swis2-VHDL20_DWEH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                5073
swis2-VHDL20_DWEH_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 09:59                5076
swis2-VHDL20_DWEH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                5160
swis2-VHDL20_DWEH_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:45                4965
swis2-VHDL20_DWEH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4230
swis2-VHDL20_DWEH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3991
swis2-VHDL20_DWEH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:15                4382
swis2-VHDL20_DWEH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4844
swis2-VHDL20_DWEH_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:50                4783
swis2-VHDL20_DWEH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                4926
swis2-VHDL20_DWEH_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:45                4659
swis2-VHDL20_DWEH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3981
swis2-VHDL20_DWEH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                4393
swis2-VHDL20_DWEH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:15                4590
swis2-VHDL20_DWEI_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4795
swis2-VHDL20_DWEI_010800_COR-2112010800-dsw--0-ia5 01-Dec-2021 10:00                4797
swis2-VHDL20_DWEI_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                4777
swis2-VHDL20_DWEI_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:45                4817
swis2-VHDL20_DWEI_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4133
swis2-VHDL20_DWEI_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3935
swis2-VHDL20_DWEI_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:15                4304
swis2-VHDL20_DWEI_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4740
swis2-VHDL20_DWEI_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:49                4706
swis2-VHDL20_DWEI_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                4886
swis2-VHDL20_DWEI_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:45                4535
swis2-VHDL20_DWEI_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3908
swis2-VHDL20_DWEI_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                4297
swis2-VHDL20_DWEI_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:15                4523
swis2-VHDL20_DWHG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                3959
swis2-VHDL20_DWHG_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:45                3887
swis2-VHDL20_DWHG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3460
swis2-VHDL20_DWHG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3467
swis2-VHDL20_DWHG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3470
swis2-VHDL20_DWHG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3896
swis2-VHDL20_DWHG_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:45                3615
swis2-VHDL20_DWHG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3286
swis2-VHDL20_DWHG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3355
swis2-VHDL20_DWHG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3354
swis2-VHDL20_DWHH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4037
swis2-VHDL20_DWHH_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:45                3874
swis2-VHDL20_DWHH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3425
swis2-VHDL20_DWHH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3357
swis2-VHDL20_DWHH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3313
swis2-VHDL20_DWHH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3636
swis2-VHDL20_DWHH_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:45                3391
swis2-VHDL20_DWHH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3156
swis2-VHDL20_DWHH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3052
swis2-VHDL20_DWHH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                2935
swis2-VHDL20_DWLG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                3620
swis2-VHDL20_DWLG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                3723
swis2-VHDL20_DWLG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3284
swis2-VHDL20_DWLG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3319
swis2-VHDL20_DWLG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3021
swis2-VHDL20_DWLG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3590
swis2-VHDL20_DWLG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                3339
swis2-VHDL20_DWLG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3501
swis2-VHDL20_DWLG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3714
swis2-VHDL20_DWLG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3767
swis2-VHDL20_DWLH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                3924
swis2-VHDL20_DWLH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                3903
swis2-VHDL20_DWLH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3160
swis2-VHDL20_DWLH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3078
swis2-VHDL20_DWLH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2982
swis2-VHDL20_DWLH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4195
swis2-VHDL20_DWLH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                3951
swis2-VHDL20_DWLH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3835
swis2-VHDL20_DWLH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                4080
swis2-VHDL20_DWLH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                4131
swis2-VHDL20_DWLI_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                3577
swis2-VHDL20_DWLI_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                3522
swis2-VHDL20_DWLI_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3122
swis2-VHDL20_DWLI_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                2922
swis2-VHDL20_DWLI_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                2860
swis2-VHDL20_DWLI_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                3734
swis2-VHDL20_DWLI_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                3479
swis2-VHDL20_DWLI_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3572
swis2-VHDL20_DWLI_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3801
swis2-VHDL20_DWLI_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3818
swis2-VHDL20_DWMG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4677
swis2-VHDL20_DWMG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                4500
swis2-VHDL20_DWMG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4032
swis2-VHDL20_DWMG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                4204
swis2-VHDL20_DWMG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                4081
swis2-VHDL20_DWMG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4334
swis2-VHDL20_DWMG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                4035
swis2-VHDL20_DWMG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3572
swis2-VHDL20_DWMG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3614
swis2-VHDL20_DWMG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3996
swis2-VHDL20_DWMO_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4080
swis2-VHDL20_DWMO_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                4099
swis2-VHDL20_DWMO_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                3686
swis2-VHDL20_DWMO_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                3989
swis2-VHDL20_DWMO_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3854
swis2-VHDL20_DWMO_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4013
swis2-VHDL20_DWMO_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                3775
swis2-VHDL20_DWMO_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3386
swis2-VHDL20_DWMO_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3625
swis2-VHDL20_DWMO_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3839
swis2-VHDL20_DWMP_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4973
swis2-VHDL20_DWMP_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:45                4708
swis2-VHDL20_DWMP_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4117
swis2-VHDL20_DWMP_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                4341
swis2-VHDL20_DWMP_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                4052
swis2-VHDL20_DWMP_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4386
swis2-VHDL20_DWMP_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:45                4116
swis2-VHDL20_DWMP_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3580
swis2-VHDL20_DWMP_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                3490
swis2-VHDL20_DWMP_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3785
swis2-VHDL20_DWPG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                3997
swis2-VHDL20_DWPG_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                3971
swis2-VHDL20_DWPG_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:30                4631
swis2-VHDL20_DWPG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                4275
swis2-VHDL20_DWPG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                3480
swis2-VHDL20_DWPG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                3461
swis2-VHDL20_DWPG_020400_COR-2112020400-dsw--0-ia5 02-Dec-2021 06:08                3715
swis2-VHDL20_DWPG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                3831
swis2-VHDL20_DWPG_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:36                3933
swis2-VHDL20_DWPG_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                4006
swis2-VHDL20_DWPG_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:30                3768
swis2-VHDL20_DWPG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                3632
swis2-VHDL20_DWPG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                3998
swis2-VHDL20_DWPG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                3622
swis2-VHDL20_DWPH_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:30                4897
swis2-VHDL20_DWPH_011300-2112011300-dsw--0-ia5     01-Dec-2021 13:30                5156
swis2-VHDL20_DWPH_011500-2112011500-dsw--0-ia5     01-Dec-2021 16:30                5259
swis2-VHDL20_DWPH_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:30                4767
swis2-VHDL20_DWPH_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:30                4241
swis2-VHDL20_DWPH_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:00                4253
swis2-VHDL20_DWPH_020400_COR-2112020400-dsw--0-ia5 02-Dec-2021 06:09                4258
swis2-VHDL20_DWPH_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:30                4325
swis2-VHDL20_DWPH_020800_COR-2112020800-dsw--0-ia5 02-Dec-2021 09:39                4571
swis2-VHDL20_DWPH_021300-2112021300-dsw--0-ia5     02-Dec-2021 13:30                4378
swis2-VHDL20_DWPH_021500-2112021500-dsw--0-ia5     02-Dec-2021 16:30                4719
swis2-VHDL20_DWPH_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:30                4447
swis2-VHDL20_DWPH_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:30                4566
swis2-VHDL20_DWPH_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:00                4637
swis2-VHDL20_DWSG_010800-2112010800-dsw--0-ia5     01-Dec-2021 09:45                4742
swis2-VHDL20_DWSG_011300-2112011300-dsw--0-ia5     01-Dec-2021 14:45                4844
swis2-VHDL20_DWSG_011800-2112011800-dsw--0-ia5     01-Dec-2021 19:45                4338
swis2-VHDL20_DWSG_020200-2112020200-dsw--0-ia5     02-Dec-2021 03:45                4008
swis2-VHDL20_DWSG_020400-2112020400-dsw--0-ia5     02-Dec-2021 06:15                4283
swis2-VHDL20_DWSG_020800-2112020800-dsw--0-ia5     02-Dec-2021 09:45                4300
swis2-VHDL20_DWSG_021300-2112021300-dsw--0-ia5     02-Dec-2021 14:45                3984
swis2-VHDL20_DWSG_021800-2112021800-dsw--0-ia5     02-Dec-2021 19:45                3825
swis2-VHDL20_DWSG_030200-2112030200-dsw--0-ia5     03-Dec-2021 03:45                4412
swis2-VHDL20_DWSG_030400-2112030400-dsw--0-ia5     03-Dec-2021 06:15                4638
wst04-VHDL20_DWEG_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:47              261587
wst04-VHDL20_DWEG_010800_COR-2112010800-omedes-..> 01-Dec-2021 10:01              261588
wst04-VHDL20_DWEG_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              260749
wst04-VHDL20_DWEG_011500-2112011500-omedes--0.pdf  01-Dec-2021 16:45              260529
wst04-VHDL20_DWEG_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              259670
wst04-VHDL20_DWEG_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:46              259771
wst04-VHDL20_DWEG_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:15              258937
wst04-VHDL20_DWEG_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              257616
wst04-VHDL20_DWEG_020800_COR-2112020800-omedes-..> 02-Dec-2021 09:51              257978
wst04-VHDL20_DWEG_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              257627
wst04-VHDL20_DWEG_021500-2112021500-omedes--0.pdf  02-Dec-2021 16:45              257258
wst04-VHDL20_DWEG_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              256874
wst04-VHDL20_DWEG_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:46              257549
wst04-VHDL20_DWEG_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:15              257379
wst04-VHDL20_DWEH_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:46              260761
wst04-VHDL20_DWEH_010800_COR-2112010800-omedes-..> 01-Dec-2021 10:01              260772
wst04-VHDL20_DWEH_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              260362
wst04-VHDL20_DWEH_011500-2112011500-omedes--0.pdf  01-Dec-2021 16:45              260098
wst04-VHDL20_DWEH_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              259177
wst04-VHDL20_DWEH_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:46              259729
wst04-VHDL20_DWEH_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:15              258597
wst04-VHDL20_DWEH_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              256057
wst04-VHDL20_DWEH_020800_COR-2112020800-omedes-..> 02-Dec-2021 09:50              255797
wst04-VHDL20_DWEH_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              255862
wst04-VHDL20_DWEH_021500-2112021500-omedes--0.pdf  02-Dec-2021 16:45              255609
wst04-VHDL20_DWEH_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              255016
wst04-VHDL20_DWEH_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:46              256447
wst04-VHDL20_DWEH_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:15              256175
wst04-VHDL20_DWEI_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:47              357527
wst04-VHDL20_DWEI_010800_COR-2112010800-omedes-..> 01-Dec-2021 10:01              357517
wst04-VHDL20_DWEI_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              356842
wst04-VHDL20_DWEI_011500-2112011500-omedes--0.pdf  01-Dec-2021 16:45              356184
wst04-VHDL20_DWEI_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              355374
wst04-VHDL20_DWEI_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:46              354949
wst04-VHDL20_DWEI_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:15              354512
wst04-VHDL20_DWEI_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              356384
wst04-VHDL20_DWEI_020800_COR-2112020800-omedes-..> 02-Dec-2021 09:52              356687
wst04-VHDL20_DWEI_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              356280
wst04-VHDL20_DWEI_021500-2112021500-omedes--0.pdf  02-Dec-2021 16:45              355205
wst04-VHDL20_DWEI_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              354543
wst04-VHDL20_DWEI_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:46              355858
wst04-VHDL20_DWEI_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:15              356093
wst04-VHDL20_DWHG_010800-2112010800-oflxs888--0..> 01-Dec-2021 09:48              346236
wst04-VHDL20_DWHG_011300-2112011300-oflxs888--0..> 01-Dec-2021 14:45              345364
wst04-VHDL20_DWHG_011800-2112011800-oflxs888--0..> 01-Dec-2021 19:46              344998
wst04-VHDL20_DWHG_020200-2112020200-oflxs888--0..> 02-Dec-2021 03:47              344281
wst04-VHDL20_DWHG_020400-2112020400-oflxs888--0..> 02-Dec-2021 06:00              344237
wst04-VHDL20_DWHG_020800-2112020800-oflxs888--0..> 02-Dec-2021 09:48              339346
wst04-VHDL20_DWHG_021300-2112021300-oflxs888--0..> 02-Dec-2021 14:45              338291
wst04-VHDL20_DWHG_021800-2112021800-oflxs888--0..> 02-Dec-2021 19:46              337844
wst04-VHDL20_DWHG_030200-2112030200-oflxs888--0..> 03-Dec-2021 03:47              337748
wst04-VHDL20_DWHG_030400-2112030400-oflxs888--0..> 03-Dec-2021 06:00              337696
wst04-VHDL20_DWHH_010800-2112010800-oflxs888--0..> 01-Dec-2021 09:48              347803
wst04-VHDL20_DWHH_011300-2112011300-oflxs888--0..> 01-Dec-2021 14:45              347234
wst04-VHDL20_DWHH_011800-2112011800-oflxs888--0..> 01-Dec-2021 19:46              346478
wst04-VHDL20_DWHH_020200-2112020200-oflxs888--0..> 02-Dec-2021 03:47              346350
wst04-VHDL20_DWHH_020400-2112020400-oflxs888--0..> 02-Dec-2021 06:01              346383
wst04-VHDL20_DWHH_020800-2112020800-oflxs888--0..> 02-Dec-2021 09:48              333641
wst04-VHDL20_DWHH_021300-2112021300-oflxs888--0..> 02-Dec-2021 14:45              333100
wst04-VHDL20_DWHH_021800-2112021800-oflxs888--0..> 02-Dec-2021 19:46              332973
wst04-VHDL20_DWHH_030200-2112030200-oflxs888--0..> 03-Dec-2021 03:47              332751
wst04-VHDL20_DWHH_030400-2112030400-oflxs888--0..> 03-Dec-2021 06:00              332671
wst04-VHDL20_DWLG_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:41              338898
wst04-VHDL20_DWLG_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:40              339531
wst04-VHDL20_DWLG_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:40              338886
wst04-VHDL20_DWLG_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:41              339450
wst04-VHDL20_DWLG_020400-2112020400-omedes--0.pdf  02-Dec-2021 05:59              338875
wst04-VHDL20_DWLG_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:42              335305
wst04-VHDL20_DWLG_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:40              334906
wst04-VHDL20_DWLG_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:40              334763
wst04-VHDL20_DWLG_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:41              336039
wst04-VHDL20_DWLG_030400-2112030400-omedes--0.pdf  03-Dec-2021 05:59              335624
wst04-VHDL20_DWLH_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:41              333518
wst04-VHDL20_DWLH_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:40              334048
wst04-VHDL20_DWLH_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:40              332601
wst04-VHDL20_DWLH_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:41              333198
wst04-VHDL20_DWLH_020400-2112020400-omedes--0.pdf  02-Dec-2021 05:59              332773
wst04-VHDL20_DWLH_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:41              334974
wst04-VHDL20_DWLH_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:40              334625
wst04-VHDL20_DWLH_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:40              334267
wst04-VHDL20_DWLH_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:41              334932
wst04-VHDL20_DWLH_030400-2112030400-omedes--0.pdf  03-Dec-2021 05:59              334540
wst04-VHDL20_DWLI_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:42              334921
wst04-VHDL20_DWLI_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:40              335256
wst04-VHDL20_DWLI_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:40              334951
wst04-VHDL20_DWLI_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:42              333940
wst04-VHDL20_DWLI_020400-2112020400-omedes--0.pdf  02-Dec-2021 05:59              334410
wst04-VHDL20_DWLI_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:42              335596
wst04-VHDL20_DWLI_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:40              335250
wst04-VHDL20_DWLI_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:40              335068
wst04-VHDL20_DWLI_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:41              335907
wst04-VHDL20_DWLI_030400-2112030400-omedes--0.pdf  03-Dec-2021 05:59              335553
wst04-VHDL20_DWMG_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:47              540867
wst04-VHDL20_DWMG_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              539972
wst04-VHDL20_DWMG_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              538838
wst04-VHDL20_DWMG_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:46              539217
wst04-VHDL20_DWMG_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:00              538931
wst04-VHDL20_DWMG_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              553199
wst04-VHDL20_DWMG_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              552808
wst04-VHDL20_DWMG_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              551545
wst04-VHDL20_DWMG_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:47              552277
wst04-VHDL20_DWMG_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:00              552396
wst04-VHDL20_DWMO_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:47              437853
wst04-VHDL20_DWMO_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              437732
wst04-VHDL20_DWMO_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              436923
wst04-VHDL20_DWMO_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:46              437356
wst04-VHDL20_DWMO_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:00              437354
wst04-VHDL20_DWMO_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              441681
wst04-VHDL20_DWMO_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              441566
wst04-VHDL20_DWMO_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              440686
wst04-VHDL20_DWMO_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:46              440974
wst04-VHDL20_DWMO_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:00              441689
wst04-VHDL20_DWMP_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:47              563356
wst04-VHDL20_DWMP_011300-2112011300-omedes--0.pdf  01-Dec-2021 13:45              562982
wst04-VHDL20_DWMP_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              561527
wst04-VHDL20_DWMP_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:47              560770
wst04-VHDL20_DWMP_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:00              561646
wst04-VHDL20_DWMP_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:48              576610
wst04-VHDL20_DWMP_021300-2112021300-omedes--0.pdf  02-Dec-2021 13:45              575646
wst04-VHDL20_DWMP_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              575173
wst04-VHDL20_DWMP_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:47              573846
wst04-VHDL20_DWMP_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:00              575033
wst04-VHDL20_DWPG_010800-2112010800-oflxs892--0..> 01-Dec-2021 09:30              388831
wst04-VHDL20_DWPG_011300-2112011300-oflxs892--0..> 01-Dec-2021 13:30              343907
wst04-VHDL20_DWPG_011500-2112011500-oflxs892--0..> 01-Dec-2021 16:30              343903
wst04-VHDL20_DWPG_011800-2112011800-oflxs892--0..> 01-Dec-2021 19:30              343635
wst04-VHDL20_DWPG_020200-2112020200-oflxs892--0..> 02-Dec-2021 03:30              343028
wst04-VHDL20_DWPG_020400-2112020400-oflxs892--0..> 02-Dec-2021 06:00              342971
wst04-VHDL20_DWPG_020400_COR-2112020400-oflxs89..> 02-Dec-2021 06:08              343051
wst04-VHDL20_DWPG_020800-2112020800-oflxs892--0..> 02-Dec-2021 09:30              387933
wst04-VHDL20_DWPG_020800_COR-2112020800-oflxs89..> 02-Dec-2021 09:38              388313
wst04-VHDL20_DWPG_021300-2112021300-oflxs892--0..> 02-Dec-2021 13:30              343094
wst04-VHDL20_DWPG_021500-2112021500-oflxs892--0..> 02-Dec-2021 16:30              342963
wst04-VHDL20_DWPG_021800-2112021800-oflxs892--0..> 02-Dec-2021 19:30              342446
wst04-VHDL20_DWPG_030200-2112030200-oflxs892--0..> 03-Dec-2021 03:30              342744
wst04-VHDL20_DWPG_030400-2112030400-oflxs892--0..> 03-Dec-2021 06:00              342511
wst04-VHDL20_DWPH_010800-2112010800-oflxs892--0..> 01-Dec-2021 09:30              303304
wst04-VHDL20_DWPH_011300-2112011300-oflxs892--0..> 01-Dec-2021 13:30              258598
wst04-VHDL20_DWPH_011500-2112011500-oflxs892--0..> 01-Dec-2021 16:30              258621
wst04-VHDL20_DWPH_011800-2112011800-oflxs892--0..> 01-Dec-2021 19:30              302869
wst04-VHDL20_DWPH_020200-2112020200-oflxs892--0..> 02-Dec-2021 03:30              258411
wst04-VHDL20_DWPH_020400-2112020400-oflxs892--0..> 02-Dec-2021 06:00              258533
wst04-VHDL20_DWPH_020400_COR-2112020400-oflxs89..> 02-Dec-2021 06:09              257864
wst04-VHDL20_DWPH_020800-2112020800-oflxs892--0..> 02-Dec-2021 09:30              295050
wst04-VHDL20_DWPH_020800_COR-2112020800-oflxs89..> 02-Dec-2021 09:40              295249
wst04-VHDL20_DWPH_021300-2112021300-oflxs892--0..> 02-Dec-2021 13:30              250241
wst04-VHDL20_DWPH_021500-2112021500-oflxs892--0..> 02-Dec-2021 16:30              250610
wst04-VHDL20_DWPH_021800-2112021800-oflxs892--0..> 02-Dec-2021 19:30              293620
wst04-VHDL20_DWPH_030200-2112030200-oflxs892--0..> 03-Dec-2021 03:30              248965
wst04-VHDL20_DWPH_030400-2112030400-oflxs892--0..> 03-Dec-2021 06:00              249124
wst04-VHDL20_DWSG_010800-2112010800-omedes--0.pdf  01-Dec-2021 09:46              368920
wst04-VHDL20_DWSG_011300-2112011300-omedes--0.pdf  01-Dec-2021 14:45              369099
wst04-VHDL20_DWSG_011800-2112011800-omedes--0.pdf  01-Dec-2021 19:45              368210
wst04-VHDL20_DWSG_020200-2112020200-omedes--0.pdf  02-Dec-2021 03:47              367553
wst04-VHDL20_DWSG_020400-2112020400-omedes--0.pdf  02-Dec-2021 06:15              367972
wst04-VHDL20_DWSG_020800-2112020800-omedes--0.pdf  02-Dec-2021 09:47              357091
wst04-VHDL20_DWSG_021300-2112021300-omedes--0.pdf  02-Dec-2021 14:45              356593
wst04-VHDL20_DWSG_021800-2112021800-omedes--0.pdf  02-Dec-2021 19:45              356418
wst04-VHDL20_DWSG_030200-2112030200-omedes--0.pdf  03-Dec-2021 03:46              358858
wst04-VHDL20_DWSG_030400-2112030400-omedes--0.pdf  03-Dec-2021 06:15              358037