Index of /weather/text_forecasts/txt/


../
FPDL13_DWMZ_240600                                 24-May-2022 11:14                4993
FPDL13_DWMZ_250600                                 25-May-2022 08:40                3502
SXDL31_DWAV_240800                                 24-May-2022 07:51                9883
SXDL31_DWAV_241800                                 24-May-2022 16:41                6872
SXDL31_DWAV_250800                                 25-May-2022 07:47               12484
SXDL31_DWAV_251800                                 25-May-2022 16:39               10366
SXDL31_DWAV_LATEST                                 25-May-2022 16:39               10366
SXDL33_DWAV_240000                                 24-May-2022 09:43                8011
SXDL33_DWAV_250000                                 25-May-2022 09:37                7093
SXDL33_DWAV_LATEST                                 25-May-2022 09:37                7093
ber01-FWDL39_DWMS_241230-2205241230-dsw--0-ia5     24-May-2022 12:07                1233
ber01-FWDL39_DWMS_251230-2205251230-dsw--0-ia5     25-May-2022 12:06                1204
ber01-VHDL13_DWEH_231800-2205231800-dsw--0-ia5     23-May-2022 18:28                3169
ber01-VHDL13_DWEH_240200-2205240200-dsw--0-ia5     24-May-2022 02:28                3049
ber01-VHDL13_DWEH_240400-2205240400-dsw--0-ia5     24-May-2022 04:58                3526
ber01-VHDL13_DWEH_240800-2205240800-dsw--0-ia5     24-May-2022 08:28                3496
ber01-VHDL13_DWEH_241300-2205241300-dsw--0-ia5     24-May-2022 12:28                3386
ber01-VHDL13_DWEH_241500-2205241500-dsw--0-ia5     24-May-2022 15:28                3286
ber01-VHDL13_DWEH_241800-2205241800-dsw--0-ia5     24-May-2022 18:28                2715
ber01-VHDL13_DWEH_250200-2205250200-dsw--0-ia5     25-May-2022 02:28                2600
ber01-VHDL13_DWEH_250400-2205250400-dsw--0-ia5     25-May-2022 04:58                3279
ber01-VHDL13_DWEH_250800-2205250800-dsw--0-ia5     25-May-2022 08:28                3330
ber01-VHDL13_DWEH_251300-2205251300-dsw--0-ia5     25-May-2022 12:28                3329
ber01-VHDL13_DWEH_251500-2205251500-dsw--0-ia5     25-May-2022 15:28                3119
ber01-VHDL13_DWHG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                3082
ber01-VHDL13_DWHG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2560
ber01-VHDL13_DWHG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2567
ber01-VHDL13_DWHG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2585
ber01-VHDL13_DWHG_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2719
ber01-VHDL13_DWHG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2358
ber01-VHDL13_DWHG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2475
ber01-VHDL13_DWHG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2422
ber01-VHDL13_DWHG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2445
ber01-VHDL13_DWHG_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2708
ber01-VHDL13_DWHH_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2879
ber01-VHDL13_DWHH_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2484
ber01-VHDL13_DWHH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2491
ber01-VHDL13_DWHH_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2481
ber01-VHDL13_DWHH_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2610
ber01-VHDL13_DWHH_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2317
ber01-VHDL13_DWHH_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2416
ber01-VHDL13_DWHH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2374
ber01-VHDL13_DWHH_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2378
ber01-VHDL13_DWHH_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2726
ber01-VHDL13_DWLG_231733-2205231733-dsw--0-ia5     23-May-2022 17:33                1874
ber01-VHDL13_DWLG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                1841
ber01-VHDL13_DWLG_231933-2205231933-dsw--0-ia5     23-May-2022 19:33                1847
ber01-VHDL13_DWLG_232033-2205232033-dsw--0-ia5     23-May-2022 20:33                1847
ber01-VHDL13_DWLG_240033-2205240033-dsw--0-ia5     24-May-2022 00:33                1934
ber01-VHDL13_DWLG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                1928
ber01-VHDL13_DWLG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                1984
ber01-VHDL13_DWLG_240533-2205240533-dsw--0-ia5     24-May-2022 05:33                1990
ber01-VHDL13_DWLG_240633-2205240633-dsw--0-ia5     24-May-2022 06:33                1990
ber01-VHDL13_DWLG_240733-2205240733-dsw--0-ia5     24-May-2022 07:33                1972
ber01-VHDL13_DWLG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                1963
ber01-VHDL13_DWLG_240933-2205240933-dsw--0-ia5     24-May-2022 09:33                1972
ber01-VHDL13_DWLG_241033-2205241033-dsw--0-ia5     24-May-2022 10:33                2000
ber01-VHDL13_DWLG_241133-2205241133-dsw--0-ia5     24-May-2022 11:33                1999
ber01-VHDL13_DWLG_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2008
ber01-VHDL13_DWLG_241333-2205241333-dsw--0-ia5     24-May-2022 13:33                2021
ber01-VHDL13_DWLG_241433-2205241433-dsw--0-ia5     24-May-2022 14:33                2021
ber01-VHDL13_DWLG_241533-2205241533-dsw--0-ia5     24-May-2022 15:33                2021
ber01-VHDL13_DWLG_241633-2205241633-dsw--0-ia5     24-May-2022 16:33                2021
ber01-VHDL13_DWLG_241733-2205241733-dsw--0-ia5     24-May-2022 17:33                2021
ber01-VHDL13_DWLG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                1719
ber01-VHDL13_DWLG_241800_COR-2205241800-dsw--0-ia5 24-May-2022 18:42                1891
ber01-VHDL13_DWLG_241933-2205241933-dsw--0-ia5     24-May-2022 19:33                1964
ber01-VHDL13_DWLG_242033-2205242033-dsw--0-ia5     24-May-2022 20:33                1964
ber01-VHDL13_DWLG_250033-2205250033-dsw--0-ia5     25-May-2022 00:33                2520
ber01-VHDL13_DWLG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2514
ber01-VHDL13_DWLG_250400-2205250400-dsw--0-ia5     25-May-2022 04:59                2392
ber01-VHDL13_DWLG_250533-2205250533-dsw--0-ia5     25-May-2022 05:33                2550
ber01-VHDL13_DWLG_250633-2205250633-dsw--0-ia5     25-May-2022 06:33                2751
ber01-VHDL13_DWLG_250733-2205250733-dsw--0-ia5     25-May-2022 07:33                2763
ber01-VHDL13_DWLG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2785
ber01-VHDL13_DWLG_250933-2205250933-dsw--0-ia5     25-May-2022 09:33                2794
ber01-VHDL13_DWLG_251033-2205251033-dsw--0-ia5     25-May-2022 10:33                2838
ber01-VHDL13_DWLG_251133-2205251133-dsw--0-ia5     25-May-2022 11:33                2838
ber01-VHDL13_DWLG_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2832
ber01-VHDL13_DWLG_251333-2205251333-dsw--0-ia5     25-May-2022 13:33                2841
ber01-VHDL13_DWLG_251433-2205251433-dsw--0-ia5     25-May-2022 14:33                2841
ber01-VHDL13_DWLG_251533-2205251533-dsw--0-ia5     25-May-2022 15:33                2841
ber01-VHDL13_DWLG_251633-2205251633-dsw--0-ia5     25-May-2022 16:33                2841
ber01-VHDL13_DWLH_231733-2205231733-dsw--0-ia5     23-May-2022 17:33                2077
ber01-VHDL13_DWLH_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2041
ber01-VHDL13_DWLH_231933-2205231933-dsw--0-ia5     23-May-2022 19:33                2050
ber01-VHDL13_DWLH_232033-2205232033-dsw--0-ia5     23-May-2022 20:33                2050
ber01-VHDL13_DWLH_240033-2205240033-dsw--0-ia5     24-May-2022 00:33                2205
ber01-VHDL13_DWLH_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2196
ber01-VHDL13_DWLH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2295
ber01-VHDL13_DWLH_240533-2205240533-dsw--0-ia5     24-May-2022 05:33                2304
ber01-VHDL13_DWLH_240633-2205240633-dsw--0-ia5     24-May-2022 06:33                2304
ber01-VHDL13_DWLH_240733-2205240733-dsw--0-ia5     24-May-2022 07:33                2286
ber01-VHDL13_DWLH_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2271
ber01-VHDL13_DWLH_240933-2205240933-dsw--0-ia5     24-May-2022 09:33                2280
ber01-VHDL13_DWLH_241033-2205241033-dsw--0-ia5     24-May-2022 10:33                2242
ber01-VHDL13_DWLH_241133-2205241133-dsw--0-ia5     24-May-2022 11:33                2242
ber01-VHDL13_DWLH_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2090
ber01-VHDL13_DWLH_241333-2205241333-dsw--0-ia5     24-May-2022 13:33                2106
ber01-VHDL13_DWLH_241433-2205241433-dsw--0-ia5     24-May-2022 14:33                2106
ber01-VHDL13_DWLH_241533-2205241533-dsw--0-ia5     24-May-2022 15:33                2106
ber01-VHDL13_DWLH_241633-2205241633-dsw--0-ia5     24-May-2022 16:33                2106
ber01-VHDL13_DWLH_241733-2205241733-dsw--0-ia5     24-May-2022 17:33                2106
ber01-VHDL13_DWLH_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                1909
ber01-VHDL13_DWLH_241933-2205241933-dsw--0-ia5     24-May-2022 19:33                1918
ber01-VHDL13_DWLH_242033-2205242033-dsw--0-ia5     24-May-2022 20:33                1918
ber01-VHDL13_DWLH_250033-2205250033-dsw--0-ia5     25-May-2022 00:33                2447
ber01-VHDL13_DWLH_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2438
ber01-VHDL13_DWLH_250400-2205250400-dsw--0-ia5     25-May-2022 04:59                2528
ber01-VHDL13_DWLH_250533-2205250533-dsw--0-ia5     25-May-2022 05:33                2558
ber01-VHDL13_DWLH_250633-2205250633-dsw--0-ia5     25-May-2022 06:33                2558
ber01-VHDL13_DWLH_250733-2205250733-dsw--0-ia5     25-May-2022 07:33                2572
ber01-VHDL13_DWLH_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2563
ber01-VHDL13_DWLH_250933-2205250933-dsw--0-ia5     25-May-2022 09:33                2559
ber01-VHDL13_DWLH_251033-2205251033-dsw--0-ia5     25-May-2022 10:33                2570
ber01-VHDL13_DWLH_251133-2205251133-dsw--0-ia5     25-May-2022 11:33                2535
ber01-VHDL13_DWLH_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2526
ber01-VHDL13_DWLH_251333-2205251333-dsw--0-ia5     25-May-2022 13:33                2513
ber01-VHDL13_DWLH_251433-2205251433-dsw--0-ia5     25-May-2022 14:33                2513
ber01-VHDL13_DWLH_251533-2205251533-dsw--0-ia5     25-May-2022 15:33                2513
ber01-VHDL13_DWLH_251633-2205251633-dsw--0-ia5     25-May-2022 16:33                2513
ber01-VHDL13_DWLI_231733-2205231733-dsw--0-ia5     23-May-2022 17:33                1950
ber01-VHDL13_DWLI_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                1917
ber01-VHDL13_DWLI_231933-2205231933-dsw--0-ia5     23-May-2022 19:33                1923
ber01-VHDL13_DWLI_232033-2205232033-dsw--0-ia5     23-May-2022 20:33                1923
ber01-VHDL13_DWLI_240033-2205240033-dsw--0-ia5     24-May-2022 00:33                1989
ber01-VHDL13_DWLI_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                1983
ber01-VHDL13_DWLI_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2062
ber01-VHDL13_DWLI_240533-2205240533-dsw--0-ia5     24-May-2022 05:33                2065
ber01-VHDL13_DWLI_240633-2205240633-dsw--0-ia5     24-May-2022 06:33                2065
ber01-VHDL13_DWLI_240733-2205240733-dsw--0-ia5     24-May-2022 07:33                1994
ber01-VHDL13_DWLI_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                1988
ber01-VHDL13_DWLI_240933-2205240933-dsw--0-ia5     24-May-2022 09:33                1994
ber01-VHDL13_DWLI_241033-2205241033-dsw--0-ia5     24-May-2022 10:33                1977
ber01-VHDL13_DWLI_241133-2205241133-dsw--0-ia5     24-May-2022 11:33                1977
ber01-VHDL13_DWLI_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2011
ber01-VHDL13_DWLI_241333-2205241333-dsw--0-ia5     24-May-2022 13:33                2024
ber01-VHDL13_DWLI_241433-2205241433-dsw--0-ia5     24-May-2022 14:33                2024
ber01-VHDL13_DWLI_241533-2205241533-dsw--0-ia5     24-May-2022 15:33                2024
ber01-VHDL13_DWLI_241633-2205241633-dsw--0-ia5     24-May-2022 16:33                2024
ber01-VHDL13_DWLI_241733-2205241733-dsw--0-ia5     24-May-2022 17:33                2024
ber01-VHDL13_DWLI_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                1756
ber01-VHDL13_DWLI_241933-2205241933-dsw--0-ia5     24-May-2022 19:33                1762
ber01-VHDL13_DWLI_242033-2205242033-dsw--0-ia5     24-May-2022 20:33                1762
ber01-VHDL13_DWLI_250033-2205250033-dsw--0-ia5     25-May-2022 00:33                2175
ber01-VHDL13_DWLI_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2169
ber01-VHDL13_DWLI_250400-2205250400-dsw--0-ia5     25-May-2022 04:59                2117
ber01-VHDL13_DWLI_250533-2205250533-dsw--0-ia5     25-May-2022 05:33                2278
ber01-VHDL13_DWLI_250633-2205250633-dsw--0-ia5     25-May-2022 06:33                2333
ber01-VHDL13_DWLI_250733-2205250733-dsw--0-ia5     25-May-2022 07:33                2335
ber01-VHDL13_DWLI_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2280
ber01-VHDL13_DWLI_250933-2205250933-dsw--0-ia5     25-May-2022 09:33                2273
ber01-VHDL13_DWLI_251033-2205251033-dsw--0-ia5     25-May-2022 10:33                2317
ber01-VHDL13_DWLI_251133-2205251133-dsw--0-ia5     25-May-2022 11:33                2317
ber01-VHDL13_DWLI_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2311
ber01-VHDL13_DWLI_251333-2205251333-dsw--0-ia5     25-May-2022 13:33                2299
ber01-VHDL13_DWLI_251433-2205251433-dsw--0-ia5     25-May-2022 14:33                2299
ber01-VHDL13_DWLI_251533-2205251533-dsw--0-ia5     25-May-2022 15:33                2299
ber01-VHDL13_DWLI_251633-2205251633-dsw--0-ia5     25-May-2022 16:33                2299
ber01-VHDL13_DWMG_231700-2205231700-dsw--0-ia5     23-May-2022 17:30                2918
ber01-VHDL13_DWMG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2699
ber01-VHDL13_DWMG_231900-2205231900-dsw--0-ia5     23-May-2022 19:30                2739
ber01-VHDL13_DWMG_232000-2205232000-dsw--0-ia5     23-May-2022 20:30                2739
ber01-VHDL13_DWMG_232100-2205232100-dsw--0-ia5     23-May-2022 21:30                2739
ber01-VHDL13_DWMG_232200-2205232200-dsw--0-ia5     23-May-2022 22:30                2612
ber01-VHDL13_DWMG_232300-2205232300-dsw--0-ia5     23-May-2022 23:30                2612
ber01-VHDL13_DWMG_240000-2205240000-dsw--0-ia5     24-May-2022 00:30                2612
ber01-VHDL13_DWMG_240100-2205240100-dsw--0-ia5     24-May-2022 01:30                2612
ber01-VHDL13_DWMG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2623
ber01-VHDL13_DWMG_240300-2205240300-dsw--0-ia5     24-May-2022 03:30                2623
ber01-VHDL13_DWMG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2739
ber01-VHDL13_DWMG_240500-2205240500-dsw--0-ia5     24-May-2022 05:30                2739
ber01-VHDL13_DWMG_240600-2205240600-dsw--0-ia5     24-May-2022 06:30                2739
ber01-VHDL13_DWMG_240700-2205240700-dsw--0-ia5     24-May-2022 07:30                2739
ber01-VHDL13_DWMG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                3042
ber01-VHDL13_DWMG_240900-2205240900-dsw--0-ia5     24-May-2022 09:30                3042
ber01-VHDL13_DWMG_241000-2205241000-dsw--0-ia5     24-May-2022 10:30                3042
ber01-VHDL13_DWMG_241100-2205241100-dsw--0-ia5     24-May-2022 11:30                3042
ber01-VHDL13_DWMG_241200-2205241200-dsw--0-ia5     24-May-2022 12:30                3050
ber01-VHDL13_DWMG_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                3050
ber01-VHDL13_DWMG_241400-2205241400-dsw--0-ia5     24-May-2022 14:30                2986
ber01-VHDL13_DWMG_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2986
ber01-VHDL13_DWMG_241600-2205241600-dsw--0-ia5     24-May-2022 16:30                2986
ber01-VHDL13_DWMG_241700-2205241700-dsw--0-ia5     24-May-2022 17:30                2529
ber01-VHDL13_DWMG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2529
ber01-VHDL13_DWMG_241900-2205241900-dsw--0-ia5     24-May-2022 19:30                2522
ber01-VHDL13_DWMG_242000-2205242000-dsw--0-ia5     24-May-2022 20:30                2522
ber01-VHDL13_DWMG_242100-2205242100-dsw--0-ia5     24-May-2022 21:30                2522
ber01-VHDL13_DWMG_242200-2205242200-dsw--0-ia5     24-May-2022 22:30                2572
ber01-VHDL13_DWMG_242300-2205242300-dsw--0-ia5     24-May-2022 23:30                2572
ber01-VHDL13_DWMG_250000-2205250000-dsw--0-ia5     25-May-2022 00:30                2572
ber01-VHDL13_DWMG_250100-2205250100-dsw--0-ia5     25-May-2022 01:30                2572
ber01-VHDL13_DWMG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2572
ber01-VHDL13_DWMG_250300-2205250300-dsw--0-ia5     25-May-2022 03:30                2572
ber01-VHDL13_DWMG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2533
ber01-VHDL13_DWMG_250500-2205250500-dsw--0-ia5     25-May-2022 05:30                2533
ber01-VHDL13_DWMG_250600-2205250600-dsw--0-ia5     25-May-2022 06:30                2533
ber01-VHDL13_DWMG_250700-2205250700-dsw--0-ia5     25-May-2022 07:30                2533
ber01-VHDL13_DWMG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2560
ber01-VHDL13_DWMG_250900-2205250900-dsw--0-ia5     25-May-2022 09:30                2560
ber01-VHDL13_DWMG_251000-2205251000-dsw--0-ia5     25-May-2022 10:30                2560
ber01-VHDL13_DWMG_251100-2205251100-dsw--0-ia5     25-May-2022 11:30                2560
ber01-VHDL13_DWMG_251200-2205251200-dsw--0-ia5     25-May-2022 12:30                2447
ber01-VHDL13_DWMG_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                2447
ber01-VHDL13_DWMG_251400-2205251400-dsw--0-ia5     25-May-2022 14:30                2530
ber01-VHDL13_DWMG_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                2530
ber01-VHDL13_DWMG_251600-2205251600-dsw--0-ia5     25-May-2022 16:30                2530
ber01-VHDL13_DWMO_231700-2205231700-dsw--0-ia5     23-May-2022 17:30                2828
ber01-VHDL13_DWMO_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2547
ber01-VHDL13_DWMO_231900-2205231900-dsw--0-ia5     23-May-2022 19:30                2666
ber01-VHDL13_DWMO_232000-2205232000-dsw--0-ia5     23-May-2022 20:30                2666
ber01-VHDL13_DWMO_232100-2205232100-dsw--0-ia5     23-May-2022 21:30                2666
ber01-VHDL13_DWMO_232200-2205232200-dsw--0-ia5     23-May-2022 22:30                2478
ber01-VHDL13_DWMO_232300-2205232300-dsw--0-ia5     23-May-2022 23:30                2478
ber01-VHDL13_DWMO_240000-2205240000-dsw--0-ia5     24-May-2022 00:30                2478
ber01-VHDL13_DWMO_240100-2205240100-dsw--0-ia5     24-May-2022 01:30                2478
ber01-VHDL13_DWMO_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2487
ber01-VHDL13_DWMO_240300-2205240300-dsw--0-ia5     24-May-2022 03:30                2487
ber01-VHDL13_DWMO_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2583
ber01-VHDL13_DWMO_240500-2205240500-dsw--0-ia5     24-May-2022 05:30                2583
ber01-VHDL13_DWMO_240600-2205240600-dsw--0-ia5     24-May-2022 06:30                2583
ber01-VHDL13_DWMO_240700-2205240700-dsw--0-ia5     24-May-2022 07:30                2583
ber01-VHDL13_DWMO_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2611
ber01-VHDL13_DWMO_240900-2205240900-dsw--0-ia5     24-May-2022 09:30                2887
ber01-VHDL13_DWMO_241000-2205241000-dsw--0-ia5     24-May-2022 10:30                2887
ber01-VHDL13_DWMO_241100-2205241100-dsw--0-ia5     24-May-2022 11:30                2887
ber01-VHDL13_DWMO_241200-2205241200-dsw--0-ia5     24-May-2022 12:30                2933
ber01-VHDL13_DWMO_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                2933
ber01-VHDL13_DWMO_241400-2205241400-dsw--0-ia5     24-May-2022 14:30                2726
ber01-VHDL13_DWMO_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2726
ber01-VHDL13_DWMO_241600-2205241600-dsw--0-ia5     24-May-2022 16:30                2726
ber01-VHDL13_DWMO_241700-2205241700-dsw--0-ia5     24-May-2022 17:30                2121
ber01-VHDL13_DWMO_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2121
ber01-VHDL13_DWMO_241900-2205241900-dsw--0-ia5     24-May-2022 19:30                2097
ber01-VHDL13_DWMO_242000-2205242000-dsw--0-ia5     24-May-2022 20:30                2097
ber01-VHDL13_DWMO_242100-2205242100-dsw--0-ia5     24-May-2022 21:30                2097
ber01-VHDL13_DWMO_242200-2205242200-dsw--0-ia5     24-May-2022 22:30                2224
ber01-VHDL13_DWMO_242300-2205242300-dsw--0-ia5     24-May-2022 23:30                2224
ber01-VHDL13_DWMO_250000-2205250000-dsw--0-ia5     25-May-2022 00:30                2224
ber01-VHDL13_DWMO_250100-2205250100-dsw--0-ia5     25-May-2022 01:30                2224
ber01-VHDL13_DWMO_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2224
ber01-VHDL13_DWMO_250300-2205250300-dsw--0-ia5     25-May-2022 03:30                2224
ber01-VHDL13_DWMO_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2224
ber01-VHDL13_DWMO_250500-2205250500-dsw--0-ia5     25-May-2022 05:30                2224
ber01-VHDL13_DWMO_250600-2205250600-dsw--0-ia5     25-May-2022 06:30                2224
ber01-VHDL13_DWMO_250700-2205250700-dsw--0-ia5     25-May-2022 07:30                2224
ber01-VHDL13_DWMO_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2252
ber01-VHDL13_DWMO_250900-2205250900-dsw--0-ia5     25-May-2022 09:30                2329
ber01-VHDL13_DWMO_251000-2205251000-dsw--0-ia5     25-May-2022 10:30                2329
ber01-VHDL13_DWMO_251100-2205251100-dsw--0-ia5     25-May-2022 11:30                2329
ber01-VHDL13_DWMO_251200-2205251200-dsw--0-ia5     25-May-2022 12:30                2097
ber01-VHDL13_DWMO_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                2097
ber01-VHDL13_DWMO_251400-2205251400-dsw--0-ia5     25-May-2022 14:30                2059
ber01-VHDL13_DWMO_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                2059
ber01-VHDL13_DWMO_251600-2205251600-dsw--0-ia5     25-May-2022 16:30                2059
ber01-VHDL13_DWMP_231700-2205231700-dsw--0-ia5     23-May-2022 17:30                2775
ber01-VHDL13_DWMP_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2556
ber01-VHDL13_DWMP_231900-2205231900-dsw--0-ia5     23-May-2022 19:30                2564
ber01-VHDL13_DWMP_232000-2205232000-dsw--0-ia5     23-May-2022 20:30                2564
ber01-VHDL13_DWMP_232100-2205232100-dsw--0-ia5     23-May-2022 21:30                2564
ber01-VHDL13_DWMP_232200-2205232200-dsw--0-ia5     23-May-2022 22:30                2306
ber01-VHDL13_DWMP_232300-2205232300-dsw--0-ia5     23-May-2022 23:30                2306
ber01-VHDL13_DWMP_240000-2205240000-dsw--0-ia5     24-May-2022 00:30                2306
ber01-VHDL13_DWMP_240100-2205240100-dsw--0-ia5     24-May-2022 01:30                2306
ber01-VHDL13_DWMP_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2306
ber01-VHDL13_DWMP_240300-2205240300-dsw--0-ia5     24-May-2022 03:30                2306
ber01-VHDL13_DWMP_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2340
ber01-VHDL13_DWMP_240500-2205240500-dsw--0-ia5     24-May-2022 05:30                2340
ber01-VHDL13_DWMP_240600-2205240600-dsw--0-ia5     24-May-2022 06:30                2340
ber01-VHDL13_DWMP_240700-2205240700-dsw--0-ia5     24-May-2022 07:30                2340
ber01-VHDL13_DWMP_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2853
ber01-VHDL13_DWMP_240900-2205240900-dsw--0-ia5     24-May-2022 09:30                2853
ber01-VHDL13_DWMP_241000-2205241000-dsw--0-ia5     24-May-2022 10:30                2853
ber01-VHDL13_DWMP_241100-2205241100-dsw--0-ia5     24-May-2022 11:30                2853
ber01-VHDL13_DWMP_241200-2205241200-dsw--0-ia5     24-May-2022 12:30                2874
ber01-VHDL13_DWMP_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                2874
ber01-VHDL13_DWMP_241400-2205241400-dsw--0-ia5     24-May-2022 14:30                2878
ber01-VHDL13_DWMP_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2878
ber01-VHDL13_DWMP_241600-2205241600-dsw--0-ia5     24-May-2022 16:30                2878
ber01-VHDL13_DWMP_241700-2205241700-dsw--0-ia5     24-May-2022 17:30                2383
ber01-VHDL13_DWMP_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2383
ber01-VHDL13_DWMP_241900-2205241900-dsw--0-ia5     24-May-2022 19:30                2366
ber01-VHDL13_DWMP_242000-2205242000-dsw--0-ia5     24-May-2022 20:30                2366
ber01-VHDL13_DWMP_242100-2205242100-dsw--0-ia5     24-May-2022 21:30                2366
ber01-VHDL13_DWMP_242200-2205242200-dsw--0-ia5     24-May-2022 22:30                2538
ber01-VHDL13_DWMP_242300-2205242300-dsw--0-ia5     24-May-2022 23:30                2538
ber01-VHDL13_DWMP_250000-2205250000-dsw--0-ia5     25-May-2022 00:30                2538
ber01-VHDL13_DWMP_250100-2205250100-dsw--0-ia5     25-May-2022 01:30                2538
ber01-VHDL13_DWMP_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2538
ber01-VHDL13_DWMP_250300-2205250300-dsw--0-ia5     25-May-2022 03:30                2538
ber01-VHDL13_DWMP_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2556
ber01-VHDL13_DWMP_250500-2205250500-dsw--0-ia5     25-May-2022 05:30                2556
ber01-VHDL13_DWMP_250600-2205250600-dsw--0-ia5     25-May-2022 06:30                2556
ber01-VHDL13_DWMP_250700-2205250700-dsw--0-ia5     25-May-2022 07:30                2556
ber01-VHDL13_DWMP_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2556
ber01-VHDL13_DWMP_250900-2205250900-dsw--0-ia5     25-May-2022 09:30                2491
ber01-VHDL13_DWMP_251000-2205251000-dsw--0-ia5     25-May-2022 10:30                2491
ber01-VHDL13_DWMP_251100-2205251100-dsw--0-ia5     25-May-2022 11:30                2491
ber01-VHDL13_DWMP_251200-2205251200-dsw--0-ia5     25-May-2022 12:30                2353
ber01-VHDL13_DWMP_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                2353
ber01-VHDL13_DWMP_251400-2205251400-dsw--0-ia5     25-May-2022 14:30                2218
ber01-VHDL13_DWMP_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                2218
ber01-VHDL13_DWMP_251600-2205251600-dsw--0-ia5     25-May-2022 16:30                2218
ber01-VHDL13_DWOG_231700-2205231700-dsw--0-ia5     23-May-2022 17:30                5375
ber01-VHDL13_DWOG_240100-2205240100-dsw--0-ia5     24-May-2022 01:45                5435
ber01-VHDL13_DWOG_240300-2205240300-dsw--0-ia5     24-May-2022 03:00                5435
ber01-VHDL13_DWOG_240800-2205240800-dsw--0-ia5     24-May-2022 08:15                4212
ber01-VHDL13_DWOG_241300-2205241300-dsw--0-ia5     24-May-2022 12:00                4599
ber01-VHDL13_DWOG_241700-2205241700-dsw--0-ia5     24-May-2022 17:30                4511
ber01-VHDL13_DWOG_250100-2205250100-dsw--0-ia5     25-May-2022 01:45                4185
ber01-VHDL13_DWOG_250300-2205250300-dsw--0-ia5     25-May-2022 03:00                4192
ber01-VHDL13_DWOG_250800-2205250800-dsw--0-ia5     25-May-2022 08:15                4299
ber01-VHDL13_DWOG_251300-2205251300-dsw--0-ia5     25-May-2022 12:00                4299
ber01-VHDL13_DWOH_231800-2205231800-dsw--0-ia5     23-May-2022 18:28                3013
ber01-VHDL13_DWOH_240200-2205240200-dsw--0-ia5     24-May-2022 02:28                2940
ber01-VHDL13_DWOH_240400-2205240400-dsw--0-ia5     24-May-2022 04:58                3383
ber01-VHDL13_DWOH_240800-2205240800-dsw--0-ia5     24-May-2022 08:28                3531
ber01-VHDL13_DWOH_241300-2205241300-dsw--0-ia5     24-May-2022 12:28                3361
ber01-VHDL13_DWOH_241500-2205241500-dsw--0-ia5     24-May-2022 15:28                2916
ber01-VHDL13_DWOH_241800-2205241800-dsw--0-ia5     24-May-2022 18:28                2587
ber01-VHDL13_DWOH_250200-2205250200-dsw--0-ia5     25-May-2022 02:28                2613
ber01-VHDL13_DWOH_250400-2205250400-dsw--0-ia5     25-May-2022 04:58                3188
ber01-VHDL13_DWOH_250800-2205250800-dsw--0-ia5     25-May-2022 08:28                3173
ber01-VHDL13_DWOH_251300-2205251300-dsw--0-ia5     25-May-2022 12:28                3196
ber01-VHDL13_DWOH_251500-2205251500-dsw--0-ia5     25-May-2022 15:28                3140
ber01-VHDL13_DWOI_231800-2205231800-dsw--0-ia5     23-May-2022 18:28                2906
ber01-VHDL13_DWOI_240200-2205240200-dsw--0-ia5     24-May-2022 02:28                2679
ber01-VHDL13_DWOI_240400-2205240400-dsw--0-ia5     24-May-2022 04:58                3424
ber01-VHDL13_DWOI_240800-2205240800-dsw--0-ia5     24-May-2022 08:28                3239
ber01-VHDL13_DWOI_241300-2205241300-dsw--0-ia5     24-May-2022 12:28                3144
ber01-VHDL13_DWOI_241500-2205241500-dsw--0-ia5     24-May-2022 15:28                2738
ber01-VHDL13_DWOI_241800-2205241800-dsw--0-ia5     24-May-2022 18:28                2374
ber01-VHDL13_DWOI_250200-2205250200-dsw--0-ia5     25-May-2022 02:28                2522
ber01-VHDL13_DWOI_250400-2205250400-dsw--0-ia5     25-May-2022 04:58                3025
ber01-VHDL13_DWOI_250800-2205250800-dsw--0-ia5     25-May-2022 08:28                3089
ber01-VHDL13_DWOI_251300-2205251300-dsw--0-ia5     25-May-2022 12:28                3102
ber01-VHDL13_DWOI_251500-2205251500-dsw--0-ia5     25-May-2022 15:28                3059
ber01-VHDL13_DWPG_231730-2205231730-dsw--0-ia5     23-May-2022 17:30                2509
ber01-VHDL13_DWPG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2300
ber01-VHDL13_DWPG_231930-2205231930-dsw--0-ia5     23-May-2022 19:30                2299
ber01-VHDL13_DWPG_232030-2205232030-dsw--0-ia5     23-May-2022 20:30                2299
ber01-VHDL13_DWPG_240030-2205240030-dsw--0-ia5     24-May-2022 00:30                2315
ber01-VHDL13_DWPG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2188
ber01-VHDL13_DWPG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2560
ber01-VHDL13_DWPG_240530-2205240530-dsw--0-ia5     24-May-2022 05:30                2551
ber01-VHDL13_DWPG_240630-2205240630-dsw--0-ia5     24-May-2022 06:30                2579
ber01-VHDL13_DWPG_240730-2205240730-dsw--0-ia5     24-May-2022 07:30                2439
ber01-VHDL13_DWPG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2622
ber01-VHDL13_DWPG_240930-2205240930-dsw--0-ia5     24-May-2022 09:30                2621
ber01-VHDL13_DWPG_241030-2205241030-dsw--0-ia5     24-May-2022 10:30                2621
ber01-VHDL13_DWPG_241130-2205241130-dsw--0-ia5     24-May-2022 11:30                2617
ber01-VHDL13_DWPG_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2624
ber01-VHDL13_DWPG_241330-2205241330-dsw--0-ia5     24-May-2022 13:30                2623
ber01-VHDL13_DWPG_241430-2205241430-dsw--0-ia5     24-May-2022 14:30                2623
ber01-VHDL13_DWPG_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2509
ber01-VHDL13_DWPG_241630-2205241630-dsw--0-ia5     24-May-2022 16:30                2508
ber01-VHDL13_DWPG_241730-2205241730-dsw--0-ia5     24-May-2022 17:30                2508
ber01-VHDL13_DWPG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2275
ber01-VHDL13_DWPG_241930-2205241930-dsw--0-ia5     24-May-2022 19:30                2274
ber01-VHDL13_DWPG_242030-2205242030-dsw--0-ia5     24-May-2022 20:30                2274
ber01-VHDL13_DWPG_250030-2205250030-dsw--0-ia5     25-May-2022 00:30                2421
ber01-VHDL13_DWPG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2416
ber01-VHDL13_DWPG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2453
ber01-VHDL13_DWPG_250530-2205250530-dsw--0-ia5     25-May-2022 05:30                2451
ber01-VHDL13_DWPG_250630-2205250630-dsw--0-ia5     25-May-2022 06:30                2451
ber01-VHDL13_DWPG_250730-2205250730-dsw--0-ia5     25-May-2022 07:30                2451
ber01-VHDL13_DWPG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2513
ber01-VHDL13_DWPG_250930-2205250930-dsw--0-ia5     25-May-2022 09:30                2512
ber01-VHDL13_DWPG_251030-2205251030-dsw--0-ia5     25-May-2022 10:30                2512
ber01-VHDL13_DWPG_251130-2205251130-dsw--0-ia5     25-May-2022 11:30                2498
ber01-VHDL13_DWPG_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2615
ber01-VHDL13_DWPG_251330-2205251330-dsw--0-ia5     25-May-2022 13:30                2614
ber01-VHDL13_DWPG_251430-2205251430-dsw--0-ia5     25-May-2022 14:30                2614
ber01-VHDL13_DWPG_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                2809
ber01-VHDL13_DWPG_251630-2205251630-dsw--0-ia5     25-May-2022 16:30                2755
ber01-VHDL13_DWPH_231730-2205231730-dsw--0-ia5     23-May-2022 17:30                2849
ber01-VHDL13_DWPH_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2593
ber01-VHDL13_DWPH_231930-2205231930-dsw--0-ia5     23-May-2022 19:30                2593
ber01-VHDL13_DWPH_232030-2205232030-dsw--0-ia5     23-May-2022 20:30                2593
ber01-VHDL13_DWPH_240030-2205240030-dsw--0-ia5     24-May-2022 00:30                2486
ber01-VHDL13_DWPH_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2413
ber01-VHDL13_DWPH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2988
ber01-VHDL13_DWPH_240530-2205240530-dsw--0-ia5     24-May-2022 05:30                2988
ber01-VHDL13_DWPH_240630-2205240630-dsw--0-ia5     24-May-2022 06:30                3019
ber01-VHDL13_DWPH_240730-2205240730-dsw--0-ia5     24-May-2022 07:30                3000
ber01-VHDL13_DWPH_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                3040
ber01-VHDL13_DWPH_240930-2205240930-dsw--0-ia5     24-May-2022 09:30                2977
ber01-VHDL13_DWPH_241030-2205241030-dsw--0-ia5     24-May-2022 10:30                2977
ber01-VHDL13_DWPH_241130-2205241130-dsw--0-ia5     24-May-2022 11:30                2986
ber01-VHDL13_DWPH_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2931
ber01-VHDL13_DWPH_241330-2205241330-dsw--0-ia5     24-May-2022 13:30                2931
ber01-VHDL13_DWPH_241430-2205241430-dsw--0-ia5     24-May-2022 14:30                2931
ber01-VHDL13_DWPH_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2777
ber01-VHDL13_DWPH_241630-2205241630-dsw--0-ia5     24-May-2022 16:30                2777
ber01-VHDL13_DWPH_241730-2205241730-dsw--0-ia5     24-May-2022 17:30                2777
ber01-VHDL13_DWPH_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2583
ber01-VHDL13_DWPH_241930-2205241930-dsw--0-ia5     24-May-2022 19:30                2583
ber01-VHDL13_DWPH_242030-2205242030-dsw--0-ia5     24-May-2022 20:30                2583
ber01-VHDL13_DWPH_250030-2205250030-dsw--0-ia5     25-May-2022 00:30                2757
ber01-VHDL13_DWPH_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2891
ber01-VHDL13_DWPH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2986
ber01-VHDL13_DWPH_250530-2205250530-dsw--0-ia5     25-May-2022 05:30                2986
ber01-VHDL13_DWPH_250630-2205250630-dsw--0-ia5     25-May-2022 06:30                2986
ber01-VHDL13_DWPH_250730-2205250730-dsw--0-ia5     25-May-2022 07:30                2986
ber01-VHDL13_DWPH_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2948
ber01-VHDL13_DWPH_250930-2205250930-dsw--0-ia5     25-May-2022 09:30                2948
ber01-VHDL13_DWPH_251030-2205251030-dsw--0-ia5     25-May-2022 10:30                2948
ber01-VHDL13_DWPH_251130-2205251130-dsw--0-ia5     25-May-2022 11:30                2926
ber01-VHDL13_DWPH_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2982
ber01-VHDL13_DWPH_251300_COR-2205251300-dsw--0-ia5 25-May-2022 12:53                3057
ber01-VHDL13_DWPH_251330-2205251330-dsw--0-ia5     25-May-2022 13:30                3053
ber01-VHDL13_DWPH_251430-2205251430-dsw--0-ia5     25-May-2022 14:30                3053
ber01-VHDL13_DWPH_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                3468
ber01-VHDL13_DWPH_251630-2205251630-dsw--0-ia5     25-May-2022 16:30                3474
ber01-VHDL13_DWSG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2770
ber01-VHDL13_DWSG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2230
ber01-VHDL13_DWSG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2234
ber01-VHDL13_DWSG_240400_COR-2205240400-dsw--0-ia5 24-May-2022 07:43                2306
ber01-VHDL13_DWSG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2275
ber01-VHDL13_DWSG_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2293
ber01-VHDL13_DWSG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                1916
ber01-VHDL13_DWSG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2079
ber01-VHDL13_DWSG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2099
ber01-VHDL13_DWSG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2100
ber01-VHDL13_DWSG_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2005
ber01-VHDL13_DWSN_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2162
ber01-VHDL13_DWSN_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2277
ber01-VHDL13_DWSN_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                1807
ber01-VHDL13_DWSN_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                1806
ber01-VHDL13_DWSN_240800_COR-2205240800-dsw--0-ia5 24-May-2022 08:35                1748
ber01-VHDL13_DWSN_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                1741
ber01-VHDL13_DWSN_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                1749
ber01-VHDL13_DWSN_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                1792
ber01-VHDL13_DWSN_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                1807
ber01-VHDL13_DWSN_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                1798
ber01-VHDL13_DWSN_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                1628
ber01-VHDL13_DWSO_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2587
ber01-VHDL13_DWSO_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2683
ber01-VHDL13_DWSO_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2108
ber01-VHDL13_DWSO_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2189
ber01-VHDL13_DWSO_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                2054
ber01-VHDL13_DWSO_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2062
ber01-VHDL13_DWSO_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                1963
ber01-VHDL13_DWSO_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                1978
ber01-VHDL13_DWSO_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                1970
ber01-VHDL13_DWSO_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                1825
ber01-VHDL13_DWSP_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2536
ber01-VHDL13_DWSP_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2627
ber01-VHDL13_DWSP_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2112
ber01-VHDL13_DWSP_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2112
ber01-VHDL13_DWSP_240800_COR-2205240800-dsw--0-ia5 24-May-2022 08:35                2180
ber01-VHDL13_DWSP_241300-2205241300-dsw--0-ia5     24-May-2022 13:30                2011
ber01-VHDL13_DWSP_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2019
ber01-VHDL13_DWSP_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                1886
ber01-VHDL13_DWSP_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                1901
ber01-VHDL13_DWSP_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                1893
ber01-VHDL13_DWSP_251300-2205251300-dsw--0-ia5     25-May-2022 13:30                1748
ber01-VHDL17_DWOG_241200-2205241200-dsw--0-ia5     24-May-2022 11:53                3216
ber01-VHDL17_DWOG_251200-2205251200-dsw--0-ia5     25-May-2022 11:44                2908
ber01-VHDL20_DWHG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3443
ber01-VHDL20_DWHG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2921
ber01-VHDL20_DWHG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2928
ber01-VHDL20_DWHG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3678
ber01-VHDL20_DWHG_241300-2205241300-dsw--0-ia5     24-May-2022 13:45                3080
ber01-VHDL20_DWHG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2719
ber01-VHDL20_DWHG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2836
ber01-VHDL20_DWHG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2785
ber01-VHDL20_DWHG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3555
ber01-VHDL20_DWHG_251300-2205251300-dsw--0-ia5     25-May-2022 13:45                3071
ber01-VHDL20_DWHH_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3248
ber01-VHDL20_DWHH_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2853
ber01-VHDL20_DWHH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2860
ber01-VHDL20_DWHH_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3585
ber01-VHDL20_DWHH_241300-2205241300-dsw--0-ia5     24-May-2022 13:45                2979
ber01-VHDL20_DWHH_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2686
ber01-VHDL20_DWHH_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2785
ber01-VHDL20_DWHH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2746
ber01-VHDL20_DWHH_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3500
ber01-VHDL20_DWHH_251300-2205251300-dsw--0-ia5     25-May-2022 13:45                3098
pid-VHDL12_DWHG_240200-2205240200-dsw--0-ia5       24-May-2022 02:30                2157
pid-VHDL12_DWHG_240400-2205240400-dsw--0-ia5       24-May-2022 05:00                2162
pid-VHDL12_DWHG_250200-2205250200-dsw--0-ia5       25-May-2022 02:30                2147
pid-VHDL12_DWHG_250400-2205250400-dsw--0-ia5       25-May-2022 05:00                2092
pid-VHDL12_DWHH_240200-2205240200-dsw--0-ia5       24-May-2022 02:30                2152
pid-VHDL12_DWHH_240400-2205240400-dsw--0-ia5       24-May-2022 05:00                2159
pid-VHDL12_DWHH_250200-2205250200-dsw--0-ia5       25-May-2022 02:30                2141
pid-VHDL12_DWHH_250400-2205250400-dsw--0-ia5       25-May-2022 05:00                2099
pid-VHDL12_DWMG_231800-2205231800-dsw--0-ia5       23-May-2022 18:30                2350
pid-VHDL12_DWMG_240200-2205240200-dsw--0-ia5       24-May-2022 02:30                2064
pid-VHDL12_DWMG_240400-2205240400-dsw--0-ia5       24-May-2022 05:00                2180
pid-VHDL12_DWMG_240800-2205240800-dsw--0-ia5       24-May-2022 08:30                2483
pid-VHDL12_DWMG_241300-2205241300-dsw--0-ia5       24-May-2022 12:30                2491
pid-VHDL12_DWMG_241800-2205241800-dsw--0-ia5       24-May-2022 18:30                1970
pid-VHDL12_DWMG_250200-2205250200-dsw--0-ia5       25-May-2022 02:30                2165
pid-VHDL12_DWMG_250400-2205250400-dsw--0-ia5       25-May-2022 05:00                2126
pid-VHDL12_DWMG_250800-2205250800-dsw--0-ia5       25-May-2022 08:30                2153
pid-VHDL12_DWMG_251300-2205251300-dsw--0-ia5       25-May-2022 12:30                2040
pid-VHDL12_DWSG_240200-2205240200-dsw--0-ia5       24-May-2022 02:30                1914
pid-VHDL12_DWSG_250200-2205250200-dsw--0-ia5       25-May-2022 02:30                1731
swis2-VHDL20_DWEG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3226
swis2-VHDL20_DWEG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                3100
swis2-VHDL20_DWEG_240400-2205240400-dsw--0-ia5     24-May-2022 05:15                3809
swis2-VHDL20_DWEG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3738
swis2-VHDL20_DWEG_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3579
swis2-VHDL20_DWEG_241500-2205241500-dsw--0-ia5     24-May-2022 15:45                3123
swis2-VHDL20_DWEG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2800
swis2-VHDL20_DWEG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2773
swis2-VHDL20_DWEG_250400-2205250400-dsw--0-ia5     25-May-2022 05:15                3395
swis2-VHDL20_DWEG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3380
swis2-VHDL20_DWEG_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                3421
swis2-VHDL20_DWEG_251500-2205251500-dsw--0-ia5     25-May-2022 15:45                3347
swis2-VHDL20_DWEH_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3398
swis2-VHDL20_DWEH_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                3241
swis2-VHDL20_DWEH_240400-2205240400-dsw--0-ia5     24-May-2022 05:15                3731
swis2-VHDL20_DWEH_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3702
swis2-VHDL20_DWEH_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3592
swis2-VHDL20_DWEH_241500-2205241500-dsw--0-ia5     24-May-2022 15:45                3492
swis2-VHDL20_DWEH_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2944
swis2-VHDL20_DWEH_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2792
swis2-VHDL20_DWEH_250400-2205250400-dsw--0-ia5     25-May-2022 05:15                3484
swis2-VHDL20_DWEH_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3536
swis2-VHDL20_DWEH_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                3535
swis2-VHDL20_DWEH_251500-2205251500-dsw--0-ia5     25-May-2022 15:45                3325
swis2-VHDL20_DWEI_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3119
swis2-VHDL20_DWEI_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2840
swis2-VHDL20_DWEI_240400-2205240400-dsw--0-ia5     24-May-2022 05:15                3612
swis2-VHDL20_DWEI_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3446
swis2-VHDL20_DWEI_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3357
swis2-VHDL20_DWEI_241500-2205241500-dsw--0-ia5     24-May-2022 15:45                2951
swis2-VHDL20_DWEI_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2587
swis2-VHDL20_DWEI_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2683
swis2-VHDL20_DWEI_250400-2205250400-dsw--0-ia5     25-May-2022 05:15                3238
swis2-VHDL20_DWEI_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3296
swis2-VHDL20_DWEI_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                3315
swis2-VHDL20_DWEI_251500-2205251500-dsw--0-ia5     25-May-2022 15:45                3272
swis2-VHDL20_DWHG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3443
swis2-VHDL20_DWHG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2921
swis2-VHDL20_DWHG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2928
swis2-VHDL20_DWHG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3678
swis2-VHDL20_DWHG_241300-2205241300-dsw--0-ia5     24-May-2022 13:45                3080
swis2-VHDL20_DWHG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2719
swis2-VHDL20_DWHG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2836
swis2-VHDL20_DWHG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2785
swis2-VHDL20_DWHG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3555
swis2-VHDL20_DWHG_251300-2205251300-dsw--0-ia5     25-May-2022 13:45                3071
swis2-VHDL20_DWHH_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3248
swis2-VHDL20_DWHH_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2853
swis2-VHDL20_DWHH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2860
swis2-VHDL20_DWHH_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3585
swis2-VHDL20_DWHH_241300-2205241300-dsw--0-ia5     24-May-2022 13:45                2979
swis2-VHDL20_DWHH_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2686
swis2-VHDL20_DWHH_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2785
swis2-VHDL20_DWHH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2746
swis2-VHDL20_DWHH_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3500
swis2-VHDL20_DWHH_251300-2205251300-dsw--0-ia5     25-May-2022 13:45                3098
swis2-VHDL20_DWLG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2090
swis2-VHDL20_DWLG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2177
swis2-VHDL20_DWLG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2233
swis2-VHDL20_DWLG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                2215
swis2-VHDL20_DWLG_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                2257
swis2-VHDL20_DWLG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2136
swis2-VHDL20_DWLG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2763
swis2-VHDL20_DWLG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2641
swis2-VHDL20_DWLG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                3037
swis2-VHDL20_DWLG_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                3081
swis2-VHDL20_DWLH_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2290
swis2-VHDL20_DWLH_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2445
swis2-VHDL20_DWLH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2544
swis2-VHDL20_DWLH_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                2520
swis2-VHDL20_DWLH_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                2339
swis2-VHDL20_DWLH_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2158
swis2-VHDL20_DWLH_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2687
swis2-VHDL20_DWLH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2777
swis2-VHDL20_DWLH_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2812
swis2-VHDL20_DWLH_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                2775
swis2-VHDL20_DWLI_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2166
swis2-VHDL20_DWLI_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2232
swis2-VHDL20_DWLI_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2308
swis2-VHDL20_DWLI_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                2237
swis2-VHDL20_DWLI_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                2260
swis2-VHDL20_DWLI_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2005
swis2-VHDL20_DWLI_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2418
swis2-VHDL20_DWLI_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2363
swis2-VHDL20_DWLI_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2529
swis2-VHDL20_DWLI_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                2560
swis2-VHDL20_DWMG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2910
swis2-VHDL20_DWMG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2784
swis2-VHDL20_DWMG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2950
swis2-VHDL20_DWMG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3253
swis2-VHDL20_DWMG_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3261
swis2-VHDL20_DWMG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2733
swis2-VHDL20_DWMG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2772
swis2-VHDL20_DWMG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2744
swis2-VHDL20_DWMG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2771
swis2-VHDL20_DWMG_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                2658
swis2-VHDL20_DWMO_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2759
swis2-VHDL20_DWMO_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2702
swis2-VHDL20_DWMO_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2798
swis2-VHDL20_DWMO_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                2795
swis2-VHDL20_DWMO_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3145
swis2-VHDL20_DWMO_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2333
swis2-VHDL20_DWMO_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2439
swis2-VHDL20_DWMO_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2439
swis2-VHDL20_DWMO_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2436
swis2-VHDL20_DWMO_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                2309
swis2-VHDL20_DWMP_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                2765
swis2-VHDL20_DWMP_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2518
swis2-VHDL20_DWMP_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2552
swis2-VHDL20_DWMP_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                3065
swis2-VHDL20_DWMP_241300-2205241300-dsw--0-ia5     24-May-2022 12:45                3086
swis2-VHDL20_DWMP_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2594
swis2-VHDL20_DWMP_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2750
swis2-VHDL20_DWMP_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2768
swis2-VHDL20_DWMP_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2768
swis2-VHDL20_DWMP_251300-2205251300-dsw--0-ia5     25-May-2022 12:45                2565
swis2-VHDL20_DWPG_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2480
swis2-VHDL20_DWPG_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2368
swis2-VHDL20_DWPG_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                2738
swis2-VHDL20_DWPG_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                2802
swis2-VHDL20_DWPG_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                2911
swis2-VHDL20_DWPG_241300_COR-2205241300-dsw--0-ia5 24-May-2022 12:55                2807
swis2-VHDL20_DWPG_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2688
swis2-VHDL20_DWPG_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2455
swis2-VHDL20_DWPG_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                2596
swis2-VHDL20_DWPG_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                2631
swis2-VHDL20_DWPG_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                2693
swis2-VHDL20_DWPG_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                2794
swis2-VHDL20_DWPG_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                2988
swis2-VHDL20_DWPH_231800-2205231800-dsw--0-ia5     23-May-2022 18:30                2773
swis2-VHDL20_DWPH_240200-2205240200-dsw--0-ia5     24-May-2022 02:30                2593
swis2-VHDL20_DWPH_240400-2205240400-dsw--0-ia5     24-May-2022 05:00                3168
swis2-VHDL20_DWPH_240800-2205240800-dsw--0-ia5     24-May-2022 08:30                3220
swis2-VHDL20_DWPH_241300-2205241300-dsw--0-ia5     24-May-2022 12:30                3111
swis2-VHDL20_DWPH_241500-2205241500-dsw--0-ia5     24-May-2022 15:30                2957
swis2-VHDL20_DWPH_241800-2205241800-dsw--0-ia5     24-May-2022 18:30                2763
swis2-VHDL20_DWPH_250200-2205250200-dsw--0-ia5     25-May-2022 02:30                3071
swis2-VHDL20_DWPH_250400-2205250400-dsw--0-ia5     25-May-2022 05:00                3166
swis2-VHDL20_DWPH_250800-2205250800-dsw--0-ia5     25-May-2022 08:30                3128
swis2-VHDL20_DWPH_251300-2205251300-dsw--0-ia5     25-May-2022 12:30                3162
swis2-VHDL20_DWPH_251300_COR-2205251300-dsw--0-ia5 25-May-2022 12:54                3237
swis2-VHDL20_DWPH_251500-2205251500-dsw--0-ia5     25-May-2022 15:30                3648
swis2-VHDL20_DWSG_231800-2205231800-dsw--0-ia5     23-May-2022 18:45                3002
swis2-VHDL20_DWSG_240200-2205240200-dsw--0-ia5     24-May-2022 02:45                2464
swis2-VHDL20_DWSG_240400-2205240400-dsw--0-ia5     24-May-2022 05:15                2465
swis2-VHDL20_DWSG_240800-2205240800-dsw--0-ia5     24-May-2022 08:45                2505
swis2-VHDL20_DWSG_241300-2205241300-dsw--0-ia5     24-May-2022 13:45                2525
swis2-VHDL20_DWSG_241800-2205241800-dsw--0-ia5     24-May-2022 18:45                2151
swis2-VHDL20_DWSG_250200-2205250200-dsw--0-ia5     25-May-2022 02:45                2313
swis2-VHDL20_DWSG_250400-2205250400-dsw--0-ia5     25-May-2022 05:15                2330
swis2-VHDL20_DWSG_250800-2205250800-dsw--0-ia5     25-May-2022 08:45                2330
swis2-VHDL20_DWSG_251300-2205251300-dsw--0-ia5     25-May-2022 13:45                2237
wst04-VHDL20_DWEG_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              271744
wst04-VHDL20_DWEG_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              270973
wst04-VHDL20_DWEG_240400-2205240400-omedes--0.pdf  24-May-2022 05:15              271660
wst04-VHDL20_DWEG_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              261216
wst04-VHDL20_DWEG_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              260827
wst04-VHDL20_DWEG_241500-2205241500-omedes--0.pdf  24-May-2022 15:45              260469
wst04-VHDL20_DWEG_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              259430
wst04-VHDL20_DWEG_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              259305
wst04-VHDL20_DWEG_250400-2205250400-omedes--0.pdf  25-May-2022 05:15              259492
wst04-VHDL20_DWEG_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              260974
wst04-VHDL20_DWEG_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              261148
wst04-VHDL20_DWEG_251500-2205251500-omedes--0.pdf  25-May-2022 15:45              261153
wst04-VHDL20_DWEH_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              268517
wst04-VHDL20_DWEH_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              267739
wst04-VHDL20_DWEH_240400-2205240400-omedes--0.pdf  24-May-2022 05:15              268779
wst04-VHDL20_DWEH_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              263676
wst04-VHDL20_DWEH_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              262785
wst04-VHDL20_DWEH_241500-2205241500-omedes--0.pdf  24-May-2022 15:45              262735
wst04-VHDL20_DWEH_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              262447
wst04-VHDL20_DWEH_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              262751
wst04-VHDL20_DWEH_250400-2205250400-omedes--0.pdf  25-May-2022 05:15              263655
wst04-VHDL20_DWEH_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              263621
wst04-VHDL20_DWEH_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              263317
wst04-VHDL20_DWEH_251500-2205251500-omedes--0.pdf  25-May-2022 15:45              262963
wst04-VHDL20_DWEI_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              380219
wst04-VHDL20_DWEI_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              380226
wst04-VHDL20_DWEI_240400-2205240400-omedes--0.pdf  24-May-2022 05:15              380554
wst04-VHDL20_DWEI_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              362004
wst04-VHDL20_DWEI_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              361698
wst04-VHDL20_DWEI_241500-2205241500-omedes--0.pdf  24-May-2022 15:45              361417
wst04-VHDL20_DWEI_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              360395
wst04-VHDL20_DWEI_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              361662
wst04-VHDL20_DWEI_250400-2205250400-omedes--0.pdf  25-May-2022 05:15              361477
wst04-VHDL20_DWEI_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              362015
wst04-VHDL20_DWEI_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              362143
wst04-VHDL20_DWEI_251500-2205251500-omedes--0.pdf  25-May-2022 15:45              362148
wst04-VHDL20_DWHG_231800-2205231800-oflxs888--0..> 23-May-2022 18:45              381343
wst04-VHDL20_DWHG_240200-2205240200-oflxs888--0..> 24-May-2022 02:45              380012
wst04-VHDL20_DWHG_240400-2205240400-oflxs888--0..> 24-May-2022 05:00              380050
wst04-VHDL20_DWHG_240800-2205240800-oflxs888--0..> 24-May-2022 08:45              379023
wst04-VHDL20_DWHG_241300-2205241300-oflxs888--0..> 24-May-2022 13:45              369244
wst04-VHDL20_DWHG_241800-2205241800-oflxs888--0..> 24-May-2022 18:45              368572
wst04-VHDL20_DWHG_250200-2205250200-oflxs888--0..> 25-May-2022 02:45              368935
wst04-VHDL20_DWHG_250400-2205250400-oflxs888--0..> 25-May-2022 05:00              368899
wst04-VHDL20_DWHG_250800-2205250800-oflxs888--0..> 25-May-2022 08:45              373170
wst04-VHDL20_DWHG_251300-2205251300-oflxs888--0..> 25-May-2022 13:45              363454
wst04-VHDL20_DWHH_231800-2205231800-oflxs888--0..> 23-May-2022 18:45              378752
wst04-VHDL20_DWHH_240200-2205240200-oflxs888--0..> 24-May-2022 02:45              377452
wst04-VHDL20_DWHH_240400-2205240400-oflxs888--0..> 24-May-2022 05:00              377562
wst04-VHDL20_DWHH_240800-2205240800-oflxs888--0..> 24-May-2022 08:45              370585
wst04-VHDL20_DWHH_241300-2205241300-oflxs888--0..> 24-May-2022 13:45              361078
wst04-VHDL20_DWHH_241800-2205241800-oflxs888--0..> 24-May-2022 18:45              360803
wst04-VHDL20_DWHH_250200-2205250200-oflxs888--0..> 25-May-2022 02:45              361298
wst04-VHDL20_DWHH_250400-2205250400-oflxs888--0..> 25-May-2022 05:00              361302
wst04-VHDL20_DWHH_250800-2205250800-oflxs888--0..> 25-May-2022 08:45              370475
wst04-VHDL20_DWHH_251300-2205251300-oflxs888--0..> 25-May-2022 13:45              361532
wst04-VHDL20_DWLG_231800-2205231800-omedes--0.pdf  23-May-2022 18:40              364858
wst04-VHDL20_DWLG_240200-2205240200-omedes--0.pdf  24-May-2022 02:40              364612
wst04-VHDL20_DWLG_240400-2205240400-omedes--0.pdf  24-May-2022 04:59              365118
wst04-VHDL20_DWLG_240800-2205240800-omedes--0.pdf  24-May-2022 08:40              355756
wst04-VHDL20_DWLG_241300-2205241300-omedes--0.pdf  24-May-2022 12:40              355987
wst04-VHDL20_DWLG_241800-2205241800-omedes--0.pdf  24-May-2022 18:40              356374
wst04-VHDL20_DWLG_250200-2205250200-omedes--0.pdf  25-May-2022 02:40              357662
wst04-VHDL20_DWLG_250400-2205250400-omedes--0.pdf  25-May-2022 04:59              356767
wst04-VHDL20_DWLG_250800-2205250800-omedes--0.pdf  25-May-2022 08:40              354821
wst04-VHDL20_DWLG_251300-2205251300-omedes--0.pdf  25-May-2022 12:40              355374
wst04-VHDL20_DWLH_231800-2205231800-omedes--0.pdf  23-May-2022 18:40              375800
wst04-VHDL20_DWLH_240200-2205240200-omedes--0.pdf  24-May-2022 02:40              375865
wst04-VHDL20_DWLH_240400-2205240400-omedes--0.pdf  24-May-2022 04:59              376323
wst04-VHDL20_DWLH_240800-2205240800-omedes--0.pdf  24-May-2022 08:40              359509
wst04-VHDL20_DWLH_241300-2205241300-omedes--0.pdf  24-May-2022 12:40              359044
wst04-VHDL20_DWLH_241800-2205241800-omedes--0.pdf  24-May-2022 18:40              359588
wst04-VHDL20_DWLH_250200-2205250200-omedes--0.pdf  25-May-2022 02:40              360816
wst04-VHDL20_DWLH_250400-2205250400-omedes--0.pdf  25-May-2022 04:59              360873
wst04-VHDL20_DWLH_250800-2205250800-omedes--0.pdf  25-May-2022 08:40              349952
wst04-VHDL20_DWLH_251300-2205251300-omedes--0.pdf  25-May-2022 12:40              350466
wst04-VHDL20_DWLI_231800-2205231800-omedes--0.pdf  23-May-2022 18:40              364287
wst04-VHDL20_DWLI_240200-2205240200-omedes--0.pdf  24-May-2022 02:40              364039
wst04-VHDL20_DWLI_240400-2205240400-omedes--0.pdf  24-May-2022 04:59              364532
wst04-VHDL20_DWLI_240800-2205240800-omedes--0.pdf  24-May-2022 08:40              352467
wst04-VHDL20_DWLI_241300-2205241300-omedes--0.pdf  24-May-2022 12:40              352466
wst04-VHDL20_DWLI_241800-2205241800-omedes--0.pdf  24-May-2022 18:40              352961
wst04-VHDL20_DWLI_250200-2205250200-omedes--0.pdf  25-May-2022 02:40              353724
wst04-VHDL20_DWLI_250400-2205250400-omedes--0.pdf  25-May-2022 04:59              352917
wst04-VHDL20_DWLI_250800-2205250800-omedes--0.pdf  25-May-2022 08:40              351313
wst04-VHDL20_DWLI_251300-2205251300-omedes--0.pdf  25-May-2022 12:40              351303
wst04-VHDL20_DWMG_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              584822
wst04-VHDL20_DWMG_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              584981
wst04-VHDL20_DWMG_240400-2205240400-omedes--0.pdf  24-May-2022 05:00              584385
wst04-VHDL20_DWMG_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              558318
wst04-VHDL20_DWMG_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              558487
wst04-VHDL20_DWMG_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              557372
wst04-VHDL20_DWMG_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              557955
wst04-VHDL20_DWMG_250400-2205250400-omedes--0.pdf  25-May-2022 05:00              557379
wst04-VHDL20_DWMG_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              562522
wst04-VHDL20_DWMG_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              561993
wst04-VHDL20_DWMO_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              477123
wst04-VHDL20_DWMO_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              477179
wst04-VHDL20_DWMO_240400-2205240400-omedes--0.pdf  24-May-2022 04:45              477667
wst04-VHDL20_DWMO_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              451951
wst04-VHDL20_DWMO_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              452206
wst04-VHDL20_DWMO_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              451075
wst04-VHDL20_DWMO_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              451424
wst04-VHDL20_DWMO_250400-2205250400-omedes--0.pdf  25-May-2022 04:45              451892
wst04-VHDL20_DWMO_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              450381
wst04-VHDL20_DWMO_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              449565
wst04-VHDL20_DWMP_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              594534
wst04-VHDL20_DWMP_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              593309
wst04-VHDL20_DWMP_240400-2205240400-omedes--0.pdf  24-May-2022 05:00              593592
wst04-VHDL20_DWMP_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              571146
wst04-VHDL20_DWMP_241300-2205241300-omedes--0.pdf  24-May-2022 12:45              571148
wst04-VHDL20_DWMP_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              570821
wst04-VHDL20_DWMP_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              570368
wst04-VHDL20_DWMP_250400-2205250400-omedes--0.pdf  25-May-2022 05:00              570620
wst04-VHDL20_DWMP_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              579652
wst04-VHDL20_DWMP_251300-2205251300-omedes--0.pdf  25-May-2022 12:45              579084
wst04-VHDL20_DWPG_231800-2205231800-oflxs892--0..> 23-May-2022 18:30              377817
wst04-VHDL20_DWPG_240200-2205240200-oflxs892--0..> 24-May-2022 02:30              377584
wst04-VHDL20_DWPG_240400-2205240400-oflxs892--0..> 24-May-2022 05:00              377641
wst04-VHDL20_DWPG_240800-2205240800-oflxs892--0..> 24-May-2022 08:30              406747
wst04-VHDL20_DWPG_241300-2205241300-oflxs892--0..> 24-May-2022 12:30              363421
wst04-VHDL20_DWPG_241500-2205241500-oflxs892--0..> 24-May-2022 15:30              362979
wst04-VHDL20_DWPG_241800-2205241800-oflxs892--0..> 24-May-2022 18:30              362784
wst04-VHDL20_DWPG_250200-2205250200-oflxs892--0..> 25-May-2022 02:30              363570
wst04-VHDL20_DWPG_250400-2205250400-oflxs892--0..> 25-May-2022 05:00              363068
wst04-VHDL20_DWPG_250800-2205250800-oflxs892--0..> 25-May-2022 08:30              402515
wst04-VHDL20_DWPG_251300-2205251300-oflxs892--0..> 25-May-2022 12:30              358115
wst04-VHDL20_DWPG_251500-2205251500-oflxs892--0..> 25-May-2022 15:30              359035
wst04-VHDL20_DWPH_231800-2205231800-oflxs892--0..> 23-May-2022 18:30              315895
wst04-VHDL20_DWPH_240200-2205240200-oflxs892--0..> 24-May-2022 02:30              270426
wst04-VHDL20_DWPH_240400-2205240400-oflxs892--0..> 24-May-2022 05:00              270295
wst04-VHDL20_DWPH_240800-2205240800-oflxs892--0..> 24-May-2022 08:30              310800
wst04-VHDL20_DWPH_241300-2205241300-oflxs892--0..> 24-May-2022 12:30              266646
wst04-VHDL20_DWPH_241500-2205241500-oflxs892--0..> 24-May-2022 15:30              266609
wst04-VHDL20_DWPH_241800-2205241800-oflxs892--0..> 24-May-2022 18:30              311043
wst04-VHDL20_DWPH_250200-2205250200-oflxs892--0..> 25-May-2022 02:30              267020
wst04-VHDL20_DWPH_250400-2205250400-oflxs892--0..> 25-May-2022 05:00              267380
wst04-VHDL20_DWPH_250800-2205250800-oflxs892--0..> 25-May-2022 08:30              308371
wst04-VHDL20_DWPH_251300-2205251300-oflxs892--0..> 25-May-2022 12:30              263553
wst04-VHDL20_DWPH_251300_COR-2205251300-oflxs89..> 25-May-2022 12:54              263617
wst04-VHDL20_DWPH_251500-2205251500-oflxs892--0..> 25-May-2022 15:30              264078
wst04-VHDL20_DWSG_231800-2205231800-omedes--0.pdf  23-May-2022 18:45              386220
wst04-VHDL20_DWSG_240200-2205240200-omedes--0.pdf  24-May-2022 02:45              385074
wst04-VHDL20_DWSG_240400-2205240400-omedes--0.pdf  24-May-2022 05:15              385196
wst04-VHDL20_DWSG_240800-2205240800-omedes--0.pdf  24-May-2022 08:45              359739
wst04-VHDL20_DWSG_241300-2205241300-omedes--0.pdf  24-May-2022 13:45              359776
wst04-VHDL20_DWSG_241800-2205241800-omedes--0.pdf  24-May-2022 18:45              359343
wst04-VHDL20_DWSG_250200-2205250200-omedes--0.pdf  25-May-2022 02:45              359394
wst04-VHDL20_DWSG_250400-2205250400-omedes--0.pdf  25-May-2022 05:15              359493
wst04-VHDL20_DWSG_250800-2205250800-omedes--0.pdf  25-May-2022 08:45              362446
wst04-VHDL20_DWSG_251300-2205251300-omedes--0.pdf  25-May-2022 13:45              362366