Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_250600 25-Jul-2024 13:58 7585
FPDL13_DWMZ_260600 26-Jul-2024 14:40 3404
SXDL31_DWAV_250800 25-Jul-2024 07:03 8459
SXDL31_DWAV_251800 25-Jul-2024 16:36 13092
SXDL31_DWAV_260800 26-Jul-2024 08:19 10690
SXDL31_DWAV_261800 26-Jul-2024 17:13 11736
SXDL31_DWAV_LATEST 26-Jul-2024 17:13 11736
SXDL33_DWAV_250000 25-Jul-2024 09:47 9238
SXDL33_DWAV_260000 26-Jul-2024 10:08 8565
SXDL33_DWAV_LATEST 26-Jul-2024 10:08 8565
ber01-FWDL39_DWMS_251230-2407251230-dsw--0-ia5 25-Jul-2024 12:28 1482
ber01-FWDL39_DWMS_261230-2407261230-dsw--0-ia5 26-Jul-2024 12:33 2120
ber01-VHDL13_DWEH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:28 2202
ber01-VHDL13_DWEH_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:58 2466
ber01-VHDL13_DWEH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:28 2841
ber01-VHDL13_DWEH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:28 2915
ber01-VHDL13_DWEH_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:28 2933
ber01-VHDL13_DWEH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:28 2974
ber01-VHDL13_DWEH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:28 2636
ber01-VHDL13_DWEH_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:58 2711
ber01-VHDL13_DWEH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:28 2834
ber01-VHDL13_DWEH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:28 2762
ber01-VHDL13_DWEH_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:28 3167
ber01-VHDL13_DWEH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:28 2847
ber01-VHDL13_DWHG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2358
ber01-VHDL13_DWHG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2340
ber01-VHDL13_DWHG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2381
ber01-VHDL13_DWHG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 2426
ber01-VHDL13_DWHG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2369
ber01-VHDL13_DWHG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 3040
ber01-VHDL13_DWHG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3419
ber01-VHDL13_DWHG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 3305
ber01-VHDL13_DWHG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 3314
ber01-VHDL13_DWHG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 3077
ber01-VHDL13_DWHH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2435
ber01-VHDL13_DWHH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2409
ber01-VHDL13_DWHH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2461
ber01-VHDL13_DWHH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 2480
ber01-VHDL13_DWHH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2219
ber01-VHDL13_DWHH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2507
ber01-VHDL13_DWHH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2723
ber01-VHDL13_DWHH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2363
ber01-VHDL13_DWHH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 2362
ber01-VHDL13_DWHH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 1972
ber01-VHDL13_DWLG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 1704
ber01-VHDL13_DWLG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1693
ber01-VHDL13_DWLG_250533-2407250533-dsw--0-ia5 25-Jul-2024 05:33 1699
ber01-VHDL13_DWLG_250633-2407250633-dsw--0-ia5 25-Jul-2024 06:33 1699
ber01-VHDL13_DWLG_250733-2407250733-dsw--0-ia5 25-Jul-2024 07:33 1699
ber01-VHDL13_DWLG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 1690
ber01-VHDL13_DWLG_250933-2407250933-dsw--0-ia5 25-Jul-2024 09:33 1708
ber01-VHDL13_DWLG_251033-2407251033-dsw--0-ia5 25-Jul-2024 10:33 1708
ber01-VHDL13_DWLG_251133-2407251133-dsw--0-ia5 25-Jul-2024 11:33 1708
ber01-VHDL13_DWLG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 1702
ber01-VHDL13_DWLG_251333-2407251333-dsw--0-ia5 25-Jul-2024 13:33 1686
ber01-VHDL13_DWLG_251433-2407251433-dsw--0-ia5 25-Jul-2024 14:33 1686
ber01-VHDL13_DWLG_251533-2407251533-dsw--0-ia5 25-Jul-2024 15:33 1686
ber01-VHDL13_DWLG_251633-2407251633-dsw--0-ia5 25-Jul-2024 16:33 1686
ber01-VHDL13_DWLG_251733-2407251733-dsw--0-ia5 25-Jul-2024 17:33 1544
ber01-VHDL13_DWLG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 1538
ber01-VHDL13_DWLG_251933-2407251933-dsw--0-ia5 25-Jul-2024 19:33 1544
ber01-VHDL13_DWLG_252033-2407252033-dsw--0-ia5 25-Jul-2024 20:33 1544
ber01-VHDL13_DWLG_260033-2407260033-dsw--0-ia5 26-Jul-2024 00:33 1682
ber01-VHDL13_DWLG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 1770
ber01-VHDL13_DWLG_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:59 1808
ber01-VHDL13_DWLG_260533-2407260533-dsw--0-ia5 26-Jul-2024 05:33 1814
ber01-VHDL13_DWLG_260633-2407260633-dsw--0-ia5 26-Jul-2024 06:33 1935
ber01-VHDL13_DWLG_260733-2407260733-dsw--0-ia5 26-Jul-2024 07:33 1935
ber01-VHDL13_DWLG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 1874
ber01-VHDL13_DWLG_260933-2407260933-dsw--0-ia5 26-Jul-2024 09:33 1932
ber01-VHDL13_DWLG_261033-2407261033-dsw--0-ia5 26-Jul-2024 10:33 2018
ber01-VHDL13_DWLG_261133-2407261133-dsw--0-ia5 26-Jul-2024 11:33 2018
ber01-VHDL13_DWLG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 2190
ber01-VHDL13_DWLG_261333-2407261333-dsw--0-ia5 26-Jul-2024 13:33 2196
ber01-VHDL13_DWLG_261433-2407261433-dsw--0-ia5 26-Jul-2024 14:33 2196
ber01-VHDL13_DWLG_261533-2407261533-dsw--0-ia5 26-Jul-2024 15:33 2196
ber01-VHDL13_DWLG_261633-2407261633-dsw--0-ia5 26-Jul-2024 16:33 2196
ber01-VHDL13_DWLG_261733-2407261733-dsw--0-ia5 26-Jul-2024 17:33 2035
ber01-VHDL13_DWLG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2029
ber01-VHDL13_DWLG_261933-2407261933-dsw--0-ia5 26-Jul-2024 19:33 2035
ber01-VHDL13_DWLG_262033-2407262033-dsw--0-ia5 26-Jul-2024 20:33 2035
ber01-VHDL13_DWLG_270033-2407270033-dsw--0-ia5 27-Jul-2024 00:33 2004
ber01-VHDL13_DWLH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 1737
ber01-VHDL13_DWLH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1712
ber01-VHDL13_DWLH_250533-2407250533-dsw--0-ia5 25-Jul-2024 05:33 1721
ber01-VHDL13_DWLH_250633-2407250633-dsw--0-ia5 25-Jul-2024 06:33 1721
ber01-VHDL13_DWLH_250733-2407250733-dsw--0-ia5 25-Jul-2024 07:33 1721
ber01-VHDL13_DWLH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 1712
ber01-VHDL13_DWLH_250933-2407250933-dsw--0-ia5 25-Jul-2024 09:33 1730
ber01-VHDL13_DWLH_251033-2407251033-dsw--0-ia5 25-Jul-2024 10:33 1730
ber01-VHDL13_DWLH_251133-2407251133-dsw--0-ia5 25-Jul-2024 11:33 1730
ber01-VHDL13_DWLH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 1721
ber01-VHDL13_DWLH_251333-2407251333-dsw--0-ia5 25-Jul-2024 13:33 1815
ber01-VHDL13_DWLH_251433-2407251433-dsw--0-ia5 25-Jul-2024 14:33 1815
ber01-VHDL13_DWLH_251533-2407251533-dsw--0-ia5 25-Jul-2024 15:33 1815
ber01-VHDL13_DWLH_251633-2407251633-dsw--0-ia5 25-Jul-2024 16:33 1815
ber01-VHDL13_DWLH_251733-2407251733-dsw--0-ia5 25-Jul-2024 17:33 1677
ber01-VHDL13_DWLH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 1668
ber01-VHDL13_DWLH_251933-2407251933-dsw--0-ia5 25-Jul-2024 19:33 1677
ber01-VHDL13_DWLH_252033-2407252033-dsw--0-ia5 25-Jul-2024 20:33 1677
ber01-VHDL13_DWLH_260033-2407260033-dsw--0-ia5 26-Jul-2024 00:33 1736
ber01-VHDL13_DWLH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2084
ber01-VHDL13_DWLH_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:59 2099
ber01-VHDL13_DWLH_260533-2407260533-dsw--0-ia5 26-Jul-2024 05:33 2108
ber01-VHDL13_DWLH_260633-2407260633-dsw--0-ia5 26-Jul-2024 06:33 2130
ber01-VHDL13_DWLH_260733-2407260733-dsw--0-ia5 26-Jul-2024 07:33 2130
ber01-VHDL13_DWLH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2117
ber01-VHDL13_DWLH_260933-2407260933-dsw--0-ia5 26-Jul-2024 09:33 2118
ber01-VHDL13_DWLH_261033-2407261033-dsw--0-ia5 26-Jul-2024 10:33 2118
ber01-VHDL13_DWLH_261133-2407261133-dsw--0-ia5 26-Jul-2024 11:33 2118
ber01-VHDL13_DWLH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 2185
ber01-VHDL13_DWLH_261333-2407261333-dsw--0-ia5 26-Jul-2024 13:33 2194
ber01-VHDL13_DWLH_261433-2407261433-dsw--0-ia5 26-Jul-2024 14:33 2194
ber01-VHDL13_DWLH_261533-2407261533-dsw--0-ia5 26-Jul-2024 15:33 2194
ber01-VHDL13_DWLH_261633-2407261633-dsw--0-ia5 26-Jul-2024 16:33 2194
ber01-VHDL13_DWLH_261733-2407261733-dsw--0-ia5 26-Jul-2024 17:33 2080
ber01-VHDL13_DWLH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2071
ber01-VHDL13_DWLH_261933-2407261933-dsw--0-ia5 26-Jul-2024 19:33 2080
ber01-VHDL13_DWLH_262033-2407262033-dsw--0-ia5 26-Jul-2024 20:33 2080
ber01-VHDL13_DWLH_270033-2407270033-dsw--0-ia5 27-Jul-2024 00:33 2088
ber01-VHDL13_DWLI_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 1715
ber01-VHDL13_DWLI_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1711
ber01-VHDL13_DWLI_250533-2407250533-dsw--0-ia5 25-Jul-2024 05:33 1714
ber01-VHDL13_DWLI_250633-2407250633-dsw--0-ia5 25-Jul-2024 06:33 1714
ber01-VHDL13_DWLI_250733-2407250733-dsw--0-ia5 25-Jul-2024 07:33 1714
ber01-VHDL13_DWLI_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 1708
ber01-VHDL13_DWLI_250933-2407250933-dsw--0-ia5 25-Jul-2024 09:33 1723
ber01-VHDL13_DWLI_251033-2407251033-dsw--0-ia5 25-Jul-2024 10:33 1723
ber01-VHDL13_DWLI_251133-2407251133-dsw--0-ia5 25-Jul-2024 11:33 1723
ber01-VHDL13_DWLI_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 1717
ber01-VHDL13_DWLI_251333-2407251333-dsw--0-ia5 25-Jul-2024 13:33 1807
ber01-VHDL13_DWLI_251433-2407251433-dsw--0-ia5 25-Jul-2024 14:33 1807
ber01-VHDL13_DWLI_251533-2407251533-dsw--0-ia5 25-Jul-2024 15:33 1807
ber01-VHDL13_DWLI_251633-2407251633-dsw--0-ia5 25-Jul-2024 16:33 1807
ber01-VHDL13_DWLI_251733-2407251733-dsw--0-ia5 25-Jul-2024 17:33 1665
ber01-VHDL13_DWLI_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 1659
ber01-VHDL13_DWLI_251933-2407251933-dsw--0-ia5 25-Jul-2024 19:33 1665
ber01-VHDL13_DWLI_252033-2407252033-dsw--0-ia5 25-Jul-2024 20:33 1665
ber01-VHDL13_DWLI_260033-2407260033-dsw--0-ia5 26-Jul-2024 00:33 1727
ber01-VHDL13_DWLI_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2046
ber01-VHDL13_DWLI_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:59 2107
ber01-VHDL13_DWLI_260533-2407260533-dsw--0-ia5 26-Jul-2024 05:33 2110
ber01-VHDL13_DWLI_260633-2407260633-dsw--0-ia5 26-Jul-2024 06:33 2098
ber01-VHDL13_DWLI_260733-2407260733-dsw--0-ia5 26-Jul-2024 07:33 2098
ber01-VHDL13_DWLI_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2088
ber01-VHDL13_DWLI_260933-2407260933-dsw--0-ia5 26-Jul-2024 09:33 2086
ber01-VHDL13_DWLI_261033-2407261033-dsw--0-ia5 26-Jul-2024 10:33 2086
ber01-VHDL13_DWLI_261133-2407261133-dsw--0-ia5 26-Jul-2024 11:33 2086
ber01-VHDL13_DWLI_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 2158
ber01-VHDL13_DWLI_261333-2407261333-dsw--0-ia5 26-Jul-2024 13:33 2164
ber01-VHDL13_DWLI_261433-2407261433-dsw--0-ia5 26-Jul-2024 14:33 2164
ber01-VHDL13_DWLI_261533-2407261533-dsw--0-ia5 26-Jul-2024 15:33 2164
ber01-VHDL13_DWLI_261633-2407261633-dsw--0-ia5 26-Jul-2024 16:33 2164
ber01-VHDL13_DWLI_261733-2407261733-dsw--0-ia5 26-Jul-2024 17:33 2046
ber01-VHDL13_DWLI_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2040
ber01-VHDL13_DWLI_261933-2407261933-dsw--0-ia5 26-Jul-2024 19:33 2046
ber01-VHDL13_DWLI_262033-2407262033-dsw--0-ia5 26-Jul-2024 20:33 2046
ber01-VHDL13_DWLI_270033-2407270033-dsw--0-ia5 27-Jul-2024 00:33 2059
ber01-VHDL13_DWMG_250100-2407250100-dsw--0-ia5 25-Jul-2024 01:30 2428
ber01-VHDL13_DWMG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2428
ber01-VHDL13_DWMG_250300-2407250300-dsw--0-ia5 25-Jul-2024 03:30 2428
ber01-VHDL13_DWMG_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:30 2414
ber01-VHDL13_DWMG_250500-2407250500-dsw--0-ia5 25-Jul-2024 05:30 2414
ber01-VHDL13_DWMG_250600-2407250600-dsw--0-ia5 25-Jul-2024 06:30 2414
ber01-VHDL13_DWMG_250700-2407250700-dsw--0-ia5 25-Jul-2024 07:30 2582
ber01-VHDL13_DWMG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2582
ber01-VHDL13_DWMG_250900-2407250900-dsw--0-ia5 25-Jul-2024 09:30 2582
ber01-VHDL13_DWMG_251000-2407251000-dsw--0-ia5 25-Jul-2024 10:30 2582
ber01-VHDL13_DWMG_251100-2407251100-dsw--0-ia5 25-Jul-2024 11:30 2582
ber01-VHDL13_DWMG_251200-2407251200-dsw--0-ia5 25-Jul-2024 12:30 2624
ber01-VHDL13_DWMG_251300-2407251300-dsw--0-ia5 25-Jul-2024 13:30 2520
ber01-VHDL13_DWMG_251400-2407251400-dsw--0-ia5 25-Jul-2024 14:30 2520
ber01-VHDL13_DWMG_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:30 2520
ber01-VHDL13_DWMG_251600-2407251600-dsw--0-ia5 25-Jul-2024 16:30 2520
ber01-VHDL13_DWMG_251700-2407251700-dsw--0-ia5 25-Jul-2024 17:30 2471
ber01-VHDL13_DWMG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2397
ber01-VHDL13_DWMG_251900-2407251900-dsw--0-ia5 25-Jul-2024 19:30 2408
ber01-VHDL13_DWMG_252000-2407252000-dsw--0-ia5 25-Jul-2024 20:30 2408
ber01-VHDL13_DWMG_252100-2407252100-dsw--0-ia5 25-Jul-2024 21:30 2408
ber01-VHDL13_DWMG_252200-2407252200-dsw--0-ia5 25-Jul-2024 22:30 2384
ber01-VHDL13_DWMG_252300-2407252300-dsw--0-ia5 25-Jul-2024 23:30 2384
ber01-VHDL13_DWMG_260000-2407260000-dsw--0-ia5 26-Jul-2024 00:30 2384
ber01-VHDL13_DWMG_260100-2407260100-dsw--0-ia5 26-Jul-2024 01:30 2384
ber01-VHDL13_DWMG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2384
ber01-VHDL13_DWMG_260300-2407260300-dsw--0-ia5 26-Jul-2024 03:30 2320
ber01-VHDL13_DWMG_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:30 2469
ber01-VHDL13_DWMG_260500-2407260500-dsw--0-ia5 26-Jul-2024 05:30 2699
ber01-VHDL13_DWMG_260600-2407260600-dsw--0-ia5 26-Jul-2024 06:30 2615
ber01-VHDL13_DWMG_260700-2407260700-dsw--0-ia5 26-Jul-2024 07:30 2615
ber01-VHDL13_DWMG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2942
ber01-VHDL13_DWMG_260900-2407260900-dsw--0-ia5 26-Jul-2024 09:30 2933
ber01-VHDL13_DWMG_261000-2407261000-dsw--0-ia5 26-Jul-2024 10:30 3369
ber01-VHDL13_DWMG_261100-2407261100-dsw--0-ia5 26-Jul-2024 11:30 3369
ber01-VHDL13_DWMG_261200-2407261200-dsw--0-ia5 26-Jul-2024 12:30 3369
ber01-VHDL13_DWMG_261300-2407261300-dsw--0-ia5 26-Jul-2024 13:30 3369
ber01-VHDL13_DWMG_261400-2407261400-dsw--0-ia5 26-Jul-2024 14:30 3260
ber01-VHDL13_DWMG_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:30 3260
ber01-VHDL13_DWMG_261600-2407261600-dsw--0-ia5 26-Jul-2024 16:30 3260
ber01-VHDL13_DWMG_261700-2407261700-dsw--0-ia5 26-Jul-2024 17:30 3260
ber01-VHDL13_DWMG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 3216
ber01-VHDL13_DWMG_261900-2407261900-dsw--0-ia5 26-Jul-2024 19:30 3216
ber01-VHDL13_DWMG_262000-2407262000-dsw--0-ia5 26-Jul-2024 20:30 3151
ber01-VHDL13_DWMG_262100-2407262100-dsw--0-ia5 26-Jul-2024 21:30 3151
ber01-VHDL13_DWMG_262200-2407262200-dsw--0-ia5 26-Jul-2024 22:30 3186
ber01-VHDL13_DWMG_262300-2407262300-dsw--0-ia5 26-Jul-2024 23:30 3186
ber01-VHDL13_DWMG_270000-2407270000-dsw--0-ia5 27-Jul-2024 00:30 3186
ber01-VHDL13_DWMO_250100-2407250100-dsw--0-ia5 25-Jul-2024 01:30 2515
ber01-VHDL13_DWMO_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2515
ber01-VHDL13_DWMO_250300-2407250300-dsw--0-ia5 25-Jul-2024 03:30 2515
ber01-VHDL13_DWMO_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:30 2495
ber01-VHDL13_DWMO_250500-2407250500-dsw--0-ia5 25-Jul-2024 05:30 2495
ber01-VHDL13_DWMO_250600-2407250600-dsw--0-ia5 25-Jul-2024 06:30 2495
ber01-VHDL13_DWMO_250700-2407250700-dsw--0-ia5 25-Jul-2024 07:30 2609
ber01-VHDL13_DWMO_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2609
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ber01-VHDL13_DWMO_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2258
ber01-VHDL13_DWMO_251900-2407251900-dsw--0-ia5 25-Jul-2024 19:30 2294
ber01-VHDL13_DWMO_252000-2407252000-dsw--0-ia5 25-Jul-2024 20:30 2294
ber01-VHDL13_DWMO_252100-2407252100-dsw--0-ia5 25-Jul-2024 21:30 2294
ber01-VHDL13_DWMO_252200-2407252200-dsw--0-ia5 25-Jul-2024 22:30 2322
ber01-VHDL13_DWMO_252300-2407252300-dsw--0-ia5 25-Jul-2024 23:30 2322
ber01-VHDL13_DWMO_260000-2407260000-dsw--0-ia5 26-Jul-2024 00:30 2322
ber01-VHDL13_DWMO_260100-2407260100-dsw--0-ia5 26-Jul-2024 01:30 2322
ber01-VHDL13_DWMO_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2322
ber01-VHDL13_DWMO_260300-2407260300-dsw--0-ia5 26-Jul-2024 03:30 2327
ber01-VHDL13_DWMO_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:30 2466
ber01-VHDL13_DWMO_260500-2407260500-dsw--0-ia5 26-Jul-2024 05:30 2791
ber01-VHDL13_DWMO_260600-2407260600-dsw--0-ia5 26-Jul-2024 06:30 2724
ber01-VHDL13_DWMO_260700-2407260700-dsw--0-ia5 26-Jul-2024 07:30 2724
ber01-VHDL13_DWMO_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2827
ber01-VHDL13_DWMO_260900-2407260900-dsw--0-ia5 26-Jul-2024 09:30 2818
ber01-VHDL13_DWMO_261000-2407261000-dsw--0-ia5 26-Jul-2024 10:30 3158
ber01-VHDL13_DWMO_261100-2407261100-dsw--0-ia5 26-Jul-2024 11:30 3158
ber01-VHDL13_DWMO_261200-2407261200-dsw--0-ia5 26-Jul-2024 12:30 3148
ber01-VHDL13_DWMO_261300-2407261300-dsw--0-ia5 26-Jul-2024 13:30 3148
ber01-VHDL13_DWMO_261400-2407261400-dsw--0-ia5 26-Jul-2024 14:30 2880
ber01-VHDL13_DWMO_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:30 2880
ber01-VHDL13_DWMO_261600-2407261600-dsw--0-ia5 26-Jul-2024 16:30 2880
ber01-VHDL13_DWMO_261700-2407261700-dsw--0-ia5 26-Jul-2024 17:30 2880
ber01-VHDL13_DWMO_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2983
ber01-VHDL13_DWMO_261900-2407261900-dsw--0-ia5 26-Jul-2024 19:30 2983
ber01-VHDL13_DWMO_262000-2407262000-dsw--0-ia5 26-Jul-2024 20:30 2983
ber01-VHDL13_DWMO_262100-2407262100-dsw--0-ia5 26-Jul-2024 21:30 2983
ber01-VHDL13_DWMO_262200-2407262200-dsw--0-ia5 26-Jul-2024 22:30 3114
ber01-VHDL13_DWMO_262300-2407262300-dsw--0-ia5 26-Jul-2024 23:30 3114
ber01-VHDL13_DWMO_270000-2407270000-dsw--0-ia5 27-Jul-2024 00:30 3114
ber01-VHDL13_DWMP_250100-2407250100-dsw--0-ia5 25-Jul-2024 01:30 2381
ber01-VHDL13_DWMP_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2381
ber01-VHDL13_DWMP_250300-2407250300-dsw--0-ia5 25-Jul-2024 03:30 2381
ber01-VHDL13_DWMP_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:30 2361
ber01-VHDL13_DWMP_250500-2407250500-dsw--0-ia5 25-Jul-2024 05:30 2361
ber01-VHDL13_DWMP_250600-2407250600-dsw--0-ia5 25-Jul-2024 06:30 2361
ber01-VHDL13_DWMP_250700-2407250700-dsw--0-ia5 25-Jul-2024 07:30 2361
ber01-VHDL13_DWMP_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2524
ber01-VHDL13_DWMP_250900-2407250900-dsw--0-ia5 25-Jul-2024 09:30 2524
ber01-VHDL13_DWMP_251000-2407251000-dsw--0-ia5 25-Jul-2024 10:30 2524
ber01-VHDL13_DWMP_251100-2407251100-dsw--0-ia5 25-Jul-2024 11:30 2524
ber01-VHDL13_DWMP_251200-2407251200-dsw--0-ia5 25-Jul-2024 12:30 2393
ber01-VHDL13_DWMP_251300-2407251300-dsw--0-ia5 25-Jul-2024 13:30 2408
ber01-VHDL13_DWMP_251400-2407251400-dsw--0-ia5 25-Jul-2024 14:30 2408
ber01-VHDL13_DWMP_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:30 2408
ber01-VHDL13_DWMP_251600-2407251600-dsw--0-ia5 25-Jul-2024 16:30 2408
ber01-VHDL13_DWMP_251700-2407251700-dsw--0-ia5 25-Jul-2024 17:30 2335
ber01-VHDL13_DWMP_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2335
ber01-VHDL13_DWMP_251900-2407251900-dsw--0-ia5 25-Jul-2024 19:30 2236
ber01-VHDL13_DWMP_252000-2407252000-dsw--0-ia5 25-Jul-2024 20:30 2236
ber01-VHDL13_DWMP_252100-2407252100-dsw--0-ia5 25-Jul-2024 21:30 2236
ber01-VHDL13_DWMP_252200-2407252200-dsw--0-ia5 25-Jul-2024 22:30 2258
ber01-VHDL13_DWMP_252300-2407252300-dsw--0-ia5 25-Jul-2024 23:30 2258
ber01-VHDL13_DWMP_260000-2407260000-dsw--0-ia5 26-Jul-2024 00:30 2258
ber01-VHDL13_DWMP_260100-2407260100-dsw--0-ia5 26-Jul-2024 01:30 2258
ber01-VHDL13_DWMP_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2258
ber01-VHDL13_DWMP_260300-2407260300-dsw--0-ia5 26-Jul-2024 03:30 2194
ber01-VHDL13_DWMP_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:30 2194
ber01-VHDL13_DWMP_260500-2407260500-dsw--0-ia5 26-Jul-2024 05:30 2275
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ber01-VHDL13_DWMP_260700-2407260700-dsw--0-ia5 26-Jul-2024 07:30 2229
ber01-VHDL13_DWMP_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2366
ber01-VHDL13_DWMP_260900-2407260900-dsw--0-ia5 26-Jul-2024 09:30 2366
ber01-VHDL13_DWMP_261000-2407261000-dsw--0-ia5 26-Jul-2024 10:30 2901
ber01-VHDL13_DWMP_261100-2407261100-dsw--0-ia5 26-Jul-2024 11:30 2901
ber01-VHDL13_DWMP_261200-2407261200-dsw--0-ia5 26-Jul-2024 12:30 2924
ber01-VHDL13_DWMP_261300-2407261300-dsw--0-ia5 26-Jul-2024 13:30 2924
ber01-VHDL13_DWMP_261400-2407261400-dsw--0-ia5 26-Jul-2024 14:30 2803
ber01-VHDL13_DWMP_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:30 2803
ber01-VHDL13_DWMP_261600-2407261600-dsw--0-ia5 26-Jul-2024 16:30 2803
ber01-VHDL13_DWMP_261700-2407261700-dsw--0-ia5 26-Jul-2024 17:30 2803
ber01-VHDL13_DWMP_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2663
ber01-VHDL13_DWMP_261900-2407261900-dsw--0-ia5 26-Jul-2024 19:30 2663
ber01-VHDL13_DWMP_262000-2407262000-dsw--0-ia5 26-Jul-2024 20:30 2663
ber01-VHDL13_DWMP_262100-2407262100-dsw--0-ia5 26-Jul-2024 21:30 2663
ber01-VHDL13_DWMP_262200-2407262200-dsw--0-ia5 26-Jul-2024 22:30 2975
ber01-VHDL13_DWMP_262300-2407262300-dsw--0-ia5 26-Jul-2024 23:30 2975
ber01-VHDL13_DWMP_270000-2407270000-dsw--0-ia5 27-Jul-2024 00:30 2975
ber01-VHDL13_DWOG_250100-2407250100-dsw--0-ia5 25-Jul-2024 01:45 3229
ber01-VHDL13_DWOG_250300-2407250300-dsw--0-ia5 25-Jul-2024 03:00 3213
ber01-VHDL13_DWOG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:15 3031
ber01-VHDL13_DWOG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:00 3220
ber01-VHDL13_DWOG_251700-2407251700-dsw--0-ia5 25-Jul-2024 17:30 3384
ber01-VHDL13_DWOG_260100-2407260100-dsw--0-ia5 26-Jul-2024 01:45 3954
ber01-VHDL13_DWOG_260300-2407260300-dsw--0-ia5 26-Jul-2024 03:00 3954
ber01-VHDL13_DWOG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:15 4153
ber01-VHDL13_DWOG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:00 3940
ber01-VHDL13_DWOG_261700-2407261700-dsw--0-ia5 26-Jul-2024 17:30 3804
ber01-VHDL13_DWOH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:28 2136
ber01-VHDL13_DWOH_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:58 2201
ber01-VHDL13_DWOH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:28 2473
ber01-VHDL13_DWOH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:28 2553
ber01-VHDL13_DWOH_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:28 2522
ber01-VHDL13_DWOH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:28 2692
ber01-VHDL13_DWOH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:28 2546
ber01-VHDL13_DWOH_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:58 2657
ber01-VHDL13_DWOH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:28 2748
ber01-VHDL13_DWOH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:28 2714
ber01-VHDL13_DWOH_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:28 3116
ber01-VHDL13_DWOH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:28 2787
ber01-VHDL13_DWOI_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:28 2130
ber01-VHDL13_DWOI_250400-2407250400-dsw--0-ia5 25-Jul-2024 04:58 2210
ber01-VHDL13_DWOI_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:28 2438
ber01-VHDL13_DWOI_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:28 2511
ber01-VHDL13_DWOI_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:28 2515
ber01-VHDL13_DWOI_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:28 2694
ber01-VHDL13_DWOI_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:28 2574
ber01-VHDL13_DWOI_260400-2407260400-dsw--0-ia5 26-Jul-2024 04:58 2761
ber01-VHDL13_DWOI_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:28 2832
ber01-VHDL13_DWOI_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:28 2750
ber01-VHDL13_DWOI_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:28 3156
ber01-VHDL13_DWOI_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:28 2812
ber01-VHDL13_DWON_250157-2407250157-dsw--0-ia5 25-Jul-2024 01:58 3239
ber01-VHDL13_DWON_250527-2407250527-dsw--0-ia5 25-Jul-2024 05:28 3239
ber01-VHDL13_DWON_250609-2407250609-dsw--0-ia5 25-Jul-2024 06:09 3524
ber01-VHDL13_DWON_251134-2407251134-dsw--0-ia5 25-Jul-2024 11:34 3546
ber01-VHDL13_DWON_251443-2407251443-dsw--0-ia5 25-Jul-2024 14:43 3711
ber01-VHDL13_DWON_251641-2407251641-dsw--0-ia5 25-Jul-2024 16:41 3621
ber01-VHDL13_DWON_251941-2407251941-dsw--0-ia5 25-Jul-2024 19:41 3605
ber01-VHDL13_DWON_260029-2407260029-dsw--0-ia5 26-Jul-2024 00:29 3676
ber01-VHDL13_DWON_260136-2407260136-dsw--0-ia5 26-Jul-2024 01:36 3676
ber01-VHDL13_DWON_260257-2407260257-dsw--0-ia5 26-Jul-2024 02:57 3756
ber01-VHDL13_DWON_260521-2407260521-dsw--0-ia5 26-Jul-2024 05:21 4164
ber01-VHDL13_DWON_260615-2407260615-dsw--0-ia5 26-Jul-2024 06:15 4244
ber01-VHDL13_DWON_261123-2407261123-dsw--0-ia5 26-Jul-2024 11:23 3987
ber01-VHDL13_DWON_261443-2407261443-dsw--0-ia5 26-Jul-2024 14:43 3940
ber01-VHDL13_DWON_261726-2407261726-dsw--0-ia5 26-Jul-2024 17:26 3232
ber01-VHDL13_DWON_262005-2407262005-dsw--0-ia5 26-Jul-2024 20:05 3518
ber01-VHDL13_DWON_270025-2407270025-dsw--0-ia5 27-Jul-2024 00:25 3446
ber01-VHDL13_DWPG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2332
ber01-VHDL13_DWPG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2236
ber01-VHDL13_DWPG_250530-2407250530-dsw--0-ia5 25-Jul-2024 05:30 2234
ber01-VHDL13_DWPG_250630-2407250630-dsw--0-ia5 25-Jul-2024 06:30 2296
ber01-VHDL13_DWPG_250730-2407250730-dsw--0-ia5 25-Jul-2024 07:30 2296
ber01-VHDL13_DWPG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2311
ber01-VHDL13_DWPG_250930-2407250930-dsw--0-ia5 25-Jul-2024 09:30 2310
ber01-VHDL13_DWPG_251030-2407251030-dsw--0-ia5 25-Jul-2024 10:30 2310
ber01-VHDL13_DWPG_251130-2407251130-dsw--0-ia5 25-Jul-2024 11:30 2363
ber01-VHDL13_DWPG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 2363
ber01-VHDL13_DWPG_251330-2407251330-dsw--0-ia5 25-Jul-2024 13:30 2362
ber01-VHDL13_DWPG_251430-2407251430-dsw--0-ia5 25-Jul-2024 14:30 2362
ber01-VHDL13_DWPG_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:30 2304
ber01-VHDL13_DWPG_251630-2407251630-dsw--0-ia5 25-Jul-2024 16:30 2303
ber01-VHDL13_DWPG_251730-2407251730-dsw--0-ia5 25-Jul-2024 17:30 2303
ber01-VHDL13_DWPG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2304
ber01-VHDL13_DWPG_251930-2407251930-dsw--0-ia5 25-Jul-2024 19:30 2303
ber01-VHDL13_DWPG_252030-2407252030-dsw--0-ia5 25-Jul-2024 20:30 2303
ber01-VHDL13_DWPG_260030-2407260030-dsw--0-ia5 26-Jul-2024 00:30 2199
ber01-VHDL13_DWPG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2200
ber01-VHDL13_DWPG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2793
ber01-VHDL13_DWPG_260400_COR-2407260400-dsw--0-ia5 26-Jul-2024 06:09 3254
ber01-VHDL13_DWPG_260530-2407260530-dsw--0-ia5 26-Jul-2024 05:30 2988
ber01-VHDL13_DWPG_260630-2407260630-dsw--0-ia5 26-Jul-2024 06:30 3248
ber01-VHDL13_DWPG_260730-2407260730-dsw--0-ia5 26-Jul-2024 07:30 3248
ber01-VHDL13_DWPG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 3595
ber01-VHDL13_DWPG_260930-2407260930-dsw--0-ia5 26-Jul-2024 09:30 3594
ber01-VHDL13_DWPG_261030-2407261030-dsw--0-ia5 26-Jul-2024 10:30 3594
ber01-VHDL13_DWPG_261130-2407261130-dsw--0-ia5 26-Jul-2024 11:30 3504
ber01-VHDL13_DWPG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 3566
ber01-VHDL13_DWPG_261330-2407261330-dsw--0-ia5 26-Jul-2024 13:30 3565
ber01-VHDL13_DWPG_261430-2407261430-dsw--0-ia5 26-Jul-2024 14:30 3565
ber01-VHDL13_DWPG_261500-2407261500-dsw--0-ia5 26-Jul-2024 15:30 3605
ber01-VHDL13_DWPG_261630-2407261630-dsw--0-ia5 26-Jul-2024 16:30 3604
ber01-VHDL13_DWPG_261730-2407261730-dsw--0-ia5 26-Jul-2024 17:30 3679
ber01-VHDL13_DWPG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 3658
ber01-VHDL13_DWPG_261930-2407261930-dsw--0-ia5 26-Jul-2024 19:30 3657
ber01-VHDL13_DWPG_262030-2407262030-dsw--0-ia5 26-Jul-2024 20:30 3657
ber01-VHDL13_DWPG_270030-2407270030-dsw--0-ia5 27-Jul-2024 00:30 3489
ber01-VHDL13_DWPH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2096
ber01-VHDL13_DWPH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2384
ber01-VHDL13_DWPH_250530-2407250530-dsw--0-ia5 25-Jul-2024 05:30 2384
ber01-VHDL13_DWPH_250630-2407250630-dsw--0-ia5 25-Jul-2024 06:30 2522
ber01-VHDL13_DWPH_250730-2407250730-dsw--0-ia5 25-Jul-2024 07:30 2522
ber01-VHDL13_DWPH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2504
ber01-VHDL13_DWPH_250930-2407250930-dsw--0-ia5 25-Jul-2024 09:30 2504
ber01-VHDL13_DWPH_251030-2407251030-dsw--0-ia5 25-Jul-2024 10:30 2504
ber01-VHDL13_DWPH_251130-2407251130-dsw--0-ia5 25-Jul-2024 11:30 2723
ber01-VHDL13_DWPH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 2723
ber01-VHDL13_DWPH_251330-2407251330-dsw--0-ia5 25-Jul-2024 13:30 2723
ber01-VHDL13_DWPH_251430-2407251430-dsw--0-ia5 25-Jul-2024 14:30 2723
ber01-VHDL13_DWPH_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:30 2620
ber01-VHDL13_DWPH_251630-2407251630-dsw--0-ia5 25-Jul-2024 16:30 2620
ber01-VHDL13_DWPH_251730-2407251730-dsw--0-ia5 25-Jul-2024 17:30 2620
ber01-VHDL13_DWPH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2620
ber01-VHDL13_DWPH_251930-2407251930-dsw--0-ia5 25-Jul-2024 19:30 2620
ber01-VHDL13_DWPH_252030-2407252030-dsw--0-ia5 25-Jul-2024 20:30 2620
ber01-VHDL13_DWPH_260030-2407260030-dsw--0-ia5 26-Jul-2024 00:30 2496
ber01-VHDL13_DWPH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2496
ber01-VHDL13_DWPH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2860
ber01-VHDL13_DWPH_260400_COR-2407260400-dsw--0-ia5 26-Jul-2024 06:10 3017
ber01-VHDL13_DWPH_260530-2407260530-dsw--0-ia5 26-Jul-2024 05:30 2851
ber01-VHDL13_DWPH_260630-2407260630-dsw--0-ia5 26-Jul-2024 06:30 3013
ber01-VHDL13_DWPH_260730-2407260730-dsw--0-ia5 26-Jul-2024 07:30 3013
ber01-VHDL13_DWPH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 3056
ber01-VHDL13_DWPH_260930-2407260930-dsw--0-ia5 26-Jul-2024 09:30 3056
ber01-VHDL13_DWPH_261030-2407261030-dsw--0-ia5 26-Jul-2024 10:30 3056
ber01-VHDL13_DWPH_261130-2407261130-dsw--0-ia5 26-Jul-2024 11:30 3086
ber01-VHDL13_DWPH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 2972
ber01-VHDL13_DWPH_261330-2407261330-dsw--0-ia5 26-Jul-2024 13:30 2972
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ber01-VHDL13_DWPH_261930-2407261930-dsw--0-ia5 26-Jul-2024 19:30 3226
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ber01-VHDL13_DWSG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2209
ber01-VHDL13_DWSG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2372
ber01-VHDL13_DWSG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2386
ber01-VHDL13_DWSG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2802
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ber01-VHDL13_DWSN_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 1579
ber01-VHDL13_DWSN_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 1615
ber01-VHDL13_DWSN_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 1590
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ber01-VHDL13_DWSO_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2178
ber01-VHDL13_DWSO_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2231
ber01-VHDL13_DWSO_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2514
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ber01-VHDL13_DWSO_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:30 2317
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ber01-VHDL13_DWSP_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2115
ber01-VHDL13_DWSP_251300-2407251300-dsw--0-ia5 25-Jul-2024 13:30 2059
ber01-VHDL13_DWSP_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 1878
ber01-VHDL13_DWSP_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 1967
ber01-VHDL13_DWSP_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 1892
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ber01-VHDL13_DWSP_261300-2407261300-dsw--0-ia5 26-Jul-2024 13:30 2181
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ber01-VHDL20_DWHG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2638
ber01-VHDL20_DWHG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 3309
ber01-VHDL20_DWHG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3688
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ber01-VHDL20_DWHH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2497
ber01-VHDL20_DWHH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2693
ber01-VHDL20_DWHH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3001
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pid-VHDL12_DWHG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 1936
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pid-VHDL12_DWHG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3168
pid-VHDL12_DWHH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 2001
pid-VHDL12_DWHH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1975
pid-VHDL12_DWHH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2255
pid-VHDL12_DWHH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2471
pid-VHDL12_DWMG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:30 1945
pid-VHDL12_DWMG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1931
pid-VHDL12_DWMG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:30 2099
pid-VHDL12_DWMG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:30 2241
pid-VHDL12_DWMG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:30 2012
pid-VHDL12_DWMG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:30 2139
pid-VHDL12_DWMG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2454
pid-VHDL12_DWMG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:30 2612
pid-VHDL12_DWMG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:30 3039
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swis2-VHDL20_DWEG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2706
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swis2-VHDL20_DWEH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2394
swis2-VHDL20_DWEH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:15 2672
swis2-VHDL20_DWEH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 3047
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swis2-VHDL20_DWEH_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:45 3139
swis2-VHDL20_DWEH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 3202
swis2-VHDL20_DWEH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2828
swis2-VHDL20_DWEH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:15 2917
swis2-VHDL20_DWEH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 3040
swis2-VHDL20_DWEH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 2968
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swis2-VHDL20_DWEI_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2291
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swis2-VHDL20_DWEI_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 2645
swis2-VHDL20_DWEI_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 2724
swis2-VHDL20_DWEI_251500-2407251500-dsw--0-ia5 25-Jul-2024 15:45 2728
swis2-VHDL20_DWEI_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2907
swis2-VHDL20_DWEI_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2735
swis2-VHDL20_DWEI_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:15 2974
swis2-VHDL20_DWEI_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 3039
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swis2-VHDL20_DWHG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2638
swis2-VHDL20_DWHG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 3309
swis2-VHDL20_DWHG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3688
swis2-VHDL20_DWHG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 5451
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swis2-VHDL20_DWHH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2621
swis2-VHDL20_DWHH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2687
swis2-VHDL20_DWHH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 4601
swis2-VHDL20_DWHH_251300-2407251300-dsw--0-ia5 25-Jul-2024 13:45 2758
swis2-VHDL20_DWHH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2497
swis2-VHDL20_DWHH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2693
swis2-VHDL20_DWHH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 3001
swis2-VHDL20_DWHH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 4524
swis2-VHDL20_DWHH_261300-2407261300-dsw--0-ia5 26-Jul-2024 13:45 2640
swis2-VHDL20_DWHH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 2250
swis2-VHDL20_DWLG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 1953
swis2-VHDL20_DWLG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1942
swis2-VHDL20_DWLG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 1951
swis2-VHDL20_DWLG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 1953
swis2-VHDL20_DWLG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 1787
swis2-VHDL20_DWLG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2019
swis2-VHDL20_DWLG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2057
swis2-VHDL20_DWLG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 2126
swis2-VHDL20_DWLG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 2439
swis2-VHDL20_DWLG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 2278
swis2-VHDL20_DWLH_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 1986
swis2-VHDL20_DWLH_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1961
swis2-VHDL20_DWLH_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 1970
swis2-VHDL20_DWLH_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 2079
swis2-VHDL20_DWLH_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 1917
swis2-VHDL20_DWLH_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2333
swis2-VHDL20_DWLH_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2348
swis2-VHDL20_DWLH_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 2366
swis2-VHDL20_DWLH_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 2434
swis2-VHDL20_DWLH_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 2320
swis2-VHDL20_DWLI_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 1964
swis2-VHDL20_DWLI_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 1957
swis2-VHDL20_DWLI_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 1966
swis2-VHDL20_DWLI_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 2074
swis2-VHDL20_DWLI_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 1908
swis2-VHDL20_DWLI_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2295
swis2-VHDL20_DWLI_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2353
swis2-VHDL20_DWLI_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 2337
swis2-VHDL20_DWLI_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 2407
swis2-VHDL20_DWLI_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 2289
swis2-VHDL20_DWMG_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2639
swis2-VHDL20_DWMG_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2625
swis2-VHDL20_DWMG_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 2793
swis2-VHDL20_DWMG_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 2835
swis2-VHDL20_DWMG_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2619
swis2-VHDL20_DWMG_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2559
swis2-VHDL20_DWMG_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2910
swis2-VHDL20_DWMG_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 3153
swis2-VHDL20_DWMG_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 3580
swis2-VHDL20_DWMG_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 3427
swis2-VHDL20_DWMO_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2730
swis2-VHDL20_DWMO_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2710
swis2-VHDL20_DWMO_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 2821
swis2-VHDL20_DWMO_251300-2407251300-dsw--0-ia5 25-Jul-2024 12:45 2808
swis2-VHDL20_DWMO_251800-2407251800-dsw--0-ia5 25-Jul-2024 18:45 2506
swis2-VHDL20_DWMO_260200-2407260200-dsw--0-ia5 26-Jul-2024 02:45 2537
swis2-VHDL20_DWMO_260400-2407260400-dsw--0-ia5 26-Jul-2024 05:00 2681
swis2-VHDL20_DWMO_260800-2407260800-dsw--0-ia5 26-Jul-2024 08:45 3039
swis2-VHDL20_DWMO_261300-2407261300-dsw--0-ia5 26-Jul-2024 12:45 3360
swis2-VHDL20_DWMO_261800-2407261800-dsw--0-ia5 26-Jul-2024 18:45 3195
swis2-VHDL20_DWMP_250200-2407250200-dsw--0-ia5 25-Jul-2024 02:46 2593
swis2-VHDL20_DWMP_250400-2407250400-dsw--0-ia5 25-Jul-2024 05:00 2573
swis2-VHDL20_DWMP_250800-2407250800-dsw--0-ia5 25-Jul-2024 08:45 2736
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