Index of /weather/text_forecasts/txt/
../
FPDL13_DWMZ_040600 04-Jul-2025 13:13:10 4476
FPDL13_DWMZ_050600 05-Jul-2025 12:22:44 2707
SXDL31_DWAV_040800 04-Jul-2025 07:41:08 12216
SXDL31_DWAV_041800 04-Jul-2025 16:40:20 5756
SXDL31_DWAV_050800 05-Jul-2025 07:20:38 7351
SXDL31_DWAV_051800 05-Jul-2025 17:00:50 10268
SXDL31_DWAV_LATEST 05-Jul-2025 17:00:50 10268
SXDL33_DWAV_040000 04-Jul-2025 09:44:29 6019
SXDL33_DWAV_050000 05-Jul-2025 08:54:05 6899
SXDL33_DWAV_LATEST 05-Jul-2025 08:54:05 6899
ber01-FWDL39_DWMS_041230-2507041230-dsw--0-ia5 04-Jul-2025 11:49:06 881
ber01-FWDL39_DWMS_051230-2507051230-dsw--0-ia5 05-Jul-2025 11:55:01 1236
ber01-VHDL13_DWEH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:28:12 2124
ber01-VHDL13_DWEH_040400-2507040400-dsw--0-ia5 04-Jul-2025 04:58:11 2078
ber01-VHDL13_DWEH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:12 2216
ber01-VHDL13_DWEH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:12 2209
ber01-VHDL13_DWEH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:11 2391
ber01-VHDL13_DWEH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:06 2349
ber01-VHDL13_DWEH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2646
ber01-VHDL13_DWEH_050800_COR-2507050800-dsw--0-ia5 05-Jul-2025 14:28:36 3110
ber01-VHDL13_DWEH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:11 2833
ber01-VHDL13_DWHG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:08 2366
ber01-VHDL13_DWHG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:11 2369
ber01-VHDL13_DWHG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:07 2983
ber01-VHDL13_DWHG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2728
ber01-VHDL13_DWHG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:08 3067
ber01-VHDL13_DWHG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3070
ber01-VHDL13_DWHG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:07 3331
ber01-VHDL13_DWHG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2659
ber01-VHDL13_DWHH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:08 2623
ber01-VHDL13_DWHH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:11 2621
ber01-VHDL13_DWHH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:07 3031
ber01-VHDL13_DWHH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2602
ber01-VHDL13_DWHH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:08 3081
ber01-VHDL13_DWHH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3084
ber01-VHDL13_DWHH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:08 3305
ber01-VHDL13_DWHH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2702
ber01-VHDL13_DWLG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:08 1869
ber01-VHDL13_DWLG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:02 1946
ber01-VHDL13_DWLG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1943
ber01-VHDL13_DWLG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1820
ber01-VHDL13_DWLG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 2065
ber01-VHDL13_DWLG_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2300
ber01-VHDL13_DWLG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2241
ber01-VHDL13_DWLG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2062
ber01-VHDL13_DWLH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:08 1833
ber01-VHDL13_DWLH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:02 1930
ber01-VHDL13_DWLH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2003
ber01-VHDL13_DWLH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1975
ber01-VHDL13_DWLH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 2349
ber01-VHDL13_DWLH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2722
ber01-VHDL13_DWLH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2752
ber01-VHDL13_DWLH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2301
ber01-VHDL13_DWLI_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:08 1771
ber01-VHDL13_DWLI_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:02 1802
ber01-VHDL13_DWLI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1798
ber01-VHDL13_DWLI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1693
ber01-VHDL13_DWLI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:05 1977
ber01-VHDL13_DWLI_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:59:57 2190
ber01-VHDL13_DWLI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2195
ber01-VHDL13_DWLI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 1981
ber01-VHDL13_DWMG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2537
ber01-VHDL13_DWMG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2545
ber01-VHDL13_DWMG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2568
ber01-VHDL13_DWMG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2450
ber01-VHDL13_DWMG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2497
ber01-VHDL13_DWMG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2500
ber01-VHDL13_DWMG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2763
ber01-VHDL13_DWMG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2649
ber01-VHDL13_DWMG_051800_COR-2507051800-dsw--0-ia5 05-Jul-2025 19:41:57 3100
ber01-VHDL13_DWMO_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2141
ber01-VHDL13_DWMO_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2141
ber01-VHDL13_DWMO_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2101
ber01-VHDL13_DWMO_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2049
ber01-VHDL13_DWMO_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2326
ber01-VHDL13_DWMO_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2333
ber01-VHDL13_DWMO_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2573
ber01-VHDL13_DWMO_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2209
ber01-VHDL13_DWMP_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2531
ber01-VHDL13_DWMP_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2531
ber01-VHDL13_DWMP_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2581
ber01-VHDL13_DWMP_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:07 2575
ber01-VHDL13_DWMP_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2890
ber01-VHDL13_DWMP_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2895
ber01-VHDL13_DWMP_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 3108
ber01-VHDL13_DWMP_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2920
ber01-VHDL13_DWOG_040300-2507040300-dsw--0-ia5 04-Jul-2025 03:00:07 3560
ber01-VHDL13_DWOG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 3383
ber01-VHDL13_DWOG_041700-2507041700-dsw--0-ia5 04-Jul-2025 18:00:06 3098
ber01-VHDL13_DWOG_050300-2507050300-dsw--0-ia5 05-Jul-2025 03:00:14 3224
ber01-VHDL13_DWOG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 4012
ber01-VHDL13_DWOG_051700-2507051700-dsw--0-ia5 05-Jul-2025 18:00:02 3408
ber01-VHDL13_DWOH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:28:08 1970
ber01-VHDL13_DWOH_040400-2507040400-dsw--0-ia5 04-Jul-2025 04:58:07 1930
ber01-VHDL13_DWOH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:12 2057
ber01-VHDL13_DWOH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:12 1973
ber01-VHDL13_DWOH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:06 2194
ber01-VHDL13_DWOH_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:12 2180
ber01-VHDL13_DWOH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2586
ber01-VHDL13_DWOH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:11 2550
ber01-VHDL13_DWOI_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:28:12 1910
ber01-VHDL13_DWOI_040400-2507040400-dsw--0-ia5 04-Jul-2025 04:58:11 1887
ber01-VHDL13_DWOI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:28:06 2122
ber01-VHDL13_DWOI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:28:06 2085
ber01-VHDL13_DWOI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:28:11 2337
ber01-VHDL13_DWOI_050400-2507050400-dsw--0-ia5 05-Jul-2025 04:58:12 2355
ber01-VHDL13_DWOI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:28:10 2661
ber01-VHDL13_DWOI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:28:07 2538
ber01-VHDL13_DWON_040152-2507040152-dsw--0-ia5 04-Jul-2025 01:52:27 3395
ber01-VHDL13_DWON_040318-2507040318-dsw--0-ia5 04-Jul-2025 03:18:16 3395
ber01-VHDL13_DWON_040530-2507040530-dsw--0-ia5 04-Jul-2025 05:30:09 3794
ber01-VHDL13_DWON_040545-2507040545-dsw--0-ia5 04-Jul-2025 05:45:36 3700
ber01-VHDL13_DWON_040620-2507040620-dsw--0-ia5 04-Jul-2025 06:20:32 3629
ber01-VHDL13_DWON_040735-2507040735-dsw--0-ia5 04-Jul-2025 07:35:16 3449
ber01-VHDL13_DWON_041410-2507041410-dsw--0-ia5 04-Jul-2025 14:10:33 3631
ber01-VHDL13_DWON_041415-2507041415-dsw--0-ia5 04-Jul-2025 14:15:17 3625
ber01-VHDL13_DWON_041722-2507041722-dsw--0-ia5 04-Jul-2025 17:22:16 3108
ber01-VHDL13_DWON_050128-2507050128-dsw--0-ia5 05-Jul-2025 01:28:53 3035
ber01-VHDL13_DWON_050251-2507050251-dsw--0-ia5 05-Jul-2025 02:51:23 3035
ber01-VHDL13_DWON_050511-2507050511-dsw--0-ia5 05-Jul-2025 05:11:11 3595
ber01-VHDL13_DWON_050618-2507050618-dsw--0-ia5 05-Jul-2025 06:18:07 3651
ber01-VHDL13_DWON_050750-2507050750-dsw--0-ia5 05-Jul-2025 07:50:47 3786
ber01-VHDL13_DWON_051027-2507051027-dsw--0-ia5 05-Jul-2025 10:28:02 3786
ber01-VHDL13_DWON_051432-2507051432-dsw--0-ia5 05-Jul-2025 14:33:04 3542
ber01-VHDL13_DWON_051741-2507051741-dsw--0-ia5 05-Jul-2025 17:41:31 2995
ber01-VHDL13_DWON_060014-2507060014-dsw--0-ia5 06-Jul-2025 00:14:47 2955
ber01-VHDL13_DWPG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2032
ber01-VHDL13_DWPG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2027
ber01-VHDL13_DWPG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2026
ber01-VHDL13_DWPG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 1784
ber01-VHDL13_DWPG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2216
ber01-VHDL13_DWPG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2674
ber01-VHDL13_DWPG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2650
ber01-VHDL13_DWPG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2171
ber01-VHDL13_DWPH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2060
ber01-VHDL13_DWPH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2028
ber01-VHDL13_DWPH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 2028
ber01-VHDL13_DWPH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 2029
ber01-VHDL13_DWPH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2276
ber01-VHDL13_DWPH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2703
ber01-VHDL13_DWPH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2713
ber01-VHDL13_DWPH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:01 2219
ber01-VHDL13_DWSG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:30:01 2457
ber01-VHDL13_DWSG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2133
ber01-VHDL13_DWSG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1949
ber01-VHDL13_DWSG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:30:01 2229
ber01-VHDL13_DWSG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:30:01 2569
ber01-VHDL13_DWSG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2587
ber01-VHDL13_DWSG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:30:02 2945
ber01-VHDL13_DWSG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:30:10 2511
ber01-VHDL13_DWSN_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 1103
ber01-VHDL13_DWSN_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1102
ber01-VHDL13_DWSO_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 1110
ber01-VHDL13_DWSO_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1110
ber01-VHDL13_DWSP_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 1124
ber01-VHDL13_DWSP_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:30:02 1124
ber01-VHDL17_DWOG_041200-2507041200-dsw--0-ia5 04-Jul-2025 11:04:37 2856
ber01-VHDL17_DWOG_051200-2507051200-dsw--0-ia5 05-Jul-2025 11:01:42 2503
swis2-VHDL20_DWEG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2102
swis2-VHDL20_DWEG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:02 2138
swis2-VHDL20_DWEG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2236
swis2-VHDL20_DWEG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2158
swis2-VHDL20_DWEG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2326
swis2-VHDL20_DWEG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:01 2388
swis2-VHDL20_DWEG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2765
swis2-VHDL20_DWEG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2735
swis2-VHDL20_DWEH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:25 2288
swis2-VHDL20_DWEH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:12 2256
swis2-VHDL20_DWEH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2394
swis2-VHDL20_DWEH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:11 2409
swis2-VHDL20_DWEH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:24 2555
swis2-VHDL20_DWEH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:13 2527
swis2-VHDL20_DWEH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:11 2824
swis2-VHDL20_DWEH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:12 3033
swis2-VHDL20_DWEI_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2043
swis2-VHDL20_DWEI_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:12 2072
swis2-VHDL20_DWEI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2301
swis2-VHDL20_DWEI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2270
swis2-VHDL20_DWEI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2470
swis2-VHDL20_DWEI_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:13 2540
swis2-VHDL20_DWEI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2840
swis2-VHDL20_DWEI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2723
swis2-VHDL20_DWHG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2552
swis2-VHDL20_DWHG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:11 2552
swis2-VHDL20_DWHG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 3166
swis2-VHDL20_DWHG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2911
swis2-VHDL20_DWHG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 3253
swis2-VHDL20_DWHG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3253
swis2-VHDL20_DWHG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3514
swis2-VHDL20_DWHG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2842
swis2-VHDL20_DWHH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2809
swis2-VHDL20_DWHH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:11 2807
swis2-VHDL20_DWHH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 3217
swis2-VHDL20_DWHH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2788
swis2-VHDL20_DWHH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 3267
swis2-VHDL20_DWHH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:11 3270
swis2-VHDL20_DWHH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3491
swis2-VHDL20_DWHH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2888
swis2-VHDL20_DWLG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2090
swis2-VHDL20_DWLG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:21 2167
swis2-VHDL20_DWLG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2167
swis2-VHDL20_DWLG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2041
swis2-VHDL20_DWLG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2286
swis2-VHDL20_DWLG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:26 2521
swis2-VHDL20_DWLG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2465
swis2-VHDL20_DWLG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2283
swis2-VHDL20_DWLH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2054
swis2-VHDL20_DWLH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:21 2151
swis2-VHDL20_DWLH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2224
swis2-VHDL20_DWLH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2196
swis2-VHDL20_DWLH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2570
swis2-VHDL20_DWLH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:26 2943
swis2-VHDL20_DWLH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2973
swis2-VHDL20_DWLH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2522
swis2-VHDL20_DWLI_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 1992
swis2-VHDL20_DWLI_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:21 2020
swis2-VHDL20_DWLI_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2019
swis2-VHDL20_DWLI_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 1914
swis2-VHDL20_DWLI_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2198
swis2-VHDL20_DWLI_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:26 2408
swis2-VHDL20_DWLI_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2416
swis2-VHDL20_DWLI_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2202
swis2-VHDL20_DWMG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2717
swis2-VHDL20_DWMG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2756
swis2-VHDL20_DWMG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2779
swis2-VHDL20_DWMG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2671
swis2-VHDL20_DWMG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2766
swis2-VHDL20_DWMG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2711
swis2-VHDL20_DWMG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2974
swis2-VHDL20_DWMG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2860
swis2-VHDL20_DWMO_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2356
swis2-VHDL20_DWMO_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2356
swis2-VHDL20_DWMO_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2313
swis2-VHDL20_DWMO_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2271
swis2-VHDL20_DWMO_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2541
swis2-VHDL20_DWMO_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2548
swis2-VHDL20_DWMO_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2785
swis2-VHDL20_DWMO_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 2421
swis2-VHDL20_DWMP_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2743
swis2-VHDL20_DWMP_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2743
swis2-VHDL20_DWMP_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2793
swis2-VHDL20_DWMP_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2785
swis2-VHDL20_DWMP_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 3102
swis2-VHDL20_DWMP_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 3107
swis2-VHDL20_DWMP_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3320
swis2-VHDL20_DWMP_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:06 3124
swis2-VHDL20_DWPG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2229
swis2-VHDL20_DWPG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2222
swis2-VHDL20_DWPG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2223
swis2-VHDL20_DWPG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 1981
swis2-VHDL20_DWPG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2413
swis2-VHDL20_DWPG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2869
swis2-VHDL20_DWPG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2847
swis2-VHDL20_DWPG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2368
swis2-VHDL20_DWPH_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2257
swis2-VHDL20_DWPH_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:00:07 2225
swis2-VHDL20_DWPH_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2225
swis2-VHDL20_DWPH_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2226
swis2-VHDL20_DWPH_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2473
swis2-VHDL20_DWPH_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:00:07 2900
swis2-VHDL20_DWPH_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 2910
swis2-VHDL20_DWPH_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2416
swis2-VHDL20_DWSG_040200-2507040200-dsw--0-ia5 04-Jul-2025 02:45:05 2691
swis2-VHDL20_DWSG_040400-2507040400-dsw--0-ia5 04-Jul-2025 05:15:02 2364
swis2-VHDL20_DWSG_040800-2507040800-dsw--0-ia5 04-Jul-2025 08:45:06 2179
swis2-VHDL20_DWSG_041300-2507041300-dsw--0-ia5 04-Jul-2025 13:45:02 2685
swis2-VHDL20_DWSG_041800-2507041800-dsw--0-ia5 04-Jul-2025 18:45:02 2461
swis2-VHDL20_DWSG_050200-2507050200-dsw--0-ia5 05-Jul-2025 02:45:02 2803
swis2-VHDL20_DWSG_050400-2507050400-dsw--0-ia5 05-Jul-2025 05:15:01 2818
swis2-VHDL20_DWSG_050800-2507050800-dsw--0-ia5 05-Jul-2025 08:45:09 3175
swis2-VHDL20_DWSG_051300-2507051300-dsw--0-ia5 05-Jul-2025 13:45:01 3020
swis2-VHDL20_DWSG_051800-2507051800-dsw--0-ia5 05-Jul-2025 18:45:02 2743
wst04-VHDL20_DWEG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 260061
wst04-VHDL20_DWEG_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:15:08 259843
wst04-VHDL20_DWEG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:10 259897
wst04-VHDL20_DWEG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:17 258302
wst04-VHDL20_DWEG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:24 258403
wst04-VHDL20_DWEG_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:15:13 259497
wst04-VHDL20_DWEG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:17 260621
wst04-VHDL20_DWEG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:17 259957
wst04-VHDL20_DWEH_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 257531
wst04-VHDL20_DWEH_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:15:08 257067
wst04-VHDL20_DWEH_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:10 257254
wst04-VHDL20_DWEH_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:17 260132
wst04-VHDL20_DWEH_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:24 260717
wst04-VHDL20_DWEH_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:15:07 260777
wst04-VHDL20_DWEH_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:11 262118
wst04-VHDL20_DWEH_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:17 257797
wst04-VHDL20_DWEI_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 358737
wst04-VHDL20_DWEI_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:15:12 357539
wst04-VHDL20_DWEI_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:10 357701
wst04-VHDL20_DWEI_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:17 355784
wst04-VHDL20_DWEI_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:24 356782
wst04-VHDL20_DWEI_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:15:13 356944
wst04-VHDL20_DWEI_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:17 358062
wst04-VHDL20_DWEI_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:17 361667
wst04-VHDL20_DWHG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 362874
wst04-VHDL20_DWHG_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:07 362938
wst04-VHDL20_DWHG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:13 363525
wst04-VHDL20_DWHG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:22 362081
wst04-VHDL20_DWHG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:11 362169
wst04-VHDL20_DWHG_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:07 362246
wst04-VHDL20_DWHG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:17 363504
wst04-VHDL20_DWHG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:17 364842
wst04-VHDL20_DWHH_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 353276
wst04-VHDL20_DWHH_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:07 353305
wst04-VHDL20_DWHH_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:16 353839
wst04-VHDL20_DWHH_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:17 352244
wst04-VHDL20_DWHH_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:11 353537
wst04-VHDL20_DWHH_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:07 353585
wst04-VHDL20_DWHH_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:22 354057
wst04-VHDL20_DWHH_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:21 351428
wst04-VHDL20_DWLG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:40:26 357915
wst04-VHDL20_DWLG_040400-2507040400-omedes--0.pdf 04-Jul-2025 04:59:36 359118
wst04-VHDL20_DWLG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:40:26 359131
wst04-VHDL20_DWLG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:40:26 347030
wst04-VHDL20_DWLG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:40:33 347297
wst04-VHDL20_DWLG_050400-2507050400-omedes--0.pdf 05-Jul-2025 04:59:37 347955
wst04-VHDL20_DWLG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:40:26 348465
wst04-VHDL20_DWLG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:40:26 352923
wst04-VHDL20_DWLH_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:40:18 356725
wst04-VHDL20_DWLH_040400-2507040400-omedes--0.pdf 04-Jul-2025 04:59:36 357901
wst04-VHDL20_DWLH_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:40:16 357946
wst04-VHDL20_DWLH_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:40:17 351076
wst04-VHDL20_DWLH_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:40:33 350981
wst04-VHDL20_DWLH_050400-2507050400-omedes--0.pdf 05-Jul-2025 04:59:37 351506
wst04-VHDL20_DWLH_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:40:17 352050
wst04-VHDL20_DWLH_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:40:16 353956
wst04-VHDL20_DWLI_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:40:36 357400
wst04-VHDL20_DWLI_040400-2507040400-omedes--0.pdf 04-Jul-2025 04:59:36 358582
wst04-VHDL20_DWLI_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:40:37 358604
wst04-VHDL20_DWLI_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:40:36 347493
wst04-VHDL20_DWLI_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:40:36 347381
wst04-VHDL20_DWLI_050400-2507050400-omedes--0.pdf 05-Jul-2025 04:59:37 348431
wst04-VHDL20_DWLI_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:40:36 348956
wst04-VHDL20_DWLI_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:40:36 357017
wst04-VHDL20_DWMG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 591072
wst04-VHDL20_DWMG_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:11 590579
wst04-VHDL20_DWMG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:16 589473
wst04-VHDL20_DWMG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:11 564803
wst04-VHDL20_DWMG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:11 566056
wst04-VHDL20_DWMG_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:11 565416
wst04-VHDL20_DWMG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:11 565437
wst04-VHDL20_DWMG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:12 569902
wst04-VHDL20_DWMO_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:05 470089
wst04-VHDL20_DWMO_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:11 470492
wst04-VHDL20_DWMO_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:16 470046
wst04-VHDL20_DWMO_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:09 451556
wst04-VHDL20_DWMO_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:05 452577
wst04-VHDL20_DWMO_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:11 453008
wst04-VHDL20_DWMO_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:11 452342
wst04-VHDL20_DWMO_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:06 454982
wst04-VHDL20_DWMP_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 601380
wst04-VHDL20_DWMP_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:11 601696
wst04-VHDL20_DWMP_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:24 601560
wst04-VHDL20_DWMP_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:11 580072
wst04-VHDL20_DWMP_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:11 580971
wst04-VHDL20_DWMP_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:11 581249
wst04-VHDL20_DWMP_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:17 580850
wst04-VHDL20_DWMP_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:12 584196
wst04-VHDL20_DWPG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 362006
wst04-VHDL20_DWPG_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:07 362589
wst04-VHDL20_DWPG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:06 407188
wst04-VHDL20_DWPG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:06 352682
wst04-VHDL20_DWPG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:05 353638
wst04-VHDL20_DWPG_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:07 353763
wst04-VHDL20_DWPG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:09 398304
wst04-VHDL20_DWPG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:06 358824
wst04-VHDL20_DWPH_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 260249
wst04-VHDL20_DWPH_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:00:07 260427
wst04-VHDL20_DWPH_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:06 305008
wst04-VHDL20_DWPH_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:06 307063
wst04-VHDL20_DWPH_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:05 263673
wst04-VHDL20_DWPH_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:00:07 263947
wst04-VHDL20_DWPH_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:09 308188
wst04-VHDL20_DWPH_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:06 305536
wst04-VHDL20_DWSG_040200-2507040200-omedes--0.pdf 04-Jul-2025 02:45:25 367674
wst04-VHDL20_DWSG_040400-2507040400-omedes--0.pdf 04-Jul-2025 05:15:06 366909
wst04-VHDL20_DWSG_040800-2507040800-omedes--0.pdf 04-Jul-2025 08:45:16 366918
wst04-VHDL20_DWSG_041300-2507041300-omedes--0.pdf 04-Jul-2025 13:45:06 363298
wst04-VHDL20_DWSG_041800-2507041800-omedes--0.pdf 04-Jul-2025 18:45:11 362525
wst04-VHDL20_DWSG_050200-2507050200-omedes--0.pdf 05-Jul-2025 02:45:24 362704
wst04-VHDL20_DWSG_050400-2507050400-omedes--0.pdf 05-Jul-2025 05:15:07 362835
wst04-VHDL20_DWSG_050800-2507050800-omedes--0.pdf 05-Jul-2025 08:45:09 362795
wst04-VHDL20_DWSG_051300-2507051300-omedes--0.pdf 05-Jul-2025 13:45:06 362385
wst04-VHDL20_DWSG_051800-2507051800-omedes--0.pdf 05-Jul-2025 18:45:12 362096